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it83xx/adc: adc control pin order changes for it83202Bx 

Add configuration for changing adc control pin order
on chip it83202Bx.

BUG=none
BRANCH=none
TEST=ADC16 of PD port2 can read correct Vbus value.

Change-Id: I9a7f81bf3cb1ac74a5f07ce817d03f5ab0569d17
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009539
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
This commit is contained in:
Ruibin Chang 2020-01-20 18:03:54 +08:00 committed by Commit Bot
parent adf6054e8e
commit 491ee94be1
2 changed files with 19 additions and 0 deletions
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11
chip/it83xx/adc.c
View File

@ -40,6 +40,16 @@ const struct adc_ctrl_t adc_ctrl_regs[] = {
&IT83XX_GPIO_GPCRI6},
{&IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL,
&IT83XX_GPIO_GPCRI7},
#ifdef IT83XX_CHIP_ADC_PIN_ORDER_CHANGE
{&IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL,
&IT83XX_GPIO_GPCRL1},
{&IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL,
&IT83XX_GPIO_GPCRL2},
{&IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL,
&IT83XX_GPIO_GPCRL3},
{&IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL,
&IT83XX_GPIO_GPCRL0},
#else
{&IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL,
&IT83XX_GPIO_GPCRL0},
{&IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL,
@ -48,6 +58,7 @@ const struct adc_ctrl_t adc_ctrl_regs[] = {
&IT83XX_GPIO_GPCRL2},
{&IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL,
&IT83XX_GPIO_GPCRL3},
#endif
};
BUILD_ASSERT(ARRAY_SIZE(adc_ctrl_regs) == CHIP_ADC_COUNT);

8
chip/it83xx/config_chip_it8xxx2.h
View File

@ -33,6 +33,14 @@
#if defined(CHIP_VARIANT_IT83202BX)
/* TODO(b/133460224): enable properly chip config option. */
#define CONFIG_FLASH_SIZE 0x00080000
/*
* ADC control pin order change:
* ADC13 control pin GPL0 GPL1
* ADC14 control pin GPL1 change to GPL2
* ADC15 control pin GPL2 ---------> GPL3
* ADC16 control pin GPL3 GPL0
*/
#define IT83XX_CHIP_ADC_PIN_ORDER_CHANGE
/* Embedded flash is KGD */
#define IT83XX_CHIP_FLASH_IS_KGD
/* Don't let internal flash go into deep power down mode. */