coreboot-mirror
/
chrome-ec
mirror of https://review.coreboot.org/chrome-ec.git
1
0
Fork 0
Code Issues Releases Wiki Activity

power: Use a general name for PMIC_RESIN_L signal on sc7180 and sdm845 

Don't bound to the PMIC part name.

BRANCH=None
BUG=b:148113568
TEST=Built the affected images.

Change-Id: I3c2e8851294b957aa133c6a8528de3960a3e468c
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2303815
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
This commit is contained in:
Wai-Hong Tam 2020-07-16 18:01:39 -07:00 committed by Commit Bot
parent cedd3fba44
commit 395e6112a9
6 changed files with 29 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
board/cheza/board.h
View File

@ -173,6 +173,9 @@
#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0
#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0
/* GPIO alias */
#define GPIO_PMIC_RESIN_L GPIO_PM845_RESIN_L
#ifndef __ASSEMBLER__
#include "gpio_signal.h"

3
board/lazor/board.h
View File

@ -61,6 +61,9 @@
#define CONFIG_GMR_TABLET_MODE
#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
/* GPIO alias */
#define GPIO_PMIC_RESIN_L GPIO_PM845_RESIN_L
#ifndef __ASSEMBLER__
#include "gpio_signal.h"

3
board/pompom/board.h
View File

@ -55,8 +55,9 @@
#define CONFIG_GMR_TABLET_MODE
#define GMR_TABLET_MODE_GPIO_L GPIO_LID_360_L
/* GPIO alias */
#define GPIO_EC_RST_ODL GPIO_EC_RST_ODL_GPIO02
#define GPIO_PM845_RESIN_L GPIO_PM7180_RESIN_D_L
#define GPIO_PMIC_RESIN_L GPIO_PM7180_RESIN_D_L
#ifndef __ASSEMBLER__

2
board/trogdor/gpio.inc
View File

@ -57,7 +57,7 @@ GPIO(EC_ENTERING_RW, PIN(E, 1), GPIO_OUT_LOW) /* Indicate when EC is en
GPIO(EC_BATT_PRES_ODL, PIN(E, 5), GPIO_INPUT) /* Battery Present */
/* PMIC/AP 1.8V */
GPIO(PM845_RESIN_L, PIN(3, 2), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* PMIC reset trigger */
GPIO(PMIC_RESIN_L, PIN(3, 2), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* PMIC reset trigger */
GPIO(PMIC_KPD_PWR_ODL, PIN(D, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* PMIC power button */
GPIO(EC_INT_L, PIN(A, 2), GPIO_ODR_HIGH) /* Interrupt line between AP and EC */

20
power/sc7180.c
View File

@ -69,7 +69,7 @@
/* Wait for polling the AP on signal */
#define PMIC_POWER_AP_WAIT (1 * MSEC)
/* The length of an issued low pulse to the PM845_RESIN_L signal */
/* The length of an issued low pulse to the PMIC_RESIN_L signal */
#define PMIC_RESIN_PULSE_LENGTH (20 * MSEC)
/* The timeout of the check if the system can boot AP */
@ -412,14 +412,14 @@ static int set_pmic_pwron(int enable)
* 3. Release PMIC_KPD_PWR_ODL
*
* Power-off sequence:
* 1. Hold down PMIC_KPD_PWR_ODL and PM845_RESIN_L, which is a power-off
* 1. Hold down PMIC_KPD_PWR_ODL and PMIC_RESIN_L, which is a power-off
* trigger (requiring reprogramming PMIC registers to make
* PMIC_KPD_PWR_ODL + PM845_RESIN_L as a shutdown trigger)
* PMIC_KPD_PWR_ODL + PMIC_RESIN_L as a shutdown trigger)
* 2. PMIC stops supplying power to POWER_GOOD (requiring
* reprogramming PMIC to set the stage-1 and stage-2 reset timers to
* 0 such that the pull down happens just after the deboucing time
* of the trigger, like 2ms)
* 3. Release PMIC_KPD_PWR_ODL and PM845_RESIN_L
* 3. Release PMIC_KPD_PWR_ODL and PMIC_RESIN_L
*
* If the above PMIC registers not programmed or programmed wrong, it
* falls back to the next functions, which cuts off the system power.
@ -427,11 +427,11 @@ static int set_pmic_pwron(int enable)
gpio_set_level(GPIO_PMIC_KPD_PWR_ODL, 0);
if (!enable)
gpio_set_level(GPIO_PM845_RESIN_L, 0);
gpio_set_level(GPIO_PMIC_RESIN_L, 0);
ret = wait_pmic_pwron(enable, PMIC_POWER_AP_RESPONSE_TIMEOUT);
gpio_set_level(GPIO_PMIC_KPD_PWR_ODL, 1);
if (!enable)
gpio_set_level(GPIO_PM845_RESIN_L, 1);
gpio_set_level(GPIO_PMIC_RESIN_L, 1);
return ret;
}
@ -710,9 +710,9 @@ void chipset_reset(enum chipset_reset_reason reason)
/*
* Warm reset sequence:
* 1. Issue a low pulse to PM845_RESIN_L, which triggers PMIC
* 1. Issue a low pulse to PMIC_RESIN_L, which triggers PMIC
* to do a warm reset (requiring reprogramming PMIC registers
* to make PM845_RESIN_L as a warm reset trigger).
* to make PMIC_RESIN_L as a warm reset trigger).
* 2. PMIC then issues a low pulse to AP_RST_L to reset AP.
* EC monitors the signal to see any low pulse.
* 2.1. If a low pulse found, done.
@ -721,9 +721,9 @@ void chipset_reset(enum chipset_reset_reason reason)
* to initiate a cold reset power sequence.
*/
gpio_set_level(GPIO_PM845_RESIN_L, 0);
gpio_set_level(GPIO_PMIC_RESIN_L, 0);
usleep(PMIC_RESIN_PULSE_LENGTH);
gpio_set_level(GPIO_PM845_RESIN_L, 1);
gpio_set_level(GPIO_PMIC_RESIN_L, 1);
rv = power_wait_signals_timeout(IN_AP_RST_ASSERTED,
PMIC_POWER_AP_RESPONSE_TIMEOUT);

20
power/sdm845.c
View File

@ -69,7 +69,7 @@
/* Wait for polling the AP on signal */
#define PMIC_POWER_AP_WAIT (1 * MSEC)
/* The length of an issued low pulse to the PM845_RESIN_L signal */
/* The length of an issued low pulse to the PMIC_RESIN_L signal */
#define PMIC_RESIN_PULSE_LENGTH (20 * MSEC)
/* The timeout of the check if the system can boot AP */
@ -371,14 +371,14 @@ static void set_pmic_pwron(int enable)
* 3. Release PMIC_KPD_PWR_ODL
*
* Power-off sequence:
* 1. Hold down PMIC_KPD_PWR_ODL and PM845_RESIN_L, which is a power-off
* 1. Hold down PMIC_KPD_PWR_ODL and PMIC_RESIN_L, which is a power-off
* trigger (requiring reprogramming PMIC registers to make
* PMIC_KPD_PWR_ODL + PM845_RESIN_L as a shutdown trigger)
* PMIC_KPD_PWR_ODL + PMIC_RESIN_L as a shutdown trigger)
* 2. PM845 stops supplying power to POWER_GOOD (requiring
* reprogramming PMIC to set the stage-1 and stage-2 reset timers to
* 0 such that the pull down happens just after the deboucing time
* of the trigger, like 2ms)
* 3. Release PMIC_KPD_PWR_ODL and PM845_RESIN_L
* 3. Release PMIC_KPD_PWR_ODL and PMIC_RESIN_L
*
* If the above PMIC registers not programmed or programmed wrong, it
* falls back to the next functions, which cuts off the system power.
@ -386,11 +386,11 @@ static void set_pmic_pwron(int enable)
gpio_set_level(GPIO_PMIC_KPD_PWR_ODL, 0);
if (!enable)
gpio_set_level(GPIO_PM845_RESIN_L, 0);
gpio_set_level(GPIO_PMIC_RESIN_L, 0);
wait_pmic_pwron(enable, PMIC_POWER_AP_RESPONSE_TIMEOUT);
gpio_set_level(GPIO_PMIC_KPD_PWR_ODL, 1);
if (!enable)
gpio_set_level(GPIO_PM845_RESIN_L, 1);
gpio_set_level(GPIO_PMIC_RESIN_L, 1);
}
enum power_state power_chipset_init(void)
@ -696,9 +696,9 @@ void chipset_reset(enum chipset_reset_reason reason)
/*
* Warm reset sequence:
* 1. Issue a low pulse to PM845_RESIN_L, which triggers PMIC
* 1. Issue a low pulse to PMIC_RESIN_L, which triggers PMIC
* to do a warm reset (requiring reprogramming PMIC registers
* to make PM845_RESIN_L as a warm reset trigger).
* to make PMIC_RESIN_L as a warm reset trigger).
* 2. PMIC then issues a low pulse to AP_RST_L to reset AP.
* EC monitors the signal to see any low pulse.
* 2.1. If a low pulse found, done.
@ -707,9 +707,9 @@ void chipset_reset(enum chipset_reset_reason reason)
* to initiate a cold reset power sequence.
*/
gpio_set_level(GPIO_PM845_RESIN_L, 0);
gpio_set_level(GPIO_PMIC_RESIN_L, 0);
usleep(PMIC_RESIN_PULSE_LENGTH);
gpio_set_level(GPIO_PM845_RESIN_L, 1);
gpio_set_level(GPIO_PMIC_RESIN_L, 1);
rv = power_wait_signals_timeout(IN_AP_RST_ASSERTED,
PMIC_POWER_AP_RESPONSE_TIMEOUT);