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Code Issues Releases Wiki Activity

util: ecst: add support for chip variant npcx9 

Allow ecst tool to compose the correct firmware header for npcx993f &
npcx996f.

BRANCH=none
BUG=b:165777478
TEST=pass "make buildall"
TEST=with the related CLs, change CHIP_VARIANT to npcx996f in
board/npcx9_evb/build.mk; "BOARD=npcx9_evb make";
check the image can be built and the image header is correct.

Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: Ia48b19854850a642a2f4ed97ca45230f46fbd65c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2393403
Reviewed-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
This commit is contained in:
Wealian Liao 2020-09-04 13:25:30 +08:00 committed by Commit Bot
parent d500d5fc51
commit 176915de59
2 changed files with 17 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
util/ecst.c
View File

@ -44,13 +44,15 @@ struct chip_info chip_info[] = {
[NPCX7M5] = {NPCX7M5X_RAM_ADDR, NPCX7M5X_RAM_SIZE},
[NPCX7M6] = {NPCX7M6X_RAM_ADDR, NPCX7M6X_RAM_SIZE},
[NPCX7M7] = {NPCX7M7X_RAM_ADDR, NPCX7M7X_RAM_SIZE},
[NPCX9M3] = {NPCX9M3X_RAM_ADDR, NPCX9M3X_RAM_SIZE},
[NPCX9M6] = {NPCX9M6X_RAM_ADDR, NPCX9M6X_RAM_SIZE},
};
BUILD_ASSERT(ARRAY_SIZE(chip_info) == NPCX_CHIP_RAM_VAR_NONE);
/* Support chips name strings */
const char *supported_chips = "npcx5m5g, npcx5m6g, npcx7m5g, npcx7m6g, "
"npcx7m6f, npcx7m6fb, npcx7m6fc, npcx7m7fc, npcx7m7wb, "
"or npcx7m7wc";
"npcx7m7wc, npcx9m3f or npcx9m6f";
static unsigned int calc_api_csum_bin(void);
static unsigned int initialize_crc_32(void);
@ -105,7 +107,11 @@ static int splice_into_path(char *result, const char *path, int resultsz,
*/
static enum npcx_chip_ram_variant chip_to_ram_var(const char *chip_name)
{
if (str_cmp_no_case(chip_name, "npcx7m7wb") == 0)
if (str_cmp_no_case(chip_name, "npcx9m6f") == 0)
return NPCX9M6;
else if (str_cmp_no_case(chip_name, "npcx9m3f") == 0)
return NPCX9M3;
else if (str_cmp_no_case(chip_name, "npcx7m7wb") == 0)
return NPCX7M7;
else if (str_cmp_no_case(chip_name, "npcx7m7wc") == 0)
return NPCX7M7;

9
util/ecst.h
View File

@ -167,21 +167,30 @@ enum npcx_chip_ram_variant {
NPCX7M5 = 2,
NPCX7M6 = 3,
NPCX7M7 = 4,
NPCX9M3 = 5,
NPCX9M6 = 6,
NPCX_CHIP_RAM_VAR_NONE
};
#define DEFAULT_CHIP NPCX5M5G
/* NPCX5 */
#define NPCX5M5G_RAM_ADDR 0x100A8000
#define NPCX5M5G_RAM_SIZE 0x20000
#define NPCX5M6G_RAM_ADDR 0x10088000
#define NPCX5M6G_RAM_SIZE 0x40000
/* NPCX7 */
#define NPCX7M5X_RAM_ADDR 0x100A8000
#define NPCX7M5X_RAM_SIZE 0x20000
#define NPCX7M6X_RAM_ADDR 0x10090000
#define NPCX7M6X_RAM_SIZE 0x40000
#define NPCX7M7X_RAM_ADDR 0x10070000
#define NPCX7M7X_RAM_SIZE 0x60000
/* NPCX9 */
#define NPCX9M3X_RAM_ADDR 0x10080000
#define NPCX9M3X_RAM_SIZE 0x50000
#define NPCX9M6X_RAM_ADDR 0x10090000
#define NPCX9M6X_RAM_SIZE 0x40000
/*---------------------------------------------------------------------------
Typedefs