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cleanup: fix all the header guards 

This unifies all the EC header files to use __CROS_EC_FILENAME_H
as the include guard. Well, except for test/ util/ and extra/
which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively.

BUG=chromium:496895
BRANCH=none
TEST=make buildall -j

Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029
Reviewed-on: https://chromium-review.googlesource.com/278121
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit is contained in:
Bill Richardson 2015-06-16 21:51:55 -07:00 committed by ChromeOS Commit Bot
parent 19cd951027
commit 104f811e67
157 changed files with 462 additions and 462 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
board/auron/board.h
View File

@ -5,8 +5,8 @@
/* Configuration for Auron mainboard */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
#define CONFIG_BACKLIGHT_LID
@ -113,4 +113,4 @@ int board_discharge_on_ac(int enable);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/bds/board.h
View File

@ -5,8 +5,8 @@
/* Stellaris EKB-LM4F-EAC board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */
@ -52,4 +52,4 @@ enum pwm_channel {
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/big/board.h
View File

@ -5,8 +5,8 @@
/* Big board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
#define CONFIG_AP_HANG_DETECT
@ -75,4 +75,4 @@ int board_discharge_on_ac(int enable);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/cr50/board.h
View File

@ -3,8 +3,8 @@
* found in the LICENSE file.
*/
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Features that we don't want just yet */
#undef CONFIG_CMD_LID_ANGLE
@ -79,4 +79,4 @@ enum usb_strings {
#undef CONFIG_UART_TX_BUF_SIZE
#define CONFIG_UART_TX_BUF_SIZE 4096
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/cyan/board.h
View File

@ -5,8 +5,8 @@
/* Cyan board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */
@ -110,4 +110,4 @@ enum temp_sensor_id {
int board_discharge_on_ac(int enable);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/dingdong/board.h
View File

@ -5,8 +5,8 @@
/* Dingdong dongle configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
@ -103,4 +103,4 @@ enum usb_strings {
#define USB_EP_CONTROL 0
#define USB_EP_COUNT 1
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/dingdong/usb_pd_config.h
View File

@ -5,8 +5,8 @@
/* USB Power delivery board configuration */
#ifndef __USB_PD_CONFIG_H
#define __USB_PD_CONFIG_H
#ifndef __CROS_EC_USB_PD_CONFIG_H
#define __CROS_EC_USB_PD_CONFIG_H
/* Timer selection for baseband PD communication */
#define TIM_CLOCK_PD_TX_C0 17
@ -125,4 +125,4 @@ static inline int pd_adc_read(int port, int cc)
return (cc == 0) ? adc_read_channel(ADC_CH_CC1_PD) : 0;
}
#endif /* __USB_PD_CONFIG_H */
#endif /* __CROS_EC_USB_PD_CONFIG_H */

6
board/discovery-stm32f072/board.h
View File

@ -5,8 +5,8 @@
/* STM32F072-discovery board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
@ -84,4 +84,4 @@ enum usb_strings {
};
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/discovery/board.h
View File

@ -5,8 +5,8 @@
/* STM32L-discovery board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
#undef CONFIG_WATCHDOG_HELP
@ -28,4 +28,4 @@
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/glados/board.h
View File

@ -5,8 +5,8 @@
/* Glados board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
#define CONFIG_ADC
@ -131,4 +131,4 @@ void board_reset_pd_mcu(void);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/glados_pd/board.h
View File

@ -5,8 +5,8 @@
/* gladoes_pd board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/*
* The flash size is only 32kB.
@ -93,4 +93,4 @@ enum adc_channel {
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/glados_pd/usb_pd_config.h
View File

@ -10,8 +10,8 @@
/* USB Power delivery board configuration */
#ifndef __USB_PD_CONFIG_H
#define __USB_PD_CONFIG_H
#ifndef __CROS_EC_USB_PD_CONFIG_H
#define __CROS_EC_USB_PD_CONFIG_H
/* Timer selection for baseband PD communication */
#define TIM_CLOCK_PD_TX_C0 16
@ -323,5 +323,5 @@ static inline void pd_set_vconn(int port, int polarity, int enable)
}
}
#endif /* __USB_PD_CONFIG_H */
#endif /* __CROS_EC_USB_PD_CONFIG_H */

6
board/glower/board.h
View File

@ -5,8 +5,8 @@
/* Glower board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
/* #define CONFIG_BACKLIGHT_LID */
@ -112,4 +112,4 @@ int board_discharge_on_ac(int enable);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/hadoken/board.h
View File

@ -5,8 +5,8 @@
/* Hadoken board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
#ifndef __ASSEMBLER__
@ -56,5 +56,5 @@
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/hoho/board.h
View File

@ -5,8 +5,8 @@
/* Hoho dongle configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
@ -114,4 +114,4 @@ enum usb_strings {
#define USB_EP_CONTROL 0
#define USB_EP_COUNT 1
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/hoho/usb_pd_config.h
View File

@ -5,8 +5,8 @@
/* USB Power delivery board configuration */
#ifndef __USB_PD_CONFIG_H
#define __USB_PD_CONFIG_H
#ifndef __CROS_EC_USB_PD_CONFIG_H
#define __CROS_EC_USB_PD_CONFIG_H
/* Timer selection for baseband PD communication */
#define TIM_CLOCK_PD_TX_C0 17
@ -125,4 +125,4 @@ static inline int pd_adc_read(int port, int cc)
return (cc == 0) ? adc_read_channel(ADC_CH_CC1_PD) : 0;
}
#endif /* __USB_PD_CONFIG_H */
#endif /* __CROS_EC_USB_PD_CONFIG_H */

6
board/honeybuns/board.h
View File

@ -5,8 +5,8 @@
/* Honeybuns board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
@ -109,4 +109,4 @@ enum usb_strings {
#define USB_EP_CONTROL 0
#define USB_EP_COUNT 1
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/honeybuns/usb_pd_config.h
View File

@ -5,8 +5,8 @@
/* USB Power delivery board configuration */
#ifndef __USB_PD_CONFIG_H
#define __USB_PD_CONFIG_H
#ifndef __CROS_EC_USB_PD_CONFIG_H
#define __CROS_EC_USB_PD_CONFIG_H
/* Timer selection for baseband PD communication */
#define TIM_CLOCK_PD_TX_C0 17
@ -138,4 +138,4 @@ static inline void pd_set_vconn(int port, int polarity, int enable)
}
#endif /* __USB_PD_CONFIG_H */
#endif /* __CROS_EC_USB_PD_CONFIG_H */

6
board/host/board.h
View File

@ -5,8 +5,8 @@
/* Emulator board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
#define CONFIG_EXTPOWER_GPIO
@ -72,4 +72,4 @@ extern const int supplier_priority[];
#define PD_MAX_CURRENT_MA 3000
#define PD_MAX_VOLTAGE_MV 20000
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/host/usb_pd_config.h
View File

@ -5,8 +5,8 @@
/* USB Power delivery board configuration */
#ifndef __USB_PD_CONFIG_H
#define __USB_PD_CONFIG_H
#ifndef __CROS_EC_USB_PD_CONFIG_H
#define __CROS_EC_USB_PD_CONFIG_H
/* Use software CRC */
#define CONFIG_SW_CRC
@ -21,4 +21,4 @@ void pd_config_init(int port, uint8_t power_role);
int pd_adc_read(int port, int cc);
#endif /* __USB_PD_CONFIG_H */
#endif /* __CROS_EC_USB_PD_CONFIG_H */

6
board/it8380dev/board.h
View File

@ -5,8 +5,8 @@
/* IT8380 development board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
#define CONFIG_POWER_BUTTON
@ -84,4 +84,4 @@ enum ec2i_setting {
};
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/kunimitsu/board.h
View File

@ -5,8 +5,8 @@
/* Skylake Chrome Reference Design board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */
@ -122,4 +122,4 @@ int board_discharge_on_ac(int enable);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/llama/board.h
View File

@ -5,8 +5,8 @@
/* llama board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
#define CONFIG_CHIPSET_MEDIATEK
/* Add for AC adaptor, charger, battery */
@ -98,4 +98,4 @@ int board_discharge_on_ac(int enable);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/mec1322_evb/board.h
View File

@ -5,8 +5,8 @@
/* MEC1322 eval board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */
@ -42,4 +42,4 @@ enum adc_channel {
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/npcx_evb/board.h
View File

@ -5,8 +5,8 @@
/* Configuration for Nuvoton M4 EB */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Support Code RAM architecture (Run code in RAM) */
#define CONFIG_CODERAM_ARCH
@ -85,4 +85,4 @@ enum mft_channel {
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/oak/board.h
View File

@ -5,8 +5,8 @@
/* oak board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Board revision */
#undef CONFIG_BOARD_OAK_REV_1
@ -175,4 +175,4 @@ void board_typec_dp_set(int port, int level);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/oak_pd/board.h
View File

@ -5,8 +5,8 @@
/* oak_pd board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
#undef CONFIG_BOARD_OAK_REV_1
#define CONFIG_BOARD_OAK_REV_2
@ -105,4 +105,4 @@ enum adc_channel {
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/oak_pd/usb_pd_config.h
View File

@ -10,8 +10,8 @@
/* USB Power delivery board configuration */
#ifndef __USB_PD_CONFIG_H
#define __USB_PD_CONFIG_H
#ifndef __CROS_EC_USB_PD_CONFIG_H
#define __CROS_EC_USB_PD_CONFIG_H
/* Timer selection for baseband PD communication */
#define TIM_CLOCK_PD_TX_C0 16
@ -323,5 +323,5 @@ static inline void pd_set_vconn(int port, int polarity, int enable)
}
}
#endif /* __USB_PD_CONFIG_H */
#endif /* __CROS_EC_USB_PD_CONFIG_H */

6
board/pinky/board.h
View File

@ -5,8 +5,8 @@
/* Veyron board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
#define CONFIG_AP_HANG_DETECT
@ -83,4 +83,4 @@ int board_discharge_on_ac(int enable);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/pit/board.h
View File

@ -5,8 +5,8 @@
/* Pit board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
#define CONFIG_BATTERY_BQ20Z453
@ -50,4 +50,4 @@
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/plankton/board.h
View File

@ -5,8 +5,8 @@
/* Plankton board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
@ -116,4 +116,4 @@ int board_in_hub_mode(void);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/plankton/usb_pd_config.h
View File

@ -5,8 +5,8 @@
/* USB Power delivery board configuration */
#ifndef __USB_PD_CONFIG_H
#define __USB_PD_CONFIG_H
#ifndef __CROS_EC_USB_PD_CONFIG_H
#define __CROS_EC_USB_PD_CONFIG_H
#include "board.h"
@ -161,4 +161,4 @@ static inline int pd_adc_read(int port, int cc)
return adc_read_channel(ADC_CH_CC2_PD);
}
#endif /* __USB_PD_CONFIG_H */
#endif /* __CROS_EC_USB_PD_CONFIG_H */

6
board/rambi/board.h
View File

@ -5,8 +5,8 @@
/* Configuration for Rambi mainboard */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
#define CONFIG_AP_HANG_DETECT
@ -130,4 +130,4 @@ int board_discharge_on_ac(int enable);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/ryu/board.h
View File

@ -5,8 +5,8 @@
/* ryu board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
@ -223,4 +223,4 @@ void pp1800_on_off_evt(enum gpio_signal signal);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/ryu/usb_pd_config.h
View File

@ -5,8 +5,8 @@
/* USB Power delivery board configuration */
#ifndef __USB_PD_CONFIG_H
#define __USB_PD_CONFIG_H
#ifndef __CROS_EC_USB_PD_CONFIG_H
#define __CROS_EC_USB_PD_CONFIG_H
#include "adc.h"
#include "charge_state.h"
@ -193,4 +193,4 @@ static inline void pd_set_vconn(int port, int polarity, int enable)
GPIO_USBC_VCONN2_EN_L, !enable);
}
#endif /* __USB_PD_CONFIG_H */
#endif /* __CROS_EC_USB_PD_CONFIG_H */

6
board/ryu_p4p5/board.h
View File

@ -5,8 +5,8 @@
/* ryu board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
@ -219,4 +219,4 @@ void pp1800_on_off_evt(enum gpio_signal signal);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/ryu_p4p5/usb_pd_config.h
View File

@ -5,8 +5,8 @@
/* USB Power delivery board configuration */
#ifndef __USB_PD_CONFIG_H
#define __USB_PD_CONFIG_H
#ifndef __CROS_EC_USB_PD_CONFIG_H
#define __CROS_EC_USB_PD_CONFIG_H
#include "adc.h"
#include "charge_state.h"
@ -192,4 +192,4 @@ static inline void pd_set_vconn(int port, int polarity, int enable)
GPIO_USBC_VCONN2_EN_L, !enable);
}
#endif /* __USB_PD_CONFIG_H */
#endif /* __CROS_EC_USB_PD_CONFIG_H */

6
board/ryu_sh/board.h
View File

@ -5,8 +5,8 @@
/* ryu sensor board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
@ -77,4 +77,4 @@ enum power_signal {
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/ryu_sh_loader/board.h
View File

@ -5,8 +5,8 @@
/* ryu sensor board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
@ -62,4 +62,4 @@
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/samus/board.h
View File

@ -5,8 +5,8 @@
/* Configuration for Samus mainboard */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Debug features */
#define CONFIG_CONSOLE_CMDHELP
@ -209,4 +209,4 @@ void set_pp5000_in_g3(int mask, int enable);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/samus_pd/board.h
View File

@ -5,8 +5,8 @@
/* samus_pd board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
@ -149,4 +149,4 @@ int board_get_battery_soc(void);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/samus_pd/usb_pd_config.h
View File

@ -9,8 +9,8 @@
/* USB Power delivery board configuration */
#ifndef __USB_PD_CONFIG_H
#define __USB_PD_CONFIG_H
#ifndef __CROS_EC_USB_PD_CONFIG_H
#define __CROS_EC_USB_PD_CONFIG_H
/* Timer selection for baseband PD communication */
#define TIM_CLOCK_PD_TX_C0 17
@ -274,4 +274,4 @@ static inline void pd_set_vconn(int port, int polarity, int enable)
GPIO_USB_C1_CC2_VCONN1_EN_L, !enable);
}
#endif /* __USB_PD_CONFIG_H */
#endif /* __CROS_EC_USB_PD_CONFIG_H */

6
board/strago/board.h
View File

@ -5,8 +5,8 @@
/* Strago board configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */
@ -131,4 +131,4 @@ int board_discharge_on_ac(int enable);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/twinkie/board.h
View File

@ -5,8 +5,8 @@
/* Twinkie dongle configuration */
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
@ -139,4 +139,4 @@ enum usb_strings {
#define USB_EP_COUNT 2
#endif
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/twinkie/injector.h
View File

@ -3,8 +3,8 @@
* found in the LICENSE file.
*/
#ifndef __INJECTOR_H
#define __INJECTOR_H
#ifndef __CROS_EC_INJECTOR_H
#define __CROS_EC_INJECTOR_H
/*
* Finite state machine definition for sending complex sequences
@ -85,4 +85,4 @@ enum trace_mode {
/* Number of words in the FSM command/data buffer */
#define INJ_CMD_COUNT 128
#endif /* __INJECTOR_H */
#endif /* __CROS_EC_INJECTOR_H */

6
board/twinkie/usb_pd_config.h
View File

@ -5,8 +5,8 @@
/* USB Power delivery board configuration */
#ifndef __USB_PD_CONFIG_H
#define __USB_PD_CONFIG_H
#ifndef __CROS_EC_USB_PD_CONFIG_H
#define __CROS_EC_USB_PD_CONFIG_H
#include "ina2xx.h"
@ -177,4 +177,4 @@ static inline int pd_adc_read(int port, int cc)
return adc_read_channel(ADC_CH_CC2_PD);
}
#endif /* __USB_PD_CONFIG_H */
#endif /* __CROS_EC_USB_PD_CONFIG_H */

6
board/zinger/board.h
View File

@ -8,8 +8,8 @@
* including zinger and minimuffin.
*/
#ifndef __BOARD_H
#define __BOARD_H
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
@ -133,4 +133,4 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
#endif /* __CROS_EC_BOARD_H */

6
board/zinger/debug.h
View File

@ -4,8 +4,8 @@
*/
/* Synchronous UART debug printf */
#ifndef __BOARD_ZINGER_DEBUG_H
#define __BOARD_ZINGER_DEBUG_H
#ifndef __CROS_EC_DEBUG_H
#define __CROS_EC_DEBUG_H
#ifdef CONFIG_DEBUG_PRINTF
void debug_printf(const char *format, ...);
@ -13,4 +13,4 @@ void debug_printf(const char *format, ...);
#define debug_printf(...)
#endif
#endif /* __BOARD_ZINGER_DEBUG_H */
#endif /* __CROS_EC_DEBUG_H */

6
board/zinger/usb_pd_config.h
View File

@ -5,8 +5,8 @@
/* USB Power delivery board configuration */
#ifndef __USB_PD_CONFIG_H
#define __USB_PD_CONFIG_H
#ifndef __CROS_EC_USB_PD_CONFIG_H
#define __CROS_EC_USB_PD_CONFIG_H
/* Timer selection for baseband PD communication */
#define TIM_CLOCK_PD_TX_C0 14
@ -106,4 +106,4 @@ static inline int pd_adc_read(int port, int cc)
return (cc == 0) ? adc_read_channel(ADC_CH_CC1_PD) : 4096;
}
#endif /* __USB_PD_CONFIG_H */
#endif /* __CROS_EC_USB_PD_CONFIG_H */

6
chip/g/cr50_a1_regdefs.h
View File

@ -6,8 +6,8 @@
/* This file is autogenerated. Do not edit. */
#ifndef GC_REGDEFS_H
#define GC_REGDEFS_H
#ifndef __CROS_EC_CR50_A1_REGDEFS_H
#define __CROS_EC_CR50_A1_REGDEFS_H
#define GC___REVA__ 1
#define GC___REVB__ 2
#define GC___REVC__ 3
@ -18354,7 +18354,7 @@
-1
#endif /* GC__ENABLE_FLASH_DFT_DEFINITIONS__ */
#endif /* GC_REGDEFS_H */
#endif /* __CROS_EC_CR50_A1_REGDEFS_H */
#define GC_CONST_FSH_PE_CONTROL_READ 0x16021765
#define GC_CONST_FSH_PE_CONTROL_PROGRAM 0x27182818
#define GC_CONST_FSH_PE_CONTROL_ERASE 0x31415927

6
chip/g/cr50_fpga_regdefs.h
View File

@ -6,8 +6,8 @@
/* This file is autogenerated. Do not edit. */
#ifndef GC_REGDEFS_H
#define GC_REGDEFS_H
#ifndef __CROS_EC_CR50_FPGA_REGDEFS_H
#define __CROS_EC_CR50_FPGA_REGDEFS_H
#define GC___REVA__ 1
#define GC___REVB__ 2
#define GC___REVC__ 3
@ -18211,7 +18211,7 @@
-1
#endif /* GC__ENABLE_FLASH_DFT_DEFINITIONS__ */
#endif /* GC_REGDEFS_H */
#endif /* __CROS_EC_CR50_FPGA_REGDEFS_H */
#define GC_CONST_FSH_PE_CONTROL_READ 0x16021765
#define GC_CONST_FSH_PE_CONTROL_PROGRAM 0x27182818
#define GC_CONST_FSH_PE_CONTROL_ERASE 0x31415927

6
chip/g/pmu.h
View File

@ -3,8 +3,8 @@
* found in the LICENSE file.
*/
#ifndef INC_PMU_H_
#define INC_PMU_H_
#ifndef __CROS_EC_PMU_H
#define __CROS_EC_PMU_H
#include "common.h"
#include "registers.h"
@ -110,4 +110,4 @@ extern void pmu_powerdown_exit(void);
* enable clock doubler for USB purposes
*/
void pmu_enable_clock_doubler(void);
#endif /* INC_PMU_H_ */
#endif /* __CROS_EC_PMU_H */

6
chip/host/persistence.h
View File

@ -5,8 +5,8 @@
/* Persistence module for emulator */
#ifndef _PERSISTENCE_H
#define _PERSISTENCE_H
#ifndef __CROS_EC_PERSISTENCE_H
#define __CROS_EC_PERSISTENCE_H
#include <stdio.h>
@ -16,4 +16,4 @@ void release_persistent_storage(FILE *ps);
void remove_persistent_storage(const char *tag);
#endif /* _PERSISTENCE_H */
#endif /* __CROS_EC_PERSISTENCE_H */

4
chip/host/reboot.h
View File

@ -5,8 +5,8 @@
/* Emulator self-reboot procedure */
#ifndef __REBOOT_H
#define __REBOOT_H
#ifndef __CROS_EC_REBOOT_H
#define __CROS_EC_REBOOT_H
void emulator_reboot(void);

6
chip/it83xx/ec2i_chip.h
View File

@ -5,8 +5,8 @@
/* EC2I control module for IT83xx. */
#ifndef __CROS_EC_IT83XX_EC2I_H
#define __CROS_EC_IT83XX_EC2I_H
#ifndef __CROS_EC_EC2I_CHIP_H
#define __CROS_EC_EC2I_CHIP_H
/* Index list of the host interface registers of PNPCFG */
enum host_pnpcfg_index {
@ -123,4 +123,4 @@ enum ec2i_message ec2i_write(enum host_pnpcfg_index index, uint8_t data);
/* EC2I read */
enum ec2i_message ec2i_read(enum host_pnpcfg_index index);
#endif /* __CROS_EC_IT83XX_EC2I_H */
#endif /* __CROS_EC_EC2I_CHIP_H */

6
chip/it83xx/intc.h
View File

@ -5,8 +5,8 @@
/* INTC control module for IT83xx. */
#ifndef __CROS_EC_IT83XX_INTC_H
#define __CROS_EC_IT83XX_INTC_H
#ifndef __CROS_EC_INTC_H
#define __CROS_EC_INTC_H
void lpc_kbc_ibf_interrupt(void);
void lpc_kbc_obe_interrupt(void);
@ -17,4 +17,4 @@ void pm4_ibf_interrupt(void);
void pm5_ibf_interrupt(void);
void lpcrst_interrupt(enum gpio_signal signal);
#endif /* __CROS_EC_IT83XX_INTC_H */
#endif /* __CROS_EC_INTC_H */

6
chip/it83xx/kmsc_chip.h
View File

@ -5,9 +5,9 @@
/* Keyboard matrix scan control module for IT83xx. */
#ifndef __CROS_EC_IT83XX_KMSC_H
#define __CROS_EC_IT83XX_KMSC_H
#ifndef __CROS_EC_KMSC_CHIP_H
#define __CROS_EC_KMSC_CHIP_H
void keyboard_raw_interrupt(void);
#endif /* __CROS_EC_IT83XX_KMSC_H */
#endif /* __CROS_EC_KMSC_CHIP_H */

6
chip/it83xx/pwm_chip.h
View File

@ -5,8 +5,8 @@
/* PWM control module for IT83xx. */
#ifndef __CROS_EC_IT83XX_PWM_H
#define __CROS_EC_IT83XX_PWM_H
#ifndef __CROS_EC_PWM_CHIP_H
#define __CROS_EC_PWM_CHIP_H
/* Data structure to define PWM channel control registers. */
struct pwm_ctrl_t {
@ -42,4 +42,4 @@ struct pwm_t {
extern const struct pwm_t pwm_channels[];
#endif /* __CROS_EC_IT83XX_PWM_H */
#endif /* __CROS_EC_PWM_CHIP_H */

6
chip/lm4/pwm_chip.h
View File

@ -5,8 +5,8 @@
/* LM4-specific PWM module for Chrome EC */
#ifndef __CROS_EC_LM4_PWM_H
#define __CROS_EC_LM4_PWM_H
#ifndef __CROS_EC_PWM_CHIP_H
#define __CROS_EC_PWM_CHIP_H
/* Data structure to define PWM channels. */
struct pwm_t {
@ -18,4 +18,4 @@ struct pwm_t {
extern const struct pwm_t pwm_channels[];
#endif /* __CROS_EC_LM4_PWM_H */
#endif /* __CROS_EC_PWM_CHIP_H */

6
chip/mec1322/pwm_chip.h
View File

@ -4,8 +4,8 @@
*/
/* MEC1322-specific PWM module for Chrome EC */
#ifndef __CROS_EC_MEC1322_PWM_H
#define __CROS_EC_MEC1322_PWM_H
#ifndef __CROS_EC_PWM_CHIP_H
#define __CROS_EC_PWM_CHIP_H
/* Data structure to define PWM channels. */
struct pwm_t {
@ -18,4 +18,4 @@ struct pwm_t {
extern const struct pwm_t pwm_channels[];
#endif /* __CROS_EC_MEC1322_PWM_H */
#endif /* __CROS_EC_PWM_CHIP_H */

6
chip/npcx/clock_chip.h
View File

@ -5,8 +5,8 @@
/* NPCX-specific clock module for Chrome EC */
#ifndef CLOCK_CHIP_H_
#define CLOCK_CHIP_H_
#ifndef __CROS_EC_CLOCK_CHIP_H
#define __CROS_EC_CLOCK_CHIP_H
/**
* Return the current APB1 clock frequency in Hz.
@ -18,4 +18,4 @@ int clock_get_apb1_freq(void);
*/
int clock_get_apb2_freq(void);
#endif /* CLOCK_CHIP_H_ */
#endif /* __CROS_EC_CLOCK_CHIP_H */

6
chip/npcx/fan_chip.h
View File

@ -5,8 +5,8 @@
/* NPCX-specific MFT module for Chrome EC */
#ifndef __CROS_EC_NPCX_FAN_H
#define __CROS_EC_NPCX_FAN_H
#ifndef __CROS_EC_FAN_CHIP_H
#define __CROS_EC_FAN_CHIP_H
/* MFT module select */
enum npcx_mft_module {
@ -59,4 +59,4 @@ struct tacho_status_t {
extern const struct mft_t mft_channels[];
#endif /* __CROS_EC_NPCX_FAN_H */
#endif /* __CROS_EC_FAN_CHIP_H */

6
chip/npcx/hwtimer_chip.h
View File

@ -5,8 +5,8 @@
/* NPCX-specific hwtimer module for Chrome EC */
#ifndef HWTIMER_CHIP_H_
#define HWTIMER_CHIP_H_
#ifndef __CROS_EC_HWTIMER_CHIP_H
#define __CROS_EC_HWTIMER_CHIP_H
/* Channel definition for ITIM16 */
#define ITIM_TIME_NO ITIM16_1
@ -25,4 +25,4 @@ void init_hw_timer(int itim_no, enum ITIM16_SOURCE_CLOCK_T source);
/* Returns time delay cause of deep idle */
uint32_t __hw_clock_get_sleep_time(void);
#endif /* HWTIMER_CHIP_H_ */
#endif /* __CROS_EC_HWTIMER_CHIP_H */

6
chip/npcx/lfw/ec_lfw.h
View File

@ -5,8 +5,8 @@
* NPCX5M5G SoC little FW used by booter
*/
#ifndef __CROS_EC_LFW_H_
#define __CROS_EC_LFW_H_
#ifndef __CROS_EC_EC_LFW_H
#define __CROS_EC_EC_LFW_H
/* Begin address for the .iram section; defined in linker script */
extern unsigned int __iram_fw_start;
@ -15,4 +15,4 @@ extern unsigned int __iram_fw_end;
/* Begin address for the iram codes; defined in linker script */
extern unsigned int __flash_fw_start;
#endif /* __CROS_EC_LFW_H_ */
#endif /* __CROS_EC_EC_LFW_H */

6
chip/npcx/pwm_chip.h
View File

@ -5,8 +5,8 @@
/* NPCX-specific PWM module for Chrome EC */
#ifndef __CROS_EC_NPCX_PWM_H
#define __CROS_EC_NPCX_PWM_H
#ifndef __CROS_EC_PWM_CHIP_H
#define __CROS_EC_PWM_CHIP_H
/* Data structure to define PWM channels. */
struct pwm_t {
@ -23,4 +23,4 @@ struct pwm_t {
extern const struct pwm_t pwm_channels[];
void pwm_config(enum pwm_channel ch);
#endif /* __CROS_EC_NPCX_PWM_H */
#endif /* __CROS_EC_PWM_CHIP_H */

6
chip/npcx/system_chip.h
View File

@ -5,8 +5,8 @@
/* NPCX-specific SIB module for Chrome EC */
#ifndef __CROS_EC_NPCX_LPC_H
#define __CROS_EC_NPCX_LPC_H
#ifndef __CROS_EC_SYSTEM_CHIP_H
#define __CROS_EC_SYSTEM_CHIP_H
/* Indices for battery-backed ram (BBRAM) data position */
enum bbram_data_index {
@ -32,4 +32,4 @@ extern unsigned int __flash_lpfw_start;
/* End flash address for the lpram codes; defined in linker script */
extern unsigned int __flash_lpfw_end;
#endif /* __CROS_EC_NPCX_LPC_H */
#endif /* __CROS_EC_SYSTEM_CHIP_H */

6
chip/stm32/crc_hw.h
View File

@ -3,8 +3,8 @@
* found in the LICENSE file.
*/
#ifndef _CRC_HW_H
#define _CRC_HW_H
#ifndef __CROS_EC_CRC_HW_H
#define __CROS_EC_CRC_HW_H
/* CRC-32 hardware implementation with USB constants */
#include "clock.h"
@ -38,4 +38,4 @@ static inline uint32_t crc32_result(void)
return STM32_CRC_DR ^ 0xFFFFFFFF;
}
#endif /* _CRC_HW_H */
#endif /* __CROS_EC_CRC_HW_H */

6
chip/stm32/pwm_chip.h
View File

@ -5,8 +5,8 @@
/* STM32-specific PWM module for Chrome EC */
#ifndef __CROS_EC_STM32_PWM_H
#define __CROS_EC_STM32_PWM_H
#ifndef __CROS_EC_PWM_CHIP_H
#define __CROS_EC_PWM_CHIP_H
/* Data structure to define PWM channels. */
struct pwm_t {
@ -36,4 +36,4 @@ extern const struct pwm_t pwm_channels[];
/* Plain ID mapping for readability */
#define STM32_TIM_CH(x) (x)
#endif /* __CROS_EC_STM32_PWM_H */
#endif /* __CROS_EC_PWM_CHIP_H */

6
chip/stm32/usart-stm32f.h
View File

@ -2,8 +2,8 @@
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#ifndef CHIP_STM32_USART_STM32F_H
#define CHIP_STM32_USART_STM32F_H
#ifndef __CROS_EC_USART_STM32F_H
#define __CROS_EC_USART_STM32F_H
#include "usart.h"
@ -17,4 +17,4 @@ extern struct usart_hw_config const usart1_hw;
extern struct usart_hw_config const usart2_hw;
extern struct usart_hw_config const usart3_hw;
#endif /* CHIP_STM32_USART_STM32F_H */
#endif /* __CROS_EC_USART_STM32F_H */

6
chip/stm32/usart-stm32f0.h
View File

@ -2,8 +2,8 @@
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#ifndef CHIP_STM32_USART_STM32F0_H
#define CHIP_STM32_USART_STM32F0_H
#ifndef __CROS_EC_USART_STM32F0_H
#define __CROS_EC_USART_STM32F0_H
#include "usart.h"
@ -18,4 +18,4 @@ extern struct usart_hw_config const usart2_hw;
extern struct usart_hw_config const usart3_hw;
extern struct usart_hw_config const usart4_hw;
#endif /* CHIP_STM32_USART_STM32F0_H */
#endif /* __CROS_EC_USART_STM32F0_H */

6
chip/stm32/usart-stm32f3.h
View File

@ -2,8 +2,8 @@
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#ifndef CHIP_STM32_USART_STM32F3_H
#define CHIP_STM32_USART_STM32F3_H
#ifndef __CROS_EC_USART_STM32F3_H
#define __CROS_EC_USART_STM32F3_H
#include "usart.h"
@ -17,4 +17,4 @@ extern struct usart_hw_config const usart1_hw;
extern struct usart_hw_config const usart2_hw;
extern struct usart_hw_config const usart3_hw;
#endif /* CHIP_STM32_USART_STM32F3_H */
#endif /* __CROS_EC_USART_STM32F3_H */

6
chip/stm32/usart-stm32l.h
View File

@ -2,8 +2,8 @@
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#ifndef CHIP_STM32_USART_STM32L_H
#define CHIP_STM32_USART_STM32L_H
#ifndef __CROS_EC_USART_STM32L_H
#define __CROS_EC_USART_STM32L_H
#include "usart.h"
@ -17,4 +17,4 @@ extern struct usart_hw_config const usart1_hw;
extern struct usart_hw_config const usart2_hw;
extern struct usart_hw_config const usart3_hw;
#endif /* CHIP_STM32_USART_STM32L_H */
#endif /* __CROS_EC_USART_STM32L_H */

6
chip/stm32/usart.h
View File

@ -2,8 +2,8 @@
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#ifndef CHIP_STM32_USART_H
#define CHIP_STM32_USART_H
#ifndef __CROS_EC_USART_H
#define __CROS_EC_USART_H
/* STM32 USART driver for Chrome EC */
@ -158,4 +158,4 @@ void usart_interrupt(struct usart_config const *config);
void usart_set_baud_f0_l(struct usart_config const *config, int frequency_hz);
void usart_set_baud_f(struct usart_config const *config, int frequency_hz);
#endif /* CHIP_STM32_USART_H */
#endif /* __CROS_EC_USART_H */

6
chip/stm32/usb-stream.h
View File

@ -2,8 +2,8 @@
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#ifndef CHIP_STM32_USB_STREAM_H
#define CHIP_STM32_USB_STREAM_H
#ifndef __CROS_EC_USB_STREAM_H
#define __CROS_EC_USB_STREAM_H
/* STM32 USB STREAM driver for Chrome EC */
@ -206,4 +206,4 @@ void usb_stream_tx(struct usb_stream_config const *config);
void usb_stream_rx(struct usb_stream_config const *config);
void usb_stream_reset(struct usb_stream_config const *config);
#endif /* CHIP_STM32_USB_STREAM_H */
#endif /* __CROS_EC_USB_STREAM_H */

6
chip/stm32/usb_gpio.h
View File

@ -2,8 +2,8 @@
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#ifndef CHIP_STM32_USB_GPIO_H
#define CHIP_STM32_USB_GPIO_H
#ifndef __CROS_EC_USB_GPIO_H
#define __CROS_EC_USB_GPIO_H
/* STM32 USB GPIO driver for Chrome EC */
@ -125,4 +125,4 @@ void usb_gpio_tx(struct usb_gpio_config const *config);
void usb_gpio_rx(struct usb_gpio_config const *config);
void usb_gpio_reset(struct usb_gpio_config const *config);
#endif /* CHIP_STM32_USB_GPIO_H */
#endif /* __CROS_EC_USB_GPIO_H */

6
chip/stm32/usb_spi.h
View File

@ -2,8 +2,8 @@
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#ifndef CHIP_STM32_USB_SPI_H
#define CHIP_STM32_USB_SPI_H
#ifndef __CROS_EC_USB_SPI_H
#define __CROS_EC_USB_SPI_H
/* STM32 USB SPI driver for Chrome EC */
@ -233,4 +233,4 @@ int usb_spi_interface(struct usb_spi_config const *config,
void usb_spi_board_enable(struct usb_spi_config const *config);
void usb_spi_board_disable(struct usb_spi_config const *config);
#endif /* CHIP_STM32_USB_SPI_H */
#endif /* __CROS_EC_USB_SPI_H */

6
core/cortex-m/config_core.h
View File

@ -3,8 +3,8 @@
* found in the LICENSE file.
*/
#ifndef __CONFIG_CORE_H
#define __CONFIG_CORE_H
#ifndef __CROS_EC_CONFIG_CORE_H
#define __CROS_EC_CONFIG_CORE_H
/* Linker binary architecture and format */
#define BFD_ARCH arm
@ -12,4 +12,4 @@
#define CONFIG_SOFTWARE_PANIC
#endif /* __CONFIG_CORE_H */
#endif /* __CROS_EC_CONFIG_CORE_H */

6
core/cortex-m/cpu.h
View File

@ -5,8 +5,8 @@
* Registers map and defintions for Cortex-MLM4x processor
*/
#ifndef __CPU_H
#define __CPU_H
#ifndef __CROS_EC_CPU_H
#define __CROS_EC_CPU_H
#include <stdint.h>
@ -50,4 +50,4 @@ enum {
/* Set up the cpu to detect faults */
void cpu_init(void);
#endif /* __CPU_H */
#endif /* __CROS_EC_CPU_H */

6
core/cortex-m/include/math.h
View File

@ -5,8 +5,8 @@
/* Math utility functions for ARMv7 */
#ifndef __EC_MATH_H
#define __EC_MATH_H
#ifndef __CROS_EC_MATH_H
#define __CROS_EC_MATH_H
#ifdef CONFIG_FPU
static inline float sqrtf(float v)
@ -21,4 +21,4 @@ static inline float sqrtf(float v)
}
#endif /* CONFIG_FPU */
#endif /* __EC_MATH_H */
#endif /* __CROS_EC_MATH_H */

6
core/cortex-m/irq_handler.h
View File

@ -5,8 +5,8 @@
/* Helper to declare IRQ handling routines */
#ifndef __IRQ_HANDLER_H
#define __IRQ_HANDLER_H
#ifndef __CROS_EC_IRQ_HANDLER_H
#define __CROS_EC_IRQ_HANDLER_H
#ifdef CONFIG_TASK_PROFILING
#define bl_task_start_irq_handler "bl task_start_irq_handler\n"
@ -38,4 +38,4 @@
const struct irq_priority IRQ_PRIORITY(irq) \
__attribute__((section(".rodata.irqprio"))) \
= {irq, priority}
#endif /* __IRQ_HANDLER_H */
#endif /* __CROS_EC_IRQ_HANDLER_H */

6
core/cortex-m0/config_core.h
View File

@ -3,8 +3,8 @@
* found in the LICENSE file.
*/
#ifndef __CONFIG_CORE_H
#define __CONFIG_CORE_H
#ifndef __CROS_EC_CONFIG_CORE_H
#define __CROS_EC_CONFIG_CORE_H
/* Linker binary architecture and format */
#define BFD_ARCH arm
@ -14,4 +14,4 @@
#define CONFIG_SOFTWARE_CLZ
#define CONFIG_SOFTWARE_PANIC
#endif /* __CONFIG_CORE_H */
#endif /* __CROS_EC_CONFIG_CORE_H */

6
core/cortex-m0/cpu.h
View File

@ -5,8 +5,8 @@
* Registers map and definitions for Cortex-M0 processor
*/
#ifndef __CPU_H
#define __CPU_H
#ifndef __CROS_EC_CPU_H
#define __CROS_EC_CPU_H
#include <stdint.h>
@ -36,4 +36,4 @@
/* Set up the cpu to detect faults */
void cpu_init(void);
#endif /* __CPU_H */
#endif /* __CROS_EC_CPU_H */

6
core/cortex-m0/irq_handler.h
View File

@ -5,8 +5,8 @@
/* Helper to declare IRQ handling routines */
#ifndef __IRQ_HANDLER_H
#define __IRQ_HANDLER_H
#ifndef __CROS_EC_IRQ_HANDLER_H
#define __CROS_EC_IRQ_HANDLER_H
#include "cpu.h"
@ -39,4 +39,4 @@
__attribute__((section(".rodata.irqprio"))) \
= {irq, priority}
#endif /* CONFIG_TASK_PROFILING */
#endif /* __IRQ_HANDLER_H */
#endif /* __CROS_EC_IRQ_HANDLER_H */

6
core/host/cpu.h
View File

@ -5,9 +5,9 @@
/* CPU specific header file */
#ifndef __CPU_H
#define __CPU_H
#ifndef __CROS_EC_CPU_H
#define __CROS_EC_CPU_H
static inline void cpu_init(void) { }
#endif /* __CPU_H */
#endif /* __CROS_EC_CPU_H */

6
core/host/irq_handler.h
View File

@ -5,8 +5,8 @@
/* Helper to declare IRQ handling routines */
#ifndef __IRQ_HANDLER_H
#define __IRQ_HANDLER_H
#ifndef __CROS_EC_IRQ_HANDLER_H
#define __CROS_EC_IRQ_HANDLER_H
/* Helper macros to build the IRQ handler and priority struct names */
#define IRQ_HANDLER(irqname) CONCAT3(irq_, irqname, _handler)
@ -26,4 +26,4 @@
const struct irq_priority IRQ_PRIORITY(irq) \
__attribute__((section(".rodata.irqprio"))) \
= {irq, priority}
#endif /* __IRQ_HANDLER_H */
#endif /* __CROS_EC_IRQ_HANDLER_H */

6
core/nds32/config_core.h
View File

@ -3,8 +3,8 @@
* found in the LICENSE file.
*/
#ifndef __CONFIG_CORE_H
#define __CONFIG_CORE_H
#ifndef __CROS_EC_CONFIG_CORE_H
#define __CROS_EC_CONFIG_CORE_H
/* Linker binary architecture and format */
#define BFD_ARCH nds32
@ -29,4 +29,4 @@
((typeof(var))(*__ptr_val)); \
})
#endif /* __CONFIG_CORE_H */
#endif /* __CROS_EC_CONFIG_CORE_H */

6
core/nds32/cpu.h
View File

@ -5,8 +5,8 @@
* Registers map and defintions for Andes cores
*/
#ifndef __CPU_H
#define __CPU_H
#ifndef __CROS_EC_CPU_H
#define __CROS_EC_CPU_H
#include <stdint.h>
@ -54,4 +54,4 @@ static inline uint32_t get_itype(void)
/* Generic CPU core initialization */
void cpu_init(void);
#endif /* __CPU_H */
#endif /* __CROS_EC_CPU_H */

6
core/nds32/irq_chip.h
View File

@ -5,8 +5,8 @@
* Chip-specific part of the IRQ handling.
*/
#ifndef __IRQ_CHIP_H
#define __IRQ_CHIP_H
#ifndef __CROS_EC_IRQ_CHIP_H
#define __CROS_EC_IRQ_CHIP_H
/**
* Enable an IRQ in the chip interrupt controller.
@ -51,4 +51,4 @@ int chip_trigger_irq(int irq);
*/
void chip_init_irqs(void);
#endif /* __IRQ_CHIP_H */
#endif /* __CROS_EC_IRQ_CHIP_H */

6
core/nds32/irq_handler.h
View File

@ -5,8 +5,8 @@
/* Helper to declare IRQ handling routines */
#ifndef __IRQ_HANDLER_H
#define __IRQ_HANDLER_H
#ifndef __CROS_EC_IRQ_HANDLER_H
#define __CROS_EC_IRQ_HANDLER_H
/* Helper macros to build the IRQ handler and priority struct names */
#define IRQ_HANDLER(irqname) CONCAT3(irq_, irqname, _handler)
@ -22,4 +22,4 @@
__attribute__((section(".rodata.irqprio"))) \
= {CPU_INT(irq), priority}
#endif /* __IRQ_HANDLER_H */
#endif /* __CROS_EC_IRQ_HANDLER_H */

6
driver/accelgyro_bmi160.h
View File

@ -5,8 +5,8 @@
/* BMI160 accelerometer and gyro and BMM150 compass module for Chrome EC */
#ifndef __CROS_EC_ACCEL_BMI160_H
#define __CROS_EC_ACCEL_BMI160_H
#ifndef __CROS_EC_ACCELGYRO_BMI160_H
#define __CROS_EC_ACCELGYRO_BMI160_H
#include "accelgyro.h"
@ -285,4 +285,4 @@ struct bmi160_drv_data_t {
struct motion_data_t saved_data[3];
uint8_t flags;
};
#endif /* __CROS_EC_ACCEL_BMI160_H */
#endif /* __CROS_EC_ACCELGYRO_BMI160_H */

6
driver/accelgyro_lsm6ds0.h
View File

@ -5,8 +5,8 @@
/* LSM6DS0 accelerometer and gyro module for Chrome EC */
#ifndef __CROS_EC_ACCEL_LSM6DS0_H
#define __CROS_EC_ACCEL_LSM6DS0_H
#ifndef __CROS_EC_ACCELGYRO_LSM6DS0_H
#define __CROS_EC_ACCELGYRO_LSM6DS0_H
#include "task.h"
@ -118,4 +118,4 @@ enum lsm6ds0_bdu {
extern const struct accelgyro_drv lsm6ds0_drv;
#endif /* __CROS_EC_ACCEL_LSM6DS0_H */
#endif /* __CROS_EC_ACCELGYRO_LSM6DS0_H */

6
driver/als_isl29035.h
View File

@ -5,9 +5,9 @@
* Intersil ILS29035 light sensor driver
*/
#ifndef __CROS_EC_ALS_ILS29035_H
#define __CROS_EC_ALS_ILS29035_H
#ifndef __CROS_EC_ALS_ISL29035_H
#define __CROS_EC_ALS_ISL29035_H
int isl29035_read_lux(int *lux, int af);
#endif /* __CROS_EC_ALS_ILS29035_H */
#endif /* __CROS_EC_ALS_ISL29035_H */

4
driver/battery/sb_fw_update.h
View File

@ -40,8 +40,8 @@
* 9. cmd.0x35.read.status
*/
#ifndef __EC_SB_FW_UPDATE__
#define __EC_SB_FW_UPDATE__
#ifndef __CROS_EC_SB_FW_UPDATE_H
#define __CROS_EC_SB_FW_UPDATE_H
#define SB_FW_UPDATE_CMD_WRITE_WORD 0x35
#define SB_FW_UPDATE_CMD_WRITE_WORD_PREPARE 0x1000

6
driver/charger/bq24192.h
View File

@ -5,8 +5,8 @@
* TI bq24192 battery charger driver.
*/
#ifndef __CROS_EC_CHARGER_BQ24192_H
#define __CROS_EC_CHARGER_BQ24192_H
#ifndef __CROS_EC_BQ24192_H
#define __CROS_EC_BQ24192_H
#define BQ24192_ADDR 0xd6
@ -25,4 +25,4 @@
#define BQ24192_DEVICE_ID 0x2b
#endif /* __CROS_EC_CHARGER_BQ24192_H */
#endif /* __CROS_EC_BQ24192_H */

6
driver/charger/bq24707a.h
View File

@ -5,8 +5,8 @@
* TI bq24707A battery charger driver.
*/
#ifndef __CROS_EC_CHARGER_BQ24707A_H
#define __CROS_EC_CHARGER_BQ24707A_H
#ifndef __CROS_EC_BQ24707A_H
#define __CROS_EC_BQ24707A_H
/* Chip specific commands */
#define BQ24707_CHARGE_OPTION 0x12
@ -40,5 +40,5 @@
#define CHARGE_WATCHDOG_88SEC (2 << 13)
#define CHARGE_WATCHDOG_175SEC_DEFAULT (3 << 13)
#endif /* __CROS_EC_CHARGER_BQ24707A_H */
#endif /* __CROS_EC_BQ24707A_H */

6
driver/charger/bq24715.h
View File

@ -5,8 +5,8 @@
* TI bq24715 battery charger driver.
*/
#ifndef __CROS_EC_CHARGER_BQ24715_H
#define __CROS_EC_CHARGER_BQ24715_H
#ifndef __CROS_EC_BQ24715_H
#define __CROS_EC_BQ24715_H
/* NOTES:
* If battery is not present keep charge current register (0x14) at 0.
@ -127,4 +127,4 @@
#define INPUT_I_MAX (8064)
#define INPUT_I_STEP (64)
#endif /* __CROS_EC_CHARGER_BQ24715_H */
#endif /* __CROS_EC_BQ24715_H */

6
driver/charger/bq24725.h
View File

@ -5,8 +5,8 @@
* TI bq24725 battery charger driver.
*/
#ifndef __CROS_EC_CHARGER_BQ24725_H
#define __CROS_EC_CHARGER_BQ24725_H
#ifndef __CROS_EC_BQ24725_H
#define __CROS_EC_BQ24725_H
/* Chip specific commands */
#define BQ24725_CHARGE_OPTION 0x12
@ -46,5 +46,5 @@
#define CHARGE_WATCHDOG_88SEC (2 << 13)
#define CHARGE_WATCHDOG_175SEC_DEFAULT (3 << 13)
#endif /* __CROS_EC_CHARGER_BQ24725_H */
#endif /* __CROS_EC_BQ24725_H */

6
driver/charger/bq24735.h
View File

@ -5,8 +5,8 @@
* TI bq24735 battery charger driver.
*/
#ifndef __CROS_EC_CHARGER_BQ24735_H
#define __CROS_EC_CHARGER_BQ24735_H
#ifndef __CROS_EC_BQ24735_H
#define __CROS_EC_BQ24735_H
/* Chip specific commands */
#define BQ24735_CHARGE_OPTION 0x12
@ -54,4 +54,4 @@
#define ACPRES_DEGLITCH_150MS (0 << 15)
#define ACPRES_DEGLITCH_1300MS_DEFAULT (1 << 15)
#endif /* __CROS_EC_CHARGER_BQ24735_H */
#endif /* __CROS_EC_BQ24735_H */

6
driver/charger/bq24738.h
View File

@ -5,8 +5,8 @@
* TI bq24738 battery charger driver.
*/
#ifndef __CROS_EC_CHARGER_BQ24738_H
#define __CROS_EC_CHARGER_BQ24738_H
#ifndef __CROS_EC_BQ24738_H
#define __CROS_EC_BQ24738_H
/* Chip specific commands */
#define BQ24738_CHARGE_OPTION 0x12
@ -54,4 +54,4 @@
#define ACPRES_DEGLITCH_150MS (0 << 15)
#define ACPRES_DEGLITCH_1300MS_DEFAULT (1 << 15)
#endif /* __CROS_EC_CHARGER_BQ24738_H */
#endif /* __CROS_EC_BQ24738_H */

6
driver/charger/bq24773.h
View File

@ -5,8 +5,8 @@
* TI bq24773 battery charger driver.
*/
#ifndef __CROS_EC_CHARGER_BQ24773_H
#define __CROS_EC_CHARGER_BQ24773_H
#ifndef __CROS_EC_BQ24773_H
#define __CROS_EC_BQ24773_H
/* for i2c_read and i2c_write functions. */
#include "i2c.h"
@ -119,4 +119,4 @@ static inline int raw_write16(int offset, int value)
return i2c_write16(I2C_PORT_CHARGER, I2C_ADDR_CHARGER, offset, value);
}
#endif /* __CROS_EC_CHARGER_BQ24773_H */
#endif /* __CROS_EC_BQ24773_H */

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