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ish: fix snowball structure linker placement 

The following bug

https://buganizer.corp.google.com/issues/136002955

indicates after my initial move of snowball to use the
linker map instead of hard defined addresses that
0xFF801E80 was reading back as all zeroes.

The change that was made for this is
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1664593

I double checked the map files and everything looked
good.  For some reason using the linker to map the location
of this structure, the system does not run properly.
If I remove the link map placement of this structure
then the issue goes away.  I looked at how aon_share
was placed at the specific address in AON memory and
this CL is doing the same thing and it is working.

I think this is the way we should keep this fix and not
try to get the linker map to place this structure where
we want it.

BUG=b:136002955
BRANCH=none
TEST=make buildall -j
TEST=verify soft reboot does not indicate power reset

Change-Id: Ibb6dbd3a4414b5c546e99f5ad7e0409250de6256
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1707998
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
This commit is contained in:
Denis Brockus 2019-07-18 11:35:21 -06:00 committed by Commit Bot
parent be58022c66
commit 03c07b4105
3 changed files with 20 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
chip/ish/aontaskfw/ish_aontask.c
View File

@ -270,8 +270,16 @@ struct ish_aon_share aon_share = {
};
/* snowball structure */
__attribute__((section(".data.snowball"))) volatile
struct snowball_struct snowball;
#if defined(CHIP_FAMILY_ISH3)
/* on ISH3, reused ISH2PMC IPC message registers */
#define SNOWBALL_BASE IPC_ISH2PMC_MSG_BASE
#else
/* from ISH4, used reserved rom part of AON memory */
#define SNOWBALL_BASE (CONFIG_AON_PERSISTENT_BASE + 256)
#endif
struct snowball_struct *snowball = (void *)SNOWBALL_BASE;
/* In IMR DDR, ISH FW image has a manifest header */
#define ISH_FW_IMAGE_MANIFEST_HEADER_SIZE (0x1000)
@ -289,9 +297,9 @@ static int store_main_fw(void)
uint64_t imr_fw_addr;
uint64_t imr_fw_rw_addr;
imr_fw_addr = (((uint64_t)snowball.uma_base_hi << 32) +
snowball.uma_base_lo +
snowball.fw_offset +
imr_fw_addr = (((uint64_t)snowball->uma_base_hi << 32) +
snowball->uma_base_lo +
snowball->fw_offset +
ISH_FW_IMAGE_MANIFEST_HEADER_SIZE);
imr_fw_rw_addr = (imr_fw_addr
@ -330,9 +338,9 @@ static int restore_main_fw(void)
uint64_t imr_fw_ro_addr;
uint64_t imr_fw_rw_addr;
imr_fw_addr = (((uint64_t)snowball.uma_base_hi << 32) +
snowball.uma_base_lo +
snowball.fw_offset +
imr_fw_addr = (((uint64_t)snowball->uma_base_hi << 32) +
snowball->uma_base_lo +
snowball->fw_offset +
ISH_FW_IMAGE_MANIFEST_HEADER_SIZE);
imr_fw_ro_addr = (imr_fw_addr

18
chip/ish/aontaskfw/ish_aontask.lds.S
View File

@ -32,23 +32,10 @@ ENTRY(ish_aon_main);
* loader.
*/
/**
* Snowball data
*/
#if defined(CHIP_FAMILY_ISH3)
/* on ISH3, reused ISH2PMC IPC message registers */
#define SNOWBALL_BASE IPC_ISH2PMC_MSG_BASE
#else
/* from ISH4, used reserved rom part of AON memory */
#define SNOWBALL_BASE (CONFIG_AON_PERSISTENT_BASE + 256)
#endif
#define SNOWBALL_LEN (4*32)
MEMORY
{
/* leave STACK_SIZE bytes in the end of memory for stack */
RAM : ORIGIN = SRAM_START, LENGTH = RAM_LEN
SNOWBALL : ORIGIN = SNOWBALL_BASE, LENGTH = SNOWBALL_LEN
}
SECTIONS
@ -59,11 +46,6 @@ SECTIONS
KEEP(*(.data.aon_share))
} > RAM
.data.snowball : AT(SNOWBALL_BASE)
{
KEEP(*(.data.snowball))
} > SNOWBALL
.data :
{
*(.data)

8
chip/ish/ish_persistent_data.h
View File

@ -44,10 +44,10 @@ void ish_persistent_data_commit(void);
*/
struct snowball_struct {
uint32_t reserved[28];
uint32_t uma_base_hi;
uint32_t uma_base_lo;
uint32_t uma_limit;
uint32_t fw_offset;
uint32_t volatile uma_base_hi;
uint32_t volatile uma_base_lo;
uint32_t volatile uma_limit;
uint32_t volatile fw_offset;
};
#endif /* __CROS_EC_ISH_PERSISTENT_DATA_H */