316 lines
7.5 KiB
ArmAsm
316 lines
7.5 KiB
ArmAsm
/*
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* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <common/bl_common.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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.globl smc
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.globl zeromem
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.globl zero_normalmem
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.globl memcpy4
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.globl disable_mmu_icache_secure
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.globl disable_mmu_secure
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.globl fixup_gdt_reloc
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#define PAGE_START_MASK ~(PAGE_SIZE_MASK)
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func smc
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/*
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* For AArch32 only r0-r3 will be in the registers;
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* rest r4-r6 will be pushed on to the stack. So here, we'll
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* have to load them from the stack to registers r4-r6 explicitly.
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* Clobbers: r4-r6
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*/
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ldm sp, {r4, r5, r6}
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smc #0
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endfunc smc
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/* -----------------------------------------------------------------------
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* void zeromem(void *mem, unsigned int length)
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*
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* Initialise a region in normal memory to 0. This functions complies with the
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* AAPCS and can be called from C code.
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*
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* -----------------------------------------------------------------------
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*/
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func zeromem
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/*
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* Readable names for registers
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*
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* Registers r0, r1 and r2 are also set by zeromem which
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* branches into the fallback path directly, so cursor, length and
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* stop_address should not be retargeted to other registers.
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*/
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cursor .req r0 /* Start address and then current address */
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length .req r1 /* Length in bytes of the region to zero out */
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/*
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* Reusing the r1 register as length is only used at the beginning of
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* the function.
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*/
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stop_address .req r1 /* Address past the last zeroed byte */
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zeroreg1 .req r2 /* Source register filled with 0 */
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zeroreg2 .req r3 /* Source register filled with 0 */
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tmp .req r12 /* Temporary scratch register */
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mov zeroreg1, #0
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/* stop_address is the address past the last to zero */
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add stop_address, cursor, length
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/*
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* Length cannot be used anymore as it shares the same register with
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* stop_address.
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*/
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.unreq length
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/*
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* If the start address is already aligned to 8 bytes, skip this loop.
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*/
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tst cursor, #(8-1)
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beq .Lzeromem_8bytes_aligned
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/* Calculate the next address aligned to 8 bytes */
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orr tmp, cursor, #(8-1)
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adds tmp, tmp, #1
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/* If it overflows, fallback to byte per byte zeroing */
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beq .Lzeromem_1byte_aligned
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/* If the next aligned address is after the stop address, fall back */
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cmp tmp, stop_address
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bhs .Lzeromem_1byte_aligned
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/* zero byte per byte */
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1:
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strb zeroreg1, [cursor], #1
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cmp cursor, tmp
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bne 1b
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/* zero 8 bytes at a time */
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.Lzeromem_8bytes_aligned:
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/* Calculate the last 8 bytes aligned address. */
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bic tmp, stop_address, #(8-1)
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cmp cursor, tmp
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bhs 2f
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mov zeroreg2, #0
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1:
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stmia cursor!, {zeroreg1, zeroreg2}
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cmp cursor, tmp
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blo 1b
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2:
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/* zero byte per byte */
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.Lzeromem_1byte_aligned:
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cmp cursor, stop_address
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beq 2f
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1:
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strb zeroreg1, [cursor], #1
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cmp cursor, stop_address
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bne 1b
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2:
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bx lr
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.unreq cursor
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/*
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* length is already unreq'ed to reuse the register for another
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* variable.
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*/
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.unreq stop_address
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.unreq zeroreg1
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.unreq zeroreg2
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.unreq tmp
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endfunc zeromem
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/*
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* AArch32 does not have special ways of zeroing normal memory as AArch64 does
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* using the DC ZVA instruction, so we just alias zero_normalmem to zeromem.
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*/
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.equ zero_normalmem, zeromem
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/* --------------------------------------------------------------------------
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* void memcpy4(void *dest, const void *src, unsigned int length)
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*
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* Copy length bytes from memory area src to memory area dest.
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* The memory areas should not overlap.
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* Destination and source addresses must be 4-byte aligned.
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* --------------------------------------------------------------------------
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*/
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func memcpy4
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#if ENABLE_ASSERTIONS
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orr r3, r0, r1
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tst r3, #0x3
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ASM_ASSERT(eq)
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#endif
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/* copy 4 bytes at a time */
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m_loop4:
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cmp r2, #4
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blo m_loop1
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ldr r3, [r1], #4
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str r3, [r0], #4
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subs r2, r2, #4
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bne m_loop4
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bx lr
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/* copy byte per byte */
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m_loop1:
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ldrb r3, [r1], #1
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strb r3, [r0], #1
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subs r2, r2, #1
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bne m_loop1
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bx lr
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endfunc memcpy4
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/* ---------------------------------------------------------------------------
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* Disable the MMU in Secure State
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* ---------------------------------------------------------------------------
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*/
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func disable_mmu_secure
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mov r1, #(SCTLR_M_BIT | SCTLR_C_BIT)
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do_disable_mmu:
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#if ERRATA_A9_794073
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stcopr r0, BPIALL
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dsb
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#endif
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ldcopr r0, SCTLR
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bic r0, r0, r1
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stcopr r0, SCTLR
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isb // ensure MMU is off
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dsb sy
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bx lr
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endfunc disable_mmu_secure
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func disable_mmu_icache_secure
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ldr r1, =(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
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b do_disable_mmu
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endfunc disable_mmu_icache_secure
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/* ---------------------------------------------------------------------------
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* Helper to fixup Global Descriptor table (GDT) and dynamic relocations
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* (.rel.dyn) at runtime.
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*
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* This function is meant to be used when the firmware is compiled with -fpie
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* and linked with -pie options. We rely on the linker script exporting
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* appropriate markers for start and end of the section. For GOT, we
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* expect __GOT_START__ and __GOT_END__. Similarly for .rela.dyn, we expect
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* __RELA_START__ and __RELA_END__.
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*
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* The function takes the limits of the memory to apply fixups to as
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* arguments (which is usually the limits of the relocable BL image).
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* r0 - the start of the fixup region
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* r1 - the limit of the fixup region
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* These addresses have to be 4KB page aligned.
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* ---------------------------------------------------------------------------
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*/
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/* Relocation codes */
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#define R_ARM_RELATIVE 23
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func fixup_gdt_reloc
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mov r6, r0
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mov r7, r1
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#if ENABLE_ASSERTIONS
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/* Test if the limits are 4K aligned */
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orr r0, r0, r1
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mov r1, #(PAGE_SIZE_MASK)
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tst r0, r1
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ASM_ASSERT(eq)
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#endif
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/*
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* Calculate the offset based on return address in lr.
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* Assume that this function is called within a page at the start of
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* fixup region.
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*/
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ldr r1, =PAGE_START_MASK
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and r2, lr, r1
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subs r0, r2, r6 /* Diff(S) = Current Address - Compiled Address */
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beq 3f /* Diff(S) = 0. No relocation needed */
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ldr r1, =__GOT_START__
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add r1, r1, r0
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ldr r2, =__GOT_END__
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add r2, r2, r0
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/*
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* GOT is an array of 32_bit addresses which must be fixed up as
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* new_addr = old_addr + Diff(S).
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* The new_addr is the address currently the binary is executing from
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* and old_addr is the address at compile time.
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*/
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1: ldr r3, [r1]
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/* Skip adding offset if address is < lower limit */
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cmp r3, r6
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blo 2f
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/* Skip adding offset if address is > upper limit */
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cmp r3, r7
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bhi 2f
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add r3, r3, r0
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str r3, [r1]
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2: add r1, r1, #4
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cmp r1, r2
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blo 1b
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/* Starting dynamic relocations. Use ldr to get RELA_START and END */
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3: ldr r1, =__RELA_START__
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add r1, r1, r0
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ldr r2, =__RELA_END__
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add r2, r2, r0
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/*
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* According to ELF-32 specification, the RELA data structure is as
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* follows:
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* typedef struct {
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* Elf32_Addr r_offset;
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* Elf32_Xword r_info;
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* } Elf32_Rela;
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*
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* r_offset is address of reference
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* r_info is symbol index and type of relocation (in this case
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* code 23 which corresponds to R_ARM_RELATIVE).
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*
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* Size of Elf32_Rela structure is 8 bytes.
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*/
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/* Skip R_ARM_NONE entry with code 0 */
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1: ldr r3, [r1, #4]
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ands r3, r3, #0xff
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beq 2f
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#if ENABLE_ASSERTIONS
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/* Assert that the relocation type is R_ARM_RELATIVE */
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cmp r3, #R_ARM_RELATIVE
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ASM_ASSERT(eq)
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#endif
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ldr r3, [r1] /* r_offset */
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add r3, r0, r3 /* Diff(S) + r_offset */
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ldr r4, [r3]
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/* Skip adding offset if address is < lower limit */
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cmp r4, r6
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blo 2f
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/* Skip adding offset if address is >= upper limit */
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cmp r4, r7
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bhs 2f
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add r4, r0, r4
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str r4, [r3]
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2: add r1, r1, #8
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cmp r1, r2
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blo 1b
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bx lr
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endfunc fixup_gdt_reloc
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