179 lines
4.7 KiB
C
179 lines
4.7 KiB
C
/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <context.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/arm/tzc400.h>
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#include <drivers/generic_delay_timer.h>
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#include <drivers/st/bsec.h>
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#include <drivers/st/stm32_console.h>
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#include <drivers/st/stm32_gpio.h>
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#include <drivers/st/stm32_iwdg.h>
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#include <drivers/st/stm32mp1_clk.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <platform_sp_min.h>
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/******************************************************************************
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* Placeholder variables for copying the arguments that have been passed to
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* BL32 from BL2.
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******************************************************************************/
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static entry_point_info_t bl33_image_ep_info;
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static struct console_stm32 console;
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/*******************************************************************************
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* Interrupt handler for FIQ (secure IRQ)
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******************************************************************************/
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void sp_min_plat_fiq_handler(uint32_t id)
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{
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switch (id & INT_ID_MASK) {
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case STM32MP1_IRQ_TZC400:
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ERROR("STM32MP1_IRQ_TZC400 generated\n");
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panic();
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break;
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case STM32MP1_IRQ_AXIERRIRQ:
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ERROR("STM32MP1_IRQ_AXIERRIRQ generated\n");
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panic();
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break;
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default:
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ERROR("SECURE IT handler not define for it : %u", id);
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break;
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}
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}
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image for
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* the security state specified. BL33 corresponds to the non-secure image type
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* while BL32 corresponds to the secure image type. A NULL pointer is returned
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* if the image does not exist.
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******************************************************************************/
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entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
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{
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entry_point_info_t *next_image_info;
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next_image_info = &bl33_image_ep_info;
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if (next_image_info->pc == 0U) {
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return NULL;
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}
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return next_image_info;
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}
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/*******************************************************************************
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* Perform any BL32 specific platform actions.
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******************************************************************************/
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void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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struct dt_node_info dt_uart_info;
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int result;
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bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
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/* Imprecise aborts can be masked in NonSecure */
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write_scr(read_scr() | SCR_AW_BIT);
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mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
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BL_CODE_END - BL_CODE_BASE,
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MT_CODE | MT_SECURE);
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configure_mmu();
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assert(params_from_bl2 != NULL);
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assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
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assert(params_from_bl2->h.version >= VERSION_2);
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bl_params_node_t *bl_params = params_from_bl2->head;
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/*
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* Copy BL33 entry point information.
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* They are stored in Secure RAM, in BL2's address space.
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*/
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while (bl_params != NULL) {
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if (bl_params->image_id == BL33_IMAGE_ID) {
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bl33_image_ep_info = *bl_params->ep_info;
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break;
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}
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bl_params = bl_params->next_params_info;
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}
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if (dt_open_and_check() < 0) {
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panic();
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}
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if (bsec_probe() != 0) {
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panic();
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}
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if (stm32mp1_clk_probe() < 0) {
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panic();
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}
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result = dt_get_stdout_uart_info(&dt_uart_info);
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if ((result > 0) && (dt_uart_info.status != 0U)) {
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unsigned int console_flags;
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if (console_stm32_register(dt_uart_info.base, 0,
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STM32MP_UART_BAUDRATE, &console) ==
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0) {
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panic();
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}
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console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH |
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CONSOLE_FLAG_TRANSLATE_CRLF;
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#ifdef DEBUG
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console_flags |= CONSOLE_FLAG_RUNTIME;
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#endif
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console_set_scope(&console.console, console_flags);
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}
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}
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/*******************************************************************************
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* Initialize the MMU, security and the GIC.
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******************************************************************************/
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void sp_min_platform_setup(void)
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{
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/* Initialize tzc400 after DDR initialization */
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stm32mp1_security_setup();
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generic_delay_timer_init();
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stm32mp1_gic_init();
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/* Unlock ETZPC securable peripherals */
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#define STM32MP1_ETZPC_BASE 0x5C007000U
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#define ETZPC_DECPROT0 0x010U
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mmio_write_32(STM32MP1_ETZPC_BASE + ETZPC_DECPROT0, 0xFFFFFFFF);
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/* Set GPIO bank Z as non secure */
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for (uint32_t pin = 0U; pin < STM32MP_GPIOZ_PIN_MAX_COUNT; pin++) {
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set_gpio_secure_cfg(GPIO_BANK_Z, pin, false);
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}
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if (stm32_iwdg_init() < 0) {
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panic();
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}
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}
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void sp_min_plat_arch_setup(void)
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{
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}
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