450 lines
16 KiB
C
450 lines
16 KiB
C
/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl31/bl31.h>
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#include <common/bl_common.h>
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#include <common/interrupt_props.h>
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#include <drivers/console.h>
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#include <context.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <cortex_a57.h>
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#include <common/debug.h>
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#include <denver.h>
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#include <drivers/arm/gic_common.h>
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#include <drivers/arm/gicv2.h>
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#include <bl31/interrupt_mgmt.h>
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#include <mce.h>
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#include <mce_private.h>
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#include <memctrl.h>
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#include <plat/common/platform.h>
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#include <smmu.h>
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#include <spe.h>
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#include <tegra_def.h>
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#include <tegra_platform.h>
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#include <tegra_private.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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/* ID for spe-console */
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#define TEGRA_CONSOLE_SPE_ID 0xFE
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/*******************************************************************************
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* Structure to store the SCR addresses and its expected settings.
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*******************************************************************************
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*/
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typedef struct {
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uint32_t scr_addr;
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uint32_t scr_val;
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} scr_settings_t;
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static const scr_settings_t t194_scr_settings[] = {
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{ SCRATCH_RSV68_SCR, SCRATCH_RSV68_SCR_VAL },
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{ SCRATCH_RSV71_SCR, SCRATCH_RSV71_SCR_VAL },
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{ SCRATCH_RSV72_SCR, SCRATCH_RSV72_SCR_VAL },
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{ SCRATCH_RSV75_SCR, SCRATCH_RSV75_SCR_VAL },
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{ SCRATCH_RSV81_SCR, SCRATCH_RSV81_SCR_VAL },
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{ SCRATCH_RSV97_SCR, SCRATCH_RSV97_SCR_VAL },
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{ SCRATCH_RSV99_SCR, SCRATCH_RSV99_SCR_VAL },
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{ SCRATCH_RSV109_SCR, SCRATCH_RSV109_SCR_VAL },
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{ MISCREG_SCR_SCRTZWELCK, MISCREG_SCR_SCRTZWELCK_VAL }
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};
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/*******************************************************************************
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* The Tegra power domain tree has a single system level power domain i.e. a
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* single root node. The first entry in the power domain descriptor specifies
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* the number of power domains at the highest power level.
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*******************************************************************************
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*/
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static const uint8_t tegra_power_domain_tree_desc[] = {
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/* No of root nodes */
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1,
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/* No of clusters */
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PLATFORM_CLUSTER_COUNT,
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/* No of CPU cores - cluster0 */
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PLATFORM_MAX_CPUS_PER_CLUSTER,
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/* No of CPU cores - cluster1 */
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PLATFORM_MAX_CPUS_PER_CLUSTER,
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/* No of CPU cores - cluster2 */
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PLATFORM_MAX_CPUS_PER_CLUSTER,
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/* No of CPU cores - cluster3 */
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PLATFORM_MAX_CPUS_PER_CLUSTER
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};
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/*******************************************************************************
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* This function returns the Tegra default topology tree information.
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******************************************************************************/
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const uint8_t *plat_get_power_domain_tree_desc(void)
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{
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return tegra_power_domain_tree_desc;
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}
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/*
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* Table of regions to map using the MMU.
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*/
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static const mmap_region_t tegra_mmap[] = {
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MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x4000U, /* 16KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_GPCDMA_BASE, 0x10000U, /* 64KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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#if !ENABLE_CONSOLE_SPE
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MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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#endif
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MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x2000U, /* 8KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x1000U, /* 4KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x1000U, /* 4KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x1000U, /* 4KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x1000U, /* 4KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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#if ENABLE_CONSOLE_SPE
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MAP_REGION_FLAT(TEGRA_CONSOLE_SPE_BASE, 0x1000U, /* 4KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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#endif
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MAP_REGION_FLAT(TEGRA_TMRUS_BASE, TEGRA_TMRUS_SIZE, /* 4KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000U, /* 4KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x800000U, /* 8MB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x800000U, /* 8MB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x800000U, /* 8MB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, 0x10000U, /* 64KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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{0}
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};
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/*******************************************************************************
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* Set up the pagetables as per the platform memory map & initialize the MMU
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******************************************************************************/
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const mmap_region_t *plat_get_mmio_map(void)
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{
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/* MMIO space */
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return tegra_mmap;
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}
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/*******************************************************************************
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* Handler to get the System Counter Frequency
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******************************************************************************/
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uint32_t plat_get_syscnt_freq2(void)
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{
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return 31250000;
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}
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#if !ENABLE_CONSOLE_SPE
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/*******************************************************************************
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* Maximum supported UART controllers
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******************************************************************************/
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#define TEGRA194_MAX_UART_PORTS 7
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/*******************************************************************************
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* This variable holds the UART port base addresses
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******************************************************************************/
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static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = {
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0, /* undefined - treated as an error case */
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TEGRA_UARTA_BASE,
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TEGRA_UARTB_BASE,
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TEGRA_UARTC_BASE,
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TEGRA_UARTD_BASE,
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TEGRA_UARTE_BASE,
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TEGRA_UARTF_BASE,
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TEGRA_UARTG_BASE
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};
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#endif
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/*******************************************************************************
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* Enable console corresponding to the console ID
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******************************************************************************/
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void plat_enable_console(int32_t id)
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{
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uint32_t console_clock = 0U;
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#if ENABLE_CONSOLE_SPE
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static console_t spe_console;
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if (id == TEGRA_CONSOLE_SPE_ID) {
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(void)console_spe_register(TEGRA_CONSOLE_SPE_BASE,
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console_clock,
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TEGRA_CONSOLE_BAUDRATE,
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&spe_console);
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console_set_scope(&spe_console, CONSOLE_FLAG_BOOT |
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CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
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}
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#else
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static console_t uart_console;
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if ((id > 0) && (id < TEGRA194_MAX_UART_PORTS)) {
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/*
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* Reference clock used by the FPGAs is a lot slower.
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*/
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if (tegra_platform_is_fpga()) {
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console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
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} else {
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console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
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}
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(void)console_16550_register(tegra194_uart_addresses[id],
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console_clock,
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TEGRA_CONSOLE_BAUDRATE,
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&uart_console);
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console_set_scope(&uart_console, CONSOLE_FLAG_BOOT |
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CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
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}
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#endif
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}
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/*******************************************************************************
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* Verify SCR settings
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******************************************************************************/
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static inline bool tegra194_is_scr_valid(void)
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{
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uint32_t scr_val;
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bool ret = true;
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for (uint8_t i = 0U; i < ARRAY_SIZE(t194_scr_settings); i++) {
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scr_val = mmio_read_32((uintptr_t)t194_scr_settings[i].scr_addr);
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if (scr_val != t194_scr_settings[i].scr_val) {
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ERROR("Mismatch at SCR addr = 0x%x\n", t194_scr_settings[i].scr_addr);
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ret = false;
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}
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}
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return ret;
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}
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/*******************************************************************************
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* Handler for early platform setup
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******************************************************************************/
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void plat_early_platform_setup(void)
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{
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const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
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uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step;
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uint64_t actlr_elx;
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/* Verify chip id is t194 */
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assert(tegra_chipid_is_t194());
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/* Verify SCR settings */
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if (tegra_platform_is_silicon()) {
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assert(tegra194_is_scr_valid());
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}
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/* sanity check MCE firmware compatibility */
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mce_verify_firmware_version();
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#if RAS_FFH_SUPPORT
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/* Enable Uncorrectable RAS error */
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tegra194_ras_enable();
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#endif
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/*
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* Program XUSB STREAMIDs
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* ======================
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* T19x XUSB has support for XUSB virtualization. It will have one
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* physical function (PF) and four Virtual function (VF)
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*
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* There were below two SIDs for XUSB until T186.
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* 1) #define TEGRA_SID_XUSB_HOST 0x1bU
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* 2) #define TEGRA_SID_XUSB_DEV 0x1cU
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*
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* We have below four new SIDs added for VF(s)
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* 3) #define TEGRA_SID_XUSB_VF0 0x5dU
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* 4) #define TEGRA_SID_XUSB_VF1 0x5eU
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* 5) #define TEGRA_SID_XUSB_VF2 0x5fU
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* 6) #define TEGRA_SID_XUSB_VF3 0x60U
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*
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* When virtualization is enabled then we have to disable SID override
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* and program above SIDs in below newly added SID registers in XUSB
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* PADCTL MMIO space. These registers are TZ protected and so need to
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* be done in ATF.
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* a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU)
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* b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU)
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* c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U)
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* d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U)
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* e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U)
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* f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)
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*
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* This change disables SID override and programs XUSB SIDs in
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* above registers to support both virtualization and
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* non-virtualization platforms
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*/
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if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
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mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
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XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
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assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
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XUSB_PADCTL_HOST_AXI_STREAMID_PF_0) == TEGRA_SID_XUSB_HOST);
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mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
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XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
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assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
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XUSB_PADCTL_HOST_AXI_STREAMID_VF_0) == TEGRA_SID_XUSB_VF0);
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mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
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XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
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assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
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XUSB_PADCTL_HOST_AXI_STREAMID_VF_1) == TEGRA_SID_XUSB_VF1);
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mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
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XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
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assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
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XUSB_PADCTL_HOST_AXI_STREAMID_VF_2) == TEGRA_SID_XUSB_VF2);
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mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
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XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
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assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
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XUSB_PADCTL_HOST_AXI_STREAMID_VF_3) == TEGRA_SID_XUSB_VF3);
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mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
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XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
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assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
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XUSB_PADCTL_DEV_AXI_STREAMID_PF_0) == TEGRA_SID_XUSB_DEV);
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}
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/*
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* Enable dual execution optimized translations for all ELx.
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*/
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if (enable_ccplex_lock_step != 0U) {
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actlr_elx = read_actlr_el3();
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actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3;
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write_actlr_el3(actlr_elx);
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/* check if the bit is actually set */
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assert((read_actlr_el3() & DENVER_CPU_ENABLE_DUAL_EXEC_EL3) != 0ULL);
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actlr_elx = read_actlr_el2();
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actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2;
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write_actlr_el2(actlr_elx);
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/* check if the bit is actually set */
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assert((read_actlr_el2() & DENVER_CPU_ENABLE_DUAL_EXEC_EL2) != 0ULL);
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actlr_elx = read_actlr_el1();
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actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1;
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write_actlr_el1(actlr_elx);
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/* check if the bit is actually set */
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assert((read_actlr_el1() & DENVER_CPU_ENABLE_DUAL_EXEC_EL1) != 0ULL);
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}
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}
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/* Secure IRQs for Tegra194 */
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static const interrupt_prop_t tegra194_interrupt_props[] = {
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INTR_PROP_DESC(TEGRA_SDEI_SGI_PRIVATE, PLAT_SDEI_CRITICAL_PRI,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
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};
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/*******************************************************************************
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* Initialize the GIC and SGIs
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******************************************************************************/
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void plat_gic_setup(void)
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{
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tegra_gic_setup(tegra194_interrupt_props, ARRAY_SIZE(tegra194_interrupt_props));
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tegra_gic_init();
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/*
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* Initialize the FIQ handler
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*/
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tegra_fiq_handler_setup();
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}
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/*******************************************************************************
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* Return pointer to the BL31 params from previous bootloader
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******************************************************************************/
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struct tegra_bl31_params *plat_get_bl31_params(void)
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{
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uint64_t val;
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val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_HI_ADDR) &
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SCRATCH_BL31_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT;
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val <<= 32;
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val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_LO_ADDR);
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return (struct tegra_bl31_params *)(uintptr_t)val;
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}
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/*******************************************************************************
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* Return pointer to the BL31 platform params from previous bootloader
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******************************************************************************/
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plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
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{
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uint64_t val;
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val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR) &
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SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT;
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val <<= 32;
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val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_LO_ADDR);
|
|
|
|
return (plat_params_from_bl2_t *)(uintptr_t)val;
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* Handler for late platform setup
|
|
******************************************************************************/
|
|
void plat_late_platform_setup(void)
|
|
{
|
|
#if ENABLE_STRICT_CHECKING_MODE
|
|
/*
|
|
* Enable strict checking after programming the GSC for
|
|
* enabling TZSRAM and TZDRAM
|
|
*/
|
|
mce_enable_strict_checking();
|
|
mce_verify_strict_checking();
|
|
#endif
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* Handler to indicate support for System Suspend
|
|
******************************************************************************/
|
|
bool plat_supports_system_suspend(void)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* Platform specific runtime setup.
|
|
******************************************************************************/
|
|
void plat_runtime_setup(void)
|
|
{
|
|
/*
|
|
* During cold boot, it is observed that the arbitration
|
|
* bit is set in the Memory controller leading to false
|
|
* error interrupts in the non-secure world. To avoid
|
|
* this, clean the interrupt status register before
|
|
* booting into the non-secure world
|
|
*/
|
|
tegra_memctrl_clear_pending_interrupts();
|
|
|
|
/*
|
|
* During boot, USB3 and flash media (SDMMC/SATA) devices need
|
|
* access to IRAM. Because these clients connect to the MC and
|
|
* do not have a direct path to the IRAM, the MC implements AHB
|
|
* redirection during boot to allow path to IRAM. In this mode
|
|
* accesses to a programmed memory address aperture are directed
|
|
* to the AHB bus, allowing access to the IRAM. This mode must be
|
|
* disabled before we jump to the non-secure world.
|
|
*/
|
|
tegra_memctrl_disable_ahb_redirection();
|
|
|
|
/*
|
|
* Verify the integrity of the previously configured SMMU(s) settings
|
|
*/
|
|
tegra_smmu_verify();
|
|
}
|