163 lines
5.8 KiB
C
163 lines
5.8 KiB
C
/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020-2023, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef TEGRA_PRIVATE_H
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#define TEGRA_PRIVATE_H
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#include <platform_def.h>
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <drivers/ti/uart/uart_16550.h>
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#include <lib/psci/psci.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <tegra_gic.h>
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/*******************************************************************************
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* Implementation defined ACTLR_EL1 bit definitions
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******************************************************************************/
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#define ACTLR_EL1_PMSTATE_MASK (ULL(0xF) << 0)
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/*******************************************************************************
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* Implementation defined ACTLR_EL2 bit definitions
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******************************************************************************/
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#define ACTLR_EL2_PMSTATE_MASK (ULL(0xF) << 0)
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/*******************************************************************************
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* Struct for parameters received from BL2
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******************************************************************************/
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typedef struct plat_params_from_bl2 {
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/* TZ memory size */
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uint64_t tzdram_size;
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/* TZ memory base */
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uint64_t tzdram_base;
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/* UART port ID */
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int32_t uart_id;
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/* L2 ECC parity protection disable flag */
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int32_t l2_ecc_parity_prot_dis;
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/* SHMEM base address for storing the boot logs */
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uint64_t boot_profiler_shmem_base;
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/* System Suspend Entry Firmware size */
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uint64_t sc7entry_fw_size;
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/* System Suspend Entry Firmware base address */
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uint64_t sc7entry_fw_base;
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/* Enable dual execution */
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uint8_t enable_ccplex_lock_step;
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} plat_params_from_bl2_t;
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/*******************************************************************************
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* Helper function to access l2ctlr_el1 register on Cortex-A57 CPUs
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******************************************************************************/
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DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1)
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/*******************************************************************************
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* Struct describing parameters passed to bl31
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******************************************************************************/
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struct tegra_bl31_params {
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param_header_t h;
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image_info_t *bl31_image_info;
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entry_point_info_t *bl32_ep_info;
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image_info_t *bl32_image_info;
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entry_point_info_t *bl33_ep_info;
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image_info_t *bl33_image_info;
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};
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/*******************************************************************************
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* To suppress Coverity MISRA C-2012 Rule 2.2 violations
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*******************************************************************************/
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#define UNUSED_FUNC_NOP() asm("nop")
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/* Declarations for plat_psci_handlers.c */
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int32_t tegra_soc_validate_power_state(uint32_t power_state,
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psci_power_state_t *req_state);
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/* Declarations for plat_setup.c */
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const mmap_region_t *plat_get_mmio_map(void);
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void plat_enable_console(int32_t id);
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void plat_gic_setup(void);
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struct tegra_bl31_params *plat_get_bl31_params(void);
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plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
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void plat_early_platform_setup(void);
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void plat_late_platform_setup(void);
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void plat_relocate_bl32_image(const image_info_t *bl32_img_info);
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bool plat_supports_system_suspend(void);
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void plat_runtime_setup(void);
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/* Declarations for plat_secondary.c */
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void plat_secondary_setup(void);
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int32_t plat_lock_cpu_vectors(void);
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/* Declarations for tegra_fiq_glue.c */
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void tegra_fiq_handler_setup(void);
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int32_t tegra_fiq_get_intr_context(void);
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void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint);
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/* Declarations for tegra_helpers.S */
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bool plat_is_my_cpu_primary(void);
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/* Declarations for tegra_security.c */
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void tegra_security_setup(void);
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void tegra_security_setup_videomem(uintptr_t base, uint64_t size);
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/* Declarations for tegra_pm.c */
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void tegra_pm_system_suspend_entry(void);
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void tegra_pm_system_suspend_exit(void);
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int32_t tegra_system_suspended(void);
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int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state);
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int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state);
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int32_t tegra_soc_pwr_domain_on(u_register_t mpidr);
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int32_t tegra_soc_pwr_domain_off_early(const psci_power_state_t *target_state);
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int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state);
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int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state);
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int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state);
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int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state);
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int32_t tegra_soc_prepare_system_reset(void);
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__dead2 void tegra_soc_prepare_system_off(void);
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plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
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const plat_local_state_t *states,
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uint32_t ncpu);
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/* Declarations for tegraXXX_pm.c */
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int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl);
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int tegra_prepare_cpu_on_finish(unsigned long mpidr);
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/* Declarations for tegra_bl31_setup.c */
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plat_params_from_bl2_t *bl31_get_plat_params(void);
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int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes);
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/* Declarations for tegra_delay_timer.c */
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void tegra_delay_timer_init(void);
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void tegra_secure_entrypoint(void);
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/* Declarations for tegra_sip_calls.c */
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uintptr_t tegra_sip_handler(uint32_t smc_fid,
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u_register_t x1,
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u_register_t x2,
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u_register_t x3,
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u_register_t x4,
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void *cookie,
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void *handle,
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u_register_t flags);
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int plat_sip_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x2,
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uint64_t x3,
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uint64_t x4,
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const void *cookie,
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void *handle,
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uint64_t flags);
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#if RAS_FFH_SUPPORT
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void tegra194_ras_enable(void);
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void tegra194_ras_corrected_err_clear(uint64_t *cookie);
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#endif
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#endif /* TEGRA_PRIVATE_H */
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