141 lines
3.9 KiB
C
141 lines
3.9 KiB
C
/*
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* Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <libfdt.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/arm/css/css_mhu_doorbell.h>
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#include <drivers/arm/css/scmi.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <plat/arm/css/common/css_pm.h>
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#include <sgi_ras.h>
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#include <sgi_variant.h>
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sgi_platform_info_t sgi_plat_info;
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static scmi_channel_plat_info_t sgi575_scmi_plat_info = {
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.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
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.db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhu_ring_doorbell,
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};
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static scmi_channel_plat_info_t plat_rd_scmi_info[] = {
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{
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.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
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.db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhuv2_ring_doorbell,
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},
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#if (CSS_SGI_CHIP_COUNT > 1)
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{
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.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
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CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
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.db_reg_addr = PLAT_CSS_MHU_BASE
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+ CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1) + SENDER_REG_SET(0),
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhuv2_ring_doorbell,
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},
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#endif
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#if (CSS_SGI_CHIP_COUNT > 2)
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{
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.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
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CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
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.db_reg_addr = PLAT_CSS_MHU_BASE +
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CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2) + SENDER_REG_SET(0),
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhuv2_ring_doorbell,
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},
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#endif
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#if (CSS_SGI_CHIP_COUNT > 3)
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{
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.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
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CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
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.db_reg_addr = PLAT_CSS_MHU_BASE +
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CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3) + SENDER_REG_SET(0),
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhuv2_ring_doorbell,
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},
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#endif
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};
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scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
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{
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if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
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sgi_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
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sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
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sgi_plat_info.platform_id == RD_V2_SID_VER_PART_NUM ||
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sgi_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM ||
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sgi_plat_info.platform_id == RD_N2_CFG3_SID_VER_PART_NUM) {
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if (channel_id >= ARRAY_SIZE(plat_rd_scmi_info))
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panic();
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return &plat_rd_scmi_info[channel_id];
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}
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else if (sgi_plat_info.platform_id == SGI575_SSC_VER_PART_NUM)
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return &sgi575_scmi_plat_info;
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else
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panic();
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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sgi_plat_info.platform_id = plat_arm_sgi_get_platform_id();
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sgi_plat_info.config_id = plat_arm_sgi_get_config_id();
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sgi_plat_info.multi_chip_mode = plat_arm_sgi_get_multi_chip_mode();
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arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
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}
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void sgi_bl31_common_platform_setup(void)
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{
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arm_bl31_platform_setup();
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#if RAS_FFH_SUPPORT
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sgi_ras_intr_handler_setup();
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#endif
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/* Configure the warm reboot SGI for primary core */
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css_setup_cpu_pwr_down_intr();
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#if CSS_SYSTEM_GRACEFUL_RESET
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/* Register priority level handlers for reboot */
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ehf_register_priority_handler(PLAT_REBOOT_PRI,
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css_reboot_interrupt_handler);
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#endif
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}
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const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
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{
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/*
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* For RD-E1-Edge, only CPU power ON/OFF, PSCI platform callbacks are
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* supported.
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*/
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if (((sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) &&
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(sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID))) {
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ops->cpu_standby = NULL;
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ops->system_off = NULL;
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ops->system_reset = NULL;
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ops->get_sys_suspend_power_state = NULL;
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ops->pwr_domain_suspend = NULL;
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ops->pwr_domain_suspend_finish = NULL;
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}
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return css_scmi_override_pm_ops(ops);
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}
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