301 lines
9.6 KiB
C
301 lines
9.6 KiB
C
/*
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* Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SGI_BASE_PLATFORM_DEF_H
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#define SGI_BASE_PLATFORM_DEF_H
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#include <lib/utils_def.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#include <plat/arm/common/arm_def.h>
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#include <plat/arm/common/arm_spm_def.h>
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#include <plat/arm/css/common/css_def.h>
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#include <plat/common/common_def.h>
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#define PLATFORM_CORE_COUNT (CSS_SGI_CHIP_COUNT * \
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PLAT_ARM_CLUSTER_COUNT * \
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CSS_SGI_MAX_CPUS_PER_CLUSTER * \
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CSS_SGI_MAX_PE_PER_CPU)
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#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */
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/* Remote chip address offset */
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#define CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) \
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((ULL(1) << CSS_SGI_ADDR_BITS_PER_CHIP) * (n))
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/*
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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* plat_arm_mmap array defined for each BL stage. In addition to that, on
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* multi-chip platforms, address regions on each of the remote chips are
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* also mapped. In BL31, for instance, three address regions on the remote
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* chips are accessed - secure ram, css device and soc device regions.
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*/
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#if defined(IMAGE_BL31)
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# if SPM_MM
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# define PLAT_ARM_MMAP_ENTRIES (9 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
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# define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
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# define PLAT_SP_IMAGE_MMAP_REGIONS 10
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# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 12
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# else
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# define PLAT_ARM_MMAP_ENTRIES (5 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
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# define MAX_XLAT_TABLES (6 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
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# endif
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#elif defined(IMAGE_BL32)
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# define PLAT_ARM_MMAP_ENTRIES 8
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# define MAX_XLAT_TABLES 5
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#elif defined(IMAGE_BL2)
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# define PLAT_ARM_MMAP_ENTRIES (11 + (CSS_SGI_CHIP_COUNT - 1))
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/*
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* MAX_XLAT_TABLES entries need to be doubled because when the address width
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* exceeds 40 bits an additional level of translation is required. In case of
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* multichip platforms peripherals also fall into address space with width
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* > 40 bits
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*
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*/
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# define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 2))
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#elif !USE_ROMLIB
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# define PLAT_ARM_MMAP_ENTRIES 11
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# define MAX_XLAT_TABLES 7
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#else
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# define PLAT_ARM_MMAP_ENTRIES 12
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# define MAX_XLAT_TABLES 6
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#endif
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/*
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* plus a little space for growth.
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*/
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#define PLAT_ARM_MAX_BL1_RW_SIZE (64 * 1024) /* 64 KB */
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/*
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* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
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*/
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#if USE_ROMLIB
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#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000
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#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000
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#else
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#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0
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#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0
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#endif
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/*
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* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
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* little space for growth. Additional 8KiB space is added per chip in
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* order to accommodate the additional level of translation required for "TZC"
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* peripheral access which lies in >4TB address space.
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*
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*/
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#if TRUSTED_BOARD_BOOT
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# define PLAT_ARM_MAX_BL2_SIZE (0x20000 + ((CSS_SGI_CHIP_COUNT - 1) * \
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0x2000))
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#else
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# define PLAT_ARM_MAX_BL2_SIZE (0x14000 + ((CSS_SGI_CHIP_COUNT - 1) * \
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0x2000))
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#endif
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/*
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* Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
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* calculated using the current BL31 PROGBITS debug size plus the sizes of BL2
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* and BL1-RW. CSS_SGI_BL31_SIZE - is tuned with respect to the actual BL31
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* PROGBITS size which is around 64-68KB at the time this change is being made.
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* A buffer of ~35KB is added to account for future expansion of the image,
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* making it a total of 100KB.
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*/
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#define CSS_SGI_BL31_SIZE (100 * 1024) /* 100 KB */
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#define PLAT_ARM_MAX_BL31_SIZE (CSS_SGI_BL31_SIZE + \
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PLAT_ARM_MAX_BL2_SIZE + \
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PLAT_ARM_MAX_BL1_RW_SIZE)
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/*
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* Size of cacheable stacks
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*/
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#if defined(IMAGE_BL1)
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# if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE 0x1000
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# else
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# define PLATFORM_STACK_SIZE 0x440
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# endif
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#elif defined(IMAGE_BL2)
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# if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE 0x1000
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# else
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# define PLATFORM_STACK_SIZE 0x400
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# endif
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#elif defined(IMAGE_BL2U)
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# define PLATFORM_STACK_SIZE 0x400
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#elif defined(IMAGE_BL31)
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# if SPM_MM
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# define PLATFORM_STACK_SIZE 0x500
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# else
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# define PLATFORM_STACK_SIZE 0x400
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# endif
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#elif defined(IMAGE_BL32)
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# define PLATFORM_STACK_SIZE 0x440
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#endif
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/* PL011 UART related constants */
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#define SOC_CSS_SEC_UART_BASE UL(0x2A410000)
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#define SOC_CSS_NSEC_UART_BASE UL(0x2A400000)
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#define SOC_CSS_UART_SIZE UL(0x10000)
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#define SOC_CSS_UART_CLK_IN_HZ UL(7372800)
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/* UART related constants */
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#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_SEC_UART_BASE
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
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#define PLAT_ARM_RUN_UART_BASE SOC_CSS_SEC_UART_BASE
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#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
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#define PLAT_ARM_CRASH_UART_BASE SOC_CSS_SEC_UART_BASE
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
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#define PLAT_ARM_NSTIMER_FRAME_ID 0
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#define PLAT_ARM_TRUSTED_ROM_BASE 0x0
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#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */
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#define PLAT_ARM_NSRAM_BASE 0x06000000
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#define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */
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#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
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#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
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#define CSS_SGI_DEVICE_BASE (0x20000000)
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#define CSS_SGI_DEVICE_SIZE (0x20000000)
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#define CSS_SGI_MAP_DEVICE MAP_REGION_FLAT( \
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CSS_SGI_DEVICE_BASE, \
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CSS_SGI_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define ARM_MAP_SHARED_RAM_REMOTE_CHIP(n) \
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MAP_REGION_FLAT( \
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CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \
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ARM_SHARED_RAM_BASE, \
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ARM_SHARED_RAM_SIZE, \
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MT_NON_CACHEABLE | MT_RW | MT_SECURE \
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)
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#define CSS_SGI_MAP_DEVICE_REMOTE_CHIP(n) \
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MAP_REGION_FLAT( \
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CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \
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CSS_SGI_DEVICE_BASE, \
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CSS_SGI_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE \
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)
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#define SOC_CSS_MAP_DEVICE_REMOTE_CHIP(n) \
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MAP_REGION_FLAT( \
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CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \
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SOC_CSS_DEVICE_BASE, \
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SOC_CSS_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE \
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)
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/* Map the secure region for access from S-EL0 */
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#define PLAT_ARM_SECURE_MAP_DEVICE MAP_REGION_FLAT( \
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SOC_CSS_DEVICE_BASE, \
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SOC_CSS_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
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#define PLAT_SP_PRI PLAT_RAS_PRI
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#if SPM_MM && RAS_FFH_SUPPORT
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/*
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* CPER buffer memory of 128KB is reserved and it is placed adjacent to the
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* memory shared between EL3 and S-EL0.
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*/
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#define CSS_SGI_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
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PLAT_SP_IMAGE_NS_BUF_SIZE)
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#define CSS_SGI_SP_CPER_BUF_SIZE ULL(0x20000)
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#define CSS_SGI_SP_CPER_BUF_MMAP MAP_REGION2( \
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CSS_SGI_SP_CPER_BUF_BASE, \
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CSS_SGI_SP_CPER_BUF_BASE, \
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CSS_SGI_SP_CPER_BUF_SIZE, \
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MT_RW_DATA | MT_NS | MT_USER, \
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PAGE_SIZE)
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/*
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* Secure partition stack follows right after the memory space reserved for
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* CPER buffer memory.
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*/
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#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
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PLAT_SP_IMAGE_NS_BUF_SIZE + \
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CSS_SGI_SP_CPER_BUF_SIZE)
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#elif SPM_MM
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/*
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* Secure partition stack follows right after the memory region that is shared
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* between EL3 and S-EL0.
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*/
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#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
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PLAT_SP_IMAGE_NS_BUF_SIZE)
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#endif /* SPM_MM && RAS_FFH_SUPPORT */
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/* Platform ID address */
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#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
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#ifndef __ASSEMBLER__
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/* SSC_VERSION related accessors */
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/* Returns the part number of the platform */
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#define GET_SGI_PART_NUM \
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GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION))
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/* Returns the configuration number of the platform */
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#define GET_SGI_CONFIG_NUM \
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GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION))
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#endif /* __ASSEMBLER__ */
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/*******************************************************************************
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* Memprotect definitions
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******************************************************************************/
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/* PSCI memory protect definitions:
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* This variable is stored in a non-secure flash because some ARM reference
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* platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
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* support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
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*/
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#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
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V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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/*Secure Watchdog Constants */
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#define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
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#define SBSA_SECURE_WDOG_TIMEOUT UL(100)
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/* Number of SCMI channels on the platform */
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#define PLAT_ARM_SCMI_CHANNEL_COUNT CSS_SGI_CHIP_COUNT
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/*
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* Mapping definition of the TrustZone Controller for ARM SGI/RD platforms
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* where both the DRAM regions are marked for non-secure access. This applies
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* to multi-chip platforms.
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*/
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#define SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(n) \
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{CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE, \
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CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END, \
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ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \
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{CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE, \
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CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END, \
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ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
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#if SPM_MM
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/*
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* Stand-alone MM logs would be routed via secure UART. Define page table
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* entry for secure UART which would be common to all platforms.
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*/
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#define SOC_PLATFORM_SECURE_UART MAP_REGION_FLAT( \
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SOC_CSS_SEC_UART_BASE, \
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SOC_CSS_UART_SIZE, \
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MT_DEVICE | MT_RW | \
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MT_SECURE | MT_USER)
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#endif
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/* SDS ID for unusable CPU MPID list structure */
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#define SDS_ISOLATED_CPU_LIST_ID U(128)
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#endif /* SGI_BASE_PLATFORM_DEF_H */
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