Madhukar Pappireddy d6c76e6c65 fix(cm): add more feature registers to EL1 context mgmt ... The following system registers are made part of save and restore operations for EL1 context: TRFCR_EL1 SCXTNUM_EL0 SCXTNUM_EL1 GCSCR_EL1 GCSCRE0_EL1 GCSPR_EL1 GCSPR_EL0 Change-Id: I1077112bdc29a6c9cd39b9707d6cf10b95fa15e3 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>		2024-04-19 09:57:36 -05:00
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aarch32	Merge "fix(pmu): fix breakage on ARMv7 CPUs with SP_min as BL32" into integration	2024-04-19 14:04:52 +02:00
aarch64	fix(cm): add more feature registers to EL1 context mgmt	2024-04-19 09:57:36 -05:00
cpu_data_array.c	chore: update to use Arm word across TF-A	2023-08-08 15:12:30 +01:00