fdts: stm32mp1: realign device tree files with internal devs
Update DDR parameters to version 1.45. Remove useless sdmmc1_dir_pins_b node. Add USART3 and UART7 nodes. Correct a PMIC value for USB regulator. Add TIMER12, TIMER15, CRYP, HASH and USBOTG_HS nodes. Update DTSI file for SDMMC compatible, but overwrite it with the former name. Move BSEC board_id node to boards DTS files, as this OTP is specific to STMicroelectronics boards. Change-Id: If4d2fe090c6a8368afe8e21e5ac70579911d3939 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier
parent
0a016775ad
commit
f237822f0b
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@ -1,8 +1,8 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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/* STM32MP157C DK1/DK2 BOARD configuration
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*
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* STM32MP157C DK1/DK2 BOARD configuration
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* 1x DDR3L 4Gb, 16-bit, 533MHz.
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* Reference used NT5CC256M16DP-DI from NANYA
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*
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@ -16,8 +16,7 @@
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* address mapping : RBC
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* Tc > + 85C : N
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*/
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#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.41"
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#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45"
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#define DDR_MEM_SPEED 533000
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#define DDR_MEM_SIZE 0x20000000
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@ -90,7 +89,7 @@
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#define DDR_PTR2 0x042DA068
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#define DDR_ACIOCR 0x10400812
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#define DDR_DXCCR 0x00000C40
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#define DDR_DSGCR 0xF200001F
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#define DDR_DSGCR 0xF200011F
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#define DDR_DCR 0x0000000B
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#define DDR_DTPR0 0x38D488D0
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#define DDR_DTPR1 0x098B00D8
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@ -109,11 +108,11 @@
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#define DDR_DX1DLLCR 0x40000000
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#define DDR_DX1DQTR 0xFFFFFFFF
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#define DDR_DX1DQSTR 0x3DB02000
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#define DDR_DX2GCR 0x0000CE81
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#define DDR_DX2GCR 0x0000CE80
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#define DDR_DX2DLLCR 0x40000000
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#define DDR_DX2DQTR 0xFFFFFFFF
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#define DDR_DX2DQSTR 0x3DB02000
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#define DDR_DX3GCR 0x0000CE81
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#define DDR_DX3GCR 0x0000CE80
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#define DDR_DX3DLLCR 0x40000000
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#define DDR_DX3DQTR 0xFFFFFFFF
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#define DDR_DX3DQSTR 0x3DB02000
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@ -1,9 +1,8 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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/* STM32MP157C ED1 BOARD configuration
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*
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* STM32MP157C ED1 BOARD configuration
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* 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
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* Reference used NT5CC256M16DP-DI from NANYA
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*
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@ -17,8 +16,7 @@
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* address mapping : RBC
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* Tc > + 85C : N
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*/
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#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.41"
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#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45"
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#define DDR_MEM_SPEED 533000
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#define DDR_MEM_SIZE 0x40000000
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@ -91,7 +89,7 @@
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#define DDR_PTR2 0x042DA068
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#define DDR_ACIOCR 0x10400812
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#define DDR_DXCCR 0x00000C40
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#define DDR_DSGCR 0xF200001F
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#define DDR_DSGCR 0xF200011F
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#define DDR_DCR 0x0000000B
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#define DDR_DTPR0 0x38D488D0
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#define DDR_DTPR1 0x098B00D8
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@ -214,21 +214,6 @@
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};
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};
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sdmmc1_dir_pins_b: sdmmc1-dir-1 {
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pins1 {
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pinmux = <STM32_PINMUX('E', 12, AF8)>, /* SDMMC1_D0DIR */
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<STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */
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<STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
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slew-rate = <3>;
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drive-push-pull;
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bias-pull-up;
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};
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pins2 {
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pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
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bias-pull-up;
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};
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};
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sdmmc2_b4_pins_a: sdmmc2-b4-0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
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@ -286,6 +271,19 @@
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};
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};
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uart7_pins_a: uart7-0 {
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pins1 {
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pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
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bias-disable;
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};
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};
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usart3_pins_a: usart3-0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
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@ -300,6 +298,21 @@
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bias-disable;
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};
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};
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usart3_pins_b: usart3-1 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
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<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
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<STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
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bias-disable;
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};
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};
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};
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pinctrl_z: pin-controller-z@54004000 {
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@ -15,6 +15,8 @@
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aliases {
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serial0 = &uart4;
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serial1 = &usart3;
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serial2 = &uart7;
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};
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chosen {
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@ -176,6 +178,18 @@
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status = "okay";
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};
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&uart7 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart7_pins_a>;
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status = "disabled";
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};
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&usart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&usart3_pins_b>;
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status = "disabled";
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};
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/* ATF Specific */
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
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@ -287,3 +301,11 @@
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cfg = < 3 98 5 7 7 PQR(1,1,1) >;
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};
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};
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&bsec {
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board_id: board_id@ec {
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reg = <0xec 0x4>;
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status = "okay";
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secure-status = "okay";
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};
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};
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@ -42,7 +42,7 @@
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st,main-control-register = <0x04>;
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st,vin-control-register = <0xc0>;
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st,usb-control-register = <0x30>;
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st,usb-control-register = <0x20>;
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regulators {
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compatible = "st,stpmic1-regulators";
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@ -308,4 +308,10 @@
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};
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};
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/delete-node/ &clk_csi;
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&bsec {
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board_id: board_id@ec {
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reg = <0xec 0x4>;
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status = "okay";
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secure-status = "okay";
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};
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};
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@ -26,9 +26,12 @@
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status = "okay";
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secure-status = "okay";
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};
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board_id: board_id@ec {
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reg = <0xec 0x4>;
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status = "okay";
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secure-status = "okay";
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};
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};
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&sdmmc1 {
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compatible = "st,stm32-sdmmc2";
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};
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&sdmmc2 {
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compatible = "st,stm32-sdmmc2";
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};
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@ -70,6 +70,16 @@
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interrupt-parent = <&intc>;
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ranges;
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timers12: timer@40006000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40006000 0x400>;
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clocks = <&rcc TIM12_K>;
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clock-names = "int";
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status = "disabled";
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};
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usart2: serial@4000e000 {
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compatible = "st,stm32h7-uart";
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reg = <0x4000e000 0x400>;
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@ -127,8 +137,19 @@
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status = "disabled";
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};
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timers15: timer@44006000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x44006000 0x400>;
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clocks = <&rcc TIM15_K>;
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clock-names = "int";
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status = "disabled";
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};
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sdmmc3: sdmmc@48004000 {
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compatible = "st,stm32-sdmmc2";
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00253180>;
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reg = <0x48004000 0x400>, <0x48005000 0x400>;
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clocks = <&rcc SDMMC3_K>;
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clock-names = "apb_pclk";
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@ -139,6 +160,16 @@
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status = "disabled";
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};
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usbotg_hs: usb-otg@49000000 {
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compatible = "st,stm32mp1-hsotg", "snps,dwc2";
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reg = <0x49000000 0x10000>;
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clocks = <&rcc USBO_K>;
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clock-names = "otg";
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resets = <&rcc USBO_R>;
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reset-names = "dwc2";
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status = "disabled";
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};
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rcc: rcc@50000000 {
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compatible = "st,stm32mp1-rcc", "syscon";
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reg = <0x50000000 0x1000>;
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@ -176,6 +207,24 @@
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clocks = <&rcc SYSCFG>;
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};
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cryp1: cryp@54001000 {
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compatible = "st,stm32mp1-cryp";
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reg = <0x54001000 0x400>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc CRYP1>;
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resets = <&rcc CRYP1_R>;
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status = "disabled";
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};
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hash1: hash@54002000 {
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compatible = "st,stm32f756-hash";
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reg = <0x54002000 0x400>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc HASH1>;
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resets = <&rcc HASH1_R>;
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status = "disabled";
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};
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rng1: rng@54003000 {
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compatible = "st,stm32-rng";
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reg = <0x54003000 0x400>;
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@ -208,7 +257,8 @@
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};
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sdmmc1: sdmmc@58005000 {
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compatible = "st,stm32-sdmmc2";
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00253180>;
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reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
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clocks = <&rcc SDMMC1_K>;
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clock-names = "apb_pclk";
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@ -220,7 +270,8 @@
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};
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sdmmc2: sdmmc@58007000 {
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compatible = "st,stm32-sdmmc2";
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00253180>;
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reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
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clocks = <&rcc SDMMC2_K>;
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clock-names = "apb_pclk";
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