Merge changes If61ab215,I3e8b0251,I1757eee9,I81b48475,I46b445a7, ... into integration
* changes: rcar_gen3: drivers: qos: Move QoS drivers out of staging rcar_gen3: drivers: qos: V3M: Configure DBSC QoS from a table rcar_gen3: drivers: qos: E3: Configure DBSC QoS from a table rcar_gen3: drivers: qos: D3: Configure DBSC QoS from a table rcar_gen3: drivers: qos: M3N: Configure DBSC QoS from a table rcar_gen3: drivers: qos: M3W: Configure DBSC QoS from a table rcar_gen3: drivers: qos: H3: Configure DBSC QoS from a table rcar_gen3: drivers: qos: Add function to configure DBSC QoS settings from a table rcar_gen3: drivers: qos: Fix checkpatch issues rcar_gen3: drivers: qos: V3M: Drop useless comments rcar_gen3: drivers: qos: V3M: Convert mstat table to uint64_t rcar_gen3: drivers: qos: V3M: Factor out mstat fix into separate file rcar_gen3: drivers: qos: V3M: Use common register definition rcar_gen3: drivers: qos: E3: Drop extra level of nesting rcar_gen3: drivers: qos: E3: Use common register definition rcar_gen3: drivers: qos: D3: Replace ad-hoc register addresses with macros rcar_gen3: drivers: qos: D3: Drop MD pin check rcar_gen3: drivers: qos: D3: Make DBSC settings local to dbsc_setting() rcar_gen3: drivers: qos: D3: Drop useless comments rcar_gen3: drivers: qos: D3: Convert mstat table to uint64_t rcar_gen3: drivers: qos: D3: Factor out mstat fix into separate file rcar_gen3: drivers: qos: D3: Use common register definition rcar_gen3: drivers: qos: M3N: Fix checkpatch issues rcar_gen3: drivers: qos: M3N: Drop MD pin check rcar_gen3: drivers: qos: M3N: Drop useless comments rcar_gen3: drivers: qos: M3N: Drop extra level of nesting rcar_gen3: drivers: qos: M3N: Use common register definition rcar_gen3: drivers: qos: M3W: Fix checkpatch issues rcar_gen3: drivers: qos: M3W: Drop MD pin check rcar_gen3: drivers: qos: M3W: Drop useless comments rcar_gen3: drivers: qos: M3W: Drop extra level of nesting rcar_gen3: drivers: qos: M3W: Convert mstat table to uint64_t rcar_gen3: drivers: qos: M3W: Factor out mstat fix into separate file rcar_gen3: drivers: qos: M3W: Use common register definition rcar_gen3: drivers: qos: H3: Fix checkpatch issues rcar_gen3: drivers: qos: H3: Drop MD pin check rcar_gen3: drivers: qos: H3: Drop useless comments rcar_gen3: drivers: qos: H3: Drop extra level of nesting rcar_gen3: drivers: qos: H3: Convert mstat table to uint64_t rcar_gen3: drivers: qos: H3: Factor out mstat fix into separate file rcar_gen3: drivers: qos: H3: Use common register definition rcar_gen3: console: Convert to multi-console API
This commit is contained in:
John Tsichritzis
TrustedFirmware Code Review
commit
de3ad4f096
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@ -1,81 +1,88 @@
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/*
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* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <console_macros.S>
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#include <drivers/renesas/rcar/console/console.h>
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.globl console_init
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.globl console_putc
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.globl console_uninit
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.globl console_core_init
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.globl console_core_putc
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.globl console_core_getc
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.globl console_flush
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.globl console_rcar_register
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.globl console_rcar_init
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.globl console_rcar_putc
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.globl console_rcar_flush
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.extern rcar_log_init
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.extern rcar_set_log_data
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/* -----------------------------------------------
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* int console_core_init(unsigned long base_addr,
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* unsigned int uart_clk, unsigned int baud_rate)
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* Function to initialize the log area. This
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* function will be accessed by console_init and
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* crash reporting.
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* Return 1 on SUCCESS, 0 on error
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* In: x0 - Not used
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* w1 - Not used
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* w2 - Not used
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* int console_rcar_register(
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* uintptr_t base, uint32_t clk, uint32_t baud,
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* console_rcar_t *console)
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* Function to initialize and register a new rcar
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* console. Storage passed in for the console struct
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* *must* be persistent (i.e. not from the stack).
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* In: x0 - UART register base address
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* w1 - UART clock in Hz
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* w2 - Baud rate
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* x3 - pointer to empty console_rcar_t struct
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* Out: return 1 on success, 0 on error
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* Clobber list : x0, x1, x2, x6, x7, x14
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* -----------------------------------------------
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*/
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func console_core_init
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b rcar_log_init
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endfunc console_core_init
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func console_init
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b console_core_init
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endfunc console_init
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func console_rcar_register
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mov x7, x30
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mov x6, x3
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cbz x6, register_fail
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str x0, [x6, #CONSOLE_T_RCAR_BASE]
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/* --------------------------------------------------------
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* int console_core_putc(int c, unsigned long base_addr)
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* Function to output a character over the log area.
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* Return 1 on SUCCESS, 0 on error
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* In : w0 - Not used
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* x1 - Not used
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* --------------------------------------------------------
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*/
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func console_core_putc
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b rcar_set_log_data
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endfunc console_core_putc
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func console_putc
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b console_core_putc
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endfunc console_putc
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bl rcar_log_init
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cbz x0, register_fail
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mov x0, x6
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mov x30, x7
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finish_console_register rcar, putc=1, getc=0, flush=1
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register_fail:
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ret x7
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endfunc console_rcar_register
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/* ---------------------------------------------
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* int console_core_getc(unsigned long base_addr)
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* Function to get a character from the console.
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* It returns the character grabbed on success
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* or -1 on error.
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* In : x0 - console base address
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* Clobber list : x0, x1
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* int console_rcar_init(unsigned long base_addr,
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* unsigned int uart_clk, unsigned int baud_rate)
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* Function to initialize the console without a
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* C Runtime to print debug information. This
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* function will be accessed by crash reporting.
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* In: x0 - console base address
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* w1 - Uart clock in Hz
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* w2 - Baud rate
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* Out: return 1 on success
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func console_core_getc
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func console_rcar_init
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mov w0, #0
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ret
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endfunc console_core_getc
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endfunc console_rcar_init
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/* -----------------------------------------------
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* void console_uninit(void)
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* Function to finish the use of console driver.
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* -----------------------------------------------
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/* --------------------------------------------------------
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* int console_rcar_putc(int c, console_rcar_t *console)
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* Function to output a character over the console. It
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* returns the character printed on success or -1 on error.
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* In : w0 - character to be printed
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* x1 - pointer to console_rcar_t structure
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* Out : return -1 on error else return character.
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* Clobber list : x2
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* --------------------------------------------------------
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*/
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func console_uninit
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ret
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endfunc console_uninit
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func console_rcar_putc
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b rcar_set_log_data
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endfunc console_rcar_putc
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/* ---------------------------------------------
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* int console_flush(void)
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* int console_rcar_flush(void)
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* Function to force a write of all buffered
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* data that hasn't been output. It returns 0
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* upon successful completion, otherwise it
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@ -83,7 +90,7 @@ endfunc console_uninit
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func console_flush
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func console_rcar_flush
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mov w0, #0
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ret
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endfunc console_flush
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endfunc console_rcar_flush
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@ -0,0 +1,147 @@
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/*
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <common/debug.h>
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#include "../qos_common.h"
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#include "../qos_reg.h"
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#include "qos_init_d3.h"
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#define RCAR_QOS_VERSION "rev.0.05"
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#include "qos_init_d3_mstat.h"
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struct rcar_gen3_dbsc_qos_settings d3_qos[] = {
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/* BUFCAM settings */
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{ DBSC_DBCAM0CNF1, 0x00043218 },
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{ DBSC_DBCAM0CNF2, 0x000000F4 },
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{ DBSC_DBSCHCNT0, 0x000F0037 },
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{ DBSC_DBSCHSZ0, 0x00000001 },
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{ DBSC_DBSCHRW0, 0x22421111 },
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/* DDR3 */
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{ DBSC_SCFCTST2, 0x012F1123 },
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/* QoS Settings */
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{ DBSC_DBSCHQOS00, 0x00000F00 },
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{ DBSC_DBSCHQOS01, 0x00000B00 },
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{ DBSC_DBSCHQOS02, 0x00000000 },
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{ DBSC_DBSCHQOS03, 0x00000000 },
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{ DBSC_DBSCHQOS40, 0x00000300 },
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{ DBSC_DBSCHQOS41, 0x000002F0 },
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{ DBSC_DBSCHQOS42, 0x00000200 },
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{ DBSC_DBSCHQOS43, 0x00000100 },
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{ DBSC_DBSCHQOS90, 0x00000300 },
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{ DBSC_DBSCHQOS91, 0x000002F0 },
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{ DBSC_DBSCHQOS92, 0x00000200 },
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{ DBSC_DBSCHQOS93, 0x00000100 },
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{ DBSC_DBSCHQOS130, 0x00000100 },
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{ DBSC_DBSCHQOS131, 0x000000F0 },
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{ DBSC_DBSCHQOS132, 0x000000A0 },
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{ DBSC_DBSCHQOS133, 0x00000040 },
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{ DBSC_DBSCHQOS140, 0x000000C0 },
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{ DBSC_DBSCHQOS141, 0x000000B0 },
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{ DBSC_DBSCHQOS142, 0x00000080 },
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{ DBSC_DBSCHQOS143, 0x00000040 },
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{ DBSC_DBSCHQOS150, 0x00000040 },
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{ DBSC_DBSCHQOS151, 0x00000030 },
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{ DBSC_DBSCHQOS152, 0x00000020 },
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{ DBSC_DBSCHQOS153, 0x00000010 },
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};
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void qos_init_d3(void)
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{
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rcar_qos_dbsc_setting(d3_qos, ARRAY_SIZE(d3_qos), true);
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/* DRAM Split Address mapping */
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#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
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ERROR("DRAM Split 4ch not supported.(D3)");
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panic();
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#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
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ERROR("DRAM Split 2ch not supported.(D3)");
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panic();
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#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO
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ERROR("DRAM Split Auto not supported.(D3)");
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panic();
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#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_LINEAR
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/* NOTICE("BL2: DRAM Split is OFF\n"); */
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/* Split setting(DDR 1ch) */
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io_write_32(AXI_ADSPLCR0, 0x00000000U);
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io_write_32(AXI_ADSPLCR3, 0x00000000U);
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#else
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ERROR("DRAM split is an invalid value.(D3)");
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panic();
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#endif
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#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
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#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
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NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
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#endif
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/* Resource Alloc setting */
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io_write_32(QOSCTRL_RAS, 0x00000020U);
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io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
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io_write_32(QOSCTRL_RAEN, 0x00000001U);
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io_write_32(QOSCTRL_REGGD, 0x00000000U);
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io_write_64(QOSCTRL_DANN, 0x0404020002020201U);
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io_write_32(QOSCTRL_DANT, 0x00100804U);
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io_write_32(QOSCTRL_EC, 0x00000000U);
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io_write_64(QOSCTRL_EMS, 0x0000000000000000U);
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io_write_32(QOSCTRL_FSS, 0x0000000AU);
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io_write_32(QOSCTRL_INSFC, 0xC7840001U);
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io_write_32(QOSCTRL_BERR, 0x00000000U);
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io_write_32(QOSCTRL_EARLYR, 0x00000000U);
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io_write_32(QOSCTRL_RACNT0, 0x00010003U);
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io_write_32(QOSCTRL_STATGEN0, 0x00000000U);
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/* GPU setting */
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io_write_32(0xFD812030U, 0x00000000U);
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/* QOSBW setting */
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io_write_32(QOSCTRL_SL_INIT, 0x030500ACU);
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io_write_32(QOSCTRL_REF_ARS, 0x00780000U);
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/* QOSBW SRAM setting */
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uint32_t i;
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for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
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io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
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io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
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}
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for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
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io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
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io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
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}
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/* 3DG bus Leaf setting */
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io_write_32(GPU_ACT_GRD, 0x00001234U);
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io_write_32(GPU_ACT0, 0x00000000U);
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io_write_32(GPU_ACT1, 0x00000000U);
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io_write_32(GPU_ACT2, 0x00000000U);
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io_write_32(GPU_ACT3, 0x00000000U);
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/* RT bus Leaf setting */
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io_write_32(CPU_ACT0, 0x00000003U);
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io_write_32(CPU_ACT1, 0x00000003U);
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io_write_32(RT_ACT0, 0x00000000U);
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io_write_32(RT_ACT1, 0x00000000U);
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/* Resource Alloc start */
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io_write_32(QOSCTRL_RAEN, 0x00000001U);
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/* QOSBW start */
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io_write_32(QOSCTRL_STATQC, 0x00000001U);
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#else
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NOTICE("BL2: QoS is None\n");
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/* Resource Alloc setting */
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io_write_32(QOSCTRL_EC, 0x00000000U);
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/* Resource Alloc start */
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io_write_32(QOSCTRL_RAEN, 0x00000001U);
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#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
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}
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|
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@ -0,0 +1,244 @@
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/*
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
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* SPDX-License-Identifier: BSD-3-Clause
|
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*/
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#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
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static const uint64_t mstat_fix[] = {
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/* 0x0000, */ 0x0000000000000000UL,
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/* 0x0008, */ 0x0000000000000000UL,
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/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
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||||
/* 0x0020, */ 0x0000000000000000UL,
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||||
/* 0x0028, */ 0x0000000000000000UL,
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||||
/* 0x0030, */ 0x001004340000FFFFUL,
|
||||
/* 0x0038, */ 0x001004140000FFFFUL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x00140B030000FFFFUL,
|
||||
/* 0x0060, */ 0x001408610000FFFFUL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x001410620000FFFFUL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00A0, */ 0x000C041C0000FFFFUL,
|
||||
/* 0x00A8, */ 0x000C04090000FFFFUL,
|
||||
/* 0x00B0, */ 0x000C04110000FFFFUL,
|
||||
/* 0x00B8, */ 0x0000000000000000UL,
|
||||
/* 0x00C0, */ 0x000C041C0000FFFFUL,
|
||||
/* 0x00C8, */ 0x000C04090000FFFFUL,
|
||||
/* 0x00D0, */ 0x000C04110000FFFFUL,
|
||||
/* 0x00D8, */ 0x0000000000000000UL,
|
||||
/* 0x00E0, */ 0x0000000000000000UL,
|
||||
/* 0x00E8, */ 0x0000000000000000UL,
|
||||
/* 0x00F0, */ 0x001018570000FFFFUL,
|
||||
/* 0x00F8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x001008570000FFFFUL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x001008520000FFFFUL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x00100CA30000FFFFUL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01A0, */ 0x0000000000000000UL,
|
||||
/* 0x01A8, */ 0x0000000000000000UL,
|
||||
/* 0x01B0, */ 0x0000000000000000UL,
|
||||
/* 0x01B8, */ 0x0000000000000000UL,
|
||||
/* 0x01C0, */ 0x0000000000000000UL,
|
||||
/* 0x01C8, */ 0x0000000000000000UL,
|
||||
/* 0x01D0, */ 0x0000000000000000UL,
|
||||
/* 0x01D8, */ 0x0000000000000000UL,
|
||||
/* 0x01E0, */ 0x0000000000000000UL,
|
||||
/* 0x01E8, */ 0x000C04020000FFFFUL,
|
||||
/* 0x01F0, */ 0x0000000000000000UL,
|
||||
/* 0x01F8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x000C04090000FFFFUL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x001410040000FFFFUL,
|
||||
/* 0x0270, */ 0x001404020000FFFFUL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001410040000FFFFUL,
|
||||
/* 0x0298, */ 0x001404020000FFFFUL,
|
||||
/* 0x02A0, */ 0x000C04050000FFFFUL,
|
||||
/* 0x02A8, */ 0x000C04050000FFFFUL,
|
||||
/* 0x02B0, */ 0x0000000000000000UL,
|
||||
/* 0x02B8, */ 0x0000000000000000UL,
|
||||
/* 0x02C0, */ 0x0000000000000000UL,
|
||||
/* 0x02C8, */ 0x0000000000000000UL,
|
||||
/* 0x02D0, */ 0x000C04050000FFFFUL,
|
||||
/* 0x02D8, */ 0x000C04050000FFFFUL,
|
||||
/* 0x02E0, */ 0x0000000000000000UL,
|
||||
/* 0x02E8, */ 0x0000000000000000UL,
|
||||
/* 0x02F0, */ 0x0000000000000000UL,
|
||||
/* 0x02F8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
/* 0x0370, */ 0x000C04020000FFFFUL,
|
||||
/* 0x0378, */ 0x000C04020000FFFFUL,
|
||||
/* 0x0380, */ 0x000C04090000FFFFUL,
|
||||
/* 0x0388, */ 0x000C04090000FFFFUL,
|
||||
/* 0x0390, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static const uint64_t mstat_be[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00A0, */ 0x0000000000000000UL,
|
||||
/* 0x00A8, */ 0x0000000000000000UL,
|
||||
/* 0x00B0, */ 0x0000000000000000UL,
|
||||
/* 0x00B8, */ 0x0000000000000000UL,
|
||||
/* 0x00C0, */ 0x0000000000000000UL,
|
||||
/* 0x00C8, */ 0x0000000000000000UL,
|
||||
/* 0x00D0, */ 0x0000000000000000UL,
|
||||
/* 0x00D8, */ 0x0000000000000000UL,
|
||||
/* 0x00E0, */ 0x0000000000000000UL,
|
||||
/* 0x00E8, */ 0x0000000000000000UL,
|
||||
/* 0x00F0, */ 0x0000000000000000UL,
|
||||
/* 0x00F8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01A0, */ 0x0000000000000000UL,
|
||||
/* 0x01A8, */ 0x0000000000000000UL,
|
||||
/* 0x01B0, */ 0x0000000000000000UL,
|
||||
/* 0x01B8, */ 0x0000000000000000UL,
|
||||
/* 0x01C0, */ 0x00110090060FA001UL,
|
||||
/* 0x01C8, */ 0x00110090060FA001UL,
|
||||
/* 0x01D0, */ 0x0000000000000000UL,
|
||||
/* 0x01D8, */ 0x0000000000000000UL,
|
||||
/* 0x01E0, */ 0x0000000000000000UL,
|
||||
/* 0x01E8, */ 0x0000000000000000UL,
|
||||
/* 0x01F0, */ 0x0011001006004401UL,
|
||||
/* 0x01F8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0011001006004401UL,
|
||||
/* 0x0218, */ 0x0011001006009801UL,
|
||||
/* 0x0220, */ 0x0011001006009801UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0011001006009801UL,
|
||||
/* 0x0238, */ 0x0011001006009801UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02A0, */ 0x0000000000000000UL,
|
||||
/* 0x02A8, */ 0x0000000000000000UL,
|
||||
/* 0x02B0, */ 0x0000000000000000UL,
|
||||
/* 0x02B8, */ 0x0011001006003401UL,
|
||||
/* 0x02C0, */ 0x0000000000000000UL,
|
||||
/* 0x02C8, */ 0x0000000000000000UL,
|
||||
/* 0x02D0, */ 0x0000000000000000UL,
|
||||
/* 0x02D8, */ 0x0000000000000000UL,
|
||||
/* 0x02E0, */ 0x0000000000000000UL,
|
||||
/* 0x02E8, */ 0x0011001006003401UL,
|
||||
/* 0x02F0, */ 0x00110090060FA001UL,
|
||||
/* 0x02F8, */ 0x00110090060FA001UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0012001006003401UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x00120090060FA001UL,
|
||||
/* 0x0360, */ 0x00120090060FA001UL,
|
||||
/* 0x0368, */ 0x0012001006003401UL,
|
||||
/* 0x0370, */ 0x0000000000000000UL,
|
||||
/* 0x0378, */ 0x0000000000000000UL,
|
||||
/* 0x0380, */ 0x0000000000000000UL,
|
||||
/* 0x0388, */ 0x0000000000000000UL,
|
||||
/* 0x0390, */ 0x0012001006003401UL,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -14,9 +14,6 @@
|
|||
|
||||
#define RCAR_QOS_VERSION "rev.0.05"
|
||||
|
||||
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
|
||||
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
|
||||
|
||||
#define REF_ARS_ARBSTOPCYCLE_E3 (((SL_INIT_SSLOTCLK_E3) - 5U) << 16U)
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
|
|
@ -29,54 +26,47 @@
|
|||
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
/* Register write enable */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
|
||||
|
||||
struct rcar_gen3_dbsc_qos_settings e3_qos[] = {
|
||||
/* BUFCAM settings */
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00043218);
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x000F0037);
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001);
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111);
|
||||
{ DBSC_DBCAM0CNF1, 0x00043218 },
|
||||
{ DBSC_DBCAM0CNF2, 0x000000F4 },
|
||||
{ DBSC_DBSCHCNT0, 0x000F0037 },
|
||||
{ DBSC_DBSCHSZ0, 0x00000001 },
|
||||
{ DBSC_DBSCHRW0, 0x22421111 },
|
||||
|
||||
/* DDR3 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
{ DBSC_SCFCTST2, 0x012F1123 },
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
|
||||
io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
|
||||
io_write_32(DBSC_DBSCHQOS02, 0x00000000);
|
||||
io_write_32(DBSC_DBSCHQOS03, 0x00000000);
|
||||
io_write_32(DBSC_DBSCHQOS40, 0x00000300);
|
||||
io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
|
||||
io_write_32(DBSC_DBSCHQOS42, 0x00000200);
|
||||
io_write_32(DBSC_DBSCHQOS43, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS90, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
|
||||
io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
|
||||
io_write_32(DBSC_DBSCHQOS93, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS130, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
|
||||
io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
|
||||
io_write_32(DBSC_DBSCHQOS133, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
|
||||
io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
|
||||
io_write_32(DBSC_DBSCHQOS142, 0x00000080);
|
||||
io_write_32(DBSC_DBSCHQOS143, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS150, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS151, 0x00000030);
|
||||
io_write_32(DBSC_DBSCHQOS152, 0x00000020);
|
||||
io_write_32(DBSC_DBSCHQOS153, 0x00000010);
|
||||
|
||||
/* Register write protect */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
|
||||
}
|
||||
{ DBSC_DBSCHQOS00, 0x00000F00 },
|
||||
{ DBSC_DBSCHQOS01, 0x00000B00 },
|
||||
{ DBSC_DBSCHQOS02, 0x00000000 },
|
||||
{ DBSC_DBSCHQOS03, 0x00000000 },
|
||||
{ DBSC_DBSCHQOS40, 0x00000300 },
|
||||
{ DBSC_DBSCHQOS41, 0x000002F0 },
|
||||
{ DBSC_DBSCHQOS42, 0x00000200 },
|
||||
{ DBSC_DBSCHQOS43, 0x00000100 },
|
||||
{ DBSC_DBSCHQOS90, 0x00000100 },
|
||||
{ DBSC_DBSCHQOS91, 0x000000F0 },
|
||||
{ DBSC_DBSCHQOS92, 0x000000A0 },
|
||||
{ DBSC_DBSCHQOS93, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS130, 0x00000100 },
|
||||
{ DBSC_DBSCHQOS131, 0x000000F0 },
|
||||
{ DBSC_DBSCHQOS132, 0x000000A0 },
|
||||
{ DBSC_DBSCHQOS133, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS140, 0x000000C0 },
|
||||
{ DBSC_DBSCHQOS141, 0x000000B0 },
|
||||
{ DBSC_DBSCHQOS142, 0x00000080 },
|
||||
{ DBSC_DBSCHQOS143, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS150, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS151, 0x00000030 },
|
||||
{ DBSC_DBSCHQOS152, 0x00000020 },
|
||||
{ DBSC_DBSCHQOS153, 0x00000010 },
|
||||
};
|
||||
|
||||
void qos_init_e3_v10(void)
|
||||
{
|
||||
dbsc_setting();
|
||||
rcar_qos_dbsc_setting(e3_qos, ARRAY_SIZE(e3_qos), true);
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
|
||||
|
|
@ -121,17 +111,16 @@ void qos_init_e3_v10(void)
|
|||
SL_INIT_SSLOTCLK_E3);
|
||||
io_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_E3);
|
||||
|
||||
{
|
||||
uint32_t i;
|
||||
/* QOSBW SRAM setting */
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
|
||||
/* RT bus Leaf setting */
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
|
||||
#include "../qos_common.h"
|
||||
#include "../qos_reg.h"
|
||||
#include "qos_init_h3_v10.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.36"
|
||||
|
||||
#include "qos_init_h3_v10_mstat.h"
|
||||
|
||||
void qos_init_h3_v10(void)
|
||||
{
|
||||
/* DRAM Split Address mapping */
|
||||
#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
|
||||
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
|
||||
NOTICE("BL2: DRAM Split is 4ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1BU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR1, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
|
||||
NOTICE("BL2: DRAM Split is 2ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1BU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR2, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#else
|
||||
NOTICE("BL2: DRAM Split is OFF\n");
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
/* AR Cache setting */
|
||||
io_write_32(0xE67D1000U, 0x00000100U);
|
||||
io_write_32(0xE67D1008U, 0x00000100U);
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(QOSCTRL_RAS, 0x00000040U);
|
||||
io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
|
||||
io_write_32(QOSCTRL_REGGD, 0x00000004U);
|
||||
io_write_64(QOSCTRL_DANN, 0x0202000004040404UL);
|
||||
io_write_32(QOSCTRL_DANT, 0x003C1110U);
|
||||
io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */
|
||||
io_write_64(QOSCTRL_EMS, 0x0000000000000000UL);
|
||||
io_write_32(QOSCTRL_INSFC, 0xC7840001U);
|
||||
io_write_32(QOSCTRL_BERR, 0x00000000U);
|
||||
|
||||
/* QOSBW setting */
|
||||
io_write_32(QOSCTRL_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
|
||||
io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
|
||||
|
||||
/* QOSBW SRAM setting */
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
io_write_32(0xFD820808U, 0x00001234U);
|
||||
io_write_32(0xFD820800U, 0x0000003FU);
|
||||
io_write_32(0xFD821800U, 0x0000003FU);
|
||||
io_write_32(0xFD822800U, 0x0000003FU);
|
||||
io_write_32(0xFD823800U, 0x0000003FU);
|
||||
io_write_32(0xFD824800U, 0x0000003FU);
|
||||
io_write_32(0xFD825800U, 0x0000003FU);
|
||||
io_write_32(0xFD826800U, 0x0000003FU);
|
||||
io_write_32(0xFD827800U, 0x0000003FU);
|
||||
|
||||
/* Resource Alloc start */
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
|
||||
/* QOSBW start */
|
||||
io_write_32(QOSCTRL_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
||||
|
|
@ -0,0 +1,221 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
static const uint64_t mstat_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x00140C050000FFFFUL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x001404030000FFFFUL,
|
||||
/* 0x0060, */ 0x001408060000FFFFUL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x00140C050000FFFFUL,
|
||||
/* 0x0090, */ 0x001408060000FFFFUL,
|
||||
/* 0x0098, */ 0x001404020000FFFFUL,
|
||||
/* 0x00A0, */ 0x0000000000000000UL,
|
||||
/* 0x00A8, */ 0x0000000000000000UL,
|
||||
/* 0x00B0, */ 0x0000000000000000UL,
|
||||
/* 0x00B8, */ 0x0000000000000000UL,
|
||||
/* 0x00C0, */ 0x0000000000000000UL,
|
||||
/* 0x00C8, */ 0x0000000000000000UL,
|
||||
/* 0x00D0, */ 0x0000000000000000UL,
|
||||
/* 0x00D8, */ 0x0000000000000000UL,
|
||||
/* 0x00E0, */ 0x0000000000000000UL,
|
||||
/* 0x00E8, */ 0x0000000000000000UL,
|
||||
/* 0x00F0, */ 0x0000000000000000UL,
|
||||
/* 0x00F8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x001004020000FFFFUL,
|
||||
/* 0x0140, */ 0x001004020000FFFFUL,
|
||||
/* 0x0148, */ 0x001004020000FFFFUL,
|
||||
/* 0x0150, */ 0x001008050000FFFFUL,
|
||||
/* 0x0158, */ 0x001008050000FFFFUL,
|
||||
/* 0x0160, */ 0x001008050000FFFFUL,
|
||||
/* 0x0168, */ 0x001008050000FFFFUL,
|
||||
/* 0x0170, */ 0x001008050000FFFFUL,
|
||||
/* 0x0178, */ 0x001004030000FFFFUL,
|
||||
/* 0x0180, */ 0x001004030000FFFFUL,
|
||||
/* 0x0188, */ 0x001004030000FFFFUL,
|
||||
/* 0x0190, */ 0x001014140000FFFFUL,
|
||||
/* 0x0198, */ 0x001014140000FFFFUL,
|
||||
/* 0x01A0, */ 0x001008060000FFFFUL,
|
||||
/* 0x01A8, */ 0x001008060000FFFFUL,
|
||||
/* 0x01B0, */ 0x001008060000FFFFUL,
|
||||
/* 0x01B8, */ 0x0000000000000000UL,
|
||||
/* 0x01C0, */ 0x0000000000000000UL,
|
||||
/* 0x01C8, */ 0x0000000000000000UL,
|
||||
/* 0x01D0, */ 0x0000000000000000UL,
|
||||
/* 0x01D8, */ 0x0000000000000000UL,
|
||||
/* 0x01E0, */ 0x0000000000000000UL,
|
||||
/* 0x01E8, */ 0x0000000000000000UL,
|
||||
/* 0x01F0, */ 0x0000000000000000UL,
|
||||
/* 0x01F8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02A0, */ 0x0000000000000000UL,
|
||||
/* 0x02A8, */ 0x0000000000000000UL,
|
||||
/* 0x02B0, */ 0x0000000000000000UL,
|
||||
/* 0x02B8, */ 0x0000000000000000UL,
|
||||
/* 0x02C0, */ 0x0000000000000000UL,
|
||||
/* 0x02C8, */ 0x0000000000000000UL,
|
||||
/* 0x02D0, */ 0x0000000000000000UL,
|
||||
/* 0x02D8, */ 0x0000000000000000UL,
|
||||
/* 0x02E0, */ 0x0000000000000000UL,
|
||||
/* 0x02E8, */ 0x0000000000000000UL,
|
||||
/* 0x02F0, */ 0x0000000000000000UL,
|
||||
/* 0x02F8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static const uint64_t mstat_be[] = {
|
||||
/* 0x0000, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0008, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0010, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0018, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0020, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0028, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0030, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0038, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0070, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0078, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0080, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00A0, */ 0x001000100C8FFC01UL,
|
||||
/* 0x00A8, */ 0x001000100C8FFC01UL,
|
||||
/* 0x00B0, */ 0x001000100C8FFC01UL,
|
||||
/* 0x00B8, */ 0x001000100C8FFC01UL,
|
||||
/* 0x00C0, */ 0x001000100C8FFC01UL,
|
||||
/* 0x00C8, */ 0x001000100C8FFC01UL,
|
||||
/* 0x00D0, */ 0x001000100C8FFC01UL,
|
||||
/* 0x00D8, */ 0x002000200C8FFC01UL,
|
||||
/* 0x00E0, */ 0x002000200C8FFC01UL,
|
||||
/* 0x00E8, */ 0x001000100C8FFC01UL,
|
||||
/* 0x00F0, */ 0x001000100C8FFC01UL,
|
||||
/* 0x00F8, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x002000200C8FFC01UL,
|
||||
/* 0x0110, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0118, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x002000200C8FFC01UL,
|
||||
/* 0x0130, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01A0, */ 0x0000000000000000UL,
|
||||
/* 0x01A8, */ 0x0000000000000000UL,
|
||||
/* 0x01B0, */ 0x0000000000000000UL,
|
||||
/* 0x01B8, */ 0x001000100C8FFC01UL,
|
||||
/* 0x01C0, */ 0x001000200C8FFC01UL,
|
||||
/* 0x01C8, */ 0x001000200C8FFC01UL,
|
||||
/* 0x01D0, */ 0x001000200C8FFC01UL,
|
||||
/* 0x01D8, */ 0x001000200C8FFC01UL,
|
||||
/* 0x01E0, */ 0x001000100C8FFC01UL,
|
||||
/* 0x01E8, */ 0x001000100C8FFC01UL,
|
||||
/* 0x01F0, */ 0x001000100C8FFC01UL,
|
||||
/* 0x01F8, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0200, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0208, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0210, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0218, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0220, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0228, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0230, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0238, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0240, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0248, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0250, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0258, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0260, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0268, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0270, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0278, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0280, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0288, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0290, */ 0x001000100C8FFC01UL,
|
||||
/* 0x0298, */ 0x001000100C8FFC01UL,
|
||||
/* 0x02A0, */ 0x001000100C8FFC01UL,
|
||||
/* 0x02A8, */ 0x001000100C8FFC01UL,
|
||||
/* 0x02B0, */ 0x001000100C8FFC01UL,
|
||||
/* 0x02B8, */ 0x001000100C8FFC01UL,
|
||||
/* 0x02C0, */ 0x001000100C8FFC01UL,
|
||||
/* 0x02C8, */ 0x001000100C8FFC01UL,
|
||||
/* 0x02D0, */ 0x001000100C8FFC01UL,
|
||||
/* 0x02D8, */ 0x001000100C8FFC01UL,
|
||||
/* 0x02E0, */ 0x001000100C8FFC01UL,
|
||||
/* 0x02E8, */ 0x001000100C8FFC01UL,
|
||||
/* 0x02F0, */ 0x001000200C8FFC01UL,
|
||||
/* 0x02F8, */ 0x001000300C8FFC01UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x001000200C8FFC01UL,
|
||||
/* 0x0310, */ 0x001000300C8FFC01UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x001000200C8FFC01UL,
|
||||
/* 0x0328, */ 0x001000300C8FFC01UL,
|
||||
/* 0x0330, */ 0x001000200C8FFC01UL,
|
||||
/* 0x0338, */ 0x001000300C8FFC01UL,
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
|
||||
#include <rcar_def.h>
|
||||
|
||||
#include "../qos_common.h"
|
||||
#include "../qos_reg.h"
|
||||
#include "qos_init_h3_v11.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.37"
|
||||
|
||||
#include "qos_init_h3_v11_mstat.h"
|
||||
|
||||
struct rcar_gen3_dbsc_qos_settings h3_v11_qos[] = {
|
||||
/* BUFCAM settings */
|
||||
/* DBSC_DBCAM0CNF0 not set */
|
||||
{ DBSC_DBCAM0CNF1, 0x00044218 },
|
||||
{ DBSC_DBCAM0CNF2, 0x000000F4 },
|
||||
/* DBSC_DBCAM0CNF3 not set */
|
||||
{ DBSC_DBSCHCNT0, 0x080F0037 },
|
||||
{ DBSC_DBSCHCNT1, 0x00001010 },
|
||||
{ DBSC_DBSCHSZ0, 0x00000001 },
|
||||
{ DBSC_DBSCHRW0, 0x22421111 },
|
||||
|
||||
/* DDR3 */
|
||||
{ DBSC_SCFCTST2, 0x012F1123 },
|
||||
|
||||
/* QoS Settings */
|
||||
{ DBSC_DBSCHQOS00, 0x0000F000 },
|
||||
{ DBSC_DBSCHQOS01, 0x0000E000 },
|
||||
{ DBSC_DBSCHQOS02, 0x00007000 },
|
||||
{ DBSC_DBSCHQOS03, 0x00000000 },
|
||||
{ DBSC_DBSCHQOS40, 0x00000E00 },
|
||||
{ DBSC_DBSCHQOS41, 0x00000DFF },
|
||||
{ DBSC_DBSCHQOS42, 0x00000400 },
|
||||
{ DBSC_DBSCHQOS43, 0x00000200 },
|
||||
{ DBSC_DBSCHQOS90, 0x00000C00 },
|
||||
{ DBSC_DBSCHQOS91, 0x00000BFF },
|
||||
{ DBSC_DBSCHQOS92, 0x00000400 },
|
||||
{ DBSC_DBSCHQOS93, 0x00000200 },
|
||||
{ DBSC_DBSCHQOS130, 0x00000980 },
|
||||
{ DBSC_DBSCHQOS131, 0x0000097F },
|
||||
{ DBSC_DBSCHQOS132, 0x00000300 },
|
||||
{ DBSC_DBSCHQOS133, 0x00000180 },
|
||||
{ DBSC_DBSCHQOS140, 0x00000800 },
|
||||
{ DBSC_DBSCHQOS141, 0x000007FF },
|
||||
{ DBSC_DBSCHQOS142, 0x00000300 },
|
||||
{ DBSC_DBSCHQOS143, 0x00000180 },
|
||||
{ DBSC_DBSCHQOS150, 0x000007D0 },
|
||||
{ DBSC_DBSCHQOS151, 0x000007CF },
|
||||
{ DBSC_DBSCHQOS152, 0x000005D0 },
|
||||
{ DBSC_DBSCHQOS153, 0x000003D0 },
|
||||
};
|
||||
|
||||
void qos_init_h3_v11(void)
|
||||
{
|
||||
rcar_qos_dbsc_setting(h3_v11_qos, ARRAY_SIZE(h3_v11_qos), false);
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
|
||||
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
|
||||
NOTICE("BL2: DRAM Split is 4ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1BU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR1, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
|
||||
NOTICE("BL2: DRAM Split is 2ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1BU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR2, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#else
|
||||
NOTICE("BL2: DRAM Split is OFF\n");
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
/* AR Cache setting */
|
||||
io_write_32(0xE67D1000U, 0x00000100U);
|
||||
io_write_32(0xE67D1008U, 0x00000100U);
|
||||
|
||||
/* Resource Alloc setting */
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
|
||||
io_write_32(QOSCTRL_RAS, 0x00000020U);
|
||||
#else
|
||||
io_write_32(QOSCTRL_RAS, 0x00000040U);
|
||||
#endif
|
||||
io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
|
||||
io_write_32(QOSCTRL_REGGD, 0x00000000U);
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
|
||||
io_write_64(QOSCTRL_DANN, 0x0101010102020201UL);
|
||||
io_write_32(QOSCTRL_DANT, 0x00181008U);
|
||||
#else
|
||||
io_write_64(QOSCTRL_DANN, 0x0101000004040401UL);
|
||||
io_write_32(QOSCTRL_DANT, 0x003C2010U);
|
||||
#endif
|
||||
io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */
|
||||
io_write_64(QOSCTRL_EMS, 0x0000000000000000UL);
|
||||
io_write_32(QOSCTRL_INSFC, 0xC7840001U);
|
||||
io_write_32(QOSCTRL_BERR, 0x00000000U);
|
||||
io_write_32(QOSCTRL_RACNT0, 0x00000000U);
|
||||
|
||||
/* QOSBW setting */
|
||||
io_write_32(QOSCTRL_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
|
||||
io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
|
||||
|
||||
/* QOSBW SRAM setting */
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
io_write_32(0xFD820808U, 0x00001234U);
|
||||
io_write_32(0xFD820800U, 0x0000003FU);
|
||||
io_write_32(0xFD821800U, 0x0000003FU);
|
||||
io_write_32(0xFD822800U, 0x0000003FU);
|
||||
io_write_32(0xFD823800U, 0x0000003FU);
|
||||
io_write_32(0xFD824800U, 0x0000003FU);
|
||||
io_write_32(0xFD825800U, 0x0000003FU);
|
||||
io_write_32(0xFD826800U, 0x0000003FU);
|
||||
io_write_32(0xFD827800U, 0x0000003FU);
|
||||
|
||||
/* VIO bus Leaf setting */
|
||||
io_write_32(0xFEB89800, 0x00000001U);
|
||||
io_write_32(0xFEB8A800, 0x00000001U);
|
||||
io_write_32(0xFEB8B800, 0x00000001U);
|
||||
io_write_32(0xFEB8C800, 0x00000001U);
|
||||
|
||||
/* HSC bus Leaf setting */
|
||||
io_write_32(0xE6430800, 0x00000001U);
|
||||
io_write_32(0xE6431800, 0x00000001U);
|
||||
io_write_32(0xE6432800, 0x00000001U);
|
||||
io_write_32(0xE6433800, 0x00000001U);
|
||||
|
||||
/* MP bus Leaf setting */
|
||||
io_write_32(0xEC620800, 0x00000001U);
|
||||
io_write_32(0xEC621800, 0x00000001U);
|
||||
|
||||
/* PERIE bus Leaf setting */
|
||||
io_write_32(0xE7760800, 0x00000001U);
|
||||
io_write_32(0xE7768800, 0x00000001U);
|
||||
|
||||
/* PERIW bus Leaf setting */
|
||||
io_write_32(0xE6760800, 0x00000001U);
|
||||
io_write_32(0xE6768800, 0x00000001U);
|
||||
|
||||
/* RT bus Leaf setting */
|
||||
io_write_32(0xFFC50800, 0x00000001U);
|
||||
io_write_32(0xFFC51800, 0x00000001U);
|
||||
|
||||
/* CCI bus Leaf setting */
|
||||
uint32_t modemr = io_read_32(RCAR_MODEMR);
|
||||
|
||||
modemr &= MODEMR_BOOT_CPU_MASK;
|
||||
|
||||
if ((modemr == MODEMR_BOOT_CPU_CA57) ||
|
||||
(modemr == MODEMR_BOOT_CPU_CA53)) {
|
||||
io_write_32(0xF1300800, 0x00000001U);
|
||||
io_write_32(0xF1340800, 0x00000001U);
|
||||
io_write_32(0xF1380800, 0x00000001U);
|
||||
io_write_32(0xF13C0800, 0x00000001U);
|
||||
}
|
||||
|
||||
/* Resource Alloc start */
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
|
||||
/* QOSBW start */
|
||||
io_write_32(QOSCTRL_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
||||
|
|
@ -0,0 +1,221 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
static const uint64_t mstat_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001004030000FFFFUL,
|
||||
/* 0x0038, */ 0x001008060000FFFFUL,
|
||||
/* 0x0040, */ 0x001414090000FFFFUL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x001410010000FFFFUL,
|
||||
/* 0x0058, */ 0x00140C0C0000FFFFUL,
|
||||
/* 0x0060, */ 0x00140C0C0000FFFFUL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x001410010000FFFFUL,
|
||||
/* 0x0078, */ 0x001008060000FFFFUL,
|
||||
/* 0x0080, */ 0x001004020000FFFFUL,
|
||||
/* 0x0088, */ 0x001414090000FFFFUL,
|
||||
/* 0x0090, */ 0x00140C0C0000FFFFUL,
|
||||
/* 0x0098, */ 0x001408080000FFFFUL,
|
||||
/* 0x00A0, */ 0x000C08020000FFFFUL,
|
||||
/* 0x00A8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00B0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00B8, */ 0x0000000000000000UL,
|
||||
/* 0x00C0, */ 0x000C08020000FFFFUL,
|
||||
/* 0x00C8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00D0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00D8, */ 0x000C04030000FFFFUL,
|
||||
/* 0x00E0, */ 0x000C100F0000FFFFUL,
|
||||
/* 0x00E8, */ 0x0000000000000000UL,
|
||||
/* 0x00F0, */ 0x001010080000FFFFUL,
|
||||
/* 0x00F8, */ 0x001010080000FFFFUL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x000C04030000FFFFUL,
|
||||
/* 0x0110, */ 0x001010080000FFFFUL,
|
||||
/* 0x0118, */ 0x001010080000FFFFUL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x000C100E0000FFFFUL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x001008050000FFFFUL,
|
||||
/* 0x0140, */ 0x001008050000FFFFUL,
|
||||
/* 0x0148, */ 0x001008050000FFFFUL,
|
||||
/* 0x0150, */ 0x001008050000FFFFUL,
|
||||
/* 0x0158, */ 0x001008050000FFFFUL,
|
||||
/* 0x0160, */ 0x001008050000FFFFUL,
|
||||
/* 0x0168, */ 0x001008050000FFFFUL,
|
||||
/* 0x0170, */ 0x001008050000FFFFUL,
|
||||
/* 0x0178, */ 0x001004030000FFFFUL,
|
||||
/* 0x0180, */ 0x001004030000FFFFUL,
|
||||
/* 0x0188, */ 0x001004030000FFFFUL,
|
||||
/* 0x0190, */ 0x001014140000FFFFUL,
|
||||
/* 0x0198, */ 0x001014140000FFFFUL,
|
||||
/* 0x01A0, */ 0x001008050000FFFFUL,
|
||||
/* 0x01A8, */ 0x001008050000FFFFUL,
|
||||
/* 0x01B0, */ 0x001008050000FFFFUL,
|
||||
/* 0x01B8, */ 0x0000000000000000UL,
|
||||
/* 0x01C0, */ 0x0000000000000000UL,
|
||||
/* 0x01C8, */ 0x0000000000000000UL,
|
||||
/* 0x01D0, */ 0x0000000000000000UL,
|
||||
/* 0x01D8, */ 0x0000000000000000UL,
|
||||
/* 0x01E0, */ 0x0000000000000000UL,
|
||||
/* 0x01E8, */ 0x0000000000000000UL,
|
||||
/* 0x01F0, */ 0x0000000000000000UL,
|
||||
/* 0x01F8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x001408010000FFFFUL,
|
||||
/* 0x0270, */ 0x001404010000FFFFUL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001408010000FFFFUL,
|
||||
/* 0x0298, */ 0x001404010000FFFFUL,
|
||||
/* 0x02A0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02A8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02B0, */ 0x001404010000FFFFUL,
|
||||
/* 0x02B8, */ 0x0000000000000000UL,
|
||||
/* 0x02C0, */ 0x0000000000000000UL,
|
||||
/* 0x02C8, */ 0x0000000000000000UL,
|
||||
/* 0x02D0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02D8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02E0, */ 0x001404010000FFFFUL,
|
||||
/* 0x02E8, */ 0x0000000000000000UL,
|
||||
/* 0x02F0, */ 0x0000000000000000UL,
|
||||
/* 0x02F8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static const uint64_t mstat_be[] = {
|
||||
/* 0x0000, */ 0x001200100C89C401UL,
|
||||
/* 0x0008, */ 0x001200100C89C401UL,
|
||||
/* 0x0010, */ 0x001200100C89C401UL,
|
||||
/* 0x0018, */ 0x001200100C89C401UL,
|
||||
/* 0x0020, */ 0x001100100C803401UL,
|
||||
/* 0x0028, */ 0x001100100C80FC01UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x001100100C803401UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00A0, */ 0x0000000000000000UL,
|
||||
/* 0x00A8, */ 0x0000000000000000UL,
|
||||
/* 0x00B0, */ 0x0000000000000000UL,
|
||||
/* 0x00B8, */ 0x001100100C803401UL,
|
||||
/* 0x00C0, */ 0x0000000000000000UL,
|
||||
/* 0x00C8, */ 0x0000000000000000UL,
|
||||
/* 0x00D0, */ 0x0000000000000000UL,
|
||||
/* 0x00D8, */ 0x0000000000000000UL,
|
||||
/* 0x00E0, */ 0x0000000000000000UL,
|
||||
/* 0x00E8, */ 0x001100100C803401UL,
|
||||
/* 0x00F0, */ 0x0000000000000000UL,
|
||||
/* 0x00F8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x001100100C803401UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01A0, */ 0x0000000000000000UL,
|
||||
/* 0x01A8, */ 0x0000000000000000UL,
|
||||
/* 0x01B0, */ 0x0000000000000000UL,
|
||||
/* 0x01B8, */ 0x001100100C803401UL,
|
||||
/* 0x01C0, */ 0x001100800C8FFC01UL,
|
||||
/* 0x01C8, */ 0x001100800C8FFC01UL,
|
||||
/* 0x01D0, */ 0x001100800C8FFC01UL,
|
||||
/* 0x01D8, */ 0x001100800C8FFC01UL,
|
||||
/* 0x01E0, */ 0x001100100C80FC01UL,
|
||||
/* 0x01E8, */ 0x001200100C80FC01UL,
|
||||
/* 0x01F0, */ 0x001100100C80FC01UL,
|
||||
/* 0x01F8, */ 0x001100100C803401UL,
|
||||
/* 0x0200, */ 0x001100100C80FC01UL,
|
||||
/* 0x0208, */ 0x001200100C80FC01UL,
|
||||
/* 0x0210, */ 0x001100100C80FC01UL,
|
||||
/* 0x0218, */ 0x001100100C825801UL,
|
||||
/* 0x0220, */ 0x001100100C825801UL,
|
||||
/* 0x0228, */ 0x001100100C803401UL,
|
||||
/* 0x0230, */ 0x001100100C825801UL,
|
||||
/* 0x0238, */ 0x001100100C825801UL,
|
||||
/* 0x0240, */ 0x001200100C8BB801UL,
|
||||
/* 0x0248, */ 0x001100200C8FFC01UL,
|
||||
/* 0x0250, */ 0x001200100C8BB801UL,
|
||||
/* 0x0258, */ 0x001100200C8FFC01UL,
|
||||
/* 0x0260, */ 0x001100100C84E401UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x001100100C81F401UL,
|
||||
/* 0x0280, */ 0x001100100C803401UL,
|
||||
/* 0x0288, */ 0x001100100C803401UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02A0, */ 0x0000000000000000UL,
|
||||
/* 0x02A8, */ 0x0000000000000000UL,
|
||||
/* 0x02B0, */ 0x0000000000000000UL,
|
||||
/* 0x02B8, */ 0x001100100C803401UL,
|
||||
/* 0x02C0, */ 0x001100100C803401UL,
|
||||
/* 0x02C8, */ 0x001100100C803401UL,
|
||||
/* 0x02D0, */ 0x0000000000000000UL,
|
||||
/* 0x02D8, */ 0x0000000000000000UL,
|
||||
/* 0x02E0, */ 0x0000000000000000UL,
|
||||
/* 0x02E8, */ 0x001100100C803401UL,
|
||||
/* 0x02F0, */ 0x001100300C8FFC01UL,
|
||||
/* 0x02F8, */ 0x001100500C8FFC01UL,
|
||||
/* 0x0300, */ 0x001100100C803401UL,
|
||||
/* 0x0308, */ 0x001100300C8FFC01UL,
|
||||
/* 0x0310, */ 0x001100500C8FFC01UL,
|
||||
/* 0x0318, */ 0x001200100C803401UL,
|
||||
/* 0x0320, */ 0x001100300C8FFC01UL,
|
||||
/* 0x0328, */ 0x001100500C8FFC01UL,
|
||||
/* 0x0330, */ 0x001100300C8FFC01UL,
|
||||
/* 0x0338, */ 0x001100500C8FFC01UL,
|
||||
};
|
||||
#endif
|
||||
|
|
@ -12,29 +12,34 @@
|
|||
#include "../qos_reg.h"
|
||||
#include "qos_init_h3_v20.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.21"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.21"
|
||||
#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
|
||||
|
||||
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
|
||||
|
||||
#define QOSWT_WTEN_ENABLE (0x1U)
|
||||
#define QOSWT_WTEN_ENABLE 0x1U
|
||||
|
||||
#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_20 (SL_INIT_SSLOTCLK_H3_20 - 0x5U)
|
||||
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
|
||||
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
|
||||
#define QOSWT_WTREF_SLOT0_EN \
|
||||
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
|
||||
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define QOSWT_WTREF_SLOT1_EN \
|
||||
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
|
||||
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
|
||||
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
|
||||
#define WT_BASE_SUB_SLOT_NUM0 (12U)
|
||||
#define QOSWT_WTSET0_PERIOD0_H3_20 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3_20)-1U)
|
||||
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
|
||||
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
|
||||
#define QOSWT_WTSET0_REQ_SSLOT0 5U
|
||||
#define WT_BASE_SUB_SLOT_NUM0 12U
|
||||
#define QOSWT_WTSET0_PERIOD0_H3_20 \
|
||||
((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3_20) - 1U)
|
||||
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
|
||||
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
|
||||
|
||||
#define QOSWT_WTSET1_PERIOD1_H3_20 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3_20)-1U)
|
||||
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
|
||||
#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 -1U)
|
||||
#define QOSWT_WTSET1_PERIOD1_H3_20 \
|
||||
((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3_20) - 1U)
|
||||
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
|
||||
#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 - 1U)
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
|
||||
|
|
@ -56,79 +61,52 @@
|
|||
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
uint32_t md = 0;
|
||||
|
||||
/* Register write enable */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
|
||||
|
||||
struct rcar_gen3_dbsc_qos_settings h3_v20_qos[] = {
|
||||
/* BUFCAM settings */
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00043218U); /* dbcam0cnf1 */
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U); /* dbcam0cnf2 */
|
||||
io_write_32(DBSC_DBCAM0CNF3, 0x00000000U); /* dbcam0cnf3 */
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x000F0037U); /* dbschcnt0 */
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001U); /* dbschsz0 */
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111U); /* dbschrw0 */
|
||||
{ DBSC_DBCAM0CNF1, 0x00043218U },
|
||||
{ DBSC_DBCAM0CNF2, 0x000000F4U },
|
||||
{ DBSC_DBCAM0CNF3, 0x00000000U },
|
||||
{ DBSC_DBSCHCNT0, 0x000F0037U },
|
||||
{ DBSC_DBSCHSZ0, 0x00000001U },
|
||||
{ DBSC_DBSCHRW0, 0x22421111U },
|
||||
|
||||
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
|
||||
|
||||
switch (md) {
|
||||
case 0x0:
|
||||
/* DDR3200 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
|
||||
/* DDR2800 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
|
||||
/* DDR2400 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
|
||||
/* DDR1600 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
}
|
||||
/* DDR3 */
|
||||
{ DBSC_SCFCTST2, 0x012F1123U },
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
|
||||
io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
|
||||
io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
|
||||
io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
|
||||
io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
|
||||
io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
|
||||
io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
|
||||
io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
|
||||
io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
|
||||
io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
|
||||
io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
|
||||
io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
|
||||
io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
|
||||
io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
|
||||
io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
|
||||
io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
|
||||
io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
|
||||
io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
|
||||
io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
|
||||
io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
|
||||
|
||||
/* Register write protect */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
|
||||
}
|
||||
{ DBSC_DBSCHQOS00, 0x00000F00U },
|
||||
{ DBSC_DBSCHQOS01, 0x00000B00U },
|
||||
{ DBSC_DBSCHQOS02, 0x00000000U },
|
||||
{ DBSC_DBSCHQOS03, 0x00000000U },
|
||||
{ DBSC_DBSCHQOS40, 0x00000300U },
|
||||
{ DBSC_DBSCHQOS41, 0x000002F0U },
|
||||
{ DBSC_DBSCHQOS42, 0x00000200U },
|
||||
{ DBSC_DBSCHQOS43, 0x00000100U },
|
||||
{ DBSC_DBSCHQOS90, 0x00000100U },
|
||||
{ DBSC_DBSCHQOS91, 0x000000F0U },
|
||||
{ DBSC_DBSCHQOS92, 0x000000A0U },
|
||||
{ DBSC_DBSCHQOS93, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS120, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS121, 0x00000030U },
|
||||
{ DBSC_DBSCHQOS122, 0x00000020U },
|
||||
{ DBSC_DBSCHQOS123, 0x00000010U },
|
||||
{ DBSC_DBSCHQOS130, 0x00000100U },
|
||||
{ DBSC_DBSCHQOS131, 0x000000F0U },
|
||||
{ DBSC_DBSCHQOS132, 0x000000A0U },
|
||||
{ DBSC_DBSCHQOS133, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS140, 0x000000C0U },
|
||||
{ DBSC_DBSCHQOS141, 0x000000B0U },
|
||||
{ DBSC_DBSCHQOS142, 0x00000080U },
|
||||
{ DBSC_DBSCHQOS143, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS150, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS151, 0x00000030U },
|
||||
{ DBSC_DBSCHQOS152, 0x00000020U },
|
||||
{ DBSC_DBSCHQOS153, 0x00000010U },
|
||||
};
|
||||
|
||||
void qos_init_h3_v20(void)
|
||||
{
|
||||
dbsc_setting();
|
||||
rcar_qos_dbsc_setting(h3_v20_qos, ARRAY_SIZE(h3_v20_qos), true);
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
|
||||
|
|
@ -188,30 +166,28 @@ void qos_init_h3_v20(void)
|
|||
io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
io_write_32(GPU_ACT0, 0x00000000U);
|
||||
|
|
@ -12,30 +12,32 @@
|
|||
#include "../qos_reg.h"
|
||||
#include "qos_init_h3_v30.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.11"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.11"
|
||||
#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
|
||||
|
||||
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
|
||||
|
||||
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
|
||||
|
||||
#define QOSWT_WTEN_ENABLE (0x1U)
|
||||
#define QOSWT_WTEN_ENABLE 0x1U
|
||||
|
||||
#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_30 (SL_INIT_SSLOTCLK_H3_30 - 0x5U)
|
||||
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
|
||||
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
|
||||
#define QOSWT_WTREF_SLOT0_EN \
|
||||
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
|
||||
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define QOSWT_WTREF_SLOT1_EN \
|
||||
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
|
||||
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
|
||||
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
|
||||
#define WT_BASE_SUB_SLOT_NUM0 (12U)
|
||||
#define QOSWT_WTSET0_PERIOD0_H3_30 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3_30)-1U)
|
||||
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
|
||||
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
|
||||
#define QOSWT_WTSET0_REQ_SSLOT0 5U
|
||||
#define WT_BASE_SUB_SLOT_NUM0 12U
|
||||
#define QOSWT_WTSET0_PERIOD0_H3_30 \
|
||||
((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3_30) - 1U)
|
||||
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
|
||||
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
|
||||
|
||||
#define QOSWT_WTSET1_PERIOD1_H3_30 (QOSWT_WTSET0_PERIOD0_H3_30)
|
||||
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0)
|
||||
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0)
|
||||
#define QOSWT_WTSET1_SLOTSLOT1 (QOSWT_WTSET0_SLOTSLOT0)
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
|
|
@ -58,80 +60,54 @@
|
|||
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
uint32_t md = 0;
|
||||
|
||||
/* Register write enable */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
|
||||
|
||||
struct rcar_gen3_dbsc_qos_settings h3_v30_qos[] = {
|
||||
/* BUFCAM settings */
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00043218U); /* dbcam0cnf1 */
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U); /* dbcam0cnf2 */
|
||||
io_write_32(DBSC_DBCAM0CNF3, 0x00000000U); /* dbcam0cnf3 */
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x000F0037U); /* dbschcnt0 */
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001U); /* dbschsz0 */
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111U); /* dbschrw0 */
|
||||
{ DBSC_DBCAM0CNF1, 0x00043218U },
|
||||
{ DBSC_DBCAM0CNF2, 0x000000F4U },
|
||||
{ DBSC_DBCAM0CNF3, 0x00000000U },
|
||||
{ DBSC_DBSCHCNT0, 0x000F0037U },
|
||||
{ DBSC_DBSCHSZ0, 0x00000001U },
|
||||
{ DBSC_DBSCHRW0, 0x22421111U },
|
||||
|
||||
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
|
||||
|
||||
switch (md) {
|
||||
case 0x0:
|
||||
/* DDR3200 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
|
||||
/* DDR2800 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
|
||||
/* DDR2400 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
|
||||
/* DDR1600 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
}
|
||||
/* DDR3 */
|
||||
{ DBSC_SCFCTST2, 0x012F1123U },
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
|
||||
io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
|
||||
io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
|
||||
io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
|
||||
io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
|
||||
io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
|
||||
io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
|
||||
io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
|
||||
io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
|
||||
io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
|
||||
io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
|
||||
io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
|
||||
io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
|
||||
io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
|
||||
io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
|
||||
io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
|
||||
io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
|
||||
io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
|
||||
io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
|
||||
io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
|
||||
|
||||
/* Register write protect */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
|
||||
}
|
||||
{ DBSC_DBSCHQOS00, 0x00000F00U },
|
||||
{ DBSC_DBSCHQOS01, 0x00000B00U },
|
||||
{ DBSC_DBSCHQOS02, 0x00000000U },
|
||||
{ DBSC_DBSCHQOS03, 0x00000000U },
|
||||
{ DBSC_DBSCHQOS40, 0x00000300U },
|
||||
{ DBSC_DBSCHQOS41, 0x000002F0U },
|
||||
{ DBSC_DBSCHQOS42, 0x00000200U },
|
||||
{ DBSC_DBSCHQOS43, 0x00000100U },
|
||||
{ DBSC_DBSCHQOS90, 0x00000100U },
|
||||
{ DBSC_DBSCHQOS91, 0x000000F0U },
|
||||
{ DBSC_DBSCHQOS92, 0x000000A0U },
|
||||
{ DBSC_DBSCHQOS93, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS120, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS121, 0x00000030U },
|
||||
{ DBSC_DBSCHQOS122, 0x00000020U },
|
||||
{ DBSC_DBSCHQOS123, 0x00000010U },
|
||||
{ DBSC_DBSCHQOS130, 0x00000100U },
|
||||
{ DBSC_DBSCHQOS131, 0x000000F0U },
|
||||
{ DBSC_DBSCHQOS132, 0x000000A0U },
|
||||
{ DBSC_DBSCHQOS133, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS140, 0x000000C0U },
|
||||
{ DBSC_DBSCHQOS141, 0x000000B0U },
|
||||
{ DBSC_DBSCHQOS142, 0x00000080U },
|
||||
{ DBSC_DBSCHQOS143, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS150, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS151, 0x00000030U },
|
||||
{ DBSC_DBSCHQOS152, 0x00000020U },
|
||||
{ DBSC_DBSCHQOS153, 0x00000010U },
|
||||
};
|
||||
|
||||
void qos_init_h3_v30(void)
|
||||
{
|
||||
unsigned int split_area;
|
||||
dbsc_setting();
|
||||
|
||||
rcar_qos_dbsc_setting(h3_v30_qos, ARRAY_SIZE(h3_v30_qos), true);
|
||||
|
||||
#if RCAR_DRAM_LPDDR4_MEMCONF == 0 /* 1GB */
|
||||
split_area = 0x1BU;
|
||||
|
|
@ -197,30 +173,28 @@ void qos_init_h3_v30(void)
|
|||
io_write_32(QOSCTRL_REF_ARS,
|
||||
((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_30 << 16)));
|
||||
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
/* AXI setting */
|
||||
io_write_32(AXI_MMCR, 0x00010008U);
|
||||
|
|
@ -12,30 +12,32 @@
|
|||
#include "../qos_reg.h"
|
||||
#include "qos_init_h3n_v30.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.07"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.07"
|
||||
#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
|
||||
|
||||
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
|
||||
|
||||
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
|
||||
|
||||
#define QOSWT_WTEN_ENABLE (0x1U)
|
||||
#define QOSWT_WTEN_ENABLE 0x1U
|
||||
|
||||
#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N (SL_INIT_SSLOTCLK_H3N - 0x5U)
|
||||
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
|
||||
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
|
||||
#define QOSWT_WTREF_SLOT0_EN \
|
||||
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
|
||||
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define QOSWT_WTREF_SLOT1_EN \
|
||||
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
|
||||
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
|
||||
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
|
||||
#define WT_BASE_SUB_SLOT_NUM0 (12U)
|
||||
#define QOSWT_WTSET0_PERIOD0_H3N ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3N)-1U)
|
||||
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
|
||||
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
|
||||
#define QOSWT_WTSET0_REQ_SSLOT0 5U
|
||||
#define WT_BASE_SUB_SLOT_NUM0 12U
|
||||
#define QOSWT_WTSET0_PERIOD0_H3N \
|
||||
((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3N) - 1U)
|
||||
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
|
||||
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
|
||||
|
||||
#define QOSWT_WTSET1_PERIOD1_H3N (QOSWT_WTSET0_PERIOD0_H3N)
|
||||
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0)
|
||||
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0)
|
||||
#define QOSWT_WTSET1_SLOTSLOT1 (QOSWT_WTSET0_SLOTSLOT0)
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
|
|
@ -58,80 +60,54 @@
|
|||
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
uint32_t md = 0;
|
||||
|
||||
/* Register write enable */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
|
||||
|
||||
struct rcar_gen3_dbsc_qos_settings h3n_v30_qos[] = {
|
||||
/* BUFCAM settings */
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00043218U); /* dbcam0cnf1 */
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U); /* dbcam0cnf2 */
|
||||
io_write_32(DBSC_DBCAM0CNF3, 0x00000000U); /* dbcam0cnf3 */
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x000F0037U); /* dbschcnt0 */
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001U); /* dbschsz0 */
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111U); /* dbschrw0 */
|
||||
{ DBSC_DBCAM0CNF1, 0x00043218U },
|
||||
{ DBSC_DBCAM0CNF2, 0x000000F4U },
|
||||
{ DBSC_DBCAM0CNF3, 0x00000000U },
|
||||
{ DBSC_DBSCHCNT0, 0x000F0037U },
|
||||
{ DBSC_DBSCHSZ0, 0x00000001U },
|
||||
{ DBSC_DBSCHRW0, 0x22421111U },
|
||||
|
||||
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
|
||||
|
||||
switch (md) {
|
||||
case 0x0:
|
||||
/* DDR3200 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
|
||||
/* DDR2800 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
|
||||
/* DDR2400 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
|
||||
/* DDR1600 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
}
|
||||
/* DDR3 */
|
||||
{ DBSC_SCFCTST2, 0x012F1123U },
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
|
||||
io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
|
||||
io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
|
||||
io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
|
||||
io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
|
||||
io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
|
||||
io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
|
||||
io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
|
||||
io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
|
||||
io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
|
||||
io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
|
||||
io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
|
||||
io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
|
||||
io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
|
||||
io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
|
||||
io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
|
||||
io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
|
||||
io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
|
||||
io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
|
||||
io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
|
||||
|
||||
/* Register write protect */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
|
||||
}
|
||||
{ DBSC_DBSCHQOS00, 0x00000F00U },
|
||||
{ DBSC_DBSCHQOS01, 0x00000B00U },
|
||||
{ DBSC_DBSCHQOS02, 0x00000000U },
|
||||
{ DBSC_DBSCHQOS03, 0x00000000U },
|
||||
{ DBSC_DBSCHQOS40, 0x00000300U },
|
||||
{ DBSC_DBSCHQOS41, 0x000002F0U },
|
||||
{ DBSC_DBSCHQOS42, 0x00000200U },
|
||||
{ DBSC_DBSCHQOS43, 0x00000100U },
|
||||
{ DBSC_DBSCHQOS90, 0x00000100U },
|
||||
{ DBSC_DBSCHQOS91, 0x000000F0U },
|
||||
{ DBSC_DBSCHQOS92, 0x000000A0U },
|
||||
{ DBSC_DBSCHQOS93, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS120, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS121, 0x00000030U },
|
||||
{ DBSC_DBSCHQOS122, 0x00000020U },
|
||||
{ DBSC_DBSCHQOS123, 0x00000010U },
|
||||
{ DBSC_DBSCHQOS130, 0x00000100U },
|
||||
{ DBSC_DBSCHQOS131, 0x000000F0U },
|
||||
{ DBSC_DBSCHQOS132, 0x000000A0U },
|
||||
{ DBSC_DBSCHQOS133, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS140, 0x000000C0U },
|
||||
{ DBSC_DBSCHQOS141, 0x000000B0U },
|
||||
{ DBSC_DBSCHQOS142, 0x00000080U },
|
||||
{ DBSC_DBSCHQOS143, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS150, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS151, 0x00000030U },
|
||||
{ DBSC_DBSCHQOS152, 0x00000020U },
|
||||
{ DBSC_DBSCHQOS153, 0x00000010U },
|
||||
};
|
||||
|
||||
void qos_init_h3n_v30(void)
|
||||
{
|
||||
unsigned int split_area;
|
||||
dbsc_setting();
|
||||
|
||||
rcar_qos_dbsc_setting(h3n_v30_qos, ARRAY_SIZE(h3n_v30_qos), true);
|
||||
|
||||
/* use 1(2GB) for RCAR_DRAM_LPDDR4_MEMCONF for H3N */
|
||||
split_area = 0x1CU;
|
||||
|
|
@ -191,30 +167,28 @@ void qos_init_h3n_v30(void)
|
|||
io_write_32(QOSCTRL_REF_ARS,
|
||||
((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N << 16)));
|
||||
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
/* AXI setting */
|
||||
io_write_32(AXI_MMCR, 0x00010008U);
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
|
||||
#include "../qos_common.h"
|
||||
#include "../qos_reg.h"
|
||||
#include "qos_init_m3_v10.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.19"
|
||||
|
||||
#include "qos_init_m3_v10_mstat.h"
|
||||
|
||||
struct rcar_gen3_dbsc_qos_settings m3_v10_qos[] = {
|
||||
/* BUFCAM settings */
|
||||
/* DBSC_DBCAM0CNF0 not set */
|
||||
{ DBSC_DBCAM0CNF1, 0x00043218 },
|
||||
{ DBSC_DBCAM0CNF2, 0x000000F4 },
|
||||
{ DBSC_DBCAM0CNF3, 0x00000000 },
|
||||
{ DBSC_DBSCHCNT0, 0x080F0037 },
|
||||
/* DBSC_DBSCHCNT1 not set */
|
||||
{ DBSC_DBSCHSZ0, 0x00000001 },
|
||||
{ DBSC_DBSCHRW0, 0x22421111 },
|
||||
|
||||
/* DDR3 */
|
||||
{ DBSC_SCFCTST2, 0x012F1123 },
|
||||
|
||||
/* QoS Settings */
|
||||
{ DBSC_DBSCHQOS00, 0x00000F00 },
|
||||
{ DBSC_DBSCHQOS01, 0x00000B00 },
|
||||
{ DBSC_DBSCHQOS02, 0x00000000 },
|
||||
{ DBSC_DBSCHQOS03, 0x00000000 },
|
||||
{ DBSC_DBSCHQOS40, 0x00000300 },
|
||||
{ DBSC_DBSCHQOS41, 0x000002F0 },
|
||||
{ DBSC_DBSCHQOS42, 0x00000200 },
|
||||
{ DBSC_DBSCHQOS43, 0x00000100 },
|
||||
{ DBSC_DBSCHQOS90, 0x00000300 },
|
||||
{ DBSC_DBSCHQOS91, 0x000002F0 },
|
||||
{ DBSC_DBSCHQOS92, 0x00000200 },
|
||||
{ DBSC_DBSCHQOS93, 0x00000100 },
|
||||
{ DBSC_DBSCHQOS130, 0x00000100 },
|
||||
{ DBSC_DBSCHQOS131, 0x000000F0 },
|
||||
{ DBSC_DBSCHQOS132, 0x000000A0 },
|
||||
{ DBSC_DBSCHQOS133, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS140, 0x000000C0 },
|
||||
{ DBSC_DBSCHQOS141, 0x000000B0 },
|
||||
{ DBSC_DBSCHQOS142, 0x00000080 },
|
||||
{ DBSC_DBSCHQOS143, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS150, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS151, 0x00000030 },
|
||||
{ DBSC_DBSCHQOS152, 0x00000020 },
|
||||
{ DBSC_DBSCHQOS153, 0x00000010 },
|
||||
};
|
||||
|
||||
void qos_init_m3_v10(void)
|
||||
{
|
||||
rcar_qos_dbsc_setting(m3_v10_qos, ARRAY_SIZE(m3_v10_qos), false);
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
|
||||
#if RCAR_LSI == RCAR_M3
|
||||
#error "Don't set DRAM Split 4ch(M3)"
|
||||
#else
|
||||
ERROR("DRAM Split 4ch not supported.(M3)");
|
||||
panic();
|
||||
#endif
|
||||
#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
|
||||
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
|
||||
NOTICE("BL2: DRAM Split is 2ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1CU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR2, 0x089A0000U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#else
|
||||
NOTICE("BL2: DRAM Split is OFF\n");
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(QOSCTRL_RAS, 0x00000028U);
|
||||
io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
|
||||
io_write_32(QOSCTRL_REGGD, 0x00000000U);
|
||||
io_write_64(QOSCTRL_DANN, 0x0101010102020201UL);
|
||||
io_write_32(QOSCTRL_DANT, 0x00100804U);
|
||||
io_write_32(QOSCTRL_EC, 0x00000000U);
|
||||
io_write_64(QOSCTRL_EMS, 0x0000000000000000UL);
|
||||
io_write_32(QOSCTRL_FSS, 0x000003e8U);
|
||||
io_write_32(QOSCTRL_INSFC, 0xC7840001U);
|
||||
io_write_32(QOSCTRL_BERR, 0x00000000U);
|
||||
io_write_32(QOSCTRL_RACNT0, 0x00000000U);
|
||||
|
||||
/* QOSBW setting */
|
||||
io_write_32(QOSCTRL_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
|
||||
io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
|
||||
|
||||
/* QOSBW SRAM setting */
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
io_write_32(0xFD820808U, 0x00001234U);
|
||||
io_write_32(0xFD820800U, 0x00000006U);
|
||||
io_write_32(0xFD821800U, 0x00000006U);
|
||||
io_write_32(0xFD822800U, 0x00000006U);
|
||||
io_write_32(0xFD823800U, 0x00000006U);
|
||||
io_write_32(0xFD824800U, 0x00000006U);
|
||||
io_write_32(0xFD825800U, 0x00000006U);
|
||||
io_write_32(0xFD826800U, 0x00000006U);
|
||||
io_write_32(0xFD827800U, 0x00000006U);
|
||||
|
||||
/* RT bus Leaf setting */
|
||||
io_write_32(0xFFC50800U, 0x00000000U);
|
||||
io_write_32(0xFFC51800U, 0x00000000U);
|
||||
|
||||
/* Resource Alloc start */
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
|
||||
/* QOSBW start */
|
||||
io_write_32(QOSCTRL_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(QOSCTRL_EC, 0x00000000U);
|
||||
/* Resource Alloc start */
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
||||
|
|
@ -0,0 +1,227 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
static const uint64_t mstat_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001004030000FFFFUL,
|
||||
/* 0x0038, */ 0x001004030000FFFFUL,
|
||||
/* 0x0040, */ 0x001414090000FFFFUL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x001410010000FFFFUL,
|
||||
/* 0x0058, */ 0x00140C090000FFFFUL,
|
||||
/* 0x0060, */ 0x00140C090000FFFFUL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x001410010000FFFFUL,
|
||||
/* 0x0078, */ 0x001004020000FFFFUL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x001414090000FFFFUL,
|
||||
/* 0x0090, */ 0x001408060000FFFFUL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00A0, */ 0x000C08020000FFFFUL,
|
||||
/* 0x00A8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00B0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00B8, */ 0x0000000000000000UL,
|
||||
/* 0x00C0, */ 0x000C08020000FFFFUL,
|
||||
/* 0x00C8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00D0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00D8, */ 0x000C04030000FFFFUL,
|
||||
/* 0x00E0, */ 0x000C100F0000FFFFUL,
|
||||
/* 0x00E8, */ 0x0000000000000000UL,
|
||||
/* 0x00F0, */ 0x001010080000FFFFUL,
|
||||
/* 0x00F8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x001010080000FFFFUL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x00100C0A0000FFFFUL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x00100C0A0000FFFFUL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x00100C0A0000FFFFUL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x001008050000FFFFUL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x001028280000FFFFUL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01A0, */ 0x00100C0A0000FFFFUL,
|
||||
/* 0x01A8, */ 0x0000000000000000UL,
|
||||
/* 0x01B0, */ 0x0000000000000000UL,
|
||||
/* 0x01B8, */ 0x0000000000000000UL,
|
||||
/* 0x01C0, */ 0x0000000000000000UL,
|
||||
/* 0x01C8, */ 0x0000000000000000UL,
|
||||
/* 0x01D0, */ 0x0000000000000000UL,
|
||||
/* 0x01D8, */ 0x0000000000000000UL,
|
||||
/* 0x01E0, */ 0x0000000000000000UL,
|
||||
/* 0x01E8, */ 0x0000000000000000UL,
|
||||
/* 0x01F0, */ 0x0000000000000000UL,
|
||||
/* 0x01F8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x001408010000FFFFUL,
|
||||
/* 0x0270, */ 0x001404010000FFFFUL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001408010000FFFFUL,
|
||||
/* 0x0298, */ 0x001404010000FFFFUL,
|
||||
/* 0x02A0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02A8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02B0, */ 0x001404010000FFFFUL,
|
||||
/* 0x02B8, */ 0x0000000000000000UL,
|
||||
/* 0x02C0, */ 0x0000000000000000UL,
|
||||
/* 0x02C8, */ 0x0000000000000000UL,
|
||||
/* 0x02D0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02D8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02E0, */ 0x001404010000FFFFUL,
|
||||
/* 0x02E8, */ 0x0000000000000000UL,
|
||||
/* 0x02F0, */ 0x0000000000000000UL,
|
||||
/* 0x02F8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static const uint64_t mstat_be[] = {
|
||||
/* 0x0000, */ 0x001200100C89C401UL,
|
||||
/* 0x0008, */ 0x001200100C89C401UL,
|
||||
/* 0x0010, */ 0x001200100C89C401UL,
|
||||
/* 0x0018, */ 0x001200100C89C401UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x001100100C803401UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00A0, */ 0x0000000000000000UL,
|
||||
/* 0x00A8, */ 0x0000000000000000UL,
|
||||
/* 0x00B0, */ 0x0000000000000000UL,
|
||||
/* 0x00B8, */ 0x0000000000000000UL,
|
||||
/* 0x00C0, */ 0x0000000000000000UL,
|
||||
/* 0x00C8, */ 0x0000000000000000UL,
|
||||
/* 0x00D0, */ 0x0000000000000000UL,
|
||||
/* 0x00D8, */ 0x0000000000000000UL,
|
||||
/* 0x00E0, */ 0x0000000000000000UL,
|
||||
/* 0x00E8, */ 0x0000000000000000UL,
|
||||
/* 0x00F0, */ 0x0000000000000000UL,
|
||||
/* 0x00F8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01A0, */ 0x0000000000000000UL,
|
||||
/* 0x01A8, */ 0x0000000000000000UL,
|
||||
/* 0x01B0, */ 0x0000000000000000UL,
|
||||
/* 0x01B8, */ 0x0000000000000000UL,
|
||||
/* 0x01C0, */ 0x001100500C8FFC01UL,
|
||||
/* 0x01C8, */ 0x001100500C8FFC01UL,
|
||||
/* 0x01D0, */ 0x001100500C8FFC01UL,
|
||||
/* 0x01D8, */ 0x001100500C8FFC01UL,
|
||||
/* 0x01E0, */ 0x0000000000000000UL,
|
||||
/* 0x01E8, */ 0x001200100C803401UL,
|
||||
/* 0x01F0, */ 0x001100100C80FC01UL,
|
||||
/* 0x01F8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x001200100C80FC01UL,
|
||||
/* 0x0210, */ 0x001100100C80FC01UL,
|
||||
/* 0x0218, */ 0x001100100C825801UL,
|
||||
/* 0x0220, */ 0x001100100C825801UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x001100100C825801UL,
|
||||
/* 0x0238, */ 0x001100100C825801UL,
|
||||
/* 0x0240, */ 0x001200100C8BB801UL,
|
||||
/* 0x0248, */ 0x001100100C8EA401UL,
|
||||
/* 0x0250, */ 0x001200100C8BB801UL,
|
||||
/* 0x0258, */ 0x001100100C8EA401UL,
|
||||
/* 0x0260, */ 0x001100100C84E401UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x001100100C81F401UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02A0, */ 0x0000000000000000UL,
|
||||
/* 0x02A8, */ 0x0000000000000000UL,
|
||||
/* 0x02B0, */ 0x0000000000000000UL,
|
||||
/* 0x02B8, */ 0x001100100C803401UL,
|
||||
/* 0x02C0, */ 0x0000000000000000UL,
|
||||
/* 0x02C8, */ 0x0000000000000000UL,
|
||||
/* 0x02D0, */ 0x0000000000000000UL,
|
||||
/* 0x02D8, */ 0x0000000000000000UL,
|
||||
/* 0x02E0, */ 0x0000000000000000UL,
|
||||
/* 0x02E8, */ 0x001100100C803401UL,
|
||||
/* 0x02F0, */ 0x001100300C8FFC01UL,
|
||||
/* 0x02F8, */ 0x001100500C8FFC01UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x001100300C8FFC01UL,
|
||||
/* 0x0310, */ 0x001100500C8FFC01UL,
|
||||
/* 0x0318, */ 0x001200100C803401UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
};
|
||||
#endif
|
||||
|
|
@ -12,29 +12,34 @@
|
|||
#include "../qos_reg.h"
|
||||
#include "qos_init_m3_v11.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.19"
|
||||
#define RCAR_QOS_VERSION "rev.0.19"
|
||||
|
||||
#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
|
||||
|
||||
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
|
||||
|
||||
#define QOSWT_WTEN_ENABLE (0x1U)
|
||||
#define QOSWT_WTEN_ENABLE 0x1U
|
||||
|
||||
#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_11 (SL_INIT_SSLOTCLK_M3_11 - 0x5U)
|
||||
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
|
||||
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
|
||||
#define QOSWT_WTREF_SLOT0_EN \
|
||||
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
|
||||
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define QOSWT_WTREF_SLOT1_EN \
|
||||
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
|
||||
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
|
||||
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
|
||||
#define WT_BASE_SUB_SLOT_NUM0 (12U)
|
||||
#define QOSWT_WTSET0_PERIOD0_M3_11 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_11)-1U)
|
||||
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
|
||||
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
|
||||
#define QOSWT_WTSET0_REQ_SSLOT0 5U
|
||||
#define WT_BASE_SUB_SLOT_NUM0 12U
|
||||
#define QOSWT_WTSET0_PERIOD0_M3_11 \
|
||||
((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_11) - 1U)
|
||||
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
|
||||
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
|
||||
|
||||
#define QOSWT_WTSET1_PERIOD1_M3_11 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_11)-1U)
|
||||
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
|
||||
#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 -1U)
|
||||
#define QOSWT_WTSET1_PERIOD1_M3_11 \
|
||||
((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_11) - 1U)
|
||||
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
|
||||
#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 - 1U)
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
|
||||
|
|
@ -55,73 +60,52 @@
|
|||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
uint32_t md = 0;
|
||||
|
||||
struct rcar_gen3_dbsc_qos_settings m3_v11_qos[] = {
|
||||
/* BUFCAM settings */
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00043218); /* dbcam0cnf1 */
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */
|
||||
io_write_32(DBSC_DBCAM0CNF3, 0x00000000); /* dbcam0cnf3 */
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x000F0037); /* dbschcnt0 */
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */
|
||||
{ DBSC_DBCAM0CNF1, 0x00043218 },
|
||||
{ DBSC_DBCAM0CNF2, 0x000000F4 },
|
||||
{ DBSC_DBCAM0CNF3, 0x00000000 },
|
||||
{ DBSC_DBSCHCNT0, 0x000F0037 },
|
||||
{ DBSC_DBSCHSZ0, 0x00000001 },
|
||||
{ DBSC_DBSCHRW0, 0x22421111 },
|
||||
|
||||
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
|
||||
|
||||
switch (md) {
|
||||
case 0x0:
|
||||
/* DDR3200 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
|
||||
/* DDR2800 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
|
||||
/* DDR2400 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
|
||||
/* DDR1600 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
}
|
||||
/* DDR3 */
|
||||
{ DBSC_SCFCTST2, 0x012F1123 },
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
|
||||
io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
|
||||
io_write_32(DBSC_DBSCHQOS02, 0x00000000);
|
||||
io_write_32(DBSC_DBSCHQOS03, 0x00000000);
|
||||
io_write_32(DBSC_DBSCHQOS40, 0x00000300);
|
||||
io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
|
||||
io_write_32(DBSC_DBSCHQOS42, 0x00000200);
|
||||
io_write_32(DBSC_DBSCHQOS43, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS90, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
|
||||
io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
|
||||
io_write_32(DBSC_DBSCHQOS93, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS120, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS121, 0x00000030);
|
||||
io_write_32(DBSC_DBSCHQOS122, 0x00000020);
|
||||
io_write_32(DBSC_DBSCHQOS123, 0x00000010);
|
||||
io_write_32(DBSC_DBSCHQOS130, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
|
||||
io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
|
||||
io_write_32(DBSC_DBSCHQOS133, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
|
||||
io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
|
||||
io_write_32(DBSC_DBSCHQOS142, 0x00000080);
|
||||
io_write_32(DBSC_DBSCHQOS143, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS150, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS151, 0x00000030);
|
||||
io_write_32(DBSC_DBSCHQOS152, 0x00000020);
|
||||
io_write_32(DBSC_DBSCHQOS153, 0x00000010);
|
||||
}
|
||||
{ DBSC_DBSCHQOS00, 0x00000F00 },
|
||||
{ DBSC_DBSCHQOS01, 0x00000B00 },
|
||||
{ DBSC_DBSCHQOS02, 0x00000000 },
|
||||
{ DBSC_DBSCHQOS03, 0x00000000 },
|
||||
{ DBSC_DBSCHQOS40, 0x00000300 },
|
||||
{ DBSC_DBSCHQOS41, 0x000002F0 },
|
||||
{ DBSC_DBSCHQOS42, 0x00000200 },
|
||||
{ DBSC_DBSCHQOS43, 0x00000100 },
|
||||
{ DBSC_DBSCHQOS90, 0x00000100 },
|
||||
{ DBSC_DBSCHQOS91, 0x000000F0 },
|
||||
{ DBSC_DBSCHQOS92, 0x000000A0 },
|
||||
{ DBSC_DBSCHQOS93, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS120, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS121, 0x00000030 },
|
||||
{ DBSC_DBSCHQOS122, 0x00000020 },
|
||||
{ DBSC_DBSCHQOS123, 0x00000010 },
|
||||
{ DBSC_DBSCHQOS130, 0x00000100 },
|
||||
{ DBSC_DBSCHQOS131, 0x000000F0 },
|
||||
{ DBSC_DBSCHQOS132, 0x000000A0 },
|
||||
{ DBSC_DBSCHQOS133, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS140, 0x000000C0 },
|
||||
{ DBSC_DBSCHQOS141, 0x000000B0 },
|
||||
{ DBSC_DBSCHQOS142, 0x00000080 },
|
||||
{ DBSC_DBSCHQOS143, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS150, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS151, 0x00000030 },
|
||||
{ DBSC_DBSCHQOS152, 0x00000020 },
|
||||
{ DBSC_DBSCHQOS153, 0x00000010 },
|
||||
};
|
||||
|
||||
void qos_init_m3_v11(void)
|
||||
{
|
||||
dbsc_setting();
|
||||
rcar_qos_dbsc_setting(m3_v11_qos, ARRAY_SIZE(m3_v11_qos), false);
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
|
||||
|
|
@ -176,30 +160,26 @@ void qos_init_m3_v11(void)
|
|||
io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8, qoswt_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
io_write_32(GPU_ACT_GRD, 0x00001234U);
|
||||
|
|
@ -12,31 +12,34 @@
|
|||
#include "../qos_reg.h"
|
||||
#include "qos_init_m3_v30.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.03"
|
||||
#define RCAR_QOS_VERSION "rev.0.03"
|
||||
|
||||
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
|
||||
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
|
||||
#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
|
||||
|
||||
#define QOSWT_TIME_BANK0 (20000000U) //unit:ns
|
||||
|
||||
#define QOSWT_WTEN_ENABLE (0x1U)
|
||||
#define QOSWT_WTEN_ENABLE 0x1U
|
||||
|
||||
#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 (SL_INIT_SSLOTCLK_M3_30 - 0x5U)
|
||||
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
|
||||
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
|
||||
#define QOSWT_WTREF_SLOT0_EN \
|
||||
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
|
||||
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define QOSWT_WTREF_SLOT1_EN \
|
||||
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
|
||||
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
|
||||
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
|
||||
#define WT_BASE_SUB_SLOT_NUM0 (12U)
|
||||
#define QOSWT_WTSET0_PERIOD0_M3_30 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_30)-1U)
|
||||
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
|
||||
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
|
||||
#define QOSWT_WTSET0_REQ_SSLOT0 5U
|
||||
#define WT_BASE_SUB_SLOT_NUM0 12U
|
||||
#define QOSWT_WTSET0_PERIOD0_M3_30 \
|
||||
((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_30) - 1U)
|
||||
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
|
||||
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
|
||||
|
||||
#define QOSWT_WTSET1_PERIOD1_M3_30 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_30)-1U)
|
||||
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
|
||||
#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 -1U)
|
||||
#define QOSWT_WTSET1_PERIOD1_M3_30 \
|
||||
((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_30) - 1U)
|
||||
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
|
||||
#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 - 1U)
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
|
||||
|
|
@ -57,79 +60,52 @@
|
|||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
uint32_t md=0;
|
||||
|
||||
/* Register write enable */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
|
||||
|
||||
struct rcar_gen3_dbsc_qos_settings m3_v30_qos[] = {
|
||||
/* BUFCAM settings */
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00043218); //dbcam0cnf1
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2
|
||||
io_write_32(DBSC_DBCAM0CNF3, 0x00000000); //dbcam0cnf3
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x000F0037); //dbschcnt0
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0
|
||||
{ DBSC_DBCAM0CNF1, 0x00043218 },
|
||||
{ DBSC_DBCAM0CNF2, 0x000000F4 },
|
||||
{ DBSC_DBCAM0CNF3, 0x00000000 },
|
||||
{ DBSC_DBSCHCNT0, 0x000F0037 },
|
||||
{ DBSC_DBSCHSZ0, 0x00000001 },
|
||||
{ DBSC_DBSCHRW0, 0x22421111 },
|
||||
|
||||
md = (*((volatile uint32_t*)RST_MODEMR) & 0x000A0000) >> 17;
|
||||
|
||||
switch (md) {
|
||||
case 0x0:
|
||||
/* DDR3200 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x1: //MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4)
|
||||
/* DDR2800 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x4: //MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4)
|
||||
/* DDR2400 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
default: //MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4)
|
||||
/* DDR1600 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
}
|
||||
/* DDR3 */
|
||||
{ DBSC_SCFCTST2, 0x012F1123 },
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
|
||||
io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
|
||||
io_write_32(DBSC_DBSCHQOS02, 0x00000000);
|
||||
io_write_32(DBSC_DBSCHQOS03, 0x00000000);
|
||||
io_write_32(DBSC_DBSCHQOS40, 0x00000300);
|
||||
io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
|
||||
io_write_32(DBSC_DBSCHQOS42, 0x00000200);
|
||||
io_write_32(DBSC_DBSCHQOS43, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS90, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
|
||||
io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
|
||||
io_write_32(DBSC_DBSCHQOS93, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS120, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS121, 0x00000030);
|
||||
io_write_32(DBSC_DBSCHQOS122, 0x00000020);
|
||||
io_write_32(DBSC_DBSCHQOS123, 0x00000010);
|
||||
io_write_32(DBSC_DBSCHQOS130, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
|
||||
io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
|
||||
io_write_32(DBSC_DBSCHQOS133, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
|
||||
io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
|
||||
io_write_32(DBSC_DBSCHQOS142, 0x00000080);
|
||||
io_write_32(DBSC_DBSCHQOS143, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS150, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS151, 0x00000030);
|
||||
io_write_32(DBSC_DBSCHQOS152, 0x00000020);
|
||||
io_write_32(DBSC_DBSCHQOS153, 0x00000010);
|
||||
|
||||
/* Register write protect */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
|
||||
}
|
||||
{ DBSC_DBSCHQOS00, 0x00000F00 },
|
||||
{ DBSC_DBSCHQOS01, 0x00000B00 },
|
||||
{ DBSC_DBSCHQOS02, 0x00000000 },
|
||||
{ DBSC_DBSCHQOS03, 0x00000000 },
|
||||
{ DBSC_DBSCHQOS40, 0x00000300 },
|
||||
{ DBSC_DBSCHQOS41, 0x000002F0 },
|
||||
{ DBSC_DBSCHQOS42, 0x00000200 },
|
||||
{ DBSC_DBSCHQOS43, 0x00000100 },
|
||||
{ DBSC_DBSCHQOS90, 0x00000100 },
|
||||
{ DBSC_DBSCHQOS91, 0x000000F0 },
|
||||
{ DBSC_DBSCHQOS92, 0x000000A0 },
|
||||
{ DBSC_DBSCHQOS93, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS120, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS121, 0x00000030 },
|
||||
{ DBSC_DBSCHQOS122, 0x00000020 },
|
||||
{ DBSC_DBSCHQOS123, 0x00000010 },
|
||||
{ DBSC_DBSCHQOS130, 0x00000100 },
|
||||
{ DBSC_DBSCHQOS131, 0x000000F0 },
|
||||
{ DBSC_DBSCHQOS132, 0x000000A0 },
|
||||
{ DBSC_DBSCHQOS133, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS140, 0x000000C0 },
|
||||
{ DBSC_DBSCHQOS141, 0x000000B0 },
|
||||
{ DBSC_DBSCHQOS142, 0x00000080 },
|
||||
{ DBSC_DBSCHQOS143, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS150, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS151, 0x00000030 },
|
||||
{ DBSC_DBSCHQOS152, 0x00000020 },
|
||||
{ DBSC_DBSCHQOS153, 0x00000010 },
|
||||
};
|
||||
|
||||
void qos_init_m3_v30(void)
|
||||
{
|
||||
dbsc_setting();
|
||||
rcar_qos_dbsc_setting(m3_v30_qos, ARRAY_SIZE(m3_v30_qos), true);
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
|
||||
|
|
@ -182,36 +158,26 @@ void qos_init_m3_v30(void)
|
|||
io_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_M3_30);
|
||||
io_write_32(QOSCTRL_REF_ARS, ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 << 16)));
|
||||
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i*8,
|
||||
mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i*8,
|
||||
mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i*8,
|
||||
mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i*8,
|
||||
mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i*8,
|
||||
qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i*8,
|
||||
qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8, qoswt_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK0 + i*8,
|
||||
qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK1 + i*8,
|
||||
qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
}
|
||||
|
||||
/* RT bus Leaf setting */
|
||||
io_write_32(RT_ACT0, 0x00000000U);
|
||||
|
|
@ -0,0 +1,203 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
|
||||
#include "../qos_common.h"
|
||||
#include "../qos_reg.h"
|
||||
#include "qos_init_m3n_v10.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.09"
|
||||
|
||||
#define REF_ARS_ARBSTOPCYCLE_M3N \
|
||||
(((SL_INIT_SSLOTCLK_M3N) - 5U) << 16U)
|
||||
|
||||
#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
|
||||
|
||||
#define QOSWT_WTEN_ENABLE 0x1U
|
||||
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
|
||||
#define QOSWT_WTREF_SLOT0_EN \
|
||||
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
|
||||
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define QOSWT_WTREF_SLOT1_EN QOSWT_WTREF_SLOT0_EN
|
||||
|
||||
#define QOSWT_WTSET0_REQ_SSLOT0 5U
|
||||
#define WT_BASE_SUB_SLOT_NUM0 12U
|
||||
#define QOSWT_WTSET0_PERIOD0_M3N \
|
||||
((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3N) - 1U)
|
||||
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
|
||||
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
|
||||
|
||||
#define QOSWT_WTSET1_PERIOD1_M3N QOSWT_WTSET0_PERIOD0_M3N
|
||||
#define QOSWT_WTSET1_SSLOT1 QOSWT_WTSET0_SSLOT0
|
||||
#define QOSWT_WTSET1_SLOTSLOT1 QOSWT_WTSET0_SLOTSLOT0
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
#include "qos_init_m3n_v10_mstat195.h"
|
||||
#else
|
||||
#include "qos_init_m3n_v10_mstat390.h"
|
||||
#endif
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
#include "qos_init_m3n_v10_qoswt195.h"
|
||||
#else
|
||||
#include "qos_init_m3n_v10_qoswt390.h"
|
||||
#endif
|
||||
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
#endif
|
||||
|
||||
struct rcar_gen3_dbsc_qos_settings m3n_v10_qos[] = {
|
||||
/* BUFCAM settings */
|
||||
{ DBSC_DBCAM0CNF1, 0x00043218 },
|
||||
{ DBSC_DBCAM0CNF2, 0x000000F4 },
|
||||
{ DBSC_DBSCHCNT0, 0x000F0037 },
|
||||
{ DBSC_DBSCHSZ0, 0x00000001 },
|
||||
{ DBSC_DBSCHRW0, 0x22421111 },
|
||||
|
||||
/* DDR3 */
|
||||
{ DBSC_SCFCTST2, 0x012F1123 },
|
||||
|
||||
/* QoS Settings */
|
||||
{ DBSC_DBSCHQOS00, 0x00000F00 },
|
||||
{ DBSC_DBSCHQOS01, 0x00000B00 },
|
||||
{ DBSC_DBSCHQOS02, 0x00000000 },
|
||||
{ DBSC_DBSCHQOS03, 0x00000000 },
|
||||
{ DBSC_DBSCHQOS40, 0x00000300 },
|
||||
{ DBSC_DBSCHQOS41, 0x000002F0 },
|
||||
{ DBSC_DBSCHQOS42, 0x00000200 },
|
||||
{ DBSC_DBSCHQOS43, 0x00000100 },
|
||||
{ DBSC_DBSCHQOS90, 0x00000100 },
|
||||
{ DBSC_DBSCHQOS91, 0x000000F0 },
|
||||
{ DBSC_DBSCHQOS92, 0x000000A0 },
|
||||
{ DBSC_DBSCHQOS93, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS130, 0x00000100 },
|
||||
{ DBSC_DBSCHQOS131, 0x000000F0 },
|
||||
{ DBSC_DBSCHQOS132, 0x000000A0 },
|
||||
{ DBSC_DBSCHQOS133, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS140, 0x000000C0 },
|
||||
{ DBSC_DBSCHQOS141, 0x000000B0 },
|
||||
{ DBSC_DBSCHQOS142, 0x00000080 },
|
||||
{ DBSC_DBSCHQOS143, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS150, 0x00000040 },
|
||||
{ DBSC_DBSCHQOS151, 0x00000030 },
|
||||
{ DBSC_DBSCHQOS152, 0x00000020 },
|
||||
{ DBSC_DBSCHQOS153, 0x00000010 },
|
||||
};
|
||||
|
||||
void qos_init_m3n_v10(void)
|
||||
{
|
||||
rcar_qos_dbsc_setting(m3n_v10_qos, ARRAY_SIZE(m3n_v10_qos), true);
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
|
||||
#if RCAR_LSI == RCAR_M3N
|
||||
#error "Don't set DRAM Split 4ch(M3N)"
|
||||
#else
|
||||
ERROR("DRAM Split 4ch not supported.(M3N)");
|
||||
panic();
|
||||
#endif
|
||||
#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
|
||||
#if RCAR_LSI == RCAR_M3N
|
||||
#error "Don't set DRAM Split 2ch(M3N)"
|
||||
#else
|
||||
ERROR("DRAM Split 2ch not supported.(M3N)");
|
||||
panic();
|
||||
#endif
|
||||
#else
|
||||
NOTICE("BL2: DRAM Split is OFF\n");
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
|
||||
#else
|
||||
NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
|
||||
#endif
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
NOTICE("BL2: Periodic Write DQ Training\n");
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
io_write_32(QOSCTRL_RAS, 0x00000028U);
|
||||
io_write_64(QOSCTRL_DANN, 0x0402000002020201UL);
|
||||
io_write_32(QOSCTRL_DANT, 0x00100804U);
|
||||
io_write_32(QOSCTRL_FSS, 0x0000000AU);
|
||||
io_write_32(QOSCTRL_INSFC, 0x06330001U);
|
||||
io_write_32(QOSCTRL_EARLYR, 0x00000001U);
|
||||
io_write_32(QOSCTRL_RACNT0, 0x00010003U);
|
||||
|
||||
io_write_32(QOSCTRL_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
|
||||
SL_INIT_SSLOTCLK_M3N);
|
||||
io_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_M3N);
|
||||
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
/* RT bus Leaf setting */
|
||||
io_write_32(RT_ACT0, 0x00000000U);
|
||||
io_write_32(RT_ACT1, 0x00000000U);
|
||||
|
||||
/* CCI bus Leaf setting */
|
||||
io_write_32(CPU_ACT0, 0x00000003U);
|
||||
io_write_32(CPU_ACT1, 0x00000003U);
|
||||
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
/* re-write training setting */
|
||||
io_write_32(QOSWT_WTREF,
|
||||
((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
|
||||
io_write_32(QOSWT_WTSET0,
|
||||
((QOSWT_WTSET0_PERIOD0_M3N << 16) |
|
||||
(QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
|
||||
io_write_32(QOSWT_WTSET1,
|
||||
((QOSWT_WTSET1_PERIOD1_M3N << 16) |
|
||||
(QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
|
||||
|
||||
io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
io_write_32(QOSCTRL_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
||||
|
|
@ -0,0 +1,111 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
|
||||
#include "../qos_common.h"
|
||||
#include "../qos_reg.h"
|
||||
#include "qos_init_v3m.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.01"
|
||||
|
||||
#include "qos_init_v3m_mstat.h"
|
||||
|
||||
struct rcar_gen3_dbsc_qos_settings v3m_qos[] = {
|
||||
/* BUFCAM settings */
|
||||
{ DBSC_DBCAM0CNF1, 0x00044218 },
|
||||
{ DBSC_DBCAM0CNF2, 0x000000F4 },
|
||||
{ DBSC_DBSCHCNT0, 0x080F003F },
|
||||
{ DBSC_DBSCHCNT1, 0x00001010 },
|
||||
|
||||
{ DBSC_DBSCHSZ0, 0x00000001 },
|
||||
{ DBSC_DBSCHRW0, 0x22421111 },
|
||||
{ DBSC_DBSCHRW1, 0x00180034 },
|
||||
{ DBSC_SCFCTST0, 0x180B1708 },
|
||||
{ DBSC_SCFCTST1, 0x0808070C },
|
||||
{ DBSC_SCFCTST2, 0x012F1123 },
|
||||
|
||||
/* QoS Settings */
|
||||
{ DBSC_DBSCHQOS00, 0x0000F000 },
|
||||
{ DBSC_DBSCHQOS01, 0x0000E000 },
|
||||
{ DBSC_DBSCHQOS02, 0x00007000 },
|
||||
{ DBSC_DBSCHQOS03, 0x00000000 },
|
||||
{ DBSC_DBSCHQOS40, 0x0000F000 },
|
||||
{ DBSC_DBSCHQOS41, 0x0000EFFF },
|
||||
{ DBSC_DBSCHQOS42, 0x0000B000 },
|
||||
{ DBSC_DBSCHQOS43, 0x00000000 },
|
||||
{ DBSC_DBSCHQOS90, 0x0000F000 },
|
||||
{ DBSC_DBSCHQOS91, 0x0000EFFF },
|
||||
{ DBSC_DBSCHQOS92, 0x0000D000 },
|
||||
{ DBSC_DBSCHQOS93, 0x00000000 },
|
||||
{ DBSC_DBSCHQOS130, 0x0000F000 },
|
||||
{ DBSC_DBSCHQOS131, 0x0000EFFF },
|
||||
{ DBSC_DBSCHQOS132, 0x0000E800 },
|
||||
{ DBSC_DBSCHQOS133, 0x00007000 },
|
||||
{ DBSC_DBSCHQOS140, 0x0000F000 },
|
||||
{ DBSC_DBSCHQOS141, 0x0000EFFF },
|
||||
{ DBSC_DBSCHQOS142, 0x0000E800 },
|
||||
{ DBSC_DBSCHQOS143, 0x0000B000 },
|
||||
{ DBSC_DBSCHQOS150, 0x000007D0 },
|
||||
{ DBSC_DBSCHQOS151, 0x000007CF },
|
||||
{ DBSC_DBSCHQOS152, 0x000005D0 },
|
||||
{ DBSC_DBSCHQOS153, 0x000003D0 },
|
||||
};
|
||||
|
||||
void qos_init_v3m(void)
|
||||
{
|
||||
return;
|
||||
|
||||
rcar_qos_dbsc_setting(v3m_qos, ARRAY_SIZE(v3m_qos), false);
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(QOSCTRL_RAS, 0x00000020U);
|
||||
io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
|
||||
io_write_32(QOSCTRL_REGGD, 0x00000004U);
|
||||
io_write_64(QOSCTRL_DANN, 0x0202020104040200U);
|
||||
io_write_32(QOSCTRL_DANT, 0x00201008U);
|
||||
io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 ES1 */
|
||||
io_write_64(QOSCTRL_EMS, 0x0000000000000000U);
|
||||
io_write_32(QOSCTRL_INSFC, 0x63C20001U);
|
||||
io_write_32(QOSCTRL_BERR, 0x00000000U);
|
||||
|
||||
/* QOSBW setting */
|
||||
io_write_32(QOSCTRL_SL_INIT, 0x0305007DU);
|
||||
io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
|
||||
|
||||
/* QOSBW SRAM setting */
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
|
||||
/* AXI-IF arbitration setting */
|
||||
io_write_32(DBSC_AXARB, 0x18010000U);
|
||||
|
||||
/* Resource Alloc start */
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
|
||||
/* QOSBW start */
|
||||
io_write_32(QOSCTRL_STATQC, 0x00000001U);
|
||||
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
static const uint64_t mstat_fix[] = {
|
||||
/* 0x0000, */ 0x000000000000FFFFUL,
|
||||
/* 0x0008, */ 0x000000000000FFFFUL,
|
||||
/* 0x0010, */ 0x000000000000FFFFUL,
|
||||
/* 0x0018, */ 0x000000000000FFFFUL,
|
||||
/* 0x0020, */ 0x001414090000FFFFUL,
|
||||
/* 0x0028, */ 0x000C00000000FFFFUL,
|
||||
/* 0x0030, */ 0x001008040000FFFFUL,
|
||||
/* 0x0038, */ 0x001004040000FFFFUL,
|
||||
/* 0x0040, */ 0x001004040000FFFFUL,
|
||||
/* 0x0048, */ 0x000000000000FFFFUL,
|
||||
/* 0x0050, */ 0x001004040000FFFFUL,
|
||||
/* 0x0058, */ 0x001004040000FFFFUL,
|
||||
/* 0x0060, */ 0x000000000000FFFFUL,
|
||||
/* 0x0068, */ 0x001404040000FFFFUL,
|
||||
/* 0x0070, */ 0x001008030000FFFFUL,
|
||||
/* 0x0078, */ 0x001004030000FFFFUL,
|
||||
/* 0x0080, */ 0x001004030000FFFFUL,
|
||||
/* 0x0088, */ 0x000000000000FFFFUL,
|
||||
/* 0x0090, */ 0x001004040000FFFFUL,
|
||||
/* 0x0098, */ 0x001004040000FFFFUL,
|
||||
/* 0x00A0, */ 0x000000000000FFFFUL,
|
||||
/* 0x00A8, */ 0x000000000000FFFFUL,
|
||||
/* 0x00B0, */ 0x000000000000FFFFUL,
|
||||
/* 0x00B8, */ 0x000000000000FFFFUL,
|
||||
/* 0x00C0, */ 0x000000000000FFFFUL,
|
||||
/* 0x00C8, */ 0x000000000000FFFFUL,
|
||||
/* 0x00D0, */ 0x000000000000FFFFUL,
|
||||
/* 0x00D8, */ 0x000000000000FFFFUL,
|
||||
/* 0x00E0, */ 0x001404020000FFFFUL,
|
||||
/* 0x00E8, */ 0x000000000000FFFFUL,
|
||||
/* 0x00F0, */ 0x000000000000FFFFUL,
|
||||
/* 0x00F8, */ 0x000000000000FFFFUL,
|
||||
/* 0x0100, */ 0x000000000000FFFFUL,
|
||||
/* 0x0108, */ 0x000C04020000FFFFUL,
|
||||
/* 0x0110, */ 0x000000000000FFFFUL,
|
||||
/* 0x0118, */ 0x001404020000FFFFUL,
|
||||
/* 0x0120, */ 0x000000000000FFFFUL,
|
||||
/* 0x0128, */ 0x000000000000FFFFUL,
|
||||
/* 0x0130, */ 0x000000000000FFFFUL,
|
||||
/* 0x0138, */ 0x000000000000FFFFUL,
|
||||
/* 0x0140, */ 0x000000000000FFFFUL,
|
||||
/* 0x0148, */ 0x000000000000FFFFUL,
|
||||
};
|
||||
|
||||
static const uint64_t mstat_be[] = {
|
||||
/* 0x0000, */ 0x00100020447FFC01UL,
|
||||
/* 0x0008, */ 0x00100020447FFC01UL,
|
||||
/* 0x0010, */ 0x00100040447FFC01UL,
|
||||
/* 0x0018, */ 0x00100040447FFC01UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00A0, */ 0x00100010447FFC01UL,
|
||||
/* 0x00A8, */ 0x00100010447FFC01UL,
|
||||
/* 0x00B0, */ 0x00100010447FFC01UL,
|
||||
/* 0x00B8, */ 0x00100010447FFC01UL,
|
||||
/* 0x00C0, */ 0x00100010447FFC01UL,
|
||||
/* 0x00C8, */ 0x00100010447FFC01UL,
|
||||
/* 0x00D0, */ 0x0000000000000000UL,
|
||||
/* 0x00D8, */ 0x00100010447FFC01UL,
|
||||
/* 0x00E0, */ 0x0000000000000000UL,
|
||||
/* 0x00E8, */ 0x00100010447FFC01UL,
|
||||
/* 0x00F0, */ 0x00100010447FFC01UL,
|
||||
/* 0x00F8, */ 0x00100010447FFC01UL,
|
||||
/* 0x0100, */ 0x00100010447FFC01UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x00100010447FFC01UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x00100010447FFC01UL,
|
||||
/* 0x0128, */ 0x00100010447FFC01UL,
|
||||
/* 0x0130, */ 0x00100010447FFC01UL,
|
||||
/* 0x0138, */ 0x00100010447FFC01UL,
|
||||
/* 0x0140, */ 0x00100020447FFC01UL,
|
||||
/* 0x0148, */ 0x00100020447FFC01UL,
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
#
|
||||
# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
ifeq (${RCAR_LSI},${RCAR_AUTO})
|
||||
# E3, H3N not available for LSI_AUTO
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v10.c
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v11.c
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v20.c
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/V3M/qos_init_v3m.c
|
||||
else ifdef RCAR_LSI_CUT_COMPAT
|
||||
ifeq (${RCAR_LSI},${RCAR_H3})
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v10.c
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v11.c
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v20.c
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_H3N})
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_M3})
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_M3N})
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_V3M})
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/V3M/qos_init_v3m.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_E3})
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/E3/qos_init_e3_v10.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_D3})
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/D3/qos_init_d3.c
|
||||
endif
|
||||
else
|
||||
ifeq (${RCAR_LSI},${RCAR_H3})
|
||||
ifeq (${LSI_CUT},10)
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v10.c
|
||||
else ifeq (${LSI_CUT},11)
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v11.c
|
||||
else ifeq (${LSI_CUT},20)
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v20.c
|
||||
else ifeq (${LSI_CUT},30)
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
|
||||
else
|
||||
# LSI_CUT 30 or later
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
|
||||
endif
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_H3N})
|
||||
ifeq (${LSI_CUT},30)
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c
|
||||
else
|
||||
# LSI_CUT 30 or later
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c
|
||||
endif
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_M3})
|
||||
ifeq (${LSI_CUT},10)
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c
|
||||
else ifeq (${LSI_CUT},11)
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
|
||||
else ifeq (${LSI_CUT},13)
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
|
||||
else ifeq (${LSI_CUT},30)
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
|
||||
else
|
||||
# LSI_CUT 30 or later
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
|
||||
endif
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_M3N})
|
||||
ifeq (${LSI_CUT},10)
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
|
||||
else
|
||||
# LSI_CUT 10 or later
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
|
||||
endif
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_V3M})
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/V3M/qos_init_v3m.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_E3})
|
||||
ifeq (${LSI_CUT},10)
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/E3/qos_init_e3_v10.c
|
||||
else
|
||||
# LSI_CUT 10 or later
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/E3/qos_init_e3_v10.c
|
||||
endif
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_D3})
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/E3/qos_init_d3.c
|
||||
endif
|
||||
endif
|
||||
|
||||
BL2_SOURCES += drivers/renesas/rcar/qos/qos_init.c
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QOS_COMMON_H
|
||||
#define QOS_COMMON_H
|
||||
|
||||
#define RCAR_REF_DEFAULT 0U
|
||||
|
||||
/* define used for get_refperiod. */
|
||||
/* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */
|
||||
/* refere to plat/renesas/rcar/ddr/ddr_a/ddr_init_e3.h for E3. */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF default */
|
||||
#define REFPERIOD_CYCLE /* unit:ns */ \
|
||||
((126 * BASE_SUB_SLOT_NUM * 1000U) / 400)
|
||||
#else /* REF option */
|
||||
#define REFPERIOD_CYCLE /* unit:ns */ \
|
||||
((252 * BASE_SUB_SLOT_NUM * 1000U) / 400)
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_E3)
|
||||
/* define used for E3 */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_E3 0xAFU /* 175 */
|
||||
#else /* REF 7.8usec */
|
||||
#define SUB_SLOT_CYCLE_E3 0x15EU /* 350 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define OPERATING_FREQ_E3 266U /* MHz */
|
||||
#define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 - 1U)
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
|
||||
/* define used for M3N */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
|
||||
#define SUB_SLOT_CYCLE_M3N 0x7EU /* 126 */
|
||||
#else /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_M3N 0xFCU /* 252 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define SL_INIT_SSLOTCLK_M3N (SUB_SLOT_CYCLE_M3N - 1U)
|
||||
#define QOSWT_WTSET0_CYCLE_M3N /* unit:ns */ \
|
||||
((SUB_SLOT_CYCLE_M3N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
|
||||
/* define used for H3 */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
|
||||
#define SUB_SLOT_CYCLE_H3_20 0x7EU /* 126 */
|
||||
#else /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_H3_20 0xFCU /* 252 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define SL_INIT_SSLOTCLK_H3_20 (SUB_SLOT_CYCLE_H3_20 - 1U)
|
||||
#define QOSWT_WTSET0_CYCLE_H3_20 /* unit:ns */ \
|
||||
((SUB_SLOT_CYCLE_H3_20 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
|
||||
|
||||
/* define used for H3 Cut 30 */
|
||||
#define SUB_SLOT_CYCLE_H3_30 (SUB_SLOT_CYCLE_H3_20) /* same as H3 Cut 20 */
|
||||
#define SL_INIT_SSLOTCLK_H3_30 (SUB_SLOT_CYCLE_H3_30 - 1U)
|
||||
#define QOSWT_WTSET0_CYCLE_H3_30 /* unit:ns */ \
|
||||
((SUB_SLOT_CYCLE_H3_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
|
||||
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_H3N)
|
||||
/* define used for H3N */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
|
||||
#define SUB_SLOT_CYCLE_H3N 0x7EU /* 126 */
|
||||
#else /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_H3N 0xFCU /* 252 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define SL_INIT_SSLOTCLK_H3N (SUB_SLOT_CYCLE_H3N - 1U)
|
||||
#define QOSWT_WTSET0_CYCLE_H3N /* unit:ns */ \
|
||||
((SUB_SLOT_CYCLE_H3N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
|
||||
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
|
||||
/* define used for M3 */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
|
||||
#define SUB_SLOT_CYCLE_M3_11 0x7EU /* 126 */
|
||||
#define SUB_SLOT_CYCLE_M3_30 0x7EU /* 126 */
|
||||
#else /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_M3_11 0xFCU /* 252 */
|
||||
#define SUB_SLOT_CYCLE_M3_30 0xFCU /* 252 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 - 1U)
|
||||
#define SL_INIT_SSLOTCLK_M3_30 (SUB_SLOT_CYCLE_M3_30 - 1U)
|
||||
#define QOSWT_WTSET0_CYCLE_M3_11 /* unit:ns */ \
|
||||
((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
|
||||
#define QOSWT_WTSET0_CYCLE_M3_30 /* unit:ns */ \
|
||||
((SUB_SLOT_CYCLE_M3_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
|
||||
#endif
|
||||
|
||||
#define OPERATING_FREQ 400U /* MHz */
|
||||
#define BASE_SUB_SLOT_NUM 0x6U
|
||||
#define SUB_SLOT_CYCLE 0x7EU /* 126 */
|
||||
|
||||
#define QOSWT_WTSET0_CYCLE /* unit:ns */ \
|
||||
((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
|
||||
|
||||
#define SL_INIT_REFFSSLOT (0x3U << 24U)
|
||||
#define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U)
|
||||
#define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE - 1U)
|
||||
|
||||
static inline void io_write_32(uintptr_t addr, uint32_t value)
|
||||
{
|
||||
*(volatile uint32_t *)addr = value;
|
||||
}
|
||||
|
||||
static inline uint32_t io_read_32(uintptr_t addr)
|
||||
{
|
||||
return *(volatile uint32_t *)addr;
|
||||
}
|
||||
|
||||
static inline void io_write_64(uintptr_t addr, uint64_t value)
|
||||
{
|
||||
*(volatile uint64_t *)addr = value;
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
uintptr_t addr;
|
||||
uint64_t value;
|
||||
} mstat_slot_t;
|
||||
|
||||
struct rcar_gen3_dbsc_qos_settings {
|
||||
uint32_t reg;
|
||||
uint32_t val;
|
||||
};
|
||||
|
||||
extern uint32_t qos_init_ddr_ch;
|
||||
extern uint8_t qos_init_ddr_phyvalid;
|
||||
|
||||
void rcar_qos_dbsc_setting(struct rcar_gen3_dbsc_qos_settings *qos,
|
||||
unsigned int qos_size, bool dbsc_wren);
|
||||
|
||||
#endif /* QOS_COMMON_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -11,6 +11,7 @@
|
|||
|
||||
#include "qos_init.h"
|
||||
#include "qos_common.h"
|
||||
#include "qos_reg.h"
|
||||
#if RCAR_LSI == RCAR_AUTO
|
||||
#include "H3/qos_init_h3_v10.h"
|
||||
#include "H3/qos_init_h3_v11.h"
|
||||
|
|
@ -50,42 +51,41 @@
|
|||
#endif
|
||||
|
||||
/* Product Register */
|
||||
#define PRR (0xFFF00044U)
|
||||
#define PRR_PRODUCT_MASK (0x00007F00U)
|
||||
#define PRR_CUT_MASK (0x000000FFU)
|
||||
#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */
|
||||
#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */
|
||||
#define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */
|
||||
#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */
|
||||
#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */
|
||||
#define PRR_PRODUCT_D3 (0x00005800U) /* R-Car D3 */
|
||||
#define PRR_PRODUCT_10 (0x00U)
|
||||
#define PRR_PRODUCT_11 (0x01U)
|
||||
#define PRR_PRODUCT_20 (0x10U)
|
||||
#define PRR_PRODUCT_21 (0x11U)
|
||||
#define PRR_PRODUCT_30 (0x20U)
|
||||
#define PRR 0xFFF00044U
|
||||
#define PRR_PRODUCT_MASK 0x00007F00U
|
||||
#define PRR_CUT_MASK 0x000000FFU
|
||||
#define PRR_PRODUCT_H3 0x00004F00U /* R-Car H3 */
|
||||
#define PRR_PRODUCT_M3 0x00005200U /* R-Car M3 */
|
||||
#define PRR_PRODUCT_V3M 0x00005400U /* R-Car V3M */
|
||||
#define PRR_PRODUCT_M3N 0x00005500U /* R-Car M3N */
|
||||
#define PRR_PRODUCT_E3 0x00005700U /* R-Car E3 */
|
||||
#define PRR_PRODUCT_D3 0x00005800U /* R-Car D3 */
|
||||
#define PRR_PRODUCT_10 0x00U
|
||||
#define PRR_PRODUCT_11 0x01U
|
||||
#define PRR_PRODUCT_20 0x10U
|
||||
#define PRR_PRODUCT_21 0x11U
|
||||
#define PRR_PRODUCT_30 0x20U
|
||||
|
||||
#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RCAR_V3M)
|
||||
|
||||
#define DRAM_CH_CNT 0x04
|
||||
uint32_t qos_init_ddr_ch;
|
||||
uint8_t qos_init_ddr_phyvalid;
|
||||
|
||||
#endif
|
||||
|
||||
#define PRR_PRODUCT_ERR(reg) \
|
||||
do{ \
|
||||
do { \
|
||||
ERROR("LSI Product ID(PRR=0x%x) QoS " \
|
||||
"initialize not supported.\n",reg); \
|
||||
"initialize not supported.\n", reg); \
|
||||
panic(); \
|
||||
} while(0)
|
||||
} while (0)
|
||||
|
||||
#define PRR_CUT_ERR(reg) \
|
||||
do{ \
|
||||
do { \
|
||||
ERROR("LSI Cut ID(PRR=0x%x) QoS " \
|
||||
"initialize not supported.\n",reg); \
|
||||
"initialize not supported.\n", reg); \
|
||||
panic(); \
|
||||
} while(0)
|
||||
} while (0)
|
||||
|
||||
void rcar_qos_init(void)
|
||||
{
|
||||
|
|
@ -390,3 +390,20 @@ uint32_t get_refperiod(void)
|
|||
return refperiod;
|
||||
}
|
||||
#endif
|
||||
|
||||
void rcar_qos_dbsc_setting(struct rcar_gen3_dbsc_qos_settings *qos,
|
||||
unsigned int qos_size, bool dbsc_wren)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Register write enable */
|
||||
if (dbsc_wren)
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
|
||||
|
||||
for (i = 0; i < qos_size; i++)
|
||||
io_write_32(qos[i].reg, qos[i].val);
|
||||
|
||||
/* Register write protect */
|
||||
if (dbsc_wren)
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
|
||||
}
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QOS_REG_H
|
||||
#define QOS_REG_H
|
||||
|
||||
#define RCAR_QOS_NONE 3U
|
||||
#define RCAR_QOS_TYPE_DEFAULT 0U
|
||||
|
||||
#define RCAR_DRAM_SPLIT_LINEAR 0U
|
||||
#define RCAR_DRAM_SPLIT_4CH 1U
|
||||
#define RCAR_DRAM_SPLIT_2CH 2U
|
||||
#define RCAR_DRAM_SPLIT_AUTO 3U
|
||||
#define RST_BASE (0xE6160000U)
|
||||
#define RST_MODEMR (RST_BASE + 0x0060U)
|
||||
|
||||
#define DBSC_BASE 0xE6790000U
|
||||
#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U)
|
||||
#define DBSC_AXARB (DBSC_BASE + 0x0800U)
|
||||
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
|
||||
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
|
||||
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
|
||||
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
|
||||
#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
|
||||
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
|
||||
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
|
||||
#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U)
|
||||
#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U)
|
||||
#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U)
|
||||
#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U)
|
||||
#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU)
|
||||
#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U)
|
||||
#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U)
|
||||
#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U)
|
||||
#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU)
|
||||
#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U)
|
||||
#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U)
|
||||
#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U)
|
||||
#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU)
|
||||
#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U)
|
||||
#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U)
|
||||
#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U)
|
||||
#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU)
|
||||
#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U)
|
||||
#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U)
|
||||
#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U)
|
||||
#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU)
|
||||
#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U)
|
||||
#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U)
|
||||
#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U)
|
||||
#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU)
|
||||
#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U)
|
||||
#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U)
|
||||
#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U)
|
||||
#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU)
|
||||
#define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U)
|
||||
#define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U)
|
||||
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
|
||||
|
||||
#define AXI_BASE 0xE6784000U
|
||||
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
|
||||
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
|
||||
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
|
||||
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
|
||||
#define AXI_MMCR (AXI_BASE + 0x0300U)
|
||||
#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
|
||||
#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
|
||||
#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
|
||||
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
|
||||
#define ADSPLCR0_SWP 0x0CU
|
||||
|
||||
#define AXI_TR3CR 0xE67D100CU
|
||||
#define AXI_TR4CR 0xE67D1014U
|
||||
|
||||
#define QOS_BASE0 0xE67E0000U
|
||||
#define QOSBW_FIX_QOS_BANK0 (QOS_BASE0 + 0x0000U)
|
||||
#define QOSBW_FIX_QOS_BANK1 (QOS_BASE0 + 0x1000U)
|
||||
#define QOSBW_BE_QOS_BANK0 (QOS_BASE0 + 0x2000U)
|
||||
#define QOSBW_BE_QOS_BANK1 (QOS_BASE0 + 0x3000U)
|
||||
#define QOSCTRL_SL_INIT (QOS_BASE0 + 0x8000U)
|
||||
#define QOSCTRL_REF_ARS (QOS_BASE0 + 0x8004U)
|
||||
#define QOSCTRL_STATQC (QOS_BASE0 + 0x8008U)
|
||||
|
||||
#define QOS_BASE1 0xE67F0000U
|
||||
#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U)
|
||||
#define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U)
|
||||
#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U)
|
||||
#define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U)
|
||||
#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U)
|
||||
#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U)
|
||||
#define QOSCTRL_EC (QOS_BASE1 + 0x003CU)
|
||||
#define QOSCTRL_EMS (QOS_BASE1 + 0x0040U)
|
||||
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
|
||||
#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U)
|
||||
#define QOSCTRL_BERR (QOS_BASE1 + 0x0054U)
|
||||
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
|
||||
#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U)
|
||||
#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U)
|
||||
|
||||
#define GPU_ACT_GRD 0xFD820808U
|
||||
#define GPU_ACT0 0xFD820800U
|
||||
#define GPU_ACT1 0xFD821800U
|
||||
#define GPU_ACT2 0xFD822800U
|
||||
#define GPU_ACT3 0xFD823800U
|
||||
#define GPU_ACT4 0xFD824800U
|
||||
#define GPU_ACT5 0xFD825800U
|
||||
#define GPU_ACT6 0xFD826800U
|
||||
#define GPU_ACT7 0xFD827800U
|
||||
|
||||
#define RT_ACT0 0xFFC50800U
|
||||
#define RT_ACT1 0xFFC51800U
|
||||
|
||||
#define CPU_ACT0 0xF1300800U
|
||||
#define CPU_ACT1 0xF1340800U
|
||||
#define CPU_ACT2 0xF1380800U
|
||||
#define CPU_ACT3 0xF13C0800U
|
||||
|
||||
#define RCAR_REWT_TRAINING_DISABLE 0U
|
||||
#define RCAR_REWT_TRAINING_ENABLE 1U
|
||||
|
||||
#define QOSWT_FIX_WTQOS_BANK0 (QOSBW_FIX_QOS_BANK0 + 0x0800U)
|
||||
#define QOSWT_FIX_WTQOS_BANK1 (QOSBW_FIX_QOS_BANK1 + 0x0800U)
|
||||
#define QOSWT_BE_WTQOS_BANK0 (QOSBW_BE_QOS_BANK0 + 0x0800U)
|
||||
#define QOSWT_BE_WTQOS_BANK1 (QOSBW_BE_QOS_BANK1 + 0x0800U)
|
||||
#define QOSWT_WTEN (QOS_BASE0 + 0x8030U)
|
||||
#define QOSWT_WTREF (QOS_BASE0 + 0x8034U)
|
||||
#define QOSWT_WTSET0 (QOS_BASE0 + 0x8038U)
|
||||
#define QOSWT_WTSET1 (QOS_BASE0 + 0x803CU)
|
||||
|
||||
#endif /* QOS_REG_H */
|
||||
|
|
@ -1,11 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <console_macros.S>
|
||||
#include <drivers/renesas/rcar/console/console.h>
|
||||
|
||||
#define SCIF_INTERNAL_CLK 0
|
||||
#define SCIF_EXTARNAL_CLK 1
|
||||
|
|
@ -116,49 +118,49 @@
|
|||
#define CKS_XIN_SCIF_CLK (0x0000)
|
||||
#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK)
|
||||
|
||||
.globl console_init
|
||||
.globl console_uninit
|
||||
.globl console_putc
|
||||
.globl console_core_init
|
||||
.globl console_core_putc
|
||||
.globl console_getc
|
||||
.globl console_flush
|
||||
.globl console_rcar_register
|
||||
.globl console_rcar_init
|
||||
.globl console_rcar_putc
|
||||
.globl console_rcar_flush
|
||||
|
||||
/*
|
||||
* The console base is in the data section and not in .bss
|
||||
* even though it is zero-init. In particular, this allows
|
||||
* the console functions to start using this variable before
|
||||
* the runtime memory is initialized for images which do not
|
||||
* need to copy the .data section from ROM to RAM.
|
||||
*/
|
||||
/* -----------------------------------------------
|
||||
* int console_init(unsigned long base_addr,
|
||||
* unsigned int uart_clk, unsigned int baud_rate)
|
||||
* Function to initialize the console without a
|
||||
* C Runtime to print debug information. It saves
|
||||
* the console base to the data section.
|
||||
* In: x0 - console base address
|
||||
* w1 - Uart clock in Hz
|
||||
* int console_rcar_register(
|
||||
* uintptr_t base, uint32_t clk, uint32_t baud,
|
||||
* console_rcar_t *console)
|
||||
* Function to initialize and register a new rcar
|
||||
* console. Storage passed in for the console struct
|
||||
* *must* be persistent (i.e. not from the stack).
|
||||
* In: x0 - UART register base address
|
||||
* w1 - UART clock in Hz
|
||||
* w2 - Baud rate
|
||||
* out: return 1 on success.
|
||||
* Clobber list : x1 - x3
|
||||
* x3 - pointer to empty console_rcar_t struct
|
||||
* Out: return 1 on success, 0 on error
|
||||
* Clobber list : x0, x1, x2, x6, x7, x14
|
||||
* -----------------------------------------------
|
||||
*/
|
||||
func console_init
|
||||
b console_core_init
|
||||
endfunc console_init
|
||||
func console_rcar_register
|
||||
mov x7, x30
|
||||
mov x6, x3
|
||||
cbz x6, register_fail
|
||||
str x0, [x6, #CONSOLE_T_RCAR_BASE]
|
||||
|
||||
func console_uninit
|
||||
ret
|
||||
endfunc console_uninit
|
||||
bl console_rcar_init
|
||||
|
||||
mov x0, x6
|
||||
mov x30, x7
|
||||
finish_console_register rcar, putc=1, getc=0, flush=1
|
||||
|
||||
register_fail:
|
||||
ret x7
|
||||
endfunc console_rcar_register
|
||||
|
||||
/* -----------------------------------------------
|
||||
* int console_core_init(unsigned long base_addr,
|
||||
* int console_rcar_init(unsigned long base_addr,
|
||||
* unsigned int uart_clk, unsigned int baud_rate)
|
||||
* Function to initialize the console without a
|
||||
* C Runtime to print debug information. This
|
||||
* function will be accessed by console_init and
|
||||
* crash reporting.
|
||||
* function will be accessed by console_rcar_register
|
||||
* and crash reporting.
|
||||
* In: x0 - console base address
|
||||
* w1 - Uart clock in Hz
|
||||
* w2 - Baud rate
|
||||
|
|
@ -166,7 +168,7 @@ endfunc console_uninit
|
|||
* Clobber list : x1, x2
|
||||
* -----------------------------------------------
|
||||
*/
|
||||
func console_core_init
|
||||
func console_rcar_init
|
||||
ldr x0, =CPG_BASE
|
||||
ldr w1, [x0, #CPG_SMSTPCR]
|
||||
and w1, w1, #~MSTP
|
||||
|
|
@ -261,33 +263,19 @@ func console_core_init
|
|||
mov x0, #1
|
||||
|
||||
ret
|
||||
endfunc console_core_init
|
||||
|
||||
/* ---------------------------------------------
|
||||
* int console_putc(int c)
|
||||
* Function to output a character over the
|
||||
* console. It returns the character printed on
|
||||
* success or -1 on error.
|
||||
* In : x0 - character to be printed
|
||||
* Out : return -1 on error else return character.
|
||||
* Clobber list : x1, x2
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func console_putc
|
||||
b console_core_putc
|
||||
endfunc console_putc
|
||||
endfunc console_rcar_init
|
||||
|
||||
/* --------------------------------------------------------
|
||||
* int console_core_putc(int c, unsigned int base_addr)
|
||||
* int console_rcar_putc(int c, unsigned int base_addr)
|
||||
* Function to output a character over the console. It
|
||||
* returns the character printed on success or -1 on error.
|
||||
* In : w0 - character to be printed
|
||||
* x1 - console base address
|
||||
* x1 - pointer to console_t structure
|
||||
* Out : return -1 on error else return character.
|
||||
* Clobber list : x2
|
||||
* --------------------------------------------------------
|
||||
*/
|
||||
func console_core_putc
|
||||
func console_rcar_putc
|
||||
ldr x1, =SCIF_BASE
|
||||
cmp w0, #0xA
|
||||
/* Prepend '\r' to '\n' */
|
||||
|
|
@ -314,23 +302,10 @@ func console_core_putc
|
|||
strh w2, [x1, #SCIF_SCFSR]
|
||||
|
||||
ret
|
||||
endfunc console_core_putc
|
||||
endfunc console_rcar_putc
|
||||
|
||||
/* ---------------------------------------------
|
||||
* int console_getc(void)
|
||||
* Function to get a character from the console.
|
||||
* It returns the character grabbed on success
|
||||
* or -1 on error.
|
||||
* Clobber list : x0, x1
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func console_getc
|
||||
mov w0, #-1
|
||||
ret
|
||||
endfunc console_getc
|
||||
|
||||
/* ---------------------------------------------
|
||||
* int console_flush(void)
|
||||
* int console_rcar_flush(void)
|
||||
* Function to force a write of all buffered
|
||||
* data that hasn't been output. It returns 0
|
||||
* upon successful completion, otherwise it
|
||||
|
|
@ -338,7 +313,7 @@ endfunc console_getc
|
|||
* Clobber list : x0, x1
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func console_flush
|
||||
func console_rcar_flush
|
||||
ldr x0, =SCIF_BASE
|
||||
1:
|
||||
/* Check TEND flag */
|
||||
|
|
@ -354,4 +329,4 @@ func console_flush
|
|||
|
||||
mov w0, #0
|
||||
ret
|
||||
endfunc console_flush
|
||||
endfunc console_rcar_flush
|
||||
|
|
|
|||
|
|
@ -1,581 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <common/debug.h>
|
||||
#include "qos_init_d3.h"
|
||||
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.05"
|
||||
|
||||
#define RCAR_QOS_NONE (3U)
|
||||
#define RCAR_QOS_TYPE_DEFAULT (0U)
|
||||
|
||||
#define RCAR_DRAM_SPLIT_LINEAR (0U)
|
||||
#define RCAR_DRAM_SPLIT_4CH (1U)
|
||||
#define RCAR_DRAM_SPLIT_2CH (2U)
|
||||
#define RCAR_DRAM_SPLIT_AUTO (3U)
|
||||
|
||||
#define RST_BASE (0xE6160000U)
|
||||
#define RST_MODEMR (RST_BASE + 0x0060U)
|
||||
|
||||
#define DBSC_BASE (0xE6790000U)
|
||||
#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U)
|
||||
#define DBSC_AXARB (DBSC_BASE + 0x0800U)
|
||||
#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
|
||||
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
|
||||
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
|
||||
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
|
||||
#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
|
||||
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
|
||||
#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
|
||||
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
|
||||
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
|
||||
#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U)
|
||||
#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
|
||||
#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
|
||||
#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
|
||||
#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
|
||||
#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
|
||||
#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
|
||||
#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
|
||||
#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
|
||||
#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
|
||||
#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
|
||||
#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
|
||||
#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
|
||||
#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
|
||||
#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
|
||||
#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
|
||||
#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
|
||||
#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
|
||||
#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
|
||||
#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
|
||||
#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
|
||||
#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
|
||||
#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
|
||||
#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
|
||||
#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
|
||||
#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
|
||||
#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
|
||||
#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
|
||||
#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
|
||||
#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
|
||||
#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
|
||||
#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
|
||||
#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
|
||||
#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
|
||||
#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
|
||||
#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
|
||||
#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
|
||||
#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
|
||||
#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
|
||||
#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
|
||||
#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
|
||||
#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
|
||||
#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
|
||||
#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
|
||||
#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
|
||||
#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
|
||||
#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
|
||||
#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
|
||||
#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
|
||||
#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
|
||||
#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
|
||||
#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
|
||||
#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
|
||||
#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
|
||||
#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
|
||||
#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
|
||||
#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
|
||||
#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
|
||||
#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
|
||||
#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
|
||||
#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
|
||||
#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
|
||||
#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
|
||||
#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
|
||||
#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
|
||||
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
|
||||
|
||||
#define AXI_BASE (0xE6784000U)
|
||||
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
|
||||
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
|
||||
|
||||
#define MSTAT_BASE (0xE67E0000U)
|
||||
#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
|
||||
#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
|
||||
#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
|
||||
#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
|
||||
#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
|
||||
#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
|
||||
#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
|
||||
|
||||
#define RALLOC_BASE (0xE67F0000U)
|
||||
#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
|
||||
#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
|
||||
#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
|
||||
#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
|
||||
#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
|
||||
#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
|
||||
#define RALLOC_EC (RALLOC_BASE + 0x003CU)
|
||||
#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
|
||||
#define RALLOC_FSS (RALLOC_BASE + 0x0048U)
|
||||
#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
|
||||
#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
|
||||
#define RALLOC_EARLYR (RALLOC_BASE + 0x0060U)
|
||||
#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
|
||||
#define RALLOC_TICKDUPL (RALLOC_BASE + 0x0088U)
|
||||
|
||||
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
|
||||
|
||||
static inline void io_write_32(uintptr_t addr, uint32_t value)
|
||||
{
|
||||
*(volatile uint32_t*)addr = value;
|
||||
}
|
||||
|
||||
static inline void io_write_64(uintptr_t addr, uint64_t value)
|
||||
{
|
||||
*(volatile uint64_t*)addr = value;
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
uintptr_t addr;
|
||||
uint64_t value;
|
||||
} mstat_slot_t;
|
||||
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
static const mstat_slot_t mstat_fix[] = {
|
||||
{0x0000U, 0x0000000000000000U},
|
||||
{0x0008U, 0x0000000000000000U},
|
||||
{0x0010U, 0x0000000000000000U},
|
||||
{0x0018U, 0x0000000000000000U},
|
||||
{0x0020U, 0x0000000000000000U},
|
||||
{0x0028U, 0x0000000000000000U},
|
||||
{0x0030U, 0x001004340000FFFFU},
|
||||
{0x0038U, 0x001004140000FFFFU},
|
||||
{0x0040U, 0x0000000000000000U},
|
||||
{0x0048U, 0x0000000000000000U},
|
||||
{0x0050U, 0x0000000000000000U},
|
||||
{0x0058U, 0x00140B030000FFFFU},
|
||||
{0x0060U, 0x001408610000FFFFU},
|
||||
{0x0068U, 0x0000000000000000U},
|
||||
{0x0070U, 0x0000000000000000U},
|
||||
{0x0078U, 0x0000000000000000U},
|
||||
{0x0080U, 0x0000000000000000U},
|
||||
{0x0088U, 0x001410620000FFFFU},
|
||||
{0x0090U, 0x0000000000000000U},
|
||||
{0x0098U, 0x0000000000000000U},
|
||||
{0x00A0U, 0x000C041C0000FFFFU},
|
||||
{0x00A8U, 0x000C04090000FFFFU},
|
||||
{0x00B0U, 0x000C04110000FFFFU},
|
||||
{0x00B8U, 0x0000000000000000U},
|
||||
{0x00C0U, 0x000C041C0000FFFFU},
|
||||
{0x00C8U, 0x000C04090000FFFFU},
|
||||
{0x00D0U, 0x000C04110000FFFFU},
|
||||
{0x00D8U, 0x0000000000000000U},
|
||||
{0x00E0U, 0x0000000000000000U},
|
||||
{0x00E8U, 0x0000000000000000U},
|
||||
{0x00F0U, 0x001018570000FFFFU},
|
||||
{0x00F8U, 0x0000000000000000U},
|
||||
{0x0100U, 0x0000000000000000U},
|
||||
{0x0108U, 0x0000000000000000U},
|
||||
{0x0110U, 0x001008570000FFFFU},
|
||||
{0x0118U, 0x0000000000000000U},
|
||||
{0x0120U, 0x0000000000000000U},
|
||||
{0x0128U, 0x0000000000000000U},
|
||||
{0x0130U, 0x0000000000000000U},
|
||||
{0x0138U, 0x0000000000000000U},
|
||||
{0x0140U, 0x0000000000000000U},
|
||||
{0x0148U, 0x0000000000000000U},
|
||||
{0x0150U, 0x001008520000FFFFU},
|
||||
{0x0158U, 0x0000000000000000U},
|
||||
{0x0160U, 0x0000000000000000U},
|
||||
{0x0168U, 0x0000000000000000U},
|
||||
{0x0170U, 0x0000000000000000U},
|
||||
{0x0178U, 0x0000000000000000U},
|
||||
{0x0180U, 0x0000000000000000U},
|
||||
{0x0188U, 0x0000000000000000U},
|
||||
{0x0190U, 0x00100CA30000FFFFU},
|
||||
{0x0198U, 0x0000000000000000U},
|
||||
{0x01A0U, 0x0000000000000000U},
|
||||
{0x01A8U, 0x0000000000000000U},
|
||||
{0x01B0U, 0x0000000000000000U},
|
||||
{0x01B8U, 0x0000000000000000U},
|
||||
{0x01C0U, 0x0000000000000000U},
|
||||
{0x01C8U, 0x0000000000000000U},
|
||||
{0x01D0U, 0x0000000000000000U},
|
||||
{0x01D8U, 0x0000000000000000U},
|
||||
{0x01E0U, 0x0000000000000000U},
|
||||
{0x01E8U, 0x000C04020000FFFFU},
|
||||
{0x01F0U, 0x0000000000000000U},
|
||||
{0x01F8U, 0x0000000000000000U},
|
||||
{0x0200U, 0x0000000000000000U},
|
||||
{0x0208U, 0x000C04090000FFFFU},
|
||||
{0x0210U, 0x0000000000000000U},
|
||||
{0x0218U, 0x0000000000000000U},
|
||||
{0x0220U, 0x0000000000000000U},
|
||||
{0x0228U, 0x0000000000000000U},
|
||||
{0x0230U, 0x0000000000000000U},
|
||||
{0x0238U, 0x0000000000000000U},
|
||||
{0x0240U, 0x0000000000000000U},
|
||||
{0x0248U, 0x0000000000000000U},
|
||||
{0x0250U, 0x0000000000000000U},
|
||||
{0x0258U, 0x0000000000000000U},
|
||||
{0x0260U, 0x0000000000000000U},
|
||||
{0x0268U, 0x001410040000FFFFU},
|
||||
{0x0270U, 0x001404020000FFFFU},
|
||||
{0x0278U, 0x0000000000000000U},
|
||||
{0x0280U, 0x0000000000000000U},
|
||||
{0x0288U, 0x0000000000000000U},
|
||||
{0x0290U, 0x001410040000FFFFU},
|
||||
{0x0298U, 0x001404020000FFFFU},
|
||||
{0x02A0U, 0x000C04050000FFFFU},
|
||||
{0x02A8U, 0x000C04050000FFFFU},
|
||||
{0x02B0U, 0x0000000000000000U},
|
||||
{0x02B8U, 0x0000000000000000U},
|
||||
{0x02C0U, 0x0000000000000000U},
|
||||
{0x02C8U, 0x0000000000000000U},
|
||||
{0x02D0U, 0x000C04050000FFFFU},
|
||||
{0x02D8U, 0x000C04050000FFFFU},
|
||||
{0x02E0U, 0x0000000000000000U},
|
||||
{0x02E8U, 0x0000000000000000U},
|
||||
{0x02F0U, 0x0000000000000000U},
|
||||
{0x02F8U, 0x0000000000000000U},
|
||||
{0x0300U, 0x0000000000000000U},
|
||||
{0x0308U, 0x0000000000000000U},
|
||||
{0x0310U, 0x0000000000000000U},
|
||||
{0x0318U, 0x0000000000000000U},
|
||||
{0x0320U, 0x0000000000000000U},
|
||||
{0x0328U, 0x0000000000000000U},
|
||||
{0x0330U, 0x0000000000000000U},
|
||||
{0x0338U, 0x0000000000000000U},
|
||||
{0x0340U, 0x0000000000000000U},
|
||||
{0x0348U, 0x0000000000000000U},
|
||||
{0x0350U, 0x0000000000000000U},
|
||||
{0x0358U, 0x0000000000000000U},
|
||||
{0x0360U, 0x0000000000000000U},
|
||||
{0x0368U, 0x0000000000000000U},
|
||||
{0x0370U, 0x000C04020000FFFFU},
|
||||
{0x0378U, 0x000C04020000FFFFU},
|
||||
{0x0380U, 0x000C04090000FFFFU},
|
||||
{0x0388U, 0x000C04090000FFFFU},
|
||||
{0x0390U, 0x0000000000000000U},
|
||||
};
|
||||
|
||||
static const mstat_slot_t mstat_be[] = {
|
||||
{0x0000U, 0x0000000000000000U},
|
||||
{0x0008U, 0x0000000000000000U},
|
||||
{0x0010U, 0x0000000000000000U},
|
||||
{0x0018U, 0x0000000000000000U},
|
||||
{0x0020U, 0x0000000000000000U},
|
||||
{0x0028U, 0x0000000000000000U},
|
||||
{0x0030U, 0x0000000000000000U},
|
||||
{0x0038U, 0x0000000000000000U},
|
||||
{0x0040U, 0x0000000000000000U},
|
||||
{0x0048U, 0x0000000000000000U},
|
||||
{0x0050U, 0x0000000000000000U},
|
||||
{0x0058U, 0x0000000000000000U},
|
||||
{0x0060U, 0x0000000000000000U},
|
||||
{0x0068U, 0x0000000000000000U},
|
||||
{0x0070U, 0x0000000000000000U},
|
||||
{0x0078U, 0x0000000000000000U},
|
||||
{0x0080U, 0x0000000000000000U},
|
||||
{0x0088U, 0x0000000000000000U},
|
||||
{0x0090U, 0x0000000000000000U},
|
||||
{0x0098U, 0x0000000000000000U},
|
||||
{0x00A0U, 0x0000000000000000U},
|
||||
{0x00A8U, 0x0000000000000000U},
|
||||
{0x00B0U, 0x0000000000000000U},
|
||||
{0x00B8U, 0x0000000000000000U},
|
||||
{0x00C0U, 0x0000000000000000U},
|
||||
{0x00C8U, 0x0000000000000000U},
|
||||
{0x00D0U, 0x0000000000000000U},
|
||||
{0x00D8U, 0x0000000000000000U},
|
||||
{0x00E0U, 0x0000000000000000U},
|
||||
{0x00E8U, 0x0000000000000000U},
|
||||
{0x00F0U, 0x0000000000000000U},
|
||||
{0x00F8U, 0x0000000000000000U},
|
||||
{0x0100U, 0x0000000000000000U},
|
||||
{0x0108U, 0x0000000000000000U},
|
||||
{0x0110U, 0x0000000000000000U},
|
||||
{0x0118U, 0x0000000000000000U},
|
||||
{0x0120U, 0x0000000000000000U},
|
||||
{0x0128U, 0x0000000000000000U},
|
||||
{0x0130U, 0x0000000000000000U},
|
||||
{0x0138U, 0x0000000000000000U},
|
||||
{0x0140U, 0x0000000000000000U},
|
||||
{0x0148U, 0x0000000000000000U},
|
||||
{0x0150U, 0x0000000000000000U},
|
||||
{0x0158U, 0x0000000000000000U},
|
||||
{0x0160U, 0x0000000000000000U},
|
||||
{0x0168U, 0x0000000000000000U},
|
||||
{0x0170U, 0x0000000000000000U},
|
||||
{0x0178U, 0x0000000000000000U},
|
||||
{0x0180U, 0x0000000000000000U},
|
||||
{0x0188U, 0x0000000000000000U},
|
||||
{0x0190U, 0x0000000000000000U},
|
||||
{0x0198U, 0x0000000000000000U},
|
||||
{0x01A0U, 0x0000000000000000U},
|
||||
{0x01A8U, 0x0000000000000000U},
|
||||
{0x01B0U, 0x0000000000000000U},
|
||||
{0x01B8U, 0x0000000000000000U},
|
||||
{0x01C0U, 0x00110090060FA001U},
|
||||
{0x01C8U, 0x00110090060FA001U},
|
||||
{0x01D0U, 0x0000000000000000U},
|
||||
{0x01D8U, 0x0000000000000000U},
|
||||
{0x01E0U, 0x0000000000000000U},
|
||||
{0x01E8U, 0x0000000000000000U},
|
||||
{0x01F0U, 0x0011001006004401U},
|
||||
{0x01F8U, 0x0000000000000000U},
|
||||
{0x0200U, 0x0000000000000000U},
|
||||
{0x0208U, 0x0000000000000000U},
|
||||
{0x0210U, 0x0011001006004401U},
|
||||
{0x0218U, 0x0011001006009801U},
|
||||
{0x0220U, 0x0011001006009801U},
|
||||
{0x0228U, 0x0000000000000000U},
|
||||
{0x0230U, 0x0011001006009801U},
|
||||
{0x0238U, 0x0011001006009801U},
|
||||
{0x0240U, 0x0000000000000000U},
|
||||
{0x0248U, 0x0000000000000000U},
|
||||
{0x0250U, 0x0000000000000000U},
|
||||
{0x0258U, 0x0000000000000000U},
|
||||
{0x0260U, 0x0000000000000000U},
|
||||
{0x0268U, 0x0000000000000000U},
|
||||
{0x0270U, 0x0000000000000000U},
|
||||
{0x0278U, 0x0000000000000000U},
|
||||
{0x0280U, 0x0000000000000000U},
|
||||
{0x0288U, 0x0000000000000000U},
|
||||
{0x0290U, 0x0000000000000000U},
|
||||
{0x0298U, 0x0000000000000000U},
|
||||
{0x02A0U, 0x0000000000000000U},
|
||||
{0x02A8U, 0x0000000000000000U},
|
||||
{0x02B0U, 0x0000000000000000U},
|
||||
{0x02B8U, 0x0011001006003401U},
|
||||
{0x02C0U, 0x0000000000000000U},
|
||||
{0x02C8U, 0x0000000000000000U},
|
||||
{0x02D0U, 0x0000000000000000U},
|
||||
{0x02D8U, 0x0000000000000000U},
|
||||
{0x02E0U, 0x0000000000000000U},
|
||||
{0x02E8U, 0x0011001006003401U},
|
||||
{0x02F0U, 0x00110090060FA001U},
|
||||
{0x02F8U, 0x00110090060FA001U},
|
||||
{0x0300U, 0x0000000000000000U},
|
||||
{0x0308U, 0x0000000000000000U},
|
||||
{0x0310U, 0x0000000000000000U},
|
||||
{0x0318U, 0x0012001006003401U},
|
||||
{0x0320U, 0x0000000000000000U},
|
||||
{0x0328U, 0x0000000000000000U},
|
||||
{0x0330U, 0x0000000000000000U},
|
||||
{0x0338U, 0x0000000000000000U},
|
||||
{0x0340U, 0x0000000000000000U},
|
||||
{0x0348U, 0x0000000000000000U},
|
||||
{0x0350U, 0x0000000000000000U},
|
||||
{0x0358U, 0x00120090060FA001U},
|
||||
{0x0360U, 0x00120090060FA001U},
|
||||
{0x0368U, 0x0012001006003401U},
|
||||
{0x0370U, 0x0000000000000000U},
|
||||
{0x0378U, 0x0000000000000000U},
|
||||
{0x0380U, 0x0000000000000000U},
|
||||
{0x0388U, 0x0000000000000000U},
|
||||
{0x0390U, 0x0012001006003401U},
|
||||
};
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
uint32_t md=0;
|
||||
|
||||
/* BUFCAM settings */
|
||||
//DBSC_DBCAM0CNF0 not set
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00043218); //dbcam0cnf1
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x000F0037); //dbschcnt0
|
||||
//DBSC_DBSCHCNT1 not set
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0
|
||||
|
||||
md = (*((volatile uint32_t*)RST_MODEMR) & 0x00080000) >> 19;
|
||||
|
||||
switch (md) {
|
||||
case 0x0: //MD19=0 : DDR3L-1600, 4GByte(1GByte x4)
|
||||
/* DDR1600 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
default: //MD19=1 : DDR3L-1856, 4GByte(1GByte x4)
|
||||
/* DDR1856 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
}
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS_0_0, 0x00000F00);
|
||||
io_write_32(DBSC_DBSCHQOS_0_1, 0x00000B00);
|
||||
io_write_32(DBSC_DBSCHQOS_0_2, 0x00000000);
|
||||
io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
|
||||
//DBSC_DBSCHQOS_1_0 not set
|
||||
//DBSC_DBSCHQOS_1_1 not set
|
||||
//DBSC_DBSCHQOS_1_2 not set
|
||||
//DBSC_DBSCHQOS_1_3 not set
|
||||
//DBSC_DBSCHQOS_2_0 not set
|
||||
//DBSC_DBSCHQOS_2_1 not set
|
||||
//DBSC_DBSCHQOS_2_2 not set
|
||||
//DBSC_DBSCHQOS_2_3 not set
|
||||
//DBSC_DBSCHQOS_3_0 not set
|
||||
//DBSC_DBSCHQOS_3_1 not set
|
||||
//DBSC_DBSCHQOS_3_2 not set
|
||||
//DBSC_DBSCHQOS_3_3 not set
|
||||
io_write_32(DBSC_DBSCHQOS_4_0, 0x00000300);
|
||||
io_write_32(DBSC_DBSCHQOS_4_1, 0x000002F0);
|
||||
io_write_32(DBSC_DBSCHQOS_4_2, 0x00000200);
|
||||
io_write_32(DBSC_DBSCHQOS_4_3, 0x00000100);
|
||||
//DBSC_DBSCHQOS_5_0 not set
|
||||
//DBSC_DBSCHQOS_5_1 not set
|
||||
//DBSC_DBSCHQOS_5_2 not set
|
||||
//DBSC_DBSCHQOS_5_3 not set
|
||||
//DBSC_DBSCHQOS_6_0 not set
|
||||
//DBSC_DBSCHQOS_6_1 not set
|
||||
//DBSC_DBSCHQOS_6_2 not set
|
||||
//DBSC_DBSCHQOS_6_3 not set
|
||||
//DBSC_DBSCHQOS_7_0 not set
|
||||
//DBSC_DBSCHQOS_7_1 not set
|
||||
//DBSC_DBSCHQOS_7_2 not set
|
||||
//DBSC_DBSCHQOS_7_3 not set
|
||||
//DBSC_DBSCHQOS_8_0 not set
|
||||
//DBSC_DBSCHQOS_8_1 not set
|
||||
//DBSC_DBSCHQOS_8_2 not set
|
||||
//DBSC_DBSCHQOS_8_3 not set
|
||||
io_write_32(DBSC_DBSCHQOS_9_0, 0x00000300);
|
||||
io_write_32(DBSC_DBSCHQOS_9_1, 0x000002F0);
|
||||
io_write_32(DBSC_DBSCHQOS_9_2, 0x00000200);
|
||||
io_write_32(DBSC_DBSCHQOS_9_3, 0x00000100);
|
||||
//DBSC_DBSCHQOS_10_0 not set
|
||||
//DBSC_DBSCHQOS_10_1 not set
|
||||
//DBSC_DBSCHQOS_10_2 not set
|
||||
//DBSC_DBSCHQOS_10_3 not set
|
||||
//DBSC_DBSCHQOS_11_0 not set
|
||||
//DBSC_DBSCHQOS_11_1 not set
|
||||
//DBSC_DBSCHQOS_11_2 not set
|
||||
//DBSC_DBSCHQOS_11_3 not set
|
||||
//DBSC_DBSCHQOS_12_0 not set
|
||||
//DBSC_DBSCHQOS_12_1 not set
|
||||
//DBSC_DBSCHQOS_12_2 not set
|
||||
//DBSC_DBSCHQOS_12_3 not set
|
||||
io_write_32(DBSC_DBSCHQOS_13_0, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS_13_1, 0x000000F0);
|
||||
io_write_32(DBSC_DBSCHQOS_13_2, 0x000000A0);
|
||||
io_write_32(DBSC_DBSCHQOS_13_3, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS_14_0, 0x000000C0);
|
||||
io_write_32(DBSC_DBSCHQOS_14_1, 0x000000B0);
|
||||
io_write_32(DBSC_DBSCHQOS_14_2, 0x00000080);
|
||||
io_write_32(DBSC_DBSCHQOS_14_3, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS_15_0, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS_15_1, 0x00000030);
|
||||
io_write_32(DBSC_DBSCHQOS_15_2, 0x00000020);
|
||||
io_write_32(DBSC_DBSCHQOS_15_3, 0x00000010);
|
||||
}
|
||||
|
||||
void qos_init_d3(void)
|
||||
{
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00001234);
|
||||
|
||||
dbsc_setting();
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
|
||||
ERROR("DRAM Split 4ch not supported.(D3)");
|
||||
panic();
|
||||
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
|
||||
ERROR("DRAM Split 2ch not supported.(D3)");
|
||||
panic();
|
||||
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO
|
||||
ERROR("DRAM Split Auto not supported.(D3)");
|
||||
panic();
|
||||
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_LINEAR
|
||||
/* NOTICE("BL2: DRAM Split is OFF\n"); */
|
||||
/* Split setting(DDR 1ch) */
|
||||
io_write_32(AXI_ADSPLCR0, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#else
|
||||
ERROR("DRAM split is an invalid value.(D3)");
|
||||
panic();
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(RALLOC_RAS, 0x00000020U);
|
||||
io_write_32(RALLOC_FIXTH, 0x000F0005U);
|
||||
io_write_32(RALLOC_RAEN, 0x00000001U);
|
||||
io_write_32(RALLOC_REGGD, 0x00000000U);
|
||||
io_write_64(RALLOC_DANN, 0x0404020002020201U);
|
||||
io_write_32(RALLOC_DANT, 0x00100804U);
|
||||
io_write_32(RALLOC_EC, 0x00000000U);
|
||||
io_write_64(RALLOC_EMS, 0x0000000000000000U);
|
||||
io_write_32(RALLOC_FSS, 0x0000000AU);
|
||||
io_write_32(RALLOC_INSFC, 0xC7840001U);
|
||||
io_write_32(RALLOC_BERR, 0x00000000U);
|
||||
io_write_32(RALLOC_EARLYR, 0x00000000U);
|
||||
io_write_32(RALLOC_RACNT0, 0x00010003U);
|
||||
io_write_32(RALLOC_TICKDUPL, 0x00000000U);
|
||||
|
||||
/* GPU setting */
|
||||
io_write_32(0xFD812030U, 0x00000000U);
|
||||
|
||||
/* MSTAT setting */
|
||||
io_write_32(MSTAT_SL_INIT, 0x030500ACU);
|
||||
io_write_32(MSTAT_REF_ARS, 0x00780000U);
|
||||
|
||||
/* MSTAT SRAM setting */
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
}
|
||||
}
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
io_write_32(0xFD820808U, 0x00001234U);
|
||||
io_write_32(0xFD820800U, 0x00000000U);
|
||||
io_write_32(0xFD821800U, 0x00000000U);
|
||||
io_write_32(0xFD822800U, 0x00000000U);
|
||||
io_write_32(0xFD823800U, 0x00000000U);
|
||||
|
||||
/* RT bus Leaf setting */
|
||||
io_write_32(0xF1300800U, 0x00000003U);
|
||||
io_write_32(0xF1340800U, 0x00000003U);
|
||||
io_write_32(0xFFC50800U, 0x00000000U);
|
||||
io_write_32(0xFFC51800U, 0x00000000U);
|
||||
|
||||
/* Resource Alloc start */
|
||||
io_write_32(RALLOC_RAEN, 0x00000001U);
|
||||
|
||||
/* MSTAT start */
|
||||
io_write_32(MSTAT_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(RALLOC_EC, 0x00000000U);
|
||||
/* Resource Alloc start */
|
||||
io_write_32(RALLOC_RAEN, 0x00000001U);
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00000000);
|
||||
}
|
||||
|
|
@ -1,359 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
|
||||
#include "../qos_common.h"
|
||||
#include "qos_init_h3_v10.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.36"
|
||||
|
||||
#define RCAR_QOS_NONE (3U)
|
||||
#define RCAR_QOS_TYPE_DEFAULT (0U)
|
||||
|
||||
#define RCAR_DRAM_SPLIT_LINEAR (0U)
|
||||
#define RCAR_DRAM_SPLIT_4CH (1U)
|
||||
#define RCAR_DRAM_SPLIT_2CH (2U)
|
||||
#define RCAR_DRAM_SPLIT_AUTO (3U)
|
||||
|
||||
#define AXI_BASE (0xE6784000U)
|
||||
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
|
||||
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
|
||||
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
|
||||
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
|
||||
#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
|
||||
#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
|
||||
#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
|
||||
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
|
||||
#define ADSPLCR0_SWP (0x0CU)
|
||||
|
||||
#define MSTAT_BASE (0xE67E0000U)
|
||||
#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
|
||||
#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
|
||||
#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
|
||||
#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
|
||||
#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
|
||||
#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
|
||||
#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
|
||||
|
||||
#define RALLOC_BASE (0xE67F0000U)
|
||||
#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
|
||||
#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
|
||||
#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
|
||||
#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
|
||||
#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
|
||||
#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
|
||||
#define RALLOC_EC (RALLOC_BASE + 0x003CU)
|
||||
#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
|
||||
#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
|
||||
#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
static const mstat_slot_t mstat_fix[] = {
|
||||
{0x0000U, 0x0000000000000000UL},
|
||||
{0x0008U, 0x0000000000000000UL},
|
||||
{0x0010U, 0x0000000000000000UL},
|
||||
{0x0018U, 0x0000000000000000UL},
|
||||
{0x0020U, 0x0000000000000000UL},
|
||||
{0x0028U, 0x0000000000000000UL},
|
||||
{0x0030U, 0x0000000000000000UL},
|
||||
{0x0038U, 0x0000000000000000UL},
|
||||
{0x0040U, 0x00140C050000FFFFUL},
|
||||
{0x0048U, 0x0000000000000000UL},
|
||||
{0x0050U, 0x0000000000000000UL},
|
||||
{0x0058U, 0x001404030000FFFFUL},
|
||||
{0x0060U, 0x001408060000FFFFUL},
|
||||
{0x0068U, 0x0000000000000000UL},
|
||||
{0x0070U, 0x0000000000000000UL},
|
||||
{0x0078U, 0x0000000000000000UL},
|
||||
{0x0080U, 0x0000000000000000UL},
|
||||
{0x0088U, 0x00140C050000FFFFUL},
|
||||
{0x0090U, 0x001408060000FFFFUL},
|
||||
{0x0098U, 0x001404020000FFFFUL},
|
||||
{0x00A0U, 0x0000000000000000UL},
|
||||
{0x00A8U, 0x0000000000000000UL},
|
||||
{0x00B0U, 0x0000000000000000UL},
|
||||
{0x00B8U, 0x0000000000000000UL},
|
||||
{0x00C0U, 0x0000000000000000UL},
|
||||
{0x00C8U, 0x0000000000000000UL},
|
||||
{0x00D0U, 0x0000000000000000UL},
|
||||
{0x00D8U, 0x0000000000000000UL},
|
||||
{0x00E0U, 0x0000000000000000UL},
|
||||
{0x00E8U, 0x0000000000000000UL},
|
||||
{0x00F0U, 0x0000000000000000UL},
|
||||
{0x00F8U, 0x0000000000000000UL},
|
||||
{0x0100U, 0x0000000000000000UL},
|
||||
{0x0108U, 0x0000000000000000UL},
|
||||
{0x0110U, 0x0000000000000000UL},
|
||||
{0x0118U, 0x0000000000000000UL},
|
||||
{0x0120U, 0x0000000000000000UL},
|
||||
{0x0128U, 0x0000000000000000UL},
|
||||
{0x0130U, 0x0000000000000000UL},
|
||||
{0x0138U, 0x001004020000FFFFUL},
|
||||
{0x0140U, 0x001004020000FFFFUL},
|
||||
{0x0148U, 0x001004020000FFFFUL},
|
||||
{0x0150U, 0x001008050000FFFFUL},
|
||||
{0x0158U, 0x001008050000FFFFUL},
|
||||
{0x0160U, 0x001008050000FFFFUL},
|
||||
{0x0168U, 0x001008050000FFFFUL},
|
||||
{0x0170U, 0x001008050000FFFFUL},
|
||||
{0x0178U, 0x001004030000FFFFUL},
|
||||
{0x0180U, 0x001004030000FFFFUL},
|
||||
{0x0188U, 0x001004030000FFFFUL},
|
||||
{0x0190U, 0x001014140000FFFFUL},
|
||||
{0x0198U, 0x001014140000FFFFUL},
|
||||
{0x01A0U, 0x001008060000FFFFUL},
|
||||
{0x01A8U, 0x001008060000FFFFUL},
|
||||
{0x01B0U, 0x001008060000FFFFUL},
|
||||
{0x01B8U, 0x0000000000000000UL},
|
||||
{0x01C0U, 0x0000000000000000UL},
|
||||
{0x01C8U, 0x0000000000000000UL},
|
||||
{0x01D0U, 0x0000000000000000UL},
|
||||
{0x01D8U, 0x0000000000000000UL},
|
||||
{0x01E0U, 0x0000000000000000UL},
|
||||
{0x01E8U, 0x0000000000000000UL},
|
||||
{0x01F0U, 0x0000000000000000UL},
|
||||
{0x01F8U, 0x0000000000000000UL},
|
||||
{0x0200U, 0x0000000000000000UL},
|
||||
{0x0208U, 0x0000000000000000UL},
|
||||
{0x0210U, 0x0000000000000000UL},
|
||||
{0x0218U, 0x0000000000000000UL},
|
||||
{0x0220U, 0x0000000000000000UL},
|
||||
{0x0228U, 0x0000000000000000UL},
|
||||
{0x0230U, 0x0000000000000000UL},
|
||||
{0x0238U, 0x0000000000000000UL},
|
||||
{0x0240U, 0x0000000000000000UL},
|
||||
{0x0248U, 0x0000000000000000UL},
|
||||
{0x0250U, 0x0000000000000000UL},
|
||||
{0x0258U, 0x0000000000000000UL},
|
||||
{0x0260U, 0x0000000000000000UL},
|
||||
{0x0268U, 0x0000000000000000UL},
|
||||
{0x0270U, 0x0000000000000000UL},
|
||||
{0x0278U, 0x0000000000000000UL},
|
||||
{0x0280U, 0x0000000000000000UL},
|
||||
{0x0288U, 0x0000000000000000UL},
|
||||
{0x0290U, 0x0000000000000000UL},
|
||||
{0x0298U, 0x0000000000000000UL},
|
||||
{0x02A0U, 0x0000000000000000UL},
|
||||
{0x02A8U, 0x0000000000000000UL},
|
||||
{0x02B0U, 0x0000000000000000UL},
|
||||
{0x02B8U, 0x0000000000000000UL},
|
||||
{0x02C0U, 0x0000000000000000UL},
|
||||
{0x02C8U, 0x0000000000000000UL},
|
||||
{0x02D0U, 0x0000000000000000UL},
|
||||
{0x02D8U, 0x0000000000000000UL},
|
||||
{0x02E0U, 0x0000000000000000UL},
|
||||
{0x02E8U, 0x0000000000000000UL},
|
||||
{0x02F0U, 0x0000000000000000UL},
|
||||
{0x02F8U, 0x0000000000000000UL},
|
||||
{0x0300U, 0x0000000000000000UL},
|
||||
{0x0308U, 0x0000000000000000UL},
|
||||
{0x0310U, 0x0000000000000000UL},
|
||||
{0x0318U, 0x0000000000000000UL},
|
||||
{0x0320U, 0x0000000000000000UL},
|
||||
{0x0328U, 0x0000000000000000UL},
|
||||
{0x0330U, 0x0000000000000000UL},
|
||||
{0x0338U, 0x0000000000000000UL},
|
||||
};
|
||||
|
||||
static const mstat_slot_t mstat_be[] = {
|
||||
{0x0000U, 0x001000100C8FFC01UL},
|
||||
{0x0008U, 0x001000100C8FFC01UL},
|
||||
{0x0010U, 0x001000100C8FFC01UL},
|
||||
{0x0018U, 0x001000100C8FFC01UL},
|
||||
{0x0020U, 0x001000100C8FFC01UL},
|
||||
{0x0028U, 0x001000100C8FFC01UL},
|
||||
{0x0030U, 0x001000100C8FFC01UL},
|
||||
{0x0038U, 0x001000100C8FFC01UL},
|
||||
{0x0040U, 0x0000000000000000UL},
|
||||
{0x0048U, 0x0000000000000000UL},
|
||||
{0x0050U, 0x001000100C8FFC01UL},
|
||||
{0x0058U, 0x0000000000000000UL},
|
||||
{0x0060U, 0x0000000000000000UL},
|
||||
{0x0068U, 0x001000100C8FFC01UL},
|
||||
{0x0070U, 0x001000100C8FFC01UL},
|
||||
{0x0078U, 0x001000100C8FFC01UL},
|
||||
{0x0080U, 0x001000100C8FFC01UL},
|
||||
{0x0088U, 0x0000000000000000UL},
|
||||
{0x0090U, 0x0000000000000000UL},
|
||||
{0x0098U, 0x0000000000000000UL},
|
||||
{0x00A0U, 0x001000100C8FFC01UL},
|
||||
{0x00A8U, 0x001000100C8FFC01UL},
|
||||
{0x00B0U, 0x001000100C8FFC01UL},
|
||||
{0x00B8U, 0x001000100C8FFC01UL},
|
||||
{0x00C0U, 0x001000100C8FFC01UL},
|
||||
{0x00C8U, 0x001000100C8FFC01UL},
|
||||
{0x00D0U, 0x001000100C8FFC01UL},
|
||||
{0x00D8U, 0x002000200C8FFC01UL},
|
||||
{0x00E0U, 0x002000200C8FFC01UL},
|
||||
{0x00E8U, 0x001000100C8FFC01UL},
|
||||
{0x00F0U, 0x001000100C8FFC01UL},
|
||||
{0x00F8U, 0x001000100C8FFC01UL},
|
||||
{0x0100U, 0x0000000000000000UL},
|
||||
{0x0108U, 0x002000200C8FFC01UL},
|
||||
{0x0110U, 0x001000100C8FFC01UL},
|
||||
{0x0118U, 0x001000100C8FFC01UL},
|
||||
{0x0120U, 0x0000000000000000UL},
|
||||
{0x0128U, 0x002000200C8FFC01UL},
|
||||
{0x0130U, 0x001000100C8FFC01UL},
|
||||
{0x0138U, 0x0000000000000000UL},
|
||||
{0x0140U, 0x0000000000000000UL},
|
||||
{0x0148U, 0x0000000000000000UL},
|
||||
{0x0150U, 0x0000000000000000UL},
|
||||
{0x0158U, 0x0000000000000000UL},
|
||||
{0x0160U, 0x0000000000000000UL},
|
||||
{0x0168U, 0x0000000000000000UL},
|
||||
{0x0170U, 0x0000000000000000UL},
|
||||
{0x0178U, 0x0000000000000000UL},
|
||||
{0x0180U, 0x0000000000000000UL},
|
||||
{0x0188U, 0x0000000000000000UL},
|
||||
{0x0190U, 0x0000000000000000UL},
|
||||
{0x0198U, 0x0000000000000000UL},
|
||||
{0x01A0U, 0x0000000000000000UL},
|
||||
{0x01A8U, 0x0000000000000000UL},
|
||||
{0x01B0U, 0x0000000000000000UL},
|
||||
{0x01B8U, 0x001000100C8FFC01UL},
|
||||
{0x01C0U, 0x001000200C8FFC01UL},
|
||||
{0x01C8U, 0x001000200C8FFC01UL},
|
||||
{0x01D0U, 0x001000200C8FFC01UL},
|
||||
{0x01D8U, 0x001000200C8FFC01UL},
|
||||
{0x01E0U, 0x001000100C8FFC01UL},
|
||||
{0x01E8U, 0x001000100C8FFC01UL},
|
||||
{0x01F0U, 0x001000100C8FFC01UL},
|
||||
{0x01F8U, 0x001000100C8FFC01UL},
|
||||
{0x0200U, 0x001000100C8FFC01UL},
|
||||
{0x0208U, 0x001000100C8FFC01UL},
|
||||
{0x0210U, 0x001000100C8FFC01UL},
|
||||
{0x0218U, 0x001000100C8FFC01UL},
|
||||
{0x0220U, 0x001000100C8FFC01UL},
|
||||
{0x0228U, 0x001000100C8FFC01UL},
|
||||
{0x0230U, 0x001000100C8FFC01UL},
|
||||
{0x0238U, 0x001000100C8FFC01UL},
|
||||
{0x0240U, 0x001000100C8FFC01UL},
|
||||
{0x0248U, 0x001000100C8FFC01UL},
|
||||
{0x0250U, 0x001000100C8FFC01UL},
|
||||
{0x0258U, 0x001000100C8FFC01UL},
|
||||
{0x0260U, 0x001000100C8FFC01UL},
|
||||
{0x0268U, 0x001000100C8FFC01UL},
|
||||
{0x0270U, 0x001000100C8FFC01UL},
|
||||
{0x0278U, 0x001000100C8FFC01UL},
|
||||
{0x0280U, 0x001000100C8FFC01UL},
|
||||
{0x0288U, 0x001000100C8FFC01UL},
|
||||
{0x0290U, 0x001000100C8FFC01UL},
|
||||
{0x0298U, 0x001000100C8FFC01UL},
|
||||
{0x02A0U, 0x001000100C8FFC01UL},
|
||||
{0x02A8U, 0x001000100C8FFC01UL},
|
||||
{0x02B0U, 0x001000100C8FFC01UL},
|
||||
{0x02B8U, 0x001000100C8FFC01UL},
|
||||
{0x02C0U, 0x001000100C8FFC01UL},
|
||||
{0x02C8U, 0x001000100C8FFC01UL},
|
||||
{0x02D0U, 0x001000100C8FFC01UL},
|
||||
{0x02D8U, 0x001000100C8FFC01UL},
|
||||
{0x02E0U, 0x001000100C8FFC01UL},
|
||||
{0x02E8U, 0x001000100C8FFC01UL},
|
||||
{0x02F0U, 0x001000200C8FFC01UL},
|
||||
{0x02F8U, 0x001000300C8FFC01UL},
|
||||
{0x0300U, 0x0000000000000000UL},
|
||||
{0x0308U, 0x001000200C8FFC01UL},
|
||||
{0x0310U, 0x001000300C8FFC01UL},
|
||||
{0x0318U, 0x0000000000000000UL},
|
||||
{0x0320U, 0x001000200C8FFC01UL},
|
||||
{0x0328U, 0x001000300C8FFC01UL},
|
||||
{0x0330U, 0x001000200C8FFC01UL},
|
||||
{0x0338U, 0x001000300C8FFC01UL},
|
||||
};
|
||||
#endif
|
||||
|
||||
void qos_init_h3_v10(void)
|
||||
{
|
||||
/* DRAM Split Address mapping */
|
||||
#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
|
||||
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
|
||||
NOTICE("BL2: DRAM Split is 4ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1BU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR1, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
|
||||
NOTICE("BL2: DRAM Split is 2ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1BU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR2, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#else
|
||||
NOTICE("BL2: DRAM Split is OFF\n");
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
/* AR Cache setting */
|
||||
io_write_32(0xE67D1000U, 0x00000100U);
|
||||
io_write_32(0xE67D1008U, 0x00000100U);
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(RALLOC_RAS, 0x00000040U);
|
||||
io_write_32(RALLOC_FIXTH, 0x000F0005U);
|
||||
io_write_32(RALLOC_REGGD, 0x00000004U);
|
||||
io_write_64(RALLOC_DANN, 0x0202000004040404UL);
|
||||
io_write_32(RALLOC_DANT, 0x003C1110U);
|
||||
io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
|
||||
io_write_64(RALLOC_EMS, 0x0000000000000000UL);
|
||||
io_write_32(RALLOC_INSFC, 0xC7840001U);
|
||||
io_write_32(RALLOC_BERR, 0x00000000U);
|
||||
|
||||
/* MSTAT setting */
|
||||
io_write_32(MSTAT_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
|
||||
io_write_32(MSTAT_REF_ARS, 0x00330000U);
|
||||
|
||||
/* MSTAT SRAM setting */
|
||||
for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
}
|
||||
for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
}
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
io_write_32(0xFD820808U, 0x00001234U);
|
||||
io_write_32(0xFD820800U, 0x0000003FU);
|
||||
io_write_32(0xFD821800U, 0x0000003FU);
|
||||
io_write_32(0xFD822800U, 0x0000003FU);
|
||||
io_write_32(0xFD823800U, 0x0000003FU);
|
||||
io_write_32(0xFD824800U, 0x0000003FU);
|
||||
io_write_32(0xFD825800U, 0x0000003FU);
|
||||
io_write_32(0xFD826800U, 0x0000003FU);
|
||||
io_write_32(0xFD827800U, 0x0000003FU);
|
||||
|
||||
/* Resource Alloc start */
|
||||
io_write_32(RALLOC_RAEN, 0x00000001U);
|
||||
|
||||
/* MSTAT start */
|
||||
io_write_32(MSTAT_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
||||
|
|
@ -1,610 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
|
||||
#include <rcar_def.h>
|
||||
|
||||
#include "../qos_common.h"
|
||||
#include "qos_init_h3_v11.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.37"
|
||||
|
||||
#define RCAR_QOS_NONE (3U)
|
||||
#define RCAR_QOS_TYPE_DEFAULT (0U)
|
||||
|
||||
#define RCAR_DRAM_SPLIT_LINEAR (0U)
|
||||
#define RCAR_DRAM_SPLIT_4CH (1U)
|
||||
#define RCAR_DRAM_SPLIT_2CH (2U)
|
||||
#define RCAR_DRAM_SPLIT_AUTO (3U)
|
||||
|
||||
#define RST_BASE (0xE6160000U)
|
||||
#define RST_MODEMR (RST_BASE + 0x0060U)
|
||||
|
||||
#define RCAR_PWRSR8 (0xE6180340U) /* A3VP_PWRSR0 */
|
||||
#define RCAR_PWRONCR8 (0xE618034CU) /* A3VP_PWRONCR */
|
||||
#define RCAR_PWRSR9 (0xE6180380U) /* A3VC_PWRSR0 */
|
||||
#define RCAR_PWRONCR9 (0xE618038CU) /* A3VC_PWRONCR */
|
||||
#define RCAR_PWRSR10 (0xE61803C0U) /* A2VC_PWRSR0 */
|
||||
#define RCAR_PWRONCR10 (0xE61803CCU) /* A2VC_PWRONCR */
|
||||
|
||||
#define DBSC_BASE (0xE6790000U)
|
||||
#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
|
||||
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
|
||||
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
|
||||
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
|
||||
#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
|
||||
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
|
||||
#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
|
||||
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
|
||||
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
|
||||
#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
|
||||
#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
|
||||
#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
|
||||
#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
|
||||
#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
|
||||
#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
|
||||
#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
|
||||
#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
|
||||
#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
|
||||
#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
|
||||
#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
|
||||
#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
|
||||
#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
|
||||
#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
|
||||
#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
|
||||
#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
|
||||
#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
|
||||
#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
|
||||
#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
|
||||
#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
|
||||
#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
|
||||
#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
|
||||
#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
|
||||
#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
|
||||
#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
|
||||
#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
|
||||
#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
|
||||
#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
|
||||
#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
|
||||
#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
|
||||
#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
|
||||
#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
|
||||
#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
|
||||
#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
|
||||
#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
|
||||
#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
|
||||
#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
|
||||
#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
|
||||
#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
|
||||
#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
|
||||
#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
|
||||
#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
|
||||
#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
|
||||
#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
|
||||
#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
|
||||
#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
|
||||
#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
|
||||
#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
|
||||
#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
|
||||
#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
|
||||
#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
|
||||
#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
|
||||
#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
|
||||
#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
|
||||
#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
|
||||
#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
|
||||
#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
|
||||
#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
|
||||
#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
|
||||
#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
|
||||
#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
|
||||
#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
|
||||
#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
|
||||
#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
|
||||
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
|
||||
|
||||
#define AXI_BASE (0xE6784000U)
|
||||
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
|
||||
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
|
||||
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
|
||||
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
|
||||
#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
|
||||
#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
|
||||
#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
|
||||
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
|
||||
#define ADSPLCR0_SWP (0x0CU)
|
||||
|
||||
#define MSTAT_BASE (0xE67E0000U)
|
||||
#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
|
||||
#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
|
||||
#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
|
||||
#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
|
||||
#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
|
||||
#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
|
||||
#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
|
||||
|
||||
#define RALLOC_BASE (0xE67F0000U)
|
||||
#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
|
||||
#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
|
||||
#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
|
||||
#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
|
||||
#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
|
||||
#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
|
||||
#define RALLOC_EC (RALLOC_BASE + 0x003CU)
|
||||
#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
|
||||
#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
|
||||
#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
|
||||
#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
static const mstat_slot_t mstat_fix[] = {
|
||||
{0x0000U, 0x0000000000000000UL},
|
||||
{0x0008U, 0x0000000000000000UL},
|
||||
{0x0010U, 0x0000000000000000UL},
|
||||
{0x0018U, 0x0000000000000000UL},
|
||||
{0x0020U, 0x0000000000000000UL},
|
||||
{0x0028U, 0x0000000000000000UL},
|
||||
{0x0030U, 0x001004030000FFFFUL},
|
||||
{0x0038U, 0x001008060000FFFFUL},
|
||||
{0x0040U, 0x001414090000FFFFUL},
|
||||
{0x0048U, 0x0000000000000000UL},
|
||||
{0x0050U, 0x001410010000FFFFUL},
|
||||
{0x0058U, 0x00140C0C0000FFFFUL},
|
||||
{0x0060U, 0x00140C0C0000FFFFUL},
|
||||
{0x0068U, 0x0000000000000000UL},
|
||||
{0x0070U, 0x001410010000FFFFUL},
|
||||
{0x0078U, 0x001008060000FFFFUL},
|
||||
{0x0080U, 0x001004020000FFFFUL},
|
||||
{0x0088U, 0x001414090000FFFFUL},
|
||||
{0x0090U, 0x00140C0C0000FFFFUL},
|
||||
{0x0098U, 0x001408080000FFFFUL},
|
||||
{0x00A0U, 0x000C08020000FFFFUL},
|
||||
{0x00A8U, 0x000C04010000FFFFUL},
|
||||
{0x00B0U, 0x000C04010000FFFFUL},
|
||||
{0x00B8U, 0x0000000000000000UL},
|
||||
{0x00C0U, 0x000C08020000FFFFUL},
|
||||
{0x00C8U, 0x000C04010000FFFFUL},
|
||||
{0x00D0U, 0x000C04010000FFFFUL},
|
||||
{0x00D8U, 0x000C04030000FFFFUL},
|
||||
{0x00E0U, 0x000C100F0000FFFFUL},
|
||||
{0x00E8U, 0x0000000000000000UL},
|
||||
{0x00F0U, 0x001010080000FFFFUL},
|
||||
{0x00F8U, 0x001010080000FFFFUL},
|
||||
{0x0100U, 0x0000000000000000UL},
|
||||
{0x0108U, 0x000C04030000FFFFUL},
|
||||
{0x0110U, 0x001010080000FFFFUL},
|
||||
{0x0118U, 0x001010080000FFFFUL},
|
||||
{0x0120U, 0x0000000000000000UL},
|
||||
{0x0128U, 0x000C100E0000FFFFUL},
|
||||
{0x0130U, 0x0000000000000000UL},
|
||||
{0x0138U, 0x001008050000FFFFUL},
|
||||
{0x0140U, 0x001008050000FFFFUL},
|
||||
{0x0148U, 0x001008050000FFFFUL},
|
||||
{0x0150U, 0x001008050000FFFFUL},
|
||||
{0x0158U, 0x001008050000FFFFUL},
|
||||
{0x0160U, 0x001008050000FFFFUL},
|
||||
{0x0168U, 0x001008050000FFFFUL},
|
||||
{0x0170U, 0x001008050000FFFFUL},
|
||||
{0x0178U, 0x001004030000FFFFUL},
|
||||
{0x0180U, 0x001004030000FFFFUL},
|
||||
{0x0188U, 0x001004030000FFFFUL},
|
||||
{0x0190U, 0x001014140000FFFFUL},
|
||||
{0x0198U, 0x001014140000FFFFUL},
|
||||
{0x01A0U, 0x001008050000FFFFUL},
|
||||
{0x01A8U, 0x001008050000FFFFUL},
|
||||
{0x01B0U, 0x001008050000FFFFUL},
|
||||
{0x01B8U, 0x0000000000000000UL},
|
||||
{0x01C0U, 0x0000000000000000UL},
|
||||
{0x01C8U, 0x0000000000000000UL},
|
||||
{0x01D0U, 0x0000000000000000UL},
|
||||
{0x01D8U, 0x0000000000000000UL},
|
||||
{0x01E0U, 0x0000000000000000UL},
|
||||
{0x01E8U, 0x0000000000000000UL},
|
||||
{0x01F0U, 0x0000000000000000UL},
|
||||
{0x01F8U, 0x0000000000000000UL},
|
||||
{0x0200U, 0x0000000000000000UL},
|
||||
{0x0208U, 0x0000000000000000UL},
|
||||
{0x0210U, 0x0000000000000000UL},
|
||||
{0x0218U, 0x0000000000000000UL},
|
||||
{0x0220U, 0x0000000000000000UL},
|
||||
{0x0228U, 0x0000000000000000UL},
|
||||
{0x0230U, 0x0000000000000000UL},
|
||||
{0x0238U, 0x0000000000000000UL},
|
||||
{0x0240U, 0x0000000000000000UL},
|
||||
{0x0248U, 0x0000000000000000UL},
|
||||
{0x0250U, 0x0000000000000000UL},
|
||||
{0x0258U, 0x0000000000000000UL},
|
||||
{0x0260U, 0x0000000000000000UL},
|
||||
{0x0268U, 0x001408010000FFFFUL},
|
||||
{0x0270U, 0x001404010000FFFFUL},
|
||||
{0x0278U, 0x0000000000000000UL},
|
||||
{0x0280U, 0x0000000000000000UL},
|
||||
{0x0288U, 0x0000000000000000UL},
|
||||
{0x0290U, 0x001408010000FFFFUL},
|
||||
{0x0298U, 0x001404010000FFFFUL},
|
||||
{0x02A0U, 0x000C04010000FFFFUL},
|
||||
{0x02A8U, 0x000C04010000FFFFUL},
|
||||
{0x02B0U, 0x001404010000FFFFUL},
|
||||
{0x02B8U, 0x0000000000000000UL},
|
||||
{0x02C0U, 0x0000000000000000UL},
|
||||
{0x02C8U, 0x0000000000000000UL},
|
||||
{0x02D0U, 0x000C04010000FFFFUL},
|
||||
{0x02D8U, 0x000C04010000FFFFUL},
|
||||
{0x02E0U, 0x001404010000FFFFUL},
|
||||
{0x02E8U, 0x0000000000000000UL},
|
||||
{0x02F0U, 0x0000000000000000UL},
|
||||
{0x02F8U, 0x0000000000000000UL},
|
||||
{0x0300U, 0x0000000000000000UL},
|
||||
{0x0308U, 0x0000000000000000UL},
|
||||
{0x0310U, 0x0000000000000000UL},
|
||||
{0x0318U, 0x0000000000000000UL},
|
||||
{0x0320U, 0x0000000000000000UL},
|
||||
{0x0328U, 0x0000000000000000UL},
|
||||
{0x0330U, 0x0000000000000000UL},
|
||||
{0x0338U, 0x0000000000000000UL},
|
||||
};
|
||||
|
||||
static const mstat_slot_t mstat_be[] = {
|
||||
{0x0000U, 0x001200100C89C401UL},
|
||||
{0x0008U, 0x001200100C89C401UL},
|
||||
{0x0010U, 0x001200100C89C401UL},
|
||||
{0x0018U, 0x001200100C89C401UL},
|
||||
{0x0020U, 0x001100100C803401UL},
|
||||
{0x0028U, 0x001100100C80FC01UL},
|
||||
{0x0030U, 0x0000000000000000UL},
|
||||
{0x0038U, 0x0000000000000000UL},
|
||||
{0x0040U, 0x0000000000000000UL},
|
||||
{0x0048U, 0x0000000000000000UL},
|
||||
{0x0050U, 0x0000000000000000UL},
|
||||
{0x0058U, 0x0000000000000000UL},
|
||||
{0x0060U, 0x0000000000000000UL},
|
||||
{0x0068U, 0x001100100C803401UL},
|
||||
{0x0070U, 0x0000000000000000UL},
|
||||
{0x0078U, 0x0000000000000000UL},
|
||||
{0x0080U, 0x0000000000000000UL},
|
||||
{0x0088U, 0x0000000000000000UL},
|
||||
{0x0090U, 0x0000000000000000UL},
|
||||
{0x0098U, 0x0000000000000000UL},
|
||||
{0x00A0U, 0x0000000000000000UL},
|
||||
{0x00A8U, 0x0000000000000000UL},
|
||||
{0x00B0U, 0x0000000000000000UL},
|
||||
{0x00B8U, 0x001100100C803401UL},
|
||||
{0x00C0U, 0x0000000000000000UL},
|
||||
{0x00C8U, 0x0000000000000000UL},
|
||||
{0x00D0U, 0x0000000000000000UL},
|
||||
{0x00D8U, 0x0000000000000000UL},
|
||||
{0x00E0U, 0x0000000000000000UL},
|
||||
{0x00E8U, 0x001100100C803401UL},
|
||||
{0x00F0U, 0x0000000000000000UL},
|
||||
{0x00F8U, 0x0000000000000000UL},
|
||||
{0x0100U, 0x0000000000000000UL},
|
||||
{0x0108U, 0x0000000000000000UL},
|
||||
{0x0110U, 0x0000000000000000UL},
|
||||
{0x0118U, 0x0000000000000000UL},
|
||||
{0x0120U, 0x0000000000000000UL},
|
||||
{0x0128U, 0x0000000000000000UL},
|
||||
{0x0130U, 0x001100100C803401UL},
|
||||
{0x0138U, 0x0000000000000000UL},
|
||||
{0x0140U, 0x0000000000000000UL},
|
||||
{0x0148U, 0x0000000000000000UL},
|
||||
{0x0150U, 0x0000000000000000UL},
|
||||
{0x0158U, 0x0000000000000000UL},
|
||||
{0x0160U, 0x0000000000000000UL},
|
||||
{0x0168U, 0x0000000000000000UL},
|
||||
{0x0170U, 0x0000000000000000UL},
|
||||
{0x0178U, 0x0000000000000000UL},
|
||||
{0x0180U, 0x0000000000000000UL},
|
||||
{0x0188U, 0x0000000000000000UL},
|
||||
{0x0190U, 0x0000000000000000UL},
|
||||
{0x0198U, 0x0000000000000000UL},
|
||||
{0x01A0U, 0x0000000000000000UL},
|
||||
{0x01A8U, 0x0000000000000000UL},
|
||||
{0x01B0U, 0x0000000000000000UL},
|
||||
{0x01B8U, 0x001100100C803401UL},
|
||||
{0x01C0U, 0x001100800C8FFC01UL},
|
||||
{0x01C8U, 0x001100800C8FFC01UL},
|
||||
{0x01D0U, 0x001100800C8FFC01UL},
|
||||
{0x01D8U, 0x001100800C8FFC01UL},
|
||||
{0x01E0U, 0x001100100C80FC01UL},
|
||||
{0x01E8U, 0x001200100C80FC01UL},
|
||||
{0x01F0U, 0x001100100C80FC01UL},
|
||||
{0x01F8U, 0x001100100C803401UL},
|
||||
{0x0200U, 0x001100100C80FC01UL},
|
||||
{0x0208U, 0x001200100C80FC01UL},
|
||||
{0x0210U, 0x001100100C80FC01UL},
|
||||
{0x0218U, 0x001100100C825801UL},
|
||||
{0x0220U, 0x001100100C825801UL},
|
||||
{0x0228U, 0x001100100C803401UL},
|
||||
{0x0230U, 0x001100100C825801UL},
|
||||
{0x0238U, 0x001100100C825801UL},
|
||||
{0x0240U, 0x001200100C8BB801UL},
|
||||
{0x0248U, 0x001100200C8FFC01UL},
|
||||
{0x0250U, 0x001200100C8BB801UL},
|
||||
{0x0258U, 0x001100200C8FFC01UL},
|
||||
{0x0260U, 0x001100100C84E401UL},
|
||||
{0x0268U, 0x0000000000000000UL},
|
||||
{0x0270U, 0x0000000000000000UL},
|
||||
{0x0278U, 0x001100100C81F401UL},
|
||||
{0x0280U, 0x001100100C803401UL},
|
||||
{0x0288U, 0x001100100C803401UL},
|
||||
{0x0290U, 0x0000000000000000UL},
|
||||
{0x0298U, 0x0000000000000000UL},
|
||||
{0x02A0U, 0x0000000000000000UL},
|
||||
{0x02A8U, 0x0000000000000000UL},
|
||||
{0x02B0U, 0x0000000000000000UL},
|
||||
{0x02B8U, 0x001100100C803401UL},
|
||||
{0x02C0U, 0x001100100C803401UL},
|
||||
{0x02C8U, 0x001100100C803401UL},
|
||||
{0x02D0U, 0x0000000000000000UL},
|
||||
{0x02D8U, 0x0000000000000000UL},
|
||||
{0x02E0U, 0x0000000000000000UL},
|
||||
{0x02E8U, 0x001100100C803401UL},
|
||||
{0x02F0U, 0x001100300C8FFC01UL},
|
||||
{0x02F8U, 0x001100500C8FFC01UL},
|
||||
{0x0300U, 0x001100100C803401UL},
|
||||
{0x0308U, 0x001100300C8FFC01UL},
|
||||
{0x0310U, 0x001100500C8FFC01UL},
|
||||
{0x0318U, 0x001200100C803401UL},
|
||||
{0x0320U, 0x001100300C8FFC01UL},
|
||||
{0x0328U, 0x001100500C8FFC01UL},
|
||||
{0x0330U, 0x001100300C8FFC01UL},
|
||||
{0x0338U, 0x001100500C8FFC01UL},
|
||||
};
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
uint32_t md = 0;
|
||||
|
||||
/* BUFCAM settings */
|
||||
/* DBSC_DBCAM0CNF0 not set */
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00044218); /* dbcam0cnf1 */
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */
|
||||
/* DBSC_DBCAM0CNF3 not set */
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x080F0037); /* dbschcnt0 */
|
||||
io_write_32(DBSC_DBSCHCNT1, 0x00001010); /* dbschcnt1 */
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */
|
||||
|
||||
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
|
||||
|
||||
switch (md) {
|
||||
case 0x0:
|
||||
/* DDR3200 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
|
||||
/* DDR2800 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
|
||||
/* DDR2400 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
|
||||
/* DDR1600 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
}
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS_0_0, 0x0000F000);
|
||||
io_write_32(DBSC_DBSCHQOS_0_1, 0x0000E000);
|
||||
io_write_32(DBSC_DBSCHQOS_0_2, 0x00007000);
|
||||
io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
|
||||
/* DBSC_DBSCHQOS_1_0 not set */
|
||||
/* DBSC_DBSCHQOS_1_1 not set */
|
||||
/* DBSC_DBSCHQOS_1_2 not set */
|
||||
/* DBSC_DBSCHQOS_1_3 not set */
|
||||
/* DBSC_DBSCHQOS_2_0 not set */
|
||||
/* DBSC_DBSCHQOS_2_1 not set */
|
||||
/* DBSC_DBSCHQOS_2_2 not set */
|
||||
/* DBSC_DBSCHQOS_2_3 not set */
|
||||
/* DBSC_DBSCHQOS_3_0 not set */
|
||||
/* DBSC_DBSCHQOS_3_1 not set */
|
||||
/* DBSC_DBSCHQOS_3_2 not set */
|
||||
/* DBSC_DBSCHQOS_3_3 not set */
|
||||
io_write_32(DBSC_DBSCHQOS_4_0, 0x00000E00);
|
||||
io_write_32(DBSC_DBSCHQOS_4_1, 0x00000DFF);
|
||||
io_write_32(DBSC_DBSCHQOS_4_2, 0x00000400);
|
||||
io_write_32(DBSC_DBSCHQOS_4_3, 0x00000200);
|
||||
/* DBSC_DBSCHQOS_5_0 not set */
|
||||
/* DBSC_DBSCHQOS_5_1 not set */
|
||||
/* DBSC_DBSCHQOS_5_2 not set */
|
||||
/* DBSC_DBSCHQOS_5_3 not set */
|
||||
/* DBSC_DBSCHQOS_6_0 not set */
|
||||
/* DBSC_DBSCHQOS_6_1 not set */
|
||||
/* DBSC_DBSCHQOS_6_2 not set */
|
||||
/* DBSC_DBSCHQOS_6_3 not set */
|
||||
/* DBSC_DBSCHQOS_7_0 not set */
|
||||
/* DBSC_DBSCHQOS_7_1 not set */
|
||||
/* DBSC_DBSCHQOS_7_2 not set */
|
||||
/* DBSC_DBSCHQOS_7_3 not set */
|
||||
/* DBSC_DBSCHQOS_8_0 not set */
|
||||
/* DBSC_DBSCHQOS_8_1 not set */
|
||||
/* DBSC_DBSCHQOS_8_2 not set */
|
||||
/* DBSC_DBSCHQOS_8_3 not set */
|
||||
io_write_32(DBSC_DBSCHQOS_9_0, 0x00000C00);
|
||||
io_write_32(DBSC_DBSCHQOS_9_1, 0x00000BFF);
|
||||
io_write_32(DBSC_DBSCHQOS_9_2, 0x00000400);
|
||||
io_write_32(DBSC_DBSCHQOS_9_3, 0x00000200);
|
||||
/* DBSC_DBSCHQOS_10_0 not set */
|
||||
/* DBSC_DBSCHQOS_10_1 not set */
|
||||
/* DBSC_DBSCHQOS_10_2 not set */
|
||||
/* DBSC_DBSCHQOS_10_3 not set */
|
||||
/* DBSC_DBSCHQOS_11_0 not set */
|
||||
/* DBSC_DBSCHQOS_11_1 not set */
|
||||
/* DBSC_DBSCHQOS_11_2 not set */
|
||||
/* DBSC_DBSCHQOS_11_3 not set */
|
||||
/* DBSC_DBSCHQOS_12_0 not set */
|
||||
/* DBSC_DBSCHQOS_12_1 not set */
|
||||
/* DBSC_DBSCHQOS_12_2 not set */
|
||||
/* DBSC_DBSCHQOS_12_3 not set */
|
||||
io_write_32(DBSC_DBSCHQOS_13_0, 0x00000980);
|
||||
io_write_32(DBSC_DBSCHQOS_13_1, 0x0000097F);
|
||||
io_write_32(DBSC_DBSCHQOS_13_2, 0x00000300);
|
||||
io_write_32(DBSC_DBSCHQOS_13_3, 0x00000180);
|
||||
io_write_32(DBSC_DBSCHQOS_14_0, 0x00000800);
|
||||
io_write_32(DBSC_DBSCHQOS_14_1, 0x000007FF);
|
||||
io_write_32(DBSC_DBSCHQOS_14_2, 0x00000300);
|
||||
io_write_32(DBSC_DBSCHQOS_14_3, 0x00000180);
|
||||
io_write_32(DBSC_DBSCHQOS_15_0, 0x000007D0);
|
||||
io_write_32(DBSC_DBSCHQOS_15_1, 0x000007CF);
|
||||
io_write_32(DBSC_DBSCHQOS_15_2, 0x000005D0);
|
||||
io_write_32(DBSC_DBSCHQOS_15_3, 0x000003D0);
|
||||
}
|
||||
|
||||
void qos_init_h3_v11(void)
|
||||
{
|
||||
dbsc_setting();
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
|
||||
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
|
||||
NOTICE("BL2: DRAM Split is 4ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1BU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR1, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
|
||||
NOTICE("BL2: DRAM Split is 2ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1BU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR2, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#else
|
||||
NOTICE("BL2: DRAM Split is OFF\n");
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
/* AR Cache setting */
|
||||
io_write_32(0xE67D1000U, 0x00000100U);
|
||||
io_write_32(0xE67D1008U, 0x00000100U);
|
||||
|
||||
/* Resource Alloc setting */
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
|
||||
io_write_32(RALLOC_RAS, 0x00000020U);
|
||||
#else
|
||||
io_write_32(RALLOC_RAS, 0x00000040U);
|
||||
#endif
|
||||
io_write_32(RALLOC_FIXTH, 0x000F0005U);
|
||||
io_write_32(RALLOC_REGGD, 0x00000000U);
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
|
||||
io_write_64(RALLOC_DANN, 0x0101010102020201UL);
|
||||
io_write_32(RALLOC_DANT, 0x00181008U);
|
||||
#else
|
||||
io_write_64(RALLOC_DANN, 0x0101000004040401UL);
|
||||
io_write_32(RALLOC_DANT, 0x003C2010U);
|
||||
#endif
|
||||
io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
|
||||
io_write_64(RALLOC_EMS, 0x0000000000000000UL);
|
||||
io_write_32(RALLOC_INSFC, 0xC7840001U);
|
||||
io_write_32(RALLOC_BERR, 0x00000000U);
|
||||
io_write_32(RALLOC_RACNT0, 0x00000000U);
|
||||
|
||||
/* MSTAT setting */
|
||||
io_write_32(MSTAT_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
|
||||
io_write_32(MSTAT_REF_ARS, 0x00330000U);
|
||||
|
||||
/* MSTAT SRAM setting */
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
}
|
||||
}
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
io_write_32(0xFD820808U, 0x00001234U);
|
||||
io_write_32(0xFD820800U, 0x0000003FU);
|
||||
io_write_32(0xFD821800U, 0x0000003FU);
|
||||
io_write_32(0xFD822800U, 0x0000003FU);
|
||||
io_write_32(0xFD823800U, 0x0000003FU);
|
||||
io_write_32(0xFD824800U, 0x0000003FU);
|
||||
io_write_32(0xFD825800U, 0x0000003FU);
|
||||
io_write_32(0xFD826800U, 0x0000003FU);
|
||||
io_write_32(0xFD827800U, 0x0000003FU);
|
||||
|
||||
/* VIO bus Leaf setting */
|
||||
io_write_32(0xFEB89800, 0x00000001U);
|
||||
io_write_32(0xFEB8A800, 0x00000001U);
|
||||
io_write_32(0xFEB8B800, 0x00000001U);
|
||||
io_write_32(0xFEB8C800, 0x00000001U);
|
||||
|
||||
/* HSC bus Leaf setting */
|
||||
io_write_32(0xE6430800, 0x00000001U);
|
||||
io_write_32(0xE6431800, 0x00000001U);
|
||||
io_write_32(0xE6432800, 0x00000001U);
|
||||
io_write_32(0xE6433800, 0x00000001U);
|
||||
|
||||
/* MP bus Leaf setting */
|
||||
io_write_32(0xEC620800, 0x00000001U);
|
||||
io_write_32(0xEC621800, 0x00000001U);
|
||||
|
||||
/* PERIE bus Leaf setting */
|
||||
io_write_32(0xE7760800, 0x00000001U);
|
||||
io_write_32(0xE7768800, 0x00000001U);
|
||||
|
||||
/* PERIW bus Leaf setting */
|
||||
io_write_32(0xE6760800, 0x00000001U);
|
||||
io_write_32(0xE6768800, 0x00000001U);
|
||||
|
||||
/* RT bus Leaf setting */
|
||||
io_write_32(0xFFC50800, 0x00000001U);
|
||||
io_write_32(0xFFC51800, 0x00000001U);
|
||||
|
||||
/* CCI bus Leaf setting */
|
||||
{
|
||||
|
||||
uint32_t modemr = io_read_32(RCAR_MODEMR);
|
||||
|
||||
modemr &= MODEMR_BOOT_CPU_MASK;
|
||||
|
||||
if ((modemr == MODEMR_BOOT_CPU_CA57) ||
|
||||
(modemr == MODEMR_BOOT_CPU_CA53)) {
|
||||
io_write_32(0xF1300800, 0x00000001U);
|
||||
io_write_32(0xF1340800, 0x00000001U);
|
||||
io_write_32(0xF1380800, 0x00000001U);
|
||||
io_write_32(0xF13C0800, 0x00000001U);
|
||||
}
|
||||
}
|
||||
|
||||
/* Resource Alloc start */
|
||||
io_write_32(RALLOC_RAEN, 0x00000001U);
|
||||
|
||||
/* MSTAT start */
|
||||
io_write_32(MSTAT_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
||||
|
|
@ -1,556 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
|
||||
#include "../qos_common.h"
|
||||
#include "qos_init_m3_v10.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.19"
|
||||
|
||||
#define RCAR_QOS_NONE (3U)
|
||||
#define RCAR_QOS_TYPE_DEFAULT (0U)
|
||||
|
||||
#define RCAR_DRAM_SPLIT_LINEAR (0U)
|
||||
#define RCAR_DRAM_SPLIT_4CH (1U)
|
||||
#define RCAR_DRAM_SPLIT_2CH (2U)
|
||||
#define RCAR_DRAM_SPLIT_AUTO (3U)
|
||||
|
||||
#define RST_BASE (0xE6160000U)
|
||||
#define RST_MODEMR (RST_BASE + 0x0060U)
|
||||
|
||||
#define DBSC_BASE (0xE6790000U)
|
||||
#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
|
||||
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
|
||||
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
|
||||
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
|
||||
#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
|
||||
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
|
||||
#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
|
||||
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
|
||||
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
|
||||
#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
|
||||
#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
|
||||
#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
|
||||
#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
|
||||
#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
|
||||
#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
|
||||
#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
|
||||
#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
|
||||
#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
|
||||
#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
|
||||
#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
|
||||
#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
|
||||
#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
|
||||
#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
|
||||
#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
|
||||
#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
|
||||
#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
|
||||
#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
|
||||
#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
|
||||
#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
|
||||
#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
|
||||
#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
|
||||
#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
|
||||
#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
|
||||
#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
|
||||
#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
|
||||
#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
|
||||
#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
|
||||
#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
|
||||
#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
|
||||
#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
|
||||
#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
|
||||
#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
|
||||
#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
|
||||
#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
|
||||
#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
|
||||
#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
|
||||
#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
|
||||
#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
|
||||
#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
|
||||
#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
|
||||
#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
|
||||
#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
|
||||
#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
|
||||
#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
|
||||
#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
|
||||
#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
|
||||
#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
|
||||
#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
|
||||
#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
|
||||
#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
|
||||
#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
|
||||
#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
|
||||
#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
|
||||
#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
|
||||
#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
|
||||
#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
|
||||
#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
|
||||
#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
|
||||
#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
|
||||
#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
|
||||
#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
|
||||
#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
|
||||
#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
|
||||
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
|
||||
|
||||
#define AXI_BASE (0xE6784000U)
|
||||
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
|
||||
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
|
||||
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
|
||||
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
|
||||
#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
|
||||
#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
|
||||
#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
|
||||
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
|
||||
#define ADSPLCR0_SWP (0x0CU)
|
||||
|
||||
#define MSTAT_BASE (0xE67E0000U)
|
||||
#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
|
||||
#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
|
||||
#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
|
||||
#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
|
||||
#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
|
||||
#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
|
||||
#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
|
||||
|
||||
#define RALLOC_BASE (0xE67F0000U)
|
||||
#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
|
||||
#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
|
||||
#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
|
||||
#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
|
||||
#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
|
||||
#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
|
||||
#define RALLOC_EC (RALLOC_BASE + 0x003CU)
|
||||
#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
|
||||
#define RALLOC_FSS (RALLOC_BASE + 0x0048U)
|
||||
#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
|
||||
#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
|
||||
#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
static const mstat_slot_t mstat_fix[] = {
|
||||
{0x0000U, 0x0000000000000000UL},
|
||||
{0x0008U, 0x0000000000000000UL},
|
||||
{0x0010U, 0x0000000000000000UL},
|
||||
{0x0018U, 0x0000000000000000UL},
|
||||
{0x0020U, 0x0000000000000000UL},
|
||||
{0x0028U, 0x0000000000000000UL},
|
||||
{0x0030U, 0x001004030000FFFFUL},
|
||||
{0x0038U, 0x001004030000FFFFUL},
|
||||
{0x0040U, 0x001414090000FFFFUL},
|
||||
{0x0048U, 0x0000000000000000UL},
|
||||
{0x0050U, 0x001410010000FFFFUL},
|
||||
{0x0058U, 0x00140C090000FFFFUL},
|
||||
{0x0060U, 0x00140C090000FFFFUL},
|
||||
{0x0068U, 0x0000000000000000UL},
|
||||
{0x0070U, 0x001410010000FFFFUL},
|
||||
{0x0078U, 0x001004020000FFFFUL},
|
||||
{0x0080U, 0x0000000000000000UL},
|
||||
{0x0088U, 0x001414090000FFFFUL},
|
||||
{0x0090U, 0x001408060000FFFFUL},
|
||||
{0x0098U, 0x0000000000000000UL},
|
||||
{0x00A0U, 0x000C08020000FFFFUL},
|
||||
{0x00A8U, 0x000C04010000FFFFUL},
|
||||
{0x00B0U, 0x000C04010000FFFFUL},
|
||||
{0x00B8U, 0x0000000000000000UL},
|
||||
{0x00C0U, 0x000C08020000FFFFUL},
|
||||
{0x00C8U, 0x000C04010000FFFFUL},
|
||||
{0x00D0U, 0x000C04010000FFFFUL},
|
||||
{0x00D8U, 0x000C04030000FFFFUL},
|
||||
{0x00E0U, 0x000C100F0000FFFFUL},
|
||||
{0x00E8U, 0x0000000000000000UL},
|
||||
{0x00F0U, 0x001010080000FFFFUL},
|
||||
{0x00F8U, 0x0000000000000000UL},
|
||||
{0x0100U, 0x0000000000000000UL},
|
||||
{0x0108U, 0x0000000000000000UL},
|
||||
{0x0110U, 0x001010080000FFFFUL},
|
||||
{0x0118U, 0x0000000000000000UL},
|
||||
{0x0120U, 0x0000000000000000UL},
|
||||
{0x0128U, 0x0000000000000000UL},
|
||||
{0x0130U, 0x0000000000000000UL},
|
||||
{0x0138U, 0x00100C0A0000FFFFUL},
|
||||
{0x0140U, 0x0000000000000000UL},
|
||||
{0x0148U, 0x0000000000000000UL},
|
||||
{0x0150U, 0x00100C0A0000FFFFUL},
|
||||
{0x0158U, 0x0000000000000000UL},
|
||||
{0x0160U, 0x00100C0A0000FFFFUL},
|
||||
{0x0168U, 0x0000000000000000UL},
|
||||
{0x0170U, 0x0000000000000000UL},
|
||||
{0x0178U, 0x001008050000FFFFUL},
|
||||
{0x0180U, 0x0000000000000000UL},
|
||||
{0x0188U, 0x0000000000000000UL},
|
||||
{0x0190U, 0x001028280000FFFFUL},
|
||||
{0x0198U, 0x0000000000000000UL},
|
||||
{0x01A0U, 0x00100C0A0000FFFFUL},
|
||||
{0x01A8U, 0x0000000000000000UL},
|
||||
{0x01B0U, 0x0000000000000000UL},
|
||||
{0x01B8U, 0x0000000000000000UL},
|
||||
{0x01C0U, 0x0000000000000000UL},
|
||||
{0x01C8U, 0x0000000000000000UL},
|
||||
{0x01D0U, 0x0000000000000000UL},
|
||||
{0x01D8U, 0x0000000000000000UL},
|
||||
{0x01E0U, 0x0000000000000000UL},
|
||||
{0x01E8U, 0x0000000000000000UL},
|
||||
{0x01F0U, 0x0000000000000000UL},
|
||||
{0x01F8U, 0x0000000000000000UL},
|
||||
{0x0200U, 0x0000000000000000UL},
|
||||
{0x0208U, 0x0000000000000000UL},
|
||||
{0x0210U, 0x0000000000000000UL},
|
||||
{0x0218U, 0x0000000000000000UL},
|
||||
{0x0220U, 0x0000000000000000UL},
|
||||
{0x0228U, 0x0000000000000000UL},
|
||||
{0x0230U, 0x0000000000000000UL},
|
||||
{0x0238U, 0x0000000000000000UL},
|
||||
{0x0240U, 0x0000000000000000UL},
|
||||
{0x0248U, 0x0000000000000000UL},
|
||||
{0x0250U, 0x0000000000000000UL},
|
||||
{0x0258U, 0x0000000000000000UL},
|
||||
{0x0260U, 0x0000000000000000UL},
|
||||
{0x0268U, 0x001408010000FFFFUL},
|
||||
{0x0270U, 0x001404010000FFFFUL},
|
||||
{0x0278U, 0x0000000000000000UL},
|
||||
{0x0280U, 0x0000000000000000UL},
|
||||
{0x0288U, 0x0000000000000000UL},
|
||||
{0x0290U, 0x001408010000FFFFUL},
|
||||
{0x0298U, 0x001404010000FFFFUL},
|
||||
{0x02A0U, 0x000C04010000FFFFUL},
|
||||
{0x02A8U, 0x000C04010000FFFFUL},
|
||||
{0x02B0U, 0x001404010000FFFFUL},
|
||||
{0x02B8U, 0x0000000000000000UL},
|
||||
{0x02C0U, 0x0000000000000000UL},
|
||||
{0x02C8U, 0x0000000000000000UL},
|
||||
{0x02D0U, 0x000C04010000FFFFUL},
|
||||
{0x02D8U, 0x000C04010000FFFFUL},
|
||||
{0x02E0U, 0x001404010000FFFFUL},
|
||||
{0x02E8U, 0x0000000000000000UL},
|
||||
{0x02F0U, 0x0000000000000000UL},
|
||||
{0x02F8U, 0x0000000000000000UL},
|
||||
{0x0300U, 0x0000000000000000UL},
|
||||
{0x0308U, 0x0000000000000000UL},
|
||||
{0x0310U, 0x0000000000000000UL},
|
||||
{0x0318U, 0x0000000000000000UL},
|
||||
{0x0320U, 0x0000000000000000UL},
|
||||
{0x0328U, 0x0000000000000000UL},
|
||||
{0x0330U, 0x0000000000000000UL},
|
||||
{0x0338U, 0x0000000000000000UL},
|
||||
{0x0340U, 0x0000000000000000UL},
|
||||
{0x0348U, 0x0000000000000000UL},
|
||||
{0x0350U, 0x0000000000000000UL},
|
||||
};
|
||||
|
||||
static const mstat_slot_t mstat_be[] = {
|
||||
{0x0000U, 0x001200100C89C401UL},
|
||||
{0x0008U, 0x001200100C89C401UL},
|
||||
{0x0010U, 0x001200100C89C401UL},
|
||||
{0x0018U, 0x001200100C89C401UL},
|
||||
{0x0020U, 0x0000000000000000UL},
|
||||
{0x0028U, 0x001100100C803401UL},
|
||||
{0x0030U, 0x0000000000000000UL},
|
||||
{0x0038U, 0x0000000000000000UL},
|
||||
{0x0040U, 0x0000000000000000UL},
|
||||
{0x0048U, 0x0000000000000000UL},
|
||||
{0x0050U, 0x0000000000000000UL},
|
||||
{0x0058U, 0x0000000000000000UL},
|
||||
{0x0060U, 0x0000000000000000UL},
|
||||
{0x0068U, 0x0000000000000000UL},
|
||||
{0x0070U, 0x0000000000000000UL},
|
||||
{0x0078U, 0x0000000000000000UL},
|
||||
{0x0080U, 0x0000000000000000UL},
|
||||
{0x0088U, 0x0000000000000000UL},
|
||||
{0x0090U, 0x0000000000000000UL},
|
||||
{0x0098U, 0x0000000000000000UL},
|
||||
{0x00A0U, 0x0000000000000000UL},
|
||||
{0x00A8U, 0x0000000000000000UL},
|
||||
{0x00B0U, 0x0000000000000000UL},
|
||||
{0x00B8U, 0x0000000000000000UL},
|
||||
{0x00C0U, 0x0000000000000000UL},
|
||||
{0x00C8U, 0x0000000000000000UL},
|
||||
{0x00D0U, 0x0000000000000000UL},
|
||||
{0x00D8U, 0x0000000000000000UL},
|
||||
{0x00E0U, 0x0000000000000000UL},
|
||||
{0x00E8U, 0x0000000000000000UL},
|
||||
{0x00F0U, 0x0000000000000000UL},
|
||||
{0x00F8U, 0x0000000000000000UL},
|
||||
{0x0100U, 0x0000000000000000UL},
|
||||
{0x0108U, 0x0000000000000000UL},
|
||||
{0x0110U, 0x0000000000000000UL},
|
||||
{0x0118U, 0x0000000000000000UL},
|
||||
{0x0120U, 0x0000000000000000UL},
|
||||
{0x0128U, 0x0000000000000000UL},
|
||||
{0x0130U, 0x0000000000000000UL},
|
||||
{0x0138U, 0x0000000000000000UL},
|
||||
{0x0140U, 0x0000000000000000UL},
|
||||
{0x0148U, 0x0000000000000000UL},
|
||||
{0x0150U, 0x0000000000000000UL},
|
||||
{0x0158U, 0x0000000000000000UL},
|
||||
{0x0160U, 0x0000000000000000UL},
|
||||
{0x0168U, 0x0000000000000000UL},
|
||||
{0x0170U, 0x0000000000000000UL},
|
||||
{0x0178U, 0x0000000000000000UL},
|
||||
{0x0180U, 0x0000000000000000UL},
|
||||
{0x0188U, 0x0000000000000000UL},
|
||||
{0x0190U, 0x0000000000000000UL},
|
||||
{0x0198U, 0x0000000000000000UL},
|
||||
{0x01A0U, 0x0000000000000000UL},
|
||||
{0x01A8U, 0x0000000000000000UL},
|
||||
{0x01B0U, 0x0000000000000000UL},
|
||||
{0x01B8U, 0x0000000000000000UL},
|
||||
{0x01C0U, 0x001100500C8FFC01UL},
|
||||
{0x01C8U, 0x001100500C8FFC01UL},
|
||||
{0x01D0U, 0x001100500C8FFC01UL},
|
||||
{0x01D8U, 0x001100500C8FFC01UL},
|
||||
{0x01E0U, 0x0000000000000000UL},
|
||||
{0x01E8U, 0x001200100C803401UL},
|
||||
{0x01F0U, 0x001100100C80FC01UL},
|
||||
{0x01F8U, 0x0000000000000000UL},
|
||||
{0x0200U, 0x0000000000000000UL},
|
||||
{0x0208U, 0x001200100C80FC01UL},
|
||||
{0x0210U, 0x001100100C80FC01UL},
|
||||
{0x0218U, 0x001100100C825801UL},
|
||||
{0x0220U, 0x001100100C825801UL},
|
||||
{0x0228U, 0x0000000000000000UL},
|
||||
{0x0230U, 0x001100100C825801UL},
|
||||
{0x0238U, 0x001100100C825801UL},
|
||||
{0x0240U, 0x001200100C8BB801UL},
|
||||
{0x0248U, 0x001100100C8EA401UL},
|
||||
{0x0250U, 0x001200100C8BB801UL},
|
||||
{0x0258U, 0x001100100C8EA401UL},
|
||||
{0x0260U, 0x001100100C84E401UL},
|
||||
{0x0268U, 0x0000000000000000UL},
|
||||
{0x0270U, 0x0000000000000000UL},
|
||||
{0x0278U, 0x001100100C81F401UL},
|
||||
{0x0280U, 0x0000000000000000UL},
|
||||
{0x0288U, 0x0000000000000000UL},
|
||||
{0x0290U, 0x0000000000000000UL},
|
||||
{0x0298U, 0x0000000000000000UL},
|
||||
{0x02A0U, 0x0000000000000000UL},
|
||||
{0x02A8U, 0x0000000000000000UL},
|
||||
{0x02B0U, 0x0000000000000000UL},
|
||||
{0x02B8U, 0x001100100C803401UL},
|
||||
{0x02C0U, 0x0000000000000000UL},
|
||||
{0x02C8U, 0x0000000000000000UL},
|
||||
{0x02D0U, 0x0000000000000000UL},
|
||||
{0x02D8U, 0x0000000000000000UL},
|
||||
{0x02E0U, 0x0000000000000000UL},
|
||||
{0x02E8U, 0x001100100C803401UL},
|
||||
{0x02F0U, 0x001100300C8FFC01UL},
|
||||
{0x02F8U, 0x001100500C8FFC01UL},
|
||||
{0x0300U, 0x0000000000000000UL},
|
||||
{0x0308U, 0x001100300C8FFC01UL},
|
||||
{0x0310U, 0x001100500C8FFC01UL},
|
||||
{0x0318U, 0x001200100C803401UL},
|
||||
{0x0320U, 0x0000000000000000UL},
|
||||
{0x0328U, 0x0000000000000000UL},
|
||||
{0x0330U, 0x0000000000000000UL},
|
||||
{0x0338U, 0x0000000000000000UL},
|
||||
{0x0340U, 0x0000000000000000UL},
|
||||
{0x0348U, 0x0000000000000000UL},
|
||||
{0x0350U, 0x0000000000000000UL},
|
||||
};
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
uint32_t md = 0;
|
||||
|
||||
/* BUFCAM settings */
|
||||
/* DBSC_DBCAM0CNF0 not set */
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00043218); /* dbcam0cnf1 */
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */
|
||||
io_write_32(DBSC_DBCAM0CNF3, 0x00000000); /* dbcam0cnf3 */
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x080F0037); /* dbschcnt0 */
|
||||
/* DBSC_DBSCHCNT1 not set */
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */
|
||||
|
||||
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
|
||||
|
||||
switch (md) {
|
||||
case 0x0:
|
||||
/* DDR3200 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
|
||||
/* DDR2800 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
|
||||
/* DDR2400 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
|
||||
/* DDR1600 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
}
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS_0_0, 0x00000F00);
|
||||
io_write_32(DBSC_DBSCHQOS_0_1, 0x00000B00);
|
||||
io_write_32(DBSC_DBSCHQOS_0_2, 0x00000000);
|
||||
io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
|
||||
/* DBSC_DBSCHQOS_1_0 not set */
|
||||
/* DBSC_DBSCHQOS_1_1 not set */
|
||||
/* DBSC_DBSCHQOS_1_2 not set */
|
||||
/* DBSC_DBSCHQOS_1_3 not set */
|
||||
/* DBSC_DBSCHQOS_2_0 not set */
|
||||
/* DBSC_DBSCHQOS_2_1 not set */
|
||||
/* DBSC_DBSCHQOS_2_2 not set */
|
||||
/* DBSC_DBSCHQOS_2_3 not set */
|
||||
/* DBSC_DBSCHQOS_3_0 not set */
|
||||
/* DBSC_DBSCHQOS_3_1 not set */
|
||||
/* DBSC_DBSCHQOS_3_2 not set */
|
||||
/* DBSC_DBSCHQOS_3_3 not set */
|
||||
io_write_32(DBSC_DBSCHQOS_4_0, 0x00000300);
|
||||
io_write_32(DBSC_DBSCHQOS_4_1, 0x000002F0);
|
||||
io_write_32(DBSC_DBSCHQOS_4_2, 0x00000200);
|
||||
io_write_32(DBSC_DBSCHQOS_4_3, 0x00000100);
|
||||
/* DBSC_DBSCHQOS_5_0 not set */
|
||||
/* DBSC_DBSCHQOS_5_1 not set */
|
||||
/* DBSC_DBSCHQOS_5_2 not set */
|
||||
/* DBSC_DBSCHQOS_5_3 not set */
|
||||
/* DBSC_DBSCHQOS_6_0 not set */
|
||||
/* DBSC_DBSCHQOS_6_1 not set */
|
||||
/* DBSC_DBSCHQOS_6_2 not set */
|
||||
/* DBSC_DBSCHQOS_6_3 not set */
|
||||
/* DBSC_DBSCHQOS_7_0 not set */
|
||||
/* DBSC_DBSCHQOS_7_1 not set */
|
||||
/* DBSC_DBSCHQOS_7_2 not set */
|
||||
/* DBSC_DBSCHQOS_7_3 not set */
|
||||
/* DBSC_DBSCHQOS_8_0 not set */
|
||||
/* DBSC_DBSCHQOS_8_1 not set */
|
||||
/* DBSC_DBSCHQOS_8_2 not set */
|
||||
/* DBSC_DBSCHQOS_8_3 not set */
|
||||
io_write_32(DBSC_DBSCHQOS_9_0, 0x00000300);
|
||||
io_write_32(DBSC_DBSCHQOS_9_1, 0x000002F0);
|
||||
io_write_32(DBSC_DBSCHQOS_9_2, 0x00000200);
|
||||
io_write_32(DBSC_DBSCHQOS_9_3, 0x00000100);
|
||||
/* DBSC_DBSCHQOS_10_0 not set */
|
||||
/* DBSC_DBSCHQOS_10_1 not set */
|
||||
/* DBSC_DBSCHQOS_10_2 not set */
|
||||
/* DBSC_DBSCHQOS_10_3 not set */
|
||||
/* DBSC_DBSCHQOS_11_0 not set */
|
||||
/* DBSC_DBSCHQOS_11_1 not set */
|
||||
/* DBSC_DBSCHQOS_11_2 not set */
|
||||
/* DBSC_DBSCHQOS_11_3 not set */
|
||||
/* DBSC_DBSCHQOS_12_0 not set */
|
||||
/* DBSC_DBSCHQOS_12_1 not set */
|
||||
/* DBSC_DBSCHQOS_12_2 not set */
|
||||
/* DBSC_DBSCHQOS_12_3 not set */
|
||||
io_write_32(DBSC_DBSCHQOS_13_0, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS_13_1, 0x000000F0);
|
||||
io_write_32(DBSC_DBSCHQOS_13_2, 0x000000A0);
|
||||
io_write_32(DBSC_DBSCHQOS_13_3, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS_14_0, 0x000000C0);
|
||||
io_write_32(DBSC_DBSCHQOS_14_1, 0x000000B0);
|
||||
io_write_32(DBSC_DBSCHQOS_14_2, 0x00000080);
|
||||
io_write_32(DBSC_DBSCHQOS_14_3, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS_15_0, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS_15_1, 0x00000030);
|
||||
io_write_32(DBSC_DBSCHQOS_15_2, 0x00000020);
|
||||
io_write_32(DBSC_DBSCHQOS_15_3, 0x00000010);
|
||||
}
|
||||
|
||||
void qos_init_m3_v10(void)
|
||||
{
|
||||
dbsc_setting();
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
|
||||
#if RCAR_LSI == RCAR_M3
|
||||
#error "Don't set DRAM Split 4ch(M3)"
|
||||
#else
|
||||
ERROR("DRAM Split 4ch not supported.(M3)");
|
||||
panic();
|
||||
#endif
|
||||
#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
|
||||
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
|
||||
NOTICE("BL2: DRAM Split is 2ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1CU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR2, 0x089A0000U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#else
|
||||
NOTICE("BL2: DRAM Split is OFF\n");
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(RALLOC_RAS, 0x00000028U);
|
||||
io_write_32(RALLOC_FIXTH, 0x000F0005U);
|
||||
io_write_32(RALLOC_REGGD, 0x00000000U);
|
||||
io_write_64(RALLOC_DANN, 0x0101010102020201UL);
|
||||
io_write_32(RALLOC_DANT, 0x00100804U);
|
||||
io_write_32(RALLOC_EC, 0x00000000U);
|
||||
io_write_64(RALLOC_EMS, 0x0000000000000000UL);
|
||||
io_write_32(RALLOC_FSS, 0x000003e8U);
|
||||
io_write_32(RALLOC_INSFC, 0xC7840001U);
|
||||
io_write_32(RALLOC_BERR, 0x00000000U);
|
||||
io_write_32(RALLOC_RACNT0, 0x00000000U);
|
||||
|
||||
/* MSTAT setting */
|
||||
io_write_32(MSTAT_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
|
||||
io_write_32(MSTAT_REF_ARS, 0x00330000U);
|
||||
|
||||
/* MSTAT SRAM setting */
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
}
|
||||
}
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
io_write_32(0xFD820808U, 0x00001234U);
|
||||
io_write_32(0xFD820800U, 0x00000006U);
|
||||
io_write_32(0xFD821800U, 0x00000006U);
|
||||
io_write_32(0xFD822800U, 0x00000006U);
|
||||
io_write_32(0xFD823800U, 0x00000006U);
|
||||
io_write_32(0xFD824800U, 0x00000006U);
|
||||
io_write_32(0xFD825800U, 0x00000006U);
|
||||
io_write_32(0xFD826800U, 0x00000006U);
|
||||
io_write_32(0xFD827800U, 0x00000006U);
|
||||
|
||||
/* RT bus Leaf setting */
|
||||
io_write_32(0xFFC50800U, 0x00000000U);
|
||||
io_write_32(0xFFC51800U, 0x00000000U);
|
||||
|
||||
/* Resource Alloc start */
|
||||
io_write_32(RALLOC_RAEN, 0x00000001U);
|
||||
|
||||
/* MSTAT start */
|
||||
io_write_32(MSTAT_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(RALLOC_EC, 0x00000000U);
|
||||
/* Resource Alloc start */
|
||||
io_write_32(RALLOC_RAEN, 0x00000001U);
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
||||
|
|
@ -1,231 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
|
||||
#include "../qos_common.h"
|
||||
#include "../qos_reg.h"
|
||||
#include "qos_init_m3n_v10.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.09"
|
||||
|
||||
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
|
||||
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
|
||||
|
||||
#define REF_ARS_ARBSTOPCYCLE_M3N (((SL_INIT_SSLOTCLK_M3N) - 5U) << 16U)
|
||||
|
||||
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
|
||||
|
||||
#define QOSWT_WTEN_ENABLE (0x1U)
|
||||
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
|
||||
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define QOSWT_WTREF_SLOT1_EN QOSWT_WTREF_SLOT0_EN
|
||||
|
||||
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
|
||||
#define WT_BASE_SUB_SLOT_NUM0 (12U)
|
||||
#define QOSWT_WTSET0_PERIOD0_M3N ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3N)-1U)
|
||||
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
|
||||
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
|
||||
|
||||
#define QOSWT_WTSET1_PERIOD1_M3N QOSWT_WTSET0_PERIOD0_M3N
|
||||
#define QOSWT_WTSET1_SSLOT1 QOSWT_WTSET0_SSLOT0
|
||||
#define QOSWT_WTSET1_SLOTSLOT1 QOSWT_WTSET0_SLOTSLOT0
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
#include "qos_init_m3n_v10_mstat195.h"
|
||||
#else
|
||||
#include "qos_init_m3n_v10_mstat390.h"
|
||||
#endif
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
#include "qos_init_m3n_v10_qoswt195.h"
|
||||
#else
|
||||
#include "qos_init_m3n_v10_qoswt390.h"
|
||||
#endif
|
||||
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
uint32_t md = 0;
|
||||
|
||||
/* Register write enable */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
|
||||
|
||||
/* BUFCAM settings */
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00043218); /* dbcam0cnf1 */
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x000F0037); /* dbschcnt0 */
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */
|
||||
|
||||
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
|
||||
|
||||
switch (md) {
|
||||
case 0x0:
|
||||
/* DDR3200 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
|
||||
/* DDR2800 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
|
||||
/* DDR2400 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
|
||||
/* DDR1600 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
}
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
|
||||
io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
|
||||
io_write_32(DBSC_DBSCHQOS02, 0x00000000);
|
||||
io_write_32(DBSC_DBSCHQOS03, 0x00000000);
|
||||
io_write_32(DBSC_DBSCHQOS40, 0x00000300);
|
||||
io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
|
||||
io_write_32(DBSC_DBSCHQOS42, 0x00000200);
|
||||
io_write_32(DBSC_DBSCHQOS43, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS90, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
|
||||
io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
|
||||
io_write_32(DBSC_DBSCHQOS93, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS130, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
|
||||
io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
|
||||
io_write_32(DBSC_DBSCHQOS133, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
|
||||
io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
|
||||
io_write_32(DBSC_DBSCHQOS142, 0x00000080);
|
||||
io_write_32(DBSC_DBSCHQOS143, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS150, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS151, 0x00000030);
|
||||
io_write_32(DBSC_DBSCHQOS152, 0x00000020);
|
||||
io_write_32(DBSC_DBSCHQOS153, 0x00000010);
|
||||
|
||||
/* Register write protect */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
|
||||
}
|
||||
|
||||
void qos_init_m3n_v10(void)
|
||||
{
|
||||
dbsc_setting();
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
|
||||
#if RCAR_LSI == RCAR_M3N
|
||||
#error "Don't set DRAM Split 4ch(M3N)"
|
||||
#else
|
||||
ERROR("DRAM Split 4ch not supported.(M3N)");
|
||||
panic();
|
||||
#endif
|
||||
#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
|
||||
#if RCAR_LSI == RCAR_M3N
|
||||
#error "Don't set DRAM Split 2ch(M3N)"
|
||||
#else
|
||||
ERROR("DRAM Split 2ch not supported.(M3N)");
|
||||
panic();
|
||||
#endif
|
||||
#else
|
||||
NOTICE("BL2: DRAM Split is OFF\n");
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
|
||||
#else
|
||||
NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
|
||||
#endif
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
NOTICE("BL2: Periodic Write DQ Training\n");
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
io_write_32(QOSCTRL_RAS, 0x00000028U);
|
||||
io_write_64(QOSCTRL_DANN, 0x0402000002020201UL);
|
||||
io_write_32(QOSCTRL_DANT, 0x00100804U);
|
||||
io_write_32(QOSCTRL_FSS, 0x0000000AU);
|
||||
io_write_32(QOSCTRL_INSFC, 0x06330001U);
|
||||
io_write_32(QOSCTRL_EARLYR, 0x00000001U);
|
||||
io_write_32(QOSCTRL_RACNT0, 0x00010003U);
|
||||
|
||||
io_write_32(QOSCTRL_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
|
||||
SL_INIT_SSLOTCLK_M3N);
|
||||
io_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_M3N);
|
||||
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
}
|
||||
|
||||
/* RT bus Leaf setting */
|
||||
io_write_32(RT_ACT0, 0x00000000U);
|
||||
io_write_32(RT_ACT1, 0x00000000U);
|
||||
|
||||
/* CCI bus Leaf setting */
|
||||
io_write_32(CPU_ACT0, 0x00000003U);
|
||||
io_write_32(CPU_ACT1, 0x00000003U);
|
||||
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
/* re-write training setting */
|
||||
io_write_32(QOSWT_WTREF,
|
||||
((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
|
||||
io_write_32(QOSWT_WTSET0,
|
||||
((QOSWT_WTSET0_PERIOD0_M3N << 16) |
|
||||
(QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
|
||||
io_write_32(QOSWT_WTSET1,
|
||||
((QOSWT_WTSET1_PERIOD1_M3N << 16) |
|
||||
(QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
|
||||
|
||||
io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
io_write_32(QOSCTRL_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
||||
|
|
@ -1,387 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <common/debug.h>
|
||||
#include "qos_init_v3m.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.01"
|
||||
|
||||
#define RCAR_QOS_NONE (3U)
|
||||
#define RCAR_QOS_TYPE_DEFAULT (0U)
|
||||
|
||||
#define RCAR_DRAM_SPLIT_LINEAR (0U)
|
||||
#define RCAR_DRAM_SPLIT_4CH (1U)
|
||||
#define RCAR_DRAM_SPLIT_2CH (2U)
|
||||
|
||||
#define DBSC_BASE (0xE6790000U)
|
||||
#define DBSC_AXARB (DBSC_BASE + 0x0800U)
|
||||
|
||||
#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
|
||||
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
|
||||
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
|
||||
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
|
||||
#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
|
||||
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
|
||||
#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
|
||||
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
|
||||
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
|
||||
#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U)
|
||||
#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
|
||||
#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
|
||||
#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
|
||||
#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
|
||||
#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
|
||||
#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
|
||||
#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
|
||||
#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
|
||||
#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
|
||||
#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
|
||||
#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
|
||||
#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
|
||||
#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
|
||||
#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
|
||||
#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
|
||||
#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
|
||||
#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
|
||||
#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
|
||||
#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
|
||||
#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
|
||||
#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
|
||||
#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
|
||||
#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
|
||||
#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
|
||||
#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
|
||||
#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
|
||||
#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
|
||||
#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
|
||||
#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
|
||||
#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
|
||||
#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
|
||||
#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
|
||||
#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
|
||||
#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
|
||||
#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
|
||||
#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
|
||||
#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
|
||||
#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
|
||||
#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
|
||||
#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
|
||||
#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
|
||||
#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
|
||||
#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
|
||||
#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
|
||||
#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
|
||||
#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
|
||||
#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
|
||||
#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
|
||||
#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
|
||||
#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
|
||||
#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
|
||||
#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
|
||||
#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
|
||||
#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
|
||||
#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
|
||||
#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
|
||||
#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
|
||||
#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
|
||||
#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
|
||||
#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
|
||||
#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
|
||||
#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
|
||||
#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
|
||||
#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
|
||||
#define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U)
|
||||
#define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U)
|
||||
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
|
||||
|
||||
#define AXI_BASE (0xE6784000U)
|
||||
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
|
||||
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
|
||||
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
|
||||
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
|
||||
#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
|
||||
#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
|
||||
#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
|
||||
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
|
||||
#define ADSPLCR0_SWP (0x0CU)
|
||||
|
||||
#define MSTAT_BASE (0xE67E0000U)
|
||||
#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
|
||||
#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
|
||||
#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
|
||||
#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
|
||||
#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
|
||||
#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
|
||||
#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
|
||||
|
||||
#define RALLOC_BASE (0xE67F0000U)
|
||||
#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
|
||||
#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
|
||||
#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
|
||||
#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
|
||||
#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
|
||||
#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
|
||||
#define RALLOC_EC (RALLOC_BASE + 0x003CU)
|
||||
#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
|
||||
#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
|
||||
#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
|
||||
#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
|
||||
|
||||
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
|
||||
|
||||
|
||||
static inline void io_write_32(uintptr_t addr, uint32_t value)
|
||||
{
|
||||
*(volatile uint32_t*)addr = value;
|
||||
}
|
||||
|
||||
static inline void io_write_64(uintptr_t addr, uint64_t value)
|
||||
{
|
||||
*(volatile uint64_t*)addr = value;
|
||||
}
|
||||
|
||||
|
||||
typedef struct {
|
||||
uintptr_t addr;
|
||||
uint64_t value;
|
||||
} mstat_slot_t;
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
static const mstat_slot_t mstat_fix[] = {
|
||||
{0x0000U, 0x000000000000FFFFU},
|
||||
{0x0008U, 0x000000000000FFFFU},
|
||||
{0x0010U, 0x000000000000FFFFU},
|
||||
{0x0018U, 0x000000000000FFFFU},
|
||||
{0x0020U, 0x001414090000FFFFU},
|
||||
{0x0028U, 0x000C00000000FFFFU},
|
||||
{0x0030U, 0x001008040000FFFFU},
|
||||
{0x0038U, 0x001004040000FFFFU},
|
||||
{0x0040U, 0x001004040000FFFFU},
|
||||
{0x0048U, 0x000000000000FFFFU},
|
||||
{0x0050U, 0x001004040000FFFFU},
|
||||
{0x0058U, 0x001004040000FFFFU},
|
||||
{0x0060U, 0x000000000000FFFFU},
|
||||
{0x0068U, 0x001404040000FFFFU},
|
||||
{0x0070U, 0x001008030000FFFFU},
|
||||
{0x0078U, 0x001004030000FFFFU},
|
||||
{0x0080U, 0x001004030000FFFFU},
|
||||
{0x0088U, 0x000000000000FFFFU},
|
||||
{0x0090U, 0x001004040000FFFFU},
|
||||
{0x0098U, 0x001004040000FFFFU},
|
||||
{0x00A0U, 0x000000000000FFFFU},
|
||||
{0x00A8U, 0x000000000000FFFFU},
|
||||
{0x00B0U, 0x000000000000FFFFU},
|
||||
{0x00B8U, 0x000000000000FFFFU},
|
||||
{0x00C0U, 0x000000000000FFFFU},
|
||||
{0x00C8U, 0x000000000000FFFFU},
|
||||
{0x00D0U, 0x000000000000FFFFU},
|
||||
{0x00D8U, 0x000000000000FFFFU},
|
||||
{0x00E0U, 0x001404020000FFFFU},
|
||||
{0x00E8U, 0x000000000000FFFFU},
|
||||
{0x00F0U, 0x000000000000FFFFU},
|
||||
{0x00F8U, 0x000000000000FFFFU},
|
||||
{0x0100U, 0x000000000000FFFFU},
|
||||
{0x0108U, 0x000C04020000FFFFU},
|
||||
{0x0110U, 0x000000000000FFFFU},
|
||||
{0x0118U, 0x001404020000FFFFU},
|
||||
{0x0120U, 0x000000000000FFFFU},
|
||||
{0x0128U, 0x000000000000FFFFU},
|
||||
{0x0130U, 0x000000000000FFFFU},
|
||||
{0x0138U, 0x000000000000FFFFU},
|
||||
{0x0140U, 0x000000000000FFFFU},
|
||||
{0x0148U, 0x000000000000FFFFU},
|
||||
};
|
||||
|
||||
static const mstat_slot_t mstat_be[] = {
|
||||
{0x0000U, 0x00100020447FFC01U},
|
||||
{0x0008U, 0x00100020447FFC01U},
|
||||
{0x0010U, 0x00100040447FFC01U},
|
||||
{0x0018U, 0x00100040447FFC01U},
|
||||
{0x0020U, 0x0000000000000000U},
|
||||
{0x0028U, 0x0000000000000000U},
|
||||
{0x0030U, 0x0000000000000000U},
|
||||
{0x0038U, 0x0000000000000000U},
|
||||
{0x0040U, 0x0000000000000000U},
|
||||
{0x0048U, 0x0000000000000000U},
|
||||
{0x0050U, 0x0000000000000000U},
|
||||
{0x0058U, 0x0000000000000000U},
|
||||
{0x0060U, 0x0000000000000000U},
|
||||
{0x0068U, 0x0000000000000000U},
|
||||
{0x0070U, 0x0000000000000000U},
|
||||
{0x0078U, 0x0000000000000000U},
|
||||
{0x0080U, 0x0000000000000000U},
|
||||
{0x0088U, 0x0000000000000000U},
|
||||
{0x0090U, 0x0000000000000000U},
|
||||
{0x0098U, 0x0000000000000000U},
|
||||
{0x00A0U, 0x00100010447FFC01U},
|
||||
{0x00A8U, 0x00100010447FFC01U},
|
||||
{0x00B0U, 0x00100010447FFC01U},
|
||||
{0x00B8U, 0x00100010447FFC01U},
|
||||
{0x00C0U, 0x00100010447FFC01U},
|
||||
{0x00C8U, 0x00100010447FFC01U},
|
||||
{0x00D0U, 0x0000000000000000U},
|
||||
{0x00D8U, 0x00100010447FFC01U},
|
||||
{0x00E0U, 0x0000000000000000U},
|
||||
{0x00E8U, 0x00100010447FFC01U},
|
||||
{0x00F0U, 0x00100010447FFC01U},
|
||||
{0x00F8U, 0x00100010447FFC01U},
|
||||
{0x0100U, 0x00100010447FFC01U},
|
||||
{0x0108U, 0x0000000000000000U},
|
||||
{0x0110U, 0x00100010447FFC01U},
|
||||
{0x0118U, 0x0000000000000000U},
|
||||
{0x0120U, 0x00100010447FFC01U},
|
||||
{0x0128U, 0x00100010447FFC01U},
|
||||
{0x0130U, 0x00100010447FFC01U},
|
||||
{0x0138U, 0x00100010447FFC01U},
|
||||
{0x0140U, 0x00100020447FFC01U},
|
||||
{0x0148U, 0x00100020447FFC01U},
|
||||
};
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
|
||||
/* BUFCAM settings */
|
||||
//DBSC_DBCAM0CNF0 not set
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00044218); //dbcam0cnf1
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2
|
||||
//io_write_32(DBSC_DBCAM0CNF3, 0x00000007); //dbcam0cnf3
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x080F003F); //dbschcnt0
|
||||
io_write_32(DBSC_DBSCHCNT1, 0x00001010); //dbschcnt0
|
||||
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0
|
||||
io_write_32(DBSC_DBSCHRW1, 0x00180034); //dbschrw1
|
||||
io_write_32(DBSC_SCFCTST0,0x180B1708);
|
||||
io_write_32(DBSC_SCFCTST1,0x0808070C);
|
||||
io_write_32(DBSC_SCFCTST2,0x012F1123);
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS_0_0, 0x0000F000);
|
||||
io_write_32(DBSC_DBSCHQOS_0_1, 0x0000E000);
|
||||
io_write_32(DBSC_DBSCHQOS_0_2, 0x00007000);
|
||||
io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
|
||||
//DBSC_DBSCHQOS_1_0 not set
|
||||
//DBSC_DBSCHQOS_1_1 not set
|
||||
//DBSC_DBSCHQOS_1_2 not set
|
||||
//DBSC_DBSCHQOS_1_3 not set
|
||||
//DBSC_DBSCHQOS_2_0 not set
|
||||
//DBSC_DBSCHQOS_2_1 not set
|
||||
//DBSC_DBSCHQOS_2_2 not set
|
||||
//DBSC_DBSCHQOS_2_3 not set
|
||||
//DBSC_DBSCHQOS_3_0 not set
|
||||
//DBSC_DBSCHQOS_3_1 not set
|
||||
//DBSC_DBSCHQOS_3_2 not set
|
||||
//DBSC_DBSCHQOS_3_3 not set
|
||||
io_write_32(DBSC_DBSCHQOS_4_0, 0x0000F000);
|
||||
io_write_32(DBSC_DBSCHQOS_4_1, 0x0000EFFF);
|
||||
io_write_32(DBSC_DBSCHQOS_4_2, 0x0000B000);
|
||||
io_write_32(DBSC_DBSCHQOS_4_3, 0x00000000);
|
||||
//DBSC_DBSCHQOS_5_0 not set
|
||||
//DBSC_DBSCHQOS_5_1 not set
|
||||
//DBSC_DBSCHQOS_5_2 not set
|
||||
//DBSC_DBSCHQOS_5_3 not set
|
||||
//DBSC_DBSCHQOS_6_0 not set
|
||||
//DBSC_DBSCHQOS_6_1 not set
|
||||
//DBSC_DBSCHQOS_6_2 not set
|
||||
//DBSC_DBSCHQOS_6_3 not set
|
||||
//DBSC_DBSCHQOS_7_0 not set
|
||||
//DBSC_DBSCHQOS_7_1 not set
|
||||
//DBSC_DBSCHQOS_7_2 not set
|
||||
//DBSC_DBSCHQOS_7_3 not set
|
||||
//DBSC_DBSCHQOS_8_0 not set
|
||||
//DBSC_DBSCHQOS_8_1 not set
|
||||
//DBSC_DBSCHQOS_8_2 not set
|
||||
//DBSC_DBSCHQOS_8_3 not set
|
||||
io_write_32(DBSC_DBSCHQOS_9_0, 0x0000F000);
|
||||
io_write_32(DBSC_DBSCHQOS_9_1, 0x0000EFFF);
|
||||
io_write_32(DBSC_DBSCHQOS_9_2, 0x0000D000);
|
||||
io_write_32(DBSC_DBSCHQOS_9_3, 0x00000000);
|
||||
//DBSC_DBSCHQOS_10_0 not set
|
||||
//DBSC_DBSCHQOS_10_1 not set
|
||||
//DBSC_DBSCHQOS_10_2 not set
|
||||
//DBSC_DBSCHQOS_10_3 not set
|
||||
//DBSC_DBSCHQOS_11_0 not set
|
||||
//DBSC_DBSCHQOS_11_1 not set
|
||||
//DBSC_DBSCHQOS_11_2 not set
|
||||
//DBSC_DBSCHQOS_11_3 not set
|
||||
//DBSC_DBSCHQOS_12_0 not set
|
||||
//DBSC_DBSCHQOS_12_1 not set
|
||||
//DBSC_DBSCHQOS_12_2 not set
|
||||
//DBSC_DBSCHQOS_12_3 not set
|
||||
io_write_32(DBSC_DBSCHQOS_13_0, 0x0000F000);
|
||||
io_write_32(DBSC_DBSCHQOS_13_1, 0x0000EFFF);
|
||||
io_write_32(DBSC_DBSCHQOS_13_2, 0x0000E800);
|
||||
io_write_32(DBSC_DBSCHQOS_13_3, 0x00007000);
|
||||
io_write_32(DBSC_DBSCHQOS_14_0, 0x0000F000);
|
||||
io_write_32(DBSC_DBSCHQOS_14_1, 0x0000EFFF);
|
||||
io_write_32(DBSC_DBSCHQOS_14_2, 0x0000E800);
|
||||
io_write_32(DBSC_DBSCHQOS_14_3, 0x0000B000);
|
||||
io_write_32(DBSC_DBSCHQOS_15_0, 0x000007D0);
|
||||
io_write_32(DBSC_DBSCHQOS_15_1, 0x000007CF);
|
||||
io_write_32(DBSC_DBSCHQOS_15_2, 0x000005D0);
|
||||
io_write_32(DBSC_DBSCHQOS_15_3, 0x000003D0);
|
||||
}
|
||||
|
||||
void qos_init_v3m(void)
|
||||
{
|
||||
return;
|
||||
|
||||
dbsc_setting();
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(RALLOC_RAS, 0x00000020U);
|
||||
io_write_32(RALLOC_FIXTH, 0x000F0005U);
|
||||
io_write_32(RALLOC_REGGD, 0x00000004U);
|
||||
io_write_64(RALLOC_DANN, 0x0202020104040200U);
|
||||
io_write_32(RALLOC_DANT, 0x00201008U);
|
||||
io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 ES1 */
|
||||
io_write_64(RALLOC_EMS, 0x0000000000000000U);
|
||||
io_write_32(RALLOC_INSFC, 0x63C20001U);
|
||||
io_write_32(RALLOC_BERR, 0x00000000U);
|
||||
|
||||
/* MSTAT setting */
|
||||
io_write_32(MSTAT_SL_INIT, 0x0305007DU);
|
||||
io_write_32(MSTAT_REF_ARS, 0x00330000U);
|
||||
|
||||
/* MSTAT SRAM setting */
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
}
|
||||
}
|
||||
|
||||
/* AXI-IF arbitration setting */
|
||||
io_write_32(DBSC_AXARB, 0x18010000U);
|
||||
|
||||
/* Resource Alloc start */
|
||||
io_write_32(RALLOC_RAEN, 0x00000001U);
|
||||
|
||||
/* MSTAT start */
|
||||
io_write_32(MSTAT_STATQC, 0x00000001U);
|
||||
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
||||
|
|
@ -1,106 +0,0 @@
|
|||
#
|
||||
# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
ifeq (${RCAR_LSI},${RCAR_AUTO})
|
||||
# E3, H3N not available for LSI_AUTO
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.c
|
||||
else ifdef RCAR_LSI_CUT_COMPAT
|
||||
ifeq (${RCAR_LSI},${RCAR_H3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_H3N})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_M3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_M3N})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_V3M})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_E3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_D3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c
|
||||
endif
|
||||
else
|
||||
ifeq (${RCAR_LSI},${RCAR_H3})
|
||||
ifeq (${LSI_CUT},10)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
|
||||
else ifeq (${LSI_CUT},11)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
|
||||
else ifeq (${LSI_CUT},20)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
|
||||
else ifeq (${LSI_CUT},30)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
|
||||
else
|
||||
# LSI_CUT 30 or later
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
|
||||
endif
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_H3N})
|
||||
ifeq (${LSI_CUT},30)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
|
||||
else
|
||||
# LSI_CUT 30 or later
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
|
||||
endif
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_M3})
|
||||
ifeq (${LSI_CUT},10)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
|
||||
else ifeq (${LSI_CUT},11)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
|
||||
else ifeq (${LSI_CUT},13)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
|
||||
else ifeq (${LSI_CUT},30)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
|
||||
else
|
||||
# LSI_CUT 30 or later
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
|
||||
endif
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_M3N})
|
||||
ifeq (${LSI_CUT},10)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
|
||||
else
|
||||
# LSI_CUT 10 or later
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
|
||||
endif
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_V3M})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_E3})
|
||||
ifeq (${LSI_CUT},10)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
|
||||
else
|
||||
# LSI_CUT 10 or later
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
|
||||
endif
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_D3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_d3.c
|
||||
endif
|
||||
endif
|
||||
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/qos_init.c
|
||||
|
|
@ -1,126 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QOS_COMMON_H
|
||||
#define QOS_COMMON_H
|
||||
|
||||
#define RCAR_REF_DEFAULT (0U)
|
||||
|
||||
/* define used for get_refperiod. */
|
||||
/* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */
|
||||
/* refere to plat/renesas/rcar/ddr/ddr_a/ddr_init_e3.h for E3. */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF default */
|
||||
#define REFPERIOD_CYCLE ((126 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */
|
||||
#else /* REF option */
|
||||
#define REFPERIOD_CYCLE ((252 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_E3)
|
||||
/* define used for E3 */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_E3 (0xAFU) /* 175 */
|
||||
#else /* REF 7.8usec */
|
||||
#define SUB_SLOT_CYCLE_E3 (0x15EU) /* 350 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define OPERATING_FREQ_E3 (266U) /* MHz */
|
||||
#define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 -1U)
|
||||
/* #define QOSWT_WTSET0_CYCLE_E3 ((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3) */ /* unit:ns */
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
|
||||
/* define used for M3N */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
|
||||
#define SUB_SLOT_CYCLE_M3N (0x7EU) /* 126 */
|
||||
#else /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_M3N (0xFCU) /* 252 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define SL_INIT_SSLOTCLK_M3N (SUB_SLOT_CYCLE_M3N -1U)
|
||||
#define QOSWT_WTSET0_CYCLE_M3N ((SUB_SLOT_CYCLE_M3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
|
||||
/* define used for H3 */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
|
||||
#define SUB_SLOT_CYCLE_H3_20 (0x7EU) /* 126 */
|
||||
#else /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_H3_20 (0xFCU) /* 252 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define SL_INIT_SSLOTCLK_H3_20 (SUB_SLOT_CYCLE_H3_20 -1U)
|
||||
#define QOSWT_WTSET0_CYCLE_H3_20 ((SUB_SLOT_CYCLE_H3_20 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
|
||||
/* define used for H3 Cut 30 */
|
||||
#define SUB_SLOT_CYCLE_H3_30 (SUB_SLOT_CYCLE_H3_20) /* same as H3 Cut 20 */
|
||||
#define SL_INIT_SSLOTCLK_H3_30 (SUB_SLOT_CYCLE_H3_30 -1U)
|
||||
#define QOSWT_WTSET0_CYCLE_H3_30 ((SUB_SLOT_CYCLE_H3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_H3N)
|
||||
/* define used for H3N */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
|
||||
#define SUB_SLOT_CYCLE_H3N (0x7EU) /* 126 */
|
||||
#else /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_H3N (0xFCU) /* 252 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define SL_INIT_SSLOTCLK_H3N (SUB_SLOT_CYCLE_H3N -1U)
|
||||
#define QOSWT_WTSET0_CYCLE_H3N ((SUB_SLOT_CYCLE_H3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
|
||||
/* define used for M3 */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
|
||||
#define SUB_SLOT_CYCLE_M3_11 (0x7EU) /* 126 */
|
||||
#define SUB_SLOT_CYCLE_M3_30 (0x7EU) /* 126 */
|
||||
#else /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_M3_11 (0xFCU) /* 252 */
|
||||
#define SUB_SLOT_CYCLE_M3_30 (0xFCU) /* 252 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 -1U)
|
||||
#define SL_INIT_SSLOTCLK_M3_30 (SUB_SLOT_CYCLE_M3_30 -1U)
|
||||
#define QOSWT_WTSET0_CYCLE_M3_11 ((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
#define QOSWT_WTSET0_CYCLE_M3_30 ((SUB_SLOT_CYCLE_M3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
#endif
|
||||
|
||||
#define OPERATING_FREQ (400U) /* MHz */
|
||||
#define BASE_SUB_SLOT_NUM (0x6U)
|
||||
#define SUB_SLOT_CYCLE (0x7EU) /* 126 */
|
||||
|
||||
#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
|
||||
#define SL_INIT_REFFSSLOT (0x3U << 24U)
|
||||
#define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U)
|
||||
#define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE -1U)
|
||||
|
||||
static inline void io_write_32(uintptr_t addr, uint32_t value)
|
||||
{
|
||||
*(volatile uint32_t *)addr = value;
|
||||
}
|
||||
|
||||
static inline uint32_t io_read_32(uintptr_t addr)
|
||||
{
|
||||
return *(volatile uint32_t *)addr;
|
||||
}
|
||||
|
||||
static inline void io_write_64(uintptr_t addr, uint64_t value)
|
||||
{
|
||||
*(volatile uint64_t *)addr = value;
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
uintptr_t addr;
|
||||
uint64_t value;
|
||||
} mstat_slot_t;
|
||||
|
||||
extern uint32_t qos_init_ddr_ch;
|
||||
extern uint8_t qos_init_ddr_phyvalid;
|
||||
|
||||
#endif /* QOS_COMMON_H */
|
||||
|
|
@ -1,121 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QOS_REG_H
|
||||
#define QOS_REG_H
|
||||
|
||||
#define RCAR_QOS_NONE (3U)
|
||||
#define RCAR_QOS_TYPE_DEFAULT (0U)
|
||||
|
||||
#define RCAR_DRAM_SPLIT_LINEAR (0U)
|
||||
#define RCAR_DRAM_SPLIT_4CH (1U)
|
||||
#define RCAR_DRAM_SPLIT_2CH (2U)
|
||||
#define RCAR_DRAM_SPLIT_AUTO (3U)
|
||||
#define RST_BASE (0xE6160000U)
|
||||
#define RST_MODEMR (RST_BASE + 0x0060U)
|
||||
|
||||
#define DBSC_BASE (0xE6790000U)
|
||||
#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U)
|
||||
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
|
||||
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
|
||||
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
|
||||
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
|
||||
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
|
||||
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
|
||||
#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U)
|
||||
#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U)
|
||||
#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U)
|
||||
#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU)
|
||||
#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U)
|
||||
#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U)
|
||||
#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U)
|
||||
#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU)
|
||||
#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U)
|
||||
#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U)
|
||||
#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U)
|
||||
#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU)
|
||||
#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U)
|
||||
#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U)
|
||||
#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U)
|
||||
#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU)
|
||||
#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U)
|
||||
#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U)
|
||||
#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U)
|
||||
#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU)
|
||||
#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U)
|
||||
#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U)
|
||||
#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U)
|
||||
#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU)
|
||||
#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U)
|
||||
#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U)
|
||||
#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U)
|
||||
#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU)
|
||||
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
|
||||
|
||||
#define AXI_BASE (0xE6784000U)
|
||||
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
|
||||
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
|
||||
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
|
||||
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
|
||||
#define AXI_MMCR (AXI_BASE + 0x0300U)
|
||||
#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
|
||||
#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
|
||||
#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
|
||||
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
|
||||
#define ADSPLCR0_SWP (0x0CU)
|
||||
|
||||
#define AXI_TR3CR (0xE67D100CU)
|
||||
#define AXI_TR4CR (0xE67D1014U)
|
||||
|
||||
#define QOS_BASE0 (0xE67E0000U)
|
||||
#define QOSBW_FIX_QOS_BANK0 (QOS_BASE0 + 0x0000U)
|
||||
#define QOSBW_FIX_QOS_BANK1 (QOS_BASE0 + 0x1000U)
|
||||
#define QOSBW_BE_QOS_BANK0 (QOS_BASE0 + 0x2000U)
|
||||
#define QOSBW_BE_QOS_BANK1 (QOS_BASE0 + 0x3000U)
|
||||
#define QOSCTRL_SL_INIT (QOS_BASE0 + 0x8000U)
|
||||
#define QOSCTRL_REF_ARS (QOS_BASE0 + 0x8004U)
|
||||
#define QOSCTRL_STATQC (QOS_BASE0 + 0x8008U)
|
||||
|
||||
#define QOS_BASE1 (0xE67F0000U)
|
||||
#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U)
|
||||
#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U)
|
||||
#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U)
|
||||
#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U)
|
||||
#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U)
|
||||
#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U)
|
||||
#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U)
|
||||
|
||||
#define GPU_ACT_GRD (0xFD820808U)
|
||||
#define GPU_ACT0 (0xFD820800U)
|
||||
#define GPU_ACT1 (0xFD821800U)
|
||||
#define GPU_ACT2 (0xFD822800U)
|
||||
#define GPU_ACT3 (0xFD823800U)
|
||||
#define GPU_ACT4 (0xFD824800U)
|
||||
#define GPU_ACT5 (0xFD825800U)
|
||||
#define GPU_ACT6 (0xFD826800U)
|
||||
#define GPU_ACT7 (0xFD827800U)
|
||||
|
||||
#define RT_ACT0 (0xFFC50800U)
|
||||
#define RT_ACT1 (0xFFC51800U)
|
||||
|
||||
#define CPU_ACT0 (0xF1300800U)
|
||||
#define CPU_ACT1 (0xF1340800U)
|
||||
#define CPU_ACT2 (0xF1380800U)
|
||||
#define CPU_ACT3 (0xF13C0800U)
|
||||
|
||||
#define RCAR_REWT_TRAINING_DISABLE (0U)
|
||||
#define RCAR_REWT_TRAINING_ENABLE (1U)
|
||||
|
||||
#define QOSWT_FIX_WTQOS_BANK0 (QOSBW_FIX_QOS_BANK0 + 0x0800U)
|
||||
#define QOSWT_FIX_WTQOS_BANK1 (QOSBW_FIX_QOS_BANK1 + 0x0800U)
|
||||
#define QOSWT_BE_WTQOS_BANK0 (QOSBW_BE_QOS_BANK0 + 0x0800U)
|
||||
#define QOSWT_BE_WTQOS_BANK1 (QOSBW_BE_QOS_BANK1 + 0x0800U)
|
||||
#define QOSWT_WTEN (QOS_BASE0 + 0x8030U)
|
||||
#define QOSWT_WTREF (QOS_BASE0 + 0x8034U)
|
||||
#define QOSWT_WTSET0 (QOS_BASE0 + 0x8038U)
|
||||
#define QOSWT_WTSET1 (QOS_BASE0 + 0x803CU)
|
||||
|
||||
#endif /* QOS_REG_H */
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef RCAR_PRINTF_H
|
||||
#define RCAR_PRINTF_H
|
||||
|
||||
#define CONSOLE_T_RCAR_BASE CONSOLE_T_DRVDATA
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
console_t console;
|
||||
uintptr_t base;
|
||||
} console_rcar_t;
|
||||
|
||||
/*
|
||||
* Initialize a new rcar console instance and register it with the console
|
||||
* framework. The |console| pointer must point to storage that will be valid
|
||||
* for the lifetime of the console, such as a global or static local variable.
|
||||
* Its contents will be reinitialized from scratch.
|
||||
*/
|
||||
int console_rcar_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
|
||||
console_rcar_t *console);
|
||||
|
||||
#endif /*__ASSEMBLY__*/
|
||||
|
||||
#endif /* RCAR_PRINTF_H */
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -20,7 +20,7 @@
|
|||
|
||||
.globl plat_crash_console_init
|
||||
.globl plat_crash_console_putc
|
||||
.globl plat_crash_console_flush
|
||||
.globl plat_crash_console_flush
|
||||
.globl plat_invalidate_icache
|
||||
.globl plat_report_exception
|
||||
.globl plat_secondary_reset
|
||||
|
|
@ -28,6 +28,10 @@
|
|||
.globl plat_my_core_pos
|
||||
.extern rcar_log_init
|
||||
|
||||
.extern console_rcar_init
|
||||
.extern console_rcar_putc
|
||||
.extern console_rcar_flush
|
||||
|
||||
#if IMAGE_BL2
|
||||
#define INT_ID_MASK (0x3ff)
|
||||
.extern bl2_interrupt_error_type
|
||||
|
|
@ -258,7 +262,7 @@ func plat_crash_console_init
|
|||
mov sp, x2
|
||||
str x1, [sp, #-16]!
|
||||
str x30, [sp, #-16]!
|
||||
bl console_core_init
|
||||
bl console_rcar_init
|
||||
ldr x30, [sp], #16
|
||||
ldr x1, [sp], #16
|
||||
mov sp, x1
|
||||
|
|
@ -280,7 +284,7 @@ func plat_crash_console_putc
|
|||
str x3, [sp, #-16]!
|
||||
str x4, [sp, #-16]!
|
||||
str x5, [sp, #-16]!
|
||||
bl console_core_putc
|
||||
bl console_rcar_putc
|
||||
ldr x5, [sp], #16
|
||||
ldr x4, [sp], #16
|
||||
ldr x3, [sp], #16
|
||||
|
|
@ -292,11 +296,10 @@ endfunc plat_crash_console_putc
|
|||
|
||||
/* ---------------------------------------------
|
||||
* int plat_crash_console_flush()
|
||||
*
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func plat_crash_console_flush
|
||||
b console_flush
|
||||
b console_rcar_flush
|
||||
endfunc plat_crash_console_flush
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -686,8 +686,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
|
|||
if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
|
||||
boot_cpu == MODEMR_BOOT_CPU_CA53) {
|
||||
rcar_pfc_init();
|
||||
/* console configuration (platform specific) done in driver */
|
||||
console_init(0, 0, 0);
|
||||
rcar_console_boot_init();
|
||||
}
|
||||
|
||||
plat_rcar_gic_driver_init();
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -79,9 +79,7 @@ struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
|
|||
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
|
||||
u_register_t arg2, u_register_t arg3)
|
||||
{
|
||||
/* dummy config: the actual console configuration (platform specific)
|
||||
is done in the driver (scif.c) */
|
||||
console_init(1, 0, 0);
|
||||
rcar_console_runtime_init();
|
||||
|
||||
NOTICE("BL3-1 : Rev.%s\n", version_of_renesas);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -99,4 +99,9 @@ void plat_cci_init(void);
|
|||
void mstpcr_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t target_bit);
|
||||
void cpg_write(uintptr_t regadr, uint32_t regval);
|
||||
|
||||
void rcar_console_boot_init(void);
|
||||
void rcar_console_boot_end(void);
|
||||
void rcar_console_runtime_init(void);
|
||||
void rcar_console_runtime_end(void);
|
||||
|
||||
#endif /* RCAR_PRIVATE_H */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
# Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
|
@ -12,6 +12,7 @@ RESET_TO_BL31 := 1
|
|||
GENERATE_COT := 1
|
||||
BL2_AT_EL3 := 1
|
||||
ENABLE_SVE_FOR_NS := 0
|
||||
MULTI_CONSOLE_API := 1
|
||||
|
||||
CRASH_REPORTING := 1
|
||||
HANDLE_EA_EL3_FIRST := 1
|
||||
|
|
@ -348,12 +349,12 @@ ERRATA_A57_859972 := 1
|
|||
ERRATA_A57_813419 := 1
|
||||
|
||||
include drivers/staging/renesas/rcar/ddr/ddr.mk
|
||||
include drivers/staging/renesas/rcar/qos/qos.mk
|
||||
include drivers/renesas/rcar/qos/qos.mk
|
||||
include drivers/staging/renesas/rcar/pfc/pfc.mk
|
||||
include lib/libfdt/libfdt.mk
|
||||
|
||||
PLAT_INCLUDES := -Idrivers/staging/renesas/rcar/ddr \
|
||||
-Idrivers/staging/renesas/rcar/qos \
|
||||
-Idrivers/renesas/rcar/qos \
|
||||
-Idrivers/renesas/rcar/iic_dvfs \
|
||||
-Idrivers/renesas/rcar/board \
|
||||
-Idrivers/renesas/rcar/cpld/ \
|
||||
|
|
|
|||
|
|
@ -67,3 +67,38 @@ void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
|
|||
|
||||
panic();
|
||||
}
|
||||
|
||||
#include <drivers/renesas/rcar/console/console.h>
|
||||
|
||||
static console_rcar_t rcar_boot_console;
|
||||
static console_rcar_t rcar_runtime_console;
|
||||
|
||||
void rcar_console_boot_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = console_rcar_register(0, 0, 0, &rcar_boot_console);
|
||||
if (!ret)
|
||||
panic();
|
||||
|
||||
console_set_scope(&rcar_boot_console.console, CONSOLE_FLAG_BOOT);
|
||||
}
|
||||
|
||||
void rcar_console_boot_end(void)
|
||||
{
|
||||
}
|
||||
|
||||
void rcar_console_runtime_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = console_rcar_register(1, 0, 0, &rcar_runtime_console);
|
||||
if (!ret)
|
||||
panic();
|
||||
|
||||
console_set_scope(&rcar_boot_console.console, CONSOLE_FLAG_RUNTIME);
|
||||
}
|
||||
|
||||
void rcar_console_runtime_end(void)
|
||||
{
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue