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refactor(mte): remove mte, mte_perm 

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently context saved/restored are needed
only when FEAT_MTE2 is enabled, so move to usage of FEAT_MTE2 and
remove FEAT_MTE usage.

BREAKING CHANGE: Any platform or downstream code trying to use
SCR_EL3.ATA bit(26) will see failures as this is now moved to be
used only with FEAT_MTE2 with
commit@ef0d0e5478a3f19cbe70a378b9b184036db38fe2

Change-Id: Id01e154156571f7792135639e17dc5c8d0e17cf8
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
This commit is contained in:
Govindraj Raja 2024-03-07 14:42:20 -06:00
parent e7419780f7
commit c282384dbb
14 changed files with 31 additions and 66 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Makefile
View File

@ -1221,7 +1221,6 @@ $(eval $(call assert_numerics,\
ENABLE_FEAT_ECV \
ENABLE_FEAT_FGT \
ENABLE_FEAT_HCX \
ENABLE_FEAT_MTE \
ENABLE_FEAT_MTE2 \
ENABLE_FEAT_PAN \
ENABLE_FEAT_RNG \
@ -1235,7 +1234,6 @@ $(eval $(call assert_numerics,\
ENABLE_FEAT_S1POE \
ENABLE_FEAT_GCS \
ENABLE_FEAT_VHE \
ENABLE_FEAT_MTE_PERM \
ENABLE_FEAT_MPAM \
ENABLE_RME \
ENABLE_SPE_FOR_NS \
@ -1384,9 +1382,7 @@ $(eval $(call add_defines,\
ENABLE_FEAT_S2POE \
ENABLE_FEAT_S1POE \
ENABLE_FEAT_GCS \
ENABLE_FEAT_MTE \
ENABLE_FEAT_MTE2 \
ENABLE_FEAT_MTE_PERM \
FEATURE_DETECTION \
TWED_DELAY \
ENABLE_FEAT_TWED \

2
bl31/bl31_traps.c
View File

@ -165,7 +165,7 @@ u_register_t create_spsr(u_register_t old_spsr, unsigned int target_el)
/* If FEAT_MTE2 is implemented mask tag faults by setting TCO bit */
new_spsr |= old_spsr & SPSR_TCO_BIT_AARCH64;
if (read_feat_mte_id_field() >= MTE_IMPLEMENTED_ELX) {
if (is_feat_mte2_present()) {
new_spsr |= SPSR_TCO_BIT_AARCH64;
}

4
bl32/tsp/tsp_main.c
View File

@ -239,10 +239,10 @@ smc_args_t *tsp_smc_handler(uint64_t func,
service_arg1 = (uint64_t)(service_args >> 64U);
/*
* Write a dummy value to an MTE register, to simulate usage in the
* Write a dummy value to an MTE2 register, to simulate usage in the
* secure world
*/
if (is_feat_mte_supported()) {
if (is_feat_mte2_supported()) {
write_gcr_el1(0x99);
}

6
common/feat_detect.c
View File

@ -167,9 +167,7 @@ void detect_arch_features(void)
"TRF", 1, 1);
/* v8.5 features */
check_feature(ENABLE_FEAT_MTE, read_feat_mte_id_field(), "MTE",
MTE_IMPLEMENTED_EL0, MTE_IMPLEMENTED_ASY);
check_feature(ENABLE_FEAT_MTE2, read_feat_mte_id_field(), "MTE2",
check_feature(ENABLE_FEAT_MTE2, get_armv8_5_mte_support(), "MTE2",
MTE_IMPLEMENTED_ELX, MTE_IMPLEMENTED_ASY);
check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(), "RNG", 1, 1);
read_feat_bti();
@ -204,8 +202,6 @@ void detect_arch_features(void)
"S2POE", 1, 1);
check_feature(ENABLE_FEAT_S1POE, read_feat_s1poe_id_field(),
"S1POE", 1, 1);
check_feature(ENABLE_FEAT_MTE_PERM, read_feat_mte_perm_id_field(),
"MTE_PERM", 1, 1);
check_feature(ENABLE_FEAT_CSV2_3, read_feat_csv2_id_field(),
"CSV2_3", 3, 3);

4
docs/components/secure-partition-manager.rst
View File

@ -215,7 +215,7 @@ implemented and the SPMC is located at S-EL2:
ARM_ARCH_MINOR=5 \
BRANCH_PROTECTION=1 \
CTX_INCLUDE_PAUTH_REGS=1 \
ENABLE_FEAT_MTE=1 \
ENABLE_FEAT_MTE2=1 \
BL32=<path-to-hafnium-binary> \
BL33=<path-to-bl33-binary> \
SP_LAYOUT_FILE=sp_layout.json \
@ -233,7 +233,7 @@ implemented, the SPMC is located at S-EL2, and enabling secure boot:
ARM_ARCH_MINOR=5 \
BRANCH_PROTECTION=1 \
CTX_INCLUDE_PAUTH_REGS=1 \
ENABLE_FEAT_MTE=1 \
ENABLE_FEAT_MTE2=1 \
BL32=<path-to-hafnium-binary> \
BL33=<path-to-bl33-binary> \
SP_LAYOUT_FILE=sp_layout.json \

8
docs/design/firmware-design.rst
View File

@ -2800,9 +2800,11 @@ Armv8.5-A
- Branch Target Identification feature is selected by ``BRANCH_PROTECTION``
option set to 1. This option defaults to 0.
- Memory Tagging Extension feature is unconditionally enabled for both worlds.
To enable MTE at EL0 use ``ENABLE_FEAT_MTE`` is required and to enable MTE at
ELX ``ENABLE_FEAT_MTE2`` is required.
- Memory Tagging Extension feature has few variants but not all of them require
enablement from EL3 to be used at lower EL. e.g. Memory tagging only at
EL0(MTE) does not require EL3 configuration however memory tagging at
EL2/EL1 (MTE2) does require EL3 enablement and we need to set this option
``ENABLE_FEAT_MTE2`` to 1. This option defaults to 0.
Armv7-A
~~~~~~~

12
docs/getting_started/build-options.rst
View File

@ -340,23 +340,11 @@ Common build options
flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
mechanism. Default value is ``0``.
- ``ENABLE_FEAT_MTE``: Numeric value to enable Memory Tagging Extension
if the platform wants to use this feature at EL0 ``ENABLE_FEAT_MTE`` is
required. This flag can take values 0 to 2, to align with the ``ENABLE_FEAT``
feature detection mechanism. Default value is ``0``.
- ``ENABLE_FEAT_MTE2``: Numeric value to enable Memory Tagging Extension2
if the platform wants to use this feature and MTE2 is enabled at ELX.
This flag can take values 0 to 2, to align with the ``ENABLE_FEAT``
mechanism. Default value is ``0``.
- ``ENABLE_FEAT_MTE_PERM``: Numeric value to enable support for
``FEAT_MTE_PERM``, which introduces Allocation tag access permission to
memory region attributes. ``FEAT_MTE_PERM`` is a optional architectural
feature available from v8.9 and upwards. This flag can take the values 0 to
2, to align with the ``ENABLE_FEAT`` mechanism. Default value is
``0``.
- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged
Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a
permission fault for any privileged data access from EL1/EL2 to virtual

1
include/arch/aarch32/arch_features.h
View File

@ -159,7 +159,6 @@ static inline bool is_feat_tcr2_supported(void) { return false; }
static inline bool is_feat_spe_supported(void) { return false; }
static inline bool is_feat_rng_supported(void) { return false; }
static inline bool is_feat_gcs_supported(void) { return false; }
static inline bool is_feat_mte_supported(void) { return false; }
static inline bool is_feat_mte2_supported(void) { return false; }
static inline bool is_feat_mpam_supported(void) { return false; }
static inline bool is_feat_hcx_supported(void) { return false; }

12
include/arch/aarch64/arch_features.h
View File

@ -105,6 +105,10 @@ static inline unsigned int get_armv8_5_mte_support(void)
return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) &
ID_AA64PFR1_EL1_MTE_MASK);
}
static inline unsigned int is_feat_mte2_present(void)
{
return get_armv8_5_mte_support() >= MTE_IMPLEMENTED_ELX;
}
static inline bool is_feat_ssbs_present(void)
{
@ -136,18 +140,14 @@ static inline bool is_feat_sebep_present(void)
ID_AA64DFR0_SEBEP_MASK) == SEBEP_IMPLEMENTED;
}
CREATE_FEATURE_FUNCS(feat_mte, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT,
ENABLE_FEAT_MTE)
CREATE_FEATURE_FUNCS_VER(feat_mte2, read_feat_mte_id_field, MTE_IMPLEMENTED_ELX,
ENABLE_FEAT_MTE2)
CREATE_FEATURE_FUNCS_VER(feat_mte2, get_armv8_5_mte_support, MTE_IMPLEMENTED_ELX,
ENABLE_FEAT_MTE2)
CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT,
ENABLE_FEAT_SEL2)
CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT,
ENABLE_FEAT_TWED)
CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
ENABLE_FEAT_FGT)
CREATE_FEATURE_FUNCS(feat_mte_perm, id_aa64pfr2_el1,
ID_AA64PFR2_EL1_MTEPERM_SHIFT, ENABLE_FEAT_MTE_PERM)
CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
ENABLE_FEAT_ECV)
CREATE_FEATURE_FUNCS_VER(feat_ecv_v2, read_feat_ecv_id_field,

4
include/lib/el3_runtime/aarch64/context.h
View File

@ -141,7 +141,7 @@
#define CTX_TIMER_SYSREGS_END CTX_AARCH32_END
#endif /* NS_TIMER_SWITCH */
#if ENABLE_FEAT_MTE
#if ENABLE_FEAT_MTE2
#define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0))
#define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8))
#define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10))
@ -151,7 +151,7 @@
#define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20))
#else
#define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END
#endif /* ENABLE_FEAT_MTE */
#endif /* ENABLE_FEAT_MTE2 */
/*
* End of system registers.

12
lib/el3_runtime/aarch64/context_mgmt.c
View File

@ -1277,7 +1277,7 @@ void cm_el2_sysregs_context_save(uint32_t security_state)
el2_sysregs_context_save_common(el2_sysregs_ctx);
el2_sysregs_context_save_gic(el2_sysregs_ctx);
if (is_feat_mte_supported()) {
if (is_feat_mte2_supported()) {
write_el2_ctx_mte(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2());
}
@ -1363,7 +1363,7 @@ void cm_el2_sysregs_context_restore(uint32_t security_state)
el2_sysregs_context_restore_common(el2_sysregs_ctx);
el2_sysregs_context_restore_gic(el2_sysregs_ctx);
if (is_feat_mte_supported()) {
if (is_feat_mte2_supported()) {
write_tfsr_el2(read_el2_ctx_mte(el2_sysregs_ctx, tfsr_el2));
}
@ -1508,12 +1508,12 @@ static void el1_sysregs_context_save(el1_sysregs_t *ctx)
write_ctx_reg(ctx, CTX_CNTKCTL_EL1, read_cntkctl_el1());
#endif /* NS_TIMER_SWITCH */
#if ENABLE_FEAT_MTE
#if ENABLE_FEAT_MTE2
write_ctx_reg(ctx, CTX_TFSRE0_EL1, read_tfsre0_el1());
write_ctx_reg(ctx, CTX_TFSR_EL1, read_tfsr_el1());
write_ctx_reg(ctx, CTX_RGSR_EL1, read_rgsr_el1());
write_ctx_reg(ctx, CTX_GCR_EL1, read_gcr_el1());
#endif /* ENABLE_FEAT_MTE */
#endif /* ENABLE_FEAT_MTE2 */
}
@ -1563,12 +1563,12 @@ static void el1_sysregs_context_restore(el1_sysregs_t *ctx)
write_cntkctl_el1(read_ctx_reg(ctx, CTX_CNTKCTL_EL1));
#endif /* NS_TIMER_SWITCH */
#if ENABLE_FEAT_MTE
#if ENABLE_FEAT_MTE2
write_tfsre0_el1(read_ctx_reg(ctx, CTX_TFSRE0_EL1));
write_tfsr_el1(read_ctx_reg(ctx, CTX_TFSR_EL1));
write_rgsr_el1(read_ctx_reg(ctx, CTX_RGSR_EL1));
write_gcr_el1(read_ctx_reg(ctx, CTX_GCR_EL1));
#endif /* ENABLE_FEAT_MTE */
#endif /* ENABLE_FEAT_MTE2 */
}

26
make_helpers/arch_features.mk
View File

@ -307,28 +307,17 @@ CTX_INCLUDE_NEVE_REGS ?= 0
# registers, by setting SCR_EL3.TRNDR.
ENABLE_FEAT_RNG_TRAP ?= 0
# Enable Memory Tagging Extension. This must be set to 1 if the platform wants
# to use this feature in the Secure world and MTE is enabled at ELX.
ifeq ($(CTX_INCLUDE_MTE_REGS),1)
$(warning CTX_INCLUDE_MTE_REGS option is deprecated use ENABLE_FEAT_MTE, Enabling ENABLE_FEAT_MTE)
ENABLE_FEAT_MTE ?= 1
$(warning CTX_INCLUDE_MTE_REGS option is deprecated, Check ENABLE_FEAT_MTE2 usage)
endif
ifeq (${ARCH},aarch32)
ifneq ($(or $(ENABLE_FEAT_MTE),0),0)
$(error ENABLE_FEAT_MTE is not supported for AArch32)
endif
ifeq ($(ENABLE_FEAT_MTE),1)
$(warning ENABLE_FEAT_MTE option is deprecated, Check ENABLE_FEAT_MTE2 usage)
endif
ENABLE_FEAT_MTE ?= 0
# Enable FEAT_MTE2. This must be set to 1 if the platform wants
# to use this feature and is enabled at ELX.
ENABLE_FEAT_MTE2 ?= 0
# Add a error message to indicate incorrect MTE2 selection without MTE enabled.
ifneq ($(ENABLE_FEAT_MTE2),0)
ifeq ($(ENABLE_FEAT_MTE),0)
$(error ENABLE_FEAT_MTE2 is not supported without enabling ENABLE_FEAT_MTE)
endif
endif
#----
# 8.6
#----
@ -352,9 +341,6 @@ DISABLE_MTPMU ?= 0
# 8.9
#----
# Flag to enable NoTagAccess memory region attribute for stage 2 of translation.
ENABLE_FEAT_MTE_PERM ?= 0
# Flag to enable access to Stage 2 Permission Indirection (FEAT_S2PIE).
ENABLE_FEAT_S2PIE ?= 0

1
plat/arm/board/fvp/platform.mk
View File

@ -76,7 +76,6 @@ ENABLE_FEAT_CSV2_2 := 2
ENABLE_FEAT_CSV2_3 := 2
ENABLE_FEAT_DIT := 2
ENABLE_FEAT_PAN := 2
ENABLE_FEAT_MTE_PERM := 2
ENABLE_FEAT_VHE := 2
CTX_INCLUDE_NEVE_REGS := 2
ENABLE_FEAT_SEL2 := 2

1
plat/arm/board/tc/platform.mk
View File

@ -40,7 +40,6 @@ CTX_INCLUDE_AARCH32_REGS := 0
ifeq (${SPD},spmd)
SPMD_SPM_AT_SEL2 := 1
ENABLE_FEAT_MTE := 1
CTX_INCLUDE_PAUTH_REGS := 1
endif