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refactor(stm32mp1): remove STM32MP_USE_STM32IMAGE 

The code managing legacy boot (without FIP) that was under
STM32MP_USE_STM32IMAGE flag is remove.

Change-Id: I04452453ed84567b0de39e900594a81526562259
Signed-off-by: Yann Gautier <yann.gautier@st.com>
This commit is contained in:
Yann Gautier 2022-11-14 14:14:48 +01:00
parent c3170fd80b
commit 981b9dcb87
23 changed files with 10 additions and 1674 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
docs/about/release-information.rst
View File

@ -65,8 +65,6 @@ after which it will be removed.
| | Date | after | |
| | | Release | |
+================================+=============+=========+=========================================================+
| STM32MP_USE_STM32IMAGE macro | Dec '21 | 2.7 | FIP is the recommended boot method for STM32MP |
+--------------------------------+-------------+---------+---------------------------------------------------------+
| plat_convert_pk() function | Nov'22 | Next | Platform conversion to manage specific PK hash |
| | | release | |
| | | after | |

63
docs/plat/stm32mp1.rst
View File

@ -63,15 +63,6 @@ Only BL2 (with STM32 header) is loaded by ROM code. The other binaries are
inside the FIP binary: BL32 (SP_min or OP-TEE), U-Boot and their respective
device tree blobs.
STM32IMAGE bootchain
~~~~~~~~~~~~~~~~~~~~
Although still supported, this way of booting is not recommended.
Pease use FIP instead.
At compilation step, BL2, BL32 and DTB file are linked together in a single
binary. The stm32image tool is also generated and the header is added to TF-A
binary. This binary file with header is named tf-a-stm32mp157c-ev1.stm32.
It can then be copied in the first partition of the boot device.
Memory mapping
~~~~~~~~~~~~~~
@ -270,44 +261,6 @@ __________________
--stm32mp-cfg-cert build/stm32mp1/cert_images/stm32mp_cfg_cert.crt stm32mp1.fip
STM32IMAGE bootchain
~~~~~~~~~~~~~~~~~~~~
You need to add the following flag to the make command:
``STM32MP_USE_STM32IMAGE=1``
To build with SP_min and support for SD-card boot:
.. code:: bash
make CROSS_COMPILE=arm-linux-gnueabihf- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
AARCH32_SP=sp_min STM32MP_SDMMC=1 DTB_FILE_NAME=stm32mp157c-ev1.dtb \
STM32MP_USE_STM32IMAGE=1
cd <u-boot_directory>
make stm32mp15_trusted_defconfig
make DEVICE_TREE=stm32mp157c-ev1 all
To build TF-A with OP-TEE support for SD-card boot:
.. code:: bash
make CROSS_COMPILE=arm-linux-gnueabihf- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
AARCH32_SP=optee STM32MP_SDMMC=1 DTB_FILE_NAME=stm32mp157c-ev1.dtb \
STM32MP_USE_STM32IMAGE=1
cd <optee_directory>
make CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm PLATFORM=stm32mp1 \
CFG_EMBED_DTB_SOURCE_FILE=stm32mp157c-ev1.dts
cd <u-boot_directory>
make stm32mp15_trusted_defconfig
make DEVICE_TREE=stm32mp157c-ev1 all
The following build options are supported:
- ``ENABLE_STACK_PROTECTOR``: To enable the stack protection.
Populate SD-card
----------------
@ -322,22 +275,6 @@ It should contain at least those partitions:
Usually, two copies of fsbl are used (fsbl1 and fsbl2) instead of one partition fsbl.
STM32IMAGE bootchain
~~~~~~~~~~~~~~~~~~~~
The SD-card has to be formatted with GPT.
It should contain at least those partitions:
- fsbl: to copy the tf-a-stm32mp157c-ev1.stm32 binary
- ssbl: to copy the u-boot.stm32 binary
Usually, two copies of fsbl are used (fsbl1 and fsbl2) instead of one partition fsbl.
OP-TEE artifacts go into separate partitions as follows:
- teeh: tee-header_v2.stm32
- teed: tee-pageable_v2.stm32
- teex: tee-pager_v2.stm32
.. _STM32MP1 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html
.. _STM32MP1 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP15_microprocessor#Part_number_codification

366
drivers/st/io/io_stm32image.c
View File

@ -1,366 +0,0 @@
/*
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <errno.h>
#include <stdint.h>
#include <string.h>
#include <platform_def.h>
#include <common/debug.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_storage.h>
#include <drivers/st/io_stm32image.h>
#include <lib/utils.h>
#include <plat/common/platform.h>
static uintptr_t backend_dev_handle;
static uintptr_t backend_image_spec;
static uint32_t *stm32_img;
static uint8_t first_lba_buffer[MAX_LBA_SIZE] __aligned(4);
static struct stm32image_part_info *current_part;
/* STM32 Image driver functions */
static int stm32image_dev_open(const uintptr_t init_params,
io_dev_info_t **dev_info);
static int stm32image_partition_open(io_dev_info_t *dev_info,
const uintptr_t spec, io_entity_t *entity);
static int stm32image_partition_size(io_entity_t *entity, size_t *length);
static int stm32image_partition_read(io_entity_t *entity, uintptr_t buffer,
size_t length, size_t *length_read);
static int stm32image_partition_close(io_entity_t *entity);
static int stm32image_dev_init(io_dev_info_t *dev_info,
const uintptr_t init_params);
static int stm32image_dev_close(io_dev_info_t *dev_info);
/* Identify the device type as a virtual driver */
static io_type_t device_type_stm32image(void)
{
return IO_TYPE_STM32IMAGE;
}
static const io_dev_connector_t stm32image_dev_connector = {
.dev_open = stm32image_dev_open
};
static const io_dev_funcs_t stm32image_dev_funcs = {
.type = device_type_stm32image,
.open = stm32image_partition_open,
.size = stm32image_partition_size,
.read = stm32image_partition_read,
.close = stm32image_partition_close,
.dev_init = stm32image_dev_init,
.dev_close = stm32image_dev_close,
};
static io_dev_info_t stm32image_dev_info = {
.funcs = &stm32image_dev_funcs,
.info = (uintptr_t)0,
};
static struct stm32image_device_info stm32image_dev;
static int get_part_idx_by_binary_type(uint32_t binary_type)
{
int i;
for (i = 0; i < STM32_PART_NUM; i++) {
if (stm32image_dev.part_info[i].binary_type == binary_type) {
return i;
}
}
return -EINVAL;
}
/* Open a connection to the STM32IMAGE device */
static int stm32image_dev_open(const uintptr_t init_params,
io_dev_info_t **dev_info)
{
int i;
struct stm32image_device_info *device_info =
(struct stm32image_device_info *)init_params;
assert(dev_info != NULL);
*dev_info = (io_dev_info_t *)&stm32image_dev_info;
stm32image_dev.device_size = device_info->device_size;
stm32image_dev.lba_size = device_info->lba_size;
for (i = 0; i < STM32_PART_NUM; i++) {
memcpy(stm32image_dev.part_info[i].name,
device_info->part_info[i].name, MAX_PART_NAME_SIZE);
stm32image_dev.part_info[i].binary_type =
device_info->part_info[i].binary_type;
stm32image_dev.part_info[i].part_offset =
device_info->part_info[i].part_offset;
stm32image_dev.part_info[i].bkp_offset =
device_info->part_info[i].bkp_offset;
}
return 0;
}
/* Do some basic package checks */
static int stm32image_dev_init(io_dev_info_t *dev_info,
const uintptr_t init_params)
{
int result;
if ((backend_dev_handle != 0U) || (backend_image_spec != 0U)) {
ERROR("STM32 Image io supports only one session\n");
return -ENOMEM;
}
/* Obtain a reference to the image by querying the platform layer */
result = plat_get_image_source(STM32_IMAGE_ID, &backend_dev_handle,
&backend_image_spec);
if (result != 0) {
ERROR("STM32 image error (%i)\n", result);
return -EINVAL;
}
return result;
}
/* Close a connection to the STM32 Image device */
static int stm32image_dev_close(io_dev_info_t *dev_info)
{
backend_dev_handle = 0U;
backend_image_spec = 0U;
stm32_img = NULL;
return 0;
}
/* Open a partition */
static int stm32image_partition_open(io_dev_info_t *dev_info,
const uintptr_t spec, io_entity_t *entity)
{
const struct stm32image_part_info *partition_spec;
int idx;
assert(entity != NULL);
partition_spec = (struct stm32image_part_info *)spec;
assert(partition_spec != NULL);
idx = get_part_idx_by_binary_type(partition_spec->binary_type);
if ((idx < 0) || (idx > STM32_PART_NUM)) {
ERROR("Wrong partition index (%d)\n", idx);
return -EINVAL;
}
current_part = &stm32image_dev.part_info[idx];
stm32_img = (uint32_t *)&current_part->part_offset;
return 0;
}
/* Return the size of a partition */
static int stm32image_partition_size(io_entity_t *entity, size_t *length)
{
int result;
uintptr_t backend_handle;
size_t bytes_read;
boot_api_image_header_t *header =
(boot_api_image_header_t *)first_lba_buffer;
assert(entity != NULL);
assert(length != NULL);
/* Attempt to access the image */
result = io_open(backend_dev_handle, backend_image_spec,
&backend_handle);
if (result < 0) {
ERROR("%s: io_open (%i)\n", __func__, result);
return result;
}
/* Reset magic header value */
header->magic = 0;
while (header->magic == 0U) {
result = io_seek(backend_handle, IO_SEEK_SET, *stm32_img);
if (result != 0) {
ERROR("%s: io_seek (%i)\n", __func__, result);
break;
}
result = io_read(backend_handle, (uintptr_t)header,
MAX_LBA_SIZE, (size_t *)&bytes_read);
if (result != 0) {
if (current_part->bkp_offset == 0U) {
ERROR("%s: io_read (%i)\n", __func__, result);
}
header->magic = 0;
}
if ((header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) ||
(header->binary_type != current_part->binary_type) ||
(header->image_length >= stm32image_dev.device_size)) {
VERBOSE("%s: partition %s not found at %x\n",
__func__, current_part->name, *stm32_img);
if (current_part->bkp_offset == 0U) {
result = -ENOMEM;
break;
}
/* Header not correct, check next offset for backup */
*stm32_img += current_part->bkp_offset;
if (*stm32_img > stm32image_dev.device_size) {
/* No backup found, end of device reached */
WARN("%s : partition %s not found\n",
__func__, current_part->name);
result = -ENOMEM;
break;
}
header->magic = 0;
}
}
io_close(backend_handle);
if (result != 0) {
return result;
}
if (header->image_length < stm32image_dev.lba_size) {
*length = stm32image_dev.lba_size;
} else {
*length = header->image_length;
}
INFO("STM32 Image size : %lu\n", (unsigned long)*length);
return 0;
}
/* Read data from a partition */
static int stm32image_partition_read(io_entity_t *entity, uintptr_t buffer,
size_t length, size_t *length_read)
{
int result = -EINVAL;
uint8_t *local_buffer;
boot_api_image_header_t *header =
(boot_api_image_header_t *)first_lba_buffer;
size_t hdr_sz = sizeof(boot_api_image_header_t);
assert(entity != NULL);
assert(buffer != 0U);
assert(length_read != NULL);
local_buffer = (uint8_t *)buffer;
*length_read = 0U;
while (*length_read == 0U) {
int offset;
int local_length;
uintptr_t backend_handle;
if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) {
/* Check for backup as image is corrupted */
if (current_part->bkp_offset == 0U) {
result = -ENOMEM;
break;
}
*stm32_img += current_part->bkp_offset;
if (*stm32_img >= stm32image_dev.device_size) {
/* End of device reached */
result = -ENOMEM;
break;
}
local_buffer = (uint8_t *)buffer;
result = stm32image_partition_size(entity, &length);
if (result != 0) {
break;
}
}
/* Part of image already loaded with the header */
memcpy(local_buffer, (uint8_t *)first_lba_buffer + hdr_sz,
MAX_LBA_SIZE - hdr_sz);
local_buffer += MAX_LBA_SIZE - hdr_sz;
offset = MAX_LBA_SIZE;
/* New image length to be read */
local_length = round_up(length - ((MAX_LBA_SIZE) - hdr_sz),
stm32image_dev.lba_size);
if ((header->load_address != 0U) &&
(header->load_address != buffer)) {
ERROR("Wrong load address\n");
panic();
}
result = io_open(backend_dev_handle, backend_image_spec,
&backend_handle);
if (result != 0) {
ERROR("%s: io_open (%i)\n", __func__, result);
break;
}
result = io_seek(backend_handle, IO_SEEK_SET,
*stm32_img + offset);
if (result != 0) {
ERROR("%s: io_seek (%i)\n", __func__, result);
*length_read = 0;
io_close(backend_handle);
break;
}
result = io_read(backend_handle, (uintptr_t)local_buffer,
local_length, length_read);
/* Adding part of size already read from header */
*length_read += MAX_LBA_SIZE - hdr_sz;
if (result != 0) {
ERROR("%s: io_read (%i)\n", __func__, result);
*length_read = 0;
header->magic = 0;
continue;
}
inv_dcache_range(round_up((uintptr_t)(local_buffer + length - hdr_sz),
CACHE_WRITEBACK_GRANULE), *length_read - length + hdr_sz);
io_close(backend_handle);
}
return result;
}
/* Close a partition */
static int stm32image_partition_close(io_entity_t *entity)
{
current_part = NULL;
return 0;
}
/* Register the stm32image driver with the IO abstraction */
int register_io_dev_stm32image(const io_dev_connector_t **dev_con)
{
int result;
assert(dev_con != NULL);
result = io_register_device(&stm32image_dev_info);
if (result == 0) {
*dev_con = &stm32image_dev_connector;
}
return result;
}

2
fdts/stm32mp15-bl2.dtsi
View File

@ -69,7 +69,6 @@
};
};
#if !STM32MP_USE_STM32IMAGE
/*
* UUID's here are UUID RFC 4122 compliant meaning fieds are stored in
* network order (big endian)
@ -113,5 +112,4 @@
#include "stm32mp1-cot-descriptors.dtsi"
#endif
#endif /* !STM32MP_USE_STM32IMAGE */
};

3
include/drivers/io/io_storage.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -24,7 +24,6 @@ typedef enum {
IO_TYPE_BLOCK,
IO_TYPE_MTD,
IO_TYPE_MMC,
IO_TYPE_STM32IMAGE,
IO_TYPE_ENCRYPTED,
IO_TYPE_MAX
} io_type_t;

32
include/drivers/st/io_stm32image.h
View File

@ -1,32 +0,0 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef IO_STM32IMAGE_H
#define IO_STM32IMAGE_H
#include <drivers/io/io_driver.h>
#include <drivers/partition/partition.h>
#define MAX_LBA_SIZE 512
#define MAX_PART_NAME_SIZE (EFI_NAMELEN + 1)
#define STM32_PART_NUM (PLAT_PARTITION_MAX_ENTRIES - STM32_TF_A_COPIES)
struct stm32image_part_info {
char name[MAX_PART_NAME_SIZE];
uint32_t binary_type;
uintptr_t part_offset;
uint32_t bkp_offset;
};
struct stm32image_device_info {
struct stm32image_part_info part_info[STM32_PART_NUM];
unsigned long long device_size;
uint32_t lba_size;
};
int register_io_dev_stm32image(const io_dev_connector_t **dev_con);
#endif /* IO_STM32IMAGE_H */

667
plat/st/common/bl2_stm32_io_storage.c
View File

@ -1,667 +0,0 @@
/*
* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <string.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/io/io_block.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_dummy.h>
#include <drivers/io/io_mtd.h>
#include <drivers/io/io_storage.h>
#include <drivers/mmc.h>
#include <drivers/partition/partition.h>
#include <drivers/raw_nand.h>
#include <drivers/spi_nand.h>
#include <drivers/spi_nor.h>
#include <drivers/st/io_mmc.h>
#include <drivers/st/io_stm32image.h>
#include <drivers/st/stm32_fmc2_nand.h>
#include <drivers/st/stm32_qspi.h>
#include <drivers/st/stm32_sdmmc2.h>
#include <lib/mmio.h>
#include <lib/utils.h>
#include <plat/common/platform.h>
#include <platform_def.h>
/* IO devices */
#ifndef AARCH32_SP_OPTEE
static const io_dev_connector_t *dummy_dev_con;
static uintptr_t dummy_dev_handle;
static uintptr_t dummy_dev_spec;
#endif
static uintptr_t image_dev_handle;
static uintptr_t storage_dev_handle;
#if STM32MP_SDMMC || STM32MP_EMMC
static struct mmc_device_info mmc_info;
static io_block_spec_t gpt_block_spec = {
.offset = 0U,
.length = 34U * MMC_BLOCK_SIZE, /* Size of GPT table */
};
static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE);
static const io_block_dev_spec_t mmc_block_dev_spec = {
/* It's used as temp buffer in block driver */
.buffer = {
.offset = (size_t)&block_buffer,
.length = MMC_BLOCK_SIZE,
},
.ops = {
.read = mmc_read_blocks,
.write = NULL,
},
.block_size = MMC_BLOCK_SIZE,
};
#if STM32MP_EMMC_BOOT
static io_block_spec_t emmc_boot_ssbl_block_spec = {
.offset = PLAT_EMMC_BOOT_SSBL_OFFSET,
.length = MMC_BLOCK_SIZE, /* We are interested only in first 4 bytes */
};
static const io_block_dev_spec_t mmc_block_dev_boot_part_spec = {
/* It's used as temp buffer in block driver */
.buffer = {
.offset = (size_t)&block_buffer,
.length = MMC_BLOCK_SIZE,
},
.ops = {
.read = mmc_boot_part_read_blocks,
.write = NULL,
},
.block_size = MMC_BLOCK_SIZE,
};
#endif
static struct io_mmc_dev_spec mmc_device_spec = {
.use_boot_part = false,
};
static const io_dev_connector_t *mmc_dev_con;
#endif /* STM32MP_SDMMC || STM32MP_EMMC */
#if STM32MP_SPI_NOR
static io_mtd_dev_spec_t spi_nor_dev_spec = {
.ops = {
.init = spi_nor_init,
.read = spi_nor_read,
},
};
#endif
#if STM32MP_RAW_NAND
static io_mtd_dev_spec_t nand_dev_spec = {
.ops = {
.init = nand_raw_init,
.read = nand_read,
},
};
static const io_dev_connector_t *nand_dev_con;
#endif
#if STM32MP_SPI_NAND
static io_mtd_dev_spec_t spi_nand_dev_spec = {
.ops = {
.init = spi_nand_init,
.read = nand_read,
},
};
#endif
#if STM32MP_SPI_NAND || STM32MP_SPI_NOR
static const io_dev_connector_t *spi_dev_con;
#endif
#ifdef AARCH32_SP_OPTEE
static const struct stm32image_part_info optee_header_partition_spec = {
.name = OPTEE_HEADER_IMAGE_NAME,
.binary_type = OPTEE_HEADER_BINARY_TYPE,
};
static const struct stm32image_part_info optee_core_partition_spec = {
.name = OPTEE_CORE_IMAGE_NAME,
.binary_type = OPTEE_CORE_BINARY_TYPE,
};
static const struct stm32image_part_info optee_paged_partition_spec = {
.name = OPTEE_PAGED_IMAGE_NAME,
.binary_type = OPTEE_PAGED_BINARY_TYPE,
};
#else
static const io_block_spec_t bl32_block_spec = {
.offset = BL32_BASE,
.length = STM32MP_BL32_SIZE
};
#endif
static const struct stm32image_part_info bl33_partition_spec = {
.name = BL33_IMAGE_NAME,
.binary_type = BL33_BINARY_TYPE,
};
enum {
IMG_IDX_BL33,
#ifdef AARCH32_SP_OPTEE
IMG_IDX_OPTEE_HEADER,
IMG_IDX_OPTEE_CORE,
IMG_IDX_OPTEE_PAGED,
#endif
IMG_IDX_NUM
};
static struct stm32image_device_info stm32image_dev_info_spec __unused = {
.lba_size = MMC_BLOCK_SIZE,
.part_info[IMG_IDX_BL33] = {
.name = BL33_IMAGE_NAME,
.binary_type = BL33_BINARY_TYPE,
},
#ifdef AARCH32_SP_OPTEE
.part_info[IMG_IDX_OPTEE_HEADER] = {
.name = OPTEE_HEADER_IMAGE_NAME,
.binary_type = OPTEE_HEADER_BINARY_TYPE,
},
.part_info[IMG_IDX_OPTEE_CORE] = {
.name = OPTEE_CORE_IMAGE_NAME,
.binary_type = OPTEE_CORE_BINARY_TYPE,
},
.part_info[IMG_IDX_OPTEE_PAGED] = {
.name = OPTEE_PAGED_IMAGE_NAME,
.binary_type = OPTEE_PAGED_BINARY_TYPE,
},
#endif
};
static io_block_spec_t stm32image_block_spec = {
.offset = 0U,
.length = 0U,
};
static const io_dev_connector_t *stm32image_dev_con __unused;
#ifndef AARCH32_SP_OPTEE
static int open_dummy(const uintptr_t spec);
#endif
static int open_image(const uintptr_t spec);
static int open_storage(const uintptr_t spec);
struct plat_io_policy {
uintptr_t *dev_handle;
uintptr_t image_spec;
int (*check)(const uintptr_t spec);
};
static const struct plat_io_policy policies[] = {
#ifdef AARCH32_SP_OPTEE
[BL32_IMAGE_ID] = {
.dev_handle = &image_dev_handle,
.image_spec = (uintptr_t)&optee_header_partition_spec,
.check = open_image
},
[BL32_EXTRA1_IMAGE_ID] = {
.dev_handle = &image_dev_handle,
.image_spec = (uintptr_t)&optee_core_partition_spec,
.check = open_image
},
[BL32_EXTRA2_IMAGE_ID] = {
.dev_handle = &image_dev_handle,
.image_spec = (uintptr_t)&optee_paged_partition_spec,
.check = open_image
},
#else
[BL32_IMAGE_ID] = {
.dev_handle = &dummy_dev_handle,
.image_spec = (uintptr_t)&bl32_block_spec,
.check = open_dummy
},
#endif
[BL33_IMAGE_ID] = {
.dev_handle = &image_dev_handle,
.image_spec = (uintptr_t)&bl33_partition_spec,
.check = open_image
},
#if STM32MP_SDMMC || STM32MP_EMMC
[GPT_IMAGE_ID] = {
.dev_handle = &storage_dev_handle,
.image_spec = (uintptr_t)&gpt_block_spec,
.check = open_storage
},
#endif
[STM32_IMAGE_ID] = {
.dev_handle = &storage_dev_handle,
.image_spec = (uintptr_t)&stm32image_block_spec,
.check = open_storage
}
};
#ifndef AARCH32_SP_OPTEE
static int open_dummy(const uintptr_t spec)
{
return io_dev_init(dummy_dev_handle, 0);
}
#endif
static int open_image(const uintptr_t spec)
{
return io_dev_init(image_dev_handle, 0);
}
static int open_storage(const uintptr_t spec)
{
return io_dev_init(storage_dev_handle, 0);
}
#if STM32MP_EMMC_BOOT
static uint32_t get_boot_part_ssbl_header(void)
{
uint32_t magic = 0U;
int io_result;
size_t bytes_read;
io_result = register_io_dev_block(&mmc_dev_con);
if (io_result != 0) {
panic();
}
io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_boot_part_spec,
&storage_dev_handle);
assert(io_result == 0);
io_result = io_open(storage_dev_handle, (uintptr_t)&emmc_boot_ssbl_block_spec,
&image_dev_handle);
assert(io_result == 0);
io_result = io_read(image_dev_handle, (uintptr_t)&magic, sizeof(magic),
&bytes_read);
assert(io_result == 0);
assert(bytes_read == sizeof(magic));
io_result = io_dev_close(storage_dev_handle);
assert(io_result == 0);
return magic;
}
#endif
static void print_boot_device(boot_api_context_t *boot_context)
{
switch (boot_context->boot_interface_selected) {
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
INFO("Using SDMMC\n");
break;
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
INFO("Using EMMC\n");
break;
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
INFO("Using QSPI NOR\n");
break;
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
INFO("Using FMC NAND\n");
break;
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
INFO("Using SPI NAND\n");
break;
default:
ERROR("Boot interface not found\n");
panic();
break;
}
if (boot_context->boot_interface_instance != 0U) {
INFO(" Instance %d\n", boot_context->boot_interface_instance);
}
}
static void stm32image_io_setup(void)
{
int io_result __unused;
io_result = register_io_dev_stm32image(&stm32image_dev_con);
assert(io_result == 0);
io_result = io_dev_open(stm32image_dev_con,
(uintptr_t)&stm32image_dev_info_spec,
&image_dev_handle);
assert(io_result == 0);
}
#if STM32MP_SDMMC || STM32MP_EMMC
static void boot_mmc(enum mmc_device_type mmc_dev_type,
uint16_t boot_interface_instance)
{
int io_result __unused;
uint8_t idx;
struct stm32image_part_info *part;
struct stm32_sdmmc2_params params;
const partition_entry_t *entry __unused;
uint32_t magic __unused;
zeromem(&params, sizeof(struct stm32_sdmmc2_params));
mmc_info.mmc_dev_type = mmc_dev_type;
switch (boot_interface_instance) {
case 1:
params.reg_base = STM32MP_SDMMC1_BASE;
break;
case 2:
params.reg_base = STM32MP_SDMMC2_BASE;
break;
case 3:
params.reg_base = STM32MP_SDMMC3_BASE;
break;
default:
WARN("SDMMC instance not found, using default\n");
if (mmc_dev_type == MMC_IS_SD) {
params.reg_base = STM32MP_SDMMC1_BASE;
} else {
params.reg_base = STM32MP_SDMMC2_BASE;
}
break;
}
params.device_info = &mmc_info;
if (stm32_sdmmc2_mmc_init(&params) != 0) {
ERROR("SDMMC%u init failed\n", boot_interface_instance);
panic();
}
stm32image_dev_info_spec.device_size =
stm32_sdmmc2_mmc_get_device_size();
#if STM32MP_EMMC_BOOT
if (mmc_dev_type == MMC_IS_EMMC) {
magic = get_boot_part_ssbl_header();
if (magic == BOOT_API_IMAGE_HEADER_MAGIC_NB) {
VERBOSE("%s, header found, jump to emmc load\n", __func__);
idx = IMG_IDX_BL33;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = PLAT_EMMC_BOOT_SSBL_OFFSET;
part->bkp_offset = 0U;
mmc_device_spec.use_boot_part = true;
goto emmc_boot;
} else {
WARN("%s: Can't find STM32 header on a boot partition\n", __func__);
}
}
#endif
/* Open MMC as a block device to read GPT table */
io_result = register_io_dev_block(&mmc_dev_con);
if (io_result != 0) {
panic();
}
io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec,
&storage_dev_handle);
assert(io_result == 0);
partition_init(GPT_IMAGE_ID);
io_result = io_dev_close(storage_dev_handle);
assert(io_result == 0);
for (idx = 0U; idx < IMG_IDX_NUM; idx++) {
part = &stm32image_dev_info_spec.part_info[idx];
entry = get_partition_entry(part->name);
if (entry == NULL) {
ERROR("Partition %s not found\n", part->name);
panic();
}
part->part_offset = entry->start;
part->bkp_offset = 0U;
}
#if STM32MP_EMMC_BOOT
emmc_boot:
#endif
/*
* Re-open MMC with io_mmc, for better perfs compared to
* io_block.
*/
io_result = register_io_dev_mmc(&mmc_dev_con);
assert(io_result == 0);
io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_device_spec,
&storage_dev_handle);
assert(io_result == 0);
}
#endif /* STM32MP_SDMMC || STM32MP_EMMC */
#if STM32MP_SPI_NOR
static void boot_spi_nor(boot_api_context_t *boot_context)
{
int io_result __unused;
uint8_t idx;
struct stm32image_part_info *part;
io_result = stm32_qspi_init();
assert(io_result == 0);
io_result = register_io_dev_mtd(&spi_dev_con);
assert(io_result == 0);
/* Open connections to device */
io_result = io_dev_open(spi_dev_con,
(uintptr_t)&spi_nor_dev_spec,
&storage_dev_handle);
assert(io_result == 0);
stm32image_dev_info_spec.device_size = spi_nor_dev_spec.device_size;
idx = IMG_IDX_BL33;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NOR_BL33_OFFSET;
part->bkp_offset = 0U;
#ifdef AARCH32_SP_OPTEE
idx = IMG_IDX_OPTEE_HEADER;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NOR_TEEH_OFFSET;
part->bkp_offset = 0U;
idx = IMG_IDX_OPTEE_PAGED;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NOR_TEED_OFFSET;
part->bkp_offset = 0U;
idx = IMG_IDX_OPTEE_CORE;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NOR_TEEX_OFFSET;
part->bkp_offset = 0U;
#endif
}
#endif /* STM32MP_SPI_NOR */
#if STM32MP_RAW_NAND
static void boot_fmc2_nand(boot_api_context_t *boot_context)
{
int io_result __unused;
uint8_t idx;
struct stm32image_part_info *part;
io_result = stm32_fmc2_init();
assert(io_result == 0);
/* Register the IO device on this platform */
io_result = register_io_dev_mtd(&nand_dev_con);
assert(io_result == 0);
/* Open connections to device */
io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec,
&storage_dev_handle);
assert(io_result == 0);
stm32image_dev_info_spec.device_size = nand_dev_spec.device_size;
idx = IMG_IDX_BL33;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_BL33_OFFSET;
part->bkp_offset = nand_dev_spec.erase_size;
#ifdef AARCH32_SP_OPTEE
idx = IMG_IDX_OPTEE_HEADER;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEEH_OFFSET;
part->bkp_offset = nand_dev_spec.erase_size;
idx = IMG_IDX_OPTEE_PAGED;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEED_OFFSET;
part->bkp_offset = nand_dev_spec.erase_size;
idx = IMG_IDX_OPTEE_CORE;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEEX_OFFSET;
part->bkp_offset = nand_dev_spec.erase_size;
#endif
}
#endif /* STM32MP_RAW_NAND */
#if STM32MP_SPI_NAND
static void boot_spi_nand(boot_api_context_t *boot_context)
{
int io_result __unused;
uint8_t idx;
struct stm32image_part_info *part;
io_result = stm32_qspi_init();
assert(io_result == 0);
io_result = register_io_dev_mtd(&spi_dev_con);
assert(io_result == 0);
/* Open connections to device */
io_result = io_dev_open(spi_dev_con,
(uintptr_t)&spi_nand_dev_spec,
&storage_dev_handle);
assert(io_result == 0);
stm32image_dev_info_spec.device_size =
spi_nand_dev_spec.device_size;
idx = IMG_IDX_BL33;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_BL33_OFFSET;
part->bkp_offset = spi_nand_dev_spec.erase_size;
#ifdef AARCH32_SP_OPTEE
idx = IMG_IDX_OPTEE_HEADER;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEEH_OFFSET;
part->bkp_offset = spi_nand_dev_spec.erase_size;
idx = IMG_IDX_OPTEE_PAGED;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEED_OFFSET;
part->bkp_offset = spi_nand_dev_spec.erase_size;
idx = IMG_IDX_OPTEE_CORE;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEEX_OFFSET;
part->bkp_offset = spi_nand_dev_spec.erase_size;
#endif
}
#endif /* STM32MP_SPI_NAND */
void stm32mp_io_setup(void)
{
int io_result __unused;
boot_api_context_t *boot_context =
(boot_api_context_t *)stm32mp_get_boot_ctx_address();
print_boot_device(boot_context);
if ((boot_context->boot_partition_used_toboot == 1U) ||
(boot_context->boot_partition_used_toboot == 2U)) {
INFO("Boot used partition fsbl%u\n",
boot_context->boot_partition_used_toboot);
}
#ifndef AARCH32_SP_OPTEE
io_result = register_io_dev_dummy(&dummy_dev_con);
assert(io_result == 0);
io_result = io_dev_open(dummy_dev_con, dummy_dev_spec,
&dummy_dev_handle);
assert(io_result == 0);
#endif
switch (boot_context->boot_interface_selected) {
#if STM32MP_SDMMC
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
dmbsy();
boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance);
stm32image_io_setup();
break;
#endif
#if STM32MP_EMMC
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
dmbsy();
boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance);
stm32image_io_setup();
break;
#endif
#if STM32MP_SPI_NOR
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
dmbsy();
boot_spi_nor(boot_context);
stm32image_io_setup();
break;
#endif
#if STM32MP_RAW_NAND
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
dmbsy();
boot_fmc2_nand(boot_context);
stm32image_io_setup();
break;
#endif
#if STM32MP_SPI_NAND
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
dmbsy();
boot_spi_nand(boot_context);
stm32image_io_setup();
break;
#endif
default:
ERROR("Boot interface %d not supported\n",
boot_context->boot_interface_selected);
panic();
break;
}
}
/*
* Return an IO device handle and specification which can be used to access
* an image. Use this to enforce platform load policy.
*/
int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
uintptr_t *image_spec)
{
int rc;
const struct plat_io_policy *policy;
assert(image_id < ARRAY_SIZE(policies));
policy = &policies[image_id];
rc = policy->check(policy->image_spec);
if (rc == 0) {
*image_spec = policy->image_spec;
*dev_handle = *(policy->dev_handle);
}
return rc;
}

4
plat/st/common/include/stm32mp_common.h
View File

@ -120,10 +120,10 @@ void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance);
/* Functions to save and get boot authentication status and partition used */
void stm32_save_boot_auth(uint32_t auth_status, uint32_t boot_partition);
#if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT
#if PSA_FWU_SUPPORT
void stm32mp1_fwu_set_boot_idx(void);
uint32_t stm32_get_and_dec_fwu_trial_boot_cnt(void);
void stm32_set_max_fwu_trial_boot_cnt(void);
#endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */
#endif /* PSA_FWU_SUPPORT */
#endif /* STM32MP_COMMON_H */

37
plat/st/common/stm32mp_common.c
View File

@ -85,43 +85,6 @@ bool stm32mp_lock_available(void)
return (read_sctlr() & c_m_bits) == c_m_bits;
}
#if STM32MP_USE_STM32IMAGE
int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer)
{
uint32_t i;
uint32_t img_checksum = 0U;
/*
* Check header/payload validity:
* - Header magic
* - Header version
* - Payload checksum
*/
if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) {
ERROR("Header magic\n");
return -EINVAL;
}
if ((header->header_version & HEADER_VERSION_MAJOR_MASK) !=
(BOOT_API_HEADER_VERSION & HEADER_VERSION_MAJOR_MASK)) {
ERROR("Header version\n");
return -EINVAL;
}
for (i = 0U; i < header->image_length; i++) {
img_checksum += *(uint8_t *)(buffer + i);
}
if (header->payload_checksum != img_checksum) {
ERROR("Checksum: 0x%x (awaited: 0x%x)\n", img_checksum,
header->payload_checksum);
return -EINVAL;
}
return 0;
}
#endif /* STM32MP_USE_STM32IMAGE */
int stm32mp_map_ddr_non_cacheable(void)
{
return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,

45
plat/st/stm32mp1/bl2_plat_setup.c
View File

@ -164,14 +164,6 @@ void bl2_platform_setup(void)
ERROR("DDR mapping: error %d\n", ret);
panic();
}
#if STM32MP_USE_STM32IMAGE
#ifdef AARCH32_SP_OPTEE
INFO("BL2 runs OP-TEE setup\n");
#else
INFO("BL2 runs SP_MIN setup\n");
#endif
#endif /* STM32MP_USE_STM32IMAGE */
}
#if STM32MP15
@ -226,19 +218,6 @@ void bl2_el3_plat_arch_setup(void)
BL_CODE_END - BL_CODE_BASE,
MT_CODE | MT_SECURE);
#if STM32MP_USE_STM32IMAGE
#ifdef AARCH32_SP_OPTEE
mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE,
STM32MP_OPTEE_SIZE,
MT_MEMORY | MT_RW | MT_SECURE);
#else
/* Prevent corruption of preloaded BL32 */
mmap_add_region(BL32_BASE, BL32_BASE,
BL32_LIMIT - BL32_BASE,
MT_RO_DATA | MT_SECURE);
#endif
#endif /* STM32MP_USE_STM32IMAGE */
/* Prevent corruption of preloaded Device Tree */
mmap_add_region(DTB_BASE, DTB_BASE,
DTB_LIMIT - DTB_BASE,
@ -396,9 +375,7 @@ skip_console_init:
stm32mp1_syscfg_enable_io_compensation_finish();
#if !STM32MP_USE_STM32IMAGE
fconf_populate("TB_FW", STM32MP_DTB_BASE);
#endif /* !STM32MP_USE_STM32IMAGE */
stm32mp_io_setup();
}
@ -414,7 +391,6 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
bl_mem_params_node_t *bl32_mem_params;
bl_mem_params_node_t *pager_mem_params __unused;
bl_mem_params_node_t *paged_mem_params __unused;
#if !STM32MP_USE_STM32IMAGE
const struct dyn_cfg_dtb_info_t *config_info;
bl_mem_params_node_t *tos_fw_mem_params;
unsigned int i;
@ -426,12 +402,10 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
HW_CONFIG_ID,
TOS_FW_CONFIG_ID,
};
#endif /* !STM32MP_USE_STM32IMAGE */
assert(bl_mem_params != NULL);
switch (image_id) {
#if !STM32MP_USE_STM32IMAGE
case FW_CONFIG_ID:
/* Set global DTB info for fixed fw_config information */
set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE,
@ -494,7 +468,6 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
}
}
break;
#endif /* !STM32MP_USE_STM32IMAGE */
case BL32_IMAGE_ID:
if (optee_header_is_valid(bl_mem_params->image_info.image_base)) {
@ -510,18 +483,6 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
paged_image_info = &paged_mem_params->image_info;
}
#if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE)
/* Set OP-TEE extra image load areas at run-time */
pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE;
pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE;
paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
dt_get_ddr_size() -
STM32MP_DDR_S_SIZE -
STM32MP_DDR_SHMEM_SIZE;
paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE;
#endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */
err = parse_optee_header(&bl_mem_params->ep_info,
&pager_mem_params->image_info,
paged_image_info);
@ -541,13 +502,11 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
bl_mem_params->ep_info.args.arg1 = 0U; /* Unused */
bl_mem_params->ep_info.args.arg2 = 0U; /* No DT supported */
} else {
#if !STM32MP_USE_STM32IMAGE
bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID);
assert(tos_fw_mem_params != NULL);
bl_mem_params->image_info.image_max_size +=
tos_fw_mem_params->image_info.image_max_size;
#endif /* !STM32MP_USE_STM32IMAGE */
bl_mem_params->ep_info.args.arg0 = 0;
}
break;
@ -556,9 +515,9 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
assert(bl32_mem_params != NULL);
bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
#if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT
#if PSA_FWU_SUPPORT
stm32mp1_fwu_set_boot_idx();
#endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */
#endif /* PSA_FWU_SUPPORT */
break;
default:

20
plat/st/stm32mp1/include/platform_def.h
View File

@ -25,26 +25,10 @@
#define PLATFORM_STACK_SIZE 0xC00
#endif
#if STM32MP_USE_STM32IMAGE
#ifdef AARCH32_SP_OPTEE
#define OPTEE_HEADER_IMAGE_NAME "teeh"
#define OPTEE_CORE_IMAGE_NAME "teex"
#define OPTEE_PAGED_IMAGE_NAME "teed"
#define OPTEE_HEADER_BINARY_TYPE U(0x20)
#define OPTEE_CORE_BINARY_TYPE U(0x21)
#define OPTEE_PAGED_BINARY_TYPE U(0x22)
#endif
/* SSBL = second stage boot loader */
#define BL33_IMAGE_NAME "ssbl"
#define BL33_BINARY_TYPE U(0x0)
#else /* STM32MP_USE_STM32IMAGE */
#define FIP_IMAGE_NAME "fip"
#define METADATA_PART_1 "metadata1"
#define METADATA_PART_2 "metadata2"
#endif /* STM32MP_USE_STM32IMAGE */
#define STM32MP_PRIMARY_CPU U(0x0)
#define STM32MP_SECONDARY_CPU U(0x1)
@ -81,7 +65,7 @@
/*******************************************************************************
* BL32 specific defines.
******************************************************************************/
#if STM32MP_USE_STM32IMAGE || defined(IMAGE_BL32)
#if defined(IMAGE_BL32)
#if ENABLE_PIE
#define BL32_BASE 0
#define BL32_LIMIT STM32MP_BL32_SIZE
@ -90,7 +74,7 @@
#define BL32_LIMIT (STM32MP_BL32_BASE + \
STM32MP_BL32_SIZE)
#endif
#endif /* STM32MP_USE_STM32IMAGE || defined(IMAGE_BL32) */
#endif /* defined(IMAGE_BL32) */
/*******************************************************************************
* BL33 specific defines.

4
plat/st/stm32mp1/include/stm32mp1_private.h
View File

@ -34,9 +34,5 @@ static inline void stm32mp1_syscfg_boot_mode_disable(void){}
void stm32mp1_deconfigure_uart_pins(void);
#if STM32MP_USE_STM32IMAGE
uint32_t stm32mp_get_ddr_ns_size(void);
#endif /* STM32MP_USE_STM32IMAGE */
void stm32mp1_init_scmi_server(void);
#endif /* STM32MP1_PRIVATE_H */

103
plat/st/stm32mp1/plat_bl2_stm32_mem_params_desc.c
View File

@ -1,103 +0,0 @@
/*
* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/bl_common.h>
#include <common/desc_image_load.h>
#include <plat/common/platform.h>
#include <platform_def.h>
/*******************************************************************************
* Following descriptor provides BL image/ep information that gets used
* by BL2 to load the images and also subset of this information is
* passed to next BL image. The image loading sequence is managed by
* populating the images in required loading order. The image execution
* sequence is managed by populating the `next_handoff_image_id` with
* the next executable image id.
******************************************************************************/
static bl_mem_params_node_t bl2_mem_params_descs[] = {
/* Fill BL32 related information */
{
.image_id = BL32_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t,
SECURE | EXECUTABLE | EP_FIRST_EXE),
/* Updated at runtime if OP-TEE is loaded */
.ep_info.pc = STM32MP_BL32_BASE,
.ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
SPSR_E_LITTLE,
DISABLE_ALL_EXCEPTIONS),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t,
IMAGE_ATTRIB_PLAT_SETUP),
/* Updated at runtime if OP-TEE is loaded */
.image_info.image_base = STM32MP_BL32_BASE,
.image_info.image_max_size = STM32MP_BL32_SIZE,
.next_handoff_image_id = BL33_IMAGE_ID,
},
#if defined(AARCH32_SP_OPTEE)
/* Fill BL32 external 1 image related information */
{
.image_id = BL32_EXTRA1_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t,
SECURE | NON_EXECUTABLE),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t,
IMAGE_ATTRIB_SKIP_LOADING),
.next_handoff_image_id = INVALID_IMAGE_ID,
},
/* Fill BL32 external 2 image related information */
{
.image_id = BL32_EXTRA2_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t,
SECURE | NON_EXECUTABLE),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t,
IMAGE_ATTRIB_SKIP_LOADING),
.next_handoff_image_id = INVALID_IMAGE_ID,
},
#endif /* AARCH32_SP_OPTEE */
/* Fill BL33 related information */
{
.image_id = BL33_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t,
NON_SECURE | EXECUTABLE),
.ep_info.pc = PLAT_STM32MP_NS_IMAGE_OFFSET,
.ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
SPSR_E_LITTLE,
DISABLE_ALL_EXCEPTIONS),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0U),
.image_info.image_base = PLAT_STM32MP_NS_IMAGE_OFFSET,
.image_info.image_max_size = STM32MP_DDR_MAX_SIZE -
(PLAT_STM32MP_NS_IMAGE_OFFSET - STM32MP_DDR_BASE),
.next_handoff_image_id = INVALID_IMAGE_ID,
}
};
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)

16
plat/st/stm32mp1/plat_image_load.c
View File

@ -4,12 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <common/desc_image_load.h>
#include <plat/common/platform.h>
#include <platform_def.h>
/*******************************************************************************
* This function flushes the data structures so that they are visible
@ -25,17 +20,6 @@ void plat_flush_next_bl_params(void)
******************************************************************************/
bl_load_info_t *plat_get_bl_image_load_info(void)
{
#if STM32MP_USE_STM32IMAGE
bl_mem_params_node_t *bl33 = get_bl_mem_params_node(BL33_IMAGE_ID);
uint32_t ddr_ns_size = stm32mp_get_ddr_ns_size();
assert(bl33 != NULL);
/* Max size is non-secure DDR end address minus image_base */
bl33->image_info.image_max_size = STM32MP_DDR_BASE + ddr_ns_size -
bl33->image_info.image_base;
#endif /* STM32MP_USE_STM32IMAGE */
return get_bl_load_info_from_mem_params_desc();
}

44
plat/st/stm32mp1/platform.mk
View File

@ -13,11 +13,6 @@ STM32MP_EARLY_CONSOLE ?= 0
STM32MP_RECONFIGURE_CONSOLE ?= 0
STM32MP_UART_BAUDRATE ?= 115200
# Allow TF-A to concatenate BL2 & BL32 binaries in a single file,
# share DTB file between BL2 and BL32
# If it is set to 0, then FIP is used
STM32MP_USE_STM32IMAGE ?= 0
TRUSTED_BOARD_BOOT ?= 0
STM32MP_USE_EXTERNAL_HEAP ?= 0
@ -117,7 +112,6 @@ STM32_TF_A_COPIES := 2
PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 4)))
ifeq (${PSA_FWU_SUPPORT},1)
ifneq (${STM32MP_USE_STM32IMAGE},1)
# Number of banks of updatable firmware
NR_OF_FW_BANKS := 2
NR_OF_IMAGES_IN_FW_BANK := 1
@ -127,9 +121,6 @@ ifeq ($(shell test $(FWU_MAX_PART) -gt $(PLAT_PARTITION_MAX_ENTRIES); echo $$?),
$(error "Required partition number is $(FWU_MAX_PART) where PLAT_PARTITION_MAX_ENTRIES is only \
$(PLAT_PARTITION_MAX_ENTRIES)")
endif
else
$(error FWU Feature enabled only with FIP images)
endif
endif
ifeq ($(STM32MP13),1)
@ -160,14 +151,6 @@ ifeq ($(STM32MP13),1)
BL2_DTSI := stm32mp13-bl2.dtsi
FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
else
ifeq ($(STM32MP_USE_STM32IMAGE),1)
ifeq ($(AARCH32_SP),optee)
BL2_DTSI := stm32mp15-bl2.dtsi
FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
else
FDT_SOURCES := $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(DTB_FILE_NAME)))
endif
else
BL2_DTSI := stm32mp15-bl2.dtsi
FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
ifeq ($(AARCH32_SP),sp_min)
@ -175,7 +158,6 @@ BL32_DTSI := stm32mp15-bl32.dtsi
FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl32.dts,$(DTB_FILE_NAME)))
endif
endif
endif
$(eval DTC_V = $(shell $(DTC) -v | awk '{print $$NF}'))
$(eval DTC_VERSION = $(shell printf "%d" $(shell echo ${DTC_V} | cut -d- -f1 | sed "s/\./0/g" | grep -o "[0-9]*")))
@ -202,7 +184,6 @@ STM32IMAGEPATH ?= tools/stm32image
STM32IMAGE ?= ${STM32IMAGEPATH}/stm32image${BIN_EXT}
STM32IMAGE_SRC := ${STM32IMAGEPATH}/stm32image.c
ifneq (${STM32MP_USE_STM32IMAGE},1)
FIP_DEPS += dtbs
STM32MP_HW_CONFIG := ${BL33_CFG}
STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME))
@ -232,7 +213,6 @@ ifneq ($(BL32_EXTRA2),)
$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2,,$(ENCRYPT_BL32)))
endif
endif
endif
# Enable flags for C files
$(eval $(call assert_booleans,\
@ -255,7 +235,6 @@ $(eval $(call assert_booleans,\
STM32MP_UART_PROGRAMMER \
STM32MP_USB_PROGRAMMER \
STM32MP_USE_EXTERNAL_HEAP \
STM32MP_USE_STM32IMAGE \
STM32MP13 \
STM32MP15 \
)))
@ -299,7 +278,6 @@ $(eval $(call add_defines,\
STM32MP_UART_PROGRAMMER \
STM32MP_USB_PROGRAMMER \
STM32MP_USE_EXTERNAL_HEAP \
STM32MP_USE_STM32IMAGE \
STM32MP13 \
STM32MP15 \
)))
@ -308,11 +286,7 @@ $(eval $(call add_defines,\
PLAT_INCLUDES := -Iplat/st/common/include/
PLAT_INCLUDES += -Iplat/st/stm32mp1/include/
ifeq (${STM32MP_USE_STM32IMAGE},1)
include common/fdt_wrappers.mk
else
include lib/fconf/fconf.mk
endif
include lib/libfdt/libfdt.mk
PLAT_BL_COMMON_SOURCES := common/uuid.c \
@ -359,7 +333,6 @@ else
PLAT_BL_COMMON_SOURCES += drivers/st/clk/stm32mp1_clk.c
endif
ifneq (${STM32MP_USE_STM32IMAGE},1)
BL2_SOURCES += ${FCONF_SOURCES} ${FCONF_DYN_SOURCES}
BL2_SOURCES += drivers/io/io_fip.c \
@ -367,15 +340,6 @@ BL2_SOURCES += drivers/io/io_fip.c \
plat/st/common/stm32mp_fconf_io.c \
plat/st/stm32mp1/plat_bl2_mem_params_desc.c \
plat/st/stm32mp1/stm32mp1_fconf_firewall.c
else
BL2_SOURCES += ${FDT_WRAPPERS_SOURCES}
BL2_SOURCES += drivers/io/io_dummy.c \
drivers/st/io/io_stm32image.c \
plat/st/common/bl2_stm32_io_storage.c \
plat/st/stm32mp1/plat_bl2_stm32_mem_params_desc.c \
plat/st/stm32mp1/stm32mp1_security.c
endif
include lib/zlib/zlib.mk
@ -541,13 +505,6 @@ check_dtc_version:
false; \
fi
ifeq ($(STM32MP_USE_STM32IMAGE)-$(AARCH32_SP),1-sp_min)
${BUILD_PLAT}/stm32mp1-%.o: ${BUILD_PLAT}/fdts/%.dtb plat/st/stm32mp1/stm32mp1.S bl2 ${BL32_DEP}
@echo " AS stm32mp1.S"
${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} \
-DDTB_BIN_PATH=\"$<\" \
-c $(word 2,$^) -o $@
else
# Create DTB file for BL2
${BUILD_PLAT}/fdts/%-bl2.dts: fdts/%.dts fdts/${BL2_DTSI} | ${BUILD_PLAT} fdt_dirs
@echo '#include "$(patsubst fdts/%,%,$<)"' > $@
@ -569,7 +526,6 @@ ${BUILD_PLAT}/stm32mp1-%.o: ${BUILD_PLAT}/fdts/%-bl2.dtb plat/st/stm32mp1/stm32m
${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} \
-DDTB_BIN_PATH=\"$<\" \
-c plat/st/stm32mp1/stm32mp1.S -o $@
endif
$(eval $(call MAKE_LD,${STM32_TF_LINKERFILE},plat/st/stm32mp1/stm32mp1.ld.S,bl2))

2
plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
View File

@ -10,11 +10,9 @@ endif
SP_MIN_WITH_SECURE_FIQ := 1
ifneq ($(STM32MP_USE_STM32IMAGE),1)
override ENABLE_PIE := 1
BL32_CFLAGS += -fpie -DENABLE_PIE
BL32_LDFLAGS += $(PIE_LDFLAGS)
endif
BL32_CFLAGS += -DSTM32MP_SHARED_RESOURCES

4
plat/st/stm32mp1/sp_min/sp_min_setup.c
View File

@ -115,11 +115,7 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
#if STM32MP_USE_STM32IMAGE
uintptr_t dt_addr = STM32MP_DTB_BASE;
#else
uintptr_t dt_addr = arg1;
#endif
stm32mp_setup_early_console();

9
plat/st/stm32mp1/stm32mp1.S
View File

@ -1,16 +1,9 @@
/*
* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#if STM32MP_USE_STM32IMAGE
#ifdef BL32_BIN_PATH
.section .bl32_image
.incbin BL32_BIN_PATH
#endif
#endif /* STM32MP_USE_STM32IMAGE */
.section .bl2_image
.incbin BL2_BIN_PATH

16
plat/st/stm32mp1/stm32mp1.ld.S
View File

@ -43,11 +43,7 @@ SECTIONS
* The strongest and only alignment contraint is MMU 4K page.
* Indeed as images below will be removed, 4K pages will be re-used.
*/
#if STM32MP_USE_STM32IMAGE
. = ( STM32MP_DTB_BASE - STM32MP_BINARY_BASE );
#else
. = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE );
#endif /* STM32MP_USE_STM32IMAGE */
__DTB_IMAGE_START__ = .;
*(.dtb_image*)
__DTB_IMAGE_END__ = .;
@ -66,18 +62,6 @@ SECTIONS
*(.bl2_image*)
__BL2_IMAGE_END__ = .;
#if STM32MP_USE_STM32IMAGE && !defined(AARCH32_SP_OPTEE)
/*
* bl32 will be settled by bl2.
* The strongest and only alignment constraint is 8 words to simplify
* memraise8 assembly code.
*/
. = ( STM32MP_BL32_BASE - STM32MP_BINARY_BASE );
__BL32_IMAGE_START__ = .;
*(.bl32_image*)
__BL32_IMAGE_END__ = .;
#endif /* STM32MP_USE_STM32IMAGE && !defined(AARCH32_SP_OPTEE) */
__DATA_END__ = .;
} >RAM

4
plat/st/stm32mp1/stm32mp1_def.h
View File

@ -26,11 +26,7 @@
#include <stm32mp1_shared_resources.h>
#endif
#if !STM32MP_USE_STM32IMAGE
#include "stm32mp1_fip_def.h"
#else /* STM32MP_USE_STM32IMAGE */
#include "stm32mp1_stm32image_def.h"
#endif /* STM32MP_USE_STM32IMAGE */
/*******************************************************************************
* CHIP ID

27
plat/st/stm32mp1/stm32mp1_private.c
View File

@ -697,29 +697,6 @@ uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags)
}
#endif
#if STM32MP_USE_STM32IMAGE
/* Get the non-secure DDR size */
uint32_t stm32mp_get_ddr_ns_size(void)
{
static uint32_t ddr_ns_size;
uint32_t ddr_size;
if (ddr_ns_size != 0U) {
return ddr_ns_size;
}
ddr_size = dt_get_ddr_size();
if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) ||
(ddr_size > STM32MP_DDR_MAX_SIZE)) {
panic();
}
ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE);
return ddr_ns_size;
}
#endif /* STM32MP_USE_STM32IMAGE */
void stm32_save_boot_interface(uint32_t interface, uint32_t instance)
{
uintptr_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
@ -767,7 +744,7 @@ void stm32_save_boot_auth(uint32_t auth_status, uint32_t boot_partition)
clk_disable(RTCAPB);
}
#if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT
#if PSA_FWU_SUPPORT
void stm32mp1_fwu_set_boot_idx(void)
{
clk_enable(RTCAPB);
@ -808,4 +785,4 @@ void stm32_set_max_fwu_trial_boot_cnt(void)
TAMP_BOOT_FWU_INFO_CNT_MSK);
clk_disable(RTCAPB);
}
#endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */
#endif /* PSA_FWU_SUPPORT */

136
plat/st/stm32mp1/stm32mp1_security.c
View File

@ -1,136 +0,0 @@
/*
* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#include <platform_def.h>
#include <common/debug.h>
#include <drivers/arm/tzc400.h>
#include <drivers/clk.h>
#include <drivers/st/stm32mp1_clk.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/soc/stm32mp15-tzc400.h>
#include <lib/mmio.h>
static unsigned int region_nb;
static void init_tzc400_begin(unsigned int region0_attr)
{
tzc400_init(STM32MP1_TZC_BASE);
tzc400_disable_filters();
/* Region 0 set to cover all DRAM at 0xC000_0000 */
tzc400_configure_region0(region0_attr, 0);
region_nb = 1U;
}
static void init_tzc400_end(unsigned int action)
{
tzc400_set_action(action);
tzc400_enable_filters();
}
static void tzc400_add_region(unsigned long long region_base,
unsigned long long region_top, bool sec)
{
unsigned int sec_attr;
unsigned int nsaid_permissions;
if (sec) {
sec_attr = TZC_REGION_S_RDWR;
nsaid_permissions = 0;
} else {
sec_attr = TZC_REGION_S_NONE;
nsaid_permissions = TZC_REGION_NSEC_ALL_ACCESS_RDWR;
}
tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, region_nb, region_base,
region_top, sec_attr, nsaid_permissions);
region_nb++;
}
/*******************************************************************************
* Initialize the TrustZone Controller. Configure Region 0 with Secure RW access
* and allow Non-Secure masters full access.
******************************************************************************/
static void init_tzc400(void)
{
unsigned long long region_base, region_top;
unsigned long long ddr_base = STM32MP_DDR_BASE;
unsigned long long ddr_ns_size =
(unsigned long long)stm32mp_get_ddr_ns_size();
unsigned long long ddr_ns_top = ddr_base + (ddr_ns_size - 1U);
unsigned long long ddr_top __unused;
init_tzc400_begin(TZC_REGION_S_NONE);
/*
* Region 1 set to cover all non-secure DRAM at 0xC000_0000. Apply the
* same configuration to all filters in the TZC.
*/
region_base = ddr_base;
region_top = ddr_ns_top;
tzc400_add_region(region_base, region_top, false);
#ifdef AARCH32_SP_OPTEE
/* Region 2 set to cover all secure DRAM. */
region_base = region_top + 1U;
region_top += STM32MP_DDR_S_SIZE;
tzc400_add_region(region_base, region_top, true);
ddr_top = STM32MP_DDR_BASE + dt_get_ddr_size() - 1U;
if (region_top < ddr_top) {
/* Region 3 set to cover non-secure memory DRAM after BL32. */
region_base = region_top + 1U;
region_top = ddr_top;
tzc400_add_region(region_base, region_top, false);
}
#endif
/*
* Raise an interrupt (secure FIQ) if a NS device tries to access
* secure memory
*/
init_tzc400_end(TZC_ACTION_INT);
}
/*******************************************************************************
* Initialize the TrustZone Controller.
* Early initialization create only one region with full access to secure.
* This setting is used before and during DDR initialization.
******************************************************************************/
static void early_init_tzc400(void)
{
clk_enable(TZC1);
clk_enable(TZC2);
/* Region 0 set to cover all DRAM secure at 0xC000_0000 */
init_tzc400_begin(TZC_REGION_S_RDWR);
/* Raise an exception if a NS device tries to access secure memory */
init_tzc400_end(TZC_ACTION_ERR);
}
/*******************************************************************************
* Initialize the secure environment. At this moment only the TrustZone
* Controller is initialized.
******************************************************************************/
void stm32mp1_arch_security_setup(void)
{
early_init_tzc400();
}
/*******************************************************************************
* Initialize the secure environment. At this moment only the TrustZone
* Controller is initialized.
******************************************************************************/
void stm32mp1_security_setup(void)
{
init_tzc400();
}

78
plat/st/stm32mp1/stm32mp1_stm32image_def.h
View File

@ -1,78 +0,0 @@
/*
* Copyright (C) 2021-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP1_STM32IMAGE_DEF_H
#define STM32MP1_STM32IMAGE_DEF_H
#ifdef AARCH32_SP_OPTEE
#if STM32MP15_OPTEE_RSV_SHM
#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
#else
#define STM32MP_DDR_S_SIZE U(0x02000000) /* 32 MB */
#define STM32MP_DDR_SHMEM_SIZE U(0) /* empty */
#endif
#else
#define STM32MP_DDR_S_SIZE U(0)
#define STM32MP_DDR_SHMEM_SIZE U(0)
#endif
#define STM32MP_BL2_SIZE U(0x0001C000) /* 112 KB for BL2 */
#define STM32MP_DTB_SIZE U(0x00006000) /* 24 KB for DTB */
#ifdef AARCH32_SP_OPTEE
#define STM32MP_BL32_BASE STM32MP_SEC_SYSRAM_BASE
#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
STM32MP_SEC_SYSRAM_SIZE - \
STM32MP_BL2_SIZE)
/* OP-TEE loads from SYSRAM base to BL2 DTB start address */
#define STM32MP_OPTEE_BASE STM32MP_BL32_BASE
#define STM32MP_OPTEE_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
STM32MP_BL2_SIZE - STM32MP_DTB_SIZE)
#define STM32MP_BL32_SIZE STM32MP_OPTEE_SIZE
#else /* AARCH32_SP_OPTEE */
#define STM32MP_BL32_SIZE U(0x00019000) /* 96 KB for BL32 */
#define STM32MP_BL32_BASE (STM32MP_SEC_SYSRAM_BASE + \
STM32MP_SEC_SYSRAM_SIZE - \
STM32MP_BL32_SIZE)
#define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \
STM32MP_BL2_SIZE)
#endif /* AARCH32_SP_OPTEE */
/* DTB initialization value */
#define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \
STM32MP_DTB_SIZE)
/*
* MAX_MMAP_REGIONS is usually:
* BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
*/
#if defined(IMAGE_BL32)
#define MAX_MMAP_REGIONS 6
#endif
/*******************************************************************************
* STM32MP1 RAW partition offset for MTD devices
******************************************************************************/
#define STM32MP_NOR_BL33_OFFSET U(0x00080000)
#ifdef AARCH32_SP_OPTEE
#define STM32MP_NOR_TEEH_OFFSET U(0x00280000)
#define STM32MP_NOR_TEED_OFFSET U(0x002C0000)
#define STM32MP_NOR_TEEX_OFFSET U(0x00300000)
#endif
#define STM32MP_NAND_BL33_OFFSET U(0x00200000)
#ifdef AARCH32_SP_OPTEE
#define STM32MP_NAND_TEEH_OFFSET U(0x00600000)
#define STM32MP_NAND_TEED_OFFSET U(0x00680000)
#define STM32MP_NAND_TEEX_OFFSET U(0x00700000)
#endif
#endif /* STM32MP1_STM32IMAGE_DEF_H */