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amd_blobs/picasso: Add items from PI 1.0.0.6 

Add add VGA BIOS, PSP bootloaders, AGESA bootloaders, keys, SMU
firmware and other items.  Release notes, where provided, are
added in the directory structure.

Change-Id: I1c9253253e4b6bcc4718e02979d69aafa32d01c9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Marshall Dawson 2019-10-28 11:59:16 -06:00
parent 15d54b63eb
commit fc99df6f69
58 changed files with 8315 additions and 0 deletions
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picasso/PSP/AblPostCode.h.txt Normal file
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/* $NoKeywords:$ */
/**
* @file
*
* AblPostCode.h
*
* Contains definition needed for ABL Post Codes
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: PSP
* @e \$Revision: 83676 $ @e \$Date: 2012-12-07 15:57:01 -0600 (Fri, 07 Dec 2012) $
*
*/
/*****************************************************************************
*
* Copyright 2008 - 2018 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
*
* AMD is granting you permission to use this software and documentation (if
* any) (collectively, the "Materials") pursuant to the terms and conditions of
* the Software License Agreement included with the Materials. If you do not
* have a copy of the Software License Agreement, contact your AMD
* representative for a copy.
*
* You agree that you will not reverse engineer or decompile the Materials, in
* whole or in part, except as allowed by applicable law.
*
* WARRANTY DISCLAIMER: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF
* ANY KIND. AMD DISCLAIMS ALL WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY,
* INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE, NON-INFRINGEMENT, THAT THE
* MATERIALS WILL RUN UNINTERRUPTED OR ERROR-FREE OR WARRANTIES ARISING FROM
* CUSTOM OF TRADE OR COURSE OF USAGE. THE ENTIRE RISK ASSOCIATED WITH THE USE
* OF THE MATERIAL IS ASSUMED BY YOU. Some jurisdictions do not allow the
* exclusion of implied warranties, so the above exclusion may not apply to
* You.
*
* LIMITATION OF LIABILITY AND INDEMNIFICATION: AMD AND ITS LICENSORS WILL
* NOT, UNDER ANY CIRCUMSTANCES BE LIABLE TO YOU FOR ANY PUNITIVE, DIRECT,
* INCIDENTAL, INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES ARISING FROM USE OF
* THE MATERIALS OR THIS AGREEMENT EVEN IF AMD AND ITS LICENSORS HAVE BEEN
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. In no event shall AMD's total
* liability to You for all damages, losses, and causes of action (whether in
* contract, tort (including negligence) or otherwise) exceed the amount of
* $100 USD. You agree to defend, indemnify and hold harmless AMD and its
* licensors, and any of their directors, officers, employees, affiliates or
* agents from and against any and all loss, damage, liability and other
* expenses (including reasonable attorneys' fees), resulting from Your use of
* the Materials or violation of the terms and conditions of this Agreement.
*
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
* subject to the restrictions as set forth in FAR 52.227-14 and
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
* Government constitutes acknowledgment of AMD's proprietary rights in them.
*
* EXPORT RESTRICTIONS: The Materials may be subject to export restrictions as
* stated in the Software License Agreement.
*******************************************************************************
*/
#ifndef _ABLPOSTCODE_H_
#define _ABLPOSTCODE_H_
/// <PostCodePrefix> 0xEA000000
/**
* AGESA ABL Test Points
*
* These are the values displayed to the user to indicate progress through boot.
*
*/
typedef enum {
StartProcessorTestPoints = 0xE000, ///< Entry used for range testing for @b Processor related TPs
// Memory test points
TpProcMemBeforeMemDataInit = 0xE001, ///< Memory structure initialization (Public interface)
TpProcMemBeforeSpdProcessing = 0xE002, ///< SPD Data processing (Public interface)
TpProcMemAmdMemAutoPhase1 = 0xE003, ///< Memory configuration (Public interface) Phase 1
TpProcMemDramInit = 0xE004, ///< DRAM initialization
TpProcMemSPDChecking = 0xE005, ///< ProcMemSPDChecking
TpProcMemModeChecking = 0xE006, ///< ProcMemModeChecking
TpProcMemSpeedTclConfig = 0xE007, ///< Speed and TCL configuration
TpProcMemSpdTiming = 0xE008, ///< ProcMemSpdTiming
TpProcMemDramMapping = 0xE009, ///< ProcMemDramMapping
TpProcMemPlatformSpecificConfig = 0xE00A, ///< ProcMemPlatformSpecificConfig
TPProcMemPhyCompensation = 0xE00B, ///< ProcMemPhyCompensation
TpProcMemStartDcts = 0xE00C, ///< ProcMemStartDcts
TpProcMemBeforeDramInit = 0xE00D, ///< ProcMemBeforeDramInit (Public interface)
TpProcMemPhyFenceTraining = 0xE00E, ///< ProcMemPhyFenceTraining
TpProcMemSynchronizeDcts = 0xE00F, ///< ProcMemSynchronizeDcts
TpProcMemSystemMemoryMapping = 0xE010, ///< ProcMemSystemMemoryMapping
TpProcMemMtrrConfiguration = 0xE011, ///< ProcMemMtrrConfiguration
TpProcMemDramTraining = 0xE012, ///< ProcMemDramTraining
TpProcMemBeforeAnyTraining = 0xE013, ///< ProcMemBeforeAnyTraining(Public interface)
// PMU Test Points
TpProcMemPmuBeforeFirmwareLoad = 0xE014, ///< ABL Mem - PMU - Before PMU Firmware load
TpProcMemPmuAfterFirmwareLoad = 0xE015, ///< ABL Mem - PMU - After PMU Firmware load
TpProcMemPmuPopulateSramTimings = 0xE016, ///< ABL Mem - PMU Populate SRAM Timing
TpProcMemPmuPopulateSramConfig = 0xE017, ///< ABL Mem - PMU Populate SRAM Config
TpProcMemPmuWriteSramMsgBlock = 0xE018, ///< ABL Mem - PMU Write SRAM Msg Block
TpProcMemPmuWaitForPhyCalComplete = 0xE019, ///< ABL Mem - Wait for Phy Cal Complete
TpProcMemPmuPhyCalComplete = 0xE01A, ///< ABL Mem - Phy Cal Complete
TpProcMemPmuStart = 0xE01B, ///< ABL Mem - PMU Start
TpProcMemPmuStarted = 0xE01C, ///< ABL Mem - PMU Started
TpProcMemPmuWaitingForComplete = 0xE01D, ///< ABL Mem - PMU Waiting for Complete
TpProcMemPmuStageDevInit = 0xE01E, ///< ABL Mem - PMU Stage Dec Init
TpProcMemPmuStageTrainWrLvl = 0xE01F, ///< ABL Mem - PMU Stage Training Wr Lvl
TpProcMemPmuStageTrainRxEn = 0xE020, ///< ABL Mem - PMU Stage Training Rx En
TpProcMemPmuStageTrainRdDqs1D = 0xE021, ///< ABL Mem - PMU Stage Training Rd Dqs
TpProcMemPmuStageTrainRd2D = 0xE022, ///< ABL Mem - PMU Stage Traning Rd 2D
TpProcMemPmuStageTrainWr2D = 0xE023, ///< ABL Mem - PMU Stage Training Wr 2D
TpProcMemPmuStagePMUQEmpty = 0xE024, ///< ABL Mem - PMU Queue Empty
TpProcMemPmuUSMsgStart = 0xE025, ///< ABL Mem - PMU US message Start
TpProcMemPmuUSMsgEnd = 0xE026, ///< ABL Mem - PMU US message End
TpProcMemPmuComplete = 0xE027, ///< ABL Mem - PMU Complete
TpProcMemAfterPmuTraining = 0xE028, ///< ABL Mem - PMU - After PMU Training
TpProcMemBeforeDisablePmu = 0xE029, ///< ABL Mem - PMU - Before Disable PMU
//Original Post code
TpProcMemTransmitDqsTraining = 0xE02A, ///< ABL Mem - ProcMemTransmitDqsTraining
TpProcMemTxDqStartSweep = 0xE02B, ///< ABL Mem - Start write sweep
TpProcMemTxDqSetDelay = 0xE02C, ///< ABL Mem - Set Transmit DQ delay
TpProcMemTxDqWritePattern = 0xE02D, ///< ABL Mem - Write test pattern
TpProcMemTxDqReadPattern = 0xE02E, ///< ABL Mem - Read Test pattern
TpProcMemTxDqTestPattern = 0xE02F, ///< ABL Mem - Compare Test pattern
TpProcMemTxDqResults = 0xE030, ///< ABL Mem - Update results
TpProcMemTxDqFindWindow = 0xE031, ///< ABL Mem - Start Find passing window
TpProcMemMaxRdLatencyTraining = 0xE032, ///< ABL Mem - ProcMemMaxRdLatencyTraining
TpProcMemMaxRdLatStartSweep = 0xE033, ///< ABL Mem - Start sweep
TpProcMemMaxRdLatSetDelay = 0xE034, ///< ABL Mem - Set delay
TpProcMemMaxRdLatWritePattern = 0xE035, ///< ABL Mem - Write test pattern
TpProcMemMaxRdLatReadPattern = 0xE036, ///< ABL Mem - Read Test pattern
TpProcMemMaxRdLatTestPattern = 0xE037, ///< ABL Mem - Compare Test pattern
TpProcMemOnlineSpareInit = 0xE038, ///< ABL Mem - Online Spare init
TpProcMemBankInterleaveInit = 0xE039, ///< ABL Mem - Bank Interleave Init
TpProcMemNodeInterleaveInit = 0xE03A, ///< ABL Mem - Node Interleave Init
TpProcMemChannelInterleaveInit = 0xE03B, ///< ABL Mem - Channel Interleave Init
TpProcMemEccInitialization = 0xE03C, ///< ABL Mem - ECC initialization
TpProcMemPlatformSpecificInit = 0xE03D, ///< ABL Mem - Platform Specific Init
TpProcMemBeforeAgesaReadSpd = 0xE03E, ///< ABL Mem - Before callout for "AgesaReadSpd"
TpProcMemAfterAgesaReadSpd = 0xE03F, ///< ABL Mem - After callout for "AgesaReadSpd"
TpProcMemBeforeAgesaHookBeforeDramInit = 0xE040, ///< ABL Mem - Before optional callout "AgesaHookBeforeDramInit"
TpProcMemAfterAgesaHookBeforeDramInit = 0xE041, ///< ABL Mem - After optional callout "AgesaHookBeforeDramInit"
TpProcMemBeforeAgesaHookBeforeDQSTraining = 0xE042, ///< ABL Mem - Before optional callout "AgesaHookBeforeDQSTraining"
TpProcMemAfterAgesaHookBeforeDQSTraining = 0xE043, ///< ABL Mem - After optional callout "AgesaHookBeforeDQSTraining"
TpProcMemBeforeAgesaHookBeforeExitSelfRef = 0xE044, ///< ABL Mem - Before optional callout "AgesaHookBeforeDramInit"
TpProcMemAfterAgesaHookBeforeExitSelfRef = 0xE045, ///< ABL Mem - After optional callout "AgesaHookBeforeDramInit"
TpProcMemAfterMemDataInit = 0xE046, ///< ABL Mem - After MemDataInit
TpProcMemInitializeMCT = 0xE047, ///< ABL Mem - Before InitializeMCT
TpProcMemLvDdr3 = 0xE048, ///< ABL Mem - Before LV DDR3
TpProcMemInitMCT = 0xE049, ///< ABL Mem - Before InitMCT
TpProcMemOtherTiming = 0xE04A, ///< ABL Mem - Before OtherTiming
TpProcMemUMAMemTyping = 0xE04B, ///< ABL Mem - Before UMAMemTyping
TpProcMemSetDqsEccTmgs = 0xE04C, ///< ABL Mem - Before SetDqsEccTmgs
TpProcMemMemClr = 0xE04D, ///< ABL Mem - Before MemClr
TpProcMemOnDimmThermal = 0xE04E, ///< ABL Mem - Before On DIMM Thermal
TpProcMemDmi = 0xE04F, ///< ABL Mem - Before DMI
TpProcMemEnd = 0xE050, ///< ABL MEM - End of phase 3 memory code
// CPU test points
TpProcCpuInitAfterTrainingStart = 0xE051, ///< Entry point CPU init after training
TpProcCpuInitAfterTrainingEnd = 0xE052, ///< Exit point CPU init after training
TpProcCpuApobCcxMapInitStart = 0xE053, ///< Entry point CPU APOB CCX map init
TpProcCpuApobCcxMapInitEnd = 0xE054, ///< Exit point CPU APOB CCX map init
TpProcCpuOptimizedBootStart = 0xE055, ///< Entry point CPU Optimized boot init
TpProcCpuOptimizedBootEnd = 0xE056, ///< Exit point CPU Optimized boot init
TpProcCpuApobCcxEdcInitStart = 0xE057, ///< Entry point CPU APOB EDC info init
TpProcCpuApobCcxEdcInitEnd = 0xE058, ///< Exit point CPU APOB EDC info init
// Topology test points
TpProcTopologyEntry = 0xE071, ///< ProcTopologyEntry
TpProcTopologyDone = 0xE07C, ///< ProcTopologyDone
// Extended memory test point
TpProcMemSendMRS2 = 0xE080, ///< ProcMemSendMRS2
TpProcMemSendMRS3 = 0xE081, ///< Sedding MRS3
TpProcMemSendMRS1 = 0xE082, ///< Sending MRS1
TpProcMemSendMRS0 = 0xE083, ///< Sending MRS0
TpProcMemContinPatternGenRead = 0xE084, ///< Continuous Pattern Read
TpProcMemContinPatternGenWrite = 0xE085, ///< Continuous Pattern Write
TpProcMem2dRdDqsTraining = 0xE086, ///< Mem: 2d RdDqs Training begin
TpProcMemBefore2dTrainExtVrefChange = 0xE087, ///< Mem: Before optional callout to platform BIOS to change External Vref during 2d Training
TpProcMemAfter2dTrainExtVrefChange = 0xE088, ///< Mem: After optional callout to platform BIOS to change External Vref during 2d Training
TpProcMemConfigureDCTForGeneral = 0xE089, ///< Configure DCT For General use begin
TpProcMemProcConfigureDCTForTraining = 0xE08A, ///< Configure DCT For training begin
TpProcMemConfigureDCTNonExplicitSeq = 0xE08B, ///< Configure DCT For Non-Explicit
TpProcMemSynchronizeChannels = 0xE08C, ///< Configure to Sync channels
TpProcMemC6StorageAllocation = 0xE08D, ///< Allocate C6 Storage
TpProcMemLvDdr4 = 0xE08E, ///< Before LV DDR4
TpProcMemLvLpddr3 = 0xE08F, ///< Before LV DDR3
// Gnb Earlier init
TP0x90 = 0xE090, ///< TP0x90
TP0x91 = 0xE091, ///< GNB earlier interface
TP0x92 = 0xE092, ///< GNB internal debug code
TP0x93 = 0xE093, ///< GNB internal debug code
TP0x94 = 0xE094, ///< GNB internal debug code
TP0x95 = 0xE095, ///< GNB internal debug code
TP0x96 = 0xE096, ///< GNB internal debug code
TP0x97 = 0xE097, ///< GNB internal debug code
TP0x98 = 0xE098, ///< GNB internal debug code
TP0x99 = 0xE099, ///< GNB internal debug code
TP0x9A = 0xE09A, ///< GNB internal debug code
TP0x9B = 0xE09B, ///< GNB internal debug code
TP0x9C = 0xE09C, ///< GNB internal debug code
TP0x9D = 0xE09D, ///< GNB internal debug code
TP0x9E = 0xE09E, ///< GNB internal debug code
TP0x9F = 0xE09F, ///< GNB internal debug code
TP0xA0 = 0xE0A0, ///< TP0xA0
TP0xA1 = 0xE0A1, ///< GNB internal debug code
TP0xA2 = 0xE0A2, ///< GNB internal debug code
TP0xA3 = 0xE0A3, ///< GNB internal debug code
TP0xA4 = 0xE0A4, ///< GNB internal debug code
TP0xA5 = 0xE0A5, ///< GNB internal debug code
TP0xA6 = 0xE0A6, ///< GNB internal debug code
TP0xA7 = 0xE0A7, ///< GNB internal debug code
TP0xA8 = 0xE0A8, ///< GNB internal debug code
TP0xA9 = 0xE0A9, ///< GNB internal debug code
TP0xAA = 0xE0AA, ///< GNB internal debug code
TP0xAB = 0xE0AB, ///< GNB internal debug code
TP0xAC = 0xE0AC, ///< GNB internal debug code
TP0xAD = 0xE0AD, ///< GNB internal debug code
TP0xAE = 0xE0AE, ///< GNB internal debug code
TP0xAF = 0xE0AF, ///< GNB internal debug code
TpAbl1Begin = 0xE0B0, ///< Abl1Begin
TpAbl1Initialization = 0xE0B1, ///< ABL 1 Initialization
TpAbl1DfEarly = 0xE0B2, ///< ABL 1 DF Early
TpAbl1DfPreTraining = 0xE0B3, ///< ABL 1 DF Pre Training
TpAbl1DebugSync = 0xE0B4, ///< ABL 1 Debug Synchronization
TpAbl1ErrorDetected = 0xE0B5, ///< ABL 1 Error Detected
TpAbl1GlobalMemErrorDetected = 0xE0B6, ///< ABL 1 Global memory error detected
TpAbl1End = 0xE0B7, ///< ABL 1 End
TpAbl2Begin = 0xE0B8, ///< ABL 2 Begin
TpAbl2Initialization = 0xE0B9, ///< ABL 2 Initialization
TpAbl2DfAfterTraining = 0xE0BA, ///< ABL 2 After Training
TpAbl2DebugSync = 0xE0BB, ///< ABL 2 Debug Synchronization
TpAbl2ErrorDetected = 0xE0BC, ///< ABL 2 Error detected
TpAbl2GlobalMemErrorDetected = 0xE0BD, ///< ABL 2 Global memory error detected
TpAbl2End = 0xE0BE, ///< ABL 2 End
TpAbl3Begin = 0xE0BF, ///< ABL 3 Begin
TpAbl3Initialization = 0xE0C0, ///< ABL 3 Initialziation
TpAbl3GmiGopInitStage1 = 0xE1C0, ///< ABL 3 GMI/xGMI Initialization Stage 1
TpAbl3GmiGopInitStage1Warning = 0xB1C0, ///< ABL 3 GMI/xGMI Initialization Stage 1 Warning
TpAbl3GmiGopInitState1Error = 0xF1C0, ///< ABL 3 GMI/xGMI Initialization Stage 2 Error
TpAbl3GmiGopInitStage2 = 0xE2C0, ///< ABL 3 GMI/xGMI Initialization Stage 2
TpAbl3GmiGopInitStage2Warning = 0xB2C0, ///< ABL 3 GMI/xGMI Initialization Stage 2 Warning
TpAbl3GmiGopInitState2Error = 0xF2C0, ///< ABL 3 GMI/xGMI Initialization Stage 2 Error
TpAbl3GmiGopInitStage3 = 0xE3C0, ///< ABL 3 GMI/xGMI Initialization Stage 3
TpAbl3GmiGopInitStage3Warning = 0xB3C0, ///< ABL 3 GMI/xGMI Initialization Stage 3 Warning
TpAbl3GmiGopInitState3Error = 0xF3C0, ///< ABL 3 GMI/xGMI Initialization Stage 3 Error
TpAbl3GmiGopInitStage4 = 0xE4C0, ///< ABL 3 GMI/xGMI Initialization Stage 4
TpAbl3GmiGopInitStage4Warning = 0xB4C0, ///< ABL 3 GMI/xGMI Initialization Stage 4 Warning
TpAbl3GmiGopInitState4Error = 0xF4C0, ///< ABL 3 GMI/xGMI Initialization Stage 4 Error
TpAbl3GmiGopInitStage5 = 0xE5C0, ///< ABL 3 GMI/xGMI Initialization Stage 5
TpAbl3GmiGopInitStage5Warning = 0xB5C0, ///< ABL 3 GMI/xGMI Initialization Stage 5 Warning
TpAbl3GmiGopInitState5Error = 0xF5C0, ///< ABL 3 GMI/xGMI Initialization Stage 5 Error
TpAbl3GmiGopInitStage6 = 0xE6C0, ///< ABL 3 GMI/xGMI Initialization Stage 6
TpAbl3GmiGopInitStage6Warning = 0xB6C0, ///< ABL 3 GMI/xGMI Initialization Stage 6 Warning
TpAbl3GmiGopInitState6Error = 0xF6C0, ///< ABL 3 GMI/xGMI Initialization Stage 6 Error
TpAbl3GmiGopInitStage7 = 0xE7C0, ///< ABL 3 GMI/xGMI Initialization Stage 7
TpAbl3GmiGopInitStage8 = 0xE8C0, ///< ABL 3 GMI/xGMI Initialization Stage 8
TpAbl3ProgramUmcKeys = 0xE0C1, ///< Abl3ProgramUmcKeys
TpAbl3DfFinalInitialization = 0xE0C2, ///< ABL 3 DF Finial Initalization
TpAbl3ExecuteSyncFunction = 0xE0C3, ///< ABL 3 Execute Synchronization Function
TpAbl3DebugSync = 0xE0C4, ///< ABL 3 Debug Synchronization Function
TpAbl3ErrorDetected = 0xE0C5, ///< ABL 3 Error Detected
TpAbl3GlobalMemErrorDetected = 0xE0C6, ///< ABL 3 Global memroy error detected
TpAbl4ColdInitialization = 0xE0C7, ///< ABL 4 Initialiation - cold boot
TpAbl4MemTest = 0xE0C8, ///< ABL 4 Memory test - cold boot
TpAbl4Apob = 0xE0C9, ///< ABL 4 APOB Initialzation - cold boot
TpAbl4Finalize = 0xE0CA, ///< ABL 4 Finalize memory settings - cold boot
TpAbl4CpuInizialOptimizedBoot = 0xE0CB, ///< ABL 4 CPU Initialize Optimized Boot - cold boot
TpAbl4GmicieTraining = 0xE0CC, ///< ABL 4 Gmi Pcie Training - cold boot
TpAbl4ColdEnd = 0xE0CD, ///< ABL 4 Cold boot End
TpAbl4ResumeInitialization = 0xE0CE, ///< ABL 4 Initialization - Resume boot
TpAbl4ResumeEnd = 0xE0CF, ///< ABL 4 Resume End
TpAbl4End = 0xE0D0, ///< ABL 4 End Cold/Resume boot
TpProcMemAmdMemAutoPhase2 = 0xE0D1, ///< ABL 2 memory initialization
TpProcMemAmdMemAutoPhase3 = 0xE0D2, ///< ABL 3 memory initialization
TpAbl3End = 0xE0D3, ///< ABL 3 End
TpAbl1EnterMemFlow = 0xE0D4, ///< ABL 1 Enter Memory Flow
TpAbl1MemFlowMemClkSync = 0xE0D5, ///< Memorry flow memory clock synchronization
TpIfAmdReadEventLogEntry = 0xE0D6, ///< IfAmdReadEventLogEntry
TpIfAmdReadEventLogExit = 0xE0D7, ///< Exiting from AmdReadEventLog
TpIfAmdGetApicIdEntry = 0xE0D8, ///< Entry to AmdGetApicId
TpIfAmdGetApicIdExit = 0xE0D9, ///< Exiting from AmdGetApicId
TpIfAmdGetPciAddressEntry = 0xE0DA, ///< Entry to AmdGetPciAddress
TpIfAmdGetPciAddressExit = 0xE0DB, ///< Exiting from AmdGetPciAddress
TpIfAmdIdentifyCoreEntry = 0xE0DC, ///< Entry to AmdIdentifyCore
TpIfAmdIdentifyCoreExit = 0xE0DD, ///< Exiting from AmdIdentifyCore
TpIfBeforeRunApFromIds = 0xE0DE, ///< After IDS calls out to run code on an AP
TpIfAfterRunApFromIds = 0xE0DF, ///< After IDS calls out to run code on an AP
TpIfBeforeGetIdsData = 0xE0E0, ///< Before IDS calls out to get IDS data
TpIfAfterGetIdsData = 0xE0E1, ///< After IDS calls out to get IDS data
TpIfBeforeAllocateHeapBuffer = 0xE0E2, ///< Before the heap manager calls out to allocate a buffer
TpIfAfterAllocateHeapBuffer = 0xE0E3, ///< After the heap manager calls out to allocate a buffer
TpIfBeforeDeallocateHeapBuffer = 0xE0E4, ///< Before the heap manager calls out to deallocate a buffer
TpIfAfterDeallocateHeapBuffer = 0xE0E5, ///< After the heap manager calls out to deallocate a buffer
TpIfBeforeLocateHeapBuffer = 0xE0E6, ///< Before the heap manager calls out to locate a buffer
TpIfAfterLocateHeapBuffer = 0xE0E7, ///< After the heap manager calls out to locate a buffer
TpAbl1MemFlowPStateSync = 0xE0E8, ///< Memory flow P-State synchronization
TpIfAfterRunApFromAllAps = 0xE0E9, ///< After the BSP calls out to run code on an AP
TpIfBeforeRunApFromAllCore0s = 0xE0EA, ///< Before the BSP calls out to run code on an AP
TpIfAfterRunApFromAllCore0s = 0xE0EB, ///< After the BSP calls out to run code on an AP
TpIfBeforeAllocateS3SaveBuffer = 0xE0EC, ///< Before the S3 save code calls out to allocate a buffer
TpIfAfterAllocateS3SaveBuffer = 0xE0ED, ///< After the S3 save code calls out to allocate a buffer
TpIfBeforeAllocateMemoryS3SaveBuffer = 0xE0EE, ///< Before the memory S3 save code calls out to allocate a buffer
TpIfAfterAllocateMemoryS3SaveBuffer = 0xE0EF, ///< After the memory S3 save code calls out to allocate a buffer
TpIfBeforeLocateS3PciBuffer = 0xE0F0, ///< Before the memory code calls out to locate a buffer
TpIfAfterLocateS3PciBuffer = 0xE0F1, ///< After the memory code calls out to locate a buffer
TpIfBeforeLocateS3CPciBuffer = 0xE0F2, ///< Before the memory code calls out to locate a buffer
TpIfAfterLocateS3CPciBuffer = 0xE0F3, ///< After the memory code calls out to locate a buffer
TpIfBeforeLocateS3MsrBuffer = 0xE0F4, ///< Before the memory code calls out to locate a buffer
TpIfAfterLocateS3MsrBuffer = 0xE0F5, ///< After the memory code calls out to locate a buffer
TpIfBeforeLocateS3CMsrBuffer = 0xE0F6, ///< Before the memory code calls out to locate a buffer
TpIfAfterLocateS3CMsrBuffer = 0xE0F7, ///< After the memory code calls out to locate a buffer
TpReadyToBoot = 0xE0F8, ///< Ready to boot event
// PMU test points
TpProcMemPmuFailed = 0xE0F9, ///< Failed PMU training.
TpProcMemPhase1End = 0xE0FA, ///< End of phase 1 memory code
TpProcMemPhase2End = 0xE0FB, ///< End of phase 2 memory code
// ABL0 test points
TpAbl0Begin = 0xE0FC, ///< Abl0Begin
TpAbl0End = 0xE0FD, ///< ABL 0 End
TpAbl5Initialization = 0xE100, ///< ABL 5 Initialization
TpAbl5DebugSync = 0xE101, ///< ABL 5 Debug Sync
TpAbl5ErrorDetected = 0xE102, ///< ABL 5 Error Detected
TpAbl5GlobalMemErrorDetected = 0xE103, ///< ABL 5 Mem Error Detected
TpAbl5End = 0xE104, ///< ABL 5 End
TpProcMemAmdMemAutoPhase1a = 0xE105, ///< ABL 5 MemAuto Phase 1a
TpProcMemPhase1aEnd = 0xE106, ///< ABL 5 MemAuto Phase 1a End
TpAbl6Initialization = 0xE107, ///< ABL 6 Initialization
TpAbl6DebugSync = 0xE108, ///< ABL 6 Debug Sync
TpAbl6ErrorDetected = 0xE109, ///< ABL 6 Error Detected
TpAbl6GlobalMemErrorDetected = 0xE10A, ///< ABL 6 Mem Error Detected
TpAbl6End = 0xE10B, ///< ABL 6 End
TpProcMemAmdMemAutoPhase2a = 0xE10C, ///< ABL 6 MemAuto Phase 2a
TpProcMemPhase2aEnd = 0xE10D, ///< ABL 6 MemAuto Phase 2a End
TpProcApobHmacFailOnS3 = 0xE10E, ///< BSP encountered HMAC fail on APOB Header
TpProcBeforeUmcBasedDeviceInit = 0xE110, ///< Before UMC based device initialization
TpProcAfterUmcBasedDeviceInit = 0xE111, ///< After UMC based device initialization
TpProcBeforeRrwTest = 0xE112, ///< Before RRW Test
TpProcAfterRrwTest = 0xE113, ///< After RRW Test
TpProcBeforeAblMemTest = 0xE114, ///< Before ABL Memory Test
TpProcAfterAblMemTest = 0xE115, ///< After ABL Memory Test
TpAblErroGeneralAssert = 0xE2A0, ///< ABL Eroor General ASSERT
TpAblErrorUnknown = 0xE2A1, ///< Unknown Error
TpAblErrorLogInitError = 0xE2A3, ///< ABL Error Log Inig Error
TpAblErrorOdtHeap = 0xE2A4, ///< ABL Error for On DIMM thermal Heap allocation error
TpAblErrorMemoryTest = 0xE2A5, ///< ABL Error for memory test error
TpAblErrorExecutingMemoryTest = 0xE2A6, ///< ABL Error while executing memory test error
TpAblErrorDpprMemAutoHeapAlocError = 0xE2A7, ///< ABL Error DDR Post Packge Repair Mem Auto Heap Alloc error
TpAblErrorDpprNoApobHeapAlocError = 0xE2A8, ///< ABL Error for DDR Post Package repair Apob Heap Alloc error
TpAblErrorDpprNoPprTblHeapAlocError = 0xE2A9, ///< ABL Error for DDR Post Package Repair No PPR Table Heap Aloc error
TpAblErrorEccMemAutoHeapAlocError = 0xE2AA, ///< ABL Error for Ecc Mem Auto Aloc Error error
TpAblErrorSocScanHeapAlocError = 0xE2AB, ///< ABL Error for Soc Scan Heap Aloc error
TpAblErrorSocScanNoDieError = 0xE2AC, ///< ABL Error for Soc Scan No Die error
TpAblErrorNbTecHeapAlocError = 0xE2AD, ///< ABL Error for Nb Tech Heap Aloc error
TpAblErrorNoNbConstError = 0xE2AE, ///< ABL Error for No Nb Constructor error
TpAblErrorApcbRecoveryError = 0xE2AF, ///< ABL Error for APCB recovery error
TpAblErrorNoTechConstError = 0xE2B0, ///< ABL Error for No Tech Constructor error
TpAblErrorAbl1bAutoAloc = 0xE2B1, ///< ABL Error for ABL1b Auto Alocation error
TpAblErrorAbl1bNoNbConst = 0xE2B2, ///< ABL Error for ABL1b No NB Constructor error
TpAblErrorAbl2NoNbConst = 0xE2B3, ///< ABL Error for ABL2 No Nb Constructor error
TpAblErrorAbl3AutoAloc = 0xE2B4, ///< ABL Error for ABL3 Auto Allocation error
TpAblErrorAbl3NoNbConst = 0xE2B5, ///< ABL Error for ABL3 No Nb Constructor error
TpAblErrorAbl1bGen = 0xE2B6, ///< ABL Error for ABL1b General error
TpAblErrorAbl2Gen = 0xE2B7, ///< ABL Error for ABL2 General error
TpAblErrorAbl3Gen = 0xE2B8, ///< ABL Error for ABL3 General error
TpAblErrorGetTargetSpeed = 0xE2B9, ///< ABL Error for Get Target Speed error
TpAblErrorFlowP1FamilySupport = 0xE2BA, ///< ABL Error for Flow P1 Family Support error
TpAblErrorNoValidDdr4Dimms = 0xE2BB, ///< ABL Error for No Valid Ddr4 Dimms error
TpAblErrorNoDimmPresent = 0xE2BC, ///< ABL Error for No Dimm Present error
TpAblErrorFlowP2FamilySupport = 0xE2BD, ///< ABL Error for Flow P2 Family Supprot error
TpAblErrorHeapDealocForPmuSramMsgBlock = 0xE2BE, ///< ABL Error for Heap Deallocation for PMU Sram Msg Block error
TpAblErrorDdrRecovery = 0xE2BF, ///< ABL Error for DDR Recovery error
TpAblErrorRrwTest = 0xEBC0, ///< ABL Error for RRW Test error
TpAblErrorOdtInit = 0xE2C1, ///< ABL Error for On Die Thermal error
TpAblErrorHeapAllocForDctStructAndChDefStruct = 0xE2C2, ///< ABL Error for Heap Allocation For Dct Struct Amd Ch Def structure error
TpAblErrorHeapAlocForPmuSramMsgBlock = 0xE2C3, ///< ABL Error for Heap Allocation for PMU SRAM Msg block error
TpAblErrorHeapPhyPllLockFailure = 0xE2C4, ///< ABL Error for Heap Phy PLL lock Flure error
TpAblErrorPmuTraining = 0xE2C5, ///< ABL Error for Pmu Training error
TpAblErrorFailureToLoadOrVerifyPmuFw = 0xE2C6, ///< ABL Error for Failure to Load or Verify PMU FW error
TpAblErrorAllocateForPmuSramMsgBlockNoInit = 0xE2C7, ///< ABL Error for Allocate for PMU SRAM Msg Block No Init error
TpAblErrorFailureBiosPmuFwMismatchAgesaPmuFwVersion = 0xE2C8, ///< ABL Error for Failure BIOS PMU FW Mismatch AGESA PMU FW version error
TpAblErrorDeallocateForPmuSramMsgBlock = 0xE2CA, ///< ABL Error for Deallocate for PMU SRAM Msg Block error
TpAblErrorModuleTypeMismatchRDimm = 0xE2CB, ///< ABL Error for Module Type Mismatch RDIMM error
TpAblErrorModuleTypeMismatchLRDimm = 0xE2CC, ///< ABL Error for Module type Mismatch LRDIMM error
TpAblErrorMemAutoNvdimm = 0xE2CD, ///< ABL Error for MEm Auto NVDIM error
TpAblErrorUnknownResponse = 0xE2CE, ///< ABL Error for Unknowm Responce error
TpAblErrorMemOverclockErrorRrwTestResults = 0xE2CF, ///< ABL Error for Over Clock Error RRW Test Results Error
TpAblErrorOverClockErrorPmuTraining = 0xE2D0, ///< ABL Error for Over Clock Error PMU Training Error
TpAblErrorAbl1GenError = 0xE2D1, ///< ABL Error for ABL1 General Error
TpAblErrorAbl2GenError = 0xE2D2, ///< ABL Error for ABL2 General Error
TpAblErrorAbl3GenError = 0xE2D3, ///< ABL Error for ABL3 General Error
TpAblErrorAbl5GenError = 0xE2D4, ///< ABL Error for ABL4 General Error
TpAblErrorOverClockMemInit = 0xE2D5, ///< ABL Error over clock Mem Init Error
TpAblErrorOverClockMemOther = 0xE2D6, ///< ABL Error over clock Mem Other Error
TpAblErrorAbl6GenError = 0xE2D7, ///< ABL Error for ABL6 General Error
TpEventLogInit = 0xE2D8, ///< ABL Error Event Log Error
TpAblErrorAbl1FatalError = 0xE2D9, ///< ABL Error FATAL ABL1 Log Error
TpAblErrorAbl2FatalError = 0xE2DA, ///< ABL Error FATAL ABL2 Log Error
TpAblErrorAbl3FatalError = 0xE2DB, ///< ABL Error FATAL ABL3 Log Error
TpAblErrorAbl4FatalError = 0xE2DC, ///< ABL Error FATAL ABL4 Log Error
TpAblErrorSlaveSyncFunctionExecutionError = 0xE2DD, ///< ABL Error Slave Sync function execution Error
TpAblErrorSlaveSyncCommWithDataSentToMasterError = 0xE2DE, ///< ABL Error Slave Sync communicaton with data set to master Error
TpAblErrorSlaveBroadcastCommFromMasterToSlaveError = 0xE2DF, ///< ABL Error Slave broadcast communication from master to slave Error
TpAblErrorAbl6FatalError = 0xE2E0, ///< ABL Error FATAL ABL6 Log Error
TpAblErrorSlaveOfflineMsgError = 0xE2E1, ///< ABL Error Slave Offline Error
TpAblErrorSlaveInformsMasterErrorInoError = 0xE2E2, ///< ABL Error Slave Informs Master Error Info Error
TpAblErrorHeapLocateForPmuSramMsgBlock = 0xE2E3, ///< ABL Error Error Heap Locate for PMU SRAM Msg Block Error
TpAblErrorAbl2AutoAloc = 0xE2E4, ///< ABL Error ABL2 Auto Error
TpAblErrorFlowP3FamilySupport = 0xE2E5, ///< ABL Error Flow P3 Family support Error
TpAblErrorAbl4GenError = 0xE2E5, ///< ABL Error Abl 4 Gen Error
TpAblErrorMbistHeapAlloc = 0xE2EB, ///< ABL Error MBIST Heap Allocation Error
TpAblErrorMbistResultsError = 0xE2EC, ///< ABL Error MBIST Results Error
TpAblErrorNoDimmSmbusInfoError = 0xE2ED, ///< ABL Error NO Dimm Smcus Info Error
TpAblErrorPorMaxFreqTblError = 0xE2EE, ///< ABL Error Por Max Freq Table Error
TpAblErrorUnsupportedDimmConfuglError = 0xE2EF, ///< ABL Error Unsupproted DIMM Config Error
TpAblErrorNoPsTableError = 0xE2F0, ///< ABL Error No Ps Table Error
TpAblErrorCadBusTmgNoFoundError = 0xE2F1, ///< ABL Error Cad Bus Timing Not Found Error
TpAblErrorDataBusTmgNoFoundError = 0xE2F2, ///< ABL Error Data Bus Timing Not Found Error
TpAblErrorLrIbtNotFoundError = 0xE2F3, ///< ABL Error LrDIMM IBT Not Found Error
TpAblErrorUnsupportedDimmConfigMaxFreqError = 0xE2F4, ///< ABL Error Unsupprote Dimm Config Max Freq Error Error
TpAblErrorMr0NotFoundError = 0xE2F5, ///< ABL Error Mr0 Not Found Error
TpAblErrorOdtPAtNotFoundError = 0xE2F6, ///< ABL Error Obt Pattern Not found Error
TpAblErrorRc10OpSpeedNotFoundError = 0xE2F7, ///< ABL Error Rc10 Op Speed Not FOund Error
TpAblErrorRc2IbtNotFoundError = 0xE2F8, ///< ABL Error Rc2 Ibt Not Found Error
TpAblErrorRttNotFoundError = 0xE2F9, ///< ABL Error Rtt Not Found Error
TpAblErrorChecksumReStrtError = 0xE2FA, ///< ABL Error Checksum ReStrt Results Error
TpAblErrorNoChipselectError = 0xE2FB, ///< ABL Error No Chipselect Results Error
TpAblErrorNoCommonCasLAtError = 0xE2FC, ///< ABL Error No Common Cas Latency Results Error
TpAblErrorCasLatXceedsTaaMaxError = 0xE2FD, ///< ABL Error Cas Latecncy exceeds Taa Max Error
TpAblErrorNvdimmArmMissmatcPowerPolicyError = 0xE2FE, ///< ABL Error Nvdimm Arm Missmatch Power Policy Error
TpAblErrorNvdimmArmMissmatchPowerSouceError = 0xE2FF, ///< ABL Error Nvdimm Arm Missmatch Power Source Error
TpAblErrorS0i3DfRestoreBufferError = 0xE300, ///< ABL Error S0i3 DF restore buffer Error
EndAgesaTps = 0xEFFF, ///< EndAgesas
} AGESA_TP;
#endif

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----------------------------------------------------------------------------
ABL RT Delivery Release Notes
Copyright 2018, Advanced Micro Devices, Inc.
Version: ABL RT WABLRTRV18080800 for Picasso
Date: Aug 8 2018
----------------------------------------------------------------------------
Contact: David Chang
----------------------------------------------------------------------------
Content:
Filename AGESA V9 Destination Folder Description
AblPostCode.h AgesaModulePkg\Firmwares\RV\ ABL/ABL RT Post Code Definitions
AgesaRTReleaseNote.txt AgesaModulePkg\Firmwares\RV\ This Release notes file
dr_agesa_prod_RV.sbin AgesaModulePkg\Firmwares\RV\ Main AGESA Runtime Driver
Based On:
Initial version
ABL RT Version String:
None
ABL RT Features and Fixes:
PLAT-34981: [PCO] Update DF s0i3 save / restore list
Known Issue(s):
----------------------------------------------------------------------------
ABL RT Delivery Release Notes
Copyright 2018, Advanced Micro Devices, Inc.
Version: ABL RT WABLRTRV18041700 for Raven
Date: April 17 2018
----------------------------------------------------------------------------
Contact: David Chang
----------------------------------------------------------------------------
Content:
Filename AGESA V9 Destination Folder Description
AblPostCode.h AgesaModulePkg\Firmwares\RV\ ABL/ABL RT Post Code Definitions
AgesaRTReleaseNote.txt AgesaModulePkg\Firmwares\RV\ This Release notes file
dr_agesa_prod_RV.sbin AgesaModulePkg\Firmwares\RV\ Main AGESA Runtime Driver
Based On:
Initial version
ABL RT Version String:
None
ABL RT Features and Fixes:
Initial ABL RT Modern Standby support
Known Issue(s):

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+-----------------------------------------+
| MP2 SFI Firmware Release Notes - Picasso
+-----------------------------------------+
+----------------------------------------------------------------------------------------------
| Version 2.0.0
+----------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 03/07/18
| * Features enabled
| - Accelerometer, Gyrometer, Magnetometer, Compass and Operating Mode Supported
| - On Tablet mode Keyboard disable is supported
| - Dynamic Calibration supported
| - LP Enabled
| - Sensors data is read after device discovery make gpio line low (if was high)
| - MH sdIntGet use GPIO1 input value instead of interrupt status
| * Issue resolved
| - Picasso released aligned with RV1 Release 1.2.22
|
| * Change Log
| - Operating Mode output and Angle is produced always.
| - MP2 Version is written into MP2 public scratch register 2
|
| Code base commit id:
| Change Id: I40647b1480175e3f0f99c5179c5e97abd29c261a
| Commit Id: f617543f48014d2fb841bbb26e58518ecd30e7e7
| Gerrit Id: 159030
|
| Jira ID : [PLAT-32026] SFH shall support change in Operating Mode angle
|
| * Limitation
| - I2C Read works on poll
| - Sensors should be disabled before S4 entry
|
+----------------------------------------------------------------------------------------------
| Version 2.0.0.1
+----------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 11/07/18
| * Features enabled
| - Accelerometer, Gyrometer, Magnetometer, Compass and Operating Mode Supported
| - On Tablet mode Keyboard disable is supported
| - Dynamic Calibration supported
| - LP Enabled
| - Sensors data is read after device discovery make gpio line low (if was high)
| - MH sdIntGet use GPIO1 input value instead of interrupt status
| * Issue resolved
| - Magnetometer not working after CB/WB
|
| * Change Log
| - Set MP2 clock at 200 Mhz before device discovery
|
| Code base commit id:
| Change Id: Ia552b0435074297c4b364c7b6c6edb519368df17
| Commit Id: 210a9d4af73aba2f94a144173821c9c3edbae0f9
| Gerrit Id: 161518
|
| Jira ID : [PLAT-32026] SFH shall support change in Operating Mode angle
|
| * Limitation
| - I2C Read works on poll
| - Sensors should be disabled before S4 entry
|
+----------------------------------------------------------------------------------------------
| Version 2.0.3.0
+----------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 14/08/18
| * Features enabled
| - Accelerometer, Gyrometer, Magnetometer, Compass, Operating Mode
| Ambient Light Sensor, Time Of Flight Sensors are supported
| - On Tablet mode Keyboard disable is supported
| - GPIO interrupt trigger if Brightness less than 200 lux
| - Dynamic Calibration supported
| - LP Enabled
| - Sensors data is read after device discovery make gpio line low (if was high)
| - MH sdIntGet use GPIO1 input value instead of interrupt status
| - Single Fimr
| * Features Added
| - Single Firmware binary supported with Config file support all customer sensors.
| - Customer specific config file to be used. Default support LSM6DS3 + LIS3MDL + LIS2DE12
|
| * Change Log
| - Set MP2 clock at 200 Mhz before device discovery
|
| Code base commit id:
| Change Id: I00f15b90164827ecca0ecab807f5f2826091002e
| Commit Id: 996d5685b3ec5fe5d5642f490da4ea59cea75133
| Gerrit Id: 167607
|
| Jira ID : [PLAT-35329] [PCO] Support single firmware for all customer sensors
|
| * Limitation
| - I2C Read works on poll
| - Sensors should be disabled before S4 entry
|
+----------------------------------------------------------------------------------------------
| Version 2.0.3.14
+----------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 15/11/18
| * Features enabled
| - Accelerometer, Gyrometer, Magnetometer, Compass, Operating Mode
| Ambient Light Sensor, Time Of Flight Sensors are supported
| - On Tablet mode Keyboard disable is supported
| - GPIO interrupt trigger if Brightness less than 200 lux
| - Dynamic Calibration supported
| - LP Enabled
| - Sensors data is read after device discovery make gpio line low (if was high)
| - MH sdIntGet use GPIO1 input value instead of interrupt status
| - Single Fimr
| * Features Added
| - Single Firmware binary supported with Config file support all customer sensors.
| - Customer specific config file to be used. Default support LSM6DS3 + LIS3MDL + LIS2DE12
| - Set MP2 clock at 200 Mhz before device discovery
|
| * Change Log
| - Block SMN access during S0i3
|
| Code base commit id:
| Change Id: I21c7a993b5c4c927794eb7ef11f2398ae8e1545a
| Commit Id: b62f5103a817694e703626ebf611c500f178b267
| Gerrit Id: 187219
|
| Jira ID : [PLAT-39289] [PCO] S0i3 fails to resume
|
| * Limitation
| - I2C Read works on poll
| - Sensors should be disabled before S4 entry
|
+---------------------------------------------------------------------------------------------
| Version 2.0.3.15
+---------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 20/11/18
|
| * Enabled Low power i.e 48MHz support.
| * Integrated the changes from RV1 to Rv2 for low power mode.
|
| * Change:
| - PLAT-39408 Implement MP2_FIRMWARE_FLAG as MP2 FW loading indicator
| - Git Change-Id: I36865278f4ac37d7db2d84bfe21acad335fcb0df
| - Gerrit ID: 188070
| - Commit Id: 3af17da6978c329edaf06a3e7691aad8c8eddb20
| * Limitation
|
+------------------------------------------
+---------------------------------------------------------------------------------------------
| Version 2.0.3.17
+---------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 20/11/18
|
| * Enabled Low power i.e 48MHz support.
| * Integrated the changes from RV1 to Rv2 for low power mode.
|
| * Change:
| - PLAT-40149 Add Book Mode Disable Support
| - Git Change-Id: Iaca6e2c793a22434041756dca85d2543bf926624
| - Gerrit ID: 191054
| - Commit Id: a73bf6d947540ab20125e4f4bd1179783cdcec33
| * Limitation
|
+------------------------------------------

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+-----------------------------------------+
| MP2 SFI Firmware Release Notes - RAVEN2X
+-----------------------------------------+
+----------------------------------------------------------------------------------------------
| Version 3.0.0
+----------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 24/05/18
| * Features enabled
| - Accelerometer, Gyrometer, Magnetometer, Compass and Operating Mode Supported.
| - On Tablet mode Keyboard disable is supported
| - Dynamic Calibration supported
| - LP disabled
| - Sensors data is read after device discovery make gpio line low (if was high)
| - MH sdIntGet use GPIO1 input value instead of interrupt status
| * Issue resolved
| - RV2 released aligned with RV1 Release 1.2.21
|
| * Change Log
| - Operating Mode output and Angle is produced always.
|
| Code base commit id:
| Change Id: Iaff94aeb13ca7dbcc4adb4b2f089245ad99d4bc9
| Commit Id: f4aacddb7f05d3ddc49d6ec49ae7d52881bc8103
| Gerrit Id: 151081
|
| Jira ID : [PLAT-32026] SFH shall support change in Operating Mode angle
|
| * Limitation
| - I2C Read works on poll
| - Sensors should be disabled before S4 entry
|
+----------------------------------------------------------------------------------------------
| Version 3.0.2.5
+----------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 21/11/18
| * Features enabled
| - Accelerometer, Gyrometer, Magnetometer, Compass and Operating Mode Supported.
| - On Tablet mode Keyboard disable is supported
| - Dynamic Calibration supported
| - LP disabled
| - Sensors data is read after device discovery make gpio line low (if was high)
| - MH sdIntGet use GPIO1 input value instead of interrupt status
| * Issue resolved
| - Aligned with PCO branch.
|
| * Change Log
| - Update MP2 FW Flags
| - Block SMN access during S0i3
|
| Code base commit id:
| Change Id: I19f23b942ce07a303c00a241935c13ba57e8b54b
| Commit Id: 8268706bd684a001bd899e0c16a48f0da49834be
| Gerrit Id: 188364
|
| Jira ID : [PLAT-39408] SFH RV2 Implement MP2_FIRMWARE_FLAG as MP2 FW loading indicator
|
| * Limitation
| - I2C Read works on poll
| - Sensors should be disabled before S4 entry
|
+---------------------------------------------------------------------------------------------
| Version 3.0.2.6
+---------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 20/11/18
|
| * Enabled Low power i.e 48MHz support.
| * Integrated the changes from RV1 to Rv2 for low power mode.
|
| * Change:
| - PLAT-40149 Add Book Mode Disable Support
| - Git Change-Id: I19f23b942ce07a303c00a241935c13ba57e8b54b
| - Gerrit ID: 188364
| - Commit Id: 8268706bd684a001bd899e0c16a48f0da49834be
| * Limitation
|
+------------------------------------------

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+---------------------------------------------------------------------------------------------
| Version 1.1.0
+---------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 09/03/18
| * The MP2 I2C firmware is enabled for Picasso Platform with S0i2 and S0i3 support
| The firmware shall support Touch Pad, NFC Devices and certain Touch Panel device
| connected with I2C0 and I2C1
|
| * Features enabled
| - Enable I2C Read/Write for devices connected with i2c0,1
| - Max Read supported 2k bytes
| - Max write supported 32 bytes
| - Add Support for NFC and Touch Pad on I2Cx
| - Add MP2 Diag Support
| - Read DRAM data in the main thread instead of Interrupt Thread
| - Add Lock after each 32 byte read and write
| - MP2 I2C PCIe Device Id 0x15E6.
| - MP2 Deep Sleep
| - MP2 S0i2 support (Available and Enabled)
| - MP2 S0i3 support (Available and Enabled)
|
| * Change:
| - PLAT-29483 : Enable S0i2, S0i3 in MP2 Firmware
| - Git Change-Id: I3c0d11d98a3ff5678f3ea92f2fdc0d82ca49e92f
| - Gerrit ID: 134888
| - Commit Id: 1450e0eeb41e6b975df16fe42713455fd3e1745f
| * Limitation
|
+---------------------------------------------------------------------------------------------
| Version 1.1.1
+---------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 27/04/18
| * New Header Field, FW Type for MP2 Fw .
|
| * Change:
| - PLAT-30716 : New Header Field, FW Type, Needed for MP2 FW
| - Git Change-Id: I3c0d11d98a3ff5678f3ea92f2fdc0d82ca49e92f
| - Gerrit ID: 134888
| - Commit Id: 1450e0eeb41e6b975df16fe42713455fd3e1745f
| * Limitation
|
+---------------------------------------------------------------------------------------------
| Version 1.1.2
+---------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 05/06/18
| * Enable 48Mhz LowPower Deep Sleep
| * Aligned with RV1 release
|
| * Change:
| - PLAT-31000: MP2CLK not entering deep sleep starting from WMD8322N BIOS
| - Git Change-Id: I1d10e41512a764ad92495c476b2995e2658bd845
| - Gerrit ID: 153195
| - Commit Id: db065617f4c0c826873dc5c9a24bfd68adb8ce83
| * Limitation
|
+---------------------------------------------------------------------------------------------
| Version 1.1.2.1
+---------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 07/05/18
| * Features enabled
| - Added support for firmware version information.
|
| * Change:
| - [PLAT-33691] Version information support in the mp2 firmware
| - Git Change-Id: I53e48e49101c7e36738adb0266af076426ddf731
| - Gerrit ID: 158990
| - Commit Id: fa69ec432bdccb957f34d222fd0b2bb29ab7871a
| * Limitation
|
+---------------------------------------------------------------------------------------------
| Version 1.1.2.3
+---------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 28/08/18
| * Features enabled
| - Optimised the read function.
| - Added error handling, i.e for faulty case MP2 will not hang.
|
| * Change:
| - [SWDEV-162698] NFC, functionality is not working on enabling I2C1 under BIOS
| - Git Change-Id: I060483887ba5f4a0d9464b5f5dc97868d9c54418
| - Gerrit ID: 169962
| - Commit Id: aad62923274be1961bb804e73403621c4fc31016
| * Limitation
|
+---------------------------------------------------------------------------------------------
| Version 1.1.2.4
+---------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 21/11/18
| * Features enabled
| - Optimised the read function.
| - Added error handling, i.e for faulty case MP2 will not hang.
|
| * Change:
| - Update MP2 Firmware Flag
|
| - [PLAT-39408] PCO I2C Implement MP2_FIRMWARE_FLAG as MP2 FW loading indicator
| - Git Change-Id: Idaeee9abd78955d447ad44b2d6c09c4df242fc9b
| - Gerrit ID: 188087
| - Commit Id: 13e1b53b05223a04ec43566de14f5a7a2ba3aee8
| * Limitation
|
+---------------------------------------------------------------------------------------------

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+-----------------------------------------+
| MP2 I2C Firmware Release Notes - RAVEN2X
+---------------------------------------------------------------------------------------------
| Version 1.2.0
+---------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 09/03/18
|
| * The MP2 I2C firmware is enabled for Picasso Platform with S0i2 and S0i3 support
| The firmware shall support Touch Pad, NFC Devices and certain Touch Panel device
| connected with I2C0 and I2C1
|
| * Features enabled
| - Enable I2C Read/Write for devices connected with i2c0,1
| - Max Read supported 2k bytes
| - Max write supported 32 bytes
| - Add Support for NFC and Touch Pad on I2Cx
| - Add MP2 Diag Support
| - Read DRAM data in the main thread instead of Interrupt Thread
| - Add Lock after each 32 byte read and write
| - MP2 I2C PCIe Device Id 0x15E6.
| - MP2 Deep Sleep (48Mhz)
| - MP2 S0i2 support (Available and Disabled)
|
| * Change:
| - PLAT-28199 : [RV2X][MP2]See MP2 mailbox registers couldn't be accessed from host
| - Git Change-Id: I827b3331c26db8551b1f218a498d17fa6352f049
| - Gerrit ID: 135791
| - Commit Id: bae849be50145e551dbaf6a9f82e91e566c34380
| * Limitation
|
+---------------------------------------------------------------------------------------------
| Version 1.2.1
+---------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 23/04/18
|
| * Taken the changes from RV1 master branch.
| * MP2 Reference clock is set at 200MHz on load by setting SEL_MP2CLK, SOC_CLK, SMN_CLK.
| * Commented the preprocessor macro LP_626 in project settings to disable low power.
| * Enabled the register C2PM12/15 in main.
|
| * Change:
| - PLAT-30616 : [RV2-FP5] The SFH device will lost and device ID
| change from 15E6 to 15E4 after running S4 or S3 test RS3.
| - Git Change-Id: I5da0fc644c457b039936027115e707bf5b65b303
| - Gerrit ID: 144325
| - Commit Id: 21508b30f7cd2562227d6bb09e235570cdfeefdb
| * Limitation
|
+---------------------------------------------------------------------------------------------
| Version 1.2.2.0
+---------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 10/07/18
|
| * Enabled Low power i.e 48MHz support.
| * Integrated the changes from RV1 to Rv2 for low power mode.
|
| * Change:
| - PLAT-33860 : [RV2] Enable Low power support
| - Git Change-Id: Ifb946babde6f52e02654ae5ab8a0bfcf591d07dc
| - Gerrit ID: 160642
| - Commit Id: 5d4ee51bb22c19369c6bec4540f90130874b5edd
| * Limitation
|
+---------------------------------------------------------------------------------------------
| Version 1.2.2.3
+---------------------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 10/07/18
|
| * Enabled Low power i.e 48MHz support.
| * Integrated the changes from RV1 to Rv2 for low power mode.
|
| * Change:
| - PLAT-39408 Implement MP2_FIRMWARE_FLAG as MP2 FW loading indicator
| - Git Change-Id: I85e79f15db98a371d96381b5039c2d9fb671b8ba
| - Gerrit ID: 188035
| - Commit Id: 5ab5e8d269c5bbd6526f95c01324ed412a0e8f6b
| * Limitation
|
+---------------------------------------------------------------------------------------------

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//----------------------------------------------------------------------------
// PSP FW Delivery Release Note
//
// Copyright 2019, Advanced Micro Devices, Inc.
// Date: January 09, 2019
//----------------------------------------------------------------------------
Content:
PSP FW Deliverables for Raven Ridge. Sync-up to HW register to RTL CL#570439
This Build is compiled using the ARM license from the AMD license server.
Files:
PspBootLoader_prod_RV.sbin [version: 0.8.3.59] - PSP off-chip BootLoader (entry type 0x1), signed with production key
PspRecoveryBootLoader_prod_RV.sbin [version: 0.8.3.59] - PSP off-chip Recovery BootLoader (entry type 0x3), signed with production key
secure_unlock_prod_RV.sbin [version: 0.8.3.59] - PSP secure unlock (entry type 0x13), signed with production key
psp_os_combined_prod_RV.sbin [version: 0.8.3.59] - PSP secure OS (entry type 0x2), signed with production key
drv_sys_prod_RV.sbin [version: 0.8.3.59] - PSP system driver (entry type 0x28), signed with production key
dr_ftpm_prod_RV.csbin [version: 3.22.0.4] - PSP fTPM (entry type 0xC), compressed and signed with production key
security_policy_RV1_FP5_AM4.sbin [version: A.2.3.2] - Raven1_Security_Policy for Raven1 program (entry type 0x24), signed with production key
security_policy_PCO_FP5_AM4.sbin [version: A.2.3.27] - Raven1_Security_Policy for Picasso program (entry type 0x224), signed with production key
security_policy_RV2_FP5_AM4.sbin [version: A.2.4.25] - Raven2_Security_Policy for Raven2 program (entry type 0x124), signed with production key
ver 0.8.3.59
00. Code base updated to CL#61260.
01. PLAT-39742: Update RV2 security policy to 10.2.4.37 (Hex:0A020425)
ver 0.8.2.59
00. Code base updated to CL#60943.
01. PLAT-39863: Fix in changes ported in 0.8.1.59, missing one line.
02. PLAT-39987: [PCO] fTPM NVRAM getting corrupted on boot-up, fTPM version updated to 3.22.0.4.
03. PLAT-39511: BSOD 0xEA when do Skype video chat.
NOTE: This point release is not meant for PI w/ AM4 packaging and NPU support, as the team agreed.
ver 0.8.1.59
00. Code base updated to CL#60908, no update in fTPM version and updated PCO security policy.
01. PLAT-39863: [PCO FP5 MS] SMNCLK and MP0CLK are not in DS after S0i3 resume - ~60mW increase on VDDSOC.
02. PLAT-39535: [PCO] Update Security Policy of PCO to version 10.2.3.39 (Hex: A.2.2.27).
NOTE: This point release is not meant for PI w/ AM4 packaging and NPU support, as the team agreed.
ver 0.8.0.59
00. Code base updated to CL#60036, no update in fTPM version
01. SWDEV-168931: Add SPClient config for tOS Signing Key and modify Security Policy compiler.
02. PSP-3507: [VG] Add new SysDrv service to allow XGMI TA reading specific registers.
03. PLAT-38385: [PCO] PSP Fw need send out Cold Reset type for Thermtrip recovery.
04. PLAT-38514: [VG20][SRIOV] Add L1 Security Policy compiler.
05. PLAT-38233: [VG10][SRIOV] Program MEC Jump Table 1 as VF Trust Level when GRBM Virtualization Firewall gets enabled.
06. PLAT-37318: [PCO] Adding specific ID to support PCO SMU/ MP2/SecurityPolicy FW in PSP directory.
07. SWDEV-148328: [VG] XGMI support over Guest Gfx Interface.
ver 0.8.0.58
00. Code base updated to CL#53148, no update in fTPM version
01. Reverting PLAT-37481 due to issue.
ver 0.8.0.57
00. Code base updated to CL#53109, fTPM version is updated to 3.21.0.4
01. Update VG10 L1 Policy Compiler to v9.1.11.40 which is release candidate.
02. SWDEV-168526: [VG20] Support for embedded security policy (header) and SRIOV L1 policy security concern.
03. PSP-3516: Move AMD-TEE SysDrv library files out of 10-RV folder.
04. SWDEV-162443: [VG20] SMU signed FW is using VG10 Key which needs to be replaced.
05. PLAT-37960: PLAT-37953: PLAT-37972: Coverity CIDs 15771, 15875 & 15873 fixes.
06. SWDEV-152309: [VG20] FLR is not working.
07. SWDEV-168931: [VG20] Add SPClient Config for tOS Signing Key and modify Security Policy compiler.
08. SWDEV-168403: [RV2] TMZ not configured correctly.
09. PLAT-38036: [RV] Update PSP Authentication Requirements for Pro 560 (DID 0x43D2) and B550 (DID 0x43D1).
ver 0.8.0.56:
00. Code base updated to CL#52932, fTPM version is updated to 3.21.0.4
01. SWDEV-162443: [VG20] SMU signed FW is using VG10 Key which needs to be replaced.
02. PLAT-37772: [RV] Coverity CID 15772 & CID 15895 fixes.
03. PLAT-35018: [RV] Observed FW_Status "0000010D" for Raven 0.8.0.4B recovery BIOS.
04. PLAT-35972, PLAT-33143, PLAT-32476, PLAT-33063, PLAT-35487:[RV] RPMC support in fTPM and new NVRAM structure.
05. PLAT-37481: [RV] Add support for multiple 0x62 entries loading to PSP BL
ver 0.8.0.55:
00. Code base updated to CL#52835, no update in fTPM version
01. PLAT-37712: System does not boot to Windows with latest PSPFW on non-secure ASIC.
02. PLAT-37664: PLAT-37658: [RV] Fixes for Coverity reported issues.
03. PLAT-37602:[VG20] PSP Data Abort on reading from MM-SCH Mailbox on reporting VCE Periodic Validation violation.
ver 0.8.0.54:
00. Code base updated to CL#52797, no update in fTPM version
01. PSP-3507: Add new SysDrv service to allow XGMI TA reading specific registers.
02. PLAT-35152: Coverity 33156 - Uninitialized scalar variable.
03. PLAT-37313: [VG20] Revert applied L0 Policy on Secure Debug Unlock.
04. Back out of SWDEV-162443: [VG20] SMU signed FW is using VG10 Key which needs to be replaced.
05. PLAT-37441: Remove older mechanism of loading security policy.
06. SWDEV-157058:[VG20] Mode1 Reset - Unconfigure C2PMSG SRIOV registers.
07. SWDEV-167192: [PCO][PlayReady] 80004005 error with multiple concurrent H.264 Netflix PlayReady HW DRM sessions.
08. PLAT-37608:[VG10][SRIOV] Address Coverity issues associated with SR-IOV infrastructure.
09. PLAT-37666: Update Security Policy to 10.2.3.34 for PCO.
ver 0.8.0.53:
00. Code base updated to CL#52660, no update in fTPM version
01. PLAT-32908: AMD Field Fusing Tool - OEM/ODM/IVB Edition.
02. SWDEV-162443: [VG20] SMU signed FW is using VG10 Key which needs to be replaced.
03. SWDEV-164404: [VG20] Load L0 Security Policy through VBIOS instead of embedding PSP FW.
04. SWDEV-136041: [VG20] Implement SR-IOV functionality in VG20 PSP Trusted OS.
05. PLAT-33496: [PCO] Enable back DMCU FW loading for S0i3.
06. PLAT-33493: [PCO] Resolve ASD driver dependency for S0i3.
07. PLAT-37307: [PCO] DMCU firmware not loaded on S0i3 resume.
ver 0.8.0.52:
00. Code base updated to CL#52526, fTPM version was updated to 3.20.0.4
01. PSP-3513: [AMD-TEE] Increase stack size of TA notification handler thread in tOS.
02. PLAT-36798, PLAT-36800: [Vega10][SRIOV] Load L0/L1 Policy through VBIOS.
03. RDAR-43003597: Fix HARD HANG Caused by HotPlugs/Unplugs multi 4K.
04. PSP-3507: Add new SysDrv service to allow XGMI TA reading specific registers.
05. PLAT-35966: PSP FW - SYS DRV - Coverity CID 472719.
06. SWDEV-158866: [PCO][PlayReady] Encrypted PlayReady TA.
07. SWDEV-156642 - VG10/12 Mode1 Reset - Unconfigure C2PMSG SRIOV registers.
08. PLAT-37059: [PCO] Fix System cannot enter S0i3 (second cycle) with PSPFW 0.8.0.51.
ver 0.8.0.51:
00. Code base updated to CL#52361, no update in fTPM version
01. SWDEV-163112: [Vega12/D20621-PCIE] The security policy was reset when GFXoff enabled.
02. SWDEV-165013 - VG20 BACO/BAMACO SOS Implementation.
03. PLAT-36563 - [Vega10][SRIOV] Support IH_RB_CNTL Register Programming for VFs over the VF Ring.
04. PLAT-36595: Add a new ATAG parameter to pass on IPv4 information to KVMOS.
05. PLAT-35971: RPMC support needed in trustedOS.
06. PLAT-35942: [PCO] System with Secure Part hangs when playing online video after resuming from S0i3.
07. PLAT-36596: Fix reporting of Security Violations to C2P_MSG registers.
08. PSP-3507: Add new SMU-to-PSP command for getting XGMI topology information.
09. PLAT-36503: [PCO] DF Cstate is not getting re-enabled at the end of S0i3 cycle preventing S0i3 re-entry (postcode 0001).
10. PLAT-36712: [PCO] TMR Regions integrity check on S0i3 cycle.
11. PSP-3512 - [PlayReady] Implementation of SysDrv API for getting properties of other modules.
12. PLAT-35435: Fixing RV2-specific PSP dir types issue.
ver 0.8.0.50:
00. Code base updated to CL#52164 and fTPM version updated to 3.19.0.4
01. PLAT-35839: [RV] Fix AMD-TEE Secure OS bugs in mmu.c and bios_mailbox.c.
02. PLAT-35905: [V10] PSP incorrectly resolves VF ID during Manual GPU Scheduling mode.
03. PLAT-35968 - [VG10] GIM Hypervisor driver Mode1 Reset failure.
04. DIAG-2503: PSP SDMA front door issue fixes.
05. PLAT-34293: [VG10] Periodic MEC FW validation.
06. PSP-3510: Fix PSP boot latency issue on dGPU.
07. PSP-3509: AACS decryption prototyping.
08. PLAT-34394:[VG10] PSP should check for illegal instruction execution of UVD/VCE FW for all Active VFs.
09. PSP-3512: [RV] Implementation of SysDrv API for getting properties of other modules.
10. PLAT-35435: [RV/PCO] Variable 2nd Storage Support in PSP BL.
11. PLAT-36259: [VG10] Update L1 Security Policy to v9.1.1.26 and allow PSP section of L1 Policy to be reverted on Debug Unlock.
12. PLAT-34830: [RV] fTPM Recovery Mechanism Requirement. VG20 boot fix.
13. SWDEV-162566: [VG20] SMU hang waiting for PSP response to SMU2PSP_CMD_GFX_CONTEXT_SAVED message.
14. PSP-3512: [RV] Bug fix in SysDrv API for getting properties as uint32.
15. PLAT-35905:[VG10] Remove GetVfId Service call from PSP Kernel.
16. SWDEV-160590: [VG20] Mode2 Reset Implementation.
17. SWDEV-163478: [RV] Change in PSP to maintain patch level for non-PSP FW.
18. SWDEV-160590: [VG20] Mode2 Reset - System Driver compiler warnings on non VG20 ASICs
19. PLAT-35297: [PCO][PRD] Enable ASSR on VBIOS notification.
20. PLAT-36409: Populate debugging information to C2P registers in case of Abort in BL.
21. PLAT-36479: Enable Encryption of Security Policy binaries.
22. PLAT-36295: Merge Build related changes done in Secure OS and System Driver for MTS/CP
23. PLAT-36509 : [PCO][PlayReady] Encrypted PlayReady TA Failure
24. PLAT-35054: Fix errors in handling GfxOff command from SMU.
ver 0.8.0.4F:
00. Code base updated to CL#51870, no update in fTPM version.
01. PLAT-35866: [RV] Remove DisableDfCstate from SaveTmrRegisters function and Use new Cmd for request to SMU for disabling/enabling DfCstate.
02. PLAT-34293/PLAT-34295: [VG10] Periodic MEC FW validation and Evasive action for Virtual Functions
ver 0.8.0.4E:
00. Code base updated to CL#51848, no update in fTPM version.
01. Back out change list 51830 PLAT-34293/PLAT-34295.
ver 0.8.0.4D:
00. Code base updated to CL#51835, fTPM version updated to 3.17.0.4 and PCO security policy is updated to 10.2.3.30
01. SWDEV-156939: [VG20] Failed to playback Blue ray discs(HDCP).
02. PLAT-32646: [VG20] Enable MP0/MP1 HS during WFI for SOC ULV.
03. PLAT-34830: [RV] fTPM recovery mechanism requirements.
04. PLAT-33119: [RV][VG] Security fixes in FindTaProperty.
05. PSP-3507: Modify XGMI topology structure according to agreement between Boot Loader and XGMI TA.
06. PLAT-35379: [PCO] Save/restore PSP only registers - for S0i3 Secure ASIC.
07. PLAT-34742: [VG10] PSP applies the SR-IOV RSMU Security policy twice
08. SWDEV-156599: [VG10] SRIOV bring-up tasks.
09. PLAT-35008: [RV2] Enable KVM support for RV2.
10. PSP-3458: Address Coverity issues.
11. PLAT-35515: [VG] Enable Applying/Reverting of Security Policy using separate binary to dGPU platforms.
12. PSP-3508: [RV] Modify PSP SRAM allocation for TA to allow multiple TAs to use SRAM.
13. PLAT-35519: Update Security Policy to version 10.2.3.30 for Picasso program ONLY.
14. PLAT-35520: Remove direct programming of DF:GCM_Enable and create new SMU cmd handler for programming register on S0i3 resume.
15. SWDEV-152804: [RV1] WA for HW bug. Remove static disable DF CS data forwarding enabled.
16. PLAT-35694: Latest PSP changes does not work - fails on S0i3 resume.
17. PLAT-34293/PLAT-34295 - [Vega10][SRIOV] Periodic MEC FW validation and Evasive action for Virtual Functions.
18. PLAT-33130: [fTPM] [RV] Insufficient Validation of fTPM Command Header Length.
19. PLAT-33061: [fTPM] [RV] The assert macro is disabled in release builds in the fTPM.
ver 0.8.0.4C:
0. Code base updated to CL#51533 and fTPM version updated to 3.16.0.4.
1. PLAT-34521: PSP should support separate GPCOM and RBI Destroy Ring commands
2. PSP-3506: Initial implementation of handling of WLAN unified binary in tOS (disabled).
3. PSP-3507: Implementation of SysDrv interfaces for XGMI TA to get XGMI topology info, enable/disable XGMI sharing, get current VF ID, get number of VFs.
4. SWDEV-156939: VG20 Failed to playback Blue ray discs(HDCP).
5. PLAT-34853: [PCO RV2 Combo] System hang at PC0026 with RV2 EVT-PCO dual source secure 1M25E5C4T2OFB.
ver 0.8.0.4B:
00. Code base updated to CL#51411 and fTPM version updated to 3.16.0.4.
01. SWDEV-157058: [VG20] Code changes for Mode1 Reset.
02. PLAT-34516: Fix - check conditions of saving data to MP2 RAM1.
03. SWDEV-157991: GPU-P: PSP load UVD & VCE ucode fail.
04. PLAT-33045: [PSP Phase II] The shared DLM buffer can be abused to corrupt TEE OS memory
05. PLAT-34675: Allow replacement of data at the existing entry if the size is same in MP2 RAM1.
06. PLAT-32478: [PSP Phase II] GPU IP firmware validation failure handling doesn’t return system to a safe state.
07. PLAT-34795: Create new service call for AGESA run time driver and PSP for writing data to MP2 RAM1.
08. DESPCSOC-2174: [Picasso Modern Standby] During S0i3 resume ABL binaries for memory and DF restore are getting loaded from SPI instead of POR MP2 SRAM.
09. PLAT-34799: Fix DF_GCM_ENABLE register programming.
10. PLAT-33492: Enabled back setting up of RSMU Interrupts (disabled for S0i3 during S0i3 bring-up)
ver 0.8.0.4A:
0. Code base updated to CL#51250 and no update in fTPM version.
1. SWDEV-156939: Display additional debug information from secure OS.
2. SWDEV-155084: [VG10][SRIOV] Fix SRIOV mode detection inside the IP FW loading.
3. SWDEV-155523 [RV] HDCP Support for Mira-cast.
4. PSP-3502: Implement DLM token validation.
5. PLAT-34383: Create Security Policy binary v. 10.2.3.29 and allow only this or greater than 0.29 version to Picasso.
ver 0.8.0.49:
0. Code base updated to CL#50710 and no update in fTPM version.
1. PSP-3503: Make local copy of Boot Loader mailbox buffer in SysDrv.
2. SWDEV-136064: [VG20] Program the fabric ID to MMHUB1 and unit ID to 0x3 when setting-up TMR region for UVD0 FW loading.
3. PLAT-33399: [RV] Picasso Modern Standby(S0i3), Save/Restore TMR registers and restore DF Late Security Policy
4. SWDEV-151541: [VG20] Added support for Mode1 Reset.
5. SWDEV-136058: [VG20] Multi-instance UVD FW loading and validation.
6. SWDEV-155084: [VG10][SRIOV] Add support for multiple Memory Regions for IP loading depends on Vfid and fix bug for CL#50949.
ver 0.8.0.48:
0. Code base updated to CL#50710 and no update in fTPM version.
1. PLAT-33037: [RV] Save ABL0 binary to MP2 RAM1 on S5 and read on S3 resume from RAM1 instead of SPI-ROM.
2. PLAT-33184: [RV][VG] Boundary macros to prevent integer overflow, restricted buffer overlap and check white-list buffer.
3. PLAT-31211: [VG20] Mapping TMR registers changed to index based indirect access.
4. PLAT-33266: PSP Kernel hang while accessing TMR registers through SMN.
5. PLAT-30616: [RV2] Update Reset & Loading sequence of MP2 firmware for RV2 only.
6. PLAT-32664: Turn on eDP on S3 resume early as possible for quick boot and fast resume.
7. PLAT-32445: [PSP Phase II] Arbitrary memory overwrite while loading components.
8. PLAT-30983: Update Copyright header for files which are part of NDA package.
ver 0.8.0.47:
0. Code base updated to CL#50468 and no update in fTPM version.
1. PLAT-32357: [RV][VG] Secure OS hangs at PC A5D5 with WMC8530N.
2. SWDEV-153927: [VG12] PNP fix, re-applying security policy and restoring HCID & SIID values after GFX-OFF exit
3. PLAT-32161: [RV] New mechanism of loading Rsmu_Security_Policy using separate binary in SPI-ROM.
4. PLAT-32161: [RV] Add SysDrv service for getting RSMU security policy version.
5. PSP-3496: Address security concern regarding issue with Panic() usage when getting Object and Operation handles in TEE I/F handlers.
6. PSP-3496: Address security concern regarding TEE interface (use local copy of command buffer).
7. PSP-3496: Address security concern regarding DLM interface (use local copy of Wptr value when writing DLM string to buffer).
8. PSP-3496: Address security concern regarding loading MMSCH IP.
ver 0.8.0.46:
0. Code base updated to CL#50300 and no update in fTPM version.
1. PSP-3458: [RV][VG] Address Coverity issues.
2. SWDEV-155084: [VG10][SRIOV] New Gfx interface for SRIOV.
3. SWDEV-153792: [VG12] Skipping SMU FW loading if firmware already loaded.
4. PSP-3496: [RV][VG] Enable ARM stack protection in Trusted OS, Kernel, SysDrv, TAs and Drivers.
5. PSP-3496: [VG12] Fix issue in GFXOFF exit handling.
6. SWDEV-148450: [VG10][SRIOV] Fix SMN mapping logic to access to virtual copy of registers (to program IH_RB_CNTL registers).
7. SWDEV-146174: [RV][VG] Support multiple invoke cmd handling in gfx interface.
8. PLAT-32378: [RV] Changes to identify Picasso ASIC and latest S0i3 changes integration from bring-up branch.
ver 0.8.0.45:
0. Code base updated to CL#50054 and no update in fTPM version.
1. PSP-3495: Address security concerns from customer review.
2. PSP-3492: [SRIOV] Fix interrupt handling.
3. PLAT-31141: Bug fix in Write TMZ keys to existing UMC channels.
4. PLAT-31211: [VG20] Bring-up activity, Enable Secure Debug Unlock.
5. PLAT-32034: Fix FwType mismatch issue for driver/ta binaries which are validated in sOS.
ver 0.8.0.44:
00. Code base updated to CL#49983 and no update in fTPM version.
01. PLAT-31211: [VG20] Enable support of Vega20 in sOS.
02. PSP-3492: [VG][SRIOV] New Gfx interface which uses only 3 registers and available only in SRIOV mode.
03. PLAT-30790: Separate out Security Policy for RV1 AM4 platforms, currently same security policy as of RV1 FP5 platforms.
04. PLAT-31322: [RV2] Some additional registers were found which have different addresses from RV1 spec.
05. PLAT-31668: Support decryption of binaries in BL and enable encryption of PSP firmware binaries.
06. PLAT-29590: [RV] Additional changes - power optimization of PSP FW in S0i2 state.
07. PLAT-31758: New service calls in PSP BL for ABL. i) Calculate & Validate HMAC for ABL ii) Load APOB buffer from SPI-ROM to MP0 SRAM chunk by chunk.
08. PLAT-31813: Bug fixes for i) System does not go to RecoveryMode in case of absence of binary ii) Copy data to local buffer before processing BiosCmd, was raised in code review.
09. PSP-3458: PLAT-31881: Address Coverity issues.
10. PSP-3495: Make local copy of FW header in Fw validation function, was raised in code review.
ver 0.8.0.43:
00. Code base updated to CL#49802 and no update in fTPM version.
01. PLAT-30947: Updated PSP BL SVC call interface file to ABL to reflect correct definitions.
02. PLAT-31047: Integrate S0i3 bing-up changes.
03. PLAT-31513: Adding additional check conditions for MMHUB mapping against TMR registers.
04. SWDEV-148450: [Vega10][SRIOV] Fix logic for MC_SPACE=3 case to program IH ring registers.
05. PLAT-31613: Project006 - Add additional check conditions for BiosCmd 0x7.
ver 0.8.0.42:
00. Code base updated to CL#49631 and no update in fTPM version.
01. SWDEV-148450: [Vega10][SRIOV] Provide PSP service to program IH ring registers. New interface with Vfid.
02. DESPCSOC-1891: [S0i3 bring-up][RV] Modify RSMU security policy to 3.26 to allow SMU read-only access to MMHUB registers.
03. PLAT-29590: [RV] Power optimization of PSP FW in S0i2 state.
04. PLAT-31094: Add FwType checking in svc call for loading BIOS directory entries (PMU FW).
05. PLAT-31212: KVM Nwd fails to come up due to the failure of SYSHUB mapping of NIC config space.
ver 0.8.0.41:
00. Code base updated to CL#49458 and no update in fTPM version.
01. PLAT-30612: [RV] Fix bugs of the "Verify SYSHUB mapped address against sensitive areas."
02. PLAT-30264: [RV] Enforce FwType check for all binaries loaded in PSP BL.
03. SWDEV-149550: [RV] Brightness2 test fails with error "Back light optimization OFF failed".
ver 0.8.0.40:
00. Code base updated to CL#49323 and fTPM version updated to 3.15.0.4
01. PLAT-30195: PLAT-30196: [RV] Add FwType in Psp Header field to PSP binaries.
02. SWDEV-148450: [Vega10][SRIOV] Provide PSP service to program IH ring registers.
03. PLAT-26070: [RV] Review design and correctly fixed uCode load in CL#46664 and CL#49012.
04. PLAT-20554: [RV] PSP Boot Loader support for ABL FW Signing Key.
05. PLAT-29925: [fTPM] Fix security issues.
06. PLAT-30612: [RV] Verify SYSHUB mapped address against sensitive areas.
07. PLAT-30919: [VG20] Integrate VG20 signing function into sOS build chain.
08. SWDEV-149097: [RV][PlayReady] Added mechanism to populate version numbers of Non-PSP firmwares.
09. PLAT-29846: [RV] Additional changes - removed not required service call.
10. PLAT-30917: [RV] Set-up I2C3 channel clock to 100KHz for customer EC messages.
ver 0.8.0.3F:
00. Code base updated to CL#49179 and fTPM version updated to 3.14.0.4
01. PLAT-30019: [RV] System hangs after HDT debug unlock.
02. PLAT-29829: [RV2] Load RV2 MP2FW binary if ASIC is RV2.
03. PLAT-29842: [RV] PSP BootLoader permits execution of unsigned data.
04. PLAT-29685: [RV] ISP firmware loading on Raven.
05. PSP-3485: [RV] Add implementation of VirtToAxi() for shared memory buffers.
06. PLAT-26070: [RV]Correctly fixed this issue in CL#46664. DMCU FW load bug fixes + GFX Save Restore Loading sequence fix.
07. PLAT-30633: [Vega20] Bring-up activity, loaded PSP sOS up to SignOfLife update.
08. SWDEV-149081: [RV] Add FwType value to the PSP FW header.
09. PSP-3462: [RV] Fix a bug with saving Time Stamp over S3 cycling.
10. SWDEV-146166: [RV][PlayReady] Fix CCP Pass Through API.
11. [PlayReady]: Add ability for TA to use SRAM buffer.
12. DESPCSOC-1862: [AMD-TEE kernel] Fix intermittent AMD-TEE data abort.
13. PLAT-29842: Address security concirn regarding the fTPM uncompressed image could overwrite valuable data.
14. PLAT-29846: [RV] Potential PSP User code privilege escalation.
15. PLAT-28831: PLAT-28923: Implement correct UMC keys programming mechanism for RVx2 and Update Security policy for RVx2 with 10.2.3.26
16. PLAT-30130: [RV][fTPM] Device level HLK Test "TPM Auxaillary Test" failing.
ver 0.8.0.3E:
0. Code base updated to CL#48879 and no update in fTPM version.
1. PLAT-29836: PLAT-29837: PLAT-29384: [RV] Security fixes.
2. PLAT-30027: [RV] Workaround for KVM Nwd soft lock up issue found on customer board.
3. SWDEV-148447: [VG12] Clearing TMR buffer before loading FW and setup TMR fence only if in case of non-SRIOV.
ver 0.8.0.3D:
0. Code base updated to CL#48646 and fTPM version is updated to 3.13.0.4
1. PLAT-29750: [RV]Skip loading of MP2 FW if requested using PSP Entry 0xB.
2. PLAT-26822: [RV] Add support for Z490 promontory device connected behind PCIe switch.
3. SWDEV-146166: [RV][PlayReady] Extra System Driver services to support Transcription optimization.
4. PLAT-29498: [RV][fTPM]Fixes for issues reported by Coverity.
5. PLAT-29693: [RV][fTPM] TPM 2.0 EK Certificate tests fails on Raven.
6. DASH-485:[KVMOS] In case of crash, system does not reboots to normal OS. - updates after code review.
7. [VG12] fixes include setting TMR fences regardless of FW loading and correction in reading RLC SRIOV control register.
ver 0.8.0.3C:
0. Code base updated to CL#48568 and fTPM version is updated to 3.12.0.4
1. PLAT-28941: [RV] More updates to RV2 Deep Sleep settings.
2. PLAT-29493: [RV] PSP BL does not support only Level1 directory structure.
3. PLAT-29236: [RV] Add service call in BL for loading binary from BIOS entry (SPI-ROM) with attributes.
4. PSP-3480: [RV][fTPM] Add handling of S0i3 suspend/resume commands in ASD and fTPM drivers.
5. PSP-3482: [RV] Add DrvSys_CcpAesCtrEncrypt() implementation to SysDrv private APIs.
6. PSP-3479: [RV][S0i3] Save SDMA and DMCU FWs in SysDrv memory when it is loaded and reload on S0i3 exit.
7. PSP-3481: [RV][S0i3] Save/restore TMR register configurations in/from MP2 SRAM.
8. PSP-3474: [RV][S0i3] Identify system is resuming from S0i3 in PSP BL from FCH register.
9. PSP-3474: [RV][S0i3] Retrieve GPIOList from RAM1 and Turn on e-Display if required based on GPIO wake source list.
ver 0.8.0.3B:
00. Code base updated to CL#48444 and fTPM version is 3.11.0.4
01. PLAT-28931: BUG FIX for CL48394: Base SMN addresses of UMC channels were same for both channels and SMN addresses were passed instead of indices.
ver 0.8.0.3A: Not-Promoted by CQE team because of S4 resume issue and replaced by 0.8.0.3B
00. Code base updated to CL#48403 and fTPM version is updated to 3.11.0.4
01. PLAT-25293:[RV] Fix S3 hang when TSME is enabled.
02. PLAT-28931:[RV] Generate UMC keys separately for Ch0 and Ch1.
03. PSP-3476:[RV] Fix OP-TEE failures on secure parts caused by Panic() behavior.
04. DASH-485:[KVMOS] In case of crash, system does not reboots to normal OS.
05. PSP-3446:[RV][S0i3] Handler for BIOS cmd for power ON eDP wake source list.
06. PSP-3480:[RV][S0i3] Add handling of S0i3 suspend/resume commands in SysDrv.
07. PLAT-29165:[fTPM][RV] Non-volatile storage optimizations.
08. PLAT-29170:[fTPM][RV] NVRAM corruption handling.
09. [VG12] Adding illegal instructions fetch support for UVD/VCE.
10. [VG12] Add support for signing Vega12 binaries.
11. [VG12] Mode1 reset fixes so it is functional for both Vg10/Vg12.
12. [VG20] Add new ASIC's registers definitions.
ver 0.8.0.39:
00. Code base updated to CL#48208 and no change in fTPM binary.
01. PLAT-28979: Change RTM signature validation such that it is validating PEI+L1+L2 image rather than just PEI+L1.
02. PLAT-16177: System cannot startup with SD card attached.
03. PLAT-28941: RV2 Deep Sleep settings
04. PLAT-28939: Fix RV2 SysHub / MMHub TLB distribution. Fix gAsicType type mismatches.
05. PLAT-28905: Fix Cache clean/invalidate related issues and fix incorrectly passed BIOS dest address rather than AXI address.
06. PSP-3460: Create build target for VG20 in Trusted OS and SysDrv.
07. PSP-3467: Increase PSP Kernel code area by 4 KB. Also, apply workaround for VG12 time stamp issue.
08. PSP-3470: Add TA property to manifest file to indicate that TA doesn't need high performance.
09. PSP-3445: MP2 RAM1 memory management for PSP/ABL region.
10. PSP-3465: Add new SysDrv service for saving data to MP2 SRAM.
11. PSP-3471: [S0i3] Additional changes for MP2 memory management.
ver 0.8.0.38:
0. Code base updated to CL#48039 and no change in fTPM binary.
1. PLAT-28343: S3 UMC state info and In-line AES key is added to SUSPEND_DRAM and BL code clean up.
2. SWDEV-143897: VG10 - DMCU FW load failure.
3. PSP-3462: Power optimization of Trusted OS (assign DPM level for each thread). Change priority of PSP sign-of-life counter thread to LOW to avoid switching to DPM3 in idle state. Replace division of time-stamp value with multiply/shift to reduce code size.
4. PSP-3464: After sending EC message to I2C3, switch GPIO pins 19/20 back to SMBUS.
5. PSP-3458: Address Coverity issues in Trusted OS.
ver 0.8.0.37:
00. Code base updated to CL#47942 and fTPM binary is updated to 3.10.0.4
01. PLAT-28447: Field upgrade to fTPM version 3.F.0.4 fails.
02. PLAT-26766: System enters into recovery mode if more than 7 APCB binaries added into BIOS.
03. PLAT-28417: With unconditional unlock, GC HW IP does not get unlocked.
04. PLAT-28149: Reduce SMN timeout value to 0.1 sec for all HW IPs.
05. PLAT-24722: Fix a bug in C2P command 0x1B to lock DF register handling.
06. PSP-3436: Add changes to load & validate whitelisted binary and perform unconditional unlock based on serial numbers.
07. PLAT-28277: Allow loading of security policy to non-secure parts based on flag in PSP Entry 0xB.
08. PSP-3458: Address Coverity issues in Trusted OS.
09. Add Encryption to fTPM and TA FW binary signing process.
10. PLAT-28293: [RV2] MP2_SOFT_RESET_CTRL address is updated to RV2 spec registers.
11. PSP-3455: [AMD-TEE] Add Svc_IsTaLoaded() service call.
12. PSP-3447: Modify PSP Secure OS, restrict access of AGESA driver.
13. PSP-3454: AMD-TEE write-once persistent storage implementation.
14. Send a message to SMU containing shifted start of SMU DRAM ADDR for VG12.
15. SWDEV-142588: Changes to support frontdoor FW load in VG12 for UVD/VCE.
ver 0.8.0.36:
0. Code base updated to CL#47537 and no change in fTPM binary.
1. PLAT-27936: Fill status in Mailbox header before acknowledging START_KVM C2P command.
2. PLAT-28027: Support plugging of 32MB SPI-ROM though it does not support BIOS image of 32MB, PSP BL will still allow to map to 16MB.
3. PLAT-27796: Revert changes in PLAT-26632, which blocks customer system to boot.
4. PLAT-28149: Reduce SMN timeout value to 0.5 sec
5. [PSP 10 SysDrv]: performance optimization for handler of SMU command 0x09 (SMU_CMD_REPROG_GFXIP_SEC_SETTINGS).
6. Diffie Hellman OPTEE test fix.
7. PLAT-25732: [Trusted OS] Power optimization of SureStart solution.
ver 0.8.0.35:
0. Code base updated to CL#47537 and fTPM binary updated to 3.F.0.4.
1. PLAT-27378: OPTEE: Illegal memory access from TA succeeds - handles undefined exception.
2. PLAT-27177: Porting of 1.38 Errata and ProofSize Patch from Reference Codes to RV fTPM.
3. PLAT-27634: PSP NVRAM clearing request is occurred during reboot long-run.
ver 0.8.0.34:
0. Code base updated to CL#47394 and fTPM binary updated to 3.E.0.04.
1. PLAT-27075: Add MP0 revision ID to atag parameters to facilitate KVM OS to differentiate between Pinnacle and Raven.
2. SWDEV-136613: Increased max TA sessions to 32 for Gfx I/F.
3. PSP-3436: Submit skeleton of debug unlock whitelist.
4. PLAT-26131: RV2 LIVMIN feature. This changelist implemented the skeleton for LIVMIN feature.
5. PSP-3265: Updating PSP 10 Secure OS (add $PS1 cookie to the binary header).
6. PLAT-26803: Secure Part Authentication Issue (Frequency cannot be set above Fmax).
7. PLAT-27038: [RV] SPI ROM protection with small range.
8. PSP-3435: Address security concern of potential buffer overflow in KDF function.
9. PSP-3435: Fix bug - caused VG10 build not able to boot to Trusted OS due to some pending interrupt left by Boot Loader.
10. PLAT-27418: [fTPM] Remove simulation and debug flags.
ver 0.8.0.33:
0. Code base updated to CL#47194 and no change in fTPM binary.
1. PLAT-26789: Clean RV/VG PSP10 FW code from CZ support.
2. PLAT-26632: Match RV Post Codes to ZP.
3. PSP-3435: Modify SysDrv I/F to address security issues found by customer program review.
4. PLAT-27061: APOB HMAC validation optimization on S3 resume.
5. PLAT-27057: Do not set Bios Mbox interface to Ready state in BL.
6. PLAT-27060: Bug fix - incorrect type used when referencing external global variable.
ver 0.8.0.32:
0. Code base updated to CL#47003 and fTPM binary version updated to 3.D.0.4.
1. PLAT-26720: [fTPM & sys_drv] Handling SPI operation when SPI is busy (FPR, Async).
2. PLAT-21059: [fTPM] fTPM platform Spec Information incorrect.
3. PLAT-25297: Raven AM4 Knoll device athentication.
ver 0.8.0.31:
0. Code base updated to CL#46899 and no change in fTPM binary.
1. FEAT-11956: Fixes Raven1_2 unified branch for Vega build.
2. PLAT-26130: MP0 MGCG feature configuration for RV2.
3. PLAT-26126: RV Dibbler MCA_IPID[InsanceID] is not unique for each DF.
4. PLAT-26076: Configuring TMZ registers in PSPFW (BL & secureOS).
5. PLAT-25732: Implementation of SS3 - support for customer desktop systems which uses I2C3 controller instead of I2C1.
6. PLAT-25297: Raven AM4 Promontory device athentication.
7. PLAT-26368: MP0 not reporting version info in J2P_MBOX_1.
ver 0.8.0.30:
0. Code base updated to CL#46761 and fTPM binary version updated to 3.C.0.4.
1. PLAT-26071: VCN non-RSMU Sec Gasket enablement bug fix + code clean up.
2. PLAT-26065: Save/restore HSTI/PSB checking fuses result C2P registers through S3 suspend/resume.
3. PLAT-25865: KDF algorithm for RSA, ECC TPM Endorsement keys based on OTP in fTPM is not sync with KDS server implementation.
4. PLAT-25499: [PSP Recovery]Corrupting fTPM binary in SPI-ROM, causes hang in sOS and does not allow user to recover the system.
5. Code changes to support RV2 in same PSPFW binaries.
ver 0.8.0.2F:
0. Code base updated to CL#46667 and fTPM binary version updated to 3.B.0.4.
1. PLAT-25425: Fix CPU swap problem in case of swapping between different platforms ASICs.
2. PLAT-25732: Integrate SS3 I2C fix from release branch to staging.
3. PLAT-26008: Enable ACP Security Policy - Raven Security Policy version 10.0.2.3.2
4. PLAT-26010: DMCU FW loading enablement.
5. PLAT-25754: System hang 000D on AM4 ASIC on Myrtle Rev E board.
6. PLAT-23999: PSP Needs to Load MP2 Config file on boot.
7. PLAT-26070: DMCU FW load bug fixes + GFX Save Restore Loading sequence fix.
8. PLAT-23726: Unlock a Secure part causes SMU to hit double Excpetion.
ver 0.8.0.2E:
0. Code base updated to CL#46427 and no change in fTPM binary.
1. PLAT-25732: Put back the PSP DPM control: when Idle thread is scheduled set to DPM0, othervise to DPM3.
2. PLAT-25683: [RV-FP5] Post code will loop (0283-A5F3) after flash bios in OS.
ver 0.8.0.2D:
0. Code base updated to CL#46343 and no change in fTPM binary.
1. PLAT-25585: ACP FWV hang on S3 resume fix + Re-enable ACP FW loading
2. PLAT-25659: Customer Key Lock (CKL) not able to be fused.
ver 0.8.0.2C:
0. Code base updated to CL#46239 and fTPM version updated to 3.A.0.4
1. PLAT-25437: Support SS3 TA signed with Leaf Token signed with Sub-CA Token.
2. PLAT-25056: Support releasing x86 without secureOS for AFF tool (support BiosCmd 0x1A for fusing but conditionally compiled).
3. PLAT-24743: Provide SVC call for ABL to read SRTC value
4. PLAT-20830: Post code show 000d after changed silicon from Summit(Zeppelin) to Raven1
5. PSP-3432: Fix issue which is causing fTPM crash during init time in some scenarios.
ver 0.8.0.2B:
0. Code base updated to CL#46084 and no change in fTPM binary.
1. PLAT-25391: SS3 TA not able to load on secure ASIC.
2. PLAT-24965: Fix a bug in SMI request interface between PSP & BIOS: use three C2PMSG registers instead of two.
3. PSP-3432: Workaround for PSP clocks lowered to Deep Sleep due to WFI whie CCP is active.
4. PLAT-25285: Fix the wrong buffer size causing buffer overflow in PSS verification
5. PLAT-25058: [RV] Provide a new PSP service call to delay 1us.
6. PLAT-25396: Fix SMNIF_TLB_n segment map
ver 0.8.0.2A:
1. DASH-619: Enable KVM support for Tambourine boards.
2. PLAT-25006: Bug fix error code reporting when BIOS cannot be loaded.
3. PLAT-25048: Added more BL sequence updates in PSPFW_Status register after releasing x86.
4. Code base updated to CL#45879 and fTPM version updated to 3.9.0.4
ver 0.8.0.29:
01. SWDEV-131055: Fix VCN Re-init of illegal instr fetch registers - setup after cold reset is released.
02. PLAT-24780: Port SM CL#44244 bug fix: wrong order of Vendor ID and Model ID in the header structure.
03. PLAT-24133: SWDEV-131237 - The bug fix for the TMR physical address used in the TMR destroy function
04. SWDEV-131817: Enable the UVD/VCE runtime validation
05. PLAT-24646: Reflect the HSTISTATE_PSP_DEBUG_LOCK_ON bit in the C2PMSG_38 after debug unlock.
06. PLAT-24792: Separate parameters from ATAG structure to avoid open usage of these parameters in KVMOS.
07. PLAT-24611: PSB - Disable Secure Unlock not being enforced
08. PLAT-21614: Request SMU to raise MP0 DPM level and controlled by BIOS PSP Entry 0xB - bit 28
09. PLAT-24565: ABL request - enhance Svc_LoadBinary to support loading of APOB entry 0x63.
10. PLAT-24541: Allow ABL to use GFX IOMMU to program UMC registers - which is blocked by security policy.
11. PLAT-24605: PLAT-24822: Update Security Policy to Phase1 + PWR - equivalent to 0.8.2.26
12. PLAT-23449: Cannot use debug features on RV B0 on secure unlocking ASIC
13. PLAT-24722: Add RsmuLateSecurityPolicy to C2P mailbox Command 0x1B handling.
14. PLAT-22775: [RV-AM4] System hang at PC:AC94 after any CBS option changed with RMR1000A.0119
15. PLAT-23991: Provide secure unlock version number when system is unlocked.
16. PLAT-24826: Revert ACP FW loading to older mechanism
17. PLAT-24856:For security reason disable handling BIOS-2-PSP command 0x1A in the PSP Secure OS on Raven
18. Code base updated to CL45714 and fTPM version is 3.7.0.4
ver 0.8.0.27:
1. Update Security Policy to 10.0.2.3.1
2. Enable Save/Restore and setup illegal instruction fetch detection for VCN FW
3. PLAT-24260: Support Platform Secure Boot (PSB) - partial not validated fully
4. Bug fix - System not getting locked back on WarmReset with debug unlock request
5. PLAT-20396: Support Recovery Boot Loader and 2nd level PSP entries changes
6. Fixes and improvements in fTPM code and version updated to 3.7.0.4
7. Improvements and fixes for SS3
8. Bug fixes and improvements in AMDTEE OS
9. Code base updated to CL#45365
ver 0.8.0.26: (Urgent release)
1. SWDEV-127891: Bug fix is sOS when thread switching did not update driver's page table which causes execution of incorrect code.
2. Code base updated to CL#44916
ver 0.8.0.25:
1. KVM change - NetCardMmioBase, Frame Buffer and Bar 2 register addresses to 64 bit from 32 bit
2. Raven ACP FWV fixes
3. PLAT-20456: Support Boot from SPI-ROM
4. Fixes and improvements in fTPM code version updated to 3.6.0.4
5. Bug fixes and improvements in AMDTEE OS
6. Code base updated to CL#44882
ver 0.8.0.24:
1. PLAT-19057: Fix PSP ROM-SIG address on Raven FP5
2. PLAT-23009: [RV-FP5] System hang with PC:A5d3 when running S3 test on Win RS2 15063 x64 bit.
3. SWDEV-127538 - Put the VCN in the cold reset state to protect the VCN to run the un-validated FW by PSP.
4. Fix - request of debug unlock could not be processed after S3 resume
5. Programs RSMU Timeout enable and RSMU Inetrrupt for GC HW block when it is powered ON
6. Fixes and improvements in fTPM code, and version updated to 3.5.0.4
7. Code base updated to CL#44725
ver 0.8.0.23:
1. Do not access GCEA_SECURE_CTRL regiser in early boot, GC is power gated.
2. Work-around for 0xA5D3 seen on S3, disable waiting for GFX thread.
3. PLAT-23265 - System hangs at SMU value 17751 - SendMessageToPspRx
4. Code base updated to CL#44515
ver 0.8.0.22:
1. PLAT-19057: Patch to enable customer request to change PSP ROM-SIG address on Raven FP5
2. PLAT-23225: Check-in modified Security Policy 10.0.1.9
3. Code base updated to CL#44303
ver 0.8.0.21:
1. PLAT-22579: RV PSP BL to support 0x68 as APCB recovery copy
2. PLAT-23115: Fix NV Storage failure due to race condition between PSP and BIOS
3. Update TMR addressing for APU/dGPU
4. Fixes/improvements in fTPM
5. Bug fixes in AMDTEE OS
6. Code base updated to CL#44259
ver 0.8.0.20:
1. Bug fix in AMDTEE OS
2. Code base updated to CL#44093
ver 0.8.0.1F:
1. Bug fix in AMDTEE OS
2. Code base updated to CL#44005
ver 0.8.0.1E:
1. PLAT-19057: HP request to change PSP ROM-SIG address on Raven FP5 and beyond silicon design
2. PLAT-16373: Support compress type BIOS image
3. PLAT-19840: Workaround changes to enable HW_PG_EN for RV1
4. PLAT-20681: Unconditionally clear SMMLOCK bit for RV on BootDone cmd from BIOS
5. PLAT-19552: Do not load MP2 FW during S4 resume
6. PLAT-20592: New Secure Unlock sequence to fetch serial number from PSP FW
7. Enable fTPM on Raven
8. Enhancements and Bug fixes in AMDTEE OS
9. Code base updated to CL#43983
ver 0.8.0.1D:
1. PLAT-20399: Add Smm region information to MboxBiosCmdSmmInfo
2. Enable secure_unlock feature
3. PLAT-14743: Hanged at 0x00BD when LPC to serial out debugger is connected
4. Enhancements and Bug fixes in AMDTEE OS
5. Code base updated to CL#43462
ver 0.8.0.1C:
1. PLAT-20399: Add Smm region information to MboxBiosCmdSmmInfo
2. PLAT-14743: Hanged at 0x00BD when LPC to serial out debugger is connected
3. Enhancements and Bug fixes in AMDTEE OS
4. Code base updated to CL#43136
ver 0.8.0.1B:
1. Disable sanity check conditions on S3 suspend request from BIOS.
ver 0.8.0.1A:
1. PLAT-21079: SST.IOHC <--RSMU (90) HARD_RESETB = 0 (PLAT-19731).
2. PLAT-21080: SST::SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK = 0x3FF for both SST0 and SST1 (PLAT-19731)
3. PLAT-19840: All the PMM features are enabled in PSP Bootloader except for the problematic "Set HW_PG_EN for MP0CCP_REGS:Mp0CcpPg_Control"
4. Enhancements and Bug fixes in AMDTEE OS
5. Code base updated to CL#42823
ver 0.8.0.19:
1. PLAT-19620: Enable S4 reporting in Svc_GetBootMode call from ABL.
2. Enhancements and Bug fixes in AMDTEE OS
3. Code base updated to CL#42392
ver 0.8.0.18:
1. PLAT-15265: Set RSMU Timeout Value and Enable.
2. Added additional debug prints for intermittent issues.
3. Addressed multiple NCC security review concerns
4. Enhancements and Bug fixes in AMDTEE OS
5. Code base updated to CL#42150
ver 0.8.0.17:
1. PLAT-3265: Added core sequence of VMIN feature
2. PLAT-15125, PLAT-18616, 18426
3. FEAT-6163, 6203,6204, 6205, 6207, 7388. Enabled MP0 Power management feature
4. Addressed multiple NCC security review concerns
5. Enhancements and Bug fixes in AMDTEE OS
6. Code base updated to CL#41734
ver 0.8.0.16:
1. Workaround of Hang 0xD on Secure ASICs
2. PLAT-17552: SMU Double exception on S3-Resume with MP0 enabled
3. Ported Level 2 Directory support changes from PSP 3.1 to PSP 10
4. Enhancements and Bug fixes in AMDTEE OS
5. Code base updated to CL# 41115
ver 0.8.0.15:
1. Support of new SPI-ROM type
2. Handle START_KVM commands from BIOS
3. Support RV1 and RV2 in BL
4. Bug fixes
ver 0.8.0.14:
1. TMZ implementation
2. Changes for MCA programming
3. Support unsigned fw loading on non-secure part
4. Fix VBIOS mailbox handler for S3-resume
5. Bug fixes.
6. Code base update to CL#39714
ver 0.8.0.13:
1. Enabled AEB's for all IPs on Raven A0 asic only.
2. Code base update to CL#38988
ver 0.8.0.12:
1. PSP cycle of S3 suspend/resume can be successfully conducted
2. re-enable platform validate
3. update MP2 SRAM usage for fast S3 resume
4. fixes on AME-TEE for S3 resume
5. changes in PSP FW for Gfx interface
6. Code base update to CL#38714
ver 0.8.0.11:
1. Implement new SPI-ROM speed & mode detection mechanism and boost mechanism, allow FCH team to dynamically adjust SPI-ROM mode and speed to apply
2. Add support to load Diag PSP BL
3. Update MP0-MP1 message IDs
4. Fixes on Syshub mapping functionalites
5. Code base update to CL#38436
ver 0.8.0.10:
1. Enable Serial Port debugging in PSP Bootloader
2. Fix MP2 FW validation in case if the signature & token are not aligned
3. Disable MP0 to MP2 for S3 message until MP2 FW has the proper support
4. Code base update to CL#38259
ver 0.8.0.0F:
1. Enable S3 suspend resume sequence support in PSP Bootloader
2. Enable MBAT programming in S5 boot
3. Add rsmu HW workaround for rsmu sata HW bug.
4. Update service calls for ABL
5. Add additional fuse detection features in S5 boot
6. Enable PSP Diag Bootloader loading in entry 0x29
7. Code base update to CL#38084
ver 0.8.0.0E:
1. Enable PM LPC Gating Bits setting
2. Enable Disable Boot Timer setting
3. Enable SMU-PSP message communication
4. Fixes existing S2P attribute issues
5. Add the support of S5 cold and warm boot mode
6. Update svc call handlers
7. fix existing bugs
8. Code base update to CL#37784
ver 0.8.0.0D:
1. code base update to CL#37584
2. change the SPI-ROM signature address for Raven to 0x1C to accomodate combo BIOS requirement
3. fix MCA register programming
ver 0.8.0.0C:
1. code base update to CL#37071
ver 0.8.0.0B:
1. Added S3 save state to MP2 Sram.
2. Added secure os and application driver loading.
3. Added latest bugfixes from ZP branch.
ver 0.8.0.0A:
1. Added handling of BIOS commands.
2. Added copy MP2 FW to the MP2 SRAM start address
ver 0.8.0.09:
1. MP2 FW validation and loading.
2. I-cache disabled.
3. Add cache cleaning prior to submitting CCP command
ver 0.8.0.08
1. Removed any residual code paths from ZP.
2. integrated stability fixes from FW version 0.8.0.07_3
- Updated HW register usage.
- Fixed data abort at end of PSP Bootloader sequence.
- Temporarily removed write to VDCI2 register.
ver 0.8.0.07
1. Plat-2408 - Updated to latest HW register spec CL#570439
2. Plat-2408 - Synchronized with with latest bug fixes and updated from PSP ZP branch CL # 33697
ver 0.8.0.06
1. Plat-2408 - Update the version number to 0.8.0.6
2. Plat-2408 - Raven release X86 core, allow syshub to map 0 DRAM address
ver 0.8.0.05
1. Plat-2408: Plat-2408: update HW register files to RTL CL# 546297
2. Plat-2408: Plat-2408: update the CCP reserved field to zero.
3. Plat-2408 Integration from PSP 3.0 (Zeppelin) to PSP 10-RV (Raven) upto CL#32296
4. Plat-2408: update the MCA bank address list as per the confirmation from Simnow and HW team.
5. Plat-2408: remove the PSP and SMU MCA bank programming as requested/confirmation from Raven HW team.
6. Plat-2408: Two important changes to PSP FW: 1. update the MCA address for HW IPs to be programmed into Mbat table; 2. update the routing table field to zero
Note that due to unavailability of updated PSP BootRom and Simnow, there is no test coverage.
ver 0.8.0.04
1. Plat-2408: Internal test version
ver 0.8.0.03
1. Plat-2408: Internal test version
ver 0.8.0.02
1. Plat-2408: Fix the MCA addresses for Mbat tables for HW IPs
2. Plat-2408: Plat-2408: update to the new HW register files
3. Plat-2408: Fix the ccx instances issue.
ver 0.8.0.01
1. Plat-2408: Remove all MCM related codes unrelated to RV
2. Plat-2408: update the HW registers header files to use RV version
3. Plat-2408: update the HW registers header files to use RV version
4. Plat-2408: Change signing key to use RV signing key via KDS server
5. Plat-2408: Change the make file to generate the final PSP Bootloader in final production name, save extra effort to always change the file name when releasing PSP FW
6. Plat-2408: Change the make file to call new signing .xml file
7. Plat-2408: remove Diffie-Hellman key exchange since Raven does not have MCM configuration, no need to encrypt WAFL link between sockets
8. Plat-2408: disable the loading of HW IP configuration FW as per the request from Alex Cejkov since it is not ready from HW team
9. Code base branch from ZP up to CL#3908.

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0x00,General - Success
0x01,Generic Error Code
0x02,Generic Memory Error
0x03,Buffer Overflow
0x04,Invalid Parameter(s)
0x05,Invalid Data Length
0x06,Data Alignment Error
0x07,Null Pointer Error
0x08,Unsupported Function
0x09,Invalid Service ID
0x0A,Invalid Address
0x0B,Out of Resource Error
0x0C,Timeout
0x0D,Data Abort exception
0x0E,Prefetch Abort exception
0x0F,Out of boundary condition reached
0x10,Data corruption
0x11,Unknown ASIC type
0x13,Failure in retrieving firmware header
0x14,Key size not supported
0x15,Entry not found at requested location
0x18,Generic FW Validation error
0x19,RSA operation fail - bootloader
0x1A,CCP Passthrough operation failed
0x1B,AES operation failed
0x1D,CCP state restore failed
0x1E,SHA256 operation failed
0x1F,ZLib Decompression operation fail
0x20,HMAC-SHA256 operation fail - internal status
0x21,Booted from boot source not recognized by PSP
0x22,PSP directory entry not found
0x23,PSP failed to set the write enable latch
0x24,PSP timed out because spirom took too long
0x25,General - Hmac validation failed
0x26,Security_Policy binary does not match to ASIC
0x2C,Valid boot mode wasn't detected
0x2D,Unconditional unlock based on serial numbers failed
0x35,No physical x86 cores were found on die
0x37,SYSHUB mapping memory target type is not supported
0x38,Attempt to unmap permanently mapped TLB to PSP secure region
0x39,Unable to map an SMN address to AXI space
0x3A,Unable to map a SYSHUB address to AXI space
0x3E,Fuse info on all dies don't match
0x3F,PSP sent message to SMU; SMU reported an error
0x46,validation of the PSP SRAM image failed on HMAC compare
0x49,Error in Validate and Loading AGESA APOB SVC call
0x4C,Secure unlock error
0x60,Error with applying security gasket
0x62,Reading fuse failed
0x63,The BIOS OEM public key of the BIOS was revoked for this platform
0x64,Fuse sense operation timed out
0x65,Fuse burn sequence/operation timed out waiting for burn done
0x66,Fuse burn sequence/operation timed out waiting for burn done
0x67,Fuse invalid operation
0x68,Fuse burn sequence/operation failed due to internal SOC error
0x69,AGESA driver binary size is exceeded limit allocated in DRAM, need to increase limit
0x6A,The Diag Bootloader is not present in SPI-ROM
0x6B,Failed to load PSP Diag BL
0x6C,Failed to verify CS_SEED
0x6D,Failed to verify CS_SEED, BootRom portion
0x6E,Failed to verify CS_SEED, Lower portion
0x70,PSP level 2 directory not match expected value.
0x71,BIOS level 2 directory not match expected value.
0x72,FCH programming error
0x73,Failed while disabling boot timer
0x74,Failure in mapping syshub with inline AES
0x76,Debug unlock disabled by fuses
0x77,Missing binary at PSP Entry 0x9 in SPI-ROM
0x78,Programming RSMU timeout failed
0x79,Missing binary at PSP Entry 0x13 in SPI-ROM
0x80,fTPM binary size exceeds limit allocated in Private DRAM, need to increase the limit
0x81,Invalid key usage flag
0x82,Bootloader failed to find OEM signature
0x83,Error copying BIOS to DRAM
0x84,Error validating BIOS image signature
0x85,The validation of the OEM public key token failed
0x86,The BIOS binding to the fused vendor/model id failed
0x87,Bootloader detects BIOS request boot from SPI-ROM, which is unsupported for PSB.
0x88,Reset image not found
0x91,FW type mismatch between the requested FW type and the FW type embedded in the FW binary header
0x9F,The maximum allowable error post code
0xA0,Bootloader successfully entered C Main
0xA2,HMAC key successfully derived
0xA3,Master got Boot Mode and sent boot mode to all slaves
0xA4,SpiRom successfully initialized
0xA5,BIOS Directory successfully read from SPI to SRAM
0xA6,Early unlock check
0xA8,Inline-AES key programming is done
0xAB,Bootloader successfully programmed MBAT table
0xAC,Bootloader successfully configured security gasket
0xAD,Bootloader successfully loaded SMU FW
0xAE,BL_SUCCESS_WAIT_SMU_INTERRUPT
0xAF,Bootloader successfully loaded MP2 FW
0xB0,Bootloader loaded Agesa0 from SpiRom
0xB1,AGESA phase has completed
0xB2,Indicates security policy loaded in DRAM from SPI-ROM
0xB3,SMU FW Successfully loaded to SMU Secure DRAM
0xB4,MP2 FW not loaded on S4 resume as requested by MP2 team
0xB6,UMC Keys generated and programmed
0xB7,Inline AES key wrapper stored in DRAM
0xB8,Completed FW Validation step
0xBC,BIOS load process fully complete
0xBD,Bootloader successfully release x86
0xC1,Successfully entered WarmBootResume()
0xD5,Successfully load Diag Bootloader into DRAM
0xD6,Successfully verified CS-SEED
0xD7,Entered recovery mode due to failure in fw validation of any component binary
0xD8,Entered idle loop defined for special bootloader versions
0xD9,SendMessage to SMUFW successful
0xE0,MP2 Block is disabled in MP2_RSMU_FUSESTRAPS or soft fuse in PSP entry 0xB
0xE1,Updated only PSPFW Status when enetered in BL
0xE2,Updated only PSPFW Status when FCH programmed
0xE3,Updated only PSPFW Status when boot timer disabled
0xE4,Updated only PSPFW Status when derived and programmed syshub inline AES
0xE5,Updated only PSPFW Status when enabled logging
0xE6,Updated only PSPFW Status when RSMU timeout enabled registers programmed
0xE7,Updated only PSPFW Status when SST reset registers programmed
0xE8,Updated only PSPFW Status when passed SS3 loading
0xE9,Updated only PSPFW Status when passed fTPM loading
0xEA,Updated only PSPFW Status when passed loading sys_drv
0xEB,Updated only PSPFW Status when passed loading secure OS
0xEC,Updated only PSPFW Status when passed validation of S3 suspend data on resume
0xED,Updated only PSPFW Status when it is about to transfer control to secureOS
0xF1,PSP BL identified resuming from S0i3
0xF2,PSP BL identified resuming from S3
0xF3,PSP BL identified resuming from S4
0xF4,PSP BL identified previous reset S5 - Cold boot
0xF5,PSP BL identified previious reset S5 - Warm boot
0xFF,Bootloader sequence finished
Can't render this file because it has a wrong number of fields in line 56.

BIN
picasso/PSP/PspBootLoader_prod_RV.sbin Normal file
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picasso/PSP/PspRecoveryBootLoader_prod_RV.sbin Normal file
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picasso/PSP/RavenSecureDebug_PublicKey.bin Normal file
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BIN
picasso/PSP/RtmPubSignedRV.key Normal file
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@ -0,0 +1,570 @@
+---------------------------------------+
| SMU Firmware Release Notes - RAVEN2X |
+---------------------------------------+
+---------------------------+
| Version 37.27.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 15/03/19
|
| * Changelist
| - DXIO FW version 31.425
| - [PMFW-1300] [NEW] Publsih BIOS/TEST messages to report overclocking capability
| - [PLAT-43459] [ETB] GFX driver is not loaded after iGPU overclock in BIOS setup
| - [PMFW-1230] [NEW] Add a PCD option to change AclkDpm0 from 200MHz to 400MHz
| - [PMFW-1313] [OPT] MP0CLK DS enable only for DC mode
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.26.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 07/03/19
|
| * Changelist
| - DXIO FW version. 31.425
| - [PMFW-1263] [WKA] Discard CGPG enable if disable CGPG message is received during the delay
| - [PLAT-43239] [WKA] R3-3200U Flavor 2 Processor USB 2.0 Device Recognized again after Safely removed by Windows Icon
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.25.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 01/03/19
|
| * Changelist
| - DXIO FW version. 31.425
| - [PLAT-41548] [ETB] FClk and UClk actual frequency ratio mismatch
| - [PMFW-1114] [IMP] Rv2 Fw needs to be updated to v027 Sw document sync
| - [PMFW-1213] [NEW] Add SMU get message for current CCLK Fmax
| - [PMFW-1215] [ETB] Rounding min/max GFXCLK return values to neareset 10s
| - [PMFW-1216] [ETB] Rounding min/max CCLK return values to the nearest 10s
| - [PMFW-1221] [IMP] System show BSOD 0xEA when play video with Miracast connected at DC mode
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.24.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 28/01/19
|
| * Changelist
| - DXIO FW version. 31.425
| - [PMFW-933] [IMP] Reallocate space from scratch section to .isr_data section
| - [PLAT-41596] [IMP] Publish OC messages to BIOS port
| - [PMFW-905] [IMP] System hang up when ping AP address for overnight (update)
| - [PMFW-909] [IMP] FUSE/Default Limits info of Power and Current required for Ryzen Master
| - [PMFW-961] [IMP] System hang when resume from S3 or press warm reset with 48MHz TMDP refclock off
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.23.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 22/01/19
|
| * Changelist
| - DXIO FW version. 31.425
| - [PMFW-728] [OPT] Re-allocate .datatables space to .text section
| - [PMFW-701] [IMP] RV2 in PCO AM4: SMU Test Messages Required for Ryzen Master
| - [PMFW-726] [IMP] Enable continues data calculation when OC mode is enabled
| - [PLAT-41021] [IMP] Add fuse check for overclocking support
| - [PMFW-759] [UTB] Clean up debug_release file list for packaging
| - [PLAT-41396] [WKA] System doesn't update the freq of the SOC to 400 MHz after several times Prochot trigger event
| - [PMFW-905] [IMP] System hang up when ping AP address for overnight
| - [PMFW-907] [IMP] SVI2 resource protection missing
| - [PMFW-908] [IMP] CC6 Filter Gets Enabled on DC to AC Switch
| - [PMFW-911] [IMP] Bypass saving and restoring CAC weights for telemetry based products
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.22.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 07/01/19
|
| * Changelist
| - DXIO FW version. 31.423
| - [PLAT-40266] [WKA] Move PCTL0_MISC programming to SMU for secure policy update
| - [PMFW-699] [IMP] Raven2x FP5: Bypass Precision Boost Overdrive (PBO) Implementation
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.21.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 18/12/18
|
| * Changelist
| - DXIO FW version. 31.422
| - [PMFW-599] [IMP] PSI0 Workaround Code Cleanup
| - [PMFW-600] [IMP] Put PeAPM Code in EXT_SECTION
| - [PLAT-39838] [IMP] Add USB31 OVERCURRENT_MAP_1_CNTR0
| - [PMFW-623] [NEW] Add Managed Overclocking
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.20.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 10/12/18
|
| * Changelist
| - DXIO FW version. 31.419
| - [PLAT-39615] [WKA] Found intermittent FPR device YB issue when resume from S0i3 (winbug 156508)
| - [PMFW-594] [IMP] STT Power Floor
| - [PMFW-595] [IMP] STT gain control
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.19.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 21/11/18
|
| * Changelist
| - DXIO FW version. 31.419
| - [PLAT-38939] [ETB] Check MP2_FIRMWARE_FLAGS for MP2 handshake
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.18.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 08/11/18
|
| * Changelist
| - DXIO FW version. 31.419
| - [PMFW-408] [IMP] Apply SMS repair for both FP5 and AM4
| - [PMFW-415] [IMP] Port PSI0 changes from PCO to RV2
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.17.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 06/11/18
|
| * Changelist
| - DXIO FW version. 0.332
| - [PMFW-329] [UTB] Data structure is not DWORD aligned
| - [PMFW-314] [IMP] Fix SMU success monitor code for GFXOFF and CPUOFF
| - [PMFW-370] [IMP] Resource issue with GfxOff Entry during Gfx Dpm Clk Change
| - [PMFW-387] [WKA] RV2 USB PHY TX_VBOOST setting
| - [PMFW-393] [IMP] Move some Log routines to EXT_SECTION
| - [PLAT-37199] [IMP] Disable CC6 Filter for DC mode
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.16.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 12/10/18
|
| * Changelist
| - DXIO FW version. 0.332
| - [PLAT-36333] [NEW] DisBypTgtDnDLowPower Settings in LP4 Mode
| - [PMFW-260] [IMP] Disable gfxoff race condition
| - [PMFW-261] [IMP] diff in PCO vs RV2 ppsmc headers
| - [PLAT-36710] [ETB] BSOD 0xEA and SMU hang at ChangeGfxDldoPlaneStateFromBypassToOn when running reboot and S4
| - [PMFW-303] [IMP] Move DV functions to EXT_SECTION to save TEXT space
| - [PLAT-31975] [WKA] Add MsgId handshake between RLC-MP1 to avoid mismatch in response register
| - [PMFW-294] [IMP] minimize no-abort vs nbif doorbell fence enable for gfxoff
| - [PMFW-309] [WKA] Add a Dummy Vid Change to Ensure PSI0 Assertion / Deassertion
| - [PMFW-310] [WKA] Sequence change for RLC safe mode in disabling GfxCGPG to mitigate deadlock
| - [PMFW-276] [IMP] RV2 CCLK DPM P-Gain for AC/FS-3D/VR change
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.15.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 04/09/18
|
| * Changelist
| - DXIO FW version. 0.332
| - [PMFW-162] [UTB] Set DisBypTgtDnDLowPower Correction for D4 vs LPD4
| - [SMURVN2-90] [WKA] High temp failure - turned off dldo chopper recovery, dldo calibrate sequence to ON to BYPASS to OFF, removed MAFDD calibration changes
| - [PMFW-199] [ETB] Potential race condition for CGPG power status update
| - [PLAT-32828] [IMP] Force GFXOFF entry sequence for iGPU disabled case
| - [PLAT-33583] [IMP] Add register override for USB20 PHY 0 Lane 4/5 param 0 and 1
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.14.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 21/08/18
|
| * Changelist
| - DXIO FW version. 0.332
| - [FEAT-23122] [IMP] Support memory clock up to 2000MHz and add 33MHz stepping support
| - [PMFW-114] [IMP] Add MP0_GFX_DISABLE to BIOS message 0x51
| - [PMFW-137] [IMP] Add CalculateIOPhyDataDis flag to BIOS table
| - [PMFW-153] [IMP] Add a Driver Message to Force GFX Content Save for GFXOFF
| - [PLAT-30866] [IMP] SHUBCLK Deep Sleep doesn't work
| - [PLAT-29360] [WKA] DL-6950 KGD will random renumerate on the USB3.1 USB port
| - [PMFW-160] [IMP] Manipulate power limit by a percentage
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.13.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 01/08/18
|
| * Changelist
| - DXIO FW version. 0.332
| - [PMFW-73] CCLK Change DfCstate Disable Optimization
| - [PLAT-33665] [IMP] Updated to allow PLL4 only to turn off if not in use
| - [SMURVN2-90] [WKA] High temperature failure change is reverted
| - [PMFW-80] [NEW] Modify BIOS message OPN_SPARE for dual source
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.12.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 20/07/18
|
| * Changelist
| - DXIO FW version. 0.332
| - [FEAT-22858] [OPT] Revert FP5 Fan Controller to RV1 Settings
| - [SMURVN2-79] [IMP] PSI0 workaround for VR going to two phases with any voltage increase
| - [SMURVN2-81] [NEW] Add delay and cancel options to SetGfxCGPG message
| - [SMURVN2-82] [UTB] DispClk entering/exiting the bypass mode
| - [PLAT-33665] [IMP] Allows PLL4 and PLL0 to be turned off if not in use, put slice into REFCLK if DFS slice is not in bypass and did is 0, except for GFxCLK
| - [SMURVN2-83] [ETB] Fix CState Residency Miscalculation with CPUOff
| - [SMURVN2-84] [IMP] Check CstateBoost Entry Condition on CPUOFF Exit
| - [SMURVN2-85] [IMP] Power off TMON in VDDOFF
| - [SMURVN2-86] [IMP] Implement DLDO WLB RV1 fix
| - [SMURVN2-87] [IMP] Enter GfxOff if GfxOffEnable message comes in after CgpgPwrDown
| - [SMURVN2-88] [IMP] Remove Gfx DLDO register programming from VddOff-GfxOff exit
| - [SMURVN2-89] [NEW] Add a message to read OPN_OPN_SPARE fuse for BIOS
| - [SMURVN2-90] [WKA] High temperature failure
| - [SMURVN2-80] [IMP] Update RV2 AC Offset for all AM4 package cases
| - [PMFW-21] Clear PMREG_INITPKG1[softrepair] on CpuOff exit
| - [PLAT-34238] [ETB] RV2 AM4 fail to shutdown - Skip checking MP2 responese register if MP2 is disabled in fuse
| - [PMFW-35] Whisper Mode add PSP stall request
| - [PMFW-37] VddOff exit memory repair not needed for FP5
| - [PMFW-38] Enable ATC for Picasso/Winston
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.11.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 29/05/18
|
| * Changelist
| - DXIO FW version. 0.332
| - [SMURVN2-71] [IMP] Enable ACPI MP2 Messages
| - [SMURVN2-72] [ETB] SOC voltage not updating immediately
| - [SMURVN2-73] [ETB] System hangs when tried to OC by 25Mhz
| - [SMURVN2-74] [IMP] Updates to FP5 FIT limits and new CONFIG OPN
| - [SMURVN2-75] [IMP] Implement Softmax and Hardmin messages for stable Pstate support
| - [SMURVN2-76] [IMP] SOFTMIN/SOFTMAX CLK message
| - [PLAT-30559] [WKA] Disable DF Cstate before turn off PLL to workaround RV2 CLK PLL power down issue
| - [SMURVN2-77] [UTB] Fix for GetSustainedPowerAndThmLimit message
| - [PLAT-30862] [UTB] SMNCLK Deep Sleep doesn't work
| - [PLAT-31572] [IMP] Enable XGBE PG when XGBE is disabled
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.10.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 13/04/18
|
| * Changelist
| - DXIO FW version. 0.332
| - [SMURVN2-58] [IMP] Update AM4 65W system config limits
| - [SMURVN2-59] [IMP] RV AM4 LCLK DPM optimization
| - [SMURVN2-60] [WKA] Sound doesn't output from HDMI monitor if boot into OS with DC mode
| - [SMURVN2-61] [WKA] Import RV1x fixes [PLAT-28597] and [PLAT-27197]
| - [SMURVN2-62] [OPT] RV AM4 CCLK DPM Busy Setpoint and P-Gain optimization AC/FS3D/VR
| - [SMURVN2-63] [OPT] AM4 CCLK DPM VIDEO Mode BUSY_SETPOINT
| - [SMURVN2-64] [OPT] Raven AM4 CCLK DPM Optimization (Full Screen 3D & VR)
| - [SMURVN2-65] [IMP] Fix Core IddMax Shows 0 on Active Cores
| - [SMURVN2-66] [IMP] Report 100% CState Boost Residency when NumEnabledCores <= CStateBoostActiveCoreThresh
| - [PLAT-30296] [PLAT-30383] [IMP] Add SizeFWSigned and FWType into SMU Header
| - [SMURVN-727] [BUG] Block BIOS DisableSmuFeature Message on secure parts
| - [SMURVN2-67] [IMP] Remove DfCstateExitDisable from S0i2
| - [SMURVN2-70] [WKA] Add Epyc/ZP Reset Bug Workaround to RV2x (PLAT-24972)
| - [FEAT-22570] [OPT] FP5 Fan Controller Updates
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.9.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 23/03/18
|
| * Changelist
| - DXIO FW version. 0.332
| - [PLAT-29635] [IMP] SMU USB Firmware programming for LLUCTL and GRXTHRCFG
| - [SMURVN2-48] [UTB] Resource protect DispClk change.
| - [SMURVN2-49] [IMP] Fix system hang issue when OS tries to boot with PLL_POWER_DOWN disabled.
| - [SMURVN2-50] [IMP] Increase precision for voltages in AGM.
| - [SMURVN2-51] Fixed issue GPU0 PLL not powered down after S3 resume.
| - [SMURVN2-52] [UTB] Correct max Gfx CU count
| - [SMURVN2-53] [IMP] Set VDDP_DDR voltage to 0.7v during S0i2
| - [SMURVN2-55] [IMP] RV AM4 FIT cntrl error coeff optimization and GFX FIT throttler active on VDD rail.
| - [SMURVN2-56] [OPT] Handle PROCHOT disable within LN2 message if already in OC.
| - [SMURVN2-57] [OPT] FP5 FIT Throttler Floor frequency.
| - [PLAT-29580] [IMP] Enable FCH RSMU Clock Gating
| - [PLAT-28169] [IMP] MP1 clk deep sleep enable when cpu idle
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.8.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 06/03/18
|
| * Changelist
| - DXIO FW version. 0.332
| - [PLAT-29426] [IMP] Remove the settings of MMHUB_DS.RAVEN2x.ini from SMU FW
| - [SMURVN2-45] [IMP] Add message response to ACP's Dram access messages
| - [PLAT-29479] [UTB] System boot up hung AF70 with iES1 sample
| - [SMURVN2-46] [UTB] Use GfxContextSaved flag in SaveGfxMicrocodes() instead of ExitAfterColdBoot
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.7.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 27/02/18
|
| * Changelist
| - DXIO FW version. 0.332
| - [SMURVN2-40] [IMP] Update RV2 AC offsets for ES1 sample
| - [SMURVN2-41] [IMP] Remove Ax Bx dependency
| - [SMURVN2-42] [IMP] Remove SVI2_CONTROL resource from RegisterSvi2Voltage()
| - [PLAT-28413] [NEW] Enable MMHUB PowerGating - SMU to program all PCTL settings (Improved)
| - [PLAT-28396] [NEW] USB controller hung when boot to Win10 desktop if any USB3.0 device attached
| - [SMURVN2-43] [IMP] Add delays in U0-in-D3 routine to avoid device hang during shut down
| - [PLAT-28391] [WKA] RV2 can't break into PDM mode after CPUOFF exit
| - [SMURVN2-44] [NEW] Enable CstateBoost
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.6.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 09/02/18
|
| * Changelist
| - DXIO FW version. 0.332
| - [PLAT-28439] [ETB] AGM reported GFX/SOC temperature are all zero
| - [SMURVN2-37] [IMP] Conditionalize core specific code
| - [PLAT-28413] [UTB] Enable MMHUB PowerGating - SMU to program all PCTL ini Settings_RV2x
| - [SMURVN2-38] [IMP] Move some code to EXT_SECTION to open up space in TEXT
| - [SMURVN2-35] [OPT] Update RV2 RM Setting to 0x3C
| - [SMURVN2-39] [IMP] MP1_PUB_SCRATCH0 must show SMU FW version
| - [SMURVN2-36] [OPT] Update GFX DLDO REG30
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.5.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 22/01/18
|
| * Changelist
| - DXIO FW version. 0.332
| - [PLAT-28158] [NEW] System Remains in FMIN 400 after ~few minutes of cold rest (Telemetry planes are swapped in RV2x)
| - [SMURVN2-34] [OPT] Update RV2 AC Offsets
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.4.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 16/01/18
|
| * Changelist
| - DXIO FW version. 0.328
| - Synced up to RV1 latest code around up to Jan 8, 2018.
| - Updated USB according to latest USB SW requirement.doc
| - [PLAT-28083] [NEW] BIOSSMC_MSG_SetupUSB31ControllerTrap message setup trap for USBC0 only
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.3.0 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 11/01/18
|
| * Changelist
| - DXIO FW version. 0.328
| - Corrected fclk fcstate setting for case switch from BYPASS to DFS.
| - bypass MP2 reg access in ACPI (workaround)
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.2.9 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 11/12/17
|
| * Changelist
| - Fixed accessing CLK1_CLK_PWR_MGMT_CONTROL register (0x5c14c) during initialization.
| - Fixed accessing PCIe instance 6 and 7, since RV2 has only 5 PCIe instances.
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.2.8 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 29/11/17
|
| * Changelist
| - Packed ucode.l0/1/2/3.dat and ucode.h0/1/2/3.dat in release package.
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.2.7 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 10/11/17
|
| * Changelist
| - Updated DXIO FW to v296 (CL3074120).
| - Fixed clk reset sequence during warn reset.
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.2.6 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 21/09/17
|
| * Changelist
| - Updated S0I2, WM and LIVMIN precondition.
| - Updated LIVMIN sequence with NBIO interlocked when disabling FCH arbiter
| - Updated LIVMIN sequence for LPDDR4 when setup ConvertD2ToPhyLP3 bit
| - Added test messages to set LPDDR4 retraining interval and allow timeout value
| - Added LivMINVid and LinMinEnable fuse
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.2.5 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 29/08/17
|
| * Changelist
| - Integrated latest RV1 code, up to August 28, 2017. Quite a lot of changes.
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.2.4 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 14/08/17
|
| * Changelist
| - Corrected an issue of accessing RSMU generic register. (Created release 37.2.3 in between)
| - Added LPDDR4 fastsim option for emulation
| - Updated LPDDR4 memory state
| - Updated GFX_DLDO_REG30 default value and gfxoff data save/restore
| - Generated ucore0.hbin and ucore1.hbin which added extra 256 bytes header on top of MP1 FW
| - Added 2 test messages for getting LPDDR4 retraining status.
| - Fixed a bug in DF Pstate change procedure.
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.2.3 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 05/05/17
|
| * Changelist
| - Fixed accessing RSMU_MGCG_CONTROL_GENERIC register cause access Violation on Address 0x01000228
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.2.2 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 27/04/17
|
| * Changelist
| - Integrated changes from RV1x up to CL2773697
| - Updated USB related function to new IP. USB watermark setting for LPDDR4 retraining is still outstanding.
| - Updated UMC related register settings for LivMin and LPDDR4 retraining.
| - Fixed pmfw_fastsim.sv to be synced with pmfw_fastsim.h and scratch_info.h in RV2. We need to variantize pmfw_fastsim.sv for FF and RV2 in the future.
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.2.1 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 31/03/17
|
| * Features enabled
| - LPDDR4 retraining (preliminary)
| - RLC PACE (preliminary)
|
| * Changelist
| - Integrated changes from RV1x up to CL2726404
| - Included preliminary version of LPDDR4 retraining. Handling ZQCAL and USB watermark during
| memory retraining is still outstanding.
| - Included preliminary version of RLC PACE feature
| - Code update for clocks change in RV2, include FCLK change, 2 slices of CLKB/CLKC and 2 DROOP detectors only.
| - Minor code update for 2 cores only (core 1 and core 3)
|
+-----------------------------------------------------------------------------------------------------------
+---------------------------+
| Version 37.1.1 |
+---------------------------+-------------------------------------------------------------------------------
| * Date (dd/mm/yy)
| 28/02/17
|
| * Features enabled
| - Long Idle vMIN
|
| * Changelist
| - Integrated base code from RV1 and compiled them under RV2 environment.
| - Implemented preliminary version of Long Idle vMIN feature. For LPDDR4 system,
| one caveat is that ConvertD2toPhyLp3 bit in UMC has not been set before entering LIVMIN.
| - Gated off unused/bypassed DFS slices.
|
+-----------------------------------------------------------------------------------------------------------

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/*****************************************************************************
*
* Copyright 2016 - 2018 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
*
* AMD is granting you permission to use this software and documentation (if
* any) (collectively, the "Materials") pursuant to the terms and conditions of
* the Software License Agreement included with the Materials. If you do not
* have a copy of the Software License Agreement, contact your AMD
* representative for a copy.
*
* You agree that you will not reverse engineer or decompile the Materials, in
* whole or in part, except as allowed by applicable law.
*
* WARRANTY DISCLAIMER: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF
* ANY KIND. AMD DISCLAIMS ALL WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY,
* INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE, NON-INFRINGEMENT, THAT THE
* MATERIALS WILL RUN UNINTERRUPTED OR ERROR-FREE OR WARRANTIES ARISING FROM
* CUSTOM OF TRADE OR COURSE OF USAGE. THE ENTIRE RISK ASSOCIATED WITH THE USE
* OF THE MATERIAL IS ASSUMED BY YOU. Some jurisdictions do not allow the
* exclusion of implied warranties, so the above exclusion may not apply to
* You.
*
* LIMITATION OF LIABILITY AND INDEMNIFICATION: AMD AND ITS LICENSORS WILL
* NOT, UNDER ANY CIRCUMSTANCES BE LIABLE TO YOU FOR ANY PUNITIVE, DIRECT,
* INCIDENTAL, INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES ARISING FROM USE OF
* THE MATERIALS OR THIS AGREEMENT EVEN IF AMD AND ITS LICENSORS HAVE BEEN
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. In no event shall AMD's total
* liability to You for all damages, losses, and causes of action (whether in
* contract, tort (including negligence) or otherwise) exceed the amount of
* $100 USD. You agree to defend, indemnify and hold harmless AMD and its
* licensors, and any of their directors, officers, employees, affiliates or
* agents from and against any and all loss, damage, liability and other
* expenses (including reasonable attorneys' fees), resulting from Your use of
* the Materials or violation of the terms and conditions of this Agreement.
*
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
* subject to the restrictions as set forth in FAR 52.227-14 and
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
* Government constitutes acknowledgment of AMD's proprietary rights in them.
*
* EXPORT RESTRICTIONS: The Materials may be subject to export restrictions as
* stated in the Software License Agreement.
*******************************************************************************
*/
#ifndef _BL_ERRORCODES_H_
#define _BL_ERRORCODES_H_
// Bootloader Return Codes, Error only (0x00 through 0x9F)
typedef enum BL_RETCODE_T
{
BL_OK = 0x00, // General - Success
BL_ERR_GENERIC = 0x01, // Generic Error Code
BL_ERR_MEMORY = 0x02, // Generic Memory Error
BL_ERR_BUFFER_OVERFLOW = 0x03, // Buffer Overflow
BL_ERR_INVALID_PARAMETER = 0x04, // Invalid Parameter(s)
BL_ERR_DATA_LENGTH = 0x05, // Invalid Data Length
BL_ERR_DATA_ALIGNMENT = 0x06, // Data Alignment Error
BL_ERR_NULL_PTR = 0x07, // Null Pointer Error
BL_ERR_FUNCTION_NOT_SUPPORTED = 0x08, // Unsupported Function
BL_ERR_INVALID_SERVICE_ID = 0x09, // Invalid Service ID
BL_ERR_INVALID_ADDRESS = 0x0A, // Invalid Address
BL_ERR_OUT_OF_RESOURCES = 0x0B, // Out of Resource Error
BL_ERR_TIMEOUT = 0x0C, // Timeout
BL_ERR_DATA_ABORT = 0x0D, // data abort exception
BL_ERR_PREFETCH_ABORT = 0x0E, // prefetch abort exception
BL_ERR_BOUNDARY_CHECK = 0x0F, // Out of Boundary Condition Reached
BL_ERR_DATA_CORRUPTION = 0x10, // Data corruption
BL_ERR_INVALID_COMMAND = 0x11, // Invalid command
BL_ERR_INCORRECT_PACKAGE_TYPE = 0x12, // The package type provided by BR is incorrect
BL_ERR_GET_FW_HEADER = 0x13, // Failed to retrieve FW header during FW validation
BL_ERR_KEY_SIZE = 0x14, // Key size not supported
BL_ERR_AGESA0 = 0x15, // Agesa0 verification error
BL_ERR_SMUFW = 0x16, // SMU FW verification error
BL_ERR_OEMSIGNING = 0x17, // OEM SINGING KEY verification error
BL_ERR_FWVALIDATION = 0x18, // Generic FW Validation error
BL_ERR_CCP_RSA = 0x19, // RSA operation fail - bootloader
BL_ERR_CCP_PASSTHR = 0x1A, // CCP Passthrough operation failed - internal status
BL_ERR_CCP_AES = 0x1B, // AES operation fail
BL_ERR_STATE_SAVE = 0x1C, // CCP state save failed
BL_ERR_STATE_RESTORE = 0x1D, // CCP state restore failed
BL_ERR_SHA256 = 0x1E, // SHA256 operation fail - internal status
BL_ERR_ZLIB = 0x1F, // ZLib Decompression operation fail
BL_ERR_HMAC_SHA256 = 0x20, // HMAC-SHA256 operation fail - internal status
BL_ERR_INVALID_BOOT_SOURCE = 0x21, // Booted from boot source not recognized by PSP
BL_ERR_DIR_ENTRY_NOT_FOUND = 0x22, // PSP directory entry not found
BL_ERR_SPIROM_WRITE_FAIL = 0x23, // PSP failed to set the write enable latch
BL_ERR_SPIROM_BUSY_TIMEOUT = 0x24, // PSP timed out because spirom took too long
BL_ERR_CANNOT_FIND_BIOS_DIR = 0x25, // Cannot find BIOS directory
BL_ERR_SPIROM_SIZE = 0x26, // SpiRom is not valid
BL_ERR_SECURITY_STATE_DIFF = 0x27, // slave die has different security state from master
BL_ERR_SMI_INIT_ERROR = 0x28, // SMI interface init failure
BL_ERR_SMI_GENERIC = 0x29, // SMI interface generic error
BL_ERR_INVALID_DIE_ID = 0x2A, // invalid die ID executes MCM related function
BL_ERR_INVALID_MCM_CONFIG = 0x2B, // invalid MCM configuration table read from bootrom
BL_ERR_DETECT_BOOT_MODE = 0x2C, // Valid boot mode wasn't detected
BL_ERR_NVSTORAGE_INIT_FAILURE = 0x2D, // NVStorage init failure
BL_ERR_NVSTORAGE_GENERIC = 0x2E, // NVStorage generic error
BL_ERR_MCM_MORE_DATA = 0x2F, // MCM 'error' to indicate slave has more data to send
BL_ERR_MCM_DATA_LENGTH = 0x30, // MCM error if data size exceeds 32B
BL_ERR_MCM_INVALID_ID = 0x31, // Invalid client id for SVC MCM call
BL_ERR_MCM_INVALID_STATE = 0x32, // MCM slave status register contains bad bits
BL_ERR_MCM_NO_SLAVES = 0x33, // MCM call was made in a single die environment
BL_ERR_PSP_SECURE_MAP = 0x34, // PSP secure mapped to invalid segment (should be 0x400_0000)
BL_ERR_NO_PHY_CORES_PRESENT = 0x35, // No physical x86 cores were found on die
BL_ERR_SECURE_OS_INSUF_SRAM = 0x36, // Insufficient space for secure OS (range of free SRAM to SVC stack base)
BL_ERR_UNSUP_SYSHUB_TARGET_TYPE = 0x37, // SYSHUB mapping memory target type is not supported
BL_ERR_UNMAP_PSP_SECURE_REGION = 0x38, // Attempt to unmap permanently mapped TLB to PSP secure region
BL_ERR_SMNMAP_FAILED = 0x39, // Unable to map an SMN address to AXI space
BL_ERR_SYSHUBMAP_FAILED = 0x3A, // Unable to map a SYSHUB address to AXI space
BL_ERR_CORECONFIG_COUNT_MISMATCH = 0x3B, // The count of CCXs or cores provided by bootrom is not consistent
BL_ERR_UNCOMP_IMAGE_SIZE_MISMATCH = 0x3C, // Uncompressed image size doesn't match value in compressed header
BL_ERR_UNSUPPORTED_COMP_OPTION = 0x3D, // Compressed option used in case where not supported
BL_ERR_FUSE_INFO = 0x3E, // Fuse info on all dies don't match
BL_ERR_PSP_SMU_MSG_FAIL = 0x3F, // PSP sent message to SMU; SMU reported an error
BL_ERR_POST_X86_RELEASE_TEST_FAIL = 0x40, // Function RunPostX86ReleaseUnitTests failed in memcmp()
BL_ERR_PSP_SMU_INTERFACE = 0x41, // Interface between PSP to SMU not available.
BL_ERR_TIMER_PARAM_OVERFLOW = 0x42, // Timer wait parameter too large
BL_ERR_TEST_HARNESS_MODULE = 0x43, // Test harness module reported an error
BL_ERR_VMG_INVALID_COMMAND = 0x44, // x86 wrote C2PMSG_0 interrupting PSP, but the command has an
// invalid format
BL_ERR_L3CT_BLOCK_WRITE_FAILED = 0x45, // A write to an L3 register failed, as read-back did not match
BL_ERR_WARM_SRAMHMAC_FAIL = 0x46, // validation of the PSP SRAM image failed on HMAC
// compare
BL_ERR_MINI_BL_HMAC_UNIT_TEST_FAIL = 0x47, // Mini-BL CCP HMAC Unit-test failed
BL_ERR_JUMP_MINI_BL_STACK_OVERFLOW = 0x48, // Potential stack corruption in jump to Mini BL
BL_ERR_LOAD_VALIDATE_APOB = 0x49, // Error in Validate and Loading AGESA APOB SVC call
BL_ERR_DIAG_BL_FUSES = 0x4A, // Correct fuse bits for DIAG_BL loading not set
BL_ERR_UMC_NOT_INIT_BY_AGESA = 0x4B, // The UmcProgramKeys() function was not called by AGESA
BL_ERR_SECURE_UNLOCK_FAIL = 0x4C, // Secure unlock error
BL_ERR_SYSHUBIF_REG_MISMATCH = 0x4D, // Syshub register programming mismatch during readback
BL_ERR_SECURE_FUSE_FAMILY_ID = 0x4E, // Family ID in MP0_SFUSE_SEC[7:3] not correct
BL_ERR_NOT_GLOBAL_MASTER = 0x4F, // An operation was invoked that can only be performed by the GM
BL_ERR_SMB_TIMEOUT_ACQR_HOST_SEMA = 0x50, // Failed to acquire host controller semaphore to claim ownership of SMB
BL_ERR_SMB_TIMEOUT_WAIT_HOST_IDLE = 0x51, // Timed out waiting for host to complete pending transactions
BL_ERR_SMB_TIMEOUT_WAIT_SLAVE_IDLE = 0x52, // Timed out waiting for slave to complete pending transactions
BL_ERR_SMB_HOST_BUSY = 0x53, // Unable to kill current transaction on host, to force idle
BL_ERR_SMB_DEVICE_ERROR = 0x54, // One of: Illegal command, Unclaimed cycle, or Host time out
BL_ERR_SMB_BUS_COLLISION = 0x55, // An smbus transaction collision detected, operation restarted
BL_ERR_SMB_TRANSACTION_FAILED = 0x56, // Transaction failed to be started or processed by host, or not completed
BL_ERR_SMB_UNSOLICITED_INTR_RX = 0x57, // An unsolicited smbus interrupt was received
BL_ERR_PSP_SMU_UNSUPPORTED_MSG = 0x58, // An attempt to send an unsupported PSP-SMU message was made
BL_ERR_PSP_SMU_CORRUPTED_TXFR = 0x59, // An error/data corruption detected on response from SMU for sent msg
BL_ERR_MCM_STEADY_UNIT_TEST_FAILED = 0x5A, // MCM Steady-state unit test failed
BL_ERR_S3_ENTER_FAILED = 0x5B, // S3 Enter failed
BL_ERR_PSP_SMU_RESERVED_NOT_SET = 0x5C, // AGESA BL did not set PSP SMU reserved addresses via SVC call
BL_ERR_PSP_SMU_RESERVED_INVALID = 0x5D,
BL_ERR_UNFUSED_PART = 0x5E, // CcxSecBisiEn not set in fuse RAM
BL_ERR_UNIT_TEST_UNEXPECTED_RESULT = 0x5F, // Received an unexpected result
BL_ERR_SECURITY_GASKET = 0x60, // Error with applying security gasket
BL_ERR_MP2_FW_RESPONSE = 0x61, // MP2 FW provides error response in the message register
BL_ERR_FUSE_SMN_MAPPING_FAILED = 0x62, // An error occured whilst attempting to SMN map a fuse register
BL_ERR_FUSE_BURN_FAILED_SOC = 0x63, // Fuse burn sequence/operation failed due to internal SOC error
BL_ERR_FUSE_SENSE_TIMEOUT = 0x64, // Fuse sense operation timed out
BL_ERR_FUSE_BURN_FAILED_TIMEOUT = 0x65, // Fuse burn sequence/operation timed out waiting for burn done
BL_ERR_SECURE_OS_REVOKED = 0x66, // Failure status indicating that the given SecureOS has been
// revoked by the current PSP BL.
BL_ERR_FUSE_FW_ID_REVOKED = 0x67, // This PSP FW was revoked
BL_ERR_PLATFORM_ID = 0x68, // The platform model/vendor id fuse is not matching the BIOS public key token
BL_ERR_BIOS_KEY_REV_ID = 0x69, // The BIOS OEM public key of the BIOS was revoked for this platform
BL_ERR_DIAGBL_NOT_PRESENT = 0X6A, // The Diag Bootloader is not present in SPI-ROM
BL_ERR_DIAG_BL_SEQUENCE = 0x6B, // Failed to load PSP Diag BL
BL_ERR_POSTCODE_MAX_VALUE = 0x9F, // The maximum allowable error post code
} BL_RETCODE;
// Bootloader Return Codes, Success only (0xA0 through 0xFF)
typedef enum BL_TRACECODE_T
{
BL_SUCCESS_C_MAIN = 0xA0, // Bootloader successfully entered C Main
BL_SUCCESS_MCM_INIT = 0xA1, // Master initialized C2P / slave waited for master to init C2P
BL_SUCCESS_DERIVE_HMAC_KEY = 0xA2, // HMAC key successfully derived
BL_SUCCESS_DETECT_BOOT_MODE = 0xA3, // Master got Boot Mode and sent boot mode to all slaves
BL_SUCCESS_SPI_INIT = 0xA4, // SpiRom successfully initialized
BL_SUCCESS_COPY_BIOS_DIRECTORY = 0xA5, // BIOS Directory successfully read from SPI to SRAM
BL_SUCCESS_CHECK_EARLY_UNLOCK = 0xA6, // Early unlock check
BL_SUCCESS_DERIVE_INLINE_AES_KEY = 0xA7, // Inline Aes key successfully derived
BL_SUCCESS_INLINE_AES_KEY_PROGRAM = 0xA8, // Inline-AES key programming is done
BL_SUCCESS_INLINE_AES_KEY_WRAPPER = 0xA9, // Inline-AES key wrapper derivation is done
BL_SUCCESS_IP_CONFIG = 0xAA, // Bootloader successfully loaded HW IP configuration values
BL_SUCCESS_MBAT_PROGRAMMING = 0xAB, // Bootloader successfully programmed MBAT table
BL_SUCCESS_SECURITY_GASKET = 0xAC, // Bootloader successfully configured security gasket
BL_SUCCESS_LOAD_SMU = 0xAD, // Bootloader successfully loaded SMU FW
BL_SUCCESS_PSP_SMU_CONFIG_WAFL = 0xAE, // PSP and SMU configured WAFL
BL_SUCCESS_LOAD_MP2 = 0xAF, // Bootloader successfully loaded MP2 FW
BL_SUCCESS_START_AGESA = 0xB0, // Bootloader loaded Agesa0 from SpiRom
BL_SUCCESS_FINISHED_AGESA = 0xB1, // AGESA phase has completed
BL_SUCCESS_POST_DRAM_TESTS = 0xB2, // RunPostDramTrainingTests() completed successfully
BL_SUCCESS_LOAD_SMU_FW_TO_DRAM = 0xB3, // SMU FW Successfully loaded to SMU Secure DRAM
BL_SUCCESS_PSP_SMU_SENT_ALL_CMDS = 0xB4, // Sent all required boot time messages to SMU
BL_SUCCESS_RUN_SECURITY_GASKET = 0xB5, // Validated and ran Security Gasket binary
BL_SUCCESS_UMC_SECURITY_INIT = 0xB6, // UMC Keys generated and programmed
BL_SUCCESS_STORE_WRAPPED_KEY = 0xB7, // Inline AES key wrapper stored in DRAM
BL_SUCCESS_VALIDATED_OEM_KEY = 0xB8, // Completed FW Validation step
BL_SUCCESS_VALIDATED_BIOS_RST = 0xB9, // Completed FW Validation step
BL_SUCCESS_LOADING_BIOS_COMPONENTS = 0xBA, // BIOS copy from SPI to DRAM complete
BL_SUCCESS_VALIDATED_BIOS = 0xBB, // Completed FW Validation step
BL_SUCCESS_BIOS_LOAD_COMPLETE = 0xBC, // BIOS load process fully complete
BL_SUCCESS_RELEASE_X86 = 0xBD, // Bootloader successfully release x86
BL_SUCCESS_NORMAL_UNLOCK = 0xBE, // Early Secure Debug completed
BL_SUCCESS_GET_VERSION_COMMAND = 0xBF, // GetFWVersion command received from BIOS is completed
BL_SUCCESS_SMI_INFO_COMMAND = 0xC0, // SMIInfo command received from BIOS is completed
BL_SUCCESS_ENTER_WARM_BOOT = 0xC1, // Successfully entered WarmBootResume()
BL_SUCCESS_COPIED_SECURE_OS_SRAM = 0xC2, // Successfully copied SecureOS image to SRAM
BL_SUCCESS_COPIED_TRUSTLETS_DRAM = 0xC3, // Successfully copied trustlets to PSP Secure Memory
BL_SUCCESS_JUMPING_TO_SECURE_OS = 0xC4, // About to jump to Secure OS (SBL about to copy and jump)
BL_SUCCESS_RESTORED_CCP_STATE = 0xC5, // Successfully restored CCP and UMC state on S3 resume
BL_SUCCESS_WARM_MB_SRAMHMAC_PASS = 0xC6, // PSP SRAM HMAC validated by Mini BL
BL_SUCCESS_WARM_MB_TRANSFER2OS = 0xC7, // About to jump to <t-base in Mini BL
BL_SUCCESS_VMG_ECDH_UNIT_TEST_START = 0xC8, // VMG ECDH unit test started
BL_SUCCESS_VMG_ECDH_UNIT_TEST_PASS = 0xC9, // VMG ECDH unit test passed
BL_SUCCESS_VMG_ECC_CDH_TEST_START = 0xCA, // VMG ECC CDH primitive unit test started
BL_SUCCESS_VMG_ECC_CDH_TEST_PASS = 0xCB, // VMG ECC CDH primitive unit test passed
BL_SUCCESS_VMG_KDF_TEST_START = 0xCC, // VMG SP800-108 KDF-CTR HMAC unit test started
BL_SUCCESS_VMG_KDF_TEST_PASS = 0xCD, // VMG SP800-108 KDF-CTR HMAC unit test passed
BL_SUCCESS_VMG_LAUNCH_TEST_START = 0xCE, // VMG LAUNCH_* test started
BL_SUCCESS_VMG_LAUNCH_TEST_PASS = 0xCF, // VMG LAUNCH_* test passed
BL_SUCCESS_MP1_RESET_COMPLETE = 0xD0, // MP1 has been taken out of reset, and executing SMUFW
BL_SUCCESS_PSP_SMU_RESERVED_PROG = 0xD1, // PSP and SMU Reserved Addresses correct
BL_SUCCESS_NAPLES_STEADY_STATE = 0xD2, // Reached Naples steady-state WFI loop
//TODO: INQUIRE TO SMU TEAM IF THEY WILL HANDLE MILESTONE_CTR ON RV LIKE THEY DO ON ZP
BL_SUCCESS_MILESTONE_CTR_START = 0xD3, // Reached Naples steady-state WFI loop
BL_SUCCESS_MILESTONE_CTR_COMPLETE = 0xD4, // Reached Naples steady-state WFI loop
//Diag Bootloader
BL_SUCCESS_COPIED_DIAG_BL_DRAM = 0xD5, //Successfully load Diag Bootloader into DRAM
//
BL_CHECKED_MP2_DISABLED = 0xE0, // MP2 Block is disabled in MP2_RSMU_FUSESTRAPS
BL_SUCCESS_BOOT_DONE = 0xFF, // Bootloader sequence finished
} BL_TRACECODE;
#endif // _BL_ERRORCODES_H_

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============================ Picasso 114 VBIOS release ========================================
Picasso B1 0x15D8 105-D00100-00A PicassoGenericVbios.114 11/05/2018,5:27 AM 1702205@16.2.0.10 ATOMBuild #434041
Major changes:
1. fix ulSupportedDPLinkRate in device info is not correct if DPCD_SUPPORTED_LINK_RATE0/7 support in eDP DPCD(1.4)
2. when the OTG timing changed, the DP_MSA_PARAMETERSx should be reprogrammed.
3. fix wrong offset when get edptolvdsrxid and stereopinid setting from integrated system info table.
============================ Picasso 113 VBIOS release ========================================
Picasso B1 0x15D8 105-D00100-00A PicassoGenericVbios.113 9/12/2018,7:37 PM 1605109@16.2.0.7 ATOMBuild #429628
Major changes:
1.PCO Enables ASSR on VBIOS notification
fixed the no DP display issue introduced in the 112 PCO Vbios release.
============================ Picasso 112 VBIOS release ========================================
Picasso B1 0x15D8 105-D00100-00A PicassoGenericVbios.112 9/7/2018,6:05 PM 1603263@16.2.0.7 ATOMBuild #429232
Major changes:
1.PCO Enables ASSR on VBIOS notification
VBIOS to notify PSP FW of ASSR enablement instead,New CMD between VBIOS/PSP FW is defined as 0x05.
On reception of VBIOS notification, PSP FW will program DCE registers to enable ASSR and report success.

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============================ Raven2 114 VBIOS release ========================================
Raven2 generic Baseline VBIOS 114
Raven2 B0 0x15DD 113-RAVEN2-114 Raven2GenericVbios.114 01/03/19,10:04:58 AM 17255561@16.2.0.10 ATOMBuild #438488
Major changes:
1. Due to the change of security policy, PCTL0_MISC is removed from VBIOS GDB and would be programed by SMU
============================ Raven2 113 VBIOS release ========================================
Raven2 generic Baseline VBIOS 113
Raven2 B0 0x15DD 113-RAVEN2-113 Raven2GenericVbios.113 11/05/18,05:59:48 AM 1702205@16.2.0.10 ATOMBuild #434043
Major changes:
1. fix ulSupportedDPLinkRate in device info is not correct if DPCD_SUPPORTED_LINK_RATE0/7 support in eDP DPCD(1.4)
2. when the OTG timing changed, the DP_MSA_PARAMETERSx should be reprogrammed.
3. fix wrong offset when get edptolvdsrxid and stereopinid setting from integrated system info table.
============================ Raven2 112 VBIOS release ========================================
Raven2 generic Baseline VBIOS 112
Raven2 B0 0x15DD 113-RAVEN-112 Raven2GenericVbios.112 09/17/18,09:24:31 AM 16063731@16.2.0.7 ATOMBuild #429980
Major changes:
1. Update to support playready
============================ Raven2 111 VBIOS release ========================================
Raven2 generic Baseline VBIOS 111
Raven2 B0 0x15DD 113-RAVEN-111 Raven2GenericVbios.111 08/26/18,21:49:15 PM 15981601@16.2.0.7 ATOMBuild #428294
Major changes:
1. Update the PN to sync with RV1`s
2. Fix issue: MC_VM_APT_CNTL is not programmed properly
3. Fix issue: DP_VS_0.4v_0dB will be over written if enable DP customized tuning set even DP_VS_0.4v_0dB no need to be tuned
============================ Raven2 X06 VBIOS release ========================================
Raven2 generic Baseline VBIOS X06
Raven2 B0 0x15DD 105-D00100-00A Raven2GenericVbios.X06 5/10/2018,11:28 PM 1553338@16.2.0.7 ATOMBuild #415353
Major changes:
1. In retimer feature, add the logic to check the EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT flag in the atom_ext_display_path.caps. if this flag is not set, check the next path. X05 would lead to no display on the type-c port in certain cases.
2. Fix issue:Bootup corrupted or no display with BenQ 2k freesync DP panel
============================ Raven2 X05 VBIOS release ========================================
Raven2 generic Baseline VBIOS X05
Raven2 B0 0x15DD 105-D00100-00A Raven2GenericVbios.X05 5/2/2018,5:54 AM 1548712@16.2.0.7 ATOMBuild #414558
Major changes:
1. Support the GFX9 enhanced data fill mode for the DMA to clear memory. It sustains 32B per clock writes, when the source is a constant.
This is to fix the increased additional 60ms boot time issue.
2. Remove connector 4 since there is only 3 on RV2
3. Apply the change of PCTL_MISC in GDB

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