mirror of https://review.coreboot.org/STM.git
414 lines
10 KiB
ArmAsm
414 lines
10 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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# Module Name:
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#
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# Exception.s
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#
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(AsmExceptionHandlers)
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ASM_GLOBAL ASM_PFX(mExceptionHandlerLength)
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ASM_GLOBAL ASM_PFX(mExternalVectorTablePtr)
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ASM_GLOBAL ASM_PFX(mErrorCodeFlag)
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.data
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ASM_PFX(mExceptionHandlerLength): .long 8
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ASM_PFX(mExternalVectorTablePtr): .quad 0
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.text
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.p2align 3
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ASM_GLOBAL ASM_PFX(AsmExceptionHandlers)
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ASM_PFX(AsmExceptionHandlers):
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# The following segment repeats 32 times:
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# No. 0
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 1
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 2
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 3
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 4
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 5
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 6
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 7
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 8
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 9
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 10
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 11
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 12
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 13
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 14
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 15
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 16
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 17
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 18
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 19
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 20
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 21
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 22
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 23
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 24
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 25
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 26
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 27
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 28
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 29
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 30
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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# No. 31
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call CommonInterruptEntry
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.word ( . - ASM_PFX(AsmExceptionHandlers) - 5 ) / 8
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nop
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#---------------------------------------;
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# CommonInterruptEntry ;
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#---------------------------------------;
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# The follow algorithm is used for the common interrupt routine.
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#
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# +---------------------+ <-- 16-byte aligned ensured by processor
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# + Old SS +
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# +---------------------+
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# + Old RSP +
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# +---------------------+
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# + RFlags +
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# +---------------------+
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# + CS +
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# +---------------------+
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# + RIP +
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# +---------------------+
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# + Error Code +
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# +---------------------+
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# + RCX / Vector Number +
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# +---------------------+
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# + RBP +
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# +---------------------+ <-- RBP, 16-byte aligned
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#
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CommonInterruptEntry:
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cli
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#
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# All interrupt handlers are invoked through interrupt gates, so
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# IF flag automatically cleared at the entry point
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#
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#
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# Calculate vector number
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#
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xchg %rcx, (%rsp)
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movzwl (%rcx), %ecx
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cmpl $32,%ecx # Intel reserved vector for exceptions?
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jae NoErrorCode
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btl %ecx, ASM_PFX(mErrorCodeFlag)(%rip)
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jc L1
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NoErrorCode:
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#
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# Push a dummy error code on the stack
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# to maintain coherent stack map
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#
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pushq (%rsp)
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movq $0, 8(%rsp)
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L1:
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pushq %rbp
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movq %rsp, %rbp
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#
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# Since here the stack pointer is 16-byte aligned, so
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# EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
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# is 16-byte aligned
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#
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## UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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## UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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pushq %r15
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pushq %r14
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pushq %r13
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pushq %r12
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pushq %r11
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pushq %r10
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pushq %r9
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pushq %r8
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pushq %rax
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pushq 8(%rbp)
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pushq %rdx
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pushq %rbx
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pushq 48(%rbp)
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pushq (%rbp)
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pushq %rsi
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pushq %rdi
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## UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
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movzwq 56(%rbp), %rax
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pushq %rax
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movzwq 32(%rbp), %rax
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pushq %rax
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movq %ds, %rax
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pushq %rax
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movq %es, %rax
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pushq %rax
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movq %fs, %rax
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pushq %rax
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movq %gs, %rax
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pushq %rax
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movq %rcx, 8(%rbp)
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## UINT64 Rip;
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pushq 24(%rbp)
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## UINT64 Gdtr[2], Idtr[2];
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subq $16, %rsp
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sidt (%rsp)
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subq $16, %rsp
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sgdt (%rsp)
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## UINT64 Ldtr, Tr;
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xorq %rax, %rax
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strw %ax
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pushq %rax
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sldtw %ax
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pushq %rax
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## UINT64 RFlags;
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pushq 40(%rbp)
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## UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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movq %cr8, %rax
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pushq %rax
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movq %cr4, %rax
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orq $0x208, %rax
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movq %rax, %cr4
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pushq %rax
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movq %cr3, %rax
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pushq %rax
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movq %cr2, %rax
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pushq %rax
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xorq %rax, %rax
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pushq %rax
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movq %cr0, %rax
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pushq %rax
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## UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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movq %dr7, %rax
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pushq %rax
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movq %dr6, %rax
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pushq %rax
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movq %dr3, %rax
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pushq %rax
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movq %dr2, %rax
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pushq %rax
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movq %dr1, %rax
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pushq %rax
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movq %dr0, %rax
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pushq %rax
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## FX_SAVE_STATE_X64 FxSaveState;
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subq $512, %rsp
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movq %rsp, %rdi
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.byte 0x0f, 0xae, 0b00000111
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## UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
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cld
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## UINT32 ExceptionData;
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pushq 16(%rbp)
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## call into exception handler
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movq 8(%rbp), %rcx
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movq 8(%rbp), %rdi ##for GCC
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movq ASM_PFX(mExternalVectorTablePtr)(%rip), %rax
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movq (%rax, %rcx, 8), %rax
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orq %rax, %rax
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je nonNullValue #
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## Prepare parameter and call
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movq %rsp, %rdx
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movq %rsp, %rsi # second parameter for GCC
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#
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# Per X64 calling convention, allocate maximum parameter stack space
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# and make sure RSP is 16-byte aligned
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#
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subq $(4 * 8 + 8), %rsp
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call *%rax
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addq $(4 * 8 + 8), %rsp
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nonNullValue:
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cli
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## UINT64 ExceptionData;
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addq $8, %rsp
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## FX_SAVE_STATE_X64 FxSaveState;
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movq %rsp, %rsi
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.byte 0x0f, 0xae, 0b00001110
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addq $512, %rsp
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## UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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## Skip restoration of DRx registers to support in-circuit emualators
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## or debuggers set breakpoint in interrupt/exception context
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addq $48, %rsp
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## UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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popq %rax
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movq %rax, %cr0
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addq $8, %rsp
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popq %rax
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movq %rax, %cr2
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popq %rax
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movq %rax, %cr3
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popq %rax
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movq %rax, %cr4
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popq %rax
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movq %rax, %cr8
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## UINT64 RFlags;
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popq 40(%rbp)
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## UINT64 Ldtr, Tr;
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## UINT64 Gdtr[2], Idtr[2];
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## Best not let anyone mess with these particular registers...
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addq $48, %rsp
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## UINT64 Rip;
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popq 24(%rbp)
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## UINT64 Gs, Fs, Es, Ds, Cs, Ss;
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popq %rax
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# mov gs, rax ; not for gs
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popq %rax
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# mov fs, rax ; not for fs
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# (X64 will not use fs and gs, so we do not restore it)
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popq %rax
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movw %ax, %es
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popq %rax
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movw %ax, %ds
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popq 32(%rbp)
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popq 56(%rbp)
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## UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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## UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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popq %rdi
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popq %rsi
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addq $8, %rsp
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popq 48(%rbp)
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popq %rbx
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popq %rdx
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popq %rcx
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popq %rax
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popq %r8
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popq %r9
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popq %r10
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popq %r11
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popq %r12
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popq %r13
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popq %r14
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popq %r15
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movq %rbp, %rsp
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popq %rbp
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addq $16, %rsp
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iretq
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