mirror of https://review.coreboot.org/STM.git
Add >4G memory map.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
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@ -14,6 +14,63 @@
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#include <Base.h>
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#include "FrmInit.h"
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/**
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This function create >4G paging for X64 mode.
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@param PageTable Page table pointer
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**/
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VOID
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CreateAbove4GPaging (
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IN UINTN PageTable
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)
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{
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UINTN Index;
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UINTN SubIndex;
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UINTN Pml4Index;
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UINT64 *Pde;
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UINT64 *Pte;
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UINT64 *Pml4;
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UINT64 BaseAddress;
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UINTN NumberOfPml4EntriesNeeded;
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UINTN NumberOfPdpEntriesNeeded;
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if (sizeof(UINTN) == sizeof(UINT64)) {
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Pml4 = (UINT64 *)PageTable;
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if (mHostContextCommon.PhysicalAddressBits <= 39) {
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NumberOfPml4EntriesNeeded = 1;
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NumberOfPdpEntriesNeeded = (UINTN)LShiftU64 (1, mHostContextCommon.PhysicalAddressBits - 30);
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} else {
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NumberOfPml4EntriesNeeded = (UINTN)LShiftU64 (1, mHostContextCommon.PhysicalAddressBits - 39);
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NumberOfPdpEntriesNeeded = 512;
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}
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BaseAddress = BASE_4GB;
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for (Pml4Index = 0; Pml4Index < NumberOfPml4EntriesNeeded; Pml4Index++) {
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if (Pml4Index > 0) {
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Pde = (UINT64 *)(UINTN)AllocatePages (1);
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Pml4[Pml4Index] = (UINT64)(UINTN)Pde | IA32_PG_P;
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Index = 0;
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} else {
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// Start from 4G - Pml4[0] already allocated.
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Pde = (UINT64 *)(UINTN)(Pml4[0] & 0xFFFFF000);
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Index = 4;
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}
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for (; Index < NumberOfPdpEntriesNeeded; Index++) {
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Pte = (UINT64 *)AllocatePages (1);
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Pde[Index] = (UINT64)(UINTN)Pte | IA32_PG_P;
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for (SubIndex = 0; SubIndex < SIZE_4KB / sizeof(*Pte); SubIndex++) {
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Pte[SubIndex] = BaseAddress | IA32_PG_PS | IA32_PG_RW | IA32_PG_P;
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BaseAddress += SIZE_2MB;
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}
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}
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}
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}
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}
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/**
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This function create 4G page table for Host.
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@ -70,6 +127,7 @@ CreatePageTable (
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//
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if (sizeof(UINTN) == sizeof(UINT64)) {
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PageTable = (UINTN)Pml4;
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CreateAbove4GPaging(PageTable);
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}
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return PageTable;
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}
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