enable 1G paging for test FRM.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
This commit is contained in:
Jiewen Yao 2016-12-14 10:53:37 +08:00
parent ca0afe832d
commit 3b0160622c
1 changed files with 39 additions and 6 deletions

View File

@ -14,6 +14,31 @@
#include <Base.h>
#include "FrmInit.h"
/**
Check if 1-GByte pages is supported by processor or not.
@retval TRUE 1-GByte pages is supported.
@retval FALSE 1-GByte pages is not supported.
**/
BOOLEAN
Is1GPageSupport (
VOID
)
{
UINT32 RegEax;
UINT32 RegEdx;
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
if (RegEax >= 0x80000001) {
AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
if ((RegEdx & BIT26) != 0) {
return TRUE;
}
}
return FALSE;
}
/**
This function create >4G paging for X64 mode.
@ -58,13 +83,21 @@ CreateAbove4GPaging (
Pde = (UINT64 *)(UINTN)(Pml4[0] & 0xFFFFF000);
Index = 4;
}
for (; Index < NumberOfPdpEntriesNeeded; Index++) {
Pte = (UINT64 *)AllocatePages (1);
Pde[Index] = (UINT64)(UINTN)Pte | IA32_PG_P;
for (SubIndex = 0; SubIndex < SIZE_4KB / sizeof(*Pte); SubIndex++) {
Pte[SubIndex] = BaseAddress | IA32_PG_PS | IA32_PG_RW | IA32_PG_P;
BaseAddress += SIZE_2MB;
if (Is1GPageSupport()) {
for (; Index < NumberOfPdpEntriesNeeded; Index++) {
Pde[Index] = (UINT64)(UINTN)BaseAddress | IA32_PG_PS | IA32_PG_RW | IA32_PG_P;
BaseAddress += SIZE_1GB;
}
} else {
for (; Index < NumberOfPdpEntriesNeeded; Index++) {
Pte = (UINT64 *)AllocatePages (1);
Pde[Index] = (UINT64)(UINTN)Pte | IA32_PG_P;
for (SubIndex = 0; SubIndex < SIZE_4KB / sizeof(*Pte); SubIndex++) {
Pte[SubIndex] = BaseAddress | IA32_PG_PS | IA32_PG_RW | IA32_PG_P;
BaseAddress += SIZE_2MB;
}
}
}
}