boards: arm: mps2-an521: Fix DT memory regions
Currently RAM region specified in the DT for board mps2-an512 to store data (not to run code) is set to start at 0x3000_0000 and a 16M contiguous space is assumed. However, at that address there is no such contiguous space of 16M, rather only a 128K area is available. As a consequence large applications linked with Zephyr might end up using memory regions that are not valid, specially at runtime when the stack grows, causing a BusFault. Application Note 512 only specifies a 16M contiguous space available starting at 0x8000_0000 (please see 'Table 3-4: SSRAM2 and SSRAM3 address mapping' and 'Table 3-6: External PSRAM mapping to Code Memory', on pages 3-7 and 3-8, respectively), which resides in the PSRAM (external RAM). The AN521 also specifies a 4M contiguous space available starting at 0x3800_0000 which can be used as RAM for data storage and which is not currently described in the DT. The current DT also defines a 224M flash region (to run code) which doesn't effectively exist, because most of it is reserved (~148M). That commit fixes the incorrect definition of region 0x3000_0000 (16M) and hence defines a new region called 'sram2_3' that maps to region 0x3800_0000 (4M) which is used as RAM to store data, and fixes the flash region defining a new region 'sram1' (4M) from where code is executed (starting at 0x1000_0000). The board has no real flash memory, rather an auxilary HW populates the appropriate memory regions from images found in a MicroSD card. That commit also defines the missing PSRAM (16M) region ('psram') which can be used by large programs as a general purpose RAM. Finally, it also fixes the DT for the non-secure memory regions to reflect the fixes described above for the secure memory regions. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
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@ -6,6 +6,7 @@
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/dts-v1/;
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <dt-bindings/i2c/i2c.h>
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@ -25,8 +26,8 @@
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,sram = &sram2_3;
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zephyr,flash = &sram1;
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};
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leds {
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@ -72,13 +73,25 @@
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};
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};
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sram0: memory@30000000 {
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/*
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* The memory regions defined below are according to AN521:
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* https://documentation-service.arm.com/static/5fa12fe9b1a7c5445f29017f
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* Please see tables from 3-1 to 3-4.
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*/
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sram1: memory@10000000 {
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compatible = "mmio-sram";
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reg = <0x30000000 0x1000000>;
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reg = <0x10000000 DT_SIZE_M(4)>;
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};
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flash0: flash@10000000 {
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reg = <0x10000000 0xE000000>;
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sram2_3: memory@38000000 {
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compatible = "mmio-sram";
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reg = <0x38000000 DT_SIZE_M(4)>;
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};
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psram: memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 DT_SIZE_M(16)>;
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};
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soc {
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@ -6,6 +6,7 @@
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/dts-v1/;
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <dt-bindings/i2c/i2c.h>
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,sram = &ram;
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zephyr,flash = &code;
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};
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leds {
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@ -72,13 +73,45 @@
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};
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};
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sram0: memory@28100000 {
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/*
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* The memory regions defined below are according to AN521:
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* https://documentation-service.arm.com/static/5fa12fe9b1a7c5445f29017f
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* Please see tables from 3-1 to 3-4.
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*/
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sram1: memory@0 {
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compatible = "mmio-sram";
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reg = <0x28100000 0x100000>;
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reg = <0x0 DT_SIZE_M(4)>;
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};
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flash0: flash@100000 {
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reg = <0x100000 0xDF00000>;
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sram2_3: memory@28000000 {
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compatible = "mmio-sram";
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reg = <0x28000000 DT_SIZE_M(4)>;
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};
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psram: memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 DT_SIZE_M(16)>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* The memory regions defined below must match what the TF-M
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* project has defined for that board - a single image boot is
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* assumed. Please see the memory layout in:
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* https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps2/an521/partition/flash_layout.h
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*/
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code: memory@100000 {
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reg = <0x00100000 DT_SIZE_K(512)>;
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};
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ram: memory@28100000 {
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reg = <0x28100000 DT_SIZE_M(1)>;
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};
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};
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soc {
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