diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 55aa13f..29429a7 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -52,8 +52,6 @@ on: - xtensa-espressif_esp32_zephyr-elf - xtensa-espressif_esp32s2_zephyr-elf - xtensa-intel_apl_adsp_zephyr-elf - - xtensa-intel_bdw_adsp_zephyr-elf - - xtensa-intel_byt_adsp_zephyr-elf - xtensa-intel_s1000_zephyr-elf - xtensa-nxp_imx_adsp_zephyr-elf - xtensa-nxp_imx8m_adsp_zephyr-elf @@ -160,8 +158,6 @@ jobs: xtensa-espressif_esp32_zephyr-elf) build_target_xtensa_espressif_esp32_zephyr_elf="y";; xtensa-espressif_esp32s2_zephyr-elf) build_target_xtensa_espressif_esp32s2_zephyr_elf="y";; xtensa-intel_apl_adsp_zephyr-elf) build_target_xtensa_intel_apl_adsp_zephyr_elf="y";; - xtensa-intel_bdw_adsp_zephyr-elf) build_target_xtensa_intel_bdw_adsp_zephyr_elf="y";; - xtensa-intel_byt_adsp_zephyr-elf) build_target_xtensa_intel_byt_adsp_zephyr_elf="y";; xtensa-intel_s1000_zephyr-elf) build_target_xtensa_intel_s1000_zephyr_elf="y";; xtensa-nxp_imx_adsp_zephyr-elf) build_target_xtensa_nxp_imx_adsp_zephyr_elf="y";; xtensa-nxp_imx8m_adsp_zephyr-elf) build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y";; @@ -196,8 +192,6 @@ jobs: build_target_xtensa_espressif_esp32_zephyr_elf="y" build_target_xtensa_espressif_esp32s2_zephyr_elf="y" build_target_xtensa_intel_apl_adsp_zephyr_elf="y" - build_target_xtensa_intel_bdw_adsp_zephyr_elf="y" - build_target_xtensa_intel_byt_adsp_zephyr_elf="y" build_target_xtensa_intel_s1000_zephyr_elf="y" build_target_xtensa_nxp_imx_adsp_zephyr_elf="y" build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y" @@ -272,8 +266,6 @@ jobs: [ "${build_target_xtensa_espressif_esp32_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-espressif_esp32_zephyr-elf",' [ "${build_target_xtensa_espressif_esp32s2_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-espressif_esp32s2_zephyr-elf",' [ "${build_target_xtensa_intel_apl_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-intel_apl_adsp_zephyr-elf",' - [ "${build_target_xtensa_intel_bdw_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-intel_bdw_adsp_zephyr-elf",' - [ "${build_target_xtensa_intel_byt_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-intel_byt_adsp_zephyr-elf",' [ "${build_target_xtensa_intel_s1000_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-intel_s1000_zephyr-elf",' [ "${build_target_xtensa_nxp_imx_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx_adsp_zephyr-elf",' [ "${build_target_xtensa_nxp_imx8m_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx8m_adsp_zephyr-elf",' @@ -1521,12 +1513,6 @@ jobs: xtensa-intel_apl_adsp_zephyr-elf) PLATFORM_ARGS+="-p intel_adsp_cavs15 " ;; - xtensa-intel_bdw_adsp_zephyr-elf) - # NOTE: no default user for this target is available - ;; - xtensa-intel_byt_adsp_zephyr-elf) - # NOTE: no default user for this target is available - ;; xtensa-intel_s1000_zephyr-elf) PLATFORM_ARGS+="-p intel_adsp_cavs18 " ;; diff --git a/README.md b/README.md index 1f41776..2c2489e 100644 --- a/README.md +++ b/README.md @@ -12,8 +12,8 @@ The toolchains for the following target architectures are supported: - Nios II - RISC-V (32-bit and 64-bit; RV32I, RV32E, RV64I) - x86 (32-bit and 64-bit) -- Xtensa (sample_controller, intel_apl_adsp, intel_bdw_adsp, intel_byt_adsp, - intel_s1000, nxp_imx_adsp, nxp_imx8m_adsp, espressif_esp32, espressif_esp32s2) +- Xtensa (sample_controller, intel_apl_adsp, intel_s1000, + nxp_imx_adsp, nxp_imx8m_adsp, espressif_esp32, espressif_esp32s2) The following host tools are available as part of the Zephyr SDK: diff --git a/configs/xtensa-intel_bdw_adsp_zephyr-elf.config b/configs/xtensa-intel_bdw_adsp_zephyr-elf.config deleted file mode 100644 index 1cecbdd..0000000 --- a/configs/xtensa-intel_bdw_adsp_zephyr-elf.config +++ /dev/null @@ -1,71 +0,0 @@ -CT_CONFIG_VERSION="3" -CT_EXPERIMENTAL=y -# CT_PREFIX_DIR_RO is not set -# CT_LOG_PROGRESS_BAR is not set -CT_ARCH_XTENSA=y -CT_XTENSA_CUSTOM=y -# CT_ARCH_USE_MMU is not set -CT_OVERLAY_NAME="intel_bdw_adsp" -CT_OVERLAY_LOCATION="./overlays" -CT_TARGET_VENDOR="intel_bdw_adsp_zephyr" -CT_TARGET_CFLAGS="-ftls-model=local-exec" -CT_BINUTILS_SRC_CUSTOM=y -CT_BINUTILS_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/binutils" -CT_NEWLIB_SRC_CUSTOM=y -CT_NEWLIB_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/newlib" -CT_LIBC_NEWLIB_TARGET_CFLAGS="-O2" -# CT_LIBC_NEWLIB_ENABLE_TARGET_OPTSPACE is not set -CT_LIBC_NEWLIB_IO_C99FMT=y -CT_LIBC_NEWLIB_IO_LL=y -CT_LIBC_NEWLIB_IO_FLOAT=y -# CT_LIBC_NEWLIB_FSEEK_OPTIMIZATION is not set -CT_LIBC_NEWLIB_DISABLE_SUPPLIED_SYSCALLS=y -CT_LIBC_NEWLIB_GLOBAL_ATEXIT=y -CT_LIBC_NEWLIB_LITE_EXIT=y -CT_LIBC_NEWLIB_MULTITHREAD=y -CT_LIBC_NEWLIB_RETARGETABLE_LOCKING=y -# CT_LIBC_NEWLIB_WIDE_ORIENT is not set -# CT_LIBC_NEWLIB_NANO_MALLOC is not set -# CT_LIBC_NEWLIB_NANO_FORMATTED_IO is not set -CT_LIBC_NEWLIB_EXTRA_SECTIONS=y -CT_GCC_SRC_CUSTOM=y -CT_GCC_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/gcc" -CT_CC_GCC_EXTRA_CONFIG_ARRAY="--with-gnu-ld --with-gnu-as --enable-initfini-array" -CT_CC_GCC_CONFIG_TLS=n -CT_CC_LANG_CXX=y -CT_DEBUG_GDB=y -CT_GDB_SRC_CUSTOM=y -CT_GDB_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/gdb" -CT_COMP_LIBS_NEWLIB_NANO=y -CT_NEWLIB_NANO_SRC_CUSTOM=y -CT_NEWLIB_NANO_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/newlib" -CT_NEWLIB_NANO_GCC_LIBSTDCXX=y -CT_NEWLIB_NANO_INSTALL_IN_TARGET=y -# CT_LIBC_NEWLIB_NANO_IO_C99FMT is not set -# CT_LIBC_NEWLIB_NANO_IO_LL is not set -CT_LIBC_NEWLIB_NANO_IO_FLOAT=y -# CT_LIBC_NEWLIB_NANO_IO_LDBL is not set -# CT_LIBC_NEWLIB_NANO_IO_POS_ARGS is not set -CT_LIBC_NEWLIB_NANO_FVWRITE_IN_STREAMIO=y -# CT_LIBC_NEWLIB_NANO_UNBUF_STREAM_OPT is not set -# CT_LIBC_NEWLIB_NANO_FSEEK_OPTIMIZATION is not set -CT_LIBC_NEWLIB_NANO_DISABLE_SUPPLIED_SYSCALLS=y -# CT_LIBC_NEWLIB_NANO_REGISTER_FINI is not set -CT_LIBC_NEWLIB_NANO_ATEXIT_DYNAMIC_ALLOC=y -CT_LIBC_NEWLIB_NANO_GLOBAL_ATEXIT=y -CT_LIBC_NEWLIB_NANO_LITE_EXIT=y -CT_LIBC_NEWLIB_NANO_REENT_SMALL=y -CT_LIBC_NEWLIB_NANO_MULTITHREAD=y -CT_LIBC_NEWLIB_NANO_RETARGETABLE_LOCKING=y -CT_LIBC_NEWLIB_NANO_EXTRA_SECTIONS=y -# CT_LIBC_NEWLIB_NANO_WIDE_ORIENT is not set -CT_LIBC_NEWLIB_NANO_ENABLE_TARGET_OPTSPACE=y -# CT_LIBC_NEWLIB_NANO_LTO is not set -CT_LIBC_NEWLIB_NANO_NANO_MALLOC=y -CT_LIBC_NEWLIB_NANO_NANO_FORMATTED_IO=y -CT_COMP_LIBS_PICOLIBC=y -CT_PICOLIBC_SRC_CUSTOM=y -CT_PICOLIBC_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/picolibc" -CT_LIBC_PICOLIBC_GLOBAL_ATEXIT=y -CT_LIBC_PICOLIBC_EXTRA_SECTIONS=y -CT_LIBC_PICOLIBC_EXTRA_CONFIG_ARRAY="-Dthread-local-storage=auto -Derrno-function=zephyr -Dsysroot-install=true -Dsysroot-install-skip-checks=true" diff --git a/configs/xtensa-intel_byt_adsp_zephyr-elf.config b/configs/xtensa-intel_byt_adsp_zephyr-elf.config deleted file mode 100644 index d5a111b..0000000 --- a/configs/xtensa-intel_byt_adsp_zephyr-elf.config +++ /dev/null @@ -1,71 +0,0 @@ -CT_CONFIG_VERSION="3" -CT_EXPERIMENTAL=y -# CT_PREFIX_DIR_RO is not set -# CT_LOG_PROGRESS_BAR is not set -CT_ARCH_XTENSA=y -CT_XTENSA_CUSTOM=y -# CT_ARCH_USE_MMU is not set -CT_OVERLAY_NAME="intel_byt_adsp" -CT_OVERLAY_LOCATION="./overlays" -CT_TARGET_VENDOR="intel_byt_adsp_zephyr" -CT_TARGET_CFLAGS="-ftls-model=local-exec" -CT_BINUTILS_SRC_CUSTOM=y -CT_BINUTILS_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/binutils" -CT_NEWLIB_SRC_CUSTOM=y -CT_NEWLIB_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/newlib" -CT_LIBC_NEWLIB_TARGET_CFLAGS="-O2" -# CT_LIBC_NEWLIB_ENABLE_TARGET_OPTSPACE is not set -CT_LIBC_NEWLIB_IO_C99FMT=y -CT_LIBC_NEWLIB_IO_LL=y -CT_LIBC_NEWLIB_IO_FLOAT=y -# CT_LIBC_NEWLIB_FSEEK_OPTIMIZATION is not set -CT_LIBC_NEWLIB_DISABLE_SUPPLIED_SYSCALLS=y -CT_LIBC_NEWLIB_GLOBAL_ATEXIT=y -CT_LIBC_NEWLIB_LITE_EXIT=y -CT_LIBC_NEWLIB_MULTITHREAD=y -CT_LIBC_NEWLIB_RETARGETABLE_LOCKING=y -# CT_LIBC_NEWLIB_WIDE_ORIENT is not set -# CT_LIBC_NEWLIB_NANO_MALLOC is not set -# CT_LIBC_NEWLIB_NANO_FORMATTED_IO is not set -CT_LIBC_NEWLIB_EXTRA_SECTIONS=y -CT_GCC_SRC_CUSTOM=y -CT_GCC_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/gcc" -CT_CC_GCC_EXTRA_CONFIG_ARRAY="--with-gnu-ld --with-gnu-as --enable-initfini-array" -CT_CC_GCC_CONFIG_TLS=n -CT_CC_LANG_CXX=y -CT_DEBUG_GDB=y -CT_GDB_SRC_CUSTOM=y -CT_GDB_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/gdb" -CT_COMP_LIBS_NEWLIB_NANO=y -CT_NEWLIB_NANO_SRC_CUSTOM=y -CT_NEWLIB_NANO_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/newlib" -CT_NEWLIB_NANO_GCC_LIBSTDCXX=y -CT_NEWLIB_NANO_INSTALL_IN_TARGET=y -# CT_LIBC_NEWLIB_NANO_IO_C99FMT is not set -# CT_LIBC_NEWLIB_NANO_IO_LL is not set -CT_LIBC_NEWLIB_NANO_IO_FLOAT=y -# CT_LIBC_NEWLIB_NANO_IO_LDBL is not set -# CT_LIBC_NEWLIB_NANO_IO_POS_ARGS is not set -CT_LIBC_NEWLIB_NANO_FVWRITE_IN_STREAMIO=y -# CT_LIBC_NEWLIB_NANO_UNBUF_STREAM_OPT is not set -# CT_LIBC_NEWLIB_NANO_FSEEK_OPTIMIZATION is not set -CT_LIBC_NEWLIB_NANO_DISABLE_SUPPLIED_SYSCALLS=y -# CT_LIBC_NEWLIB_NANO_REGISTER_FINI is not set -CT_LIBC_NEWLIB_NANO_ATEXIT_DYNAMIC_ALLOC=y -CT_LIBC_NEWLIB_NANO_GLOBAL_ATEXIT=y -CT_LIBC_NEWLIB_NANO_LITE_EXIT=y -CT_LIBC_NEWLIB_NANO_REENT_SMALL=y -CT_LIBC_NEWLIB_NANO_MULTITHREAD=y -CT_LIBC_NEWLIB_NANO_RETARGETABLE_LOCKING=y -CT_LIBC_NEWLIB_NANO_EXTRA_SECTIONS=y -# CT_LIBC_NEWLIB_NANO_WIDE_ORIENT is not set -CT_LIBC_NEWLIB_NANO_ENABLE_TARGET_OPTSPACE=y -# CT_LIBC_NEWLIB_NANO_LTO is not set -CT_LIBC_NEWLIB_NANO_NANO_MALLOC=y -CT_LIBC_NEWLIB_NANO_NANO_FORMATTED_IO=y -CT_COMP_LIBS_PICOLIBC=y -CT_PICOLIBC_SRC_CUSTOM=y -CT_PICOLIBC_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/picolibc" -CT_LIBC_PICOLIBC_GLOBAL_ATEXIT=y -CT_LIBC_PICOLIBC_EXTRA_SECTIONS=y -CT_LIBC_PICOLIBC_EXTRA_CONFIG_ARRAY="-Dthread-local-storage=auto -Derrno-function=zephyr -Dsysroot-install=true -Dsysroot-install-skip-checks=true" diff --git a/overlays/xtensa_intel_bdw_adsp/binutils/bfd/xtensa-modules.c b/overlays/xtensa_intel_bdw_adsp/binutils/bfd/xtensa-modules.c deleted file mode 100644 index d71738b..0000000 --- a/overlays/xtensa_intel_bdw_adsp/binutils/bfd/xtensa-modules.c +++ /dev/null @@ -1,42144 +0,0 @@ -/* Xtensa configuration-specific ISA information. - - Customer ID=4313; Build=0x5483e; Copyright (c) 2003-2015 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#include "ansidecl.h" -#include -#include "xtensa-isa-internal.h" - -#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) - - -/* Sysregs. */ - -static xtensa_sysreg_internal sysregs[] = { - { "LBEG", 0, 0 }, - { "LEND", 1, 0 }, - { "LCOUNT", 2, 0 }, - { "BR", 4, 0 }, - { "MMID", 89, 0 }, - { "DDR", 104, 0 }, - { "CONFIGID0", 176, 0 }, - { "CONFIGID1", 208, 0 }, - { "INTERRUPT", 226, 0 }, - { "INTCLEAR", 227, 0 }, - { "CCOUNT", 234, 0 }, - { "PRID", 235, 0 }, - { "ICOUNT", 236, 0 }, - { "CCOMPARE0", 240, 0 }, - { "CCOMPARE1", 241, 0 }, - { "CCOMPARE2", 242, 0 }, - { "VECBASE", 231, 0 }, - { "EPC1", 177, 0 }, - { "EPC2", 178, 0 }, - { "EPC3", 179, 0 }, - { "EPC4", 180, 0 }, - { "EPC5", 181, 0 }, - { "EPC6", 182, 0 }, - { "EPC7", 183, 0 }, - { "EXCSAVE1", 209, 0 }, - { "EXCSAVE2", 210, 0 }, - { "EXCSAVE3", 211, 0 }, - { "EXCSAVE4", 212, 0 }, - { "EXCSAVE5", 213, 0 }, - { "EXCSAVE6", 214, 0 }, - { "EXCSAVE7", 215, 0 }, - { "EPS2", 194, 0 }, - { "EPS3", 195, 0 }, - { "EPS4", 196, 0 }, - { "EPS5", 197, 0 }, - { "EPS6", 198, 0 }, - { "EPS7", 199, 0 }, - { "EXCCAUSE", 232, 0 }, - { "DEPC", 192, 0 }, - { "EXCVADDR", 238, 0 }, - { "WINDOWBASE", 72, 0 }, - { "WINDOWSTART", 73, 0 }, - { "SAR", 3, 0 }, - { "PS", 230, 0 }, - { "MISC0", 244, 0 }, - { "MISC1", 245, 0 }, - { "INTENABLE", 228, 0 }, - { "DBREAKA0", 144, 0 }, - { "DBREAKC0", 160, 0 }, - { "DBREAKA1", 145, 0 }, - { "DBREAKC1", 161, 0 }, - { "IBREAKA0", 128, 0 }, - { "IBREAKA1", 129, 0 }, - { "IBREAKENABLE", 96, 0 }, - { "ICOUNTLEVEL", 237, 0 }, - { "DEBUGCAUSE", 233, 0 }, - { "PREFCTL", 40, 0 }, - { "CPENABLE", 224, 0 }, - { "SCOMPARE1", 12, 0 }, - { "ATOMCTL", 99, 0 }, - { "AE_OVF_SAR", 240, 1 }, - { "AE_BITHEAD", 241, 1 }, - { "AE_TS_FTS_BU_BP", 242, 1 }, - { "AE_SD_NO", 243, 1 }, - { "AE_CBEGIN0", 246, 1 }, - { "AE_CEND0", 247, 1 }, - { "EXPSTATE", 230, 1 }, - { "MEPC", 106, 0}, - { "MEPS", 107, 0}, - { "MESAVE", 108, 0}, - { "MESR", 109, 0}, - { "MECR", 110, 0}, - { "MEVADDR", 111, 0}, - { "MEMCTL", 97, 0}, - { "ACCLO", 16, 0}, - { "ACCHI", 17, 0}, - { "THREADPTR", 231, 1}, -}; - -#define NUM_SYSREGS ARRAY_SIZE(sysregs) -#define MAX_SPECIAL_REG 245 -#define MAX_USER_REG 247 - - -/* Processor states. */ - -static xtensa_state_internal states[] = { - { "LCOUNT", 32, 0 }, - { "PC", 32, 0 }, - { "ICOUNT", 32, 0 }, - { "DDR", 32, 0 }, - { "INTERRUPT", 22, 0 }, - { "CCOUNT", 32, 0 }, - { "XTSYNC", 1, 0 }, - { "VECBASE", 22, 0 }, - { "EPC1", 32, 0 }, - { "EPC2", 32, 0 }, - { "EPC3", 32, 0 }, - { "EPC4", 32, 0 }, - { "EPC5", 32, 0 }, - { "EPC6", 32, 0 }, - { "EPC7", 32, 0 }, - { "EXCSAVE1", 32, 0 }, - { "EXCSAVE2", 32, 0 }, - { "EXCSAVE3", 32, 0 }, - { "EXCSAVE4", 32, 0 }, - { "EXCSAVE5", 32, 0 }, - { "EXCSAVE6", 32, 0 }, - { "EXCSAVE7", 32, 0 }, - { "EPS2", 13, 0 }, - { "EPS3", 13, 0 }, - { "EPS4", 13, 0 }, - { "EPS5", 13, 0 }, - { "EPS6", 13, 0 }, - { "EPS7", 13, 0 }, - { "EXCCAUSE", 6, 0 }, - { "PSINTLEVEL", 4, 0 }, - { "PSUM", 1, 0 }, - { "PSWOE", 1, 0 }, - { "PSEXCM", 1, 0 }, - { "DEPC", 32, 0 }, - { "EXCVADDR", 32, 0 }, - { "WindowBase", 3, 0 }, - { "WindowStart", 8, 0 }, - { "PSCALLINC", 2, 0 }, - { "PSOWB", 4, 0 }, - { "LBEG", 32, 0 }, - { "LEND", 32, 0 }, - { "SAR", 6, 0 }, - { "MISC0", 32, 0 }, - { "MISC1", 32, 0 }, - { "InOCDMode", 1, 0 }, - { "INTENABLE", 22, 0 }, - { "DBREAKA0", 32, 0 }, - { "DBREAKC0", 8, 0 }, - { "DBREAKA1", 32, 0 }, - { "DBREAKC1", 8, 0 }, - { "IBREAKA0", 32, 0 }, - { "IBREAKA1", 32, 0 }, - { "IBREAKENABLE", 2, 0 }, - { "ICOUNTLEVEL", 4, 0 }, - { "DEBUGCAUSE", 6, 0 }, - { "DBNUM", 4, 0 }, - { "CCOMPARE0", 32, 0 }, - { "CCOMPARE1", 32, 0 }, - { "CCOMPARE2", 32, 0 }, - { "PREFCTL", 9, 0 }, - { "CPENABLE", 2, 0 }, - { "SCOMPARE1", 32, 0 }, - { "ATOMCTL", 6, 0 }, - { "AE_OVERFLOW", 1, XTENSA_STATE_IS_SHARED_OR }, - { "AE_SAR", 6, 0 }, - { "AE_BITHEAD", 32, 0 }, - { "AE_BITPTR", 4, 0 }, - { "AE_BITSUSED", 4, 0 }, - { "AE_TABLESIZE", 4, 0 }, - { "AE_FIRST_TS", 4, 0 }, - { "AE_NEXTOFFSET", 27, 0 }, - { "AE_SEARCHDONE", 1, 0 }, - { "AE_CBEGIN0", 32, 0 }, - { "AE_CEND0", 32, 0 }, - { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }, - { "MEPC", 32, 0}, - { "MEPS", 13, 0}, - { "MESAVE", 32, 0}, - { "MESR", 19, 0}, - { "MECR", 22, 0}, - { "MEVADDR", 32, 0}, - { "MEMCTL", 32, 0}, - { "ACCLO", 32, 0}, - { "ACCHI", 8, 0}, - { "THREADPTR", 32, 0}, -}; - -#define NUM_STATES ARRAY_SIZE(states) - -enum xtensa_state_id { - STATE_LCOUNT, - STATE_PC, - STATE_ICOUNT, - STATE_DDR, - STATE_INTERRUPT, - STATE_CCOUNT, - STATE_XTSYNC, - STATE_VECBASE, - STATE_EPC1, - STATE_EPC2, - STATE_EPC3, - STATE_EPC4, - STATE_EPC5, - STATE_EPC6, - STATE_EPC7, - STATE_EXCSAVE1, - STATE_EXCSAVE2, - STATE_EXCSAVE3, - STATE_EXCSAVE4, - STATE_EXCSAVE5, - STATE_EXCSAVE6, - STATE_EXCSAVE7, - STATE_EPS2, - STATE_EPS3, - STATE_EPS4, - STATE_EPS5, - STATE_EPS6, - STATE_EPS7, - STATE_EXCCAUSE, - STATE_PSINTLEVEL, - STATE_PSUM, - STATE_PSWOE, - STATE_PSEXCM, - STATE_DEPC, - STATE_EXCVADDR, - STATE_WindowBase, - STATE_WindowStart, - STATE_PSCALLINC, - STATE_PSOWB, - STATE_LBEG, - STATE_LEND, - STATE_SAR, - STATE_MISC0, - STATE_MISC1, - STATE_InOCDMode, - STATE_INTENABLE, - STATE_DBREAKA0, - STATE_DBREAKC0, - STATE_DBREAKA1, - STATE_DBREAKC1, - STATE_IBREAKA0, - STATE_IBREAKA1, - STATE_IBREAKENABLE, - STATE_ICOUNTLEVEL, - STATE_DEBUGCAUSE, - STATE_DBNUM, - STATE_CCOMPARE0, - STATE_CCOMPARE1, - STATE_CCOMPARE2, - STATE_PREFCTL, - STATE_CPENABLE, - STATE_SCOMPARE1, - STATE_ATOMCTL, - STATE_AE_OVERFLOW, - STATE_AE_SAR, - STATE_AE_BITHEAD, - STATE_AE_BITPTR, - STATE_AE_BITSUSED, - STATE_AE_TABLESIZE, - STATE_AE_FIRST_TS, - STATE_AE_NEXTOFFSET, - STATE_AE_SEARCHDONE, - STATE_AE_CBEGIN0, - STATE_AE_CEND0, - STATE_EXPSTATE, - STATE_MEPC, - STATE_MEPS, - STATE_MESAVE, - STATE_MESR, - STATE_MECR, - STATE_MEVADDR, - STATE_MEMCTL, - STATE_ACCLO, - STATE_ACCHI, - STATE_THREADPTR, -}; - - -/* Field definitions. */ - -static unsigned -Field_t_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_s_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_r_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_op2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); - return tie_t; -} - -static void -Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); -} - -static unsigned -Field_op1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_op0_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_n_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_m_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_sr_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_st_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ae_r3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_ae_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_ae_r10_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_ae_r32_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ae_s3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_ae_s3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_ae_s_non_samt_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_ae_s_non_samt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf61ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf61ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 22) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_op0_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - return tie_t; -} - -static void -Field_op0_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf330ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_ftsf330ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ftsf81ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf81ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ae_r20_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_ftsf73ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf73ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf35ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf35ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf34ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf34ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf32ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf32ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf33ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf33ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf96ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf96ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ae_s20_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); -} - -static unsigned -Field_ftsf94ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_ftsf94ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf347_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf347_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); -} - -static unsigned -Field_ftsf24ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - return tie_t; -} - -static void -Field_ftsf24ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf23ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - return tie_t; -} - -static void -Field_ftsf23ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf125ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_ftsf125ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_ftsf350ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); - return tie_t; -} - -static void -Field_ftsf350ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78) | (tie_t << 3); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf80ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf80ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf88ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf88ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 23) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf340_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf340_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_ftsf87ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf87ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x60) | (tie_t << 5); - tie_t = (val << 22) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf342ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_ftsf342ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_ftsf86ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); - return tie_t; -} - -static void -Field_ftsf86ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78) | (tie_t << 3); - tie_t = (val << 21) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf84ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); - return tie_t; -} - -static void -Field_ftsf84ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78) | (tie_t << 3); - tie_t = (val << 21) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf76ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf76ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf75ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf75ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf60ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf60ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 21) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf64ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf64ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 20) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf63ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf63ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ae_r10_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf59ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf59ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 21) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf119ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf119ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 24) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 21) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf338_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf338_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_ftsf69ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf69ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 22) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf67ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf67ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x60) | (tie_t << 5); - tie_t = (val << 21) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf66ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf66ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 20) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf25ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf25ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf36ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf36ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf103ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf103ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf349ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 23) >> 26); - return tie_t; -} - -static void -Field_ftsf349ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x1f8) | (tie_t << 3); -} - -static unsigned -Field_ftsf99ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf99ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf27ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf27ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf28ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf28ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf21ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf21ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf22ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf22ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf29ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf29ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf97ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf97ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf100ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf100ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf101ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - return tie_t; -} - -static void -Field_ftsf101ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf348ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); - return tie_t; -} - -static void -Field_ftsf348ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); -} - -static unsigned -Field_ftsf26ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf26ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf30ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf30ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf31ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf31ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf98ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf98ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf92ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); - return tie_t; -} - -static void -Field_ftsf92ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6) | (tie_t << 1); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf208_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf208_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); -} - -static unsigned -Field_ftsf91ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf91ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf90ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf90ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf126ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); - return tie_t; -} - -static void -Field_ftsf126ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); -} - -static unsigned -Field_ftsf344ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf344ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 23) >> 30; - insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); -} - -static unsigned -Field_ftsf112ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf112ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf122ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); - return tie_t; -} - -static void -Field_ftsf122ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); - tie_t = (val << 24) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf346ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf346ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf116ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); - return tie_t; -} - -static void -Field_ftsf116ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); - tie_t = (val << 20) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf109ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf109ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf111ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf111ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf104ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf104ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf105ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf105ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf107ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf107ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf113ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf113ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf118ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); - return tie_t; -} - -static void -Field_ftsf118ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); - tie_t = (val << 20) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf120ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 6) | ((insn[0] << 25) >> 26); - return tie_t; -} - -static void -Field_ftsf120ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x7e) | (tie_t << 1); - tie_t = (val << 23) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf343ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf343ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf108ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf108ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf115ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf115ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf110ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf110ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf114ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf114ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf37ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - return tie_t; -} - -static void -Field_ftsf37ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf78ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf78ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf79ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf79ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf77ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf77ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf13_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_ftsf13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf12_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - return tie_t; -} - -static void -Field_ftsf12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf82ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf82ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 24) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf341ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf341ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ftsf124ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf124ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 28) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf339ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf339ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ftsf106ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf106ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ae_r32_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ae_mul32x24fld_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ae_mul32x24fld_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf160ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf160ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf154ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf154ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf175ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf175ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf158ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf158ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf155ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf155ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf167ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf167ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf157ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf157ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf153ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf153ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf163ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf163ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf156ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf156ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf152ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf152ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf161ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf161ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf133ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf133ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf191ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf191ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf142ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf142ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf159ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf159ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf141ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf141ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf130ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf130ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf143ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf143ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf140ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf140ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf211ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_ftsf211ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_ftsf332ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf332ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_ftsf135ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf135ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf138ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf138ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf176ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf176ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf170ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf170ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf184ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf184ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf174ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf174ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf171ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf171ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf182ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf182ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf173ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf173ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf169ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf169ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf181ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf181ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf172ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf172ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf168ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf168ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf180ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf180ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf139ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf139ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf151ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf151ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf137ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf137ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf136ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf136ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf145ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf145ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf134ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf134ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf144ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf144ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf178ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf178ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf188ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf188ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf183ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf183ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf186ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf186ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf179ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf179ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf187ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf187ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf177ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf177ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf185ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf185ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf45ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf45ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf44ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf44ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf48ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf48ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf47ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf47ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf49ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf49ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf50ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf50ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf52ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf52ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf51ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf51ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf38ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf38ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf54ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf54ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf40ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf40ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf39ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf39ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf46ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf46ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf42ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf42ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf43ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf43ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf41ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf41ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf55ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf55ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf53ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf53ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf58ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf58ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf56ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf56ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf72ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf72ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 26) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf71ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf71ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 26) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf57ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf57ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf89ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_ftsf89ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_ftsf334ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf334ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_ftsf195ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf195ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf207ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf207ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf336ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; -} - -static void -Field_ftsf336ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); -} - -static unsigned -Field_ftsf199ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf199ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf210ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} - -static void -Field_ftsf210ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf337ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf337ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_ftsf194ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf194ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf197ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf197ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf196ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf196ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf198ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf198ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf200ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf200ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf203ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf203ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf201ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf201ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf202ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf202ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf204ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf204ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf206ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf206ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf205ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf205ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf209ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf209ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf127ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf127ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf129ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf129ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf128ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf128ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf146ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf146ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf149ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf149ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf148ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf148ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf150ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf150ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf162ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf162ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf165ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf165ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf164ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf164ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf166ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf166ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf189ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf189ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf192ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf192ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf190ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf190ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf193ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf193ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_combined1b97e84f_fld49_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld49_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_combined1b97e84f_fld54_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld54_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_combined1b97e84f_fld51_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld51_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined1b97e84f_fld23_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld23_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_op0_s3_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - return tie_t; -} - -static void -Field_op0_s3_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_combined1b97e84f_fld17_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld17_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); -} - -static unsigned -Field_combined1b97e84f_fld76_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld76_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2) | (tie_t << 1); -} - -static unsigned -Field_combined1b97e84f_fld73_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld73_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); -} - -static unsigned -Field_combined1b97e84f_fld62_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld62_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld24_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld24_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_combined1b97e84f_fld70_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld70_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_combined1b97e84f_fld58_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld58_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); -} - -static unsigned -Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_xt_fld0_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 9) >> 16); - return tie_t; -} - -static void -Field_xt_fld0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0x7fff80) | (tie_t << 7); -} - -static unsigned -Field_xt_fld1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_xt_fld1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_op0_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); - return tie_t; -} - -static void -Field_op0_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); -} - -static unsigned -Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - return tie_t; -} - -static void -Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_ftsf293_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_ftsf293_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_ftsf321_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf321_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_ae_s20_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); -} - -static unsigned -Field_ftsf214ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_ftsf214ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf213ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); - return tie_t; -} - -static void -Field_ftsf213ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); -} - -static unsigned -Field_ftsf212ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_ftsf212ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_ftsf281ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_ftsf281ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); - tie_t = (val << 16) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf217_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf217_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_ae_r20_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_ftsf300ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - return tie_t; -} - -static void -Field_ftsf300ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf283ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); - return tie_t; -} - -static void -Field_ftsf283ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 17) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf352ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf352ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf282ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_ftsf282ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); - tie_t = (val << 16) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf288ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); - return tie_t; -} - -static void -Field_ftsf288ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x38) | (tie_t << 3); - tie_t = (val << 21) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf359ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf359ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf286ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); - return tie_t; -} - -static void -Field_ftsf286ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf356ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf356ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf284ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 5) | ((insn[0] << 26) >> 27); - return tie_t; -} - -static void -Field_ftsf284ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x3e) | (tie_t << 1); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf354ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf354ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf295ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_ftsf295ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf358ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf358ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf325ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf325ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf215ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); - return tie_t; -} - -static void -Field_ftsf215ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); -} - -static unsigned -Field_ftsf301ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19); - return tie_t; -} - -static void -Field_ftsf301ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 19) >> 19; - insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf353_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf353_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_ftsf309ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23); - return tie_t; -} - -static void -Field_ftsf309ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0xff800) | (tie_t << 11); -} - -static unsigned -Field_ftsf360ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 21) >> 27); - return tie_t; -} - -static void -Field_ftsf360ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x7c0) | (tie_t << 6); -} - -static unsigned -Field_ftsf294ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_ftsf294ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); - tie_t = (val << 21) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf292ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_ftsf292ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); - tie_t = (val << 21) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf319_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; -} - -static void -Field_ftsf319_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); -} - -static unsigned -Field_ftsf361ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf361ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_ftsf218ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf218ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf220ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf220ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf221ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf221ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf222ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf222ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf228ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf228ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf229ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf229ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf230ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf230ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf232ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf232ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf233ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf233ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf235ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf235ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf239ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf239ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf234ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf234ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf224ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf224ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf225ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf225ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf227ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf227ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf226ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf226ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf241ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf241ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf243ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf243ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf242ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf242ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf244ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf244ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf236ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf236ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf237ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf237ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf238ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf238ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf240ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf240ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf261ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf261ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf296ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf296ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf248ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf248ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf250ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf250ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf269ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf269ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf264ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf264ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf266ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf266ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf267ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf267ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf260ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf260ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf262ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf262ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf263ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf263ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf265ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf265ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf246ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf246ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf247ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf247ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf249ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf249ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf253ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf253ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf257ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf257ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf256ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf256ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf258ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf258ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf259ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf259ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf251ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf251ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf252ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf252ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf254ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf254ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf255ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf255ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf275ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf275ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf277ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf277ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf278ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf278ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf290ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_ftsf290ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_ftsf272ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf272ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf276ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf276ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf273ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf273ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf274ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf274ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf297ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf297ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf298ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf298ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf310ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf310ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf311ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf311ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf270ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf270ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf271ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf271ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ae_r32_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf329ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); - return tie_t; -} - -static void -Field_ftsf329ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); -} - -static unsigned -Field_ftsf362ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf362ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 27) >> 29; - insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); -} - -static unsigned -Field_combined4b12daa6_fld85_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld85_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_combined4b12daa6_fld122_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld122_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x200) | (tie_t << 9); -} - -static unsigned -Field_combined4b12daa6_fld119_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld119_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x400) | (tie_t << 10); -} - -static unsigned -Field_combined4b12daa6_fld97_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); - return tie_t; -} - -static void -Field_combined4b12daa6_fld97_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); -} - -static unsigned -Field_combined4b12daa6_fld124_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld124_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_combined4b12daa6_fld79_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld79_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_combined4b12daa6_fld80_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld80_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); -} - -static unsigned -Field_combined4b12daa6_fld108_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_combined4b12daa6_fld108_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_op0_s4_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); - return tie_t; -} - -static void -Field_op0_s4_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); -} - -static unsigned -Field_combined4b12daa6_fld115_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld115_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_ftsf245ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf245ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf268ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf268ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf313ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf313ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf312ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf312ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf231ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf231ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf223ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf223ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf219ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf219ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf216ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf216ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf302ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf302ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 17) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf364ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf364ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_ftsf322ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf322ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf279ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); - return tie_t; -} - -static void -Field_ftsf279ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); - tie_t = (val << 18) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf318ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; -} - -static void -Field_ftsf318ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); - tie_t = (val << 28) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf365ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf365ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_ftsf316ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf316ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf314ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf314ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf315ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf315ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf320ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf320ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf299ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); - return tie_t; -} - -static void -Field_ftsf299ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 22) >> 22; - insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); -} - -static unsigned -Field_ftsf308ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21); - return tie_t; -} - -static void -Field_ftsf308ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 21) >> 21; - insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf366ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf366ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_ftsf306ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_ftsf306ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); - tie_t = (val << 19) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf368ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf368ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); - tie_t = (val << 29) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_ftsf304ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); - return tie_t; -} - -static void -Field_ftsf304ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6) | (tie_t << 1); - tie_t = (val << 18) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf369ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf369ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_ftsf323ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf323ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf328ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf328ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf326ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); - return tie_t; -} - -static void -Field_ftsf326ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc) | (tie_t << 2); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf357_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf357_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); -} - -static unsigned -Field_ftsf303ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf303ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 17) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf324ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf324ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf317ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf317ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld101_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld101_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); -} - -static unsigned -Field_combined1b97e84f_fld88_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld88_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2) | (tie_t << 1); -} - -static unsigned -Field_combined1b97e84f_fld39_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld39_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); -} - -static unsigned -Field_combined1b97e84f_fld115_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld115_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined1b97e84f_fld97_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); - return tie_t; -} - -static void -Field_combined1b97e84f_fld97_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); -} - -static unsigned -Field_combined1b97e84f_fld124_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld124_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld79_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld79_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_combined1b97e84f_fld80_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld80_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); -} - -static unsigned -Field_combined1b97e84f_fld108_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_combined1b97e84f_fld108_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld83_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld83_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld93_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld93_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_combined1b97e84f_fld90_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld90_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); -} - -static unsigned -Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_bbi_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); - return tie_t; -} - -static void -Field_bbi_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); -} - -static unsigned -Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); - return tie_t; -} - -static void -Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); -} - -static unsigned -Field_imm12_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_imm12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); -} - -static unsigned -Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); - return tie_t; -} - -static void -Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); -} - -static unsigned -Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); - return tie_t; -} - -static void -Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); -} - -static unsigned -Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); - return tie_t; -} - -static void -Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); -} - -static unsigned -Field_offset_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); - return tie_t; -} - -static void -Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); -} - -static unsigned -Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - return tie_t; -} - -static void -Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sae_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27); - return tie_t; -} - -static void -Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12); -} - -static unsigned -Field_sal_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); - return tie_t; -} - -static void -Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); -} - -static unsigned -Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sas_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); - return tie_t; -} - -static void -Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); -} - -static unsigned -Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_mn_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_t2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t2_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_t2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_s2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_r2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} - -static unsigned -Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} - -static unsigned -Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} - -static unsigned -Field_t4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_s4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_r4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_t8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_s8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_r8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); - return tie_t; -} - -static void -Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 17) >> 17; - insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); -} - -static unsigned -Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_ae_samt_s_t_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); - return tie_t; -} - -static void -Field_ae_samt_s_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); -} - -static unsigned -Field_ae_samt_s_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ae_samt_s_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -} - -static unsigned -Field_ae_r20_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); -} - -static unsigned -Field_ae_r10_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_ae_s20_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); -} - -static unsigned -Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_ftsf12_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf13_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf13_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_ftsf14_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf14_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); -} - -static unsigned -Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_bitindex_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s3to1_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static void -Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, - uint32 val ATTRIBUTE_UNUSED) -{ - /* Do nothing. */ -} - -static unsigned -Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 4; -} - -static unsigned -Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 8; -} - -static unsigned -Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 12; -} - -static unsigned -Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -enum xtensa_field_id { - FIELD_t, - FIELD_bbi4, - FIELD_bbi, - FIELD_imm12, - FIELD_imm8, - FIELD_s, - FIELD_imm12b, - FIELD_imm16, - FIELD_m, - FIELD_n, - FIELD_offset, - FIELD_op0, - FIELD_op1, - FIELD_op2, - FIELD_r, - FIELD_sa4, - FIELD_sae4, - FIELD_sae, - FIELD_sal, - FIELD_sargt, - FIELD_sas4, - FIELD_sas, - FIELD_sr, - FIELD_st, - FIELD_thi3, - FIELD_imm4, - FIELD_mn, - FIELD_i, - FIELD_imm6lo, - FIELD_imm6hi, - FIELD_imm7lo, - FIELD_imm7hi, - FIELD_z, - FIELD_imm6, - FIELD_imm7, - FIELD_t2, - FIELD_s2, - FIELD_r2, - FIELD_t4, - FIELD_s4, - FIELD_r4, - FIELD_t8, - FIELD_s8, - FIELD_r8, - FIELD_xt_wbr15_imm, - FIELD_xt_wbr18_imm, - FIELD_ae_r3, - FIELD_ae_s_non_samt, - FIELD_ae_s3, - FIELD_ae_r32, - FIELD_ae_samt_s_t, - FIELD_ae_r20, - FIELD_ae_r10, - FIELD_ae_s20, - FIELD_ae_fld_ohba, - FIELD_ae_fld_ohba2, - FIELD_op0_s3, - FIELD_ftsf12, - FIELD_ftsf13, - FIELD_ftsf14, - FIELD_ftsf21ae_slot1, - FIELD_ftsf22ae_slot1, - FIELD_ftsf23ae_slot1, - FIELD_ftsf24ae_slot1, - FIELD_ftsf25ae_slot1, - FIELD_ftsf26ae_slot1, - FIELD_ftsf27ae_slot1, - FIELD_ftsf28ae_slot1, - FIELD_ftsf29ae_slot1, - FIELD_ftsf30ae_slot1, - FIELD_ftsf31ae_slot1, - FIELD_ftsf32ae_slot1, - FIELD_ftsf33ae_slot1, - FIELD_ftsf34ae_slot1, - FIELD_ftsf35ae_slot1, - FIELD_ftsf36ae_slot1, - FIELD_ftsf37ae_slot1, - FIELD_ftsf38ae_slot1, - FIELD_ftsf39ae_slot1, - FIELD_ftsf40ae_slot1, - FIELD_ftsf41ae_slot1, - FIELD_ftsf42ae_slot1, - FIELD_ftsf43ae_slot1, - FIELD_ftsf44ae_slot1, - FIELD_ftsf45ae_slot1, - FIELD_ftsf46ae_slot1, - FIELD_ftsf47ae_slot1, - FIELD_ftsf48ae_slot1, - FIELD_ftsf49ae_slot1, - FIELD_ftsf50ae_slot1, - FIELD_ftsf51ae_slot1, - FIELD_ftsf52ae_slot1, - FIELD_ftsf53ae_slot1, - FIELD_ftsf54ae_slot1, - FIELD_ftsf55ae_slot1, - FIELD_ftsf56ae_slot1, - FIELD_ftsf57ae_slot1, - FIELD_ftsf58ae_slot1, - FIELD_ftsf59ae_slot1, - FIELD_ftsf60ae_slot1, - FIELD_ftsf61ae_slot1, - FIELD_ftsf63ae_slot1, - FIELD_ftsf64ae_slot1, - FIELD_ftsf66ae_slot1, - FIELD_ftsf67ae_slot1, - FIELD_ftsf69ae_slot1, - FIELD_ftsf71ae_slot1, - FIELD_ftsf72ae_slot1, - FIELD_ftsf73ae_slot1, - FIELD_ftsf75ae_slot1, - FIELD_ftsf76ae_slot1, - FIELD_ftsf77ae_slot1, - FIELD_ftsf78ae_slot1, - FIELD_ftsf79ae_slot1, - FIELD_ftsf80ae_slot1, - FIELD_ftsf81ae_slot1, - FIELD_ftsf82ae_slot1, - FIELD_ftsf84ae_slot1, - FIELD_ftsf86ae_slot1, - FIELD_ftsf87ae_slot1, - FIELD_ftsf88ae_slot1, - FIELD_ftsf89ae_slot1, - FIELD_ftsf90ae_slot1, - FIELD_ftsf91ae_slot1, - FIELD_ftsf92ae_slot1, - FIELD_ftsf94ae_slot1, - FIELD_ftsf96ae_slot1, - FIELD_ftsf97ae_slot1, - FIELD_ftsf98ae_slot1, - FIELD_ftsf99ae_slot1, - FIELD_ftsf100ae_slot1, - FIELD_ftsf101ae_slot1, - FIELD_ftsf103ae_slot1, - FIELD_ftsf104ae_slot1, - FIELD_ftsf105ae_slot1, - FIELD_ftsf106ae_slot1, - FIELD_ftsf107ae_slot1, - FIELD_ftsf108ae_slot1, - FIELD_ftsf109ae_slot1, - FIELD_ftsf110ae_slot1, - FIELD_ftsf111ae_slot1, - FIELD_ftsf112ae_slot1, - FIELD_ftsf113ae_slot1, - FIELD_ftsf114ae_slot1, - FIELD_ftsf115ae_slot1, - FIELD_ftsf116ae_slot1, - FIELD_ftsf118ae_slot1, - FIELD_ftsf119ae_slot1, - FIELD_ftsf120ae_slot1, - FIELD_ftsf122ae_slot1, - FIELD_ftsf124ae_slot1, - FIELD_ftsf125ae_slot1, - FIELD_ftsf126ae_slot1, - FIELD_ftsf127ae_slot1, - FIELD_ftsf128ae_slot1, - FIELD_ftsf129ae_slot1, - FIELD_ftsf130ae_slot1, - FIELD_ftsf131ae_slot1, - FIELD_ftsf132ae_slot1, - FIELD_ftsf133ae_slot1, - FIELD_ftsf134ae_slot1, - FIELD_ftsf135ae_slot1, - FIELD_ftsf136ae_slot1, - FIELD_ftsf137ae_slot1, - FIELD_ftsf138ae_slot1, - FIELD_ftsf139ae_slot1, - FIELD_ftsf140ae_slot1, - FIELD_ftsf141ae_slot1, - FIELD_ftsf142ae_slot1, - FIELD_ftsf143ae_slot1, - FIELD_ftsf144ae_slot1, - FIELD_ftsf145ae_slot1, - FIELD_ftsf146ae_slot1, - FIELD_ftsf147ae_slot1, - FIELD_ftsf148ae_slot1, - FIELD_ftsf149ae_slot1, - FIELD_ftsf150ae_slot1, - FIELD_ftsf151ae_slot1, - FIELD_ftsf152ae_slot1, - FIELD_ftsf153ae_slot1, - FIELD_ftsf154ae_slot1, - FIELD_ftsf155ae_slot1, - FIELD_ftsf156ae_slot1, - FIELD_ftsf157ae_slot1, - FIELD_ftsf158ae_slot1, - FIELD_ftsf159ae_slot1, - FIELD_ftsf160ae_slot1, - FIELD_ftsf161ae_slot1, - FIELD_ftsf162ae_slot1, - FIELD_ftsf163ae_slot1, - FIELD_ftsf164ae_slot1, - FIELD_ftsf165ae_slot1, - FIELD_ftsf166ae_slot1, - FIELD_ftsf167ae_slot1, - FIELD_ftsf168ae_slot1, - FIELD_ftsf169ae_slot1, - FIELD_ftsf170ae_slot1, - FIELD_ftsf171ae_slot1, - FIELD_ftsf172ae_slot1, - FIELD_ftsf173ae_slot1, - FIELD_ftsf174ae_slot1, - FIELD_ftsf175ae_slot1, - FIELD_ftsf176ae_slot1, - FIELD_ftsf177ae_slot1, - FIELD_ftsf178ae_slot1, - FIELD_ftsf179ae_slot1, - FIELD_ftsf180ae_slot1, - FIELD_ftsf181ae_slot1, - FIELD_ftsf182ae_slot1, - FIELD_ftsf183ae_slot1, - FIELD_ftsf184ae_slot1, - FIELD_ftsf185ae_slot1, - FIELD_ftsf186ae_slot1, - FIELD_ftsf187ae_slot1, - FIELD_ftsf188ae_slot1, - FIELD_ftsf189ae_slot1, - FIELD_ftsf190ae_slot1, - FIELD_ftsf191ae_slot1, - FIELD_ftsf192ae_slot1, - FIELD_ftsf193ae_slot1, - FIELD_ftsf194ae_slot1, - FIELD_ftsf195ae_slot1, - FIELD_ftsf196ae_slot1, - FIELD_ftsf197ae_slot1, - FIELD_ftsf198ae_slot1, - FIELD_ftsf199ae_slot1, - FIELD_ftsf200ae_slot1, - FIELD_ftsf201ae_slot1, - FIELD_ftsf202ae_slot1, - FIELD_ftsf203ae_slot1, - FIELD_ftsf204ae_slot1, - FIELD_ftsf205ae_slot1, - FIELD_ftsf206ae_slot1, - FIELD_ftsf207ae_slot1, - FIELD_ftsf208, - FIELD_ftsf209ae_slot1, - FIELD_ftsf210ae_slot1, - FIELD_ftsf211ae_slot1, - FIELD_ftsf330ae_slot1, - FIELD_ftsf332ae_slot1, - FIELD_ftsf334ae_slot1, - FIELD_ftsf336ae_slot1, - FIELD_ftsf337ae_slot1, - FIELD_ftsf338, - FIELD_ftsf339ae_slot1, - FIELD_ftsf340, - FIELD_ftsf341ae_slot1, - FIELD_ftsf342ae_slot1, - FIELD_ftsf343ae_slot1, - FIELD_ftsf344ae_slot1, - FIELD_ftsf346ae_slot1, - FIELD_ftsf347, - FIELD_ftsf348ae_slot1, - FIELD_ftsf349ae_slot1, - FIELD_ftsf350ae_slot1, - FIELD_op0_s4, - FIELD_ftsf212ae_slot0, - FIELD_ftsf213ae_slot0, - FIELD_ftsf214ae_slot0, - FIELD_ftsf215ae_slot0, - FIELD_ftsf216ae_slot0, - FIELD_ftsf217, - FIELD_ftsf218ae_slot0, - FIELD_ftsf219ae_slot0, - FIELD_ftsf220ae_slot0, - FIELD_ftsf221ae_slot0, - FIELD_ftsf222ae_slot0, - FIELD_ftsf223ae_slot0, - FIELD_ftsf224ae_slot0, - FIELD_ftsf225ae_slot0, - FIELD_ftsf226ae_slot0, - FIELD_ftsf227ae_slot0, - FIELD_ftsf228ae_slot0, - FIELD_ftsf229ae_slot0, - FIELD_ftsf230ae_slot0, - FIELD_ftsf231ae_slot0, - FIELD_ftsf232ae_slot0, - FIELD_ftsf233ae_slot0, - FIELD_ftsf234ae_slot0, - FIELD_ftsf235ae_slot0, - FIELD_ftsf236ae_slot0, - FIELD_ftsf237ae_slot0, - FIELD_ftsf238ae_slot0, - FIELD_ftsf239ae_slot0, - FIELD_ftsf240ae_slot0, - FIELD_ftsf241ae_slot0, - FIELD_ftsf242ae_slot0, - FIELD_ftsf243ae_slot0, - FIELD_ftsf244ae_slot0, - FIELD_ftsf245ae_slot0, - FIELD_ftsf246ae_slot0, - FIELD_ftsf247ae_slot0, - FIELD_ftsf248ae_slot0, - FIELD_ftsf249ae_slot0, - FIELD_ftsf250ae_slot0, - FIELD_ftsf251ae_slot0, - FIELD_ftsf252ae_slot0, - FIELD_ftsf253ae_slot0, - FIELD_ftsf254ae_slot0, - FIELD_ftsf255ae_slot0, - FIELD_ftsf256ae_slot0, - FIELD_ftsf257ae_slot0, - FIELD_ftsf258ae_slot0, - FIELD_ftsf259ae_slot0, - FIELD_ftsf260ae_slot0, - FIELD_ftsf261ae_slot0, - FIELD_ftsf262ae_slot0, - FIELD_ftsf263ae_slot0, - FIELD_ftsf264ae_slot0, - FIELD_ftsf265ae_slot0, - FIELD_ftsf266ae_slot0, - FIELD_ftsf267ae_slot0, - FIELD_ftsf268ae_slot0, - FIELD_ftsf269ae_slot0, - FIELD_ftsf270ae_slot0, - FIELD_ftsf271ae_slot0, - FIELD_ftsf272ae_slot0, - FIELD_ftsf273ae_slot0, - FIELD_ftsf274ae_slot0, - FIELD_ftsf275ae_slot0, - FIELD_ftsf276ae_slot0, - FIELD_ftsf277ae_slot0, - FIELD_ftsf278ae_slot0, - FIELD_ftsf279ae_slot0, - FIELD_ftsf281ae_slot0, - FIELD_ftsf282ae_slot0, - FIELD_ftsf283ae_slot0, - FIELD_ftsf284ae_slot0, - FIELD_ftsf286ae_slot0, - FIELD_ftsf288ae_slot0, - FIELD_ftsf290ae_slot0, - FIELD_ftsf292ae_slot0, - FIELD_ftsf293, - FIELD_ftsf294ae_slot0, - FIELD_ftsf295ae_slot0, - FIELD_ftsf296ae_slot0, - FIELD_ftsf297ae_slot0, - FIELD_ftsf298ae_slot0, - FIELD_ftsf299ae_slot0, - FIELD_ftsf300ae_slot0, - FIELD_ftsf301ae_slot0, - FIELD_ftsf302ae_slot0, - FIELD_ftsf303ae_slot0, - FIELD_ftsf304ae_slot0, - FIELD_ftsf306ae_slot0, - FIELD_ftsf308ae_slot0, - FIELD_ftsf309ae_slot0, - FIELD_ftsf310ae_slot0, - FIELD_ftsf311ae_slot0, - FIELD_ftsf312ae_slot0, - FIELD_ftsf313ae_slot0, - FIELD_ftsf314ae_slot0, - FIELD_ftsf315ae_slot0, - FIELD_ftsf316ae_slot0, - FIELD_ftsf317ae_slot0, - FIELD_ftsf318ae_slot0, - FIELD_ftsf319, - FIELD_ftsf320ae_slot0, - FIELD_ftsf321, - FIELD_ftsf322ae_slot0, - FIELD_ftsf323ae_slot0, - FIELD_ftsf324ae_slot0, - FIELD_ftsf325ae_slot0, - FIELD_ftsf326ae_slot0, - FIELD_ftsf328ae_slot0, - FIELD_ftsf329ae_slot0, - FIELD_ftsf352ae_slot0, - FIELD_ftsf353, - FIELD_ftsf354ae_slot0, - FIELD_ftsf356ae_slot0, - FIELD_ftsf357, - FIELD_ftsf358ae_slot0, - FIELD_ftsf359ae_slot0, - FIELD_ftsf360ae_slot0, - FIELD_ftsf361ae_slot0, - FIELD_ftsf362ae_slot0, - FIELD_ftsf364ae_slot0, - FIELD_ftsf365ae_slot0, - FIELD_ftsf366ae_slot0, - FIELD_ftsf368ae_slot0, - FIELD_ftsf369ae_slot0, - FIELD_ae_mul32x24fld, - FIELD_combined1b97e84f_fld115, - FIELD_combined1b97e84f_fld97, - FIELD_combined1b97e84f_fld124, - FIELD_combined1b97e84f_fld79, - FIELD_combined1b97e84f_fld80, - FIELD_combined1b97e84f_fld108, - FIELD_combined1b97e84f_fld101, - FIELD_combined1b97e84f_fld88, - FIELD_combined1b97e84f_fld39, - FIELD_op0_s4_s4, - FIELD_combined1b97e84f_fld83, - FIELD_combined1b97e84f_fld90, - FIELD_combined1b97e84f_fld93, - FIELD_combined1b97e84f_fld138ae_slot0, - FIELD_combined1b97e84f_fld130ae_slot0, - FIELD_combined1b97e84f_fld137ae_slot0, - FIELD_combined1b97e84f_fld135ae_slot0, - FIELD_combined1b97e84f_fld136ae_slot0, - FIELD_combined1b97e84f_fld129ae_slot0, - FIELD_combined1b97e84f_fld127ae_slot0, - FIELD_combined1b97e84f_fld128ae_slot0, - FIELD_combined1b97e84f_fld132ae_slot0, - FIELD_combined1b97e84f_fld134ae_slot0, - FIELD_combined4b12daa6_fld122, - FIELD_combined4b12daa6_fld115, - FIELD_combined4b12daa6_fld85, - FIELD_combined4b12daa6_fld119, - FIELD_combined4b12daa6_fld97, - FIELD_combined4b12daa6_fld124, - FIELD_combined4b12daa6_fld79, - FIELD_combined4b12daa6_fld80, - FIELD_combined4b12daa6_fld108, - FIELD_combined1b97e84f_fld54, - FIELD_combined1b97e84f_fld17, - FIELD_combined1b97e84f_fld76, - FIELD_combined1b97e84f_fld73, - FIELD_combined1b97e84f_fld62, - FIELD_combined1b97e84f_fld24, - FIELD_combined1b97e84f_fld70, - FIELD_combined1b97e84f_fld58, - FIELD_combined1b97e84f_fld131ae_slot1, - FIELD_op0_s3_s3, - FIELD_combined1b97e84f_fld49, - FIELD_combined1b97e84f_fld51, - FIELD_combined1b97e84f_fld23, - FIELD_xt_fld0, - FIELD_xt_fld1, - FIELD_bitindex, - FIELD_s3to1, - FIELD__ar0, - FIELD__ar4, - FIELD__ar8, - FIELD__ar12, - FIELD__bt16, - FIELD__bs16, - FIELD__br16, - FIELD__brall -}; - - -/* Functional units. */ - -static xtensa_funcUnit_internal funcUnits[] = { - { "ae_add32", 1 }, - { "ae_shift32x4", 1 }, - { "ae_shift32x5", 1 }, - { "ae_subshift", 1 } -}; - -enum xtensa_funcUnit_id { - FUNCUNIT_ae_add32, - FUNCUNIT_ae_shift32x4, - FUNCUNIT_ae_shift32x5, - FUNCUNIT_ae_subshift -}; - - -/* Register files. */ - -enum xtensa_regfile_id { - REGFILE_AR, - REGFILE_BR, - REGFILE_AE_PR, - REGFILE_AE_QR, - REGFILE_BR2, - REGFILE_BR4, - REGFILE_BR8, - REGFILE_BR16 -}; - -static xtensa_regfile_internal regfiles[] = { - { "AR", "a", REGFILE_AR, 32, 32 }, - { "BR", "b", REGFILE_BR, 1, 16 }, - { "AE_PR", "aep", REGFILE_AE_PR, 48, 8 }, - { "AE_QR", "aeq", REGFILE_AE_QR, 56, 4 }, - { "BR2", "b", REGFILE_BR, 2, 8 }, - { "BR4", "b", REGFILE_BR, 4, 4 }, - { "BR8", "b", REGFILE_BR, 8, 2 }, - { "BR16", "b", REGFILE_BR, 16, 1 } -}; - - -/* Interfaces. */ - -static xtensa_interface_internal interfaces[] = { - { "IPQ_Empty", 1, 0, 0, 'i' }, - { "IPQ", 32, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 0, 'i' }, - { "IPQ_NOTRDY", 1, 0, 0, 'i' }, - { "IPQ_KILL", 1, 0, 0, 'o' }, - { "OPQ_Full", 1, 0, 1, 'i' }, - { "OPQ", 32, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 1, 'o' }, - { "OPQ_NOTRDY", 1, 0, 1, 'i' }, - { "OPQ_KILL", 1, 0, 1, 'o' }, - { "IMPWIRE", 32, 0, 2, 'i' } -}; - -enum xtensa_interface_id { - INTERFACE_IPQ_Empty, - INTERFACE_IPQ, - INTERFACE_IPQ_NOTRDY, - INTERFACE_IPQ_KILL, - INTERFACE_OPQ_Full, - INTERFACE_OPQ, - INTERFACE_OPQ_NOTRDY, - INTERFACE_OPQ_KILL, - INTERFACE_IMPWIRE -}; - - -/* Constant tables. */ - -/* constant table ai4c */ -static const unsigned CONST_TBL_ai4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0x9, - 0xa, - 0xb, - 0xc, - 0xd, - 0xe, - 0xf, - 0 -}; - -/* constant table b4c */ -static const unsigned CONST_TBL_b4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - -/* constant table b4cu */ -static const unsigned CONST_TBL_b4cu_0[] = { - 0x8000, - 0x10000, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - - -/* Instruction operands. */ - -static int -OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) -{ - unsigned soffsetx4_out_0; - unsigned soffsetx4_in_0; - soffsetx4_in_0 = *valp & 0x3ffff; - soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); - *valp = soffsetx4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) -{ - unsigned soffsetx4_in_0; - unsigned soffsetx4_out_0; - soffsetx4_out_0 = *valp; - soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; - *valp = soffsetx4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) -{ - unsigned uimm12x8_out_0; - unsigned uimm12x8_in_0; - uimm12x8_in_0 = *valp & 0xfff; - uimm12x8_out_0 = uimm12x8_in_0 << 3; - *valp = uimm12x8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) -{ - unsigned uimm12x8_in_0; - unsigned uimm12x8_out_0; - uimm12x8_out_0 = *valp; - uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); - *valp = uimm12x8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm4_decode (uint32 *valp) -{ - unsigned simm4_out_0; - unsigned simm4_in_0; - simm4_in_0 = *valp & 0xf; - simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; - *valp = simm4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm4_encode (uint32 *valp) -{ - unsigned simm4_in_0; - unsigned simm4_out_0; - simm4_out_0 = *valp; - simm4_in_0 = (simm4_out_0 & 0xf); - *valp = simm4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_0_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_1_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_2_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_3_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_4_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_immrx4_decode (uint32 *valp) -{ - unsigned immrx4_out_0; - unsigned immrx4_in_0; - immrx4_in_0 = *valp & 0xf; - immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; - *valp = immrx4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_immrx4_encode (uint32 *valp) -{ - unsigned immrx4_in_0; - unsigned immrx4_out_0; - immrx4_out_0 = *valp; - immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); - *valp = immrx4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) -{ - unsigned lsi4x4_out_0; - unsigned lsi4x4_in_0; - lsi4x4_in_0 = *valp & 0xf; - lsi4x4_out_0 = lsi4x4_in_0 << 2; - *valp = lsi4x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) -{ - unsigned lsi4x4_in_0; - unsigned lsi4x4_out_0; - lsi4x4_out_0 = *valp; - lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); - *valp = lsi4x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm7_decode (uint32 *valp) -{ - unsigned simm7_out_0; - unsigned simm7_in_0; - simm7_in_0 = *valp & 0x7f; - simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; - *valp = simm7_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm7_encode (uint32 *valp) -{ - unsigned simm7_in_0; - unsigned simm7_out_0; - simm7_out_0 = *valp; - simm7_in_0 = (simm7_out_0 & 0x7f); - *valp = simm7_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm6_decode (uint32 *valp) -{ - unsigned uimm6_out_0; - unsigned uimm6_in_0; - uimm6_in_0 = *valp & 0x3f; - uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); - *valp = uimm6_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm6_encode (uint32 *valp) -{ - unsigned uimm6_in_0; - unsigned uimm6_out_0; - uimm6_out_0 = *valp; - uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; - *valp = uimm6_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ai4const_decode (uint32 *valp) -{ - unsigned ai4const_out_0; - unsigned ai4const_in_0; - ai4const_in_0 = *valp & 0xf; - ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; - *valp = ai4const_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ai4const_encode (uint32 *valp) -{ - unsigned ai4const_in_0; - unsigned ai4const_out_0; - ai4const_out_0 = *valp; - switch (ai4const_out_0) - { - case 0xffffffff: ai4const_in_0 = 0; break; - case 0x1: ai4const_in_0 = 0x1; break; - case 0x2: ai4const_in_0 = 0x2; break; - case 0x3: ai4const_in_0 = 0x3; break; - case 0x4: ai4const_in_0 = 0x4; break; - case 0x5: ai4const_in_0 = 0x5; break; - case 0x6: ai4const_in_0 = 0x6; break; - case 0x7: ai4const_in_0 = 0x7; break; - case 0x8: ai4const_in_0 = 0x8; break; - case 0x9: ai4const_in_0 = 0x9; break; - case 0xa: ai4const_in_0 = 0xa; break; - case 0xb: ai4const_in_0 = 0xb; break; - case 0xc: ai4const_in_0 = 0xc; break; - case 0xd: ai4const_in_0 = 0xd; break; - case 0xe: ai4const_in_0 = 0xe; break; - default: ai4const_in_0 = 0xf; break; - } - *valp = ai4const_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4const_decode (uint32 *valp) -{ - unsigned b4const_out_0; - unsigned b4const_in_0; - b4const_in_0 = *valp & 0xf; - b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; - *valp = b4const_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4const_encode (uint32 *valp) -{ - unsigned b4const_in_0; - unsigned b4const_out_0; - b4const_out_0 = *valp; - switch (b4const_out_0) - { - case 0xffffffff: b4const_in_0 = 0; break; - case 0x1: b4const_in_0 = 0x1; break; - case 0x2: b4const_in_0 = 0x2; break; - case 0x3: b4const_in_0 = 0x3; break; - case 0x4: b4const_in_0 = 0x4; break; - case 0x5: b4const_in_0 = 0x5; break; - case 0x6: b4const_in_0 = 0x6; break; - case 0x7: b4const_in_0 = 0x7; break; - case 0x8: b4const_in_0 = 0x8; break; - case 0xa: b4const_in_0 = 0x9; break; - case 0xc: b4const_in_0 = 0xa; break; - case 0x10: b4const_in_0 = 0xb; break; - case 0x20: b4const_in_0 = 0xc; break; - case 0x40: b4const_in_0 = 0xd; break; - case 0x80: b4const_in_0 = 0xe; break; - default: b4const_in_0 = 0xf; break; - } - *valp = b4const_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4constu_decode (uint32 *valp) -{ - unsigned b4constu_out_0; - unsigned b4constu_in_0; - b4constu_in_0 = *valp & 0xf; - b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; - *valp = b4constu_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4constu_encode (uint32 *valp) -{ - unsigned b4constu_in_0; - unsigned b4constu_out_0; - b4constu_out_0 = *valp; - switch (b4constu_out_0) - { - case 0x8000: b4constu_in_0 = 0; break; - case 0x10000: b4constu_in_0 = 0x1; break; - case 0x2: b4constu_in_0 = 0x2; break; - case 0x3: b4constu_in_0 = 0x3; break; - case 0x4: b4constu_in_0 = 0x4; break; - case 0x5: b4constu_in_0 = 0x5; break; - case 0x6: b4constu_in_0 = 0x6; break; - case 0x7: b4constu_in_0 = 0x7; break; - case 0x8: b4constu_in_0 = 0x8; break; - case 0xa: b4constu_in_0 = 0x9; break; - case 0xc: b4constu_in_0 = 0xa; break; - case 0x10: b4constu_in_0 = 0xb; break; - case 0x20: b4constu_in_0 = 0xc; break; - case 0x40: b4constu_in_0 = 0xd; break; - case 0x80: b4constu_in_0 = 0xe; break; - default: b4constu_in_0 = 0xf; break; - } - *valp = b4constu_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8_decode (uint32 *valp) -{ - unsigned uimm8_out_0; - unsigned uimm8_in_0; - uimm8_in_0 = *valp & 0xff; - uimm8_out_0 = uimm8_in_0; - *valp = uimm8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8_encode (uint32 *valp) -{ - unsigned uimm8_in_0; - unsigned uimm8_out_0; - uimm8_out_0 = *valp; - uimm8_in_0 = (uimm8_out_0 & 0xff); - *valp = uimm8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) -{ - unsigned uimm8x2_out_0; - unsigned uimm8x2_in_0; - uimm8x2_in_0 = *valp & 0xff; - uimm8x2_out_0 = uimm8x2_in_0 << 1; - *valp = uimm8x2_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) -{ - unsigned uimm8x2_in_0; - unsigned uimm8x2_out_0; - uimm8x2_out_0 = *valp; - uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); - *valp = uimm8x2_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) -{ - unsigned uimm8x4_out_0; - unsigned uimm8x4_in_0; - uimm8x4_in_0 = *valp & 0xff; - uimm8x4_out_0 = uimm8x4_in_0 << 2; - *valp = uimm8x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) -{ - unsigned uimm8x4_in_0; - unsigned uimm8x4_out_0; - uimm8x4_out_0 = *valp; - uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); - *valp = uimm8x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) -{ - unsigned uimm4x16_out_0; - unsigned uimm4x16_in_0; - uimm4x16_in_0 = *valp & 0xf; - uimm4x16_out_0 = uimm4x16_in_0 << 4; - *valp = uimm4x16_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) -{ - unsigned uimm4x16_in_0; - unsigned uimm4x16_out_0; - uimm4x16_out_0 = *valp; - uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); - *valp = uimm4x16_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8_decode (uint32 *valp) -{ - unsigned simm8_out_0; - unsigned simm8_in_0; - simm8_in_0 = *valp & 0xff; - simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; - *valp = simm8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8_encode (uint32 *valp) -{ - unsigned simm8_in_0; - unsigned simm8_out_0; - simm8_out_0 = *valp; - simm8_in_0 = (simm8_out_0 & 0xff); - *valp = simm8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) -{ - unsigned simm8x256_out_0; - unsigned simm8x256_in_0; - simm8x256_in_0 = *valp & 0xff; - simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; - *valp = simm8x256_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) -{ - unsigned simm8x256_in_0; - unsigned simm8x256_out_0; - simm8x256_out_0 = *valp; - simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); - *valp = simm8x256_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm12b_decode (uint32 *valp) -{ - unsigned simm12b_out_0; - unsigned simm12b_in_0; - simm12b_in_0 = *valp & 0xfff; - simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; - *valp = simm12b_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm12b_encode (uint32 *valp) -{ - unsigned simm12b_in_0; - unsigned simm12b_out_0; - simm12b_out_0 = *valp; - simm12b_in_0 = (simm12b_out_0 & 0xfff); - *valp = simm12b_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_msalp32_decode (uint32 *valp) -{ - unsigned msalp32_out_0; - unsigned msalp32_in_0; - msalp32_in_0 = *valp & 0x1f; - msalp32_out_0 = 0x20 - msalp32_in_0; - *valp = msalp32_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_msalp32_encode (uint32 *valp) -{ - unsigned msalp32_in_0; - unsigned msalp32_out_0; - msalp32_out_0 = *valp; - msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; - *valp = msalp32_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_op2p1_decode (uint32 *valp) -{ - unsigned op2p1_out_0; - unsigned op2p1_in_0; - op2p1_in_0 = *valp & 0xf; - op2p1_out_0 = op2p1_in_0 + 0x1; - *valp = op2p1_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_op2p1_encode (uint32 *valp) -{ - unsigned op2p1_in_0; - unsigned op2p1_out_0; - op2p1_out_0 = *valp; - op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; - *valp = op2p1_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_label8_decode (uint32 *valp) -{ - unsigned label8_out_0; - unsigned label8_in_0; - label8_in_0 = *valp & 0xff; - label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); - *valp = label8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_label8_encode (uint32 *valp) -{ - unsigned label8_in_0; - unsigned label8_out_0; - label8_out_0 = *valp; - label8_in_0 = (label8_out_0 - 0x4) & 0xff; - *valp = label8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) -{ - unsigned ulabel8_out_0; - unsigned ulabel8_in_0; - ulabel8_in_0 = *valp & 0xff; - ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); - *valp = ulabel8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) -{ - unsigned ulabel8_in_0; - unsigned ulabel8_out_0; - ulabel8_out_0 = *valp; - ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; - *valp = ulabel8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_label12_decode (uint32 *valp) -{ - unsigned label12_out_0; - unsigned label12_in_0; - label12_in_0 = *valp & 0xfff; - label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); - *valp = label12_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_label12_encode (uint32 *valp) -{ - unsigned label12_in_0; - unsigned label12_out_0; - label12_out_0 = *valp; - label12_in_0 = (label12_out_0 - 0x4) & 0xfff; - *valp = label12_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffset_decode (uint32 *valp) -{ - unsigned soffset_out_0; - unsigned soffset_in_0; - soffset_in_0 = *valp & 0x3ffff; - soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); - *valp = soffset_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffset_encode (uint32 *valp) -{ - unsigned soffset_in_0; - unsigned soffset_out_0; - soffset_out_0 = *valp; - soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; - *valp = soffset_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) -{ - unsigned uimm16x4_out_0; - unsigned uimm16x4_in_0; - uimm16x4_in_0 = *valp & 0xffff; - uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; - *valp = uimm16x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) -{ - unsigned uimm16x4_in_0; - unsigned uimm16x4_out_0; - uimm16x4_out_0 = *valp; - uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; - *valp = uimm16x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_bbi_decode (uint32 *valp) -{ - unsigned bbi_out_0; - unsigned bbi_in_0; - bbi_in_0 = *valp & 0x1f; - bbi_out_0 = (0 << 5) | bbi_in_0; - *valp = bbi_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_bbi_encode (uint32 *valp) -{ - unsigned bbi_in_0; - unsigned bbi_out_0; - bbi_out_0 = *valp; - bbi_in_0 = (bbi_out_0 & 0x1f); - *valp = bbi_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_s_decode (uint32 *valp) -{ - unsigned s_out_0; - unsigned s_in_0; - s_in_0 = *valp & 0xf; - s_out_0 = (0 << 4) | s_in_0; - *valp = s_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_s_encode (uint32 *valp) -{ - unsigned s_in_0; - unsigned s_out_0; - s_out_0 = *valp; - s_in_0 = (s_out_0 & 0xf); - *valp = s_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_immt_decode (uint32 *valp) -{ - unsigned immt_out_0; - unsigned immt_in_0; - immt_in_0 = *valp & 0xf; - immt_out_0 = immt_in_0; - *valp = immt_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_immt_encode (uint32 *valp) -{ - unsigned immt_in_0; - unsigned immt_out_0; - immt_out_0 = *valp; - immt_in_0 = immt_out_0 & 0xf; - *valp = immt_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_BR_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16); - return error; -} - -static int -OperandSem_opnd_sem_BR2_decode (uint32 *valp) -{ - *valp = *valp << 1; - return 0; -} - -static int -OperandSem_opnd_sem_BR2_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16) || ((*valp & 1) != 0); - *valp = *valp >> 1; - return error; -} - -static int -OperandSem_opnd_sem_BR4_decode (uint32 *valp) -{ - *valp = *valp << 2; - return 0; -} - -static int -OperandSem_opnd_sem_BR4_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16) || ((*valp & 3) != 0); - *valp = *valp >> 2; - return error; -} - -static int -OperandSem_opnd_sem_BR8_decode (uint32 *valp) -{ - *valp = *valp << 3; - return 0; -} - -static int -OperandSem_opnd_sem_BR8_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16) || ((*valp & 7) != 0); - *valp = *valp >> 3; - return error; -} - -static int -OperandSem_opnd_sem_BR16_decode (uint32 *valp) -{ - *valp = *valp << 4; - return 0; -} - -static int -OperandSem_opnd_sem_BR16_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16) || ((*valp & 15) != 0); - *valp = *valp >> 4; - return error; -} - -static int -OperandSem_opnd_sem_tp7_decode (uint32 *valp) -{ - unsigned tp7_out_0; - unsigned tp7_in_0; - tp7_in_0 = *valp & 0xf; - tp7_out_0 = tp7_in_0 + 0x7; - *valp = tp7_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_tp7_encode (uint32 *valp) -{ - unsigned tp7_in_0; - unsigned tp7_out_0; - tp7_out_0 = *valp; - tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; - *valp = tp7_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) -{ - unsigned xt_wbr15_label_out_0; - unsigned xt_wbr15_label_in_0; - xt_wbr15_label_in_0 = *valp & 0x7fff; - xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); - *valp = xt_wbr15_label_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) -{ - unsigned xt_wbr15_label_in_0; - unsigned xt_wbr15_label_out_0; - xt_wbr15_label_out_0 = *valp; - xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; - *valp = xt_wbr15_label_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_samt32_decode (uint32 *valp) -{ - unsigned ae_samt32_out_0; - unsigned ae_samt32_in_0; - ae_samt32_in_0 = *valp & 0x1f; - ae_samt32_out_0 = (0 << 5) | ae_samt32_in_0; - *valp = ae_samt32_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_samt32_encode (uint32 *valp) -{ - unsigned ae_samt32_in_0; - unsigned ae_samt32_out_0; - ae_samt32_out_0 = *valp; - ae_samt32_in_0 = (ae_samt32_out_0 & 0x1f); - *valp = ae_samt32_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_AE_PR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AE_PR_encode (uint32 *valp) -{ - int error; - error = (*valp >= 8); - return error; -} - -static int -OperandSem_opnd_sem_AE_QR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AE_QR_encode (uint32 *valp) -{ - int error; - error = (*valp >= 4); - return error; -} - -static int -OperandSem_opnd_sem_ae_lsimm16_decode (uint32 *valp) -{ - unsigned ae_lsimm16_out_0; - unsigned ae_lsimm16_in_0; - ae_lsimm16_in_0 = *valp & 0xf; - ae_lsimm16_out_0 = (((int) ae_lsimm16_in_0 << 28) >> 28) << 1; - *valp = ae_lsimm16_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm16_encode (uint32 *valp) -{ - unsigned ae_lsimm16_in_0; - unsigned ae_lsimm16_out_0; - ae_lsimm16_out_0 = *valp; - ae_lsimm16_in_0 = ((ae_lsimm16_out_0 >> 1) & 0xf); - *valp = ae_lsimm16_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm32_decode (uint32 *valp) -{ - unsigned ae_lsimm32_out_0; - unsigned ae_lsimm32_in_0; - ae_lsimm32_in_0 = *valp & 0xf; - ae_lsimm32_out_0 = (((int) ae_lsimm32_in_0 << 28) >> 28) << 2; - *valp = ae_lsimm32_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm32_encode (uint32 *valp) -{ - unsigned ae_lsimm32_in_0; - unsigned ae_lsimm32_out_0; - ae_lsimm32_out_0 = *valp; - ae_lsimm32_in_0 = ((ae_lsimm32_out_0 >> 2) & 0xf); - *valp = ae_lsimm32_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm64_decode (uint32 *valp) -{ - unsigned ae_lsimm64_out_0; - unsigned ae_lsimm64_in_0; - ae_lsimm64_in_0 = *valp & 0xf; - ae_lsimm64_out_0 = (((int) ae_lsimm64_in_0 << 28) >> 28) << 3; - *valp = ae_lsimm64_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm64_encode (uint32 *valp) -{ - unsigned ae_lsimm64_in_0; - unsigned ae_lsimm64_out_0; - ae_lsimm64_out_0 = *valp; - ae_lsimm64_in_0 = ((ae_lsimm64_out_0 >> 3) & 0xf); - *valp = ae_lsimm64_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_samt64_decode (uint32 *valp) -{ - unsigned ae_samt64_out_0; - unsigned ae_samt64_in_0; - ae_samt64_in_0 = *valp & 0x3f; - ae_samt64_out_0 = (0 << 6) | ae_samt64_in_0; - *valp = ae_samt64_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_samt64_encode (uint32 *valp) -{ - unsigned ae_samt64_in_0; - unsigned ae_samt64_out_0; - ae_samt64_out_0 = *valp; - ae_samt64_in_0 = (ae_samt64_out_0 & 0x3f); - *valp = ae_samt64_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp) -{ - unsigned ae_ohba_out_0; - unsigned ae_ohba_in_0; - ae_ohba_in_0 = *valp & 0xf; - ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf)); - *valp = ae_ohba_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp) -{ - unsigned ae_ohba_in_0; - unsigned ae_ohba_out_0; - ae_ohba_out_0 = *valp; - ae_ohba_in_0 = (ae_ohba_out_0 & 0xf); - *valp = ae_ohba_in_0; - return 0; -} - -static int -Operand_soffsetx4_ator (uint32 *valp, uint32 pc) -{ - *valp -= (pc & ~0x3); - return 0; -} - -static int -Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += (pc & ~0x3); - return 0; -} - -static int -Operand_uimm6_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_uimm6_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_label8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ulabel8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_label12_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label12_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_soffset_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_soffset_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_uimm16x4_ator (uint32 *valp, uint32 pc) -{ - *valp -= ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static xtensa_operand_internal operands[] = { - { "soffsetx4", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, - Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, - { "uimm12x8", FIELD_imm12, -1, 0, - 0, - OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, - 0, 0 }, - { "simm4", FIELD_mn, -1, 0, - 0, - OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, - 0, 0 }, - { "arr", FIELD_r, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "ars", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "*ars_invisible", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "art", FIELD_t, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "ar0", FIELD__ar0, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, - 0, 0 }, - { "ar4", FIELD__ar4, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode, - 0, 0 }, - { "ar8", FIELD__ar8, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode, - 0, 0 }, - { "ar12", FIELD__ar12, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode, - 0, 0 }, - { "ars_entry", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, - 0, 0 }, - { "immrx4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, - 0, 0 }, - { "lsi4x4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, - 0, 0 }, - { "simm7", FIELD_imm7, -1, 0, - 0, - OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, - 0, 0 }, - { "uimm6", FIELD_imm6, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, - Operand_uimm6_ator, Operand_uimm6_rtoa }, - { "ai4const", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, - 0, 0 }, - { "b4const", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, - 0, 0 }, - { "b4constu", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, - 0, 0 }, - { "uimm8", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, - 0, 0 }, - { "uimm8x2", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, - 0, 0 }, - { "uimm8x4", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, - 0, 0 }, - { "uimm4x16", FIELD_op2, -1, 0, - 0, - OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, - 0, 0 }, - { "uimmrx4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, - 0, 0 }, - { "simm8", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, - 0, 0 }, - { "simm8x256", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, - 0, 0 }, - { "simm12b", FIELD_imm12b, -1, 0, - 0, - OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, - 0, 0 }, - { "msalp32", FIELD_sal, -1, 0, - 0, - OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, - 0, 0 }, - { "op2p1", FIELD_op2, -1, 0, - 0, - OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, - 0, 0 }, - { "label8", FIELD_imm8, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, - Operand_label8_ator, Operand_label8_rtoa }, - { "ulabel8", FIELD_imm8, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, - Operand_ulabel8_ator, Operand_ulabel8_rtoa }, - { "label12", FIELD_imm12, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, - Operand_label12_ator, Operand_label12_rtoa }, - { "soffset", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, - Operand_soffset_ator, Operand_soffset_rtoa }, - { "uimm16x4", FIELD_imm16, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, - Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, - { "bbi", FIELD_bbi, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sae", FIELD_sae, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sas", FIELD_sas, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sargt", FIELD_sargt, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "s", FIELD_s, -1, 0, - 0, - OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, - 0, 0 }, - { "immt", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, - 0, 0 }, - { "imms", FIELD_s, -1, 0, - 0, - OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, - 0, 0 }, - { "bt", FIELD_t, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, - 0, 0 }, - { "bs", FIELD_s, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, - 0, 0 }, - { "br", FIELD_r, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, - 0, 0 }, - { "bt2", FIELD_t2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, - 0, 0 }, - { "bs2", FIELD_s2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, - 0, 0 }, - { "br2", FIELD_r2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, - 0, 0 }, - { "bt4", FIELD_t4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, - 0, 0 }, - { "bs4", FIELD_s4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, - 0, 0 }, - { "br4", FIELD_r4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, - 0, 0 }, - { "bt8", FIELD_t8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, - 0, 0 }, - { "bs8", FIELD_s8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, - 0, 0 }, - { "br8", FIELD_r8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, - 0, 0 }, - { "bt16", FIELD__bt16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, - 0, 0 }, - { "bs16", FIELD__bs16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, - 0, 0 }, - { "br16", FIELD__br16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, - 0, 0 }, - { "brall", FIELD__brall, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, - 0, 0 }, - { "tp7", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, - 0, 0 }, - { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, - Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, - { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, - Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, - { "ae_samt32", FIELD_ftsf14, -1, 0, - 0, - OperandSem_opnd_sem_ae_samt32_encode, OperandSem_opnd_sem_ae_samt32_decode, - 0, 0 }, - { "pr0", FIELD_ftsf12, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "qr0", FIELD_ftsf13, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "mac_qr0", FIELD_ftsf13, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "ae_lsimm16", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ae_lsimm16_encode, OperandSem_opnd_sem_ae_lsimm16_decode, - 0, 0 }, - { "ae_lsimm32", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ae_lsimm32_encode, OperandSem_opnd_sem_ae_lsimm32_decode, - 0, 0 }, - { "ae_lsimm64", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ae_lsimm64_encode, OperandSem_opnd_sem_ae_lsimm64_decode, - 0, 0 }, - { "ae_samt64", FIELD_ae_samt_s_t, -1, 0, - 0, - OperandSem_opnd_sem_ae_samt64_encode, OperandSem_opnd_sem_ae_samt64_decode, - 0, 0 }, - { "ae_ohba", FIELD_ae_fld_ohba, -1, 0, - 0, - OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, - 0, 0 }, - { "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0, - 0, - OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, - 0, 0 }, - { "pr", FIELD_ae_r20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "ps", FIELD_ae_s20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "bitindex", FIELD_bitindex, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, - { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, - { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, - { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, - { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, - { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, - { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, - { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, - { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, - { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, - { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, - { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, - { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, - { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, - { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, - { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, - { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, - { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, - { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, - { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, - { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, - { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, - { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, - { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, - { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, - { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, - { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, - { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, - { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, - { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, - { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r3", FIELD_ae_r3, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s_non_samt", FIELD_ae_s_non_samt, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s3", FIELD_ae_s3, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r32", FIELD_ae_r32, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_samt_s_t", FIELD_ae_samt_s_t, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf14", FIELD_ftsf14, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf21ae_slot1", FIELD_ftsf21ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf22ae_slot1", FIELD_ftsf22ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf23ae_slot1", FIELD_ftsf23ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf24ae_slot1", FIELD_ftsf24ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf25ae_slot1", FIELD_ftsf25ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf26ae_slot1", FIELD_ftsf26ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf27ae_slot1", FIELD_ftsf27ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf28ae_slot1", FIELD_ftsf28ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf29ae_slot1", FIELD_ftsf29ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf30ae_slot1", FIELD_ftsf30ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf31ae_slot1", FIELD_ftsf31ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf32ae_slot1", FIELD_ftsf32ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf33ae_slot1", FIELD_ftsf33ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf34ae_slot1", FIELD_ftsf34ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf35ae_slot1", FIELD_ftsf35ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf36ae_slot1", FIELD_ftsf36ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf37ae_slot1", FIELD_ftsf37ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf38ae_slot1", FIELD_ftsf38ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf39ae_slot1", FIELD_ftsf39ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf40ae_slot1", FIELD_ftsf40ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf41ae_slot1", FIELD_ftsf41ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf42ae_slot1", FIELD_ftsf42ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf43ae_slot1", FIELD_ftsf43ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf44ae_slot1", FIELD_ftsf44ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf45ae_slot1", FIELD_ftsf45ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf46ae_slot1", FIELD_ftsf46ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf47ae_slot1", FIELD_ftsf47ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf48ae_slot1", FIELD_ftsf48ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf49ae_slot1", FIELD_ftsf49ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf50ae_slot1", FIELD_ftsf50ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf51ae_slot1", FIELD_ftsf51ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf52ae_slot1", FIELD_ftsf52ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf53ae_slot1", FIELD_ftsf53ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf54ae_slot1", FIELD_ftsf54ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf55ae_slot1", FIELD_ftsf55ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf56ae_slot1", FIELD_ftsf56ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf57ae_slot1", FIELD_ftsf57ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf58ae_slot1", FIELD_ftsf58ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf59ae_slot1", FIELD_ftsf59ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf60ae_slot1", FIELD_ftsf60ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf61ae_slot1", FIELD_ftsf61ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf63ae_slot1", FIELD_ftsf63ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf64ae_slot1", FIELD_ftsf64ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf66ae_slot1", FIELD_ftsf66ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf67ae_slot1", FIELD_ftsf67ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf69ae_slot1", FIELD_ftsf69ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf71ae_slot1", FIELD_ftsf71ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf72ae_slot1", FIELD_ftsf72ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf73ae_slot1", FIELD_ftsf73ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf75ae_slot1", FIELD_ftsf75ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf76ae_slot1", FIELD_ftsf76ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf77ae_slot1", FIELD_ftsf77ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf78ae_slot1", FIELD_ftsf78ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf79ae_slot1", FIELD_ftsf79ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf80ae_slot1", FIELD_ftsf80ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf81ae_slot1", FIELD_ftsf81ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf82ae_slot1", FIELD_ftsf82ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf84ae_slot1", FIELD_ftsf84ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf86ae_slot1", FIELD_ftsf86ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf87ae_slot1", FIELD_ftsf87ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf88ae_slot1", FIELD_ftsf88ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf89ae_slot1", FIELD_ftsf89ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf90ae_slot1", FIELD_ftsf90ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf91ae_slot1", FIELD_ftsf91ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf92ae_slot1", FIELD_ftsf92ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf94ae_slot1", FIELD_ftsf94ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf96ae_slot1", FIELD_ftsf96ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf97ae_slot1", FIELD_ftsf97ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf98ae_slot1", FIELD_ftsf98ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf99ae_slot1", FIELD_ftsf99ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf100ae_slot1", FIELD_ftsf100ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf101ae_slot1", FIELD_ftsf101ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf103ae_slot1", FIELD_ftsf103ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf104ae_slot1", FIELD_ftsf104ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf105ae_slot1", FIELD_ftsf105ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf106ae_slot1", FIELD_ftsf106ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf107ae_slot1", FIELD_ftsf107ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf108ae_slot1", FIELD_ftsf108ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf109ae_slot1", FIELD_ftsf109ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf110ae_slot1", FIELD_ftsf110ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf111ae_slot1", FIELD_ftsf111ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf112ae_slot1", FIELD_ftsf112ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf113ae_slot1", FIELD_ftsf113ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf114ae_slot1", FIELD_ftsf114ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf115ae_slot1", FIELD_ftsf115ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf116ae_slot1", FIELD_ftsf116ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf118ae_slot1", FIELD_ftsf118ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf119ae_slot1", FIELD_ftsf119ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf120ae_slot1", FIELD_ftsf120ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf122ae_slot1", FIELD_ftsf122ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf124ae_slot1", FIELD_ftsf124ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf125ae_slot1", FIELD_ftsf125ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf126ae_slot1", FIELD_ftsf126ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf127ae_slot1", FIELD_ftsf127ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf128ae_slot1", FIELD_ftsf128ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf129ae_slot1", FIELD_ftsf129ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf130ae_slot1", FIELD_ftsf130ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf131ae_slot1", FIELD_ftsf131ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf132ae_slot1", FIELD_ftsf132ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf133ae_slot1", FIELD_ftsf133ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf134ae_slot1", FIELD_ftsf134ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf135ae_slot1", FIELD_ftsf135ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf136ae_slot1", FIELD_ftsf136ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf137ae_slot1", FIELD_ftsf137ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf138ae_slot1", FIELD_ftsf138ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf139ae_slot1", FIELD_ftsf139ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf140ae_slot1", FIELD_ftsf140ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf141ae_slot1", FIELD_ftsf141ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf142ae_slot1", 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FIELD_ftsf281ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf282ae_slot0", FIELD_ftsf282ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf283ae_slot0", FIELD_ftsf283ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf284ae_slot0", FIELD_ftsf284ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf286ae_slot0", FIELD_ftsf286ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf288ae_slot0", FIELD_ftsf288ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf290ae_slot0", FIELD_ftsf290ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf292ae_slot0", FIELD_ftsf292ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf293", FIELD_ftsf293, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf294ae_slot0", FIELD_ftsf294ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf295ae_slot0", FIELD_ftsf295ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf296ae_slot0", FIELD_ftsf296ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf297ae_slot0", FIELD_ftsf297ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf298ae_slot0", FIELD_ftsf298ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf299ae_slot0", FIELD_ftsf299ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf300ae_slot0", FIELD_ftsf300ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf301ae_slot0", FIELD_ftsf301ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf302ae_slot0", FIELD_ftsf302ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf303ae_slot0", FIELD_ftsf303ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf304ae_slot0", FIELD_ftsf304ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf306ae_slot0", FIELD_ftsf306ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf308ae_slot0", FIELD_ftsf308ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf309ae_slot0", FIELD_ftsf309ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf310ae_slot0", FIELD_ftsf310ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf311ae_slot0", FIELD_ftsf311ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf312ae_slot0", FIELD_ftsf312ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf313ae_slot0", FIELD_ftsf313ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf314ae_slot0", FIELD_ftsf314ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf315ae_slot0", FIELD_ftsf315ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf316ae_slot0", FIELD_ftsf316ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf317ae_slot0", FIELD_ftsf317ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf318ae_slot0", FIELD_ftsf318ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf319", FIELD_ftsf319, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf320ae_slot0", FIELD_ftsf320ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf321", FIELD_ftsf321, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf322ae_slot0", FIELD_ftsf322ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf323ae_slot0", FIELD_ftsf323ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf324ae_slot0", FIELD_ftsf324ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf325ae_slot0", FIELD_ftsf325ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf326ae_slot0", FIELD_ftsf326ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf328ae_slot0", FIELD_ftsf328ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf329ae_slot0", FIELD_ftsf329ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf352ae_slot0", FIELD_ftsf352ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf353", FIELD_ftsf353, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf354ae_slot0", FIELD_ftsf354ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf356ae_slot0", FIELD_ftsf356ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf357", FIELD_ftsf357, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf358ae_slot0", FIELD_ftsf358ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf359ae_slot0", FIELD_ftsf359ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf360ae_slot0", FIELD_ftsf360ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf361ae_slot0", FIELD_ftsf361ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf362ae_slot0", FIELD_ftsf362ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf364ae_slot0", FIELD_ftsf364ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf365ae_slot0", FIELD_ftsf365ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf366ae_slot0", FIELD_ftsf366ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf368ae_slot0", FIELD_ftsf368ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf369ae_slot0", FIELD_ftsf369ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_mul32x24fld", FIELD_ae_mul32x24fld, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld115", FIELD_combined1b97e84f_fld115, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld97", FIELD_combined1b97e84f_fld97, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld124", FIELD_combined1b97e84f_fld124, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld79", FIELD_combined1b97e84f_fld79, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld80", FIELD_combined1b97e84f_fld80, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld108", FIELD_combined1b97e84f_fld108, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld101", FIELD_combined1b97e84f_fld101, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld88", FIELD_combined1b97e84f_fld88, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld39", FIELD_combined1b97e84f_fld39, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s4_s4", FIELD_op0_s4_s4, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld83", FIELD_combined1b97e84f_fld83, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld90", FIELD_combined1b97e84f_fld90, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld93", FIELD_combined1b97e84f_fld93, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld138ae_slot0", FIELD_combined1b97e84f_fld138ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld130ae_slot0", FIELD_combined1b97e84f_fld130ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld137ae_slot0", FIELD_combined1b97e84f_fld137ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld135ae_slot0", FIELD_combined1b97e84f_fld135ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld136ae_slot0", FIELD_combined1b97e84f_fld136ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld129ae_slot0", FIELD_combined1b97e84f_fld129ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld127ae_slot0", FIELD_combined1b97e84f_fld127ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld128ae_slot0", FIELD_combined1b97e84f_fld128ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld132ae_slot0", FIELD_combined1b97e84f_fld132ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld134ae_slot0", FIELD_combined1b97e84f_fld134ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld122", FIELD_combined4b12daa6_fld122, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld115", FIELD_combined4b12daa6_fld115, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld85", FIELD_combined4b12daa6_fld85, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld119", FIELD_combined4b12daa6_fld119, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld97", FIELD_combined4b12daa6_fld97, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld124", FIELD_combined4b12daa6_fld124, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld79", FIELD_combined4b12daa6_fld79, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld80", FIELD_combined4b12daa6_fld80, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld108", FIELD_combined4b12daa6_fld108, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld54", FIELD_combined1b97e84f_fld54, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld17", FIELD_combined1b97e84f_fld17, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld76", FIELD_combined1b97e84f_fld76, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld73", FIELD_combined1b97e84f_fld73, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld62", FIELD_combined1b97e84f_fld62, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld24", FIELD_combined1b97e84f_fld24, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld70", FIELD_combined1b97e84f_fld70, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld58", FIELD_combined1b97e84f_fld58, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld131ae_slot1", FIELD_combined1b97e84f_fld131ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s3_s3", FIELD_op0_s3_s3, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld49", FIELD_combined1b97e84f_fld49, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld51", FIELD_combined1b97e84f_fld51, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld23", FIELD_combined1b97e84f_fld23, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_fld0", FIELD_xt_fld0, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_fld1", FIELD_xt_fld1, -1, 0, 0, 0, 0, 0, 0 }, - { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } -}; - -enum xtensa_operand_id { - OPERAND_soffsetx4, - OPERAND_uimm12x8, - OPERAND_simm4, - OPERAND_arr, - OPERAND_ars, - OPERAND__ars_invisible, - OPERAND_art, - OPERAND_ar0, - OPERAND_ar4, - OPERAND_ar8, - OPERAND_ar12, - OPERAND_ars_entry, - OPERAND_immrx4, - OPERAND_lsi4x4, - OPERAND_simm7, - OPERAND_uimm6, - OPERAND_ai4const, - OPERAND_b4const, - OPERAND_b4constu, - OPERAND_uimm8, - OPERAND_uimm8x2, - OPERAND_uimm8x4, - OPERAND_uimm4x16, - OPERAND_uimmrx4, - OPERAND_simm8, - OPERAND_simm8x256, - OPERAND_simm12b, - OPERAND_msalp32, - OPERAND_op2p1, - OPERAND_label8, - OPERAND_ulabel8, - OPERAND_label12, - OPERAND_soffset, - OPERAND_uimm16x4, - OPERAND_bbi, - OPERAND_sae, - OPERAND_sas, - OPERAND_sargt, - OPERAND_s, - OPERAND_immt, - OPERAND_imms, - OPERAND_bt, - OPERAND_bs, - OPERAND_br, - OPERAND_bt2, - OPERAND_bs2, - OPERAND_br2, - OPERAND_bt4, - OPERAND_bs4, - OPERAND_br4, - OPERAND_bt8, - OPERAND_bs8, - OPERAND_br8, - OPERAND_bt16, - OPERAND_bs16, - OPERAND_br16, - OPERAND_brall, - OPERAND_tp7, - OPERAND_xt_wbr15_label, - OPERAND_xt_wbr18_label, - OPERAND_ae_samt32, - OPERAND_pr0, - OPERAND_qr0, - OPERAND_mac_qr0, - OPERAND_ae_lsimm16, - OPERAND_ae_lsimm32, - OPERAND_ae_lsimm64, - OPERAND_ae_samt64, - OPERAND_ae_ohba, - OPERAND_ae_ohba2, - OPERAND_pr, - OPERAND_cvt_pr, - OPERAND_qr0_rw, - OPERAND_mac_qr0_rw, - OPERAND_qr1_w, - OPERAND_mac_qr1_w, - OPERAND_ps, - OPERAND_alupppb_ps, - OPERAND_bitindex, - OPERAND_t, - OPERAND_bbi4, - OPERAND_imm12, - OPERAND_imm8, - OPERAND_imm12b, - OPERAND_imm16, - OPERAND_m, - OPERAND_n, - OPERAND_offset, - OPERAND_op0, - OPERAND_op1, - OPERAND_op2, - OPERAND_r, - OPERAND_sa4, - OPERAND_sae4, - OPERAND_sal, - OPERAND_sas4, - OPERAND_sr, - OPERAND_st, - OPERAND_thi3, - OPERAND_imm4, - OPERAND_mn, - OPERAND_i, - OPERAND_imm6lo, - OPERAND_imm6hi, - OPERAND_imm7lo, - OPERAND_imm7hi, - OPERAND_z, - OPERAND_imm6, - OPERAND_imm7, - OPERAND_t2, - OPERAND_s2, - OPERAND_r2, - OPERAND_t4, - OPERAND_s4, - OPERAND_r4, - OPERAND_t8, - OPERAND_s8, - OPERAND_r8, - OPERAND_xt_wbr15_imm, - OPERAND_xt_wbr18_imm, - OPERAND_ae_r3, - OPERAND_ae_s_non_samt, - OPERAND_ae_s3, - OPERAND_ae_r32, - OPERAND_ae_samt_s_t, - OPERAND_ae_r20, - OPERAND_ae_r10, - OPERAND_ae_s20, - OPERAND_ae_fld_ohba, - OPERAND_ae_fld_ohba2, - OPERAND_op0_s3, - OPERAND_ftsf12, - OPERAND_ftsf13, - OPERAND_ftsf14, - OPERAND_ftsf21ae_slot1, - OPERAND_ftsf22ae_slot1, - OPERAND_ftsf23ae_slot1, - OPERAND_ftsf24ae_slot1, - OPERAND_ftsf25ae_slot1, - OPERAND_ftsf26ae_slot1, - OPERAND_ftsf27ae_slot1, - OPERAND_ftsf28ae_slot1, - OPERAND_ftsf29ae_slot1, - OPERAND_ftsf30ae_slot1, - OPERAND_ftsf31ae_slot1, - OPERAND_ftsf32ae_slot1, - OPERAND_ftsf33ae_slot1, - OPERAND_ftsf34ae_slot1, - OPERAND_ftsf35ae_slot1, - OPERAND_ftsf36ae_slot1, - OPERAND_ftsf37ae_slot1, - OPERAND_ftsf38ae_slot1, - OPERAND_ftsf39ae_slot1, - OPERAND_ftsf40ae_slot1, - OPERAND_ftsf41ae_slot1, - OPERAND_ftsf42ae_slot1, - OPERAND_ftsf43ae_slot1, - OPERAND_ftsf44ae_slot1, - OPERAND_ftsf45ae_slot1, - OPERAND_ftsf46ae_slot1, - OPERAND_ftsf47ae_slot1, - OPERAND_ftsf48ae_slot1, - OPERAND_ftsf49ae_slot1, - OPERAND_ftsf50ae_slot1, - OPERAND_ftsf51ae_slot1, - OPERAND_ftsf52ae_slot1, - OPERAND_ftsf53ae_slot1, - OPERAND_ftsf54ae_slot1, - OPERAND_ftsf55ae_slot1, - OPERAND_ftsf56ae_slot1, - OPERAND_ftsf57ae_slot1, - OPERAND_ftsf58ae_slot1, - OPERAND_ftsf59ae_slot1, - OPERAND_ftsf60ae_slot1, - OPERAND_ftsf61ae_slot1, - OPERAND_ftsf63ae_slot1, - OPERAND_ftsf64ae_slot1, - OPERAND_ftsf66ae_slot1, - OPERAND_ftsf67ae_slot1, - OPERAND_ftsf69ae_slot1, - OPERAND_ftsf71ae_slot1, - OPERAND_ftsf72ae_slot1, - OPERAND_ftsf73ae_slot1, - OPERAND_ftsf75ae_slot1, - OPERAND_ftsf76ae_slot1, - OPERAND_ftsf77ae_slot1, - OPERAND_ftsf78ae_slot1, - OPERAND_ftsf79ae_slot1, - OPERAND_ftsf80ae_slot1, - OPERAND_ftsf81ae_slot1, - OPERAND_ftsf82ae_slot1, - OPERAND_ftsf84ae_slot1, - OPERAND_ftsf86ae_slot1, - OPERAND_ftsf87ae_slot1, - OPERAND_ftsf88ae_slot1, - OPERAND_ftsf89ae_slot1, - OPERAND_ftsf90ae_slot1, - OPERAND_ftsf91ae_slot1, - OPERAND_ftsf92ae_slot1, - OPERAND_ftsf94ae_slot1, - OPERAND_ftsf96ae_slot1, - OPERAND_ftsf97ae_slot1, - OPERAND_ftsf98ae_slot1, - OPERAND_ftsf99ae_slot1, - OPERAND_ftsf100ae_slot1, - OPERAND_ftsf101ae_slot1, - OPERAND_ftsf103ae_slot1, - OPERAND_ftsf104ae_slot1, - OPERAND_ftsf105ae_slot1, - OPERAND_ftsf106ae_slot1, - OPERAND_ftsf107ae_slot1, - OPERAND_ftsf108ae_slot1, - OPERAND_ftsf109ae_slot1, - OPERAND_ftsf110ae_slot1, - OPERAND_ftsf111ae_slot1, - OPERAND_ftsf112ae_slot1, - OPERAND_ftsf113ae_slot1, - OPERAND_ftsf114ae_slot1, - OPERAND_ftsf115ae_slot1, - OPERAND_ftsf116ae_slot1, - OPERAND_ftsf118ae_slot1, - OPERAND_ftsf119ae_slot1, - OPERAND_ftsf120ae_slot1, - OPERAND_ftsf122ae_slot1, - OPERAND_ftsf124ae_slot1, - OPERAND_ftsf125ae_slot1, - OPERAND_ftsf126ae_slot1, - OPERAND_ftsf127ae_slot1, - OPERAND_ftsf128ae_slot1, - OPERAND_ftsf129ae_slot1, - OPERAND_ftsf130ae_slot1, - OPERAND_ftsf131ae_slot1, - OPERAND_ftsf132ae_slot1, - OPERAND_ftsf133ae_slot1, - OPERAND_ftsf134ae_slot1, - OPERAND_ftsf135ae_slot1, - OPERAND_ftsf136ae_slot1, - OPERAND_ftsf137ae_slot1, - OPERAND_ftsf138ae_slot1, - OPERAND_ftsf139ae_slot1, - OPERAND_ftsf140ae_slot1, - OPERAND_ftsf141ae_slot1, - OPERAND_ftsf142ae_slot1, - OPERAND_ftsf143ae_slot1, - OPERAND_ftsf144ae_slot1, - OPERAND_ftsf145ae_slot1, - OPERAND_ftsf146ae_slot1, - OPERAND_ftsf147ae_slot1, - OPERAND_ftsf148ae_slot1, - OPERAND_ftsf149ae_slot1, - OPERAND_ftsf150ae_slot1, - OPERAND_ftsf151ae_slot1, - OPERAND_ftsf152ae_slot1, - OPERAND_ftsf153ae_slot1, - OPERAND_ftsf154ae_slot1, - OPERAND_ftsf155ae_slot1, - OPERAND_ftsf156ae_slot1, - OPERAND_ftsf157ae_slot1, - OPERAND_ftsf158ae_slot1, - OPERAND_ftsf159ae_slot1, - OPERAND_ftsf160ae_slot1, - OPERAND_ftsf161ae_slot1, - OPERAND_ftsf162ae_slot1, - OPERAND_ftsf163ae_slot1, - OPERAND_ftsf164ae_slot1, - OPERAND_ftsf165ae_slot1, - OPERAND_ftsf166ae_slot1, - OPERAND_ftsf167ae_slot1, - OPERAND_ftsf168ae_slot1, - OPERAND_ftsf169ae_slot1, - OPERAND_ftsf170ae_slot1, - OPERAND_ftsf171ae_slot1, - OPERAND_ftsf172ae_slot1, - OPERAND_ftsf173ae_slot1, - OPERAND_ftsf174ae_slot1, - OPERAND_ftsf175ae_slot1, - OPERAND_ftsf176ae_slot1, - OPERAND_ftsf177ae_slot1, - OPERAND_ftsf178ae_slot1, - OPERAND_ftsf179ae_slot1, - OPERAND_ftsf180ae_slot1, - OPERAND_ftsf181ae_slot1, - OPERAND_ftsf182ae_slot1, - OPERAND_ftsf183ae_slot1, - OPERAND_ftsf184ae_slot1, - OPERAND_ftsf185ae_slot1, - OPERAND_ftsf186ae_slot1, - OPERAND_ftsf187ae_slot1, - OPERAND_ftsf188ae_slot1, - OPERAND_ftsf189ae_slot1, - OPERAND_ftsf190ae_slot1, - OPERAND_ftsf191ae_slot1, - OPERAND_ftsf192ae_slot1, - OPERAND_ftsf193ae_slot1, - OPERAND_ftsf194ae_slot1, - OPERAND_ftsf195ae_slot1, - OPERAND_ftsf196ae_slot1, - OPERAND_ftsf197ae_slot1, - OPERAND_ftsf198ae_slot1, - OPERAND_ftsf199ae_slot1, - OPERAND_ftsf200ae_slot1, - OPERAND_ftsf201ae_slot1, - OPERAND_ftsf202ae_slot1, - OPERAND_ftsf203ae_slot1, - OPERAND_ftsf204ae_slot1, - OPERAND_ftsf205ae_slot1, - OPERAND_ftsf206ae_slot1, - OPERAND_ftsf207ae_slot1, - OPERAND_ftsf208, - OPERAND_ftsf209ae_slot1, - OPERAND_ftsf210ae_slot1, - OPERAND_ftsf211ae_slot1, - OPERAND_ftsf330ae_slot1, - OPERAND_ftsf332ae_slot1, - OPERAND_ftsf334ae_slot1, - OPERAND_ftsf336ae_slot1, - OPERAND_ftsf337ae_slot1, - OPERAND_ftsf338, - OPERAND_ftsf339ae_slot1, - OPERAND_ftsf340, - OPERAND_ftsf341ae_slot1, - OPERAND_ftsf342ae_slot1, - OPERAND_ftsf343ae_slot1, - OPERAND_ftsf344ae_slot1, - OPERAND_ftsf346ae_slot1, - OPERAND_ftsf347, - OPERAND_ftsf348ae_slot1, - OPERAND_ftsf349ae_slot1, - OPERAND_ftsf350ae_slot1, - OPERAND_op0_s4, - OPERAND_ftsf212ae_slot0, - OPERAND_ftsf213ae_slot0, - OPERAND_ftsf214ae_slot0, - OPERAND_ftsf215ae_slot0, - OPERAND_ftsf216ae_slot0, - OPERAND_ftsf217, - OPERAND_ftsf218ae_slot0, - OPERAND_ftsf219ae_slot0, - OPERAND_ftsf220ae_slot0, - OPERAND_ftsf221ae_slot0, - OPERAND_ftsf222ae_slot0, - OPERAND_ftsf223ae_slot0, - OPERAND_ftsf224ae_slot0, - OPERAND_ftsf225ae_slot0, - OPERAND_ftsf226ae_slot0, - OPERAND_ftsf227ae_slot0, - OPERAND_ftsf228ae_slot0, - OPERAND_ftsf229ae_slot0, - OPERAND_ftsf230ae_slot0, - OPERAND_ftsf231ae_slot0, - OPERAND_ftsf232ae_slot0, - OPERAND_ftsf233ae_slot0, - OPERAND_ftsf234ae_slot0, - OPERAND_ftsf235ae_slot0, - OPERAND_ftsf236ae_slot0, - OPERAND_ftsf237ae_slot0, - OPERAND_ftsf238ae_slot0, - OPERAND_ftsf239ae_slot0, - OPERAND_ftsf240ae_slot0, - OPERAND_ftsf241ae_slot0, - OPERAND_ftsf242ae_slot0, - OPERAND_ftsf243ae_slot0, - OPERAND_ftsf244ae_slot0, - OPERAND_ftsf245ae_slot0, - OPERAND_ftsf246ae_slot0, - OPERAND_ftsf247ae_slot0, - OPERAND_ftsf248ae_slot0, - OPERAND_ftsf249ae_slot0, - OPERAND_ftsf250ae_slot0, - OPERAND_ftsf251ae_slot0, - OPERAND_ftsf252ae_slot0, - OPERAND_ftsf253ae_slot0, - OPERAND_ftsf254ae_slot0, - OPERAND_ftsf255ae_slot0, - OPERAND_ftsf256ae_slot0, - OPERAND_ftsf257ae_slot0, - OPERAND_ftsf258ae_slot0, - OPERAND_ftsf259ae_slot0, - OPERAND_ftsf260ae_slot0, - OPERAND_ftsf261ae_slot0, - OPERAND_ftsf262ae_slot0, - OPERAND_ftsf263ae_slot0, - OPERAND_ftsf264ae_slot0, - OPERAND_ftsf265ae_slot0, - OPERAND_ftsf266ae_slot0, - OPERAND_ftsf267ae_slot0, - OPERAND_ftsf268ae_slot0, - OPERAND_ftsf269ae_slot0, - OPERAND_ftsf270ae_slot0, - OPERAND_ftsf271ae_slot0, - OPERAND_ftsf272ae_slot0, - OPERAND_ftsf273ae_slot0, - OPERAND_ftsf274ae_slot0, - OPERAND_ftsf275ae_slot0, - OPERAND_ftsf276ae_slot0, - OPERAND_ftsf277ae_slot0, - OPERAND_ftsf278ae_slot0, - OPERAND_ftsf279ae_slot0, - OPERAND_ftsf281ae_slot0, - OPERAND_ftsf282ae_slot0, - OPERAND_ftsf283ae_slot0, - OPERAND_ftsf284ae_slot0, - OPERAND_ftsf286ae_slot0, - OPERAND_ftsf288ae_slot0, - OPERAND_ftsf290ae_slot0, - OPERAND_ftsf292ae_slot0, - OPERAND_ftsf293, - OPERAND_ftsf294ae_slot0, - OPERAND_ftsf295ae_slot0, - OPERAND_ftsf296ae_slot0, - OPERAND_ftsf297ae_slot0, - OPERAND_ftsf298ae_slot0, - OPERAND_ftsf299ae_slot0, - OPERAND_ftsf300ae_slot0, - OPERAND_ftsf301ae_slot0, - OPERAND_ftsf302ae_slot0, - OPERAND_ftsf303ae_slot0, - OPERAND_ftsf304ae_slot0, - OPERAND_ftsf306ae_slot0, - OPERAND_ftsf308ae_slot0, - OPERAND_ftsf309ae_slot0, - OPERAND_ftsf310ae_slot0, - OPERAND_ftsf311ae_slot0, - OPERAND_ftsf312ae_slot0, - OPERAND_ftsf313ae_slot0, - OPERAND_ftsf314ae_slot0, - OPERAND_ftsf315ae_slot0, - OPERAND_ftsf316ae_slot0, - OPERAND_ftsf317ae_slot0, - OPERAND_ftsf318ae_slot0, - OPERAND_ftsf319, - OPERAND_ftsf320ae_slot0, - OPERAND_ftsf321, - OPERAND_ftsf322ae_slot0, - OPERAND_ftsf323ae_slot0, - OPERAND_ftsf324ae_slot0, - OPERAND_ftsf325ae_slot0, - OPERAND_ftsf326ae_slot0, - OPERAND_ftsf328ae_slot0, - OPERAND_ftsf329ae_slot0, - OPERAND_ftsf352ae_slot0, - OPERAND_ftsf353, - OPERAND_ftsf354ae_slot0, - OPERAND_ftsf356ae_slot0, - OPERAND_ftsf357, - OPERAND_ftsf358ae_slot0, - OPERAND_ftsf359ae_slot0, - OPERAND_ftsf360ae_slot0, - OPERAND_ftsf361ae_slot0, - OPERAND_ftsf362ae_slot0, - OPERAND_ftsf364ae_slot0, - OPERAND_ftsf365ae_slot0, - OPERAND_ftsf366ae_slot0, - OPERAND_ftsf368ae_slot0, - OPERAND_ftsf369ae_slot0, - OPERAND_ae_mul32x24fld, - OPERAND_combined1b97e84f_fld115, - OPERAND_combined1b97e84f_fld97, - OPERAND_combined1b97e84f_fld124, - OPERAND_combined1b97e84f_fld79, - OPERAND_combined1b97e84f_fld80, - OPERAND_combined1b97e84f_fld108, - OPERAND_combined1b97e84f_fld101, - OPERAND_combined1b97e84f_fld88, - OPERAND_combined1b97e84f_fld39, - OPERAND_op0_s4_s4, - OPERAND_combined1b97e84f_fld83, - OPERAND_combined1b97e84f_fld90, - OPERAND_combined1b97e84f_fld93, - OPERAND_combined1b97e84f_fld138ae_slot0, - OPERAND_combined1b97e84f_fld130ae_slot0, - OPERAND_combined1b97e84f_fld137ae_slot0, - OPERAND_combined1b97e84f_fld135ae_slot0, - OPERAND_combined1b97e84f_fld136ae_slot0, - OPERAND_combined1b97e84f_fld129ae_slot0, - OPERAND_combined1b97e84f_fld127ae_slot0, - OPERAND_combined1b97e84f_fld128ae_slot0, - OPERAND_combined1b97e84f_fld132ae_slot0, - OPERAND_combined1b97e84f_fld134ae_slot0, - OPERAND_combined4b12daa6_fld122, - OPERAND_combined4b12daa6_fld115, - OPERAND_combined4b12daa6_fld85, - OPERAND_combined4b12daa6_fld119, - OPERAND_combined4b12daa6_fld97, - OPERAND_combined4b12daa6_fld124, - OPERAND_combined4b12daa6_fld79, - OPERAND_combined4b12daa6_fld80, - OPERAND_combined4b12daa6_fld108, - OPERAND_combined1b97e84f_fld54, - OPERAND_combined1b97e84f_fld17, - OPERAND_combined1b97e84f_fld76, - OPERAND_combined1b97e84f_fld73, - OPERAND_combined1b97e84f_fld62, - OPERAND_combined1b97e84f_fld24, - OPERAND_combined1b97e84f_fld70, - OPERAND_combined1b97e84f_fld58, - OPERAND_combined1b97e84f_fld131ae_slot1, - OPERAND_op0_s3_s3, - OPERAND_combined1b97e84f_fld49, - OPERAND_combined1b97e84f_fld51, - OPERAND_combined1b97e84f_fld23, - OPERAND_xt_fld0, - OPERAND_xt_fld1, - OPERAND_s3to1 -}; - - -/* Iclass table. */ - -static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { - { { STATE_PSEXCM }, 'o' }, - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfme_stateArgs[] = { - { { STATE_MESR }, 'o' }, - { { STATE_MEPC }, 'i' }, - { { STATE_MEPS }, 'i' }, - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { - { { OPERAND_ars_entry }, 's' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm12x8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { - { { STATE_WindowBase }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { - { { OPERAND_simm4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { - { { STATE_EPC1 }, 'i' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSOWB }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ai4const }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_simm7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8x256 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4const }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_bbi }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4constu }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_label12 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sae }, 'i' }, - { { OPERAND_op2p1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { - { { OPERAND_soffset }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_uimm16x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ulabel8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ulabel8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_simm12b }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { - { { OPERAND_arr }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimmrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { - { { OPERAND_sas }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_msalp32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sargt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { - { { STATE_LEND }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { - { { STATE_LEND }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { - { { STATE_LEND }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { - { { STATE_LCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { - { { STATE_SAR }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { - { { STATE_SAR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { - { { OPERAND_art }, 'm' } -}; - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { - { { OPERAND_art }, 'm' } -}; - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_243_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'm' }, - { { STATE_PSCALLINC }, 'm' }, - { { STATE_PSOWB }, 'm' }, - { { STATE_PSUM }, 'm' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'i' }, - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { - { { STATE_MISC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { - { { STATE_MISC0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { - { { STATE_MISC0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { - { { STATE_MISC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { - { { STATE_MISC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { - { { STATE_MISC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_mul16_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_mul32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPC1 }, 'i' }, - { { STATE_EPC2 }, 'i' }, - { { STATE_EPC3 }, 'i' }, - { { STATE_EPC4 }, 'i' }, - { { STATE_EPC5 }, 'i' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_EPC7 }, 'i' }, - { { STATE_EPS2 }, 'i' }, - { { STATE_EPS3 }, 'i' }, - { { STATE_EPS4 }, 'i' }, - { { STATE_EPS5 }, 'i' }, - { { STATE_EPS6 }, 'i' }, - { { STATE_EPS7 }, 'i' }, - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { - { { STATE_INTERRUPT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { - { { OPERAND_imms }, 'i' }, - { { OPERAND_immt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'i' }, - { { STATE_DBNUM }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'o' }, - { { STATE_DBNUM }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'm' }, - { { STATE_DBNUM }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { - { { STATE_ICOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { - { { STATE_DDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_InOCDMode }, 'i' }, - { { STATE_DDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { - { { STATE_InOCDMode }, 'i' }, - { { STATE_DDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { - { { STATE_InOCDMode }, 'm' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_bs }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_bs4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_bs8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { - { { OPERAND_bs }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { - { { OPERAND_arr }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_brall }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_brall }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_brall }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { - { { STATE_CCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'm' } -}; - - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mepc_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mepc_stateArgs[] = { - { { STATE_MEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mepc_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mepc_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MEPC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mepc_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mepc_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MEPC }, 'm' } -}; - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_meps_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_meps_stateArgs[] = { - { { STATE_MEPS }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_meps_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_meps_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MEPS }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_meps_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_meps_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MEPS }, 'm' } -}; - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mesave_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mesave_stateArgs[] = { - { { STATE_MESAVE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mesave_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mesave_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MESAVE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mesave_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mesave_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MESAVE }, 'm' } -}; - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mesr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mesr_stateArgs[] = { - { { STATE_MESR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mesr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mesr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MESR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mesr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mesr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MESR }, 'm' } -}; - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mecr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mecr_stateArgs[] = { - { { STATE_MECR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mecr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mecr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MECR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mecr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mecr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MECR }, 'm' } -}; - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mevaddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mevaddr_stateArgs[] = { - { { STATE_MEVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mevaddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mevaddr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MEVADDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mevaddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mevaddr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MEVADDR }, 'm' } -}; - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_stateArgs[] = { - { { STATE_PREFCTL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_stateArgs[] = { - { { STATE_PREFCTL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_stateArgs[] = { - { { STATE_PREFCTL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { - { { STATE_CPENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { - { { STATE_CPENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_tp7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_tp7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' }, - { { STATE_XTSYNC }, 'i' }, - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'i' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'o' }, - { { STATE_AE_SAR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = { - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = { - { { STATE_AE_BITHEAD }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_TABLESIZE }, 'i' }, - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = { - { { STATE_AE_BITPTR }, 'o' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_sd_no_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_sd_no_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_sd_no_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_sd_no_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_stateArgs[] = { - { { STATE_AE_SAR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_stateArgs[] = { - { { STATE_AE_BITPTR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_stateArgs[] = { - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_stateArgs[] = { - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_stateArgs[] = { - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_stateArgs[] = { - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_rur_threadptr_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_iclass_rur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'i' }, -}; - -static xtensa_arg_internal Iclass_iclass_wur_threadptr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_wur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'o' }, -}; - - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_i_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_x_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zerop48_args[] = { - { { OPERAND_ps }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zerop48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp48_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp48_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp16_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp16_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zeroq56_args[] = { - { { OPERAND_qr1_w }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zeroq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtq56_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bs }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfq56_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bs }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_cvt_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_cvt_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_satq48s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_satq48s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncq32_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncq32_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = { - { { OPERAND_alupppb_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = { - { { OPERAND_alupppb_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltp24s_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lep24s_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lep24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqp24_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bt }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bt }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_slliq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_slliq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srliq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srliq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraiq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraiq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltq56s_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_leq56s_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_leq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqq56_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sha32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl32t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl32t_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16t_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16c_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16c_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldsht_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldsht_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lb_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ae_ohba2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbk_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_ohba2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_db_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_db_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_dbi_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_ohba }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_dbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel32t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel32t_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel16t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel16t_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sb_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sb_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbi_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_ae_ohba }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vles16c_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vles16c_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbf_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbf_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_ADDBRBA32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cbegin0_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cbegin0_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cbegin0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cbegin0_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cend0_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cend0_stateArgs[] = { - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cend0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cend0_stateArgs[] = { - { { STATE_AE_CEND0 }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ56_C_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ56_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_READ_IPQ_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_interface Iclass_iclass_READ_IPQ_intfArgs[] = { - INTERFACE_IPQ -}; - -static xtensa_arg_internal Iclass_iclass_CHECK_IPQ_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_interface Iclass_iclass_CHECK_IPQ_intfArgs[] = { - INTERFACE_IPQ_NOTRDY -}; - -static xtensa_arg_internal Iclass_iclass_WRITE_OPQ_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_interface Iclass_iclass_WRITE_OPQ_intfArgs[] = { - INTERFACE_OPQ -}; - -static xtensa_arg_internal Iclass_iclass_CHECK_OPQ_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_interface Iclass_iclass_CHECK_OPQ_intfArgs[] = { - INTERFACE_OPQ_NOTRDY -}; - -static xtensa_arg_internal Iclass_rur_expstate_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { - { { STATE_EXPSTATE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_expstate_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { - { { STATE_EXPSTATE }, 'o' } -}; - -static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { - INTERFACE_IMPWIRE -}; - -static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { - { { OPERAND_bitindex }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' } -}; - -static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { - { { OPERAND_bitindex }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' } -}; - -static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' } -}; - -static xtensa_iclass_internal iclasses[] = { - { 0, 0 /* xt_iclass_excw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_rfe */, - 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfme */, - 9, Iclass_xt_iclass_rfme_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfde */, - 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_syscall */, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call12_args, - 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call8_args, - 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call4_args, - 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx12_args, - 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx8_args, - 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx4_args, - 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_entry_args, - 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movsp_args, - 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rotw_args, - 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_retw_args, - 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfwou */, - 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_l32e_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32e_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowbase_args, - 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowbase_args, - 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowbase_args, - 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowstart_args, - 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowstart_args, - 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowstart_args, - 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_add_n_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addi_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bz6_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill_n */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_loadi4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_mov_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_movi_n_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nopn */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_retn_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_storei4_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addmi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addsub_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bit_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8b_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8u_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bst8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bsz12_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_callx0_args, - 0, 0, 0, 0 }, - { 4, Iclass_xt_iclass_exti_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jump_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jumpx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16ui_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16si_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_l32r_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l8i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_loop_args, - 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_loopz_args, - 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_movz_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_neg_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nop */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_return_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_simcall */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s16i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32nb_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s8i_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_sar_args, - 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_sari_args, - 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shifts_args, - 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_shiftst_args, - 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shiftt_args, - 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_slli_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srli_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_memw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_extw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_isync */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_sync */, - 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rsil_args, - 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lend_args, - 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lend_args, - 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lend_args, - 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lcount_args, - 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lcount_args, - 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lcount_args, - 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lbeg_args, - 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lbeg_args, - 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lbeg_args, - 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_sar_args, - 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_sar_args, - 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_sar_args, - 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_acclo_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acclo_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acclo_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_acchi_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acchi_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acchi_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_memctl_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_memctl_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_memctl_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_mepc_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mepc_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_mepc_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_meps_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_meps_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_meps_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_mesave_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mesave_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_mesave_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_mesr_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mesr_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_mesr_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_mecr_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mecr_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_mecr_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_mevaddr_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mevaddr_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_mevaddr_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_configid0_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_configid0_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_configid1_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_243_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ps_args, - 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ps_args, - 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ps_args, - 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc1_args, - 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc1_args, - 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc1_args, - 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave1_args, - 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave1_args, - 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave1_args, - 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc2_args, - 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc2_args, - 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc2_args, - 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave2_args, - 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave2_args, - 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave2_args, - 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc3_args, - 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc3_args, - 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc3_args, - 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave3_args, - 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave3_args, - 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave3_args, - 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc4_args, - 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc4_args, - 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc4_args, - 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave4_args, - 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave4_args, - 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave4_args, - 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc5_args, - 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc5_args, - 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc5_args, - 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave5_args, - 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave5_args, - 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave5_args, - 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc6_args, - 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc6_args, - 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc6_args, - 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave6_args, - 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave6_args, - 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave6_args, - 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc7_args, - 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc7_args, - 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc7_args, - 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave7_args, - 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave7_args, - 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave7_args, - 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps2_args, - 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps2_args, - 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps2_args, - 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps3_args, - 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps3_args, - 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps3_args, - 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps4_args, - 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps4_args, - 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps4_args, - 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps5_args, - 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps5_args, - 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps5_args, - 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps6_args, - 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps6_args, - 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps6_args, - 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps7_args, - 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps7_args, - 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps7_args, - 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excvaddr_args, - 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excvaddr_args, - 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excvaddr_args, - 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_depc_args, - 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_depc_args, - 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_depc_args, - 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_exccause_args, - 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_exccause_args, - 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_exccause_args, - 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc0_args, - 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc0_args, - 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc0_args, - 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc1_args, - 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc1_args, - 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc1_args, - 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_prid_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_vecbase_args, - 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_vecbase_args, - 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_vecbase_args, - 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, - { 3, Iclass_xt_mul16_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_mul32_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rfi_args, - 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wait_args, - 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_interrupt_args, - 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intset_args, - 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intclear_args, - 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_intenable_args, - 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intenable_args, - 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_intenable_args, - 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_break_args, - 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_break_n_args, - 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka0_args, - 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka0_args, - 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka0_args, - 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc0_args, - 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc0_args, - 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc0_args, - 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka1_args, - 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka1_args, - 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka1_args, - 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc1_args, - 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc1_args, - 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc1_args, - 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka0_args, - 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka0_args, - 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka0_args, - 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka1_args, - 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka1_args, - 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka1_args, - 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreakenable_args, - 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreakenable_args, - 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreakenable_args, - 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_debugcause_args, - 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_debugcause_args, - 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_debugcause_args, - 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icount_args, - 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icount_args, - 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icount_args, - 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icountlevel_args, - 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icountlevel_args, - 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icountlevel_args, - 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ddr_args, - 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ddr_args, - 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ddr_args, - 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_lddr32_p_args, - 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_sddr32_p_args, - 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfdo_args, - 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfdd */, - 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mmid_args, - 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_bbool1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbool4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbool8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbranch_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bmove_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_RSR_BR_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_WSR_BR_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_XSR_BR_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccount_args, - 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccount_args, - 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccount_args, - 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare0_args, - 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare0_args, - 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare0_args, - 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare1_args, - 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare1_args, - 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare1_args, - 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare2_args, - 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare2_args, - 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare2_args, - 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_icache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_icache_lock_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_icache_inv_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_licx_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_sicx_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_dcache_dyn_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_ind_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_inv_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dpf_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_lock_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_sdct_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_ldct_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_prefctl_args, - 1, Iclass_xt_iclass_rsr_prefctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_prefctl_args, - 1, Iclass_xt_iclass_wsr_prefctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_prefctl_args, - 1, Iclass_xt_iclass_xsr_prefctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_idtlb_args, - 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rdtlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wdtlb_args, - 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_iitlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_ritlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_witlb_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_cpenable_args, - 1, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_cpenable_args, - 1, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_cpenable_args, - 1, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_clamp_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_minmax_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_nsa_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_sx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32ai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32ri_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32c1i_args, - 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_scompare1_args, - 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_scompare1_args, - 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_scompare1_args, - 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_atomctl_args, - 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_atomctl_args, - 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_atomctl_args, - 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_div_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rer_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wer_args, - 0, 0, 0, 0 }, - { 1, Iclass_rur_ae_ovf_sar_args, - 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_ovf_sar_args, - 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_bithead_args, - 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_bithead_args, - 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_ts_fts_bu_bp_args, - 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_ts_fts_bu_bp_args, - 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_sd_no_args, - 3, Iclass_rur_ae_sd_no_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_sd_no_args, - 3, Iclass_wur_ae_sd_no_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_overflow_args, - 2, Iclass_ae_iclass_rur_ae_overflow_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_overflow_args, - 2, Iclass_ae_iclass_wur_ae_overflow_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_sar_args, - 2, Iclass_ae_iclass_rur_ae_sar_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_sar_args, - 2, Iclass_ae_iclass_wur_ae_sar_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_bitptr_args, - 2, Iclass_ae_iclass_rur_ae_bitptr_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_bitptr_args, - 2, Iclass_ae_iclass_wur_ae_bitptr_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_bitsused_args, - 2, Iclass_ae_iclass_rur_ae_bitsused_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_bitsused_args, - 2, Iclass_ae_iclass_wur_ae_bitsused_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_tablesize_args, - 2, Iclass_ae_iclass_rur_ae_tablesize_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_tablesize_args, - 2, Iclass_ae_iclass_wur_ae_tablesize_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_first_ts_args, - 2, Iclass_ae_iclass_rur_ae_first_ts_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_first_ts_args, - 2, Iclass_ae_iclass_wur_ae_first_ts_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_nextoffset_args, - 2, Iclass_ae_iclass_rur_ae_nextoffset_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_nextoffset_args, - 2, Iclass_ae_iclass_wur_ae_nextoffset_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_searchdone_args, - 2, Iclass_ae_iclass_rur_ae_searchdone_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_searchdone_args, - 2, Iclass_ae_iclass_wur_ae_searchdone_stateArgs, 0, 0 }, - - { 1, Iclass_iclass_rur_threadptr_args, - 2, Iclass_iclass_rur_threadptr_stateArgs, 0, 0 }, - { 1, Iclass_iclass_wur_threadptr_args, - 2, Iclass_iclass_wur_threadptr_stateArgs, 0, 0 }, - - { 3, Iclass_ae_iclass_lp16f_i_args, - 1, Iclass_ae_iclass_lp16f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_iu_args, - 1, Iclass_ae_iclass_lp16f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_x_args, - 1, Iclass_ae_iclass_lp16f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_xu_args, - 1, Iclass_ae_iclass_lp16f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_i_args, - 1, Iclass_ae_iclass_lp24_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_iu_args, - 1, Iclass_ae_iclass_lp24_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_x_args, - 1, Iclass_ae_iclass_lp24_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_xu_args, - 1, Iclass_ae_iclass_lp24_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_i_args, - 1, Iclass_ae_iclass_lp24f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_iu_args, - 1, Iclass_ae_iclass_lp24f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_x_args, - 1, Iclass_ae_iclass_lp24f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_xu_args, - 1, Iclass_ae_iclass_lp24f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_i_args, - 1, Iclass_ae_iclass_lp16x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_iu_args, - 1, Iclass_ae_iclass_lp16x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_x_args, - 1, Iclass_ae_iclass_lp16x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_xu_args, - 1, Iclass_ae_iclass_lp16x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_i_args, - 1, Iclass_ae_iclass_lp24x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_iu_args, - 1, Iclass_ae_iclass_lp24x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_x_args, - 1, Iclass_ae_iclass_lp24x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_xu_args, - 1, Iclass_ae_iclass_lp24x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_i_args, - 1, Iclass_ae_iclass_lp24x2_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_iu_args, - 1, Iclass_ae_iclass_lp24x2_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_x_args, - 1, Iclass_ae_iclass_lp24x2_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_xu_args, - 1, Iclass_ae_iclass_lp24x2_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_i_args, - 1, Iclass_ae_iclass_sp16x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_iu_args, - 1, Iclass_ae_iclass_sp16x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_x_args, - 1, Iclass_ae_iclass_sp16x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_xu_args, - 1, Iclass_ae_iclass_sp16x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_i_args, - 1, Iclass_ae_iclass_sp24x2s_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_iu_args, - 1, Iclass_ae_iclass_sp24x2s_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_x_args, - 1, Iclass_ae_iclass_sp24x2s_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_xu_args, - 1, Iclass_ae_iclass_sp24x2s_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_i_args, - 1, Iclass_ae_iclass_sp24x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_iu_args, - 1, Iclass_ae_iclass_sp24x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_x_args, - 1, Iclass_ae_iclass_sp24x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_xu_args, - 1, Iclass_ae_iclass_sp24x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_i_args, - 1, Iclass_ae_iclass_sp16f_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_iu_args, - 1, Iclass_ae_iclass_sp16f_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_x_args, - 1, Iclass_ae_iclass_sp16f_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_xu_args, - 1, Iclass_ae_iclass_sp16f_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_i_args, - 1, Iclass_ae_iclass_sp24s_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_iu_args, - 1, Iclass_ae_iclass_sp24s_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_x_args, - 1, Iclass_ae_iclass_sp24s_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_xu_args, - 1, Iclass_ae_iclass_sp24s_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_i_args, - 1, Iclass_ae_iclass_sp24f_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_iu_args, - 1, Iclass_ae_iclass_sp24f_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_x_args, - 1, Iclass_ae_iclass_sp24f_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_xu_args, - 1, Iclass_ae_iclass_sp24f_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_i_args, - 1, Iclass_ae_iclass_lq56_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_iu_args, - 1, Iclass_ae_iclass_lq56_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_x_args, - 1, Iclass_ae_iclass_lq56_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_xu_args, - 1, Iclass_ae_iclass_lq56_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_i_args, - 1, Iclass_ae_iclass_lq32f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_iu_args, - 1, Iclass_ae_iclass_lq32f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_x_args, - 1, Iclass_ae_iclass_lq32f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_xu_args, - 1, Iclass_ae_iclass_lq32f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_i_args, - 1, Iclass_ae_iclass_sq56s_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_iu_args, - 1, Iclass_ae_iclass_sq56s_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_x_args, - 1, Iclass_ae_iclass_sq56s_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_xu_args, - 1, Iclass_ae_iclass_sq56s_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_i_args, - 1, Iclass_ae_iclass_sq32f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_iu_args, - 1, Iclass_ae_iclass_sq32f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_x_args, - 1, Iclass_ae_iclass_sq32f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_xu_args, - 1, Iclass_ae_iclass_sq32f_xu_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_zerop48_args, - 1, Iclass_ae_iclass_zerop48_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movp48_args, - 1, Iclass_ae_iclass_movp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_ll_args, - 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Iclass_icls_AE_LQ56_C_args, - 3, Iclass_icls_AE_LQ56_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SQ56S_C_args, - 3, Iclass_icls_AE_SQ56S_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LQ32F_C_args, - 3, Iclass_icls_AE_LQ32F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SQ32F_C_args, - 3, Iclass_icls_AE_SQ32F_C_stateArgs, 0, 0 }, - { 1, Iclass_iclass_READ_IPQ_args, - 0, 0, 1, Iclass_iclass_READ_IPQ_intfArgs }, - { 1, Iclass_iclass_CHECK_IPQ_args, - 0, 0, 1, Iclass_iclass_CHECK_IPQ_intfArgs }, - { 1, Iclass_iclass_WRITE_OPQ_args, - 0, 0, 1, Iclass_iclass_WRITE_OPQ_intfArgs }, - { 1, Iclass_iclass_CHECK_OPQ_args, - 0, 0, 1, Iclass_iclass_CHECK_OPQ_intfArgs }, - { 1, Iclass_rur_expstate_args, - 1, Iclass_rur_expstate_stateArgs, 0, 0 }, - { 1, Iclass_wur_expstate_args, - 1, Iclass_wur_expstate_stateArgs, 0, 0 }, - { 1, Iclass_iclass_READ_IMPWIRE_args, - 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, - { 1, Iclass_iclass_SETB_EXPSTATE_args, - 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, - { 1, Iclass_iclass_CLRB_EXPSTATE_args, - 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, - { 2, Iclass_iclass_WRMSK_EXPSTATE_args, - 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } -}; - -enum xtensa_iclass_id { - ICLASS_xt_iclass_excw, - ICLASS_xt_iclass_rfe, - ICLASS_xt_iclass_rfme, - ICLASS_xt_iclass_rfde, - ICLASS_xt_iclass_syscall, - ICLASS_xt_iclass_call12, - ICLASS_xt_iclass_call8, - ICLASS_xt_iclass_call4, - ICLASS_xt_iclass_callx12, - ICLASS_xt_iclass_callx8, - ICLASS_xt_iclass_callx4, - ICLASS_xt_iclass_entry, - ICLASS_xt_iclass_movsp, - ICLASS_xt_iclass_rotw, - ICLASS_xt_iclass_retw, - ICLASS_xt_iclass_rfwou, - ICLASS_xt_iclass_l32e, - ICLASS_xt_iclass_s32e, - ICLASS_xt_iclass_rsr_windowbase, - ICLASS_xt_iclass_wsr_windowbase, - ICLASS_xt_iclass_xsr_windowbase, - ICLASS_xt_iclass_rsr_windowstart, - ICLASS_xt_iclass_wsr_windowstart, - ICLASS_xt_iclass_xsr_windowstart, - ICLASS_xt_iclass_add_n, - ICLASS_xt_iclass_addi_n, - ICLASS_xt_iclass_bz6, - ICLASS_xt_iclass_ill_n, - ICLASS_xt_iclass_loadi4, - ICLASS_xt_iclass_mov_n, - ICLASS_xt_iclass_movi_n, - ICLASS_xt_iclass_nopn, - ICLASS_xt_iclass_retn, - ICLASS_xt_iclass_storei4, - ICLASS_xt_iclass_addi, - ICLASS_xt_iclass_addmi, - ICLASS_xt_iclass_addsub, - ICLASS_xt_iclass_bit, - ICLASS_xt_iclass_bsi8, - ICLASS_xt_iclass_bsi8b, - ICLASS_xt_iclass_bsi8u, - ICLASS_xt_iclass_bst8, - ICLASS_xt_iclass_bsz12, - ICLASS_xt_iclass_call0, - ICLASS_xt_iclass_callx0, - ICLASS_xt_iclass_exti, - ICLASS_xt_iclass_ill, - ICLASS_xt_iclass_jump, - ICLASS_xt_iclass_jumpx, - ICLASS_xt_iclass_l16ui, - ICLASS_xt_iclass_l16si, - ICLASS_xt_iclass_l32i, - ICLASS_xt_iclass_l32r, - ICLASS_xt_iclass_l8i, - ICLASS_xt_iclass_loop, - ICLASS_xt_iclass_loopz, - ICLASS_xt_iclass_movi, - ICLASS_xt_iclass_movz, - ICLASS_xt_iclass_neg, - ICLASS_xt_iclass_nop, - ICLASS_xt_iclass_return, - ICLASS_xt_iclass_simcall, - ICLASS_xt_iclass_s16i, - ICLASS_xt_iclass_s32i, - ICLASS_xt_iclass_s32nb, - ICLASS_xt_iclass_s8i, - ICLASS_xt_iclass_sar, - ICLASS_xt_iclass_sari, - ICLASS_xt_iclass_shifts, - ICLASS_xt_iclass_shiftst, - ICLASS_xt_iclass_shiftt, - ICLASS_xt_iclass_slli, - ICLASS_xt_iclass_srai, - ICLASS_xt_iclass_srli, - ICLASS_xt_iclass_memw, - ICLASS_xt_iclass_extw, - ICLASS_xt_iclass_isync, - ICLASS_xt_iclass_sync, - ICLASS_xt_iclass_rsil, - ICLASS_xt_iclass_rsr_lend, - ICLASS_xt_iclass_wsr_lend, - ICLASS_xt_iclass_xsr_lend, - ICLASS_xt_iclass_rsr_lcount, - ICLASS_xt_iclass_wsr_lcount, - ICLASS_xt_iclass_xsr_lcount, - ICLASS_xt_iclass_rsr_lbeg, - ICLASS_xt_iclass_wsr_lbeg, - ICLASS_xt_iclass_xsr_lbeg, - ICLASS_xt_iclass_rsr_sar, - ICLASS_xt_iclass_wsr_sar, - ICLASS_xt_iclass_xsr_sar, - - ICLASS_xt_iclass_rsr_acclo, - ICLASS_xt_iclass_wsr_acclo, - ICLASS_xt_iclass_xsr_acclo, - - ICLASS_xt_iclass_rsr_acchi, - ICLASS_xt_iclass_wsr_acchi, - ICLASS_xt_iclass_xsr_acchi, - - ICLASS_xt_iclass_rsr_memctl, - ICLASS_xt_iclass_wsr_memctl, - ICLASS_xt_iclass_xsr_memctl, - - ICLASS_xt_iclass_rsr_mepc, - ICLASS_xt_iclass_wsr_mepc, - ICLASS_xt_iclass_xsr_mepc, - ICLASS_xt_iclass_rsr_meps, - ICLASS_xt_iclass_wsr_meps, - ICLASS_xt_iclass_xsr_meps, - ICLASS_xt_iclass_rsr_mesave, - ICLASS_xt_iclass_wsr_mesave, - ICLASS_xt_iclass_xsr_mesave, - ICLASS_xt_iclass_rsr_mesr, - ICLASS_xt_iclass_wsr_mesr, - ICLASS_xt_iclass_xsr_mesr, - ICLASS_xt_iclass_rsr_mecr, - ICLASS_xt_iclass_wsr_mecr, - ICLASS_xt_iclass_xsr_mecr, - ICLASS_xt_iclass_rsr_mevaddr, - ICLASS_xt_iclass_wsr_mevaddr, - ICLASS_xt_iclass_xsr_mevaddr, - - ICLASS_xt_iclass_rsr_litbase, - ICLASS_xt_iclass_wsr_litbase, - ICLASS_xt_iclass_xsr_litbase, - ICLASS_xt_iclass_rsr_configid0, - ICLASS_xt_iclass_wsr_configid0, - ICLASS_xt_iclass_rsr_configid1, - ICLASS_xt_iclass_rsr_243, - ICLASS_xt_iclass_rsr_ps, - ICLASS_xt_iclass_wsr_ps, - ICLASS_xt_iclass_xsr_ps, - ICLASS_xt_iclass_rsr_epc1, - ICLASS_xt_iclass_wsr_epc1, - ICLASS_xt_iclass_xsr_epc1, - ICLASS_xt_iclass_rsr_excsave1, - ICLASS_xt_iclass_wsr_excsave1, - ICLASS_xt_iclass_xsr_excsave1, - ICLASS_xt_iclass_rsr_epc2, - ICLASS_xt_iclass_wsr_epc2, - ICLASS_xt_iclass_xsr_epc2, - ICLASS_xt_iclass_rsr_excsave2, - ICLASS_xt_iclass_wsr_excsave2, - ICLASS_xt_iclass_xsr_excsave2, - ICLASS_xt_iclass_rsr_epc3, - ICLASS_xt_iclass_wsr_epc3, - ICLASS_xt_iclass_xsr_epc3, - ICLASS_xt_iclass_rsr_excsave3, - ICLASS_xt_iclass_wsr_excsave3, - ICLASS_xt_iclass_xsr_excsave3, - ICLASS_xt_iclass_rsr_epc4, - ICLASS_xt_iclass_wsr_epc4, - ICLASS_xt_iclass_xsr_epc4, - ICLASS_xt_iclass_rsr_excsave4, - ICLASS_xt_iclass_wsr_excsave4, - ICLASS_xt_iclass_xsr_excsave4, - ICLASS_xt_iclass_rsr_epc5, - ICLASS_xt_iclass_wsr_epc5, - ICLASS_xt_iclass_xsr_epc5, - ICLASS_xt_iclass_rsr_excsave5, - ICLASS_xt_iclass_wsr_excsave5, - ICLASS_xt_iclass_xsr_excsave5, - ICLASS_xt_iclass_rsr_epc6, - ICLASS_xt_iclass_wsr_epc6, - ICLASS_xt_iclass_xsr_epc6, - ICLASS_xt_iclass_rsr_excsave6, - ICLASS_xt_iclass_wsr_excsave6, - ICLASS_xt_iclass_xsr_excsave6, - ICLASS_xt_iclass_rsr_epc7, - ICLASS_xt_iclass_wsr_epc7, - ICLASS_xt_iclass_xsr_epc7, - ICLASS_xt_iclass_rsr_excsave7, - ICLASS_xt_iclass_wsr_excsave7, - ICLASS_xt_iclass_xsr_excsave7, - ICLASS_xt_iclass_rsr_eps2, - ICLASS_xt_iclass_wsr_eps2, - ICLASS_xt_iclass_xsr_eps2, - ICLASS_xt_iclass_rsr_eps3, - ICLASS_xt_iclass_wsr_eps3, - ICLASS_xt_iclass_xsr_eps3, - ICLASS_xt_iclass_rsr_eps4, - ICLASS_xt_iclass_wsr_eps4, - ICLASS_xt_iclass_xsr_eps4, - ICLASS_xt_iclass_rsr_eps5, - ICLASS_xt_iclass_wsr_eps5, - ICLASS_xt_iclass_xsr_eps5, - ICLASS_xt_iclass_rsr_eps6, - ICLASS_xt_iclass_wsr_eps6, - ICLASS_xt_iclass_xsr_eps6, - ICLASS_xt_iclass_rsr_eps7, - ICLASS_xt_iclass_wsr_eps7, - ICLASS_xt_iclass_xsr_eps7, - ICLASS_xt_iclass_rsr_excvaddr, - ICLASS_xt_iclass_wsr_excvaddr, - ICLASS_xt_iclass_xsr_excvaddr, - ICLASS_xt_iclass_rsr_depc, - ICLASS_xt_iclass_wsr_depc, - ICLASS_xt_iclass_xsr_depc, - ICLASS_xt_iclass_rsr_exccause, - ICLASS_xt_iclass_wsr_exccause, - ICLASS_xt_iclass_xsr_exccause, - ICLASS_xt_iclass_rsr_misc0, - ICLASS_xt_iclass_wsr_misc0, - ICLASS_xt_iclass_xsr_misc0, - ICLASS_xt_iclass_rsr_misc1, - ICLASS_xt_iclass_wsr_misc1, - ICLASS_xt_iclass_xsr_misc1, - ICLASS_xt_iclass_rsr_prid, - ICLASS_xt_iclass_rsr_vecbase, - ICLASS_xt_iclass_wsr_vecbase, - ICLASS_xt_iclass_xsr_vecbase, - ICLASS_xt_mul16, - ICLASS_xt_mul32, - ICLASS_xt_iclass_rfi, - ICLASS_xt_iclass_wait, - ICLASS_xt_iclass_rsr_interrupt, - ICLASS_xt_iclass_wsr_intset, - ICLASS_xt_iclass_wsr_intclear, - ICLASS_xt_iclass_rsr_intenable, - ICLASS_xt_iclass_wsr_intenable, - ICLASS_xt_iclass_xsr_intenable, - ICLASS_xt_iclass_break, - ICLASS_xt_iclass_break_n, - ICLASS_xt_iclass_rsr_dbreaka0, - ICLASS_xt_iclass_wsr_dbreaka0, - ICLASS_xt_iclass_xsr_dbreaka0, - ICLASS_xt_iclass_rsr_dbreakc0, - ICLASS_xt_iclass_wsr_dbreakc0, - ICLASS_xt_iclass_xsr_dbreakc0, - ICLASS_xt_iclass_rsr_dbreaka1, - ICLASS_xt_iclass_wsr_dbreaka1, - ICLASS_xt_iclass_xsr_dbreaka1, - ICLASS_xt_iclass_rsr_dbreakc1, - ICLASS_xt_iclass_wsr_dbreakc1, - ICLASS_xt_iclass_xsr_dbreakc1, - ICLASS_xt_iclass_rsr_ibreaka0, - ICLASS_xt_iclass_wsr_ibreaka0, - ICLASS_xt_iclass_xsr_ibreaka0, - ICLASS_xt_iclass_rsr_ibreaka1, - ICLASS_xt_iclass_wsr_ibreaka1, - ICLASS_xt_iclass_xsr_ibreaka1, - ICLASS_xt_iclass_rsr_ibreakenable, - ICLASS_xt_iclass_wsr_ibreakenable, - ICLASS_xt_iclass_xsr_ibreakenable, - ICLASS_xt_iclass_rsr_debugcause, - ICLASS_xt_iclass_wsr_debugcause, - ICLASS_xt_iclass_xsr_debugcause, - ICLASS_xt_iclass_rsr_icount, - ICLASS_xt_iclass_wsr_icount, - ICLASS_xt_iclass_xsr_icount, - ICLASS_xt_iclass_rsr_icountlevel, - ICLASS_xt_iclass_wsr_icountlevel, - ICLASS_xt_iclass_xsr_icountlevel, - ICLASS_xt_iclass_rsr_ddr, - ICLASS_xt_iclass_wsr_ddr, - ICLASS_xt_iclass_xsr_ddr, - ICLASS_xt_iclass_lddr32_p, - ICLASS_xt_iclass_sddr32_p, - ICLASS_xt_iclass_rfdo, - ICLASS_xt_iclass_rfdd, - ICLASS_xt_iclass_wsr_mmid, - ICLASS_xt_iclass_bbool1, - ICLASS_xt_iclass_bbool4, - ICLASS_xt_iclass_bbool8, - ICLASS_xt_iclass_bbranch, - ICLASS_xt_iclass_bmove, - ICLASS_xt_iclass_RSR_BR, - ICLASS_xt_iclass_WSR_BR, - ICLASS_xt_iclass_XSR_BR, - ICLASS_xt_iclass_rsr_ccount, - ICLASS_xt_iclass_wsr_ccount, - ICLASS_xt_iclass_xsr_ccount, - ICLASS_xt_iclass_rsr_ccompare0, - ICLASS_xt_iclass_wsr_ccompare0, - ICLASS_xt_iclass_xsr_ccompare0, - ICLASS_xt_iclass_rsr_ccompare1, - ICLASS_xt_iclass_wsr_ccompare1, - ICLASS_xt_iclass_xsr_ccompare1, - ICLASS_xt_iclass_rsr_ccompare2, - ICLASS_xt_iclass_wsr_ccompare2, - ICLASS_xt_iclass_xsr_ccompare2, - ICLASS_xt_iclass_icache, - ICLASS_xt_iclass_icache_lock, - ICLASS_xt_iclass_icache_inv, - ICLASS_xt_iclass_licx, - ICLASS_xt_iclass_sicx, - ICLASS_xt_iclass_dcache, - ICLASS_xt_iclass_dcache_dyn, - ICLASS_xt_iclass_dcache_ind, - ICLASS_xt_iclass_dcache_inv, - ICLASS_xt_iclass_dpf, - ICLASS_xt_iclass_dcache_lock, - ICLASS_xt_iclass_sdct, - ICLASS_xt_iclass_ldct, - ICLASS_xt_iclass_rsr_prefctl, - ICLASS_xt_iclass_wsr_prefctl, - ICLASS_xt_iclass_xsr_prefctl, - ICLASS_xt_iclass_idtlb, - ICLASS_xt_iclass_rdtlb, - ICLASS_xt_iclass_wdtlb, - ICLASS_xt_iclass_iitlb, - ICLASS_xt_iclass_ritlb, - ICLASS_xt_iclass_witlb, - ICLASS_xt_iclass_rsr_cpenable, - ICLASS_xt_iclass_wsr_cpenable, - ICLASS_xt_iclass_xsr_cpenable, - ICLASS_xt_iclass_clamp, - ICLASS_xt_iclass_minmax, - ICLASS_xt_iclass_nsa, - ICLASS_xt_iclass_sx, - ICLASS_xt_iclass_l32ai, - ICLASS_xt_iclass_s32ri, - ICLASS_xt_iclass_s32c1i, - ICLASS_xt_iclass_rsr_scompare1, - ICLASS_xt_iclass_wsr_scompare1, - ICLASS_xt_iclass_xsr_scompare1, - ICLASS_xt_iclass_rsr_atomctl, - ICLASS_xt_iclass_wsr_atomctl, - ICLASS_xt_iclass_xsr_atomctl, - ICLASS_xt_iclass_div, - ICLASS_xt_iclass_rer, - ICLASS_xt_iclass_wer, - ICLASS_rur_ae_ovf_sar, - ICLASS_wur_ae_ovf_sar, - ICLASS_rur_ae_bithead, - ICLASS_wur_ae_bithead, - ICLASS_rur_ae_ts_fts_bu_bp, - ICLASS_wur_ae_ts_fts_bu_bp, - ICLASS_rur_ae_sd_no, - ICLASS_wur_ae_sd_no, - ICLASS_ae_iclass_rur_ae_overflow, - ICLASS_ae_iclass_wur_ae_overflow, - ICLASS_ae_iclass_rur_ae_sar, - ICLASS_ae_iclass_wur_ae_sar, - ICLASS_ae_iclass_rur_ae_bitptr, - ICLASS_ae_iclass_wur_ae_bitptr, - ICLASS_ae_iclass_rur_ae_bitsused, - ICLASS_ae_iclass_wur_ae_bitsused, - ICLASS_ae_iclass_rur_ae_tablesize, - ICLASS_ae_iclass_wur_ae_tablesize, - ICLASS_ae_iclass_rur_ae_first_ts, - ICLASS_ae_iclass_wur_ae_first_ts, - ICLASS_ae_iclass_rur_ae_nextoffset, - ICLASS_ae_iclass_wur_ae_nextoffset, - ICLASS_ae_iclass_rur_ae_searchdone, - ICLASS_ae_iclass_wur_ae_searchdone, - ICLASS_iclass_rur_threadptr, - ICLASS_iclass_wur_threadptr, - ICLASS_ae_iclass_lp16f_i, - ICLASS_ae_iclass_lp16f_iu, - ICLASS_ae_iclass_lp16f_x, - ICLASS_ae_iclass_lp16f_xu, - ICLASS_ae_iclass_lp24_i, - ICLASS_ae_iclass_lp24_iu, - ICLASS_ae_iclass_lp24_x, - ICLASS_ae_iclass_lp24_xu, - ICLASS_ae_iclass_lp24f_i, - ICLASS_ae_iclass_lp24f_iu, - ICLASS_ae_iclass_lp24f_x, - ICLASS_ae_iclass_lp24f_xu, - ICLASS_ae_iclass_lp16x2f_i, - ICLASS_ae_iclass_lp16x2f_iu, - ICLASS_ae_iclass_lp16x2f_x, - ICLASS_ae_iclass_lp16x2f_xu, - ICLASS_ae_iclass_lp24x2f_i, - ICLASS_ae_iclass_lp24x2f_iu, - ICLASS_ae_iclass_lp24x2f_x, - ICLASS_ae_iclass_lp24x2f_xu, - ICLASS_ae_iclass_lp24x2_i, - ICLASS_ae_iclass_lp24x2_iu, - ICLASS_ae_iclass_lp24x2_x, - ICLASS_ae_iclass_lp24x2_xu, - ICLASS_ae_iclass_sp16x2f_i, - ICLASS_ae_iclass_sp16x2f_iu, - ICLASS_ae_iclass_sp16x2f_x, - ICLASS_ae_iclass_sp16x2f_xu, - ICLASS_ae_iclass_sp24x2s_i, - ICLASS_ae_iclass_sp24x2s_iu, - ICLASS_ae_iclass_sp24x2s_x, - ICLASS_ae_iclass_sp24x2s_xu, - ICLASS_ae_iclass_sp24x2f_i, - ICLASS_ae_iclass_sp24x2f_iu, - ICLASS_ae_iclass_sp24x2f_x, - ICLASS_ae_iclass_sp24x2f_xu, - ICLASS_ae_iclass_sp16f_l_i, - ICLASS_ae_iclass_sp16f_l_iu, - ICLASS_ae_iclass_sp16f_l_x, - ICLASS_ae_iclass_sp16f_l_xu, - ICLASS_ae_iclass_sp24s_l_i, - ICLASS_ae_iclass_sp24s_l_iu, - ICLASS_ae_iclass_sp24s_l_x, - ICLASS_ae_iclass_sp24s_l_xu, - ICLASS_ae_iclass_sp24f_l_i, - ICLASS_ae_iclass_sp24f_l_iu, - ICLASS_ae_iclass_sp24f_l_x, - ICLASS_ae_iclass_sp24f_l_xu, - ICLASS_ae_iclass_lq56_i, - ICLASS_ae_iclass_lq56_iu, - ICLASS_ae_iclass_lq56_x, - ICLASS_ae_iclass_lq56_xu, - ICLASS_ae_iclass_lq32f_i, - ICLASS_ae_iclass_lq32f_iu, - ICLASS_ae_iclass_lq32f_x, - ICLASS_ae_iclass_lq32f_xu, - ICLASS_ae_iclass_sq56s_i, - ICLASS_ae_iclass_sq56s_iu, - ICLASS_ae_iclass_sq56s_x, - ICLASS_ae_iclass_sq56s_xu, - ICLASS_ae_iclass_sq32f_i, - ICLASS_ae_iclass_sq32f_iu, - ICLASS_ae_iclass_sq32f_x, - ICLASS_ae_iclass_sq32f_xu, - ICLASS_ae_iclass_zerop48, - ICLASS_ae_iclass_movp48, - ICLASS_ae_iclass_selp24_ll, - ICLASS_ae_iclass_selp24_lh, - ICLASS_ae_iclass_selp24_hl, - ICLASS_ae_iclass_selp24_hh, - ICLASS_ae_iclass_movtp24x2, - ICLASS_ae_iclass_movfp24x2, - ICLASS_ae_iclass_movtp48, - ICLASS_ae_iclass_movfp48, - ICLASS_ae_iclass_movpa24x2, - ICLASS_ae_iclass_truncp24a32x2, - ICLASS_ae_iclass_cvta32p24_l, - ICLASS_ae_iclass_cvta32p24_h, - ICLASS_ae_iclass_cvtp24a16x2_ll, - ICLASS_ae_iclass_cvtp24a16x2_lh, - ICLASS_ae_iclass_cvtp24a16x2_hl, - ICLASS_ae_iclass_cvtp24a16x2_hh, - ICLASS_ae_iclass_truncp24q48x2, - ICLASS_ae_iclass_truncp16, - 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ICLASS_ae_iclass_mulaafp24s_hl_lh, - ICLASS_ae_iclass_mulaap24s_hl_lh, - ICLASS_ae_iclass_mulasfp24s_hh_ll, - ICLASS_ae_iclass_mulasp24s_hh_ll, - ICLASS_ae_iclass_mulasfp24s_hl_lh, - ICLASS_ae_iclass_mulasp24s_hl_lh, - ICLASS_ae_iclass_mulsafp24s_hh_ll, - ICLASS_ae_iclass_mulsap24s_hh_ll, - ICLASS_ae_iclass_mulsafp24s_hl_lh, - ICLASS_ae_iclass_mulsap24s_hl_lh, - ICLASS_ae_iclass_mulssfp24s_hh_ll, - ICLASS_ae_iclass_mulssp24s_hh_ll, - ICLASS_ae_iclass_mulssfp24s_hl_lh, - ICLASS_ae_iclass_mulssp24s_hl_lh, - ICLASS_ae_iclass_sha32, - ICLASS_ae_iclass_vldl32t, - ICLASS_ae_iclass_vldl16t, - ICLASS_ae_iclass_vldl16c, - ICLASS_ae_iclass_vldsht, - ICLASS_ae_iclass_lb, - ICLASS_ae_iclass_lbi, - ICLASS_ae_iclass_lbk, - ICLASS_ae_iclass_lbki, - ICLASS_ae_iclass_db, - ICLASS_ae_iclass_dbi, - ICLASS_ae_iclass_vlel32t, - ICLASS_ae_iclass_vlel16t, - ICLASS_ae_iclass_sb, - ICLASS_ae_iclass_sbi, - ICLASS_ae_iclass_vles16c, - ICLASS_ae_iclass_sbf, - ICLASS_icls_AE_SLAASQ56S, - ICLASS_icls_AE_ADDBRBA32, - ICLASS_icls_AE_MINABSSP24S, - ICLASS_icls_AE_MAXABSSP24S, - ICLASS_icls_AE_MINABSSQ56S, - ICLASS_icls_AE_MAXABSSQ56S, - ICLASS_rur_ae_cbegin0, - ICLASS_wur_ae_cbegin0, - ICLASS_rur_ae_cend0, - ICLASS_wur_ae_cend0, - ICLASS_icls_AE_LP24X2_C, - ICLASS_icls_AE_SP24X2S_C, - ICLASS_icls_AE_LP24X2F_C, - ICLASS_icls_AE_SP24X2F_C, - ICLASS_icls_AE_LP16X2F_C, - ICLASS_icls_AE_SP16X2F_C, - ICLASS_icls_AE_LP24_C, - ICLASS_icls_AE_SP24S_L_C, - ICLASS_icls_AE_LP24F_C, - ICLASS_icls_AE_SP24F_L_C, - ICLASS_icls_AE_LP16F_C, - ICLASS_icls_AE_SP16F_L_C, - ICLASS_icls_AE_LQ56_C, - ICLASS_icls_AE_SQ56S_C, - ICLASS_icls_AE_LQ32F_C, - ICLASS_icls_AE_SQ32F_C, - ICLASS_iclass_READ_IPQ, - ICLASS_iclass_CHECK_IPQ, - ICLASS_iclass_WRITE_OPQ, - ICLASS_iclass_CHECK_OPQ, - ICLASS_rur_expstate, - ICLASS_wur_expstate, - ICLASS_iclass_READ_IMPWIRE, - ICLASS_iclass_SETB_EXPSTATE, - ICLASS_iclass_CLRB_EXPSTATE, - ICLASS_iclass_WRMSK_EXPSTATE -}; - - -/* Opcode encodings. */ - -static void -Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2080; -} - -static void -Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000; -} - -static void -Opcode_rfme_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3020; -} - -static void -Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3200; -} - -static void -Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5000; -} - -static void -Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35; -} - -static void -Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x25; -} - -static void -Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15; -} - -static void -Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf0; -} - -static void -Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0; -} - -static void -Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd0; -} - -static void -Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36; -} - -static void -Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1000; -} - -static void -Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x408000; -} - -static void -Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90; -} - -static void -Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf01d; -} - -static void -Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3400; -} - -static void -Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3500; -} - -static void -Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90000; -} - -static void -Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x490000; -} - -static void -Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34800; -} - -static void -Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134800; -} - -static void -Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614800; -} - -static void -Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34900; -} - -static void -Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134900; -} - -static void -Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614900; -} - -static void -Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa; -} - -static void -Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb; -} - -static void -Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8c; -} - -static void -Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcc; -} - -static void -Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf06d; -} - -static void -Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8; -} - -static void -Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd; -} - -static void -Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc; -} - -static void -Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf03d; -} - -static void -Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00d; -} - -static void -Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9; -} - -static void -Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc002; -} - -static void -Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200040; -} - -static void -Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd002; -} - -static void -Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200080; -} - -static void -Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800000; -} - -static void -Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b2000; -} - -static void -Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc00000; -} - -static void -Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ca000; -} - -static void -Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900000; -} - -static void -Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b4000; -} - -static void -Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00000; -} - -static void -Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b8000; -} - -static void -Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb00000; -} - -static void -Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b3000; -} - -static void -Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd00000; -} - -static void -Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cc000; -} - -static void -Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00000; -} - -static void -Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cb000; -} - -static void -Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00000; -} - -static void -Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cd000; -} - -static void -Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b5000; -} - -static void -Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e0000; -} - -static void -Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300000; -} - -static void -Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ce000; -} - -static void -Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x26; -} - -static void -Opcode_beqi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300000; -} - -static void -Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x66; -} - -static void -Opcode_bnei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300003; -} - -static void -Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe6; -} - -static void -Opcode_bgei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300001; -} - -static void -Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa6; -} - -static void -Opcode_blti_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300004; -} - -static void -Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6007; -} - -static void -Opcode_bbci_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe007; -} - -static void -Opcode_bbsi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200020; -} - -static void -Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf6; -} - -static void -Opcode_bgeui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300002; -} - -static void -Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb6; -} - -static void -Opcode_bltui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300008; -} - -static void -Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1007; -} - -static void -Opcode_beq_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000a0; -} - -static void -Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9007; -} - -static void -Opcode_bne_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400000; -} - -static void -Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa007; -} - -static void -Opcode_bge_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000c0; -} - -static void -Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2007; -} - -static void -Opcode_blt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000d0; -} - -static void -Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb007; -} - -static void -Opcode_bgeu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000b0; -} - -static void -Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3007; -} - -static void -Opcode_bltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000e0; -} - -static void -Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8007; -} - -static void -Opcode_bany_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200060; -} - -static void -Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7; -} - -static void -Opcode_bnone_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400010; -} - -static void -Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4007; -} - -static void -Opcode_ball_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200050; -} - -static void -Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc007; -} - -static void -Opcode_bnall_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000f0; -} - -static void -Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5007; -} - -static void -Opcode_bbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200070; -} - -static void -Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd007; -} - -static void -Opcode_bbs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200090; -} - -static void -Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16; -} - -static void -Opcode_beqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180000; -} - -static void -Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x56; -} - -static void -Opcode_bnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x190000; -} - -static void -Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd6; -} - -static void -Opcode_bgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x160000; -} - -static void -Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x96; -} - -static void -Opcode_bltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x170000; -} - -static void -Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5; -} - -static void -Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc0; -} - -static void -Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000; -} - -static void -Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x140000; -} - -static void -Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0; -} - -static void -Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6; -} - -static void -Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0; -} - -static void -Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee031; -} - -static void -Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1002; -} - -static void -Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400040; -} - -static void -Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9002; -} - -static void -Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400020; -} - -static void -Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2002; -} - -static void -Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400080; -} - -static void -Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1; -} - -static void -Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500000; -} - -static void -Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2; -} - -static void -Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400030; -} - -static void -Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8076; -} - -static void -Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9076; -} - -static void -Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa076; -} - -static void -Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa002; -} - -static void -Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a0000; -} - -static void -Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x830000; -} - -static void -Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1be000; -} - -static void -Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x930000; -} - -static void -Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c8000; -} - -static void -Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa30000; -} - -static void -Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c4000; -} - -static void -Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb30000; -} - -static void -Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c2000; -} - -static void -Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600000; -} - -static void -Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1d00; -} - -static void -Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600100; -} - -static void -Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1c00; -} - -static void -Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20f0; -} - -static void -Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16105; -} - -static void -Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee0b1; -} - -static void -Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80; -} - -static void -Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5100; -} - -static void -Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5002; -} - -static void -Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400050; -} - -static void -Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6002; -} - -static void -Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400060; -} - -static void -Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x590000; -} - -static void -Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4002; -} - -static void -Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400070; -} - -static void -Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400000; -} - -static void -Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee071; -} - -static void -Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x401000; -} - -static void -Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee038; -} - -static void -Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x402000; -} - -static void -Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee034; -} - -static void -Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x403000; -} - -static void -Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee032; -} - -static void -Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x404000; -} - -static void -Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef0a0; -} - -static void -Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa10000; -} - -static void -Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5003; -} - -static void -Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x810000; -} - -static void -Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c7000; -} - -static void -Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x910000; -} - -static void -Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1f00; -} - -static void -Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb10000; -} - -static void -Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1e00; -} - -static void -Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10000; -} - -static void -Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c0000; -} - -static void -Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x210000; -} - -static void -Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b0000; -} - -static void -Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x410000; -} - -static void -Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c9000; -} - -static void -Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20c0; -} - -static void -Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20d0; -} - -static void -Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000; -} - -static void -Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2010; -} - -static void -Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2020; -} - -static void -Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2030; -} - -static void -Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000; -} - -static void -Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30100; -} - -static void -Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130100; -} - -static void -Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610100; -} - -static void -Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30200; -} - -static void -Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130200; -} - -static void -Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610200; -} - -static void -Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000; -} - -static void -Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130000; -} - -static void -Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610000; -} - -static void -Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30300; -} - -static void -Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130300; -} - -static void -Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610300; -} - -static void -Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31000; -} - -static void -Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131000; -} - -static void -Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x611000; -} - -static void -Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31100; -} - -static void -Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131100; -} - -static void -Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x611100; -} - -static void -Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36100; -} - -static void -Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136100; -} - -static void -Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616100; -} - -static void -Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30500; -} - -static void -Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130500; -} - -static void -Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610500; -} - -static void -Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b000; -} - -static void -Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b000; -} - -static void -Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d000; -} - -static void -Opcode_rsr_243_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f300; -} - -static void -Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e600; -} - -static void -Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e600; -} - -static void -Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e600; -} - -static void -Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b100; -} - -static void -Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b100; -} - -static void -Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b100; -} - -static void -Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d100; -} - -static void -Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d100; -} - -static void -Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d100; -} - -static void -Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b200; -} - -static void -Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b200; -} - -static void -Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b200; -} - -static void -Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d200; -} - -static void -Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d200; -} - -static void -Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d200; -} - -static void -Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b300; -} - -static void -Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b300; -} - -static void -Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b300; -} - -static void -Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d300; -} - -static void -Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d300; -} - -static void -Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d300; -} - -static void -Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b400; -} - -static void -Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b400; -} - -static void -Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b400; -} - -static void -Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d400; -} - -static void -Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d400; -} - -static void -Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d400; -} - -static void -Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b500; -} - -static void -Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b500; -} - -static void -Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b500; -} - -static void -Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d500; -} - -static void -Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d500; -} - -static void -Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d500; -} - -static void -Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b600; -} - -static void -Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b600; -} - -static void -Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b600; -} - -static void -Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d600; -} - -static void -Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d600; -} - -static void -Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d600; -} - -static void -Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b700; -} - -static void -Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b700; -} - -static void -Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b700; -} - -static void -Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d700; -} - -static void -Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d700; -} - -static void -Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d700; -} - -static void -Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c200; -} - -static void -Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c200; -} - -static void -Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c200; -} - -static void -Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c300; -} - -static void -Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c300; -} - -static void -Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c300; -} - -static void -Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c400; -} - -static void -Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c400; -} - -static void -Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c400; -} - -static void -Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c500; -} - -static void -Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c500; -} - -static void -Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c500; -} - -static void -Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c600; -} - -static void -Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c600; -} - -static void -Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c600; -} - -static void -Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c700; -} - -static void -Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c700; -} - -static void -Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c700; -} - -static void -Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ee00; -} - -static void -Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ee00; -} - -static void -Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ee00; -} - -static void -Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c000; -} - -static void -Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c000; -} - -static void -Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c000; -} - -static void -Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e800; -} - -static void -Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e800; -} - -static void -Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e800; -} - -static void -Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f400; -} - -static void -Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f400; -} - -static void -Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f400; -} - -static void -Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f500; -} - -static void -Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f500; -} - -static void -Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f500; -} - -static void -Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3eb00; -} - -static void -Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e700; -} - -static void -Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e700; -} - -static void -Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e700; -} - -static void -Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc10000; -} - -static void -Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd10000; -} - -static void -Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x820000; -} - -static void -Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3010; -} - -static void -Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7000; -} - -static void -Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e200; -} - -static void -Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e200; -} - -static void -Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e300; -} - -static void -Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e400; -} - -static void -Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e400; -} - -static void -Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e400; -} - -static void -Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000; -} - -static void -Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf02d; -} - -static void -Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39000; -} - -static void -Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139000; -} - -static void -Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619000; -} - -static void -Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a000; -} - -static void -Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a000; -} - -static void -Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a000; -} - -static void -Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39100; -} - -static void -Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139100; -} - -static void -Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619100; -} - -static void -Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a100; -} - -static void -Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a100; -} - -static void -Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a100; -} - -static void -Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38000; -} - -static void -Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138000; -} - -static void -Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618000; -} - -static void -Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38100; -} - -static void -Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138100; -} - -static void -Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618100; -} - -static void -Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36000; -} - -static void -Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136000; -} - -static void -Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616000; -} - -static void -Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e900; -} - -static void -Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e900; -} - -static void -Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e900; -} - -static void -Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ec00; -} - -static void -Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ec00; -} - -static void -Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ec00; -} - -static void -Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ed00; -} - -static void -Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ed00; -} - -static void -Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ed00; -} - -static void -Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36800; -} - -static void -Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136800; -} - -static void -Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616800; -} - -static void -Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70e0; -} - -static void -Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70f0; -} - -static void -Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e000; -} - -static void -Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e010; -} - -static void -Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135900; -} - -static void -Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20000; -} - -static void -Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b6000; -} - -static void -Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x120000; -} - -static void -Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b7000; -} - -static void -Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x220000; -} - -static void -Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c3000; -} - -static void -Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x320000; -} - -static void -Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c5000; -} - -static void -Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x420000; -} - -static void -Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cf000; -} - -static void -Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8000; -} - -static void -Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2480; -} - -static void -Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9000; -} - -static void -Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2800; -} - -static void -Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa000; -} - -static void -Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef060; -} - -static void -Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb000; -} - -static void -Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef020; -} - -static void -Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x76; -} - -static void -Opcode_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300005; -} - -static void -Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1076; -} - -static void -Opcode_bt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300006; -} - -static void -Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc30000; -} - -static void -Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bf000; -} - -static void -Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd30000; -} - -static void -Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d0000; -} - -static void -Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30400; -} - -static void -Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130400; -} - -static void -Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610400; -} - -static void -Opcode_rsr_mevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36f00; -} - -static void -Opcode_wsr_mevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136f00; -} - -static void -Opcode_xsr_mevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616f00; -} - -static void -Opcode_rsr_mecr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36e00; -} - -static void -Opcode_wsr_mecr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136e00; -} - -static void -Opcode_xsr_mecr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616e00; -} - -static void -Opcode_rsr_mesr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36d00; -} - -static void -Opcode_wsr_mesr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136d00; -} - -static void -Opcode_xsr_mesr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616d00; -} - -static void -Opcode_rsr_mesave_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36c00; -} - -static void -Opcode_wsr_mesave_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136c00; -} - -static void -Opcode_xsr_mesave_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616c00; -} - -static void -Opcode_rsr_meps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36b00; -} - -static void -Opcode_wsr_meps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136b00; -} - -static void -Opcode_xsr_meps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616b00; -} - -static void -Opcode_rsr_mepc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36a00; -} - -static void -Opcode_wsr_mepc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136a00; -} - -static void -Opcode_xsr_mepc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616a00; -} - -static void -Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ea00; -} - -static void -Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ea00; -} - -static void -Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ea00; -} - -static void -Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f000; -} - -static void -Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f000; -} - -static void -Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f000; -} - -static void -Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f100; -} - -static void -Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f100; -} - -static void -Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f100; -} - -static void -Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f200; -} - -static void -Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f200; -} - -static void -Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f200; -} - -static void -Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70c2; -} - -static void -Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70e2; -} - -static void -Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70d2; -} - -static void -Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x270d2; -} - -static void -Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x370d2; -} - -static void -Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70f2; -} - -static void -Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf10000; -} - -static void -Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf12000; -} - -static void -Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf11000; -} - -static void -Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf13000; -} - -static void -Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7042; -} - -static void -Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7052; -} - -static void -Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf7082; -} - -static void -Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x47082; -} - -static void -Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x57082; -} - -static void -Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7062; -} - -static void -Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7072; -} - -static void -Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7002; -} - -static void -Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7012; -} - -static void -Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7022; -} - -static void -Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7032; -} - -static void -Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7082; -} - -static void -Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x27082; -} - -static void -Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x37082; -} - -static void -Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf19000; -} - -static void -Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf18000; -} - -static void -Opcode_rsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32800; -} - -static void -Opcode_wsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132800; -} - -static void -Opcode_xsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612800; -} - -static void -Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50c000; -} - -static void -Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50d000; -} - -static void -Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50b000; -} - -static void -Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50f000; -} - -static void -Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50e000; -} - -static void -Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x504000; -} - -static void -Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x505000; -} - -static void -Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x503000; -} - -static void -Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x507000; -} - -static void -Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x506000; -} - -static void -Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e000; -} - -static void -Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e000; -} - -static void -Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e000; -} - -static void -Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x330000; -} - -static void -Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b9000; -} - -static void -Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x430000; -} - -static void -Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bb000; -} - -static void -Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x530000; -} - -static void -Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ba000; -} - -static void -Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x630000; -} - -static void -Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bd000; -} - -static void -Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x730000; -} - -static void -Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bc000; -} - -static void -Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40e000; -} - -static void -Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40f000; -} - -static void -Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x230000; -} - -static void -Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c6000; -} - -static void -Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb002; -} - -static void -Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf002; -} - -static void -Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe002; -} - -static void -Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30c00; -} - -static void -Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130c00; -} - -static void -Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610c00; -} - -static void -Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36300; -} - -static void -Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136300; -} - -static void -Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616300; -} - -static void -Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc20000; -} - -static void -Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd20000; -} - -static void -Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe20000; -} - -static void -Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf20000; -} - -static void -Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x406000; -} - -static void -Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x407000; -} - -static void -Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f00; -} - -static void -Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f000; -} - -static void -Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f10; -} - -static void -Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f100; -} - -static void -Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f20; -} - -static void -Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f200; -} - -static void -Opcode_rur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f30; -} - -static void -Opcode_wur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f300; -} - -static void -Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90804; -} - -static void -Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca0004; -} - -static void -Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90904; -} - -static void -Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca1004; -} - -static void -Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90a04; -} - -static void -Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca2004; -} - -static void -Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90b04; -} - -static void -Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca3004; -} - -static void -Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90c04; -} - -static void -Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca4004; -} - -static void -Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90d04; -} - -static void -Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca5004; -} - -static void -Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90e04; -} - -static void -Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca6004; -} - -static void -Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90f04; -} - -static void -Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca7004; -} - -static void -Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30e70; -} - -static void -Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3e700; -} - -static void -Opcode_ae_lp16f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d1080; -} - -static void -Opcode_ae_lp16f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa50004; -} - -static void -Opcode_ae_lp16f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d2080; -} - -static void -Opcode_ae_lp16f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa90004; -} - -static void -Opcode_ae_lp16f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d3000; -} - -static void -Opcode_ae_lp16f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xac0004; -} - -static void -Opcode_ae_lp16f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d3080; -} - -static void -Opcode_ae_lp16f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaf0004; -} - -static void -Opcode_ae_lp24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d6080; -} - -static void -Opcode_ae_lp24_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa58004; -} - -static void -Opcode_ae_lp24_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d7000; -} - -static void -Opcode_ae_lp24_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa98004; -} - -static void -Opcode_ae_lp24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d7080; -} - -static void -Opcode_ae_lp24_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xac8004; -} - -static void -Opcode_ae_lp24_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d8080; -} - -static void -Opcode_ae_lp24_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaf8004; -} - -static void -Opcode_ae_lp24f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d9000; -} - -static void -Opcode_ae_lp24f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa60004; -} - -static void -Opcode_ae_lp24f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1da000; -} - -static void -Opcode_ae_lp24f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaa0004; -} - -static void -Opcode_ae_lp24f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dc000; -} - -static void -Opcode_ae_lp24f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xad0004; -} - -static void -Opcode_ae_lp24f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d9080; -} - -static void -Opcode_ae_lp24f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb00004; -} - -static void -Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d4080; -} - -static void -Opcode_ae_lp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa68004; -} - -static void -Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d5000; -} - -static void -Opcode_ae_lp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaa8004; -} - -static void -Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d6000; -} - -static void -Opcode_ae_lp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xad8004; -} - -static void -Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d5080; -} - -static void -Opcode_ae_lp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb08004; -} - -static void -Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dd000; -} - -static void -Opcode_ae_lp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa70004; -} - -static void -Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1de000; -} - -static void -Opcode_ae_lp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xab0004; -} - -static void -Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dd080; -} - -static void -Opcode_ae_lp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xae0004; -} - -static void -Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1de080; -} - -static void -Opcode_ae_lp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb10004; -} - -static void -Opcode_ae_lp24x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1da080; -} - -static void -Opcode_ae_lp24x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa78004; -} - -static void -Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1db000; -} - -static void -Opcode_ae_lp24x2_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xab8004; -} - -static void -Opcode_ae_lp24x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1db080; -} - -static void -Opcode_ae_lp24x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xae8004; -} - -static void -Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dc080; -} - -static void -Opcode_ae_lp24x2_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb18004; -} - -static void -Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e8000; -} - -static void -Opcode_ae_sp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb20004; -} - -static void -Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f0000; -} - -static void -Opcode_ae_sp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb50004; -} - -static void -Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e1080; -} - -static void -Opcode_ae_sp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb80004; -} - -static void -Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e2080; -} - -static void -Opcode_ae_sp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbb0004; -} - -static void -Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ec000; -} - -static void -Opcode_ae_sp24x2s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb28004; -} - -static void -Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e9080; -} - -static void -Opcode_ae_sp24x2s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb58004; -} - -static void -Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ea080; -} - -static void -Opcode_ae_sp24x2s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb88004; -} - -static void -Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1eb000; -} - -static void -Opcode_ae_sp24x2s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbb8004; -} - -static void -Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e7080; -} - -static void -Opcode_ae_sp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb30004; -} - -static void -Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e8080; -} - -static void -Opcode_ae_sp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb60004; -} - -static void -Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e9000; -} - -static void -Opcode_ae_sp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb90004; -} - -static void -Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ea000; -} - -static void -Opcode_ae_sp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbc0004; -} - -static void -Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1df080; -} - -static void -Opcode_ae_sp16f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb38004; -} - -static void -Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e1000; -} - -static void -Opcode_ae_sp16f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb68004; -} - -static void -Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e2000; -} - -static void -Opcode_ae_sp16f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb98004; -} - -static void -Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e4000; -} - -static void -Opcode_ae_sp16f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbc8004; -} - -static void -Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e6000; -} - -static void -Opcode_ae_sp24s_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb40004; -} - -static void -Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e5080; -} - -static void -Opcode_ae_sp24s_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb70004; -} - -static void -Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e6080; -} - -static void -Opcode_ae_sp24s_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xba0004; -} - -static void -Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e7000; -} - -static void -Opcode_ae_sp24s_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbd0004; -} - -static void -Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e3000; -} - -static void -Opcode_ae_sp24f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb48004; -} - -static void -Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e3080; -} - -static void -Opcode_ae_sp24f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb78004; -} - -static void -Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e4080; -} - -static void -Opcode_ae_sp24f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xba8004; -} - -static void -Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e5000; -} - -static void -Opcode_ae_sp24f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbd8004; -} - -static void -Opcode_ae_lq56_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed030; -} - -static void -Opcode_ae_lq56_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc10004; -} - -static void -Opcode_ae_lq56_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee010; -} - -static void -Opcode_ae_lq56_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc12004; -} - -static void -Opcode_ae_lq56_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee020; -} - -static void -Opcode_ae_lq56_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc20004; -} - -static void -Opcode_ae_lq56_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef000; -} - -static void -Opcode_ae_lq56_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc22004; -} - -static void -Opcode_ae_lq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed000; -} - -static void -Opcode_ae_lq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc11004; -} - -static void -Opcode_ae_lq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee000; -} - -static void -Opcode_ae_lq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc13004; -} - -static void -Opcode_ae_lq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed010; -} - -static void -Opcode_ae_lq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc21004; -} - -static void -Opcode_ae_lq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed020; -} - -static void -Opcode_ae_lq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc23004; -} - -static void -Opcode_ae_sq56s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f0080; -} - -static void -Opcode_ae_sq56s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc30004; -} - -static void -Opcode_ae_sq56s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f00c0; -} - -static void -Opcode_ae_sq56s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc38004; -} - -static void -Opcode_ae_sq56s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3000; -} - -static void -Opcode_ae_sq56s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc40004; -} - -static void -Opcode_ae_sq56s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3040; -} - -static void -Opcode_ae_sq56s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc48004; -} - -static void -Opcode_ae_sq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ec080; -} - -static void -Opcode_ae_sq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc34004; -} - -static void -Opcode_ae_sq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ec0c0; -} - -static void -Opcode_ae_sq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc3c004; -} - -static void -Opcode_ae_sq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f4000; -} - -static void -Opcode_ae_sq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc44004; -} - -static void -Opcode_ae_sq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f8000; -} - -static void -Opcode_ae_sq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc4c004; -} - -static void -Opcode_ae_zerop48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16b88; -} - -static void -Opcode_ae_movp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16808; -} - -static void -Opcode_ae_movp48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2400; -} - -static void -Opcode_ae_movp48_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90004; -} - -static void -Opcode_ae_selp24_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10780; -} - -static void -Opcode_ae_selp24_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2e00; -} - -static void -Opcode_ae_selp24_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10708; -} - -static void -Opcode_ae_selp24_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fa600; -} - -static void -Opcode_ae_selp24_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10688; -} - -static void -Opcode_ae_selp24_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fa200; -} - -static void -Opcode_ae_selp24_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10700; -} - -static void -Opcode_ae_selp24_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fa000; -} - -static void -Opcode_ae_movtp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c200; -} - -static void -Opcode_ae_movfp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c004; -} - -static void -Opcode_ae_movtp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10480; -} - -static void -Opcode_ae_movfp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10400; -} - -static void -Opcode_ae_movpa24x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1df000; -} - -static void -Opcode_ae_movpa24x2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc00004; -} - -static void -Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1eb080; -} - -static void -Opcode_ae_truncp24a32x2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc08004; -} - -static void -Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3081; -} - -static void -Opcode_ae_cvta32p24_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcb0004; -} - -static void -Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3080; -} - -static void -Opcode_ae_cvta32p24_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcb8004; -} - -static void -Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d8000; -} - -static void -Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbe0004; -} - -static void -Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d4000; -} - -static void -Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbe8004; -} - -static void -Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d2000; -} - -static void -Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbf0004; -} - -static void -Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d1000; -} - -static void -Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbf8004; -} - -static void -Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x51000; -} - -static void -Opcode_ae_truncp16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16b08; -} - -static void -Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e48; -} - -static void -Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e28; -} - -static void -Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e18; -} - -static void -Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e08; -} - -static void -Opcode_ae_roundsp16sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16908; -} - -static void -Opcode_ae_roundsp16asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16888; -} - -static void -Opcode_ae_zeroq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16085; -} - -static void -Opcode_ae_movq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16007; -} - -static void -Opcode_ae_movq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2500; -} - -static void -Opcode_ae_movq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90414; -} - -static void -Opcode_ae_movtq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f6000; -} - -static void -Opcode_ae_movtq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe50014; -} - -static void -Opcode_ae_movfq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5000; -} - -static void -Opcode_ae_movfq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe60014; -} - -static void -Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee030; -} - -static void -Opcode_ae_cvtq48a32s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe72034; -} - -static void -Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16006; -} - -static void -Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16005; -} - -static void -Opcode_ae_satq48s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50139; -} - -static void -Opcode_ae_truncq32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16047; -} - -static void -Opcode_ae_roundsq32sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16027; -} - -static void -Opcode_ae_roundsq32asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16017; -} - -static void -Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3086; -} - -static void -Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe70014; -} - -static void -Opcode_ae_movap24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3084; -} - -static void -Opcode_ae_movap24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc70004; -} - -static void -Opcode_ae_movap24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3082; -} - -static void -Opcode_ae_movap24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc78004; -} - -static void -Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3083; -} - -static void -Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc80004; -} - -static void -Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3088; -} - -static void -Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc88004; -} - -static void -Opcode_ae_addp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10500; -} - -static void -Opcode_ae_subp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10788; -} - -static void -Opcode_ae_negp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c600; -} - -static void -Opcode_ae_absp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c480; -} - -static void -Opcode_ae_maxp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10580; -} - -static void -Opcode_ae_minp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10588; -} - -static void -Opcode_ae_maxbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10000; -} - -static void -Opcode_ae_minbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10200; -} - -static void -Opcode_ae_addsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10600; -} - -static void -Opcode_ae_subsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c400; -} - -static void -Opcode_ae_negsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c488; -} - -static void -Opcode_ae_abssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c500; -} - -static void -Opcode_ae_andp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10508; -} - -static void -Opcode_ae_nandp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10608; -} - -static void -Opcode_ae_orp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10680; -} - -static void -Opcode_ae_xorp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c408; -} - -static void -Opcode_ae_ltp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c002; -} - -static void -Opcode_ae_lep24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c001; -} - -static void -Opcode_ae_eqp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c000; -} - -static void -Opcode_ae_addq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x52000; -} - -static void -Opcode_ae_subq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50035; -} - -static void -Opcode_ae_negq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5003c; -} - -static void -Opcode_ae_absq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50039; -} - -static void -Opcode_ae_maxq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50032; -} - -static void -Opcode_ae_minq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50034; -} - -static void -Opcode_ae_maxbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50000; -} - -static void -Opcode_ae_minbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50010; -} - -static void -Opcode_ae_addsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50030; -} - -static void -Opcode_ae_subsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50036; -} - -static void -Opcode_ae_negsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500b9; -} - -static void -Opcode_ae_abssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5003a; -} - -static void -Opcode_ae_andq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50031; -} - -static void -Opcode_ae_nandq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50038; -} - -static void -Opcode_ae_orq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50033; -} - -static void -Opcode_ae_xorq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50037; -} - -static void -Opcode_ae_sllip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x14000; -} - -static void -Opcode_ae_srlip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15000; -} - -static void -Opcode_ae_sraip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x14800; -} - -static void -Opcode_ae_sllsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16a08; -} - -static void -Opcode_ae_srlsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16a88; -} - -static void -Opcode_ae_srasp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16988; -} - -static void -Opcode_ae_sllisp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x18000; -} - -static void -Opcode_ae_sllssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16c08; -} - -static void -Opcode_ae_slliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1000; -} - -static void -Opcode_ae_slliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50004; -} - -static void -Opcode_ae_srliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1800; -} - -static void -Opcode_ae_srliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50404; -} - -static void -Opcode_ae_sraiq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1400; -} - -static void -Opcode_ae_sraiq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50804; -} - -static void -Opcode_ae_sllsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2600; -} - -static void -Opcode_ae_sllsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90014; -} - -static void -Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2504; -} - -static void -Opcode_ae_srlsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90114; -} - -static void -Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2502; -} - -static void -Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90214; -} - -static void -Opcode_ae_sllaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5001; -} - -static void -Opcode_ae_sllaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe10014; -} - -static void -Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5008; -} - -static void -Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe20014; -} - -static void -Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5004; -} - -static void -Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30014; -} - -static void -Opcode_ae_sllisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2000; -} - -static void -Opcode_ae_sllisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50c04; -} - -static void -Opcode_ae_sllssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2501; -} - -static void -Opcode_ae_sllssq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90314; -} - -static void -Opcode_ae_sllasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5002; -} - -static void -Opcode_ae_sllasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe40014; -} - -static void -Opcode_ae_ltq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50800; -} - -static void -Opcode_ae_leq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50040; -} - -static void -Opcode_ae_eqq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50020; -} - -static void -Opcode_ae_nsaq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3085; -} - -static void -Opcode_ae_nsaq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe74014; -} - -static void -Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19004; -} - -static void -Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19005; -} - -static void -Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19002; -} - -static void -Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19003; -} - -static void -Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19000; -} - -static void -Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19001; -} - -static void -Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1900a; -} - -static void -Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1900b; -} - -static void -Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19008; -} - -static void -Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19009; -} - -static void -Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19006; -} - -static void -Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19007; -} - -static void -Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60101; -} - -static void -Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008b; -} - -static void -Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60180; -} - -static void -Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008f; -} - -static void -Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008c; -} - -static void -Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60108; -} - -static void -Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008e; -} - -static void -Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008a; -} - -static void -Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60104; -} - -static void -Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008d; -} - -static void -Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60089; -} - -static void -Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60102; -} - -static void -Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60006; -} - -static void -Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64000; -} - -static void -Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000f; -} - -static void -Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60005; -} - -static void -Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60100; -} - -static void -Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000e; -} - -static void -Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60003; -} - -static void -Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60080; -} - -static void -Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000d; -} - -static void -Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x68000; -} - -static void -Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60008; -} - -static void -Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000b; -} - -static void -Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60181; -} - -static void -Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010b; -} - -static void -Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60189; -} - -static void -Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010f; -} - -static void -Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010c; -} - -static void -Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60187; -} - -static void -Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010e; -} - -static void -Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010a; -} - -static void -Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60186; -} - -static void -Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010d; -} - -static void -Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60109; -} - -static void -Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60185; -} - -static void -Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000c; -} - -static void -Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60088; -} - -static void -Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000a; -} - -static void -Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60084; -} - -static void -Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60009; -} - -static void -Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60082; -} - -static void -Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60007; -} - -static void -Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60081; -} - -static void -Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60183; -} - -static void -Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018d; -} - -static void -Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60188; -} - -static void -Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018b; -} - -static void -Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60184; -} - -static void -Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018c; -} - -static void -Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60182; -} - -static void -Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018a; -} - -static void -Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15807; -} - -static void -Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15806; -} - -static void -Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580a; -} - -static void -Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15809; -} - -static void -Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580b; -} - -static void -Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580c; -} - -static void -Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580e; -} - -static void -Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580d; -} - -static void -Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15800; -} - -static void -Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16000; -} - -static void -Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15802; -} - -static void -Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15801; -} - -static void -Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15808; -} - -static void -Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15804; -} - -static void -Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15805; -} - -static void -Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15803; -} - -static void -Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16001; -} - -static void -Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580f; -} - -static void -Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16004; -} - -static void -Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16002; -} - -static void -Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16800; -} - -static void -Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16008; -} - -static void -Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16003; -} - -static void -Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x17000; -} - -static void -Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20007; -} - -static void -Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20002; -} - -static void -Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000c; -} - -static void -Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20003; -} - -static void -Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20005; -} - -static void -Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20000; -} - -static void -Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20009; -} - -static void -Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20004; -} - -static void -Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20006; -} - -static void -Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20001; -} - -static void -Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000a; -} - -static void -Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20008; -} - -static void -Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30008; -} - -static void -Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000e; -} - -static void -Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30006; -} - -static void -Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30001; -} - -static void -Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30002; -} - -static void -Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000b; -} - -static void -Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30003; -} - -static void -Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000f; -} - -static void -Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30004; -} - -static void -Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000d; -} - -static void -Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30005; -} - -static void -Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000; -} - -static void -Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000; -} - -static void -Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000a; -} - -static void -Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40004; -} - -static void -Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000d; -} - -static void -Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000e; -} - -static void -Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30007; -} - -static void -Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40001; -} - -static void -Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000c; -} - -static void -Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000f; -} - -static void -Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30009; -} - -static void -Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40002; -} - -static void -Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000b; -} - -static void -Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000b; -} - -static void -Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40005; -} - -static void -Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000f; -} - -static void -Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40009; -} - -static void -Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000a; -} - -static void -Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40008; -} - -static void -Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000d; -} - -static void -Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40006; -} - -static void -Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000c; -} - -static void -Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40003; -} - -static void -Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000e; -} - -static void -Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40007; -} - -static void -Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64004; -} - -static void -Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64080; -} - -static void -Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64008; -} - -static void -Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64100; -} - -static void -Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64003; -} - -static void -Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64006; -} - -static void -Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64005; -} - -static void -Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64007; -} - -static void -Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64009; -} - -static void -Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400c; -} - -static void -Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400a; -} - -static void -Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400b; -} - -static void -Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400d; -} - -static void -Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400f; -} - -static void -Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400e; -} - -static void -Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64081; -} - -static void -Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60000; -} - -static void -Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60002; -} - -static void -Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60001; -} - -static void -Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60004; -} - -static void -Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60083; -} - -static void -Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60086; -} - -static void -Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60085; -} - -static void -Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60087; -} - -static void -Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60103; -} - -static void -Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60106; -} - -static void -Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60105; -} - -static void -Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60107; -} - -static void -Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018e; -} - -static void -Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64001; -} - -static void -Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018f; -} - -static void -Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64002; -} - -static void -Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00014; -} - -static void -Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00004; -} - -static void -Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa10004; -} - -static void -Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe7e014; -} - -static void -Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca8004; -} - -static void -Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc60004; -} - -static void -Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00024; -} - -static void -Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa20004; -} - -static void -Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00004; -} - -static void -Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf01004; -} - -static void -Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf02004; -} - -static void -Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa30004; -} - -static void -Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa40004; -} - -static void -Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf11004; -} - -static void -Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00004; -} - -static void -Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe7c014; -} - -static void -Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe7d014; -} - -static void -Opcode_ae_slaasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f6008; -} - -static void -Opcode_ae_addbrba32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f7000; -} - -static void -Opcode_ae_minabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c508; -} - -static void -Opcode_ae_maxabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c580; -} - -static void -Opcode_ae_minabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x52004; -} - -static void -Opcode_ae_maxabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x52008; -} - -static void -Opcode_rur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f60; -} - -static void -Opcode_wur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f600; -} - -static void -Opcode_rur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f70; -} - -static void -Opcode_wur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f700; -} - -static void -Opcode_ae_lp24x2_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fe080; -} - -static void -Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900000; -} - -static void -Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ff000; -} - -static void -Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800000; -} - -static void -Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f4080; -} - -static void -Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0; -} - -static void -Opcode_ae_lp24_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fc080; -} - -static void -Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700000; -} - -static void -Opcode_ae_lp24f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fe000; -} - -static void -Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600000; -} - -static void -Opcode_ae_lp16f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fc000; -} - -static void -Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ff080; -} - -static void -Opcode_ae_lq56_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00000; -} - -static void -Opcode_ae_sq56s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f8080; -} - -static void -Opcode_ae_lq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef010; -} - -static void -Opcode_ae_sq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f8040; -} - -static void -Opcode_read_ipq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe4000; -} - -static void -Opcode_read_ipq_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a020; -} - -static void -Opcode_check_ipq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe5000; -} - -static void -Opcode_check_ipq_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a000; -} - -static void -Opcode_write_opq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe6000; -} - -static void -Opcode_write_opq_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a030; -} - -static void -Opcode_check_opq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe7000; -} - -static void -Opcode_check_opq_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a010; -} - -static void -Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30e60; -} - -static void -Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3e600; -} - -static void -Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0000; -} - -static void -Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe1000; -} - -static void -Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe1200; -} - -static void -Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe2000; -} - -xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { - Opcode_excw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { - Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfme_encode_fns[] = { - Opcode_rfme_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { - Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { - Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { - Opcode_call12_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { - Opcode_call8_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { - Opcode_call4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { - Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { - Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { - Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { - Opcode_entry_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { - Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { - Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { - Opcode_retw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { - 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { - Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { - Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { - Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { - Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { - Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { - Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { - Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { - Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { - Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { - Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { - 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { - 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { - 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { - 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { - 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { - 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { - 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { - 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { - 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { - 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { - 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { - Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { - Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { - Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { - Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { - Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { - Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { - Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { - Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { - Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { - Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { - Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { - Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { - Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { - Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { - Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { - Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { - Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { - Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { - Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { - Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { - Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { - Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { - Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { - Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { - Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { - Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { - Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { - Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { - Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { - Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { - Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { - Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { - Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { - Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { - Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { - Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { - Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { - Opcode_call0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { - Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { - Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { - Opcode_ill_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { - Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { - Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { - Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { - Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { - Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { - Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { - Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { - Opcode_loop_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { - Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { - Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { - Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { - Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { - Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { - Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { - Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { - Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { - Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { - Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { - Opcode_ret_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { - Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { - Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { - Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { - Opcode_s32nb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { - Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { - Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { - Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { - Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { - Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { - Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { - Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { - Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { - Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { - Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { - Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { - Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { - Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { - Opcode_memw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { - Opcode_extw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { - Opcode_isync_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { - Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { - Opcode_esync_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { - Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { - Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { - Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { - Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { - Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { - Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { - Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { - Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { - Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { - Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { - Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { - Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { - Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { - Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { - Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { - Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { - Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { - Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { - Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { - Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_243_encode_fns[] = { - Opcode_rsr_243_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { - Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { - Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { - Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { - Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { - Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { - Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { - Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { - Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { - Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { - Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { - Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { - Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { - Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { - Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { - Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { - Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { - Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { - Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { - Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { - Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { - Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { - Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { - Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { - Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { - Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { - Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { - Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { - Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { - Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { - Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { - Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { - Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { - Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { - Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { - Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { - Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { - Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { - Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { - Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { - Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { - Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { - Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { - Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { - Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { - Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { - Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { - Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { - Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { - Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { - Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { - Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { - Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { - Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { - Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { - Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { - Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { - Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { - Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { - Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { - Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { - Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { - Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { - Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { - Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { - Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { - Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { - Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { - Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { - Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { - Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { - Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { - Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { - Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { - Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { - Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { - Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { - Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { - Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { - Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { - Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { - Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { - Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { - Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { - Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { - Opcode_mull_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { - Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { - Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { - Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { - Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { - Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { - Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { - Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { - Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { - Opcode_break_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { - 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { - Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { - Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { - Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { - Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { - Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { - Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { - Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { - Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { - Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { - Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { - Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { - Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { - Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { - Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { - Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { - Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { - Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { - Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { - Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { - Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { - Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { - Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { - Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { - Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { - Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { - Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { - Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { - Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { - Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { - Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { - Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { - Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { - Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { - Opcode_lddr32_p_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { - Opcode_sddr32_p_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { - Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { - Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { - Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { - Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { - Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { - Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { - Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { - Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { - Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { - Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { - Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { - Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { - Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { - Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { - Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { - Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { - Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { - Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { - Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { - Opcode_rsr_memctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { - Opcode_wsr_memctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { - Opcode_xsr_memctl_Slot_inst_encode, 0, 0, 0, 0 -}; - - -xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { - Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { - Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { - Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { - Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { - Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { - Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_mepc_encode_fns[] = { - Opcode_rsr_mepc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_mepc_encode_fns[] = { - Opcode_wsr_mepc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_mepc_encode_fns[] = { - Opcode_xsr_mepc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_meps_encode_fns[] = { - Opcode_rsr_meps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_meps_encode_fns[] = { - Opcode_wsr_meps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_meps_encode_fns[] = { - Opcode_xsr_meps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_mesave_encode_fns[] = { - Opcode_rsr_mesave_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_mesave_encode_fns[] = { - Opcode_wsr_mesave_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_mesave_encode_fns[] = { - Opcode_xsr_mesave_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_mesr_encode_fns[] = { - Opcode_rsr_mesr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_mesr_encode_fns[] = { - Opcode_wsr_mesr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_mesr_encode_fns[] = { - Opcode_xsr_mesr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_mecr_encode_fns[] = { - Opcode_rsr_mecr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_mecr_encode_fns[] = { - Opcode_wsr_mecr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_mecr_encode_fns[] = { - Opcode_xsr_mecr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_mevaddr_encode_fns[] = { - Opcode_rsr_mevaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_mevaddr_encode_fns[] = { - Opcode_wsr_mevaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_mevaddr_encode_fns[] = { - Opcode_xsr_mevaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { - Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { - Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { - Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { - Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { - Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { - Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { - Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { - Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { - Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { - Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { - Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { - Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { - Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { - Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { - Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { - Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { - Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { - Opcode_iii_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { - Opcode_lict_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { - Opcode_licw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { - Opcode_sict_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { - Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { - Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { - Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = { - Opcode_diwbui_p_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { - Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { - Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { - Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { - Opcode_dii_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { - Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { - Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { - Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { - Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { - Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { - Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { - Opcode_diu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { - Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { - Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_prefctl_encode_fns[] = { - Opcode_rsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_prefctl_encode_fns[] = { - Opcode_wsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_prefctl_encode_fns[] = { - Opcode_xsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { - Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { - Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { - Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { - Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { - Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { - Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { - Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { - Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { - Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { - Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { - Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { - Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { - Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { - Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { - Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { - Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { - Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { - Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { - Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { - Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { - Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { - Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { - Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { - Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { - Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { - Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { - Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { - Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { - Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { - Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { - Opcode_quou_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { - Opcode_quos_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { - Opcode_remu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { - Opcode_rems_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { - Opcode_rer_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { - Opcode_wer_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { - Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { - Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { - Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { - Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { - Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { - Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = { - Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = { - Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { - Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { - Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { - Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { - Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { - Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { - Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { - Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { - Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { - Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { - Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { - Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { - Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { - Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { - Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { - Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { - Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { - Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { - Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = { - Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = { - Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = { - Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = { - Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = { - Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = { - Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = { - Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = { - Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = { - Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = { - Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = { - Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = { - Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = { - Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = { - Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = { - Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = { - Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = { - Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = { - Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = { - Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = { - Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = { - Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = { - Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = { - Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = { - Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = { - Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = { - Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = { - Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = { - Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = { - Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = { - Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = { - Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = { - Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = { - Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = { - Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = { - Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = { - Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = { - Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = { - Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = { - Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = { - Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = { - Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = { - Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = { - Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = { - Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = { - Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = { - Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = { - Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = { - Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = { - Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = { - Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = { - Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = { - Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = { - Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = { - Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = { - Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = { - Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = { - Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = { - Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = { - Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = { - Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = { - Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = { - Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = { - Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = { - Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = { - 0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = { - Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, Opcode_ae_selp24_ll_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, Opcode_ae_selp24_lh_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, Opcode_ae_selp24_hl_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, Opcode_ae_selp24_hh_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = { - Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { - Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = { - Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = { - Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { - Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { - Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { - Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { - Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = { - Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = { - Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = { - Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = { - Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = { - 0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { - Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = { - Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = { - Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { - Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { - Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = { - Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = { - Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = { - Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = { - Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { - Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { - Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = { - Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { - Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { - Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = { - Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = { - Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = { - Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = { - Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { - Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { - Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { - Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { - Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { - Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { - Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { - Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { - Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { - Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { - Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { - Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { - Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { - Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { - Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { - Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { - Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { - Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_slaasq56s_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_addbrba32_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_minabssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minabssp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxabssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxabssp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minabssq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minabssq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxabssq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxabssq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_cbegin0_encode_fns[] = { - Opcode_rur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_cbegin0_encode_fns[] = { - Opcode_wur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_cend0_encode_fns[] = { - Opcode_rur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_cend0_encode_fns[] = { - Opcode_wur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24x2_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp16f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lq56_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sq56s_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lq32f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sq32f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_read_ipq_encode_fns[] = { - Opcode_read_ipq_Slot_inst_encode, 0, 0, Opcode_read_ipq_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_check_ipq_encode_fns[] = { - Opcode_check_ipq_Slot_inst_encode, 0, 0, Opcode_check_ipq_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_write_opq_encode_fns[] = { - Opcode_write_opq_Slot_inst_encode, 0, 0, Opcode_write_opq_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_check_opq_encode_fns[] = { - Opcode_check_opq_Slot_inst_encode, 0, 0, Opcode_check_opq_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { - Opcode_rur_expstate_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { - Opcode_wur_expstate_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { - Opcode_read_impwire_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { - Opcode_setb_expstate_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { - Opcode_clrb_expstate_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { - Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0, 0, 0 -}; - -int num_bypass_groups() { - return 0; -} - -int num_bypass_group_chunks() { - return 0; -} - -uint32 *bypass_entry(int i) { - return 0; -} - - -/* Opcode table. */ - -static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_shift32x5, 3 }, - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_shift32x5, 3 }, - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_opcode_internal opcodes[] = { - { "excw", ICLASS_xt_iclass_excw, - 0, - Opcode_excw_encode_fns, 0, 0 }, - { "rfe", ICLASS_xt_iclass_rfe, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfe_encode_fns, 0, 0 }, - { "rfme", ICLASS_xt_iclass_rfme, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfme_encode_fns, 0, 0 }, - { "rfde", ICLASS_xt_iclass_rfde, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfde_encode_fns, 0, 0 }, - { "syscall", ICLASS_xt_iclass_syscall, - 0, - Opcode_syscall_encode_fns, 0, 0 }, - { "call12", ICLASS_xt_iclass_call12, - XTENSA_OPCODE_IS_CALL, - Opcode_call12_encode_fns, 0, 0 }, - { "call8", ICLASS_xt_iclass_call8, - XTENSA_OPCODE_IS_CALL, - Opcode_call8_encode_fns, 0, 0 }, - { "call4", ICLASS_xt_iclass_call4, - XTENSA_OPCODE_IS_CALL, - Opcode_call4_encode_fns, 0, 0 }, - { "callx12", ICLASS_xt_iclass_callx12, - XTENSA_OPCODE_IS_CALL, - Opcode_callx12_encode_fns, 0, 0 }, - { "callx8", ICLASS_xt_iclass_callx8, - XTENSA_OPCODE_IS_CALL, - Opcode_callx8_encode_fns, 0, 0 }, - { "callx4", ICLASS_xt_iclass_callx4, - XTENSA_OPCODE_IS_CALL, - Opcode_callx4_encode_fns, 0, 0 }, - { "entry", ICLASS_xt_iclass_entry, - 0, - Opcode_entry_encode_fns, 0, 0 }, - { "movsp", ICLASS_xt_iclass_movsp, - 0, - Opcode_movsp_encode_fns, 0, 0 }, - { "rotw", ICLASS_xt_iclass_rotw, - 0, - Opcode_rotw_encode_fns, 0, 0 }, - { "retw", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_encode_fns, 0, 0 }, - { "retw.n", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_n_encode_fns, 0, 0 }, - { "rfwo", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwo_encode_fns, 0, 0 }, - { "rfwu", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwu_encode_fns, 0, 0 }, - { "l32e", ICLASS_xt_iclass_l32e, - 0, - Opcode_l32e_encode_fns, 0, 0 }, - { "s32e", ICLASS_xt_iclass_s32e, - 0, - Opcode_s32e_encode_fns, 0, 0 }, - { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, - 0, - Opcode_rsr_windowbase_encode_fns, 0, 0 }, - { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, - 0, - Opcode_wsr_windowbase_encode_fns, 0, 0 }, - { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, - 0, - Opcode_xsr_windowbase_encode_fns, 0, 0 }, - { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, - 0, - Opcode_rsr_windowstart_encode_fns, 0, 0 }, - { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, - 0, - Opcode_wsr_windowstart_encode_fns, 0, 0 }, - { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, - 0, - Opcode_xsr_windowstart_encode_fns, 0, 0 }, - { "add.n", ICLASS_xt_iclass_add_n, - 0, - Opcode_add_n_encode_fns, 0, 0 }, - { "addi.n", ICLASS_xt_iclass_addi_n, - 0, - Opcode_addi_n_encode_fns, 0, 0 }, - { "beqz.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_n_encode_fns, 0, 0 }, - { "bnez.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_n_encode_fns, 0, 0 }, - { "ill.n", ICLASS_xt_iclass_ill_n, - 0, - Opcode_ill_n_encode_fns, 0, 0 }, - { "l32i.n", ICLASS_xt_iclass_loadi4, - 0, - Opcode_l32i_n_encode_fns, 0, 0 }, - { "mov.n", ICLASS_xt_iclass_mov_n, - 0, - Opcode_mov_n_encode_fns, 0, 0 }, - { "movi.n", ICLASS_xt_iclass_movi_n, - 0, - Opcode_movi_n_encode_fns, 0, 0 }, - { "nop.n", ICLASS_xt_iclass_nopn, - 0, - Opcode_nop_n_encode_fns, 0, 0 }, - { "ret.n", ICLASS_xt_iclass_retn, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_n_encode_fns, 0, 0 }, - { "s32i.n", ICLASS_xt_iclass_storei4, - 0, - Opcode_s32i_n_encode_fns, 0, 0 }, - { "addi", ICLASS_xt_iclass_addi, - 0, - Opcode_addi_encode_fns, 0, 0 }, - { "addmi", ICLASS_xt_iclass_addmi, - 0, - Opcode_addmi_encode_fns, 0, 0 }, - { "add", ICLASS_xt_iclass_addsub, - 0, - Opcode_add_encode_fns, 0, 0 }, - { "sub", ICLASS_xt_iclass_addsub, - 0, - Opcode_sub_encode_fns, 0, 0 }, - { "addx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx2_encode_fns, 0, 0 }, - { "addx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx4_encode_fns, 0, 0 }, - { "addx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx8_encode_fns, 0, 0 }, - { "subx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx2_encode_fns, 0, 0 }, - { "subx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx4_encode_fns, 0, 0 }, - { "subx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx8_encode_fns, 0, 0 }, - { "and", ICLASS_xt_iclass_bit, - 0, - Opcode_and_encode_fns, 0, 0 }, - { "or", ICLASS_xt_iclass_bit, - 0, - Opcode_or_encode_fns, 0, 0 }, - { "xor", ICLASS_xt_iclass_bit, - 0, - Opcode_xor_encode_fns, 0, 0 }, - { "beqi", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqi_encode_fns, 0, 0 }, - { "bnei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnei_encode_fns, 0, 0 }, - { "bgei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgei_encode_fns, 0, 0 }, - { "blti", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blti_encode_fns, 0, 0 }, - { "bbci", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbci_encode_fns, 0, 0 }, - { "bbsi", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbsi_encode_fns, 0, 0 }, - { "bgeui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeui_encode_fns, 0, 0 }, - { "bltui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltui_encode_fns, 0, 0 }, - { "beq", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beq_encode_fns, 0, 0 }, - { "bne", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bne_encode_fns, 0, 0 }, - { "bge", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bge_encode_fns, 0, 0 }, - { "blt", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blt_encode_fns, 0, 0 }, - { "bgeu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeu_encode_fns, 0, 0 }, - { "bltu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltu_encode_fns, 0, 0 }, - { "bany", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bany_encode_fns, 0, 0 }, - { "bnone", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnone_encode_fns, 0, 0 }, - { "ball", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_ball_encode_fns, 0, 0 }, - { "bnall", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnall_encode_fns, 0, 0 }, - { "bbc", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbc_encode_fns, 0, 0 }, - { "bbs", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbs_encode_fns, 0, 0 }, - { "beqz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_encode_fns, 0, 0 }, - { "bnez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_encode_fns, 0, 0 }, - { "bgez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgez_encode_fns, 0, 0 }, - { "bltz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltz_encode_fns, 0, 0 }, - { "call0", ICLASS_xt_iclass_call0, - XTENSA_OPCODE_IS_CALL, - Opcode_call0_encode_fns, 0, 0 }, - { "callx0", ICLASS_xt_iclass_callx0, - XTENSA_OPCODE_IS_CALL, - Opcode_callx0_encode_fns, 0, 0 }, - { "extui", ICLASS_xt_iclass_exti, - 0, - Opcode_extui_encode_fns, 0, 0 }, - { "ill", ICLASS_xt_iclass_ill, - 0, - Opcode_ill_encode_fns, 0, 0 }, - { "j", ICLASS_xt_iclass_jump, - XTENSA_OPCODE_IS_JUMP, - Opcode_j_encode_fns, 0, 0 }, - { "jx", ICLASS_xt_iclass_jumpx, - XTENSA_OPCODE_IS_JUMP, - Opcode_jx_encode_fns, 0, 0 }, - { "l16ui", ICLASS_xt_iclass_l16ui, - 0, - Opcode_l16ui_encode_fns, 0, 0 }, - { "l16si", ICLASS_xt_iclass_l16si, - 0, - Opcode_l16si_encode_fns, 0, 0 }, - { "l32i", ICLASS_xt_iclass_l32i, - 0, - Opcode_l32i_encode_fns, 0, 0 }, - { "l32r", ICLASS_xt_iclass_l32r, - 0, - Opcode_l32r_encode_fns, 0, 0 }, - { "l8ui", ICLASS_xt_iclass_l8i, - 0, - Opcode_l8ui_encode_fns, 0, 0 }, - { "loop", ICLASS_xt_iclass_loop, - XTENSA_OPCODE_IS_LOOP, - Opcode_loop_encode_fns, 0, 0 }, - { "loopnez", ICLASS_xt_iclass_loopz, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopnez_encode_fns, 0, 0 }, - { "loopgtz", ICLASS_xt_iclass_loopz, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopgtz_encode_fns, 0, 0 }, - { "movi", ICLASS_xt_iclass_movi, - 0, - Opcode_movi_encode_fns, 0, 0 }, - { "moveqz", ICLASS_xt_iclass_movz, - 0, - Opcode_moveqz_encode_fns, 0, 0 }, - { "movnez", ICLASS_xt_iclass_movz, - 0, - Opcode_movnez_encode_fns, 0, 0 }, - { "movltz", ICLASS_xt_iclass_movz, - 0, - Opcode_movltz_encode_fns, 0, 0 }, - { "movgez", ICLASS_xt_iclass_movz, - 0, - Opcode_movgez_encode_fns, 0, 0 }, - { "neg", ICLASS_xt_iclass_neg, - 0, - Opcode_neg_encode_fns, 0, 0 }, - { "abs", ICLASS_xt_iclass_neg, - 0, - Opcode_abs_encode_fns, 0, 0 }, - { "nop", ICLASS_xt_iclass_nop, - 0, - Opcode_nop_encode_fns, 0, 0 }, - { "ret", ICLASS_xt_iclass_return, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_encode_fns, 0, 0 }, - { "simcall", ICLASS_xt_iclass_simcall, - 0, - Opcode_simcall_encode_fns, 0, 0 }, - { "s16i", ICLASS_xt_iclass_s16i, - 0, - Opcode_s16i_encode_fns, 0, 0 }, - { "s32i", ICLASS_xt_iclass_s32i, - 0, - Opcode_s32i_encode_fns, 0, 0 }, - { "s32nb", ICLASS_xt_iclass_s32nb, - 0, - Opcode_s32nb_encode_fns, 0, 0 }, - { "s8i", ICLASS_xt_iclass_s8i, - 0, - Opcode_s8i_encode_fns, 0, 0 }, - { "ssr", ICLASS_xt_iclass_sar, - 0, - Opcode_ssr_encode_fns, 0, 0 }, - { "ssl", ICLASS_xt_iclass_sar, - 0, - Opcode_ssl_encode_fns, 0, 0 }, - { "ssa8l", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8l_encode_fns, 0, 0 }, - { "ssa8b", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8b_encode_fns, 0, 0 }, - { "ssai", ICLASS_xt_iclass_sari, - 0, - Opcode_ssai_encode_fns, 0, 0 }, - { "sll", ICLASS_xt_iclass_shifts, - 0, - Opcode_sll_encode_fns, 0, 0 }, - { "src", ICLASS_xt_iclass_shiftst, - 0, - Opcode_src_encode_fns, 0, 0 }, - { "srl", ICLASS_xt_iclass_shiftt, - 0, - Opcode_srl_encode_fns, 0, 0 }, - { "sra", ICLASS_xt_iclass_shiftt, - 0, - Opcode_sra_encode_fns, 0, 0 }, - { "slli", ICLASS_xt_iclass_slli, - 0, - Opcode_slli_encode_fns, 0, 0 }, - { "srai", ICLASS_xt_iclass_srai, - 0, - Opcode_srai_encode_fns, 0, 0 }, - { "srli", ICLASS_xt_iclass_srli, - 0, - Opcode_srli_encode_fns, 0, 0 }, - { "memw", ICLASS_xt_iclass_memw, - 0, - Opcode_memw_encode_fns, 0, 0 }, - { "extw", ICLASS_xt_iclass_extw, - 0, - Opcode_extw_encode_fns, 0, 0 }, - { "isync", ICLASS_xt_iclass_isync, - 0, - Opcode_isync_encode_fns, 0, 0 }, - { "rsync", ICLASS_xt_iclass_sync, - 0, - Opcode_rsync_encode_fns, 0, 0 }, - { "esync", ICLASS_xt_iclass_sync, - 0, - Opcode_esync_encode_fns, 0, 0 }, - { "dsync", ICLASS_xt_iclass_sync, - 0, - Opcode_dsync_encode_fns, 0, 0 }, - { "rsil", ICLASS_xt_iclass_rsil, - 0, - Opcode_rsil_encode_fns, 0, 0 }, - { "rsr.lend", ICLASS_xt_iclass_rsr_lend, - 0, - Opcode_rsr_lend_encode_fns, 0, 0 }, - { "wsr.lend", ICLASS_xt_iclass_wsr_lend, - 0, - Opcode_wsr_lend_encode_fns, 0, 0 }, - { "xsr.lend", ICLASS_xt_iclass_xsr_lend, - 0, - Opcode_xsr_lend_encode_fns, 0, 0 }, - { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, - 0, - Opcode_rsr_lcount_encode_fns, 0, 0 }, - { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, - 0, - Opcode_wsr_lcount_encode_fns, 0, 0 }, - { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, - 0, - Opcode_xsr_lcount_encode_fns, 0, 0 }, - { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, - 0, - Opcode_rsr_lbeg_encode_fns, 0, 0 }, - { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, - 0, - Opcode_wsr_lbeg_encode_fns, 0, 0 }, - { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, - 0, - Opcode_xsr_lbeg_encode_fns, 0, 0 }, - { "rsr.sar", ICLASS_xt_iclass_rsr_sar, - 0, - Opcode_rsr_sar_encode_fns, 0, 0 }, - { "wsr.sar", ICLASS_xt_iclass_wsr_sar, - 0, - Opcode_wsr_sar_encode_fns, 0, 0 }, - { "xsr.sar", ICLASS_xt_iclass_xsr_sar, - 0, - Opcode_xsr_sar_encode_fns, 0, 0 }, - - - - { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo, - 0, - Opcode_rsr_acclo_encode_fns, 0, 0 }, - { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo, - 0, - Opcode_wsr_acclo_encode_fns, 0, 0 }, - { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo, - 0, - Opcode_xsr_acclo_encode_fns, 0, 0 }, - - { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi, - 0, - Opcode_rsr_acchi_encode_fns, 0, 0 }, - { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi, - 0, - Opcode_wsr_acchi_encode_fns, 0, 0 }, - { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi, - 0, - Opcode_xsr_acchi_encode_fns, 0, 0 }, - - { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, - 0, - Opcode_rsr_memctl_encode_fns, 0, 0 }, - { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, - 0, - Opcode_wsr_memctl_encode_fns, 0, 0 }, - { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, - 0, - Opcode_xsr_memctl_encode_fns, 0, 0 }, - - - { "rsr.mepc", ICLASS_xt_iclass_rsr_mepc, - 0, - Opcode_rsr_mepc_encode_fns, 0, 0 }, - { "wsr.mepc", ICLASS_xt_iclass_wsr_mepc, - 0, - Opcode_wsr_mepc_encode_fns, 0, 0 }, - { "xsr.mepc", ICLASS_xt_iclass_xsr_mepc, - 0, - Opcode_xsr_mepc_encode_fns, 0, 0 }, - - { "rsr.meps", ICLASS_xt_iclass_rsr_meps, - 0, - Opcode_rsr_meps_encode_fns, 0, 0 }, - { "wsr.meps", ICLASS_xt_iclass_wsr_meps, - 0, - Opcode_wsr_meps_encode_fns, 0, 0 }, - { "xsr.meps", ICLASS_xt_iclass_xsr_meps, - 0, - Opcode_xsr_meps_encode_fns, 0, 0 }, - - { "rsr.mesave", ICLASS_xt_iclass_rsr_mesave, - 0, - Opcode_rsr_mesave_encode_fns, 0, 0 }, - { "wsr.mesave", ICLASS_xt_iclass_wsr_mesave, - 0, - Opcode_wsr_mesave_encode_fns, 0, 0 }, - { "xsr.mesave", ICLASS_xt_iclass_xsr_mesave, - 0, - Opcode_xsr_mesave_encode_fns, 0, 0 }, - - { "rsr.mesr", ICLASS_xt_iclass_rsr_mesr, - 0, - Opcode_rsr_mesr_encode_fns, 0, 0 }, - { "wsr.mesr", ICLASS_xt_iclass_wsr_mesr, - 0, - Opcode_wsr_mesr_encode_fns, 0, 0 }, - { "xsr.mesr", ICLASS_xt_iclass_xsr_mesr, - 0, - Opcode_xsr_mesr_encode_fns, 0, 0 }, - - { "rsr.mecr", ICLASS_xt_iclass_rsr_mecr, - 0, - Opcode_rsr_mecr_encode_fns, 0, 0 }, - { "wsr.mecr", ICLASS_xt_iclass_wsr_mecr, - 0, - Opcode_wsr_mecr_encode_fns, 0, 0 }, - { "xsr.mecr", ICLASS_xt_iclass_xsr_mecr, - 0, - Opcode_xsr_mecr_encode_fns, 0, 0 }, - - { "rsr.mevaddr", ICLASS_xt_iclass_rsr_mevaddr, - 0, - Opcode_rsr_mevaddr_encode_fns, 0, 0 }, - { "wsr.mevaddr", ICLASS_xt_iclass_wsr_mevaddr, - 0, - Opcode_wsr_mevaddr_encode_fns, 0, 0 }, - { "xsr.mevaddr", ICLASS_xt_iclass_xsr_mevaddr, - 0, - Opcode_xsr_mevaddr_encode_fns, 0, 0 }, - - { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, - 0, - Opcode_rsr_litbase_encode_fns, 0, 0 }, - { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, - 0, - Opcode_wsr_litbase_encode_fns, 0, 0 }, - { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, - 0, - Opcode_xsr_litbase_encode_fns, 0, 0 }, - { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, - 0, - Opcode_rsr_configid0_encode_fns, 0, 0 }, - { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, - 0, - Opcode_wsr_configid0_encode_fns, 0, 0 }, - { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, - 0, - Opcode_rsr_configid1_encode_fns, 0, 0 }, - { "rsr.243", ICLASS_xt_iclass_rsr_243, - 0, - Opcode_rsr_243_encode_fns, 0, 0 }, - { "rsr.ps", ICLASS_xt_iclass_rsr_ps, - 0, - Opcode_rsr_ps_encode_fns, 0, 0 }, - { "wsr.ps", ICLASS_xt_iclass_wsr_ps, - 0, - Opcode_wsr_ps_encode_fns, 0, 0 }, - { "xsr.ps", ICLASS_xt_iclass_xsr_ps, - 0, - Opcode_xsr_ps_encode_fns, 0, 0 }, - { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, - 0, - Opcode_rsr_epc1_encode_fns, 0, 0 }, - { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, - 0, - Opcode_wsr_epc1_encode_fns, 0, 0 }, - { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, - 0, - Opcode_xsr_epc1_encode_fns, 0, 0 }, - { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, - 0, - Opcode_rsr_excsave1_encode_fns, 0, 0 }, - { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, - 0, - Opcode_wsr_excsave1_encode_fns, 0, 0 }, - { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, - 0, - Opcode_xsr_excsave1_encode_fns, 0, 0 }, - { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, - 0, - Opcode_rsr_epc2_encode_fns, 0, 0 }, - { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, - 0, - Opcode_wsr_epc2_encode_fns, 0, 0 }, - { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, - 0, - Opcode_xsr_epc2_encode_fns, 0, 0 }, - { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, - 0, - Opcode_rsr_excsave2_encode_fns, 0, 0 }, - { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, - 0, - Opcode_wsr_excsave2_encode_fns, 0, 0 }, - { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, - 0, - Opcode_xsr_excsave2_encode_fns, 0, 0 }, - { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, - 0, - Opcode_rsr_epc3_encode_fns, 0, 0 }, - { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, - 0, - Opcode_wsr_epc3_encode_fns, 0, 0 }, - { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, - 0, - Opcode_xsr_epc3_encode_fns, 0, 0 }, - { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, - 0, - Opcode_rsr_excsave3_encode_fns, 0, 0 }, - { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, - 0, - Opcode_wsr_excsave3_encode_fns, 0, 0 }, - { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, - 0, - Opcode_xsr_excsave3_encode_fns, 0, 0 }, - { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, - 0, - Opcode_rsr_epc4_encode_fns, 0, 0 }, - { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, - 0, - Opcode_wsr_epc4_encode_fns, 0, 0 }, - { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, - 0, - Opcode_xsr_epc4_encode_fns, 0, 0 }, - { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, - 0, - Opcode_rsr_excsave4_encode_fns, 0, 0 }, - { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, - 0, - Opcode_wsr_excsave4_encode_fns, 0, 0 }, - { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, - 0, - Opcode_xsr_excsave4_encode_fns, 0, 0 }, - { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, - 0, - Opcode_rsr_epc5_encode_fns, 0, 0 }, - { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, - 0, - Opcode_wsr_epc5_encode_fns, 0, 0 }, - { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, - 0, - Opcode_xsr_epc5_encode_fns, 0, 0 }, - { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, - 0, - Opcode_rsr_excsave5_encode_fns, 0, 0 }, - { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, - 0, - Opcode_wsr_excsave5_encode_fns, 0, 0 }, - { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, - 0, - Opcode_xsr_excsave5_encode_fns, 0, 0 }, - { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, - 0, - Opcode_rsr_epc6_encode_fns, 0, 0 }, - { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, - 0, - Opcode_wsr_epc6_encode_fns, 0, 0 }, - { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, - 0, - Opcode_xsr_epc6_encode_fns, 0, 0 }, - { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, - 0, - Opcode_rsr_excsave6_encode_fns, 0, 0 }, - { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, - 0, - Opcode_wsr_excsave6_encode_fns, 0, 0 }, - { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, - 0, - Opcode_xsr_excsave6_encode_fns, 0, 0 }, - { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, - 0, - Opcode_rsr_epc7_encode_fns, 0, 0 }, - { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, - 0, - Opcode_wsr_epc7_encode_fns, 0, 0 }, - { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, - 0, - Opcode_xsr_epc7_encode_fns, 0, 0 }, - { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, - 0, - Opcode_rsr_excsave7_encode_fns, 0, 0 }, - { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, - 0, - Opcode_wsr_excsave7_encode_fns, 0, 0 }, - { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, - 0, - Opcode_xsr_excsave7_encode_fns, 0, 0 }, - { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, - 0, - Opcode_rsr_eps2_encode_fns, 0, 0 }, - { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, - 0, - Opcode_wsr_eps2_encode_fns, 0, 0 }, - { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, - 0, - Opcode_xsr_eps2_encode_fns, 0, 0 }, - { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, - 0, - Opcode_rsr_eps3_encode_fns, 0, 0 }, - { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, - 0, - Opcode_wsr_eps3_encode_fns, 0, 0 }, - { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, - 0, - Opcode_xsr_eps3_encode_fns, 0, 0 }, - { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, - 0, - Opcode_rsr_eps4_encode_fns, 0, 0 }, - { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, - 0, - Opcode_wsr_eps4_encode_fns, 0, 0 }, - { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, - 0, - Opcode_xsr_eps4_encode_fns, 0, 0 }, - { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, - 0, - Opcode_rsr_eps5_encode_fns, 0, 0 }, - { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, - 0, - Opcode_wsr_eps5_encode_fns, 0, 0 }, - { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, - 0, - Opcode_xsr_eps5_encode_fns, 0, 0 }, - { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, - 0, - Opcode_rsr_eps6_encode_fns, 0, 0 }, - { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, - 0, - Opcode_wsr_eps6_encode_fns, 0, 0 }, - { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, - 0, - Opcode_xsr_eps6_encode_fns, 0, 0 }, - { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, - 0, - Opcode_rsr_eps7_encode_fns, 0, 0 }, - { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, - 0, - Opcode_wsr_eps7_encode_fns, 0, 0 }, - { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, - 0, - Opcode_xsr_eps7_encode_fns, 0, 0 }, - { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, - 0, - Opcode_rsr_excvaddr_encode_fns, 0, 0 }, - { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, - 0, - Opcode_wsr_excvaddr_encode_fns, 0, 0 }, - { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, - 0, - Opcode_xsr_excvaddr_encode_fns, 0, 0 }, - { "rsr.depc", ICLASS_xt_iclass_rsr_depc, - 0, - Opcode_rsr_depc_encode_fns, 0, 0 }, - { "wsr.depc", ICLASS_xt_iclass_wsr_depc, - 0, - Opcode_wsr_depc_encode_fns, 0, 0 }, - { "xsr.depc", ICLASS_xt_iclass_xsr_depc, - 0, - Opcode_xsr_depc_encode_fns, 0, 0 }, - { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, - 0, - Opcode_rsr_exccause_encode_fns, 0, 0 }, - { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, - 0, - Opcode_wsr_exccause_encode_fns, 0, 0 }, - { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, - 0, - Opcode_xsr_exccause_encode_fns, 0, 0 }, - { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, - 0, - Opcode_rsr_misc0_encode_fns, 0, 0 }, - { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, - 0, - Opcode_wsr_misc0_encode_fns, 0, 0 }, - { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, - 0, - Opcode_xsr_misc0_encode_fns, 0, 0 }, - { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, - 0, - Opcode_rsr_misc1_encode_fns, 0, 0 }, - { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, - 0, - Opcode_wsr_misc1_encode_fns, 0, 0 }, - { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, - 0, - Opcode_xsr_misc1_encode_fns, 0, 0 }, - { "rsr.prid", ICLASS_xt_iclass_rsr_prid, - 0, - Opcode_rsr_prid_encode_fns, 0, 0 }, - { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, - 0, - Opcode_rsr_vecbase_encode_fns, 0, 0 }, - { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, - 0, - Opcode_wsr_vecbase_encode_fns, 0, 0 }, - { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, - 0, - Opcode_xsr_vecbase_encode_fns, 0, 0 }, - { "mul16u", ICLASS_xt_mul16, - 0, - Opcode_mul16u_encode_fns, 0, 0 }, - { "mul16s", ICLASS_xt_mul16, - 0, - Opcode_mul16s_encode_fns, 0, 0 }, - { "mull", ICLASS_xt_mul32, - 0, - Opcode_mull_encode_fns, 0, 0 }, - { "rfi", ICLASS_xt_iclass_rfi, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfi_encode_fns, 0, 0 }, - { "waiti", ICLASS_xt_iclass_wait, - 0, - Opcode_waiti_encode_fns, 0, 0 }, - { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, - 0, - Opcode_rsr_interrupt_encode_fns, 0, 0 }, - { "wsr.intset", ICLASS_xt_iclass_wsr_intset, - 0, - Opcode_wsr_intset_encode_fns, 0, 0 }, - { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, - 0, - Opcode_wsr_intclear_encode_fns, 0, 0 }, - { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, - 0, - Opcode_rsr_intenable_encode_fns, 0, 0 }, - { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, - 0, - Opcode_wsr_intenable_encode_fns, 0, 0 }, - { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, - 0, - Opcode_xsr_intenable_encode_fns, 0, 0 }, - { "break", ICLASS_xt_iclass_break, - 0, - Opcode_break_encode_fns, 0, 0 }, - { "break.n", ICLASS_xt_iclass_break_n, - 0, - Opcode_break_n_encode_fns, 0, 0 }, - { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, - 0, - Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, - { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, - 0, - Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, - { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, - 0, - Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, - { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, - 0, - Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, - { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, - 0, - Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, - { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, - 0, - Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, - { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, - 0, - Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, - { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, - 0, - Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, - { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, - 0, - Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, - { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, - 0, - Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, - { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, - 0, - Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, - { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, - 0, - Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, - { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, - 0, - Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, - { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, - 0, - Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, - { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, - 0, - Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, - { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, - 0, - Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, - { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, - 0, - Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, - { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, - 0, - Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, - { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, - 0, - Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, - { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, - 0, - Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, - { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, - 0, - Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, - { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, - 0, - Opcode_rsr_debugcause_encode_fns, 0, 0 }, - { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, - 0, - Opcode_wsr_debugcause_encode_fns, 0, 0 }, - { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, - 0, - Opcode_xsr_debugcause_encode_fns, 0, 0 }, - { "rsr.icount", ICLASS_xt_iclass_rsr_icount, - 0, - Opcode_rsr_icount_encode_fns, 0, 0 }, - { "wsr.icount", ICLASS_xt_iclass_wsr_icount, - 0, - Opcode_wsr_icount_encode_fns, 0, 0 }, - { "xsr.icount", ICLASS_xt_iclass_xsr_icount, - 0, - Opcode_xsr_icount_encode_fns, 0, 0 }, - { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, - 0, - Opcode_rsr_icountlevel_encode_fns, 0, 0 }, - { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, - 0, - Opcode_wsr_icountlevel_encode_fns, 0, 0 }, - { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, - 0, - Opcode_xsr_icountlevel_encode_fns, 0, 0 }, - { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, - 0, - Opcode_rsr_ddr_encode_fns, 0, 0 }, - { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, - 0, - Opcode_wsr_ddr_encode_fns, 0, 0 }, - { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, - 0, - Opcode_xsr_ddr_encode_fns, 0, 0 }, - { "lddr32.p", ICLASS_xt_iclass_lddr32_p, - 0, - Opcode_lddr32_p_encode_fns, 0, 0 }, - { "sddr32.p", ICLASS_xt_iclass_sddr32_p, - 0, - Opcode_sddr32_p_encode_fns, 0, 0 }, - { "rfdo", ICLASS_xt_iclass_rfdo, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdo_encode_fns, 0, 0 }, - { "rfdd", ICLASS_xt_iclass_rfdd, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdd_encode_fns, 0, 0 }, - { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, - 0, - Opcode_wsr_mmid_encode_fns, 0, 0 }, - { "andb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_andb_encode_fns, 0, 0 }, - { "andbc", ICLASS_xt_iclass_bbool1, - 0, - Opcode_andbc_encode_fns, 0, 0 }, - { "orb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_orb_encode_fns, 0, 0 }, - { "orbc", ICLASS_xt_iclass_bbool1, - 0, - Opcode_orbc_encode_fns, 0, 0 }, - { "xorb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_xorb_encode_fns, 0, 0 }, - { "any4", ICLASS_xt_iclass_bbool4, - 0, - Opcode_any4_encode_fns, 0, 0 }, - { "all4", ICLASS_xt_iclass_bbool4, - 0, - Opcode_all4_encode_fns, 0, 0 }, - { "any8", ICLASS_xt_iclass_bbool8, - 0, - Opcode_any8_encode_fns, 0, 0 }, - { "all8", ICLASS_xt_iclass_bbool8, - 0, - Opcode_all8_encode_fns, 0, 0 }, - { "bf", ICLASS_xt_iclass_bbranch, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bf_encode_fns, 0, 0 }, - { "bt", ICLASS_xt_iclass_bbranch, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bt_encode_fns, 0, 0 }, - { "movf", ICLASS_xt_iclass_bmove, - 0, - Opcode_movf_encode_fns, 0, 0 }, - { "movt", ICLASS_xt_iclass_bmove, - 0, - Opcode_movt_encode_fns, 0, 0 }, - { "rsr.br", ICLASS_xt_iclass_RSR_BR, - 0, - Opcode_rsr_br_encode_fns, 0, 0 }, - { "wsr.br", ICLASS_xt_iclass_WSR_BR, - 0, - Opcode_wsr_br_encode_fns, 0, 0 }, - { "xsr.br", ICLASS_xt_iclass_XSR_BR, - 0, - Opcode_xsr_br_encode_fns, 0, 0 }, - { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, - 0, - Opcode_rsr_ccount_encode_fns, 0, 0 }, - { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, - 0, - Opcode_wsr_ccount_encode_fns, 0, 0 }, - { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, - 0, - Opcode_xsr_ccount_encode_fns, 0, 0 }, - { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, - 0, - Opcode_rsr_ccompare0_encode_fns, 0, 0 }, - { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, - 0, - Opcode_wsr_ccompare0_encode_fns, 0, 0 }, - { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, - 0, - Opcode_xsr_ccompare0_encode_fns, 0, 0 }, - { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, - 0, - Opcode_rsr_ccompare1_encode_fns, 0, 0 }, - { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, - 0, - Opcode_wsr_ccompare1_encode_fns, 0, 0 }, - { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, - 0, - Opcode_xsr_ccompare1_encode_fns, 0, 0 }, - { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, - 0, - Opcode_rsr_ccompare2_encode_fns, 0, 0 }, - { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, - 0, - Opcode_wsr_ccompare2_encode_fns, 0, 0 }, - { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, - 0, - Opcode_xsr_ccompare2_encode_fns, 0, 0 }, - { "ipf", ICLASS_xt_iclass_icache, - 0, - Opcode_ipf_encode_fns, 0, 0 }, - { "ihi", ICLASS_xt_iclass_icache, - 0, - Opcode_ihi_encode_fns, 0, 0 }, - { "ipfl", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_ipfl_encode_fns, 0, 0 }, - { "ihu", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_ihu_encode_fns, 0, 0 }, - { "iiu", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_iiu_encode_fns, 0, 0 }, - { "iii", ICLASS_xt_iclass_icache_inv, - 0, - Opcode_iii_encode_fns, 0, 0 }, - { "lict", ICLASS_xt_iclass_licx, - 0, - Opcode_lict_encode_fns, 0, 0 }, - { "licw", ICLASS_xt_iclass_licx, - 0, - Opcode_licw_encode_fns, 0, 0 }, - { "sict", ICLASS_xt_iclass_sicx, - 0, - Opcode_sict_encode_fns, 0, 0 }, - { "sicw", ICLASS_xt_iclass_sicx, - 0, - Opcode_sicw_encode_fns, 0, 0 }, - { "dhwb", ICLASS_xt_iclass_dcache, - 0, - Opcode_dhwb_encode_fns, 0, 0 }, - { "dhwbi", ICLASS_xt_iclass_dcache, - 0, - Opcode_dhwbi_encode_fns, 0, 0 }, - { "diwbui.p", ICLASS_xt_iclass_dcache_dyn, - 0, - Opcode_diwbui_p_encode_fns, 0, 0 }, - { "diwb", ICLASS_xt_iclass_dcache_ind, - 0, - Opcode_diwb_encode_fns, 0, 0 }, - { "diwbi", ICLASS_xt_iclass_dcache_ind, - 0, - Opcode_diwbi_encode_fns, 0, 0 }, - { "dhi", ICLASS_xt_iclass_dcache_inv, - 0, - Opcode_dhi_encode_fns, 0, 0 }, - { "dii", ICLASS_xt_iclass_dcache_inv, - 0, - Opcode_dii_encode_fns, 0, 0 }, - { "dpfr", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfr_encode_fns, 0, 0 }, - { "dpfw", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfw_encode_fns, 0, 0 }, - { "dpfro", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfro_encode_fns, 0, 0 }, - { "dpfwo", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfwo_encode_fns, 0, 0 }, - { "dpfl", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_dpfl_encode_fns, 0, 0 }, - { "dhu", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_dhu_encode_fns, 0, 0 }, - { "diu", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_diu_encode_fns, 0, 0 }, - { "sdct", ICLASS_xt_iclass_sdct, - 0, - Opcode_sdct_encode_fns, 0, 0 }, - { "ldct", ICLASS_xt_iclass_ldct, - 0, - Opcode_ldct_encode_fns, 0, 0 }, - { "rsr.prefctl", ICLASS_xt_iclass_rsr_prefctl, - 0, - Opcode_rsr_prefctl_encode_fns, 0, 0 }, - { "wsr.prefctl", ICLASS_xt_iclass_wsr_prefctl, - 0, - Opcode_wsr_prefctl_encode_fns, 0, 0 }, - { "xsr.prefctl", ICLASS_xt_iclass_xsr_prefctl, - 0, - Opcode_xsr_prefctl_encode_fns, 0, 0 }, - { "idtlb", ICLASS_xt_iclass_idtlb, - 0, - Opcode_idtlb_encode_fns, 0, 0 }, - { "pdtlb", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_pdtlb_encode_fns, 0, 0 }, - { "rdtlb0", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb0_encode_fns, 0, 0 }, - { "rdtlb1", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb1_encode_fns, 0, 0 }, - { "wdtlb", ICLASS_xt_iclass_wdtlb, - 0, - Opcode_wdtlb_encode_fns, 0, 0 }, - { "iitlb", ICLASS_xt_iclass_iitlb, - 0, - Opcode_iitlb_encode_fns, 0, 0 }, - { "pitlb", ICLASS_xt_iclass_ritlb, - 0, - Opcode_pitlb_encode_fns, 0, 0 }, - { "ritlb0", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb0_encode_fns, 0, 0 }, - { "ritlb1", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb1_encode_fns, 0, 0 }, - { "witlb", ICLASS_xt_iclass_witlb, - 0, - Opcode_witlb_encode_fns, 0, 0 }, - { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, - 0, - Opcode_rsr_cpenable_encode_fns, 0, 0 }, - { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, - 0, - Opcode_wsr_cpenable_encode_fns, 0, 0 }, - { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, - 0, - Opcode_xsr_cpenable_encode_fns, 0, 0 }, - { "clamps", ICLASS_xt_iclass_clamp, - 0, - Opcode_clamps_encode_fns, 0, 0 }, - { "min", ICLASS_xt_iclass_minmax, - 0, - Opcode_min_encode_fns, 0, 0 }, - { "max", ICLASS_xt_iclass_minmax, - 0, - Opcode_max_encode_fns, 0, 0 }, - { "minu", ICLASS_xt_iclass_minmax, - 0, - Opcode_minu_encode_fns, 0, 0 }, - { "maxu", ICLASS_xt_iclass_minmax, - 0, - Opcode_maxu_encode_fns, 0, 0 }, - { "nsa", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsa_encode_fns, 0, 0 }, - { "nsau", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsau_encode_fns, 0, 0 }, - { "sext", ICLASS_xt_iclass_sx, - 0, - Opcode_sext_encode_fns, 0, 0 }, - { "l32ai", ICLASS_xt_iclass_l32ai, - 0, - Opcode_l32ai_encode_fns, 0, 0 }, - { "s32ri", ICLASS_xt_iclass_s32ri, - 0, - Opcode_s32ri_encode_fns, 0, 0 }, - { "s32c1i", ICLASS_xt_iclass_s32c1i, - 0, - Opcode_s32c1i_encode_fns, 0, 0 }, - { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, - 0, - Opcode_rsr_scompare1_encode_fns, 0, 0 }, - { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, - 0, - Opcode_wsr_scompare1_encode_fns, 0, 0 }, - { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, - 0, - Opcode_xsr_scompare1_encode_fns, 0, 0 }, - { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, - 0, - Opcode_rsr_atomctl_encode_fns, 0, 0 }, - { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, - 0, - Opcode_wsr_atomctl_encode_fns, 0, 0 }, - { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, - 0, - Opcode_xsr_atomctl_encode_fns, 0, 0 }, - { "quou", ICLASS_xt_iclass_div, - 0, - Opcode_quou_encode_fns, 0, 0 }, - { "quos", ICLASS_xt_iclass_div, - 0, - Opcode_quos_encode_fns, 0, 0 }, - { "remu", ICLASS_xt_iclass_div, - 0, - Opcode_remu_encode_fns, 0, 0 }, - { "rems", ICLASS_xt_iclass_div, - 0, - Opcode_rems_encode_fns, 0, 0 }, - { "rer", ICLASS_xt_iclass_rer, - 0, - Opcode_rer_encode_fns, 0, 0 }, - { "wer", ICLASS_xt_iclass_wer, - 0, - Opcode_wer_encode_fns, 0, 0 }, - { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar, - 0, - Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 }, - { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar, - 0, - Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 }, - { "rur.ae_bithead", ICLASS_rur_ae_bithead, - 0, - Opcode_rur_ae_bithead_encode_fns, 0, 0 }, - { "wur.ae_bithead", ICLASS_wur_ae_bithead, - 0, - Opcode_wur_ae_bithead_encode_fns, 0, 0 }, - { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp, - 0, - Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, - { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp, - 0, - Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, - { "rur.ae_sd_no", ICLASS_rur_ae_sd_no, - 0, - Opcode_rur_ae_sd_no_encode_fns, 0, 0 }, - { "wur.ae_sd_no", ICLASS_wur_ae_sd_no, - 0, - Opcode_wur_ae_sd_no_encode_fns, 0, 0 }, - { "rur.ae_overflow", ICLASS_ae_iclass_rur_ae_overflow, - 0, - Opcode_rur_ae_overflow_encode_fns, 0, 0 }, - { "wur.ae_overflow", ICLASS_ae_iclass_wur_ae_overflow, - 0, - Opcode_wur_ae_overflow_encode_fns, 0, 0 }, - { "rur.ae_sar", ICLASS_ae_iclass_rur_ae_sar, - 0, - Opcode_rur_ae_sar_encode_fns, 0, 0 }, - { "wur.ae_sar", ICLASS_ae_iclass_wur_ae_sar, - 0, - Opcode_wur_ae_sar_encode_fns, 0, 0 }, - { "rur.ae_bitptr", ICLASS_ae_iclass_rur_ae_bitptr, - 0, - Opcode_rur_ae_bitptr_encode_fns, 0, 0 }, - { "wur.ae_bitptr", ICLASS_ae_iclass_wur_ae_bitptr, - 0, - Opcode_wur_ae_bitptr_encode_fns, 0, 0 }, - { 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Opcode_ae_roundsq32asym_encode_fns, 0, 0 }, - { "ae_trunca32q48", ICLASS_ae_iclass_trunca32q48, - 0, - Opcode_ae_trunca32q48_encode_fns, 0, 0 }, - { "ae_movap24s.l", ICLASS_ae_iclass_movap24s_l, - 0, - Opcode_ae_movap24s_l_encode_fns, 0, 0 }, - { "ae_movap24s.h", ICLASS_ae_iclass_movap24s_h, - 0, - Opcode_ae_movap24s_h_encode_fns, 0, 0 }, - { "ae_trunca16p24s.l", ICLASS_ae_iclass_trunca16p24s_l, - 0, - Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 }, - { "ae_trunca16p24s.h", ICLASS_ae_iclass_trunca16p24s_h, - 0, - Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 }, - { "ae_addp24", ICLASS_ae_iclass_addp24, - 0, - Opcode_ae_addp24_encode_fns, 0, 0 }, - { "ae_subp24", ICLASS_ae_iclass_subp24, - 0, - Opcode_ae_subp24_encode_fns, 0, 0 }, - { "ae_negp24", ICLASS_ae_iclass_negp24, - 0, - Opcode_ae_negp24_encode_fns, 0, 0 }, - { "ae_absp24", ICLASS_ae_iclass_absp24, - 0, - Opcode_ae_absp24_encode_fns, 0, 0 }, - { "ae_maxp24s", ICLASS_ae_iclass_maxp24s, - 0, - Opcode_ae_maxp24s_encode_fns, 0, 0 }, - { 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Opcode_ae_mulzsaq32sp16s_hh_encode_fns, 0, 0 }, - { "ae_mulzsafq32sp16s.hh", ICLASS_ae_iclass_mulzsafq32sp16s_hh, - 0, - Opcode_ae_mulzsafq32sp16s_hh_encode_fns, 0, 0 }, - { "ae_mulzsaq32sp16u.hh", ICLASS_ae_iclass_mulzsaq32sp16u_hh, - 0, - Opcode_ae_mulzsaq32sp16u_hh_encode_fns, 0, 0 }, - { "ae_mulzsafq32sp16u.hh", ICLASS_ae_iclass_mulzsafq32sp16u_hh, - 0, - Opcode_ae_mulzsafq32sp16u_hh_encode_fns, 0, 0 }, - { "ae_mulzsaq32sp16s.lh", ICLASS_ae_iclass_mulzsaq32sp16s_lh, - 0, - Opcode_ae_mulzsaq32sp16s_lh_encode_fns, 0, 0 }, - { "ae_mulzsafq32sp16s.lh", ICLASS_ae_iclass_mulzsafq32sp16s_lh, - 0, - Opcode_ae_mulzsafq32sp16s_lh_encode_fns, 0, 0 }, - { "ae_mulzsaq32sp16u.lh", ICLASS_ae_iclass_mulzsaq32sp16u_lh, - 0, - Opcode_ae_mulzsaq32sp16u_lh_encode_fns, 0, 0 }, - { "ae_mulzsafq32sp16u.lh", ICLASS_ae_iclass_mulzsafq32sp16u_lh, - 0, - Opcode_ae_mulzsafq32sp16u_lh_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16s.ll", ICLASS_ae_iclass_mulzssq32sp16s_ll, - 0, - Opcode_ae_mulzssq32sp16s_ll_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16s.ll", ICLASS_ae_iclass_mulzssfq32sp16s_ll, - 0, - Opcode_ae_mulzssfq32sp16s_ll_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16u.ll", ICLASS_ae_iclass_mulzssq32sp16u_ll, - 0, - Opcode_ae_mulzssq32sp16u_ll_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16u.ll", ICLASS_ae_iclass_mulzssfq32sp16u_ll, - 0, - Opcode_ae_mulzssfq32sp16u_ll_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16s.hh", ICLASS_ae_iclass_mulzssq32sp16s_hh, - 0, - Opcode_ae_mulzssq32sp16s_hh_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16s.hh", ICLASS_ae_iclass_mulzssfq32sp16s_hh, - 0, - Opcode_ae_mulzssfq32sp16s_hh_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16u.hh", ICLASS_ae_iclass_mulzssq32sp16u_hh, - 0, - Opcode_ae_mulzssq32sp16u_hh_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16u.hh", ICLASS_ae_iclass_mulzssfq32sp16u_hh, - 0, - Opcode_ae_mulzssfq32sp16u_hh_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16s.lh", ICLASS_ae_iclass_mulzssq32sp16s_lh, - 0, - Opcode_ae_mulzssq32sp16s_lh_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16s.lh", ICLASS_ae_iclass_mulzssfq32sp16s_lh, - 0, - Opcode_ae_mulzssfq32sp16s_lh_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16u.lh", ICLASS_ae_iclass_mulzssq32sp16u_lh, - 0, - Opcode_ae_mulzssq32sp16u_lh_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16u.lh", ICLASS_ae_iclass_mulzssfq32sp16u_lh, - 0, - Opcode_ae_mulzssfq32sp16u_lh_encode_fns, 0, 0 }, - { "ae_mulzaafp24s.hh.ll", ICLASS_ae_iclass_mulzaafp24s_hh_ll, - 0, - Opcode_ae_mulzaafp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzaap24s.hh.ll", ICLASS_ae_iclass_mulzaap24s_hh_ll, - 0, - Opcode_ae_mulzaap24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzaafp24s.hl.lh", ICLASS_ae_iclass_mulzaafp24s_hl_lh, - 0, - Opcode_ae_mulzaafp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzaap24s.hl.lh", ICLASS_ae_iclass_mulzaap24s_hl_lh, - 0, - Opcode_ae_mulzaap24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzasfp24s.hh.ll", ICLASS_ae_iclass_mulzasfp24s_hh_ll, - 0, - Opcode_ae_mulzasfp24s_hh_ll_encode_fns, 0, 0 }, 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- Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses }, - { "ae_lbki", ICLASS_ae_iclass_lbki, - 0, - Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses }, - { "ae_db", ICLASS_ae_iclass_db, - 0, - Opcode_ae_db_encode_fns, 2, Opcode_ae_db_funcUnit_uses }, - { "ae_dbi", ICLASS_ae_iclass_dbi, - 0, - Opcode_ae_dbi_encode_fns, 2, Opcode_ae_dbi_funcUnit_uses }, - { "ae_vlel32t", ICLASS_ae_iclass_vlel32t, - 0, - Opcode_ae_vlel32t_encode_fns, 1, Opcode_ae_vlel32t_funcUnit_uses }, - { "ae_vlel16t", ICLASS_ae_iclass_vlel16t, - 0, - Opcode_ae_vlel16t_encode_fns, 1, Opcode_ae_vlel16t_funcUnit_uses }, - { "ae_sb", ICLASS_ae_iclass_sb, - 0, - Opcode_ae_sb_encode_fns, 2, Opcode_ae_sb_funcUnit_uses }, - { "ae_sbi", ICLASS_ae_iclass_sbi, - 0, - Opcode_ae_sbi_encode_fns, 2, Opcode_ae_sbi_funcUnit_uses }, - { "ae_vles16c", ICLASS_ae_iclass_vles16c, - 0, - Opcode_ae_vles16c_encode_fns, 2, Opcode_ae_vles16c_funcUnit_uses }, - { "ae_sbf", ICLASS_ae_iclass_sbf, - 0, - Opcode_ae_sbf_encode_fns, 2, Opcode_ae_sbf_funcUnit_uses }, - { "ae_slaasq56s", ICLASS_icls_AE_SLAASQ56S, - 0, - Opcode_ae_slaasq56s_encode_fns, 0, 0 }, - { "ae_addbrba32", ICLASS_icls_AE_ADDBRBA32, - 0, - Opcode_ae_addbrba32_encode_fns, 0, 0 }, - { "ae_minabssp24s", ICLASS_icls_AE_MINABSSP24S, - 0, - Opcode_ae_minabssp24s_encode_fns, 0, 0 }, - { "ae_maxabssp24s", ICLASS_icls_AE_MAXABSSP24S, - 0, - Opcode_ae_maxabssp24s_encode_fns, 0, 0 }, - { "ae_minabssq56s", ICLASS_icls_AE_MINABSSQ56S, - 0, - Opcode_ae_minabssq56s_encode_fns, 0, 0 }, - { "ae_maxabssq56s", ICLASS_icls_AE_MAXABSSQ56S, - 0, - Opcode_ae_maxabssq56s_encode_fns, 0, 0 }, - { "rur.ae_cbegin0", ICLASS_rur_ae_cbegin0, - 0, - Opcode_rur_ae_cbegin0_encode_fns, 0, 0 }, - { "wur.ae_cbegin0", ICLASS_wur_ae_cbegin0, - 0, - Opcode_wur_ae_cbegin0_encode_fns, 0, 0 }, - { "rur.ae_cend0", ICLASS_rur_ae_cend0, - 0, - Opcode_rur_ae_cend0_encode_fns, 0, 0 }, - { "wur.ae_cend0", ICLASS_wur_ae_cend0, - 0, - Opcode_wur_ae_cend0_encode_fns, 0, 0 }, - { "ae_lp24x2.c", ICLASS_icls_AE_LP24X2_C, - 0, - Opcode_ae_lp24x2_c_encode_fns, 0, 0 }, - { "ae_sp24x2s.c", ICLASS_icls_AE_SP24X2S_C, - 0, - Opcode_ae_sp24x2s_c_encode_fns, 0, 0 }, - { "ae_lp24x2f.c", ICLASS_icls_AE_LP24X2F_C, - 0, - Opcode_ae_lp24x2f_c_encode_fns, 0, 0 }, - { "ae_sp24x2f.c", ICLASS_icls_AE_SP24X2F_C, - 0, - Opcode_ae_sp24x2f_c_encode_fns, 0, 0 }, - { "ae_lp16x2f.c", ICLASS_icls_AE_LP16X2F_C, - 0, - Opcode_ae_lp16x2f_c_encode_fns, 0, 0 }, - { "ae_sp16x2f.c", ICLASS_icls_AE_SP16X2F_C, - 0, - Opcode_ae_sp16x2f_c_encode_fns, 0, 0 }, - { "ae_lp24.c", ICLASS_icls_AE_LP24_C, - 0, - Opcode_ae_lp24_c_encode_fns, 0, 0 }, - { "ae_sp24s.l.c", ICLASS_icls_AE_SP24S_L_C, - 0, - Opcode_ae_sp24s_l_c_encode_fns, 0, 0 }, - { "ae_lp24f.c", ICLASS_icls_AE_LP24F_C, - 0, - Opcode_ae_lp24f_c_encode_fns, 0, 0 }, - { "ae_sp24f.l.c", ICLASS_icls_AE_SP24F_L_C, - 0, - Opcode_ae_sp24f_l_c_encode_fns, 0, 0 }, - { "ae_lp16f.c", ICLASS_icls_AE_LP16F_C, - 0, - Opcode_ae_lp16f_c_encode_fns, 0, 0 }, - { "ae_sp16f.l.c", ICLASS_icls_AE_SP16F_L_C, - 0, - Opcode_ae_sp16f_l_c_encode_fns, 0, 0 }, - { "ae_lq56.c", ICLASS_icls_AE_LQ56_C, - 0, - Opcode_ae_lq56_c_encode_fns, 0, 0 }, - { "ae_sq56s.c", ICLASS_icls_AE_SQ56S_C, - 0, - Opcode_ae_sq56s_c_encode_fns, 0, 0 }, - { "ae_lq32f.c", ICLASS_icls_AE_LQ32F_C, - 0, - Opcode_ae_lq32f_c_encode_fns, 0, 0 }, - { "ae_sq32f.c", ICLASS_icls_AE_SQ32F_C, - 0, - Opcode_ae_sq32f_c_encode_fns, 0, 0 }, - { "read_ipq", ICLASS_iclass_READ_IPQ, - 0, - Opcode_read_ipq_encode_fns, 0, 0 }, - { "check_ipq", ICLASS_iclass_CHECK_IPQ, - 0, - Opcode_check_ipq_encode_fns, 0, 0 }, - { "write_opq", ICLASS_iclass_WRITE_OPQ, - 0, - Opcode_write_opq_encode_fns, 0, 0 }, - { "check_opq", ICLASS_iclass_CHECK_OPQ, - 0, - Opcode_check_opq_encode_fns, 0, 0 }, - { "rur.expstate", ICLASS_rur_expstate, - 0, - Opcode_rur_expstate_encode_fns, 0, 0 }, - { "wur.expstate", ICLASS_wur_expstate, - 0, - Opcode_wur_expstate_encode_fns, 0, 0 }, - { "read_impwire", ICLASS_iclass_READ_IMPWIRE, - 0, - Opcode_read_impwire_encode_fns, 0, 0 }, - { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, - 0, - Opcode_setb_expstate_encode_fns, 0, 0 }, - { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, - 0, - Opcode_clrb_expstate_encode_fns, 0, 0 }, - { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, - 0, - Opcode_wrmsk_expstate_encode_fns, 0, 0 } -}; - -enum xtensa_opcode_id { - OPCODE_EXCW, - OPCODE_RFE, - OPCODE_RFME, - OPCODE_RFDE, - OPCODE_SYSCALL, - OPCODE_CALL12, - OPCODE_CALL8, - OPCODE_CALL4, - OPCODE_CALLX12, - OPCODE_CALLX8, - OPCODE_CALLX4, - OPCODE_ENTRY, - OPCODE_MOVSP, - OPCODE_ROTW, - OPCODE_RETW, - OPCODE_RETW_N, - OPCODE_RFWO, - OPCODE_RFWU, - OPCODE_L32E, - OPCODE_S32E, - OPCODE_RSR_WINDOWBASE, - OPCODE_WSR_WINDOWBASE, - OPCODE_XSR_WINDOWBASE, - OPCODE_RSR_WINDOWSTART, - OPCODE_WSR_WINDOWSTART, - OPCODE_XSR_WINDOWSTART, - OPCODE_ADD_N, - OPCODE_ADDI_N, - OPCODE_BEQZ_N, - OPCODE_BNEZ_N, - OPCODE_ILL_N, - OPCODE_L32I_N, - OPCODE_MOV_N, - OPCODE_MOVI_N, - OPCODE_NOP_N, - OPCODE_RET_N, - OPCODE_S32I_N, - OPCODE_ADDI, - OPCODE_ADDMI, - OPCODE_ADD, - OPCODE_SUB, - OPCODE_ADDX2, - OPCODE_ADDX4, - OPCODE_ADDX8, - OPCODE_SUBX2, - OPCODE_SUBX4, - OPCODE_SUBX8, - OPCODE_AND, - OPCODE_OR, - OPCODE_XOR, - OPCODE_BEQI, - OPCODE_BNEI, - OPCODE_BGEI, - OPCODE_BLTI, - OPCODE_BBCI, - OPCODE_BBSI, - OPCODE_BGEUI, - OPCODE_BLTUI, - OPCODE_BEQ, - OPCODE_BNE, - OPCODE_BGE, - OPCODE_BLT, - OPCODE_BGEU, - OPCODE_BLTU, - OPCODE_BANY, - OPCODE_BNONE, - OPCODE_BALL, - OPCODE_BNALL, - OPCODE_BBC, - OPCODE_BBS, - OPCODE_BEQZ, - OPCODE_BNEZ, - OPCODE_BGEZ, - OPCODE_BLTZ, - OPCODE_CALL0, - OPCODE_CALLX0, - OPCODE_EXTUI, - OPCODE_ILL, - OPCODE_J, - OPCODE_JX, - OPCODE_L16UI, - OPCODE_L16SI, - OPCODE_L32I, - OPCODE_L32R, - OPCODE_L8UI, - OPCODE_LOOP, - OPCODE_LOOPNEZ, - OPCODE_LOOPGTZ, - OPCODE_MOVI, - OPCODE_MOVEQZ, - OPCODE_MOVNEZ, - OPCODE_MOVLTZ, - OPCODE_MOVGEZ, - OPCODE_NEG, - OPCODE_ABS, - OPCODE_NOP, - OPCODE_RET, - OPCODE_SIMCALL, - OPCODE_S16I, - OPCODE_S32I, - OPCODE_S32NB, - OPCODE_S8I, - OPCODE_SSR, - OPCODE_SSL, - OPCODE_SSA8L, - OPCODE_SSA8B, - OPCODE_SSAI, - OPCODE_SLL, - OPCODE_SRC, - OPCODE_SRL, - OPCODE_SRA, - OPCODE_SLLI, - OPCODE_SRAI, - OPCODE_SRLI, - OPCODE_MEMW, - OPCODE_EXTW, - OPCODE_ISYNC, - OPCODE_RSYNC, - OPCODE_ESYNC, - OPCODE_DSYNC, - OPCODE_RSIL, - OPCODE_RSR_LEND, - OPCODE_WSR_LEND, - OPCODE_XSR_LEND, - OPCODE_RSR_LCOUNT, - OPCODE_WSR_LCOUNT, - OPCODE_XSR_LCOUNT, - OPCODE_RSR_LBEG, - OPCODE_WSR_LBEG, - OPCODE_XSR_LBEG, - OPCODE_RSR_SAR, - OPCODE_WSR_SAR, - OPCODE_XSR_SAR, - - OPCODE_RSR_ACCLO, - OPCODE_WSR_ACCLO, - OPCODE_XSR_ACCLO, - - OPCODE_RSR_ACCHI, - OPCODE_WSR_ACCHI, - OPCODE_XSR_ACCHI, - - OPCODE_RSR_MEMCTL, - OPCODE_WSR_MEMCTL, - OPCODE_XSR_MEMCTL, - - OPCODE_RSR_MEPC, - OPCODE_WSR_MEPC, - OPCODE_XSR_MEPC, - OPCODE_RSR_MEPS, - OPCODE_WSR_MEPS, - OPCODE_XSR_MEPS, - OPCODE_RSR_MESAVE, - OPCODE_WSR_MESAVE, - OPCODE_XSR_MESAVE, - OPCODE_RSR_MESR, - OPCODE_WSR_MESR, - OPCODE_XSR_MESR, - OPCODE_RSR_MECR, - OPCODE_WSR_MECR, - OPCODE_XSR_MECR, - OPCODE_RSR_MEVADDR, - OPCODE_WSR_MEVADDR, - OPCODE_XSR_MEVADDR, - - - OPCODE_RSR_LITBASE, - OPCODE_WSR_LITBASE, - OPCODE_XSR_LITBASE, - OPCODE_RSR_CONFIGID0, - OPCODE_WSR_CONFIGID0, - OPCODE_RSR_CONFIGID1, - OPCODE_RSR_243, - OPCODE_RSR_PS, - OPCODE_WSR_PS, - OPCODE_XSR_PS, - OPCODE_RSR_EPC1, - OPCODE_WSR_EPC1, - OPCODE_XSR_EPC1, - OPCODE_RSR_EXCSAVE1, - OPCODE_WSR_EXCSAVE1, - OPCODE_XSR_EXCSAVE1, - OPCODE_RSR_EPC2, - OPCODE_WSR_EPC2, - OPCODE_XSR_EPC2, - OPCODE_RSR_EXCSAVE2, - OPCODE_WSR_EXCSAVE2, - OPCODE_XSR_EXCSAVE2, - OPCODE_RSR_EPC3, - OPCODE_WSR_EPC3, - OPCODE_XSR_EPC3, - OPCODE_RSR_EXCSAVE3, - OPCODE_WSR_EXCSAVE3, - OPCODE_XSR_EXCSAVE3, - OPCODE_RSR_EPC4, - OPCODE_WSR_EPC4, - OPCODE_XSR_EPC4, - OPCODE_RSR_EXCSAVE4, - OPCODE_WSR_EXCSAVE4, - OPCODE_XSR_EXCSAVE4, - OPCODE_RSR_EPC5, - OPCODE_WSR_EPC5, - OPCODE_XSR_EPC5, - OPCODE_RSR_EXCSAVE5, - OPCODE_WSR_EXCSAVE5, - OPCODE_XSR_EXCSAVE5, - OPCODE_RSR_EPC6, - OPCODE_WSR_EPC6, - OPCODE_XSR_EPC6, - OPCODE_RSR_EXCSAVE6, - OPCODE_WSR_EXCSAVE6, - OPCODE_XSR_EXCSAVE6, - OPCODE_RSR_EPC7, - OPCODE_WSR_EPC7, - OPCODE_XSR_EPC7, - OPCODE_RSR_EXCSAVE7, - OPCODE_WSR_EXCSAVE7, - OPCODE_XSR_EXCSAVE7, - OPCODE_RSR_EPS2, - OPCODE_WSR_EPS2, - OPCODE_XSR_EPS2, - OPCODE_RSR_EPS3, - OPCODE_WSR_EPS3, - OPCODE_XSR_EPS3, - OPCODE_RSR_EPS4, - OPCODE_WSR_EPS4, - OPCODE_XSR_EPS4, - OPCODE_RSR_EPS5, - OPCODE_WSR_EPS5, - OPCODE_XSR_EPS5, - OPCODE_RSR_EPS6, - OPCODE_WSR_EPS6, - OPCODE_XSR_EPS6, - OPCODE_RSR_EPS7, - OPCODE_WSR_EPS7, - OPCODE_XSR_EPS7, - OPCODE_RSR_EXCVADDR, - OPCODE_WSR_EXCVADDR, - OPCODE_XSR_EXCVADDR, - OPCODE_RSR_DEPC, - OPCODE_WSR_DEPC, - OPCODE_XSR_DEPC, - OPCODE_RSR_EXCCAUSE, - OPCODE_WSR_EXCCAUSE, - OPCODE_XSR_EXCCAUSE, - OPCODE_RSR_MISC0, - OPCODE_WSR_MISC0, - OPCODE_XSR_MISC0, - OPCODE_RSR_MISC1, - OPCODE_WSR_MISC1, - OPCODE_XSR_MISC1, - OPCODE_RSR_PRID, - OPCODE_RSR_VECBASE, - OPCODE_WSR_VECBASE, - OPCODE_XSR_VECBASE, - OPCODE_MUL16U, - OPCODE_MUL16S, - OPCODE_MULL, - OPCODE_RFI, - OPCODE_WAITI, - OPCODE_RSR_INTERRUPT, - OPCODE_WSR_INTSET, - OPCODE_WSR_INTCLEAR, - OPCODE_RSR_INTENABLE, - OPCODE_WSR_INTENABLE, - OPCODE_XSR_INTENABLE, - OPCODE_BREAK, - OPCODE_BREAK_N, - OPCODE_RSR_DBREAKA0, - OPCODE_WSR_DBREAKA0, - OPCODE_XSR_DBREAKA0, - OPCODE_RSR_DBREAKC0, - OPCODE_WSR_DBREAKC0, - OPCODE_XSR_DBREAKC0, - OPCODE_RSR_DBREAKA1, - OPCODE_WSR_DBREAKA1, - OPCODE_XSR_DBREAKA1, - OPCODE_RSR_DBREAKC1, - OPCODE_WSR_DBREAKC1, - OPCODE_XSR_DBREAKC1, - OPCODE_RSR_IBREAKA0, - OPCODE_WSR_IBREAKA0, - OPCODE_XSR_IBREAKA0, - OPCODE_RSR_IBREAKA1, - OPCODE_WSR_IBREAKA1, - OPCODE_XSR_IBREAKA1, - OPCODE_RSR_IBREAKENABLE, - OPCODE_WSR_IBREAKENABLE, - OPCODE_XSR_IBREAKENABLE, - OPCODE_RSR_DEBUGCAUSE, - OPCODE_WSR_DEBUGCAUSE, - OPCODE_XSR_DEBUGCAUSE, - OPCODE_RSR_ICOUNT, - OPCODE_WSR_ICOUNT, - OPCODE_XSR_ICOUNT, - OPCODE_RSR_ICOUNTLEVEL, - OPCODE_WSR_ICOUNTLEVEL, - OPCODE_XSR_ICOUNTLEVEL, - OPCODE_RSR_DDR, - OPCODE_WSR_DDR, - OPCODE_XSR_DDR, - OPCODE_LDDR32_P, - OPCODE_SDDR32_P, - OPCODE_RFDO, - OPCODE_RFDD, - OPCODE_WSR_MMID, - OPCODE_ANDB, - OPCODE_ANDBC, - OPCODE_ORB, - OPCODE_ORBC, - OPCODE_XORB, - OPCODE_ANY4, - OPCODE_ALL4, - OPCODE_ANY8, - OPCODE_ALL8, - OPCODE_BF, - OPCODE_BT, - OPCODE_MOVF, - OPCODE_MOVT, - OPCODE_RSR_BR, - OPCODE_WSR_BR, - OPCODE_XSR_BR, - OPCODE_RSR_CCOUNT, - OPCODE_WSR_CCOUNT, - OPCODE_XSR_CCOUNT, - OPCODE_RSR_CCOMPARE0, - OPCODE_WSR_CCOMPARE0, - OPCODE_XSR_CCOMPARE0, - OPCODE_RSR_CCOMPARE1, - OPCODE_WSR_CCOMPARE1, - OPCODE_XSR_CCOMPARE1, - OPCODE_RSR_CCOMPARE2, - OPCODE_WSR_CCOMPARE2, - OPCODE_XSR_CCOMPARE2, - OPCODE_IPF, - OPCODE_IHI, - OPCODE_IPFL, - OPCODE_IHU, - OPCODE_IIU, - OPCODE_III, - OPCODE_LICT, - OPCODE_LICW, - OPCODE_SICT, - OPCODE_SICW, - OPCODE_DHWB, - OPCODE_DHWBI, - OPCODE_DIWBUI_P, - OPCODE_DIWB, - OPCODE_DIWBI, - OPCODE_DHI, - OPCODE_DII, - OPCODE_DPFR, - OPCODE_DPFW, - OPCODE_DPFRO, - OPCODE_DPFWO, - OPCODE_DPFL, - OPCODE_DHU, - OPCODE_DIU, - OPCODE_SDCT, - OPCODE_LDCT, - OPCODE_RSR_PREFCTL, - OPCODE_WSR_PREFCTL, - OPCODE_XSR_PREFCTL, - OPCODE_IDTLB, - OPCODE_PDTLB, - OPCODE_RDTLB0, - OPCODE_RDTLB1, - OPCODE_WDTLB, - OPCODE_IITLB, - OPCODE_PITLB, - OPCODE_RITLB0, - OPCODE_RITLB1, - OPCODE_WITLB, - OPCODE_RSR_CPENABLE, - OPCODE_WSR_CPENABLE, - OPCODE_XSR_CPENABLE, - OPCODE_CLAMPS, - OPCODE_MIN, - OPCODE_MAX, - OPCODE_MINU, - OPCODE_MAXU, - OPCODE_NSA, - OPCODE_NSAU, - OPCODE_SEXT, - OPCODE_L32AI, - OPCODE_S32RI, - OPCODE_S32C1I, - OPCODE_RSR_SCOMPARE1, - OPCODE_WSR_SCOMPARE1, - OPCODE_XSR_SCOMPARE1, - OPCODE_RSR_ATOMCTL, - OPCODE_WSR_ATOMCTL, - OPCODE_XSR_ATOMCTL, - OPCODE_QUOU, - OPCODE_QUOS, - OPCODE_REMU, - OPCODE_REMS, - OPCODE_RER, - OPCODE_WER, - OPCODE_RUR_AE_OVF_SAR, - OPCODE_WUR_AE_OVF_SAR, - OPCODE_RUR_AE_BITHEAD, - OPCODE_WUR_AE_BITHEAD, - OPCODE_RUR_AE_TS_FTS_BU_BP, - OPCODE_WUR_AE_TS_FTS_BU_BP, - OPCODE_RUR_AE_SD_NO, - OPCODE_WUR_AE_SD_NO, - OPCODE_RUR_AE_OVERFLOW, - OPCODE_WUR_AE_OVERFLOW, - OPCODE_RUR_AE_SAR, - OPCODE_WUR_AE_SAR, - OPCODE_RUR_AE_BITPTR, - OPCODE_WUR_AE_BITPTR, - OPCODE_RUR_AE_BITSUSED, - OPCODE_WUR_AE_BITSUSED, - OPCODE_RUR_AE_TABLESIZE, - OPCODE_WUR_AE_TABLESIZE, - OPCODE_RUR_AE_FIRST_TS, - OPCODE_WUR_AE_FIRST_TS, - OPCODE_RUR_AE_NEXTOFFSET, - OPCODE_WUR_AE_NEXTOFFSET, - OPCODE_RUR_AE_SEARCHDONE, - OPCODE_WUR_AE_SEARCHDONE, - OPCODE_RUR_THREADPTR, - OPCODE_WUR_THREADPTR, - OPCODE_AE_LP16F_I, - OPCODE_AE_LP16F_IU, - OPCODE_AE_LP16F_X, - OPCODE_AE_LP16F_XU, - OPCODE_AE_LP24_I, - OPCODE_AE_LP24_IU, - OPCODE_AE_LP24_X, - OPCODE_AE_LP24_XU, - OPCODE_AE_LP24F_I, - OPCODE_AE_LP24F_IU, - OPCODE_AE_LP24F_X, - OPCODE_AE_LP24F_XU, - OPCODE_AE_LP16X2F_I, - OPCODE_AE_LP16X2F_IU, - OPCODE_AE_LP16X2F_X, - OPCODE_AE_LP16X2F_XU, - OPCODE_AE_LP24X2F_I, - OPCODE_AE_LP24X2F_IU, - OPCODE_AE_LP24X2F_X, - OPCODE_AE_LP24X2F_XU, - OPCODE_AE_LP24X2_I, - OPCODE_AE_LP24X2_IU, - OPCODE_AE_LP24X2_X, - OPCODE_AE_LP24X2_XU, - OPCODE_AE_SP16X2F_I, - OPCODE_AE_SP16X2F_IU, - OPCODE_AE_SP16X2F_X, - OPCODE_AE_SP16X2F_XU, - OPCODE_AE_SP24X2S_I, - OPCODE_AE_SP24X2S_IU, - OPCODE_AE_SP24X2S_X, - OPCODE_AE_SP24X2S_XU, - OPCODE_AE_SP24X2F_I, - OPCODE_AE_SP24X2F_IU, - OPCODE_AE_SP24X2F_X, - OPCODE_AE_SP24X2F_XU, - OPCODE_AE_SP16F_L_I, - OPCODE_AE_SP16F_L_IU, - OPCODE_AE_SP16F_L_X, - OPCODE_AE_SP16F_L_XU, - OPCODE_AE_SP24S_L_I, - OPCODE_AE_SP24S_L_IU, - OPCODE_AE_SP24S_L_X, - OPCODE_AE_SP24S_L_XU, - OPCODE_AE_SP24F_L_I, - OPCODE_AE_SP24F_L_IU, - OPCODE_AE_SP24F_L_X, - OPCODE_AE_SP24F_L_XU, - OPCODE_AE_LQ56_I, - OPCODE_AE_LQ56_IU, - OPCODE_AE_LQ56_X, - OPCODE_AE_LQ56_XU, - OPCODE_AE_LQ32F_I, - OPCODE_AE_LQ32F_IU, - OPCODE_AE_LQ32F_X, - OPCODE_AE_LQ32F_XU, - OPCODE_AE_SQ56S_I, - OPCODE_AE_SQ56S_IU, - OPCODE_AE_SQ56S_X, - OPCODE_AE_SQ56S_XU, - OPCODE_AE_SQ32F_I, - OPCODE_AE_SQ32F_IU, - OPCODE_AE_SQ32F_X, - OPCODE_AE_SQ32F_XU, - OPCODE_AE_ZEROP48, - OPCODE_AE_MOVP48, - OPCODE_AE_SELP24_LL, - OPCODE_AE_SELP24_LH, - OPCODE_AE_SELP24_HL, - OPCODE_AE_SELP24_HH, - OPCODE_AE_MOVTP24X2, - OPCODE_AE_MOVFP24X2, - OPCODE_AE_MOVTP48, - OPCODE_AE_MOVFP48, - OPCODE_AE_MOVPA24X2, - OPCODE_AE_TRUNCP24A32X2, - OPCODE_AE_CVTA32P24_L, - OPCODE_AE_CVTA32P24_H, - OPCODE_AE_CVTP24A16X2_LL, - OPCODE_AE_CVTP24A16X2_LH, - OPCODE_AE_CVTP24A16X2_HL, - OPCODE_AE_CVTP24A16X2_HH, - OPCODE_AE_TRUNCP24Q48X2, - OPCODE_AE_TRUNCP16, - OPCODE_AE_ROUNDSP24Q48SYM, - OPCODE_AE_ROUNDSP24Q48ASYM, - OPCODE_AE_ROUNDSP16Q48SYM, - OPCODE_AE_ROUNDSP16Q48ASYM, - OPCODE_AE_ROUNDSP16SYM, - OPCODE_AE_ROUNDSP16ASYM, - OPCODE_AE_ZEROQ56, - OPCODE_AE_MOVQ56, - OPCODE_AE_MOVTQ56, - OPCODE_AE_MOVFQ56, - OPCODE_AE_CVTQ48A32S, - OPCODE_AE_CVTQ48P24S_L, - OPCODE_AE_CVTQ48P24S_H, - OPCODE_AE_SATQ48S, - OPCODE_AE_TRUNCQ32, - OPCODE_AE_ROUNDSQ32SYM, - OPCODE_AE_ROUNDSQ32ASYM, - OPCODE_AE_TRUNCA32Q48, - OPCODE_AE_MOVAP24S_L, - OPCODE_AE_MOVAP24S_H, - OPCODE_AE_TRUNCA16P24S_L, - OPCODE_AE_TRUNCA16P24S_H, - OPCODE_AE_ADDP24, - OPCODE_AE_SUBP24, - OPCODE_AE_NEGP24, - OPCODE_AE_ABSP24, - OPCODE_AE_MAXP24S, - OPCODE_AE_MINP24S, - OPCODE_AE_MAXBP24S, - OPCODE_AE_MINBP24S, - OPCODE_AE_ADDSP24S, - OPCODE_AE_SUBSP24S, - OPCODE_AE_NEGSP24S, - OPCODE_AE_ABSSP24S, - OPCODE_AE_ANDP48, - OPCODE_AE_NANDP48, - OPCODE_AE_ORP48, - OPCODE_AE_XORP48, - OPCODE_AE_LTP24S, - OPCODE_AE_LEP24S, - OPCODE_AE_EQP24, - OPCODE_AE_ADDQ56, - OPCODE_AE_SUBQ56, - OPCODE_AE_NEGQ56, - OPCODE_AE_ABSQ56, - OPCODE_AE_MAXQ56S, - OPCODE_AE_MINQ56S, - OPCODE_AE_MAXBQ56S, - OPCODE_AE_MINBQ56S, - OPCODE_AE_ADDSQ56S, - OPCODE_AE_SUBSQ56S, - OPCODE_AE_NEGSQ56S, - OPCODE_AE_ABSSQ56S, - OPCODE_AE_ANDQ56, - OPCODE_AE_NANDQ56, - OPCODE_AE_ORQ56, - OPCODE_AE_XORQ56, - OPCODE_AE_SLLIP24, - OPCODE_AE_SRLIP24, - OPCODE_AE_SRAIP24, - OPCODE_AE_SLLSP24, - OPCODE_AE_SRLSP24, - OPCODE_AE_SRASP24, - OPCODE_AE_SLLISP24S, - OPCODE_AE_SLLSSP24S, - OPCODE_AE_SLLIQ56, - OPCODE_AE_SRLIQ56, - OPCODE_AE_SRAIQ56, - OPCODE_AE_SLLSQ56, - OPCODE_AE_SRLSQ56, - OPCODE_AE_SRASQ56, - OPCODE_AE_SLLAQ56, - OPCODE_AE_SRLAQ56, - OPCODE_AE_SRAAQ56, - OPCODE_AE_SLLISQ56S, - OPCODE_AE_SLLSSQ56S, - OPCODE_AE_SLLASQ56S, - OPCODE_AE_LTQ56S, - OPCODE_AE_LEQ56S, - OPCODE_AE_EQQ56, - OPCODE_AE_NSAQ56S, - OPCODE_AE_MULSRFQ32SP24S_H, - OPCODE_AE_MULSRFQ32SP24S_L, - OPCODE_AE_MULARFQ32SP24S_H, - OPCODE_AE_MULARFQ32SP24S_L, - OPCODE_AE_MULRFQ32SP24S_H, - OPCODE_AE_MULRFQ32SP24S_L, - OPCODE_AE_MULSFQ32SP24S_H, - OPCODE_AE_MULSFQ32SP24S_L, - OPCODE_AE_MULAFQ32SP24S_H, - OPCODE_AE_MULAFQ32SP24S_L, - OPCODE_AE_MULFQ32SP24S_H, - OPCODE_AE_MULFQ32SP24S_L, - OPCODE_AE_MULFS32P16S_LL, - OPCODE_AE_MULFP24S_LL, - OPCODE_AE_MULP24S_LL, - OPCODE_AE_MULFS32P16S_LH, - OPCODE_AE_MULFP24S_LH, - OPCODE_AE_MULP24S_LH, - OPCODE_AE_MULFS32P16S_HL, - OPCODE_AE_MULFP24S_HL, - OPCODE_AE_MULP24S_HL, - OPCODE_AE_MULFS32P16S_HH, - OPCODE_AE_MULFP24S_HH, - OPCODE_AE_MULP24S_HH, - OPCODE_AE_MULAFS32P16S_LL, - OPCODE_AE_MULAFP24S_LL, - OPCODE_AE_MULAP24S_LL, - OPCODE_AE_MULAFS32P16S_LH, - OPCODE_AE_MULAFP24S_LH, - OPCODE_AE_MULAP24S_LH, - OPCODE_AE_MULAFS32P16S_HL, - OPCODE_AE_MULAFP24S_HL, - OPCODE_AE_MULAP24S_HL, - OPCODE_AE_MULAFS32P16S_HH, - OPCODE_AE_MULAFP24S_HH, - OPCODE_AE_MULAP24S_HH, - OPCODE_AE_MULSFS32P16S_LL, - OPCODE_AE_MULSFP24S_LL, - OPCODE_AE_MULSP24S_LL, - OPCODE_AE_MULSFS32P16S_LH, - OPCODE_AE_MULSFP24S_LH, - OPCODE_AE_MULSP24S_LH, - OPCODE_AE_MULSFS32P16S_HL, - OPCODE_AE_MULSFP24S_HL, - OPCODE_AE_MULSP24S_HL, - OPCODE_AE_MULSFS32P16S_HH, - OPCODE_AE_MULSFP24S_HH, - OPCODE_AE_MULSP24S_HH, - OPCODE_AE_MULAFS56P24S_LL, - OPCODE_AE_MULAS56P24S_LL, - OPCODE_AE_MULAFS56P24S_LH, - OPCODE_AE_MULAS56P24S_LH, - OPCODE_AE_MULAFS56P24S_HL, - OPCODE_AE_MULAS56P24S_HL, - OPCODE_AE_MULAFS56P24S_HH, - OPCODE_AE_MULAS56P24S_HH, - OPCODE_AE_MULSFS56P24S_LL, - OPCODE_AE_MULSS56P24S_LL, - OPCODE_AE_MULSFS56P24S_LH, - OPCODE_AE_MULSS56P24S_LH, - OPCODE_AE_MULSFS56P24S_HL, - OPCODE_AE_MULSS56P24S_HL, - OPCODE_AE_MULSFS56P24S_HH, - OPCODE_AE_MULSS56P24S_HH, - OPCODE_AE_MULFQ32SP16S_L, - OPCODE_AE_MULFQ32SP16S_H, - OPCODE_AE_MULFQ32SP16U_L, - OPCODE_AE_MULFQ32SP16U_H, - OPCODE_AE_MULQ32SP16S_L, - OPCODE_AE_MULQ32SP16S_H, - OPCODE_AE_MULQ32SP16U_L, - OPCODE_AE_MULQ32SP16U_H, - OPCODE_AE_MULAFQ32SP16S_L, - OPCODE_AE_MULAFQ32SP16S_H, - OPCODE_AE_MULAFQ32SP16U_L, - OPCODE_AE_MULAFQ32SP16U_H, - OPCODE_AE_MULAQ32SP16S_L, - OPCODE_AE_MULAQ32SP16S_H, - OPCODE_AE_MULAQ32SP16U_L, - OPCODE_AE_MULAQ32SP16U_H, - OPCODE_AE_MULSFQ32SP16S_L, - OPCODE_AE_MULSFQ32SP16S_H, - OPCODE_AE_MULSFQ32SP16U_L, - OPCODE_AE_MULSFQ32SP16U_H, - OPCODE_AE_MULSQ32SP16S_L, - OPCODE_AE_MULSQ32SP16S_H, - OPCODE_AE_MULSQ32SP16U_L, - OPCODE_AE_MULSQ32SP16U_H, - OPCODE_AE_MULZAAQ32SP16S_LL, - OPCODE_AE_MULZAAFQ32SP16S_LL, - OPCODE_AE_MULZAAQ32SP16U_LL, - OPCODE_AE_MULZAAFQ32SP16U_LL, - OPCODE_AE_MULZAAQ32SP16S_HH, - OPCODE_AE_MULZAAFQ32SP16S_HH, - OPCODE_AE_MULZAAQ32SP16U_HH, - OPCODE_AE_MULZAAFQ32SP16U_HH, - OPCODE_AE_MULZAAQ32SP16S_LH, - OPCODE_AE_MULZAAFQ32SP16S_LH, - OPCODE_AE_MULZAAQ32SP16U_LH, - OPCODE_AE_MULZAAFQ32SP16U_LH, - OPCODE_AE_MULZASQ32SP16S_LL, - OPCODE_AE_MULZASFQ32SP16S_LL, - OPCODE_AE_MULZASQ32SP16U_LL, - OPCODE_AE_MULZASFQ32SP16U_LL, - OPCODE_AE_MULZASQ32SP16S_HH, - OPCODE_AE_MULZASFQ32SP16S_HH, - OPCODE_AE_MULZASQ32SP16U_HH, - OPCODE_AE_MULZASFQ32SP16U_HH, - OPCODE_AE_MULZASQ32SP16S_LH, - OPCODE_AE_MULZASFQ32SP16S_LH, - OPCODE_AE_MULZASQ32SP16U_LH, - OPCODE_AE_MULZASFQ32SP16U_LH, - OPCODE_AE_MULZSAQ32SP16S_LL, - OPCODE_AE_MULZSAFQ32SP16S_LL, - OPCODE_AE_MULZSAQ32SP16U_LL, - OPCODE_AE_MULZSAFQ32SP16U_LL, - OPCODE_AE_MULZSAQ32SP16S_HH, - OPCODE_AE_MULZSAFQ32SP16S_HH, - OPCODE_AE_MULZSAQ32SP16U_HH, - OPCODE_AE_MULZSAFQ32SP16U_HH, - OPCODE_AE_MULZSAQ32SP16S_LH, - OPCODE_AE_MULZSAFQ32SP16S_LH, - OPCODE_AE_MULZSAQ32SP16U_LH, - OPCODE_AE_MULZSAFQ32SP16U_LH, - OPCODE_AE_MULZSSQ32SP16S_LL, - OPCODE_AE_MULZSSFQ32SP16S_LL, - OPCODE_AE_MULZSSQ32SP16U_LL, - OPCODE_AE_MULZSSFQ32SP16U_LL, - OPCODE_AE_MULZSSQ32SP16S_HH, - OPCODE_AE_MULZSSFQ32SP16S_HH, - OPCODE_AE_MULZSSQ32SP16U_HH, - OPCODE_AE_MULZSSFQ32SP16U_HH, - OPCODE_AE_MULZSSQ32SP16S_LH, - OPCODE_AE_MULZSSFQ32SP16S_LH, - OPCODE_AE_MULZSSQ32SP16U_LH, - OPCODE_AE_MULZSSFQ32SP16U_LH, - OPCODE_AE_MULZAAFP24S_HH_LL, - OPCODE_AE_MULZAAP24S_HH_LL, - OPCODE_AE_MULZAAFP24S_HL_LH, - OPCODE_AE_MULZAAP24S_HL_LH, - OPCODE_AE_MULZASFP24S_HH_LL, - OPCODE_AE_MULZASP24S_HH_LL, - OPCODE_AE_MULZASFP24S_HL_LH, - OPCODE_AE_MULZASP24S_HL_LH, - OPCODE_AE_MULZSAFP24S_HH_LL, - OPCODE_AE_MULZSAP24S_HH_LL, - OPCODE_AE_MULZSAFP24S_HL_LH, - OPCODE_AE_MULZSAP24S_HL_LH, - OPCODE_AE_MULZSSFP24S_HH_LL, - OPCODE_AE_MULZSSP24S_HH_LL, - OPCODE_AE_MULZSSFP24S_HL_LH, - OPCODE_AE_MULZSSP24S_HL_LH, - OPCODE_AE_MULAAFP24S_HH_LL, - OPCODE_AE_MULAAP24S_HH_LL, - OPCODE_AE_MULAAFP24S_HL_LH, - OPCODE_AE_MULAAP24S_HL_LH, - OPCODE_AE_MULASFP24S_HH_LL, - OPCODE_AE_MULASP24S_HH_LL, - OPCODE_AE_MULASFP24S_HL_LH, - OPCODE_AE_MULASP24S_HL_LH, - OPCODE_AE_MULSAFP24S_HH_LL, - OPCODE_AE_MULSAP24S_HH_LL, - OPCODE_AE_MULSAFP24S_HL_LH, - OPCODE_AE_MULSAP24S_HL_LH, - OPCODE_AE_MULSSFP24S_HH_LL, - OPCODE_AE_MULSSP24S_HH_LL, - OPCODE_AE_MULSSFP24S_HL_LH, - OPCODE_AE_MULSSP24S_HL_LH, - OPCODE_AE_SHA32, - OPCODE_AE_VLDL32T, - OPCODE_AE_VLDL16T, - OPCODE_AE_VLDL16C, - OPCODE_AE_VLDSHT, - OPCODE_AE_LB, - OPCODE_AE_LBI, - OPCODE_AE_LBK, - OPCODE_AE_LBKI, - OPCODE_AE_DB, - OPCODE_AE_DBI, - OPCODE_AE_VLEL32T, - OPCODE_AE_VLEL16T, - OPCODE_AE_SB, - OPCODE_AE_SBI, - OPCODE_AE_VLES16C, - OPCODE_AE_SBF, - OPCODE_AE_SLAASQ56S, - OPCODE_AE_ADDBRBA32, - OPCODE_AE_MINABSSP24S, - OPCODE_AE_MAXABSSP24S, - OPCODE_AE_MINABSSQ56S, - OPCODE_AE_MAXABSSQ56S, - OPCODE_RUR_AE_CBEGIN0, - OPCODE_WUR_AE_CBEGIN0, - OPCODE_RUR_AE_CEND0, - OPCODE_WUR_AE_CEND0, - OPCODE_AE_LP24X2_C, - OPCODE_AE_SP24X2S_C, - OPCODE_AE_LP24X2F_C, - OPCODE_AE_SP24X2F_C, - OPCODE_AE_LP16X2F_C, - OPCODE_AE_SP16X2F_C, - OPCODE_AE_LP24_C, - OPCODE_AE_SP24S_L_C, - OPCODE_AE_LP24F_C, - OPCODE_AE_SP24F_L_C, - OPCODE_AE_LP16F_C, - OPCODE_AE_SP16F_L_C, - OPCODE_AE_LQ56_C, - OPCODE_AE_SQ56S_C, - OPCODE_AE_LQ32F_C, - OPCODE_AE_SQ32F_C, - OPCODE_READ_IPQ, - OPCODE_CHECK_IPQ, - OPCODE_WRITE_OPQ, - OPCODE_CHECK_OPQ, - OPCODE_RUR_EXPSTATE, - OPCODE_WUR_EXPSTATE, - OPCODE_READ_IMPWIRE, - OPCODE_SETB_EXPSTATE, - OPCODE_CLRB_EXPSTATE, - OPCODE_WRMSK_EXPSTATE -}; - - -/* Slot-specific opcode decode functions. */ - -static int -Slot_inst_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst_get (insn) == 0) - { - if (Field_op1_Slot_inst_get (insn) == 0) - { - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_r_Slot_inst_get (insn) == 0) - { - if (Field_m_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_n_Slot_inst_get (insn) == 0) - return OPCODE_ILL; - if (Field_m_Slot_inst_get (insn) == 2) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_RET; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_RETW; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_JX; - } - if (Field_m_Slot_inst_get (insn) == 3) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_CALLX0; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_CALLX4; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_CALLX8; - if (Field_n_Slot_inst_get (insn) == 3) - return OPCODE_CALLX12; - } - } - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_MOVSP; - if (Field_r_Slot_inst_get (insn) == 2) - { - if (Field_s_Slot_inst_get (insn) == 0) - { - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_ISYNC; - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RSYNC; - if (Field_t_Slot_inst_get (insn) == 2) - return OPCODE_ESYNC; - if (Field_t_Slot_inst_get (insn) == 3) - return OPCODE_DSYNC; - if (Field_t_Slot_inst_get (insn) == 8) - return OPCODE_EXCW; - if (Field_t_Slot_inst_get (insn) == 12) - return OPCODE_MEMW; - if (Field_t_Slot_inst_get (insn) == 13) - return OPCODE_EXTW; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_NOP; - } - } - if (Field_r_Slot_inst_get (insn) == 3) - { - if (Field_t_Slot_inst_get (insn) == 0) - { - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_RFE; - if (Field_s_Slot_inst_get (insn) == 2) - return OPCODE_RFDE; - if (Field_s_Slot_inst_get (insn) == 4) - return OPCODE_RFWO; - if (Field_s_Slot_inst_get (insn) == 5) - return OPCODE_RFWU; - } - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFI; - if (Field_t_Slot_inst_get (insn) == 2) - return OPCODE_RFME; - } - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_BREAK; - if (Field_r_Slot_inst_get (insn) == 5) - { - if (Field_s_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SYSCALL; - if (Field_s_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SIMCALL; - } - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_RSIL; - if (Field_r_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_WAITI; - if (Field_r_Slot_inst_get (insn) == 7) - { - if (Field_t_Slot_inst_get (insn) == 14) - return OPCODE_LDDR32_P; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_SDDR32_P; - } - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_ANY4; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_ALL4; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_ANY8; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_ALL8; - } - if (Field_op2_Slot_inst_get (insn) == 1) - return OPCODE_AND; - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_OR; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_XOR; - if (Field_op2_Slot_inst_get (insn) == 4) - { - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSR; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSL; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8L; - if (Field_r_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8B; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_thi3_Slot_inst_get (insn) == 0) - return OPCODE_SSAI; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_RER; - if (Field_r_Slot_inst_get (insn) == 7) - return OPCODE_WER; - if (Field_r_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_ROTW; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_NSA; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_NSAU; - } - if (Field_op2_Slot_inst_get (insn) == 5) - { - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_RITLB0; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IITLB; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_PITLB; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_WITLB; - if (Field_r_Slot_inst_get (insn) == 7) - return OPCODE_RITLB1; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_RDTLB0; - if (Field_r_Slot_inst_get (insn) == 12 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IDTLB; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_PDTLB; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_WDTLB; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_RDTLB1; - } - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_NEG; - if (Field_s_Slot_inst_get (insn) == 1) - return OPCODE_ABS; - } - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_ADD; - if (Field_op2_Slot_inst_get (insn) == 9) - return OPCODE_ADDX2; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_ADDX4; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_ADDX8; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_SUB; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_SUBX2; - if (Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_SUBX4; - if (Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_SUBX8; - } - if (Field_op1_Slot_inst_get (insn) == 1) - { - if ((Field_op2_Slot_inst_get (insn) == 0 || - Field_op2_Slot_inst_get (insn) == 1)) - return OPCODE_SLLI; - if ((Field_op2_Slot_inst_get (insn) == 2 || - Field_op2_Slot_inst_get (insn) == 3)) - return OPCODE_SRAI; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_SRLI; - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_XSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_XSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_XSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_XSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_XSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_XSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_XSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_XSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_XSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 40) - return OPCODE_XSR_PREFCTL; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_XSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_XSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_XSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 97) - return OPCODE_XSR_MEMCTL; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_XSR_ATOMCTL; - - if (Field_sr_Slot_inst_get (insn) == 106) - return OPCODE_XSR_MEPC; - if (Field_sr_Slot_inst_get (insn) == 107) - return OPCODE_XSR_MEPS; - if (Field_sr_Slot_inst_get (insn) == 108) - return OPCODE_XSR_MESAVE; - if (Field_sr_Slot_inst_get (insn) == 109) - return OPCODE_XSR_MESR; - if (Field_sr_Slot_inst_get (insn) == 110) - return OPCODE_XSR_MECR; - if (Field_sr_Slot_inst_get (insn) == 111) - return OPCODE_XSR_MEVADDR; - - - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_XSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_XSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_XSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_XSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_XSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_XSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_XSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_XSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_XSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_XSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_XSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_XSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_XSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_XSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_XSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_XSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_XSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_XSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_XSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_XSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_XSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_XSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_XSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_XSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_XSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_XSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_XSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_XSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_XSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_XSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_XSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_XSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_XSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_XSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_XSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_XSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_XSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_XSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_XSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_XSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_XSR_CCOMPARE2; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_XSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_XSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_SRC; - if (Field_op2_Slot_inst_get (insn) == 9 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRL; - if (Field_op2_Slot_inst_get (insn) == 10 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SLL; - if (Field_op2_Slot_inst_get (insn) == 11 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRA; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_MUL16U; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_MUL16S; - if (Field_op2_Slot_inst_get (insn) == 15) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_LICT; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_SICT; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_LICW; - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_SICW; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_LDCT; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_SDCT; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_RFDO; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFDD; - } - } - if (Field_op1_Slot_inst_get (insn) == 2) - { - if (Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_ANDB; - if (Field_op2_Slot_inst_get (insn) == 1) - return OPCODE_ANDBC; - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_ORB; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_ORBC; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_XORB; - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_MULL; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_QUOU; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_QUOS; - if (Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_REMU; - if (Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_REMS; - } - if (Field_op1_Slot_inst_get (insn) == 3) - { - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_RSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_RSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_RSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_RSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_RSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_RSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_RSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_RSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_RSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 40) - return OPCODE_RSR_PREFCTL; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_RSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_RSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_RSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 97) - return OPCODE_RSR_MEMCTL; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_RSR_ATOMCTL; - - if (Field_sr_Slot_inst_get (insn) == 106) - return OPCODE_RSR_MEPC; - if (Field_sr_Slot_inst_get (insn) == 107) - return OPCODE_RSR_MEPS; - if (Field_sr_Slot_inst_get (insn) == 108) - return OPCODE_RSR_MESAVE; - if (Field_sr_Slot_inst_get (insn) == 109) - return OPCODE_RSR_MESR; - if (Field_sr_Slot_inst_get (insn) == 110) - return OPCODE_RSR_MECR; - if (Field_sr_Slot_inst_get (insn) == 111) - return OPCODE_RSR_MEVADDR; - - - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_RSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_RSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_RSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_RSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_RSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_RSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_RSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 176) - return OPCODE_RSR_CONFIGID0; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_RSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_RSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_RSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_RSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_RSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_RSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_RSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_RSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_RSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_RSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_RSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_RSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_RSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_RSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 208) - return OPCODE_RSR_CONFIGID1; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_RSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_RSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_RSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_RSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_RSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_RSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_RSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_RSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 226) - return OPCODE_RSR_INTERRUPT; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_RSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_RSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_RSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_RSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_RSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_RSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 235) - return OPCODE_RSR_PRID; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_RSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_RSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_RSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_RSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_RSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_RSR_CCOMPARE2; - if (Field_sr_Slot_inst_get (insn) == 243) - return OPCODE_RSR_243; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_RSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_RSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 1) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_WSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_WSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_WSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_WSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_WSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_WSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_WSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_WSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_WSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 40) - return OPCODE_WSR_PREFCTL; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_WSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_WSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 89) - return OPCODE_WSR_MMID; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_WSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 97) - return OPCODE_WSR_MEMCTL; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_WSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 106) - return OPCODE_WSR_MEPC; - if (Field_sr_Slot_inst_get (insn) == 107) - return OPCODE_WSR_MEPS; - if (Field_sr_Slot_inst_get (insn) == 108) - return OPCODE_WSR_MESAVE; - if (Field_sr_Slot_inst_get (insn) == 109) - return OPCODE_WSR_MESR; - if (Field_sr_Slot_inst_get (insn) == 110) - return OPCODE_WSR_MECR; - if (Field_sr_Slot_inst_get (insn) == 111) - return OPCODE_WSR_MEVADDR; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_WSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_WSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_WSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_WSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_WSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_WSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_WSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 176) - return OPCODE_WSR_CONFIGID0; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_WSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_WSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_WSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_WSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_WSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_WSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_WSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_WSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_WSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_WSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_WSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_WSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_WSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_WSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_WSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_WSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_WSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_WSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_WSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_WSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_WSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_WSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 226) - return OPCODE_WSR_INTSET; - if (Field_sr_Slot_inst_get (insn) == 227) - return OPCODE_WSR_INTCLEAR; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_WSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_WSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_WSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_WSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_WSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_WSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_WSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_WSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_WSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_WSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_WSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_WSR_CCOMPARE2; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_WSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_WSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_SEXT; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_CLAMPS; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_MIN; - if (Field_op2_Slot_inst_get (insn) == 5) - return OPCODE_MAX; - if (Field_op2_Slot_inst_get (insn) == 6) - return OPCODE_MINU; - if (Field_op2_Slot_inst_get (insn) == 7) - return OPCODE_MAXU; - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_MOVEQZ; - if (Field_op2_Slot_inst_get (insn) == 9) - return OPCODE_MOVNEZ; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_MOVLTZ; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_MOVGEZ; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_MOVF; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_MOVT; - if (Field_op2_Slot_inst_get (insn) == 14) - { - if (Field_st_Slot_inst_get (insn) == 230) - return OPCODE_RUR_EXPSTATE; - if (Field_st_Slot_inst_get (insn) == 231) - return OPCODE_RUR_THREADPTR; - if (Field_st_Slot_inst_get (insn) == 240) - return OPCODE_RUR_AE_OVF_SAR; - if (Field_st_Slot_inst_get (insn) == 241) - return OPCODE_RUR_AE_BITHEAD; - if (Field_st_Slot_inst_get (insn) == 242) - return OPCODE_RUR_AE_TS_FTS_BU_BP; - if (Field_st_Slot_inst_get (insn) == 243) - return OPCODE_RUR_AE_SD_NO; - if (Field_st_Slot_inst_get (insn) == 246) - return OPCODE_RUR_AE_CBEGIN0; - if (Field_st_Slot_inst_get (insn) == 247) - return OPCODE_RUR_AE_CEND0; - } - if (Field_op2_Slot_inst_get (insn) == 15) - { - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_WUR_EXPSTATE; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_WUR_THREADPTR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_WUR_AE_OVF_SAR; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_WUR_AE_BITHEAD; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_WUR_AE_TS_FTS_BU_BP; - if (Field_sr_Slot_inst_get (insn) == 243) - return OPCODE_WUR_AE_SD_NO; - if (Field_sr_Slot_inst_get (insn) == 246) - return OPCODE_WUR_AE_CBEGIN0; - if (Field_sr_Slot_inst_get (insn) == 247) - return OPCODE_WUR_AE_CEND0; - } - } - if ((Field_op1_Slot_inst_get (insn) == 4 || - Field_op1_Slot_inst_get (insn) == 5)) - return OPCODE_EXTUI; - if (Field_op1_Slot_inst_get (insn) == 9) - { - if (Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_L32E; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_S32E; - if (Field_op2_Slot_inst_get (insn) == 5) - return OPCODE_S32NB; - } - if (Field_r_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_READ_IMPWIRE; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_s3to1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_SETB_EXPSTATE; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_s3to1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_CLRB_EXPSTATE; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_WRMSK_EXPSTATE; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_READ_IPQ; - if (Field_r_Slot_inst_get (insn) == 5 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_CHECK_IPQ; - if (Field_r_Slot_inst_get (insn) == 6 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_WRITE_OPQ; - if (Field_r_Slot_inst_get (insn) == 7 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_CHECK_OPQ; - } - if (Field_op0_Slot_inst_get (insn) == 1) - return OPCODE_L32R; - if (Field_op0_Slot_inst_get (insn) == 2) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_L8UI; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_L16UI; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_L32I; - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_S8I; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_S16I; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_S32I; - if (Field_r_Slot_inst_get (insn) == 7) - { - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_DPFR; - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_DPFW; - if (Field_t_Slot_inst_get (insn) == 2) - return OPCODE_DPFRO; - if (Field_t_Slot_inst_get (insn) == 3) - return OPCODE_DPFWO; - if (Field_t_Slot_inst_get (insn) == 4) - return OPCODE_DHWB; - if (Field_t_Slot_inst_get (insn) == 5) - return OPCODE_DHWBI; - if (Field_t_Slot_inst_get (insn) == 6) - return OPCODE_DHI; - if (Field_t_Slot_inst_get (insn) == 7) - return OPCODE_DII; - if (Field_t_Slot_inst_get (insn) == 8) - { - if (Field_op1_Slot_inst_get (insn) == 0) - return OPCODE_DPFL; - if (Field_op1_Slot_inst_get (insn) == 2) - return OPCODE_DHU; - if (Field_op1_Slot_inst_get (insn) == 3) - return OPCODE_DIU; - if (Field_op1_Slot_inst_get (insn) == 4) - return OPCODE_DIWB; - if (Field_op1_Slot_inst_get (insn) == 5) - return OPCODE_DIWBI; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_DIWBUI_P; - } - if (Field_t_Slot_inst_get (insn) == 12) - return OPCODE_IPF; - if (Field_t_Slot_inst_get (insn) == 13) - { - if (Field_op1_Slot_inst_get (insn) == 0) - return OPCODE_IPFL; - if (Field_op1_Slot_inst_get (insn) == 2) - return OPCODE_IHU; - if (Field_op1_Slot_inst_get (insn) == 3) - return OPCODE_IIU; - } - if (Field_t_Slot_inst_get (insn) == 14) - return OPCODE_IHI; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_III; - } - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_L16SI; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_MOVI; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_L32AI; - if (Field_r_Slot_inst_get (insn) == 12) - return OPCODE_ADDI; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_ADDMI; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_S32C1I; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_S32RI; - } - if (Field_op0_Slot_inst_get (insn) == 4) - { - if (Field_ae_r10_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_I; - if (Field_ae_r10_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_X; - if (Field_ae_r10_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_I; - if (Field_ae_r10_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_X; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_IU; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_XU; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_CVTQ48A32S; - if (Field_ae_r10_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_IU; - if (Field_ae_r10_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_ae_s3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVP48; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVPA24X2; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_CVTA32P24_L; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_LL; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_HL; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVAP24S_L; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCA16P24S_L; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP16X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24X2_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCP24A32X2; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_CVTA32P24_H; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_LH; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_HH; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVAP24S_H; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCA16P24S_H; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_I; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_X; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_TRUNCA32Q48; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_I; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_X; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_NSAQ56S; - if (Field_ae_r32_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_IU; - if (Field_ae_r32_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_XU; - if (Field_ae_r32_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_IU; - if (Field_ae_r32_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_XU; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRLIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRAIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLISQ56S; - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SHA32; - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLDL32T; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SLLAQ56; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLDL16T; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SRLAQ56; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LBK; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SRAAQ56; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLEL32T; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SLLASQ56S; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLEL16T; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_MOVTQ56; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_MOVFQ56; - if (Field_r_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_OVERFLOW; - if (Field_r_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_SBI; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_SAR; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_DB; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_SB; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_BITPTR; - if (Field_r_Slot_inst_get (insn) == 3 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_BITSUSED; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_TABLESIZE; - if (Field_r_Slot_inst_get (insn) == 5 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_FIRST_TS; - if (Field_r_Slot_inst_get (insn) == 6 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_NEXTOFFSET; - if (Field_r_Slot_inst_get (insn) == 7 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_SEARCHDONE; - if (Field_r_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_VLDSHT; - if (Field_r_Slot_inst_get (insn) == 12 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_VLES16C; - if (Field_r_Slot_inst_get (insn) == 13 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SBF; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_VLDL16C; - if (Field_s_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLSQ56; - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LB; - if (Field_s_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRLSQ56; - if (Field_s_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRASQ56; - if (Field_s_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLSSQ56S; - if (Field_s_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVQ56; - if (Field_s_Slot_inst_get (insn) == 8 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_OVERFLOW; - if (Field_s_Slot_inst_get (insn) == 9 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_SAR; - if (Field_s_Slot_inst_get (insn) == 10 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_BITPTR; - if (Field_s_Slot_inst_get (insn) == 11 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_BITSUSED; - if (Field_s_Slot_inst_get (insn) == 12 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_TABLESIZE; - if (Field_s_Slot_inst_get (insn) == 13 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_FIRST_TS; - if (Field_s_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_NEXTOFFSET; - if (Field_s_Slot_inst_get (insn) == 15 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_SEARCHDONE; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_LBKI; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_r_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_DBI; - if (Field_t_Slot_inst_get (insn) == 2 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_LBI; - } - if (Field_op0_Slot_inst_get (insn) == 5) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_CALL0; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_CALL4; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_CALL8; - if (Field_n_Slot_inst_get (insn) == 3) - return OPCODE_CALL12; - } - if (Field_op0_Slot_inst_get (insn) == 6) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_J; - if (Field_n_Slot_inst_get (insn) == 1) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_BEQZ; - if (Field_m_Slot_inst_get (insn) == 1) - return OPCODE_BNEZ; - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTZ; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEZ; - } - if (Field_n_Slot_inst_get (insn) == 2) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_BEQI; - if (Field_m_Slot_inst_get (insn) == 1) - return OPCODE_BNEI; - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTI; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEI; - } - if (Field_n_Slot_inst_get (insn) == 3) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_ENTRY; - if (Field_m_Slot_inst_get (insn) == 1) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_BF; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_BT; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_LOOP; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_LOOPNEZ; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_LOOPGTZ; - } - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTUI; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEUI; - } - } - if (Field_op0_Slot_inst_get (insn) == 7) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_BNONE; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_BEQ; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_BLT; - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_BLTU; - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_BALL; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_BBC; - if ((Field_r_Slot_inst_get (insn) == 6 || - Field_r_Slot_inst_get (insn) == 7)) - return OPCODE_BBCI; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_BANY; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_BNE; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_BGE; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_BGEU; - if (Field_r_Slot_inst_get (insn) == 12) - return OPCODE_BNALL; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_BBS; - if ((Field_r_Slot_inst_get (insn) == 14 || - Field_r_Slot_inst_get (insn) == 15)) - return OPCODE_BBSI; - } - return 0; -} - -static int -Slot_inst16b_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst16b_get (insn) == 12) - { - if (Field_i_Slot_inst16b_get (insn) == 0) - return OPCODE_MOVI_N; - if (Field_i_Slot_inst16b_get (insn) == 1) - { - if (Field_z_Slot_inst16b_get (insn) == 0) - return OPCODE_BEQZ_N; - if (Field_z_Slot_inst16b_get (insn) == 1) - return OPCODE_BNEZ_N; - } - } - if (Field_op0_Slot_inst16b_get (insn) == 13) - { - if (Field_r_Slot_inst16b_get (insn) == 0) - return OPCODE_MOV_N; - if (Field_r_Slot_inst16b_get (insn) == 15) - { - if (Field_t_Slot_inst16b_get (insn) == 0) - return OPCODE_RET_N; - if (Field_t_Slot_inst16b_get (insn) == 1) - return OPCODE_RETW_N; - if (Field_t_Slot_inst16b_get (insn) == 2) - return OPCODE_BREAK_N; - if (Field_t_Slot_inst16b_get (insn) == 3 && - Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_NOP_N; - if (Field_t_Slot_inst16b_get (insn) == 6 && - Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_ILL_N; - } - } - return 0; -} - -static int -Slot_inst16a_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst16a_get (insn) == 8) - return OPCODE_L32I_N; - if (Field_op0_Slot_inst16a_get (insn) == 9) - return OPCODE_S32I_N; - if (Field_op0_Slot_inst16a_get (insn) == 10) - return OPCODE_ADD_N; - if (Field_op0_Slot_inst16a_get (insn) == 11) - return OPCODE_ADDI_N; - return 0; -} - -static int -Slot_ae_slot0_decode (const xtensa_insnbuf insn) -{ - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_ADDBRBA32; - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 2 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_C; - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 2 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_C; - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 2 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_C; - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf353_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_C; - if (Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_C; - if (Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_C; - if (Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_get (insn) == 2 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_C; - if (Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_C; - if (Field_combined1b97e84f_fld93_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld90_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_C; - if (Field_combined4b12daa6_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld85_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld122_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld119_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld97_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SELP24_LH; - if (Field_combined4b12daa6_fld122_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld85_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld119_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld97_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SELP24_HH; - if (Field_combined4b12daa6_fld122_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld85_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld119_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld97_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SELP24_HL; - if (Field_combined4b12daa6_fld85_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld122_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld119_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld97_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld115_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SELP24_LL; - if (Field_ftsf212ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_J; - if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_EXTUI; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BGEZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BLTZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 8 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BEQZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 9 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BNEZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVI; - if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 88 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRAI; - if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 96 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SLLI; - if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 123 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVTQ56; - if (Field_ftsf216ae_slot0_Slot_ae_slot0_get (insn) == 418 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_HH; - if (Field_ftsf217_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4 && - Field_ae_r20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_L32I; - if (Field_ftsf218ae_slot0_Slot_ae_slot0_get (insn) == 419 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_I; - if (Field_ftsf219ae_slot0_Slot_ae_slot0_get (insn) == 420 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_HL; - if (Field_ftsf220ae_slot0_Slot_ae_slot0_get (insn) == 421 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_IU; - if (Field_ftsf221ae_slot0_Slot_ae_slot0_get (insn) == 422 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_X; - if (Field_ftsf222ae_slot0_Slot_ae_slot0_get (insn) == 423 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_XU; - if (Field_ftsf223ae_slot0_Slot_ae_slot0_get (insn) == 424 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_LH; - if (Field_ftsf224ae_slot0_Slot_ae_slot0_get (insn) == 425 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_I; - if (Field_ftsf225ae_slot0_Slot_ae_slot0_get (insn) == 426 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_IU; - if (Field_ftsf226ae_slot0_Slot_ae_slot0_get (insn) == 427 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_XU; - if (Field_ftsf227ae_slot0_Slot_ae_slot0_get (insn) == 428 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_X; - if (Field_ftsf228ae_slot0_Slot_ae_slot0_get (insn) == 429 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_I; - if (Field_ftsf229ae_slot0_Slot_ae_slot0_get (insn) == 430 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_IU; - if (Field_ftsf230ae_slot0_Slot_ae_slot0_get (insn) == 431 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_X; - if (Field_ftsf231ae_slot0_Slot_ae_slot0_get (insn) == 432 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_LL; - if (Field_ftsf232ae_slot0_Slot_ae_slot0_get (insn) == 433 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_XU; - if (Field_ftsf233ae_slot0_Slot_ae_slot0_get (insn) == 434 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_I; - if (Field_ftsf234ae_slot0_Slot_ae_slot0_get (insn) == 435 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_XU; - if (Field_ftsf235ae_slot0_Slot_ae_slot0_get (insn) == 436 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_IU; - if (Field_ftsf236ae_slot0_Slot_ae_slot0_get (insn) == 437 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_I; - if (Field_ftsf237ae_slot0_Slot_ae_slot0_get (insn) == 438 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_IU; - if (Field_ftsf238ae_slot0_Slot_ae_slot0_get (insn) == 439 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_X; - if (Field_ftsf239ae_slot0_Slot_ae_slot0_get (insn) == 440 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_X; - if (Field_ftsf240ae_slot0_Slot_ae_slot0_get (insn) == 441 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_XU; - if (Field_ftsf241ae_slot0_Slot_ae_slot0_get (insn) == 442 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_I; - if (Field_ftsf242ae_slot0_Slot_ae_slot0_get (insn) == 443 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_X; - if (Field_ftsf243ae_slot0_Slot_ae_slot0_get (insn) == 444 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_IU; - if (Field_ftsf244ae_slot0_Slot_ae_slot0_get (insn) == 445 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_XU; - if (Field_ftsf245ae_slot0_Slot_ae_slot0_get (insn) == 446 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVPA24X2; - if (Field_ftsf246ae_slot0_Slot_ae_slot0_get (insn) == 447 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_I; - if (Field_ftsf247ae_slot0_Slot_ae_slot0_get (insn) == 450 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_IU; - if (Field_ftsf248ae_slot0_Slot_ae_slot0_get (insn) == 451 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_X; - if (Field_ftsf249ae_slot0_Slot_ae_slot0_get (insn) == 452 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_X; - if (Field_ftsf250ae_slot0_Slot_ae_slot0_get (insn) == 453 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_XU; - if (Field_ftsf251ae_slot0_Slot_ae_slot0_get (insn) == 454 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_I; - if (Field_ftsf252ae_slot0_Slot_ae_slot0_get (insn) == 455 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_IU; - if (Field_ftsf253ae_slot0_Slot_ae_slot0_get (insn) == 456 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_XU; - if (Field_ftsf254ae_slot0_Slot_ae_slot0_get (insn) == 457 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_X; - if (Field_ftsf255ae_slot0_Slot_ae_slot0_get (insn) == 458 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_XU; - if (Field_ftsf256ae_slot0_Slot_ae_slot0_get (insn) == 459 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_IU; - if (Field_ftsf257ae_slot0_Slot_ae_slot0_get (insn) == 460 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_I; - if (Field_ftsf258ae_slot0_Slot_ae_slot0_get (insn) == 461 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_X; - if (Field_ftsf259ae_slot0_Slot_ae_slot0_get (insn) == 462 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_XU; - if (Field_ftsf260ae_slot0_Slot_ae_slot0_get (insn) == 463 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_I; - if (Field_ftsf261ae_slot0_Slot_ae_slot0_get (insn) == 464 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_I; - if (Field_ftsf262ae_slot0_Slot_ae_slot0_get (insn) == 465 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_IU; - if (Field_ftsf263ae_slot0_Slot_ae_slot0_get (insn) == 466 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_X; - if (Field_ftsf264ae_slot0_Slot_ae_slot0_get (insn) == 467 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_IU; - if (Field_ftsf265ae_slot0_Slot_ae_slot0_get (insn) == 468 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_XU; - if (Field_ftsf266ae_slot0_Slot_ae_slot0_get (insn) == 469 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_X; - if (Field_ftsf267ae_slot0_Slot_ae_slot0_get (insn) == 470 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_XU; - if (Field_ftsf268ae_slot0_Slot_ae_slot0_get (insn) == 471 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_TRUNCP24A32X2; - if (Field_ftsf269ae_slot0_Slot_ae_slot0_get (insn) == 472 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_I; - if (Field_ftsf270ae_slot0_Slot_ae_slot0_get (insn) == 946 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_I; - if (Field_ftsf271ae_slot0_Slot_ae_slot0_get (insn) == 947 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_IU; - if (Field_ftsf272ae_slot0_Slot_ae_slot0_get (insn) == 948 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_I; - if (Field_ftsf273ae_slot0_Slot_ae_slot0_get (insn) == 949 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_X; - if (Field_ftsf274ae_slot0_Slot_ae_slot0_get (insn) == 950 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_XU; - if (Field_ftsf275ae_slot0_Slot_ae_slot0_get (insn) == 951 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_I; - if (Field_ftsf276ae_slot0_Slot_ae_slot0_get (insn) == 952 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_IU; - if (Field_ftsf277ae_slot0_Slot_ae_slot0_get (insn) == 953 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_IU; - if (Field_ftsf278ae_slot0_Slot_ae_slot0_get (insn) == 954 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_X; - if (Field_ftsf279ae_slot0_Slot_ae_slot0_get (insn) == 15280 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTQ48A32S; - if (Field_ftsf281ae_slot0_Slot_ae_slot0_get (insn) == 60977 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_JX; - if (Field_ftsf282ae_slot0_Slot_ae_slot0_get (insn) == 61041 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SSR; - if (Field_ftsf283ae_slot0_Slot_ae_slot0_get (insn) == 30577 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf352ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_NOP; - if (Field_ftsf284ae_slot0_Slot_ae_slot0_get (insn) == 7641 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf354ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSA8B; - if (Field_ftsf286ae_slot0_Slot_ae_slot0_get (insn) == 3821 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf356ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSA8L; - if (Field_ftsf288ae_slot0_Slot_ae_slot0_get (insn) == 1911 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf359ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSL; - if (Field_ftsf290ae_slot0_Slot_ae_slot0_get (insn) == 478 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s8_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_LQ56_XU; - if (Field_ftsf292ae_slot0_Slot_ae_slot0_get (insn) == 1913 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ALL8; - if (Field_ftsf293_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBCI; - if (Field_ftsf293_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBSI; - if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 1915 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ANY8; - if (Field_ftsf295ae_slot0_Slot_ae_slot0_get (insn) == 959 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf358ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSAI; - if (Field_ftsf296ae_slot0_Slot_ae_slot0_get (insn) == 480 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_IU; - if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 962 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_I; - if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 963 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_IU; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 964 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLIQ56; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 965 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SRAIQ56; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 966 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SRLIQ56; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 968 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLISQ56S; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3868 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ABS; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3869 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_NEG; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3870 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRA; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3871 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRL; - if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7752 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf321_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVP48; - if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7753 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf353_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ANY4; - if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 31016 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf321_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVQ56; - if (Field_ftsf303ae_slot0_Slot_ae_slot0_get (insn) == 31017 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf321_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SLLSSQ56S; - if (Field_ftsf304ae_slot0_Slot_ae_slot0_get (insn) == 15509 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf369ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRASQ56; - if (Field_ftsf306ae_slot0_Slot_ae_slot0_get (insn) == 7755 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf368ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRLSQ56; - if (Field_ftsf308ae_slot0_Slot_ae_slot0_get (insn) == 1939 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf366ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SLLSQ56; - if (Field_ftsf309ae_slot0_Slot_ae_slot0_get (insn) == 485 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ALL4; - if (Field_ftsf310ae_slot0_Slot_ae_slot0_get (insn) == 972 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_X; - if (Field_ftsf311ae_slot0_Slot_ae_slot0_get (insn) == 973 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_XU; - if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 7792 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTA32P24_H; - if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 7793 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTA32P24_L; - if (Field_ftsf314ae_slot0_Slot_ae_slot0_get (insn) == 7794 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVAP24S_H; - if (Field_ftsf315ae_slot0_Slot_ae_slot0_get (insn) == 7795 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_TRUNCA16P24S_L; - if (Field_ftsf316ae_slot0_Slot_ae_slot0_get (insn) == 7796 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVAP24S_L; - if (Field_ftsf317ae_slot0_Slot_ae_slot0_get (insn) == 7797 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf353_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_NSAQ56S; - if (Field_ftsf318ae_slot0_Slot_ae_slot0_get (insn) == 3899 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf365ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_TRUNCA32Q48; - if (Field_ftsf319_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_ftsf361ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BT; - if (Field_ftsf320ae_slot0_Slot_ae_slot0_get (insn) == 975 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_TRUNCA16P24S_H; - if (Field_ftsf321_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_ae_s20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BLTUI; - if (Field_ftsf321_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld101_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld88_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld39_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLAASQ56S; - if (Field_ftsf322ae_slot0_Slot_ae_slot0_get (insn) == 3920 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVFQ56; - if (Field_ftsf323ae_slot0_Slot_ae_slot0_get (insn) == 3921 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLAQ56; - if (Field_ftsf324ae_slot0_Slot_ae_slot0_get (insn) == 3922 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLASQ56S; - if (Field_ftsf325ae_slot0_Slot_ae_slot0_get (insn) == 3923 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SLL; - if (Field_ftsf326ae_slot0_Slot_ae_slot0_get (insn) == 981 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf357_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRAAQ56; - if (Field_ftsf328ae_slot0_Slot_ae_slot0_get (insn) == 491 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRLAQ56; - if (Field_ftsf329ae_slot0_Slot_ae_slot0_get (insn) == 31 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SQ32F_XU; - if (Field_ftsf353_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_C; - if (Field_imm8_Slot_ae_slot0_get (insn) == 178 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADD; - if (Field_imm8_Slot_ae_slot0_get (insn) == 179 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX8; - if (Field_imm8_Slot_ae_slot0_get (insn) == 180 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX2; - if (Field_imm8_Slot_ae_slot0_get (insn) == 181 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AND; - if (Field_imm8_Slot_ae_slot0_get (insn) == 182 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ANDB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 183 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ANDBC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 184 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX4; - if (Field_imm8_Slot_ae_slot0_get (insn) == 185 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_CLAMPS; - if (Field_imm8_Slot_ae_slot0_get (insn) == 186 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MAX; - if (Field_imm8_Slot_ae_slot0_get (insn) == 187 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MIN; - if (Field_imm8_Slot_ae_slot0_get (insn) == 188 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MAXU; - if (Field_imm8_Slot_ae_slot0_get (insn) == 189 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MINU; - if (Field_imm8_Slot_ae_slot0_get (insn) == 190 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVEQZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 191 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVF; - if (Field_imm8_Slot_ae_slot0_get (insn) == 194 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVGEZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 195 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ORB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 196 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVLTZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 197 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ORBC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 198 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SEXT; - if (Field_imm8_Slot_ae_slot0_get (insn) == 199 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 200 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVNEZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 201 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRLI; - if (Field_imm8_Slot_ae_slot0_get (insn) == 202 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 203 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX4; - if (Field_imm8_Slot_ae_slot0_get (insn) == 204 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX2; - if (Field_imm8_Slot_ae_slot0_get (insn) == 205 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX8; - if (Field_imm8_Slot_ae_slot0_get (insn) == 206 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_XOR; - if (Field_imm8_Slot_ae_slot0_get (insn) == 207 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_XORB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 208 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVT; - if (Field_imm8_Slot_ae_slot0_get (insn) == 224 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_OR; - if (Field_imm8_Slot_ae_slot0_get (insn) == 244 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_r32_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SQ32F_X; - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5) - return OPCODE_L32R; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP16X2F_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 6 && - Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP24F_L_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 7 && - Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP24S_L_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 8 && - Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP24X2F_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 9 && - Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP24X2S_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 10 && - Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_LQ56_C; - if (Field_r_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_BNE; - if (Field_r_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_BNONE; - if (Field_r_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L16SI; - if (Field_r_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L8UI; - if (Field_r_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_ADDI; - if (Field_r_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L16UI; - if (Field_r_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BALL; - if (Field_r_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S16I; - if (Field_r_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BANY; - if (Field_r_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S32I; - if (Field_r_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBC; - if (Field_r_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S8I; - if (Field_r_Slot_ae_slot0_get (insn) == 8 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_ADDMI; - if (Field_r_Slot_ae_slot0_get (insn) == 9 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBS; - if (Field_r_Slot_ae_slot0_get (insn) == 10 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BEQ; - if (Field_r_Slot_ae_slot0_get (insn) == 11 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BGEU; - if (Field_r_Slot_ae_slot0_get (insn) == 12 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BGE; - if (Field_r_Slot_ae_slot0_get (insn) == 13 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BLT; - if (Field_r_Slot_ae_slot0_get (insn) == 14 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BLTU; - if (Field_r_Slot_ae_slot0_get (insn) == 15 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BNALL; - if (Field_t_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BEQI; - if (Field_t_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BGEI; - if (Field_t_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BGEUI; - if (Field_t_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BNEI; - if (Field_t_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BLTI; - if (Field_t_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_r_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BF; - return 0; -} - -static int -Slot_ae_slot1_decode (const xtensa_insnbuf insn) -{ - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 288 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULRFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 289 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULRFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 290 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULARFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 291 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULARFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 292 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSRFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 293 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSRFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 294 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 295 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 296 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 297 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 298 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 299 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP24S_L; - if (Field_combined1b97e84f_fld17_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld76_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf208_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld73_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld62_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld24_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld70_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld58_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5 && - Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MINABSSQ56S; - if (Field_combined1b97e84f_fld49_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf338_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld54_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r32_Slot_ae_slot1_get (insn) == 2 && - Field_combined1b97e84f_fld51_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld23_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MINABSSP24S; - if (Field_combined1b97e84f_fld49_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf338_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld54_Slot_ae_slot1_get (insn) == 0 && - Field_ae_r32_Slot_ae_slot1_get (insn) == 2 && - Field_combined1b97e84f_fld51_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld23_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MAXABSSP24S; - if (Field_combined1b97e84f_fld54_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld17_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld76_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf208_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld73_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld62_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld24_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld70_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld58_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MAXABSSQ56S; - if (Field_ftsf100ae_slot1_Slot_ae_slot1_get (insn) == 115 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_NEGSP24S; - if (Field_ftsf101ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf348ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ABSSP24S; - if (Field_ftsf103ae_slot1_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf349ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_NEGP24; - if (Field_ftsf104ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MAXBQ56S; - if (Field_ftsf105ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MINBQ56S; - if (Field_ftsf106ae_slot1_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ae_r32_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_EQQ56; - if (Field_ftsf107ae_slot1_Slot_ae_slot1_get (insn) == 48 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ADDSQ56S; - if (Field_ftsf108ae_slot1_Slot_ae_slot1_get (insn) == 49 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ANDQ56; - if (Field_ftsf109ae_slot1_Slot_ae_slot1_get (insn) == 50 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MAXQ56S; - if (Field_ftsf110ae_slot1_Slot_ae_slot1_get (insn) == 51 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ORQ56; - if (Field_ftsf111ae_slot1_Slot_ae_slot1_get (insn) == 52 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MINQ56S; - if (Field_ftsf112ae_slot1_Slot_ae_slot1_get (insn) == 53 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_SUBQ56; - if (Field_ftsf113ae_slot1_Slot_ae_slot1_get (insn) == 54 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_SUBSQ56S; - if (Field_ftsf114ae_slot1_Slot_ae_slot1_get (insn) == 55 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_XORQ56; - if (Field_ftsf115ae_slot1_Slot_ae_slot1_get (insn) == 56 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_NANDQ56; - if (Field_ftsf116ae_slot1_Slot_ae_slot1_get (insn) == 57 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ABSQ56; - if (Field_ftsf118ae_slot1_Slot_ae_slot1_get (insn) == 185 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_NEGSQ56S; - if (Field_ftsf119ae_slot1_Slot_ae_slot1_get (insn) == 185 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf338_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_SATQ48S; - if (Field_ftsf12_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf341ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LTQ56S; - if (Field_ftsf120ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf343ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ABSSQ56S; - if (Field_ftsf122ae_slot1_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf346ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_NEGQ56; - if (Field_ftsf124ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf339ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LEQ56S; - if (Field_ftsf125ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf350ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_TRUNCP24Q48X2; - if (Field_ftsf126ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ADDQ56; - if (Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAFP24S_HH_LL; - if (Field_ftsf128ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAFP24S_HL_LH; - if (Field_ftsf129ae_slot1_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAP24S_HH_LL; - if (Field_ftsf13_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf12_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_SLLISP24S; - if (Field_ftsf130ae_slot1_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_HL; - if (Field_ftsf131ae_slot1_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAP24S_HL_LH; - if (Field_ftsf132ae_slot1_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_LH; - if (Field_ftsf133ae_slot1_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_LL; - if (Field_ftsf134ae_slot1_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_HH; - if (Field_ftsf135ae_slot1_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_HH; - if (Field_ftsf136ae_slot1_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_HL; - if (Field_ftsf137ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_LH; - if (Field_ftsf138ae_slot1_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_HH; - if (Field_ftsf139ae_slot1_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_LL; - if (Field_ftsf140ae_slot1_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_HL; - if (Field_ftsf141ae_slot1_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_LH; - if (Field_ftsf142ae_slot1_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_LL; - if (Field_ftsf143ae_slot1_Slot_ae_slot1_get (insn) == 16 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_HL; - if (Field_ftsf144ae_slot1_Slot_ae_slot1_get (insn) == 17 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_HH; - if (Field_ftsf145ae_slot1_Slot_ae_slot1_get (insn) == 18 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_HL; - if (Field_ftsf146ae_slot1_Slot_ae_slot1_get (insn) == 19 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASFP24S_HH_LL; - if (Field_ftsf147ae_slot1_Slot_ae_slot1_get (insn) == 20 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_LH; - if (Field_ftsf148ae_slot1_Slot_ae_slot1_get (insn) == 21 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASFP24S_HL_LH; - if (Field_ftsf149ae_slot1_Slot_ae_slot1_get (insn) == 22 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASP24S_HH_LL; - if (Field_ftsf150ae_slot1_Slot_ae_slot1_get (insn) == 23 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASP24S_HL_LH; - if (Field_ftsf151ae_slot1_Slot_ae_slot1_get (insn) == 24 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_LL; - if (Field_ftsf152ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_HH; - if (Field_ftsf153ae_slot1_Slot_ae_slot1_get (insn) == 26 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_HL; - if (Field_ftsf154ae_slot1_Slot_ae_slot1_get (insn) == 27 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_LL; - if (Field_ftsf155ae_slot1_Slot_ae_slot1_get (insn) == 28 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_LH; - if (Field_ftsf156ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_HH; - if (Field_ftsf157ae_slot1_Slot_ae_slot1_get (insn) == 30 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_HL; - if (Field_ftsf158ae_slot1_Slot_ae_slot1_get (insn) == 31 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_LH; - if (Field_ftsf159ae_slot1_Slot_ae_slot1_get (insn) == 32 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_LH; - if (Field_ftsf160ae_slot1_Slot_ae_slot1_get (insn) == 33 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_LL; - if (Field_ftsf161ae_slot1_Slot_ae_slot1_get (insn) == 34 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_HH; - if (Field_ftsf162ae_slot1_Slot_ae_slot1_get (insn) == 35 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAFP24S_HH_LL; - if (Field_ftsf163ae_slot1_Slot_ae_slot1_get (insn) == 36 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_HL; - if (Field_ftsf164ae_slot1_Slot_ae_slot1_get (insn) == 37 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAFP24S_HL_LH; - if (Field_ftsf165ae_slot1_Slot_ae_slot1_get (insn) == 38 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAP24S_HH_LL; - if (Field_ftsf166ae_slot1_Slot_ae_slot1_get (insn) == 39 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAP24S_HL_LH; - if (Field_ftsf167ae_slot1_Slot_ae_slot1_get (insn) == 40 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_LH; - if (Field_ftsf168ae_slot1_Slot_ae_slot1_get (insn) == 41 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_HH; - if (Field_ftsf169ae_slot1_Slot_ae_slot1_get (insn) == 42 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_HL; - if (Field_ftsf170ae_slot1_Slot_ae_slot1_get (insn) == 43 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_LL; - if (Field_ftsf171ae_slot1_Slot_ae_slot1_get (insn) == 44 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_LH; - if (Field_ftsf172ae_slot1_Slot_ae_slot1_get (insn) == 45 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_HH; - if (Field_ftsf173ae_slot1_Slot_ae_slot1_get (insn) == 46 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_HL; - if (Field_ftsf174ae_slot1_Slot_ae_slot1_get (insn) == 47 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_LH; - if (Field_ftsf175ae_slot1_Slot_ae_slot1_get (insn) == 48 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_LL; - if (Field_ftsf176ae_slot1_Slot_ae_slot1_get (insn) == 49 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_LL; - if (Field_ftsf177ae_slot1_Slot_ae_slot1_get (insn) == 50 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_HH; - if (Field_ftsf178ae_slot1_Slot_ae_slot1_get (insn) == 51 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_LL; - if (Field_ftsf179ae_slot1_Slot_ae_slot1_get (insn) == 52 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_HL; - if (Field_ftsf180ae_slot1_Slot_ae_slot1_get (insn) == 53 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_HH; - if (Field_ftsf181ae_slot1_Slot_ae_slot1_get (insn) == 54 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_HL; - if (Field_ftsf182ae_slot1_Slot_ae_slot1_get (insn) == 55 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_LH; - if (Field_ftsf183ae_slot1_Slot_ae_slot1_get (insn) == 56 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_LH; - if (Field_ftsf184ae_slot1_Slot_ae_slot1_get (insn) == 57 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_LL; - if (Field_ftsf185ae_slot1_Slot_ae_slot1_get (insn) == 58 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_HH; - if (Field_ftsf186ae_slot1_Slot_ae_slot1_get (insn) == 59 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_LH; - if (Field_ftsf187ae_slot1_Slot_ae_slot1_get (insn) == 60 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_HL; - if (Field_ftsf188ae_slot1_Slot_ae_slot1_get (insn) == 61 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_LL; - if (Field_ftsf189ae_slot1_Slot_ae_slot1_get (insn) == 62 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSFP24S_HH_LL; - if (Field_ftsf190ae_slot1_Slot_ae_slot1_get (insn) == 63 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSFP24S_HL_LH; - if (Field_ftsf191ae_slot1_Slot_ae_slot1_get (insn) == 64 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_LL; - if (Field_ftsf192ae_slot1_Slot_ae_slot1_get (insn) == 65 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSP24S_HH_LL; - if (Field_ftsf193ae_slot1_Slot_ae_slot1_get (insn) == 66 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSP24S_HL_LH; - if (Field_ftsf194ae_slot1_Slot_ae_slot1_get (insn) == 67 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASFP24S_HH_LL; - if (Field_ftsf195ae_slot1_Slot_ae_slot1_get (insn) == 68 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZAAFP24S_HH_LL; - if (Field_ftsf196ae_slot1_Slot_ae_slot1_get (insn) == 69 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASFP24S_HL_LH; - if (Field_ftsf197ae_slot1_Slot_ae_slot1_get (insn) == 70 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASP24S_HH_LL; - if (Field_ftsf198ae_slot1_Slot_ae_slot1_get (insn) == 71 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASP24S_HL_LH; - if (Field_ftsf199ae_slot1_Slot_ae_slot1_get (insn) == 72 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZAAFP24S_HL_LH; - if (Field_ftsf200ae_slot1_Slot_ae_slot1_get (insn) == 73 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAFP24S_HH_LL; - if (Field_ftsf201ae_slot1_Slot_ae_slot1_get (insn) == 74 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAFP24S_HL_LH; - if (Field_ftsf202ae_slot1_Slot_ae_slot1_get (insn) == 75 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAP24S_HL_LH; - if (Field_ftsf203ae_slot1_Slot_ae_slot1_get (insn) == 76 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAP24S_HH_LL; - if (Field_ftsf204ae_slot1_Slot_ae_slot1_get (insn) == 77 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSFP24S_HH_LL; - if (Field_ftsf205ae_slot1_Slot_ae_slot1_get (insn) == 78 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSFP24S_HL_LH; - if (Field_ftsf206ae_slot1_Slot_ae_slot1_get (insn) == 79 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSP24S_HH_LL; - if (Field_ftsf207ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZAAP24S_HH_LL; - if (Field_ftsf209ae_slot1_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZSSP24S_HL_LH; - if (Field_ftsf210ae_slot1_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf337ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZAAP24S_HL_LH; - if (Field_ftsf211ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf332ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULAFS32P16S_HH; - if (Field_ftsf21ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MAXBP24S; - if (Field_ftsf22ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MINBP24S; - if (Field_ftsf23ae_slot1_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVFP48; - if (Field_ftsf24ae_slot1_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVTP48; - if (Field_ftsf25ae_slot1_Slot_ae_slot1_get (insn) == 20 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ADDP24; - if (Field_ftsf26ae_slot1_Slot_ae_slot1_get (insn) == 21 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ANDP48; - if (Field_ftsf27ae_slot1_Slot_ae_slot1_get (insn) == 22 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MAXP24S; - if (Field_ftsf28ae_slot1_Slot_ae_slot1_get (insn) == 23 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MINP24S; - if (Field_ftsf29ae_slot1_Slot_ae_slot1_get (insn) == 24 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ADDSP24S; - if (Field_ftsf30ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_NANDP48; - if (Field_ftsf31ae_slot1_Slot_ae_slot1_get (insn) == 26 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ORP48; - if (Field_ftsf32ae_slot1_Slot_ae_slot1_get (insn) == 27 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_HL; - if (Field_ftsf33ae_slot1_Slot_ae_slot1_get (insn) == 28 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_HH; - if (Field_ftsf34ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_LH; - if (Field_ftsf35ae_slot1_Slot_ae_slot1_get (insn) == 30 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_LL; - if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 31 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SUBP24; - if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SLLIP24; - if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRAIP24; - if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRLIP24; - if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 176 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16S_L; - if (Field_ftsf39ae_slot1_Slot_ae_slot1_get (insn) == 177 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16U_H; - if (Field_ftsf40ae_slot1_Slot_ae_slot1_get (insn) == 178 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16U_L; - if (Field_ftsf41ae_slot1_Slot_ae_slot1_get (insn) == 179 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16U_H; - if (Field_ftsf42ae_slot1_Slot_ae_slot1_get (insn) == 180 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16S_H; - if (Field_ftsf43ae_slot1_Slot_ae_slot1_get (insn) == 181 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16U_L; - if (Field_ftsf44ae_slot1_Slot_ae_slot1_get (insn) == 182 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16S_H; - if (Field_ftsf45ae_slot1_Slot_ae_slot1_get (insn) == 183 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16S_L; - if (Field_ftsf46ae_slot1_Slot_ae_slot1_get (insn) == 184 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16S_L; - if (Field_ftsf47ae_slot1_Slot_ae_slot1_get (insn) == 185 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16U_H; - if (Field_ftsf48ae_slot1_Slot_ae_slot1_get (insn) == 186 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16U_L; - if (Field_ftsf49ae_slot1_Slot_ae_slot1_get (insn) == 187 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16S_L; - if (Field_ftsf50ae_slot1_Slot_ae_slot1_get (insn) == 188 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16S_H; - if (Field_ftsf51ae_slot1_Slot_ae_slot1_get (insn) == 189 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16U_H; - if (Field_ftsf52ae_slot1_Slot_ae_slot1_get (insn) == 190 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16U_L; - if (Field_ftsf53ae_slot1_Slot_ae_slot1_get (insn) == 191 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16S_H; - if (Field_ftsf54ae_slot1_Slot_ae_slot1_get (insn) == 192 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16S_H; - if (Field_ftsf55ae_slot1_Slot_ae_slot1_get (insn) == 193 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16S_L; - if (Field_ftsf56ae_slot1_Slot_ae_slot1_get (insn) == 194 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16U_H; - if (Field_ftsf57ae_slot1_Slot_ae_slot1_get (insn) == 195 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSQ32SP16U_L; - if (Field_ftsf58ae_slot1_Slot_ae_slot1_get (insn) == 196 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16U_L; - if (Field_ftsf59ae_slot1_Slot_ae_slot1_get (insn) == 773 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_CVTQ48P24S_H; - if (Field_ftsf60ae_slot1_Slot_ae_slot1_get (insn) == 789 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ZEROQ56; - if (Field_ftsf61ae_slot1_Slot_ae_slot1_get (insn) == 405 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf330ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_NOP; - if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 198 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r10_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_CVTQ48P24S_L; - if (Field_ftsf64ae_slot1_Slot_ae_slot1_get (insn) == 1543 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVQ56; - if (Field_ftsf66ae_slot1_Slot_ae_slot1_get (insn) == 1559 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSQ32ASYM; - if (Field_ftsf67ae_slot1_Slot_ae_slot1_get (insn) == 791 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSQ32SYM; - if (Field_ftsf69ae_slot1_Slot_ae_slot1_get (insn) == 407 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf340_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_TRUNCQ32; - if (Field_ftsf71ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULSQ32SP16S_H; - if (Field_ftsf72ae_slot1_Slot_ae_slot1_get (insn) == 26 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULSQ32SP16S_L; - if (Field_ftsf73ae_slot1_Slot_ae_slot1_get (insn) == 417 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVP48; - if (Field_ftsf75ae_slot1_Slot_ae_slot1_get (insn) == 419 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16ASYM; - if (Field_ftsf76ae_slot1_Slot_ae_slot1_get (insn) == 421 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16SYM; - if (Field_ftsf77ae_slot1_Slot_ae_slot1_get (insn) == 423 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRASP24; - if (Field_ftsf78ae_slot1_Slot_ae_slot1_get (insn) == 425 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SLLSP24; - if (Field_ftsf79ae_slot1_Slot_ae_slot1_get (insn) == 427 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRLSP24; - if (Field_ftsf80ae_slot1_Slot_ae_slot1_get (insn) == 429 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_TRUNCP16; - if (Field_ftsf81ae_slot1_Slot_ae_slot1_get (insn) == 431 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ZEROP48; - if (Field_ftsf82ae_slot1_Slot_ae_slot1_get (insn) == 109 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r10_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_SLLSSP24S; - if (Field_ftsf84ae_slot1_Slot_ae_slot1_get (insn) == 881 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16Q48ASYM; - if (Field_ftsf86ae_slot1_Slot_ae_slot1_get (insn) == 883 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16Q48SYM; - if (Field_ftsf87ae_slot1_Slot_ae_slot1_get (insn) == 443 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSP24Q48ASYM; - if (Field_ftsf88ae_slot1_Slot_ae_slot1_get (insn) == 223 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf340_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSP24Q48SYM; - if (Field_ftsf89ae_slot1_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf334ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULSQ32SP16U_H; - if (Field_ftsf90ae_slot1_Slot_ae_slot1_get (insn) == 96 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_EQP24; - if (Field_ftsf91ae_slot1_Slot_ae_slot1_get (insn) == 97 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_LEP24S; - if (Field_ftsf92ae_slot1_Slot_ae_slot1_get (insn) == 49 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf208_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LTP24S; - if (Field_ftsf94ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf347_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MOVFP24X2; - if (Field_ftsf96ae_slot1_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MOVTP24X2; - if (Field_ftsf97ae_slot1_Slot_ae_slot1_get (insn) == 112 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SUBSP24S; - if (Field_ftsf98ae_slot1_Slot_ae_slot1_get (insn) == 113 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_XORP48; - if (Field_ftsf99ae_slot1_Slot_ae_slot1_get (insn) == 114 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ABSP24; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_LL; - if (Field_xt_fld0_Slot_ae_slot1_get (insn) == 832 && - Field_xt_fld1_Slot_ae_slot1_get (insn) == 2) - return OPCODE_READ_IPQ; - if (Field_xt_fld0_Slot_ae_slot1_get (insn) == 832 && - Field_xt_fld1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_CHECK_IPQ; - if (Field_xt_fld0_Slot_ae_slot1_get (insn) == 832 && - Field_xt_fld1_Slot_ae_slot1_get (insn) == 3) - return OPCODE_WRITE_OPQ; - if (Field_xt_fld0_Slot_ae_slot1_get (insn) == 832 && - Field_xt_fld1_Slot_ae_slot1_get (insn) == 1) - return OPCODE_CHECK_OPQ; - return 0; -} - - -/* Instruction slots. */ - -static void -Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffffff); -} - -static void -Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); -} - -static void -Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static void -Slot_ae_format_Format_ae_slot1_31_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[0] & 0x80000000) >> 31); - slotbuf[0] = (slotbuf[0] & ~0x7ffffe) | ((insn[1] & 0x3fffff) << 1); -} - -static void -Slot_ae_format_Format_ae_slot1_31_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0x80000000) | ((slotbuf[0] & 0x1) << 31); - insn[1] = (insn[1] & ~0x3fffff) | ((slotbuf[0] & 0x7ffffe) >> 1); -} - -static void -Slot_ae_format_Format_ae_slot0_4_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[0] & 0x7ffffff0) >> 4); -} - -static void -Slot_ae_format_Format_ae_slot0_4_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0x7ffffff0) | ((slotbuf[0] & 0x7ffffff) << 4); -} - -static xtensa_get_field_fn -Slot_inst_get_field_fns[] = { - Field_t_Slot_inst_get, - Field_bbi4_Slot_inst_get, - Field_bbi_Slot_inst_get, - Field_imm12_Slot_inst_get, - Field_imm8_Slot_inst_get, - Field_s_Slot_inst_get, - Field_imm12b_Slot_inst_get, - Field_imm16_Slot_inst_get, - Field_m_Slot_inst_get, - Field_n_Slot_inst_get, - Field_offset_Slot_inst_get, - Field_op0_Slot_inst_get, - Field_op1_Slot_inst_get, - Field_op2_Slot_inst_get, - Field_r_Slot_inst_get, - Field_sa4_Slot_inst_get, - Field_sae4_Slot_inst_get, - Field_sae_Slot_inst_get, - Field_sal_Slot_inst_get, - Field_sargt_Slot_inst_get, - Field_sas4_Slot_inst_get, - Field_sas_Slot_inst_get, - Field_sr_Slot_inst_get, - Field_st_Slot_inst_get, - Field_thi3_Slot_inst_get, - Field_imm4_Slot_inst_get, - Field_mn_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst_get, - Field_s2_Slot_inst_get, - Field_r2_Slot_inst_get, - Field_t4_Slot_inst_get, - Field_s4_Slot_inst_get, - Field_r4_Slot_inst_get, - Field_t8_Slot_inst_get, - Field_s8_Slot_inst_get, - Field_r8_Slot_inst_get, - Field_xt_wbr15_imm_Slot_inst_get, - Field_xt_wbr18_imm_Slot_inst_get, - Field_ae_r3_Slot_inst_get, - Field_ae_s_non_samt_Slot_inst_get, - Field_ae_s3_Slot_inst_get, - Field_ae_r32_Slot_inst_get, - Field_ae_samt_s_t_Slot_inst_get, - Field_ae_r20_Slot_inst_get, - Field_ae_r10_Slot_inst_get, - Field_ae_s20_Slot_inst_get, - Field_ae_fld_ohba_Slot_inst_get, - Field_ae_fld_ohba2_Slot_inst_get, - 0, - Field_ftsf12_Slot_inst_get, - Field_ftsf13_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst_get, - Field_s3to1_Slot_inst_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst_set_field_fns[] = { - Field_t_Slot_inst_set, - Field_bbi4_Slot_inst_set, - Field_bbi_Slot_inst_set, - Field_imm12_Slot_inst_set, - Field_imm8_Slot_inst_set, - Field_s_Slot_inst_set, - Field_imm12b_Slot_inst_set, - Field_imm16_Slot_inst_set, - Field_m_Slot_inst_set, - Field_n_Slot_inst_set, - Field_offset_Slot_inst_set, - Field_op0_Slot_inst_set, - Field_op1_Slot_inst_set, - Field_op2_Slot_inst_set, - Field_r_Slot_inst_set, - Field_sa4_Slot_inst_set, - Field_sae4_Slot_inst_set, - Field_sae_Slot_inst_set, - Field_sal_Slot_inst_set, - Field_sargt_Slot_inst_set, - Field_sas4_Slot_inst_set, - Field_sas_Slot_inst_set, - Field_sr_Slot_inst_set, - Field_st_Slot_inst_set, - Field_thi3_Slot_inst_set, - Field_imm4_Slot_inst_set, - Field_mn_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst_set, - Field_s2_Slot_inst_set, - Field_r2_Slot_inst_set, - Field_t4_Slot_inst_set, - Field_s4_Slot_inst_set, - Field_r4_Slot_inst_set, - Field_t8_Slot_inst_set, - Field_s8_Slot_inst_set, - Field_r8_Slot_inst_set, - Field_xt_wbr15_imm_Slot_inst_set, - Field_xt_wbr18_imm_Slot_inst_set, - Field_ae_r3_Slot_inst_set, - Field_ae_s_non_samt_Slot_inst_set, - Field_ae_s3_Slot_inst_set, - Field_ae_r32_Slot_inst_set, - Field_ae_samt_s_t_Slot_inst_set, - Field_ae_r20_Slot_inst_set, - Field_ae_r10_Slot_inst_set, - Field_ae_s20_Slot_inst_set, - Field_ae_fld_ohba_Slot_inst_set, - Field_ae_fld_ohba2_Slot_inst_set, - 0, - Field_ftsf12_Slot_inst_set, - Field_ftsf13_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst_set, - Field_s3to1_Slot_inst_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16a_get_field_fns[] = { - Field_t_Slot_inst16a_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_get, - 0, - 0, - Field_r_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_get, - Field_st_Slot_inst16a_get, - 0, - Field_imm4_Slot_inst16a_get, - 0, - Field_i_Slot_inst16a_get, - Field_imm6lo_Slot_inst16a_get, - Field_imm6hi_Slot_inst16a_get, - Field_imm7lo_Slot_inst16a_get, - Field_imm7hi_Slot_inst16a_get, - Field_z_Slot_inst16a_get, - Field_imm6_Slot_inst16a_get, - Field_imm7_Slot_inst16a_get, - Field_t2_Slot_inst16a_get, - Field_s2_Slot_inst16a_get, - Field_r2_Slot_inst16a_get, - Field_t4_Slot_inst16a_get, - Field_s4_Slot_inst16a_get, - Field_r4_Slot_inst16a_get, - Field_t8_Slot_inst16a_get, - Field_s8_Slot_inst16a_get, - Field_r8_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16a_get, - Field_s3to1_Slot_inst16a_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst16a_set_field_fns[] = { - Field_t_Slot_inst16a_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_set, - 0, - 0, - Field_r_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_set, - Field_st_Slot_inst16a_set, - 0, - Field_imm4_Slot_inst16a_set, - 0, - Field_i_Slot_inst16a_set, - Field_imm6lo_Slot_inst16a_set, - Field_imm6hi_Slot_inst16a_set, - Field_imm7lo_Slot_inst16a_set, - Field_imm7hi_Slot_inst16a_set, - Field_z_Slot_inst16a_set, - Field_imm6_Slot_inst16a_set, - Field_imm7_Slot_inst16a_set, - Field_t2_Slot_inst16a_set, - Field_s2_Slot_inst16a_set, - Field_r2_Slot_inst16a_set, - Field_t4_Slot_inst16a_set, - Field_s4_Slot_inst16a_set, - Field_r4_Slot_inst16a_set, - Field_t8_Slot_inst16a_set, - Field_s8_Slot_inst16a_set, - Field_r8_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16a_set, - Field_s3to1_Slot_inst16a_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16b_get_field_fns[] = { - Field_t_Slot_inst16b_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_get, - 0, - 0, - Field_r_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_get, - Field_st_Slot_inst16b_get, - 0, - Field_imm4_Slot_inst16b_get, - 0, - Field_i_Slot_inst16b_get, - Field_imm6lo_Slot_inst16b_get, - Field_imm6hi_Slot_inst16b_get, - Field_imm7lo_Slot_inst16b_get, - Field_imm7hi_Slot_inst16b_get, - Field_z_Slot_inst16b_get, - Field_imm6_Slot_inst16b_get, - Field_imm7_Slot_inst16b_get, - Field_t2_Slot_inst16b_get, - Field_s2_Slot_inst16b_get, - Field_r2_Slot_inst16b_get, - Field_t4_Slot_inst16b_get, - Field_s4_Slot_inst16b_get, - Field_r4_Slot_inst16b_get, - Field_t8_Slot_inst16b_get, - Field_s8_Slot_inst16b_get, - Field_r8_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16b_get, - Field_s3to1_Slot_inst16b_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst16b_set_field_fns[] = { - Field_t_Slot_inst16b_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_set, - 0, - 0, - Field_r_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_set, - Field_st_Slot_inst16b_set, - 0, - Field_imm4_Slot_inst16b_set, - 0, - Field_i_Slot_inst16b_set, - Field_imm6lo_Slot_inst16b_set, - Field_imm6hi_Slot_inst16b_set, - Field_imm7lo_Slot_inst16b_set, - Field_imm7hi_Slot_inst16b_set, - Field_z_Slot_inst16b_set, - Field_imm6_Slot_inst16b_set, - Field_imm7_Slot_inst16b_set, - Field_t2_Slot_inst16b_set, - Field_s2_Slot_inst16b_set, - Field_r2_Slot_inst16b_set, - Field_t4_Slot_inst16b_set, - Field_s4_Slot_inst16b_set, - Field_r4_Slot_inst16b_set, - Field_t8_Slot_inst16b_set, - Field_s8_Slot_inst16b_set, - Field_r8_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16b_set, - Field_s3to1_Slot_inst16b_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_ae_slot1_get_field_fns[] = { - Field_t_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot1_get, - 0, - Field_ae_r20_Slot_ae_slot1_get, - Field_ae_r10_Slot_ae_slot1_get, - Field_ae_s20_Slot_ae_slot1_get, - 0, - 0, - Field_op0_s3_Slot_ae_slot1_get, - Field_ftsf12_Slot_ae_slot1_get, - Field_ftsf13_Slot_ae_slot1_get, - Field_ftsf14_Slot_ae_slot1_get, - Field_ftsf21ae_slot1_Slot_ae_slot1_get, - Field_ftsf22ae_slot1_Slot_ae_slot1_get, - Field_ftsf23ae_slot1_Slot_ae_slot1_get, - Field_ftsf24ae_slot1_Slot_ae_slot1_get, - Field_ftsf25ae_slot1_Slot_ae_slot1_get, - Field_ftsf26ae_slot1_Slot_ae_slot1_get, - Field_ftsf27ae_slot1_Slot_ae_slot1_get, - Field_ftsf28ae_slot1_Slot_ae_slot1_get, - Field_ftsf29ae_slot1_Slot_ae_slot1_get, - Field_ftsf30ae_slot1_Slot_ae_slot1_get, - Field_ftsf31ae_slot1_Slot_ae_slot1_get, - Field_ftsf32ae_slot1_Slot_ae_slot1_get, - Field_ftsf33ae_slot1_Slot_ae_slot1_get, - Field_ftsf34ae_slot1_Slot_ae_slot1_get, - Field_ftsf35ae_slot1_Slot_ae_slot1_get, - Field_ftsf36ae_slot1_Slot_ae_slot1_get, - Field_ftsf37ae_slot1_Slot_ae_slot1_get, - Field_ftsf38ae_slot1_Slot_ae_slot1_get, - Field_ftsf39ae_slot1_Slot_ae_slot1_get, - Field_ftsf40ae_slot1_Slot_ae_slot1_get, - Field_ftsf41ae_slot1_Slot_ae_slot1_get, - Field_ftsf42ae_slot1_Slot_ae_slot1_get, - Field_ftsf43ae_slot1_Slot_ae_slot1_get, - Field_ftsf44ae_slot1_Slot_ae_slot1_get, - Field_ftsf45ae_slot1_Slot_ae_slot1_get, - Field_ftsf46ae_slot1_Slot_ae_slot1_get, - Field_ftsf47ae_slot1_Slot_ae_slot1_get, - Field_ftsf48ae_slot1_Slot_ae_slot1_get, - Field_ftsf49ae_slot1_Slot_ae_slot1_get, - Field_ftsf50ae_slot1_Slot_ae_slot1_get, - Field_ftsf51ae_slot1_Slot_ae_slot1_get, - Field_ftsf52ae_slot1_Slot_ae_slot1_get, - Field_ftsf53ae_slot1_Slot_ae_slot1_get, - Field_ftsf54ae_slot1_Slot_ae_slot1_get, - Field_ftsf55ae_slot1_Slot_ae_slot1_get, - Field_ftsf56ae_slot1_Slot_ae_slot1_get, - Field_ftsf57ae_slot1_Slot_ae_slot1_get, - Field_ftsf58ae_slot1_Slot_ae_slot1_get, - Field_ftsf59ae_slot1_Slot_ae_slot1_get, - Field_ftsf60ae_slot1_Slot_ae_slot1_get, - Field_ftsf61ae_slot1_Slot_ae_slot1_get, - Field_ftsf63ae_slot1_Slot_ae_slot1_get, - Field_ftsf64ae_slot1_Slot_ae_slot1_get, - Field_ftsf66ae_slot1_Slot_ae_slot1_get, - Field_ftsf67ae_slot1_Slot_ae_slot1_get, - Field_ftsf69ae_slot1_Slot_ae_slot1_get, - Field_ftsf71ae_slot1_Slot_ae_slot1_get, - Field_ftsf72ae_slot1_Slot_ae_slot1_get, - Field_ftsf73ae_slot1_Slot_ae_slot1_get, - Field_ftsf75ae_slot1_Slot_ae_slot1_get, - Field_ftsf76ae_slot1_Slot_ae_slot1_get, - Field_ftsf77ae_slot1_Slot_ae_slot1_get, - Field_ftsf78ae_slot1_Slot_ae_slot1_get, - Field_ftsf79ae_slot1_Slot_ae_slot1_get, - Field_ftsf80ae_slot1_Slot_ae_slot1_get, - Field_ftsf81ae_slot1_Slot_ae_slot1_get, - Field_ftsf82ae_slot1_Slot_ae_slot1_get, - Field_ftsf84ae_slot1_Slot_ae_slot1_get, - Field_ftsf86ae_slot1_Slot_ae_slot1_get, - Field_ftsf87ae_slot1_Slot_ae_slot1_get, - Field_ftsf88ae_slot1_Slot_ae_slot1_get, - Field_ftsf89ae_slot1_Slot_ae_slot1_get, - Field_ftsf90ae_slot1_Slot_ae_slot1_get, - Field_ftsf91ae_slot1_Slot_ae_slot1_get, - Field_ftsf92ae_slot1_Slot_ae_slot1_get, - Field_ftsf94ae_slot1_Slot_ae_slot1_get, - Field_ftsf96ae_slot1_Slot_ae_slot1_get, - Field_ftsf97ae_slot1_Slot_ae_slot1_get, - Field_ftsf98ae_slot1_Slot_ae_slot1_get, - Field_ftsf99ae_slot1_Slot_ae_slot1_get, - Field_ftsf100ae_slot1_Slot_ae_slot1_get, - Field_ftsf101ae_slot1_Slot_ae_slot1_get, - Field_ftsf103ae_slot1_Slot_ae_slot1_get, - Field_ftsf104ae_slot1_Slot_ae_slot1_get, - Field_ftsf105ae_slot1_Slot_ae_slot1_get, - Field_ftsf106ae_slot1_Slot_ae_slot1_get, - Field_ftsf107ae_slot1_Slot_ae_slot1_get, - Field_ftsf108ae_slot1_Slot_ae_slot1_get, - Field_ftsf109ae_slot1_Slot_ae_slot1_get, - Field_ftsf110ae_slot1_Slot_ae_slot1_get, - Field_ftsf111ae_slot1_Slot_ae_slot1_get, - Field_ftsf112ae_slot1_Slot_ae_slot1_get, - Field_ftsf113ae_slot1_Slot_ae_slot1_get, - Field_ftsf114ae_slot1_Slot_ae_slot1_get, - Field_ftsf115ae_slot1_Slot_ae_slot1_get, - Field_ftsf116ae_slot1_Slot_ae_slot1_get, - Field_ftsf118ae_slot1_Slot_ae_slot1_get, - Field_ftsf119ae_slot1_Slot_ae_slot1_get, - Field_ftsf120ae_slot1_Slot_ae_slot1_get, - Field_ftsf122ae_slot1_Slot_ae_slot1_get, - Field_ftsf124ae_slot1_Slot_ae_slot1_get, - Field_ftsf125ae_slot1_Slot_ae_slot1_get, - Field_ftsf126ae_slot1_Slot_ae_slot1_get, - Field_ftsf127ae_slot1_Slot_ae_slot1_get, - Field_ftsf128ae_slot1_Slot_ae_slot1_get, - Field_ftsf129ae_slot1_Slot_ae_slot1_get, - Field_ftsf130ae_slot1_Slot_ae_slot1_get, - Field_ftsf131ae_slot1_Slot_ae_slot1_get, - Field_ftsf132ae_slot1_Slot_ae_slot1_get, - Field_ftsf133ae_slot1_Slot_ae_slot1_get, - Field_ftsf134ae_slot1_Slot_ae_slot1_get, - Field_ftsf135ae_slot1_Slot_ae_slot1_get, - Field_ftsf136ae_slot1_Slot_ae_slot1_get, - Field_ftsf137ae_slot1_Slot_ae_slot1_get, - Field_ftsf138ae_slot1_Slot_ae_slot1_get, - Field_ftsf139ae_slot1_Slot_ae_slot1_get, - Field_ftsf140ae_slot1_Slot_ae_slot1_get, - Field_ftsf141ae_slot1_Slot_ae_slot1_get, - Field_ftsf142ae_slot1_Slot_ae_slot1_get, - Field_ftsf143ae_slot1_Slot_ae_slot1_get, - Field_ftsf144ae_slot1_Slot_ae_slot1_get, - Field_ftsf145ae_slot1_Slot_ae_slot1_get, - Field_ftsf146ae_slot1_Slot_ae_slot1_get, - Field_ftsf147ae_slot1_Slot_ae_slot1_get, - Field_ftsf148ae_slot1_Slot_ae_slot1_get, - Field_ftsf149ae_slot1_Slot_ae_slot1_get, - Field_ftsf150ae_slot1_Slot_ae_slot1_get, - Field_ftsf151ae_slot1_Slot_ae_slot1_get, - Field_ftsf152ae_slot1_Slot_ae_slot1_get, - Field_ftsf153ae_slot1_Slot_ae_slot1_get, - Field_ftsf154ae_slot1_Slot_ae_slot1_get, - Field_ftsf155ae_slot1_Slot_ae_slot1_get, - Field_ftsf156ae_slot1_Slot_ae_slot1_get, - Field_ftsf157ae_slot1_Slot_ae_slot1_get, - Field_ftsf158ae_slot1_Slot_ae_slot1_get, - Field_ftsf159ae_slot1_Slot_ae_slot1_get, - Field_ftsf160ae_slot1_Slot_ae_slot1_get, - Field_ftsf161ae_slot1_Slot_ae_slot1_get, - Field_ftsf162ae_slot1_Slot_ae_slot1_get, - Field_ftsf163ae_slot1_Slot_ae_slot1_get, - Field_ftsf164ae_slot1_Slot_ae_slot1_get, - Field_ftsf165ae_slot1_Slot_ae_slot1_get, - Field_ftsf166ae_slot1_Slot_ae_slot1_get, - Field_ftsf167ae_slot1_Slot_ae_slot1_get, - Field_ftsf168ae_slot1_Slot_ae_slot1_get, - Field_ftsf169ae_slot1_Slot_ae_slot1_get, - Field_ftsf170ae_slot1_Slot_ae_slot1_get, - Field_ftsf171ae_slot1_Slot_ae_slot1_get, - Field_ftsf172ae_slot1_Slot_ae_slot1_get, - Field_ftsf173ae_slot1_Slot_ae_slot1_get, - Field_ftsf174ae_slot1_Slot_ae_slot1_get, - Field_ftsf175ae_slot1_Slot_ae_slot1_get, - Field_ftsf176ae_slot1_Slot_ae_slot1_get, - Field_ftsf177ae_slot1_Slot_ae_slot1_get, - Field_ftsf178ae_slot1_Slot_ae_slot1_get, - Field_ftsf179ae_slot1_Slot_ae_slot1_get, - Field_ftsf180ae_slot1_Slot_ae_slot1_get, - Field_ftsf181ae_slot1_Slot_ae_slot1_get, - Field_ftsf182ae_slot1_Slot_ae_slot1_get, - Field_ftsf183ae_slot1_Slot_ae_slot1_get, - Field_ftsf184ae_slot1_Slot_ae_slot1_get, - Field_ftsf185ae_slot1_Slot_ae_slot1_get, - Field_ftsf186ae_slot1_Slot_ae_slot1_get, - Field_ftsf187ae_slot1_Slot_ae_slot1_get, - Field_ftsf188ae_slot1_Slot_ae_slot1_get, - Field_ftsf189ae_slot1_Slot_ae_slot1_get, - Field_ftsf190ae_slot1_Slot_ae_slot1_get, - Field_ftsf191ae_slot1_Slot_ae_slot1_get, - Field_ftsf192ae_slot1_Slot_ae_slot1_get, - Field_ftsf193ae_slot1_Slot_ae_slot1_get, - Field_ftsf194ae_slot1_Slot_ae_slot1_get, - Field_ftsf195ae_slot1_Slot_ae_slot1_get, - Field_ftsf196ae_slot1_Slot_ae_slot1_get, - Field_ftsf197ae_slot1_Slot_ae_slot1_get, - Field_ftsf198ae_slot1_Slot_ae_slot1_get, - Field_ftsf199ae_slot1_Slot_ae_slot1_get, - Field_ftsf200ae_slot1_Slot_ae_slot1_get, - Field_ftsf201ae_slot1_Slot_ae_slot1_get, - Field_ftsf202ae_slot1_Slot_ae_slot1_get, - Field_ftsf203ae_slot1_Slot_ae_slot1_get, - Field_ftsf204ae_slot1_Slot_ae_slot1_get, - Field_ftsf205ae_slot1_Slot_ae_slot1_get, - Field_ftsf206ae_slot1_Slot_ae_slot1_get, - Field_ftsf207ae_slot1_Slot_ae_slot1_get, - Field_ftsf208_Slot_ae_slot1_get, - Field_ftsf209ae_slot1_Slot_ae_slot1_get, - Field_ftsf210ae_slot1_Slot_ae_slot1_get, - Field_ftsf211ae_slot1_Slot_ae_slot1_get, - Field_ftsf330ae_slot1_Slot_ae_slot1_get, - Field_ftsf332ae_slot1_Slot_ae_slot1_get, - Field_ftsf334ae_slot1_Slot_ae_slot1_get, - Field_ftsf336ae_slot1_Slot_ae_slot1_get, - Field_ftsf337ae_slot1_Slot_ae_slot1_get, - Field_ftsf338_Slot_ae_slot1_get, - Field_ftsf339ae_slot1_Slot_ae_slot1_get, - Field_ftsf340_Slot_ae_slot1_get, - Field_ftsf341ae_slot1_Slot_ae_slot1_get, - Field_ftsf342ae_slot1_Slot_ae_slot1_get, - Field_ftsf343ae_slot1_Slot_ae_slot1_get, - Field_ftsf344ae_slot1_Slot_ae_slot1_get, - Field_ftsf346ae_slot1_Slot_ae_slot1_get, - Field_ftsf347_Slot_ae_slot1_get, - Field_ftsf348ae_slot1_Slot_ae_slot1_get, - Field_ftsf349ae_slot1_Slot_ae_slot1_get, - Field_ftsf350ae_slot1_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_mul32x24fld_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_combined1b97e84f_fld54_Slot_ae_slot1_get, - Field_combined1b97e84f_fld17_Slot_ae_slot1_get, - Field_combined1b97e84f_fld76_Slot_ae_slot1_get, - Field_combined1b97e84f_fld73_Slot_ae_slot1_get, - Field_combined1b97e84f_fld62_Slot_ae_slot1_get, - Field_combined1b97e84f_fld24_Slot_ae_slot1_get, - Field_combined1b97e84f_fld70_Slot_ae_slot1_get, - Field_combined1b97e84f_fld58_Slot_ae_slot1_get, - Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_get, - Field_op0_s3_s3_Slot_ae_slot1_get, - Field_combined1b97e84f_fld49_Slot_ae_slot1_get, - Field_combined1b97e84f_fld51_Slot_ae_slot1_get, - Field_combined1b97e84f_fld23_Slot_ae_slot1_get, - Field_xt_fld0_Slot_ae_slot1_get, - Field_xt_fld1_Slot_ae_slot1_get, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_ae_slot1_set_field_fns[] = { - Field_t_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot1_set, - 0, - Field_ae_r20_Slot_ae_slot1_set, - Field_ae_r10_Slot_ae_slot1_set, - Field_ae_s20_Slot_ae_slot1_set, - 0, - 0, - Field_op0_s3_Slot_ae_slot1_set, - Field_ftsf12_Slot_ae_slot1_set, - Field_ftsf13_Slot_ae_slot1_set, - Field_ftsf14_Slot_ae_slot1_set, - Field_ftsf21ae_slot1_Slot_ae_slot1_set, - Field_ftsf22ae_slot1_Slot_ae_slot1_set, - Field_ftsf23ae_slot1_Slot_ae_slot1_set, - Field_ftsf24ae_slot1_Slot_ae_slot1_set, - Field_ftsf25ae_slot1_Slot_ae_slot1_set, - Field_ftsf26ae_slot1_Slot_ae_slot1_set, - Field_ftsf27ae_slot1_Slot_ae_slot1_set, - Field_ftsf28ae_slot1_Slot_ae_slot1_set, - Field_ftsf29ae_slot1_Slot_ae_slot1_set, - Field_ftsf30ae_slot1_Slot_ae_slot1_set, - Field_ftsf31ae_slot1_Slot_ae_slot1_set, - Field_ftsf32ae_slot1_Slot_ae_slot1_set, - Field_ftsf33ae_slot1_Slot_ae_slot1_set, - Field_ftsf34ae_slot1_Slot_ae_slot1_set, - Field_ftsf35ae_slot1_Slot_ae_slot1_set, - Field_ftsf36ae_slot1_Slot_ae_slot1_set, - Field_ftsf37ae_slot1_Slot_ae_slot1_set, - Field_ftsf38ae_slot1_Slot_ae_slot1_set, - Field_ftsf39ae_slot1_Slot_ae_slot1_set, - Field_ftsf40ae_slot1_Slot_ae_slot1_set, - Field_ftsf41ae_slot1_Slot_ae_slot1_set, - Field_ftsf42ae_slot1_Slot_ae_slot1_set, - Field_ftsf43ae_slot1_Slot_ae_slot1_set, - Field_ftsf44ae_slot1_Slot_ae_slot1_set, - Field_ftsf45ae_slot1_Slot_ae_slot1_set, - Field_ftsf46ae_slot1_Slot_ae_slot1_set, - Field_ftsf47ae_slot1_Slot_ae_slot1_set, - Field_ftsf48ae_slot1_Slot_ae_slot1_set, - Field_ftsf49ae_slot1_Slot_ae_slot1_set, - Field_ftsf50ae_slot1_Slot_ae_slot1_set, - Field_ftsf51ae_slot1_Slot_ae_slot1_set, - Field_ftsf52ae_slot1_Slot_ae_slot1_set, - Field_ftsf53ae_slot1_Slot_ae_slot1_set, - Field_ftsf54ae_slot1_Slot_ae_slot1_set, - Field_ftsf55ae_slot1_Slot_ae_slot1_set, - Field_ftsf56ae_slot1_Slot_ae_slot1_set, - Field_ftsf57ae_slot1_Slot_ae_slot1_set, - Field_ftsf58ae_slot1_Slot_ae_slot1_set, - Field_ftsf59ae_slot1_Slot_ae_slot1_set, - Field_ftsf60ae_slot1_Slot_ae_slot1_set, - Field_ftsf61ae_slot1_Slot_ae_slot1_set, - Field_ftsf63ae_slot1_Slot_ae_slot1_set, - Field_ftsf64ae_slot1_Slot_ae_slot1_set, - Field_ftsf66ae_slot1_Slot_ae_slot1_set, - Field_ftsf67ae_slot1_Slot_ae_slot1_set, - Field_ftsf69ae_slot1_Slot_ae_slot1_set, - Field_ftsf71ae_slot1_Slot_ae_slot1_set, - Field_ftsf72ae_slot1_Slot_ae_slot1_set, - Field_ftsf73ae_slot1_Slot_ae_slot1_set, - Field_ftsf75ae_slot1_Slot_ae_slot1_set, - Field_ftsf76ae_slot1_Slot_ae_slot1_set, - Field_ftsf77ae_slot1_Slot_ae_slot1_set, - Field_ftsf78ae_slot1_Slot_ae_slot1_set, - Field_ftsf79ae_slot1_Slot_ae_slot1_set, - Field_ftsf80ae_slot1_Slot_ae_slot1_set, - Field_ftsf81ae_slot1_Slot_ae_slot1_set, - Field_ftsf82ae_slot1_Slot_ae_slot1_set, - Field_ftsf84ae_slot1_Slot_ae_slot1_set, - Field_ftsf86ae_slot1_Slot_ae_slot1_set, - Field_ftsf87ae_slot1_Slot_ae_slot1_set, - Field_ftsf88ae_slot1_Slot_ae_slot1_set, - Field_ftsf89ae_slot1_Slot_ae_slot1_set, - Field_ftsf90ae_slot1_Slot_ae_slot1_set, - Field_ftsf91ae_slot1_Slot_ae_slot1_set, - Field_ftsf92ae_slot1_Slot_ae_slot1_set, - Field_ftsf94ae_slot1_Slot_ae_slot1_set, - Field_ftsf96ae_slot1_Slot_ae_slot1_set, - Field_ftsf97ae_slot1_Slot_ae_slot1_set, - Field_ftsf98ae_slot1_Slot_ae_slot1_set, - Field_ftsf99ae_slot1_Slot_ae_slot1_set, - Field_ftsf100ae_slot1_Slot_ae_slot1_set, - Field_ftsf101ae_slot1_Slot_ae_slot1_set, - Field_ftsf103ae_slot1_Slot_ae_slot1_set, - Field_ftsf104ae_slot1_Slot_ae_slot1_set, - Field_ftsf105ae_slot1_Slot_ae_slot1_set, - Field_ftsf106ae_slot1_Slot_ae_slot1_set, - Field_ftsf107ae_slot1_Slot_ae_slot1_set, - Field_ftsf108ae_slot1_Slot_ae_slot1_set, - Field_ftsf109ae_slot1_Slot_ae_slot1_set, - Field_ftsf110ae_slot1_Slot_ae_slot1_set, - Field_ftsf111ae_slot1_Slot_ae_slot1_set, - Field_ftsf112ae_slot1_Slot_ae_slot1_set, - Field_ftsf113ae_slot1_Slot_ae_slot1_set, - Field_ftsf114ae_slot1_Slot_ae_slot1_set, - Field_ftsf115ae_slot1_Slot_ae_slot1_set, - Field_ftsf116ae_slot1_Slot_ae_slot1_set, - Field_ftsf118ae_slot1_Slot_ae_slot1_set, - Field_ftsf119ae_slot1_Slot_ae_slot1_set, - Field_ftsf120ae_slot1_Slot_ae_slot1_set, - Field_ftsf122ae_slot1_Slot_ae_slot1_set, - Field_ftsf124ae_slot1_Slot_ae_slot1_set, - Field_ftsf125ae_slot1_Slot_ae_slot1_set, - Field_ftsf126ae_slot1_Slot_ae_slot1_set, - Field_ftsf127ae_slot1_Slot_ae_slot1_set, - Field_ftsf128ae_slot1_Slot_ae_slot1_set, - Field_ftsf129ae_slot1_Slot_ae_slot1_set, - Field_ftsf130ae_slot1_Slot_ae_slot1_set, - Field_ftsf131ae_slot1_Slot_ae_slot1_set, - Field_ftsf132ae_slot1_Slot_ae_slot1_set, - Field_ftsf133ae_slot1_Slot_ae_slot1_set, - Field_ftsf134ae_slot1_Slot_ae_slot1_set, - Field_ftsf135ae_slot1_Slot_ae_slot1_set, - Field_ftsf136ae_slot1_Slot_ae_slot1_set, - Field_ftsf137ae_slot1_Slot_ae_slot1_set, - Field_ftsf138ae_slot1_Slot_ae_slot1_set, - Field_ftsf139ae_slot1_Slot_ae_slot1_set, - Field_ftsf140ae_slot1_Slot_ae_slot1_set, - Field_ftsf141ae_slot1_Slot_ae_slot1_set, - Field_ftsf142ae_slot1_Slot_ae_slot1_set, - Field_ftsf143ae_slot1_Slot_ae_slot1_set, - Field_ftsf144ae_slot1_Slot_ae_slot1_set, - Field_ftsf145ae_slot1_Slot_ae_slot1_set, - Field_ftsf146ae_slot1_Slot_ae_slot1_set, - Field_ftsf147ae_slot1_Slot_ae_slot1_set, - Field_ftsf148ae_slot1_Slot_ae_slot1_set, - Field_ftsf149ae_slot1_Slot_ae_slot1_set, - Field_ftsf150ae_slot1_Slot_ae_slot1_set, - Field_ftsf151ae_slot1_Slot_ae_slot1_set, - Field_ftsf152ae_slot1_Slot_ae_slot1_set, - Field_ftsf153ae_slot1_Slot_ae_slot1_set, - Field_ftsf154ae_slot1_Slot_ae_slot1_set, - Field_ftsf155ae_slot1_Slot_ae_slot1_set, - Field_ftsf156ae_slot1_Slot_ae_slot1_set, - Field_ftsf157ae_slot1_Slot_ae_slot1_set, - Field_ftsf158ae_slot1_Slot_ae_slot1_set, - Field_ftsf159ae_slot1_Slot_ae_slot1_set, - Field_ftsf160ae_slot1_Slot_ae_slot1_set, - Field_ftsf161ae_slot1_Slot_ae_slot1_set, - Field_ftsf162ae_slot1_Slot_ae_slot1_set, - Field_ftsf163ae_slot1_Slot_ae_slot1_set, - Field_ftsf164ae_slot1_Slot_ae_slot1_set, - Field_ftsf165ae_slot1_Slot_ae_slot1_set, - Field_ftsf166ae_slot1_Slot_ae_slot1_set, - Field_ftsf167ae_slot1_Slot_ae_slot1_set, - Field_ftsf168ae_slot1_Slot_ae_slot1_set, - Field_ftsf169ae_slot1_Slot_ae_slot1_set, - Field_ftsf170ae_slot1_Slot_ae_slot1_set, - Field_ftsf171ae_slot1_Slot_ae_slot1_set, - Field_ftsf172ae_slot1_Slot_ae_slot1_set, - Field_ftsf173ae_slot1_Slot_ae_slot1_set, - Field_ftsf174ae_slot1_Slot_ae_slot1_set, - Field_ftsf175ae_slot1_Slot_ae_slot1_set, - Field_ftsf176ae_slot1_Slot_ae_slot1_set, - Field_ftsf177ae_slot1_Slot_ae_slot1_set, - Field_ftsf178ae_slot1_Slot_ae_slot1_set, - Field_ftsf179ae_slot1_Slot_ae_slot1_set, - Field_ftsf180ae_slot1_Slot_ae_slot1_set, - Field_ftsf181ae_slot1_Slot_ae_slot1_set, - Field_ftsf182ae_slot1_Slot_ae_slot1_set, - Field_ftsf183ae_slot1_Slot_ae_slot1_set, - Field_ftsf184ae_slot1_Slot_ae_slot1_set, - Field_ftsf185ae_slot1_Slot_ae_slot1_set, - Field_ftsf186ae_slot1_Slot_ae_slot1_set, - Field_ftsf187ae_slot1_Slot_ae_slot1_set, - Field_ftsf188ae_slot1_Slot_ae_slot1_set, - Field_ftsf189ae_slot1_Slot_ae_slot1_set, - Field_ftsf190ae_slot1_Slot_ae_slot1_set, - Field_ftsf191ae_slot1_Slot_ae_slot1_set, - Field_ftsf192ae_slot1_Slot_ae_slot1_set, - Field_ftsf193ae_slot1_Slot_ae_slot1_set, - Field_ftsf194ae_slot1_Slot_ae_slot1_set, - Field_ftsf195ae_slot1_Slot_ae_slot1_set, - Field_ftsf196ae_slot1_Slot_ae_slot1_set, - Field_ftsf197ae_slot1_Slot_ae_slot1_set, - Field_ftsf198ae_slot1_Slot_ae_slot1_set, - Field_ftsf199ae_slot1_Slot_ae_slot1_set, - Field_ftsf200ae_slot1_Slot_ae_slot1_set, - Field_ftsf201ae_slot1_Slot_ae_slot1_set, - Field_ftsf202ae_slot1_Slot_ae_slot1_set, - Field_ftsf203ae_slot1_Slot_ae_slot1_set, - Field_ftsf204ae_slot1_Slot_ae_slot1_set, - Field_ftsf205ae_slot1_Slot_ae_slot1_set, - Field_ftsf206ae_slot1_Slot_ae_slot1_set, - Field_ftsf207ae_slot1_Slot_ae_slot1_set, - Field_ftsf208_Slot_ae_slot1_set, - Field_ftsf209ae_slot1_Slot_ae_slot1_set, - Field_ftsf210ae_slot1_Slot_ae_slot1_set, - Field_ftsf211ae_slot1_Slot_ae_slot1_set, - Field_ftsf330ae_slot1_Slot_ae_slot1_set, - Field_ftsf332ae_slot1_Slot_ae_slot1_set, - Field_ftsf334ae_slot1_Slot_ae_slot1_set, - Field_ftsf336ae_slot1_Slot_ae_slot1_set, - Field_ftsf337ae_slot1_Slot_ae_slot1_set, - Field_ftsf338_Slot_ae_slot1_set, - Field_ftsf339ae_slot1_Slot_ae_slot1_set, - Field_ftsf340_Slot_ae_slot1_set, - Field_ftsf341ae_slot1_Slot_ae_slot1_set, - Field_ftsf342ae_slot1_Slot_ae_slot1_set, - Field_ftsf343ae_slot1_Slot_ae_slot1_set, - Field_ftsf344ae_slot1_Slot_ae_slot1_set, - Field_ftsf346ae_slot1_Slot_ae_slot1_set, - Field_ftsf347_Slot_ae_slot1_set, - Field_ftsf348ae_slot1_Slot_ae_slot1_set, - Field_ftsf349ae_slot1_Slot_ae_slot1_set, - Field_ftsf350ae_slot1_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_mul32x24fld_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_combined1b97e84f_fld54_Slot_ae_slot1_set, - Field_combined1b97e84f_fld17_Slot_ae_slot1_set, - Field_combined1b97e84f_fld76_Slot_ae_slot1_set, - Field_combined1b97e84f_fld73_Slot_ae_slot1_set, - Field_combined1b97e84f_fld62_Slot_ae_slot1_set, - Field_combined1b97e84f_fld24_Slot_ae_slot1_set, - Field_combined1b97e84f_fld70_Slot_ae_slot1_set, - Field_combined1b97e84f_fld58_Slot_ae_slot1_set, - Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_set, - Field_op0_s3_s3_Slot_ae_slot1_set, - Field_combined1b97e84f_fld49_Slot_ae_slot1_set, - Field_combined1b97e84f_fld51_Slot_ae_slot1_set, - Field_combined1b97e84f_fld23_Slot_ae_slot1_set, - Field_xt_fld0_Slot_ae_slot1_set, - Field_xt_fld1_Slot_ae_slot1_set, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_ae_slot0_get_field_fns[] = { - Field_t_Slot_ae_slot0_get, - 0, - Field_bbi_Slot_ae_slot0_get, - Field_imm12_Slot_ae_slot0_get, - Field_imm8_Slot_ae_slot0_get, - Field_s_Slot_ae_slot0_get, - Field_imm12b_Slot_ae_slot0_get, - Field_imm16_Slot_ae_slot0_get, - 0, - 0, - Field_offset_Slot_ae_slot0_get, - 0, - 0, - Field_op2_Slot_ae_slot0_get, - Field_r_Slot_ae_slot0_get, - 0, - 0, - Field_sae_Slot_ae_slot0_get, - Field_sal_Slot_ae_slot0_get, - Field_sargt_Slot_ae_slot0_get, - 0, - Field_sas_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_s4_Slot_ae_slot0_get, - 0, - 0, - Field_s8_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot0_get, - Field_ae_samt_s_t_Slot_ae_slot0_get, - Field_ae_r20_Slot_ae_slot0_get, - Field_ae_r10_Slot_ae_slot0_get, - Field_ae_s20_Slot_ae_slot0_get, - 0, - 0, - 0, - Field_ftsf12_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s4_Slot_ae_slot0_get, - Field_ftsf212ae_slot0_Slot_ae_slot0_get, - Field_ftsf213ae_slot0_Slot_ae_slot0_get, - Field_ftsf214ae_slot0_Slot_ae_slot0_get, - Field_ftsf215ae_slot0_Slot_ae_slot0_get, - Field_ftsf216ae_slot0_Slot_ae_slot0_get, - Field_ftsf217_Slot_ae_slot0_get, - Field_ftsf218ae_slot0_Slot_ae_slot0_get, - Field_ftsf219ae_slot0_Slot_ae_slot0_get, - Field_ftsf220ae_slot0_Slot_ae_slot0_get, - Field_ftsf221ae_slot0_Slot_ae_slot0_get, - Field_ftsf222ae_slot0_Slot_ae_slot0_get, - Field_ftsf223ae_slot0_Slot_ae_slot0_get, - Field_ftsf224ae_slot0_Slot_ae_slot0_get, - Field_ftsf225ae_slot0_Slot_ae_slot0_get, - Field_ftsf226ae_slot0_Slot_ae_slot0_get, - Field_ftsf227ae_slot0_Slot_ae_slot0_get, - Field_ftsf228ae_slot0_Slot_ae_slot0_get, - Field_ftsf229ae_slot0_Slot_ae_slot0_get, - Field_ftsf230ae_slot0_Slot_ae_slot0_get, - Field_ftsf231ae_slot0_Slot_ae_slot0_get, - Field_ftsf232ae_slot0_Slot_ae_slot0_get, - Field_ftsf233ae_slot0_Slot_ae_slot0_get, - Field_ftsf234ae_slot0_Slot_ae_slot0_get, - Field_ftsf235ae_slot0_Slot_ae_slot0_get, - Field_ftsf236ae_slot0_Slot_ae_slot0_get, - Field_ftsf237ae_slot0_Slot_ae_slot0_get, - Field_ftsf238ae_slot0_Slot_ae_slot0_get, - Field_ftsf239ae_slot0_Slot_ae_slot0_get, - Field_ftsf240ae_slot0_Slot_ae_slot0_get, - Field_ftsf241ae_slot0_Slot_ae_slot0_get, - Field_ftsf242ae_slot0_Slot_ae_slot0_get, - Field_ftsf243ae_slot0_Slot_ae_slot0_get, - Field_ftsf244ae_slot0_Slot_ae_slot0_get, - Field_ftsf245ae_slot0_Slot_ae_slot0_get, - Field_ftsf246ae_slot0_Slot_ae_slot0_get, - Field_ftsf247ae_slot0_Slot_ae_slot0_get, - Field_ftsf248ae_slot0_Slot_ae_slot0_get, - Field_ftsf249ae_slot0_Slot_ae_slot0_get, - Field_ftsf250ae_slot0_Slot_ae_slot0_get, - Field_ftsf251ae_slot0_Slot_ae_slot0_get, - Field_ftsf252ae_slot0_Slot_ae_slot0_get, - Field_ftsf253ae_slot0_Slot_ae_slot0_get, - Field_ftsf254ae_slot0_Slot_ae_slot0_get, - Field_ftsf255ae_slot0_Slot_ae_slot0_get, - Field_ftsf256ae_slot0_Slot_ae_slot0_get, - Field_ftsf257ae_slot0_Slot_ae_slot0_get, - Field_ftsf258ae_slot0_Slot_ae_slot0_get, - Field_ftsf259ae_slot0_Slot_ae_slot0_get, - Field_ftsf260ae_slot0_Slot_ae_slot0_get, - Field_ftsf261ae_slot0_Slot_ae_slot0_get, - Field_ftsf262ae_slot0_Slot_ae_slot0_get, - Field_ftsf263ae_slot0_Slot_ae_slot0_get, - Field_ftsf264ae_slot0_Slot_ae_slot0_get, - Field_ftsf265ae_slot0_Slot_ae_slot0_get, - Field_ftsf266ae_slot0_Slot_ae_slot0_get, - Field_ftsf267ae_slot0_Slot_ae_slot0_get, - Field_ftsf268ae_slot0_Slot_ae_slot0_get, - Field_ftsf269ae_slot0_Slot_ae_slot0_get, - Field_ftsf270ae_slot0_Slot_ae_slot0_get, - Field_ftsf271ae_slot0_Slot_ae_slot0_get, - Field_ftsf272ae_slot0_Slot_ae_slot0_get, - Field_ftsf273ae_slot0_Slot_ae_slot0_get, - Field_ftsf274ae_slot0_Slot_ae_slot0_get, - Field_ftsf275ae_slot0_Slot_ae_slot0_get, - Field_ftsf276ae_slot0_Slot_ae_slot0_get, - Field_ftsf277ae_slot0_Slot_ae_slot0_get, - Field_ftsf278ae_slot0_Slot_ae_slot0_get, - Field_ftsf279ae_slot0_Slot_ae_slot0_get, - Field_ftsf281ae_slot0_Slot_ae_slot0_get, - Field_ftsf282ae_slot0_Slot_ae_slot0_get, - Field_ftsf283ae_slot0_Slot_ae_slot0_get, - Field_ftsf284ae_slot0_Slot_ae_slot0_get, - Field_ftsf286ae_slot0_Slot_ae_slot0_get, - Field_ftsf288ae_slot0_Slot_ae_slot0_get, - Field_ftsf290ae_slot0_Slot_ae_slot0_get, - Field_ftsf292ae_slot0_Slot_ae_slot0_get, - Field_ftsf293_Slot_ae_slot0_get, - Field_ftsf294ae_slot0_Slot_ae_slot0_get, - Field_ftsf295ae_slot0_Slot_ae_slot0_get, - Field_ftsf296ae_slot0_Slot_ae_slot0_get, - Field_ftsf297ae_slot0_Slot_ae_slot0_get, - Field_ftsf298ae_slot0_Slot_ae_slot0_get, - Field_ftsf299ae_slot0_Slot_ae_slot0_get, - Field_ftsf300ae_slot0_Slot_ae_slot0_get, - Field_ftsf301ae_slot0_Slot_ae_slot0_get, - Field_ftsf302ae_slot0_Slot_ae_slot0_get, - Field_ftsf303ae_slot0_Slot_ae_slot0_get, - Field_ftsf304ae_slot0_Slot_ae_slot0_get, - Field_ftsf306ae_slot0_Slot_ae_slot0_get, - Field_ftsf308ae_slot0_Slot_ae_slot0_get, - Field_ftsf309ae_slot0_Slot_ae_slot0_get, - Field_ftsf310ae_slot0_Slot_ae_slot0_get, - Field_ftsf311ae_slot0_Slot_ae_slot0_get, - Field_ftsf312ae_slot0_Slot_ae_slot0_get, - Field_ftsf313ae_slot0_Slot_ae_slot0_get, - Field_ftsf314ae_slot0_Slot_ae_slot0_get, - Field_ftsf315ae_slot0_Slot_ae_slot0_get, - Field_ftsf316ae_slot0_Slot_ae_slot0_get, - Field_ftsf317ae_slot0_Slot_ae_slot0_get, - Field_ftsf318ae_slot0_Slot_ae_slot0_get, - Field_ftsf319_Slot_ae_slot0_get, - Field_ftsf320ae_slot0_Slot_ae_slot0_get, - Field_ftsf321_Slot_ae_slot0_get, - Field_ftsf322ae_slot0_Slot_ae_slot0_get, - Field_ftsf323ae_slot0_Slot_ae_slot0_get, - Field_ftsf324ae_slot0_Slot_ae_slot0_get, - Field_ftsf325ae_slot0_Slot_ae_slot0_get, - Field_ftsf326ae_slot0_Slot_ae_slot0_get, - Field_ftsf328ae_slot0_Slot_ae_slot0_get, - Field_ftsf329ae_slot0_Slot_ae_slot0_get, - Field_ftsf352ae_slot0_Slot_ae_slot0_get, - Field_ftsf353_Slot_ae_slot0_get, - Field_ftsf354ae_slot0_Slot_ae_slot0_get, - Field_ftsf356ae_slot0_Slot_ae_slot0_get, - Field_ftsf357_Slot_ae_slot0_get, - Field_ftsf358ae_slot0_Slot_ae_slot0_get, - Field_ftsf359ae_slot0_Slot_ae_slot0_get, - Field_ftsf360ae_slot0_Slot_ae_slot0_get, - Field_ftsf361ae_slot0_Slot_ae_slot0_get, - Field_ftsf362ae_slot0_Slot_ae_slot0_get, - Field_ftsf364ae_slot0_Slot_ae_slot0_get, - Field_ftsf365ae_slot0_Slot_ae_slot0_get, - Field_ftsf366ae_slot0_Slot_ae_slot0_get, - Field_ftsf368ae_slot0_Slot_ae_slot0_get, - Field_ftsf369ae_slot0_Slot_ae_slot0_get, - 0, - Field_combined1b97e84f_fld115_Slot_ae_slot0_get, - Field_combined1b97e84f_fld97_Slot_ae_slot0_get, - Field_combined1b97e84f_fld124_Slot_ae_slot0_get, - Field_combined1b97e84f_fld79_Slot_ae_slot0_get, - Field_combined1b97e84f_fld80_Slot_ae_slot0_get, - Field_combined1b97e84f_fld108_Slot_ae_slot0_get, - Field_combined1b97e84f_fld101_Slot_ae_slot0_get, - Field_combined1b97e84f_fld88_Slot_ae_slot0_get, - Field_combined1b97e84f_fld39_Slot_ae_slot0_get, - Field_op0_s4_s4_Slot_ae_slot0_get, - Field_combined1b97e84f_fld83_Slot_ae_slot0_get, - Field_combined1b97e84f_fld90_Slot_ae_slot0_get, - Field_combined1b97e84f_fld93_Slot_ae_slot0_get, - Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_get, - Field_combined4b12daa6_fld122_Slot_ae_slot0_get, - Field_combined4b12daa6_fld115_Slot_ae_slot0_get, - Field_combined4b12daa6_fld85_Slot_ae_slot0_get, - Field_combined4b12daa6_fld119_Slot_ae_slot0_get, - Field_combined4b12daa6_fld97_Slot_ae_slot0_get, - Field_combined4b12daa6_fld124_Slot_ae_slot0_get, - Field_combined4b12daa6_fld79_Slot_ae_slot0_get, - Field_combined4b12daa6_fld80_Slot_ae_slot0_get, - Field_combined4b12daa6_fld108_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_ae_slot0_get, - Field_s3to1_Slot_ae_slot0_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_ae_slot0_set_field_fns[] = { - Field_t_Slot_ae_slot0_set, - 0, - Field_bbi_Slot_ae_slot0_set, - Field_imm12_Slot_ae_slot0_set, - Field_imm8_Slot_ae_slot0_set, - Field_s_Slot_ae_slot0_set, - Field_imm12b_Slot_ae_slot0_set, - Field_imm16_Slot_ae_slot0_set, - 0, - 0, - Field_offset_Slot_ae_slot0_set, - 0, - 0, - Field_op2_Slot_ae_slot0_set, - Field_r_Slot_ae_slot0_set, - 0, - 0, - Field_sae_Slot_ae_slot0_set, - Field_sal_Slot_ae_slot0_set, - Field_sargt_Slot_ae_slot0_set, - 0, - Field_sas_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_s4_Slot_ae_slot0_set, - 0, - 0, - Field_s8_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot0_set, - Field_ae_samt_s_t_Slot_ae_slot0_set, - Field_ae_r20_Slot_ae_slot0_set, - Field_ae_r10_Slot_ae_slot0_set, - Field_ae_s20_Slot_ae_slot0_set, - 0, - 0, - 0, - Field_ftsf12_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s4_Slot_ae_slot0_set, - Field_ftsf212ae_slot0_Slot_ae_slot0_set, - Field_ftsf213ae_slot0_Slot_ae_slot0_set, - Field_ftsf214ae_slot0_Slot_ae_slot0_set, - Field_ftsf215ae_slot0_Slot_ae_slot0_set, - Field_ftsf216ae_slot0_Slot_ae_slot0_set, - Field_ftsf217_Slot_ae_slot0_set, - Field_ftsf218ae_slot0_Slot_ae_slot0_set, - Field_ftsf219ae_slot0_Slot_ae_slot0_set, - Field_ftsf220ae_slot0_Slot_ae_slot0_set, - Field_ftsf221ae_slot0_Slot_ae_slot0_set, - Field_ftsf222ae_slot0_Slot_ae_slot0_set, - Field_ftsf223ae_slot0_Slot_ae_slot0_set, - Field_ftsf224ae_slot0_Slot_ae_slot0_set, - Field_ftsf225ae_slot0_Slot_ae_slot0_set, - Field_ftsf226ae_slot0_Slot_ae_slot0_set, - Field_ftsf227ae_slot0_Slot_ae_slot0_set, - Field_ftsf228ae_slot0_Slot_ae_slot0_set, - Field_ftsf229ae_slot0_Slot_ae_slot0_set, - Field_ftsf230ae_slot0_Slot_ae_slot0_set, - Field_ftsf231ae_slot0_Slot_ae_slot0_set, - Field_ftsf232ae_slot0_Slot_ae_slot0_set, - Field_ftsf233ae_slot0_Slot_ae_slot0_set, - Field_ftsf234ae_slot0_Slot_ae_slot0_set, - Field_ftsf235ae_slot0_Slot_ae_slot0_set, - Field_ftsf236ae_slot0_Slot_ae_slot0_set, - Field_ftsf237ae_slot0_Slot_ae_slot0_set, - Field_ftsf238ae_slot0_Slot_ae_slot0_set, - Field_ftsf239ae_slot0_Slot_ae_slot0_set, - Field_ftsf240ae_slot0_Slot_ae_slot0_set, - Field_ftsf241ae_slot0_Slot_ae_slot0_set, - Field_ftsf242ae_slot0_Slot_ae_slot0_set, - Field_ftsf243ae_slot0_Slot_ae_slot0_set, - Field_ftsf244ae_slot0_Slot_ae_slot0_set, - Field_ftsf245ae_slot0_Slot_ae_slot0_set, - Field_ftsf246ae_slot0_Slot_ae_slot0_set, - Field_ftsf247ae_slot0_Slot_ae_slot0_set, - Field_ftsf248ae_slot0_Slot_ae_slot0_set, - Field_ftsf249ae_slot0_Slot_ae_slot0_set, - Field_ftsf250ae_slot0_Slot_ae_slot0_set, - Field_ftsf251ae_slot0_Slot_ae_slot0_set, - Field_ftsf252ae_slot0_Slot_ae_slot0_set, - Field_ftsf253ae_slot0_Slot_ae_slot0_set, - Field_ftsf254ae_slot0_Slot_ae_slot0_set, - Field_ftsf255ae_slot0_Slot_ae_slot0_set, - Field_ftsf256ae_slot0_Slot_ae_slot0_set, - Field_ftsf257ae_slot0_Slot_ae_slot0_set, - Field_ftsf258ae_slot0_Slot_ae_slot0_set, - Field_ftsf259ae_slot0_Slot_ae_slot0_set, - Field_ftsf260ae_slot0_Slot_ae_slot0_set, - Field_ftsf261ae_slot0_Slot_ae_slot0_set, - Field_ftsf262ae_slot0_Slot_ae_slot0_set, - Field_ftsf263ae_slot0_Slot_ae_slot0_set, - Field_ftsf264ae_slot0_Slot_ae_slot0_set, - Field_ftsf265ae_slot0_Slot_ae_slot0_set, - Field_ftsf266ae_slot0_Slot_ae_slot0_set, - Field_ftsf267ae_slot0_Slot_ae_slot0_set, - Field_ftsf268ae_slot0_Slot_ae_slot0_set, - Field_ftsf269ae_slot0_Slot_ae_slot0_set, - Field_ftsf270ae_slot0_Slot_ae_slot0_set, - Field_ftsf271ae_slot0_Slot_ae_slot0_set, - Field_ftsf272ae_slot0_Slot_ae_slot0_set, - Field_ftsf273ae_slot0_Slot_ae_slot0_set, - Field_ftsf274ae_slot0_Slot_ae_slot0_set, - Field_ftsf275ae_slot0_Slot_ae_slot0_set, - Field_ftsf276ae_slot0_Slot_ae_slot0_set, - Field_ftsf277ae_slot0_Slot_ae_slot0_set, - Field_ftsf278ae_slot0_Slot_ae_slot0_set, - Field_ftsf279ae_slot0_Slot_ae_slot0_set, - Field_ftsf281ae_slot0_Slot_ae_slot0_set, - Field_ftsf282ae_slot0_Slot_ae_slot0_set, - Field_ftsf283ae_slot0_Slot_ae_slot0_set, - Field_ftsf284ae_slot0_Slot_ae_slot0_set, - Field_ftsf286ae_slot0_Slot_ae_slot0_set, - Field_ftsf288ae_slot0_Slot_ae_slot0_set, - Field_ftsf290ae_slot0_Slot_ae_slot0_set, - Field_ftsf292ae_slot0_Slot_ae_slot0_set, - Field_ftsf293_Slot_ae_slot0_set, - Field_ftsf294ae_slot0_Slot_ae_slot0_set, - Field_ftsf295ae_slot0_Slot_ae_slot0_set, - Field_ftsf296ae_slot0_Slot_ae_slot0_set, - Field_ftsf297ae_slot0_Slot_ae_slot0_set, - Field_ftsf298ae_slot0_Slot_ae_slot0_set, - Field_ftsf299ae_slot0_Slot_ae_slot0_set, - Field_ftsf300ae_slot0_Slot_ae_slot0_set, - Field_ftsf301ae_slot0_Slot_ae_slot0_set, - Field_ftsf302ae_slot0_Slot_ae_slot0_set, - Field_ftsf303ae_slot0_Slot_ae_slot0_set, - Field_ftsf304ae_slot0_Slot_ae_slot0_set, - Field_ftsf306ae_slot0_Slot_ae_slot0_set, - Field_ftsf308ae_slot0_Slot_ae_slot0_set, - Field_ftsf309ae_slot0_Slot_ae_slot0_set, - Field_ftsf310ae_slot0_Slot_ae_slot0_set, - Field_ftsf311ae_slot0_Slot_ae_slot0_set, - Field_ftsf312ae_slot0_Slot_ae_slot0_set, - Field_ftsf313ae_slot0_Slot_ae_slot0_set, - Field_ftsf314ae_slot0_Slot_ae_slot0_set, - Field_ftsf315ae_slot0_Slot_ae_slot0_set, - Field_ftsf316ae_slot0_Slot_ae_slot0_set, - Field_ftsf317ae_slot0_Slot_ae_slot0_set, - Field_ftsf318ae_slot0_Slot_ae_slot0_set, - Field_ftsf319_Slot_ae_slot0_set, - Field_ftsf320ae_slot0_Slot_ae_slot0_set, - Field_ftsf321_Slot_ae_slot0_set, - Field_ftsf322ae_slot0_Slot_ae_slot0_set, - Field_ftsf323ae_slot0_Slot_ae_slot0_set, - Field_ftsf324ae_slot0_Slot_ae_slot0_set, - Field_ftsf325ae_slot0_Slot_ae_slot0_set, - Field_ftsf326ae_slot0_Slot_ae_slot0_set, - Field_ftsf328ae_slot0_Slot_ae_slot0_set, - Field_ftsf329ae_slot0_Slot_ae_slot0_set, - Field_ftsf352ae_slot0_Slot_ae_slot0_set, - Field_ftsf353_Slot_ae_slot0_set, - Field_ftsf354ae_slot0_Slot_ae_slot0_set, - Field_ftsf356ae_slot0_Slot_ae_slot0_set, - Field_ftsf357_Slot_ae_slot0_set, - Field_ftsf358ae_slot0_Slot_ae_slot0_set, - Field_ftsf359ae_slot0_Slot_ae_slot0_set, - Field_ftsf360ae_slot0_Slot_ae_slot0_set, - Field_ftsf361ae_slot0_Slot_ae_slot0_set, - Field_ftsf362ae_slot0_Slot_ae_slot0_set, - Field_ftsf364ae_slot0_Slot_ae_slot0_set, - Field_ftsf365ae_slot0_Slot_ae_slot0_set, - Field_ftsf366ae_slot0_Slot_ae_slot0_set, - Field_ftsf368ae_slot0_Slot_ae_slot0_set, - Field_ftsf369ae_slot0_Slot_ae_slot0_set, - 0, - Field_combined1b97e84f_fld115_Slot_ae_slot0_set, - Field_combined1b97e84f_fld97_Slot_ae_slot0_set, - Field_combined1b97e84f_fld124_Slot_ae_slot0_set, - Field_combined1b97e84f_fld79_Slot_ae_slot0_set, - Field_combined1b97e84f_fld80_Slot_ae_slot0_set, - Field_combined1b97e84f_fld108_Slot_ae_slot0_set, - Field_combined1b97e84f_fld101_Slot_ae_slot0_set, - Field_combined1b97e84f_fld88_Slot_ae_slot0_set, - Field_combined1b97e84f_fld39_Slot_ae_slot0_set, - Field_op0_s4_s4_Slot_ae_slot0_set, - Field_combined1b97e84f_fld83_Slot_ae_slot0_set, - Field_combined1b97e84f_fld90_Slot_ae_slot0_set, - Field_combined1b97e84f_fld93_Slot_ae_slot0_set, - Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_set, - Field_combined4b12daa6_fld122_Slot_ae_slot0_set, - Field_combined4b12daa6_fld115_Slot_ae_slot0_set, - Field_combined4b12daa6_fld85_Slot_ae_slot0_set, - Field_combined4b12daa6_fld119_Slot_ae_slot0_set, - Field_combined4b12daa6_fld97_Slot_ae_slot0_set, - Field_combined4b12daa6_fld124_Slot_ae_slot0_set, - Field_combined4b12daa6_fld79_Slot_ae_slot0_set, - Field_combined4b12daa6_fld80_Slot_ae_slot0_set, - Field_combined4b12daa6_fld108_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_ae_slot0_set, - Field_s3to1_Slot_ae_slot0_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_slot_internal slots[] = { - { "Inst", "x24", 0, - Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, - Slot_inst_get_field_fns, Slot_inst_set_field_fns, - Slot_inst_decode, "nop" }, - { "Inst16a", "x16a", 0, - Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, - Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, - Slot_inst16a_decode, "" }, - { "Inst16b", "x16b", 0, - Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, - Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, - Slot_inst16b_decode, "nop.n" }, - { "ae_slot1", "ae_format", 1, - Slot_ae_format_Format_ae_slot1_31_get, Slot_ae_format_Format_ae_slot1_31_set, - Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns, - Slot_ae_slot1_decode, "nop" }, - { "ae_slot0", "ae_format", 0, - Slot_ae_format_Format_ae_slot0_4_get, Slot_ae_format_Format_ae_slot0_4_set, - Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns, - Slot_ae_slot0_decode, "nop" } -}; - - -/* Instruction formats. */ - -static void -Format_x24_encode (xtensa_insnbuf insn) -{ - insn[0] = 0; - insn[1] = 0; -} - -static void -Format_x16a_encode (xtensa_insnbuf insn) -{ - insn[0] = 0x8; - insn[1] = 0; -} - -static void -Format_x16b_encode (xtensa_insnbuf insn) -{ - insn[0] = 0xc; - insn[1] = 0; -} - -static void -Format_ae_format_encode (xtensa_insnbuf insn) -{ - insn[0] = 0xf; - insn[1] = 0; -} - -static int Format_x24_slots[] = { 0 }; - -static int Format_x16a_slots[] = { 1 }; - -static int Format_x16b_slots[] = { 2 }; - -static int Format_ae_format_slots[] = { 4, 3 }; - -static xtensa_format_internal formats[] = { - { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, - { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, - { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, - { "ae_format", 8, Format_ae_format_encode, 2, Format_ae_format_slots } -}; - - -static int -format_decoder (const xtensa_insnbuf insn) -{ - if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0) - return 0; /* x24 */ - if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0) - return 1; /* x16a */ - if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0) - return 2; /* x16b */ - if ((insn[0] & 0xf) == 0xf && (insn[1] & 0xffc00000) == 0) - return 3; /* ae_format */ - return -1; -} - -static int length_table[256] = { - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8 -}; - -static int -length_decoder (const unsigned char *insn) -{ - int l = insn[0]; - return length_table[l]; -} - - -/* Top-level ISA structure. */ - -xtensa_isa_internal xtensa_modules = { - 0 /* little-endian */, - 8 /* insn_size */, 0, - 4, formats, format_decoder, length_decoder, - 5, slots, - 439 /* num_fields */, - 504, operands, - 703, iclasses, - 778, opcodes, 0, - 8, regfiles, - NUM_STATES, states, 0, - NUM_SYSREGS, sysregs, 0, - { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, - 9, interfaces, 0, - 4, funcUnits, 0 -}; diff --git a/overlays/xtensa_intel_bdw_adsp/binutils/include/xtensa-config.h b/overlays/xtensa_intel_bdw_adsp/binutils/include/xtensa-config.h deleted file mode 100644 index fe6442e..0000000 --- a/overlays/xtensa_intel_bdw_adsp/binutils/include/xtensa-config.h +++ /dev/null @@ -1,177 +0,0 @@ -/* Xtensa configuration settings. - Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 - Free Software Foundation, Inc. - Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef XTENSA_CONFIG_H -#define XTENSA_CONFIG_H - -/* The macros defined here match those with the same names in the Xtensa - compile-time HAL (Hardware Abstraction Layer). Please refer to the - Xtensa System Software Reference Manual for documentation of these - macros. */ - -#undef XCHAL_HAVE_BE -#define XCHAL_HAVE_BE 0 - -#undef XCHAL_HAVE_DENSITY -#define XCHAL_HAVE_DENSITY 1 - -#undef XCHAL_HAVE_CONST16 -#define XCHAL_HAVE_CONST16 0 - -#undef XCHAL_HAVE_ABS -#define XCHAL_HAVE_ABS 1 - -#undef XCHAL_HAVE_ADDX -#define XCHAL_HAVE_ADDX 1 - -#undef XCHAL_HAVE_L32R -#define XCHAL_HAVE_L32R 1 - -#undef XSHAL_USE_ABSOLUTE_LITERALS -#define XSHAL_USE_ABSOLUTE_LITERALS 0 - -#undef XSHAL_HAVE_TEXT_SECTION_LITERALS -#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ - -#undef XCHAL_HAVE_MAC16 -#define XCHAL_HAVE_MAC16 0 - -#undef XCHAL_HAVE_MUL16 -#define XCHAL_HAVE_MUL16 1 - -#undef XCHAL_HAVE_MUL32 -#define XCHAL_HAVE_MUL32 0 - -#undef XCHAL_HAVE_MUL32_HIGH -#define XCHAL_HAVE_MUL32_HIGH 0 - -#undef XCHAL_HAVE_DIV32 -#define XCHAL_HAVE_DIV32 0 - -#undef XCHAL_HAVE_NSA -#define XCHAL_HAVE_NSA 1 - -#undef XCHAL_HAVE_MINMAX -#define XCHAL_HAVE_MINMAX 1 - -#undef XCHAL_HAVE_SEXT -#define XCHAL_HAVE_SEXT 1 - -#undef XCHAL_HAVE_LOOPS -#define XCHAL_HAVE_LOOPS 1 - -#undef XCHAL_HAVE_THREADPTR -#define XCHAL_HAVE_THREADPTR 1 - -#undef XCHAL_HAVE_RELEASE_SYNC -#define XCHAL_HAVE_RELEASE_SYNC 1 - -#undef XCHAL_HAVE_S32C1I -#define XCHAL_HAVE_S32C1I 1 - -#undef XCHAL_HAVE_BOOLEANS -#define XCHAL_HAVE_BOOLEANS 1 - -#undef XCHAL_HAVE_FP -#define XCHAL_HAVE_FP 0 - -#undef XCHAL_HAVE_FP_DIV -#define XCHAL_HAVE_FP_DIV 0 - -#undef XCHAL_HAVE_FP_RECIP -#define XCHAL_HAVE_FP_RECIP 0 - -#undef XCHAL_HAVE_FP_SQRT -#define XCHAL_HAVE_FP_SQRT 0 - -#undef XCHAL_HAVE_FP_RSQRT -#define XCHAL_HAVE_FP_RSQRT 0 - -#undef XCHAL_HAVE_DFP_accel -#define XCHAL_HAVE_DFP_accel 0 -#undef XCHAL_HAVE_WINDOWED -#define XCHAL_HAVE_WINDOWED 1 - -#undef XCHAL_NUM_AREGS -#define XCHAL_NUM_AREGS 32 - -#undef XCHAL_HAVE_WIDE_BRANCHES -#define XCHAL_HAVE_WIDE_BRANCHES 0 - -#undef XCHAL_HAVE_PREDICTED_BRANCHES -#define XCHAL_HAVE_PREDICTED_BRANCHES 0 - - -#undef XCHAL_ICACHE_SIZE -#define XCHAL_ICACHE_SIZE 0 - -#undef XCHAL_DCACHE_SIZE -#define XCHAL_DCACHE_SIZE 0 - -#undef XCHAL_ICACHE_LINESIZE -#define XCHAL_ICACHE_LINESIZE 128 - -#undef XCHAL_DCACHE_LINESIZE -#define XCHAL_DCACHE_LINESIZE 128 - -#undef XCHAL_ICACHE_LINEWIDTH -#define XCHAL_ICACHE_LINEWIDTH 7 - -#undef XCHAL_DCACHE_LINEWIDTH -#define XCHAL_DCACHE_LINEWIDTH 7 - -#undef XCHAL_DCACHE_IS_WRITEBACK -#define XCHAL_DCACHE_IS_WRITEBACK 0 - - -#undef XCHAL_HAVE_MMU -#define XCHAL_HAVE_MMU 1 - -#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE -#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 - - -#undef XCHAL_HAVE_DEBUG -#define XCHAL_HAVE_DEBUG 1 - -#undef XCHAL_NUM_IBREAK -#define XCHAL_NUM_IBREAK 2 - -#undef XCHAL_NUM_DBREAK -#define XCHAL_NUM_DBREAK 2 - -#undef XCHAL_DEBUGLEVEL -#define XCHAL_DEBUGLEVEL 6 - - -#undef XCHAL_MAX_INSTRUCTION_SIZE -#define XCHAL_MAX_INSTRUCTION_SIZE 8 - -#undef XCHAL_INST_FETCH_WIDTH -#define XCHAL_INST_FETCH_WIDTH 4 - - -#undef XSHAL_ABI -#undef XTHAL_ABI_WINDOWED -#undef XTHAL_ABI_CALL0 -#define XSHAL_ABI XTHAL_ABI_WINDOWED -#define XTHAL_ABI_WINDOWED 0 -#define XTHAL_ABI_CALL0 1 - -#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_intel_bdw_adsp/gcc/include/xtensa-config.h b/overlays/xtensa_intel_bdw_adsp/gcc/include/xtensa-config.h deleted file mode 100644 index fe6442e..0000000 --- a/overlays/xtensa_intel_bdw_adsp/gcc/include/xtensa-config.h +++ /dev/null @@ -1,177 +0,0 @@ -/* Xtensa configuration settings. - Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 - Free Software Foundation, Inc. - Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef XTENSA_CONFIG_H -#define XTENSA_CONFIG_H - -/* The macros defined here match those with the same names in the Xtensa - compile-time HAL (Hardware Abstraction Layer). Please refer to the - Xtensa System Software Reference Manual for documentation of these - macros. */ - -#undef XCHAL_HAVE_BE -#define XCHAL_HAVE_BE 0 - -#undef XCHAL_HAVE_DENSITY -#define XCHAL_HAVE_DENSITY 1 - -#undef XCHAL_HAVE_CONST16 -#define XCHAL_HAVE_CONST16 0 - -#undef XCHAL_HAVE_ABS -#define XCHAL_HAVE_ABS 1 - -#undef XCHAL_HAVE_ADDX -#define XCHAL_HAVE_ADDX 1 - -#undef XCHAL_HAVE_L32R -#define XCHAL_HAVE_L32R 1 - -#undef XSHAL_USE_ABSOLUTE_LITERALS -#define XSHAL_USE_ABSOLUTE_LITERALS 0 - -#undef XSHAL_HAVE_TEXT_SECTION_LITERALS -#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ - -#undef XCHAL_HAVE_MAC16 -#define XCHAL_HAVE_MAC16 0 - -#undef XCHAL_HAVE_MUL16 -#define XCHAL_HAVE_MUL16 1 - -#undef XCHAL_HAVE_MUL32 -#define XCHAL_HAVE_MUL32 0 - -#undef XCHAL_HAVE_MUL32_HIGH -#define XCHAL_HAVE_MUL32_HIGH 0 - -#undef XCHAL_HAVE_DIV32 -#define XCHAL_HAVE_DIV32 0 - -#undef XCHAL_HAVE_NSA -#define XCHAL_HAVE_NSA 1 - -#undef XCHAL_HAVE_MINMAX -#define XCHAL_HAVE_MINMAX 1 - -#undef XCHAL_HAVE_SEXT -#define XCHAL_HAVE_SEXT 1 - -#undef XCHAL_HAVE_LOOPS -#define XCHAL_HAVE_LOOPS 1 - -#undef XCHAL_HAVE_THREADPTR -#define XCHAL_HAVE_THREADPTR 1 - -#undef XCHAL_HAVE_RELEASE_SYNC -#define XCHAL_HAVE_RELEASE_SYNC 1 - -#undef XCHAL_HAVE_S32C1I -#define XCHAL_HAVE_S32C1I 1 - -#undef XCHAL_HAVE_BOOLEANS -#define XCHAL_HAVE_BOOLEANS 1 - -#undef XCHAL_HAVE_FP -#define XCHAL_HAVE_FP 0 - -#undef XCHAL_HAVE_FP_DIV -#define XCHAL_HAVE_FP_DIV 0 - -#undef XCHAL_HAVE_FP_RECIP -#define XCHAL_HAVE_FP_RECIP 0 - -#undef XCHAL_HAVE_FP_SQRT -#define XCHAL_HAVE_FP_SQRT 0 - -#undef XCHAL_HAVE_FP_RSQRT -#define XCHAL_HAVE_FP_RSQRT 0 - -#undef XCHAL_HAVE_DFP_accel -#define XCHAL_HAVE_DFP_accel 0 -#undef XCHAL_HAVE_WINDOWED -#define XCHAL_HAVE_WINDOWED 1 - -#undef XCHAL_NUM_AREGS -#define XCHAL_NUM_AREGS 32 - -#undef XCHAL_HAVE_WIDE_BRANCHES -#define XCHAL_HAVE_WIDE_BRANCHES 0 - -#undef XCHAL_HAVE_PREDICTED_BRANCHES -#define XCHAL_HAVE_PREDICTED_BRANCHES 0 - - -#undef XCHAL_ICACHE_SIZE -#define XCHAL_ICACHE_SIZE 0 - -#undef XCHAL_DCACHE_SIZE -#define XCHAL_DCACHE_SIZE 0 - -#undef XCHAL_ICACHE_LINESIZE -#define XCHAL_ICACHE_LINESIZE 128 - -#undef XCHAL_DCACHE_LINESIZE -#define XCHAL_DCACHE_LINESIZE 128 - -#undef XCHAL_ICACHE_LINEWIDTH -#define XCHAL_ICACHE_LINEWIDTH 7 - -#undef XCHAL_DCACHE_LINEWIDTH -#define XCHAL_DCACHE_LINEWIDTH 7 - -#undef XCHAL_DCACHE_IS_WRITEBACK -#define XCHAL_DCACHE_IS_WRITEBACK 0 - - -#undef XCHAL_HAVE_MMU -#define XCHAL_HAVE_MMU 1 - -#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE -#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 - - -#undef XCHAL_HAVE_DEBUG -#define XCHAL_HAVE_DEBUG 1 - -#undef XCHAL_NUM_IBREAK -#define XCHAL_NUM_IBREAK 2 - -#undef XCHAL_NUM_DBREAK -#define XCHAL_NUM_DBREAK 2 - -#undef XCHAL_DEBUGLEVEL -#define XCHAL_DEBUGLEVEL 6 - - -#undef XCHAL_MAX_INSTRUCTION_SIZE -#define XCHAL_MAX_INSTRUCTION_SIZE 8 - -#undef XCHAL_INST_FETCH_WIDTH -#define XCHAL_INST_FETCH_WIDTH 4 - - -#undef XSHAL_ABI -#undef XTHAL_ABI_WINDOWED -#undef XTHAL_ABI_CALL0 -#define XSHAL_ABI XTHAL_ABI_WINDOWED -#define XTHAL_ABI_WINDOWED 0 -#define XTHAL_ABI_CALL0 1 - -#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_intel_bdw_adsp/gdb/bfd/xtensa-modules.c b/overlays/xtensa_intel_bdw_adsp/gdb/bfd/xtensa-modules.c deleted file mode 100644 index d71738b..0000000 --- a/overlays/xtensa_intel_bdw_adsp/gdb/bfd/xtensa-modules.c +++ /dev/null @@ -1,42144 +0,0 @@ -/* Xtensa configuration-specific ISA information. - - Customer ID=4313; Build=0x5483e; Copyright (c) 2003-2015 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#include "ansidecl.h" -#include -#include "xtensa-isa-internal.h" - -#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) - - -/* Sysregs. */ - -static xtensa_sysreg_internal sysregs[] = { - { "LBEG", 0, 0 }, - { "LEND", 1, 0 }, - { "LCOUNT", 2, 0 }, - { "BR", 4, 0 }, - { "MMID", 89, 0 }, - { "DDR", 104, 0 }, - { "CONFIGID0", 176, 0 }, - { "CONFIGID1", 208, 0 }, - { "INTERRUPT", 226, 0 }, - { "INTCLEAR", 227, 0 }, - { "CCOUNT", 234, 0 }, - { "PRID", 235, 0 }, - { "ICOUNT", 236, 0 }, - { "CCOMPARE0", 240, 0 }, - { "CCOMPARE1", 241, 0 }, - { "CCOMPARE2", 242, 0 }, - { "VECBASE", 231, 0 }, - { "EPC1", 177, 0 }, - { "EPC2", 178, 0 }, - { "EPC3", 179, 0 }, - { "EPC4", 180, 0 }, - { "EPC5", 181, 0 }, - { "EPC6", 182, 0 }, - { "EPC7", 183, 0 }, - { "EXCSAVE1", 209, 0 }, - { "EXCSAVE2", 210, 0 }, - { "EXCSAVE3", 211, 0 }, - { "EXCSAVE4", 212, 0 }, - { "EXCSAVE5", 213, 0 }, - { "EXCSAVE6", 214, 0 }, - { "EXCSAVE7", 215, 0 }, - { "EPS2", 194, 0 }, - { "EPS3", 195, 0 }, - { "EPS4", 196, 0 }, - { "EPS5", 197, 0 }, - { "EPS6", 198, 0 }, - { "EPS7", 199, 0 }, - { "EXCCAUSE", 232, 0 }, - { "DEPC", 192, 0 }, - { "EXCVADDR", 238, 0 }, - { "WINDOWBASE", 72, 0 }, - { "WINDOWSTART", 73, 0 }, - { "SAR", 3, 0 }, - { "PS", 230, 0 }, - { "MISC0", 244, 0 }, - { "MISC1", 245, 0 }, - { "INTENABLE", 228, 0 }, - { "DBREAKA0", 144, 0 }, - { "DBREAKC0", 160, 0 }, - { "DBREAKA1", 145, 0 }, - { "DBREAKC1", 161, 0 }, - { "IBREAKA0", 128, 0 }, - { "IBREAKA1", 129, 0 }, - { "IBREAKENABLE", 96, 0 }, - { "ICOUNTLEVEL", 237, 0 }, - { "DEBUGCAUSE", 233, 0 }, - { "PREFCTL", 40, 0 }, - { "CPENABLE", 224, 0 }, - { "SCOMPARE1", 12, 0 }, - { "ATOMCTL", 99, 0 }, - { "AE_OVF_SAR", 240, 1 }, - { "AE_BITHEAD", 241, 1 }, - { "AE_TS_FTS_BU_BP", 242, 1 }, - { "AE_SD_NO", 243, 1 }, - { "AE_CBEGIN0", 246, 1 }, - { "AE_CEND0", 247, 1 }, - { "EXPSTATE", 230, 1 }, - { "MEPC", 106, 0}, - { "MEPS", 107, 0}, - { "MESAVE", 108, 0}, - { "MESR", 109, 0}, - { "MECR", 110, 0}, - { "MEVADDR", 111, 0}, - { "MEMCTL", 97, 0}, - { "ACCLO", 16, 0}, - { "ACCHI", 17, 0}, - { "THREADPTR", 231, 1}, -}; - -#define NUM_SYSREGS ARRAY_SIZE(sysregs) -#define MAX_SPECIAL_REG 245 -#define MAX_USER_REG 247 - - -/* Processor states. */ - -static xtensa_state_internal states[] = { - { "LCOUNT", 32, 0 }, - { "PC", 32, 0 }, - { "ICOUNT", 32, 0 }, - { "DDR", 32, 0 }, - { "INTERRUPT", 22, 0 }, - { "CCOUNT", 32, 0 }, - { "XTSYNC", 1, 0 }, - { "VECBASE", 22, 0 }, - { "EPC1", 32, 0 }, - { "EPC2", 32, 0 }, - { "EPC3", 32, 0 }, - { "EPC4", 32, 0 }, - { "EPC5", 32, 0 }, - { "EPC6", 32, 0 }, - { "EPC7", 32, 0 }, - { "EXCSAVE1", 32, 0 }, - { "EXCSAVE2", 32, 0 }, - { "EXCSAVE3", 32, 0 }, - { "EXCSAVE4", 32, 0 }, - { "EXCSAVE5", 32, 0 }, - { "EXCSAVE6", 32, 0 }, - { "EXCSAVE7", 32, 0 }, - { "EPS2", 13, 0 }, - { "EPS3", 13, 0 }, - { "EPS4", 13, 0 }, - { "EPS5", 13, 0 }, - { "EPS6", 13, 0 }, - { "EPS7", 13, 0 }, - { "EXCCAUSE", 6, 0 }, - { "PSINTLEVEL", 4, 0 }, - { "PSUM", 1, 0 }, - { "PSWOE", 1, 0 }, - { "PSEXCM", 1, 0 }, - { "DEPC", 32, 0 }, - { "EXCVADDR", 32, 0 }, - { "WindowBase", 3, 0 }, - { "WindowStart", 8, 0 }, - { "PSCALLINC", 2, 0 }, - { "PSOWB", 4, 0 }, - { "LBEG", 32, 0 }, - { "LEND", 32, 0 }, - { "SAR", 6, 0 }, - { "MISC0", 32, 0 }, - { "MISC1", 32, 0 }, - { "InOCDMode", 1, 0 }, - { "INTENABLE", 22, 0 }, - { "DBREAKA0", 32, 0 }, - { "DBREAKC0", 8, 0 }, - { "DBREAKA1", 32, 0 }, - { "DBREAKC1", 8, 0 }, - { "IBREAKA0", 32, 0 }, - { "IBREAKA1", 32, 0 }, - { "IBREAKENABLE", 2, 0 }, - { "ICOUNTLEVEL", 4, 0 }, - { "DEBUGCAUSE", 6, 0 }, - { "DBNUM", 4, 0 }, - { "CCOMPARE0", 32, 0 }, - { "CCOMPARE1", 32, 0 }, - { "CCOMPARE2", 32, 0 }, - { "PREFCTL", 9, 0 }, - { "CPENABLE", 2, 0 }, - { "SCOMPARE1", 32, 0 }, - { "ATOMCTL", 6, 0 }, - { "AE_OVERFLOW", 1, XTENSA_STATE_IS_SHARED_OR }, - { "AE_SAR", 6, 0 }, - { "AE_BITHEAD", 32, 0 }, - { "AE_BITPTR", 4, 0 }, - { "AE_BITSUSED", 4, 0 }, - { "AE_TABLESIZE", 4, 0 }, - { "AE_FIRST_TS", 4, 0 }, - { "AE_NEXTOFFSET", 27, 0 }, - { "AE_SEARCHDONE", 1, 0 }, - { "AE_CBEGIN0", 32, 0 }, - { "AE_CEND0", 32, 0 }, - { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }, - { "MEPC", 32, 0}, - { "MEPS", 13, 0}, - { "MESAVE", 32, 0}, - { "MESR", 19, 0}, - { "MECR", 22, 0}, - { "MEVADDR", 32, 0}, - { "MEMCTL", 32, 0}, - { "ACCLO", 32, 0}, - { "ACCHI", 8, 0}, - { "THREADPTR", 32, 0}, -}; - -#define NUM_STATES ARRAY_SIZE(states) - -enum xtensa_state_id { - STATE_LCOUNT, - STATE_PC, - STATE_ICOUNT, - STATE_DDR, - STATE_INTERRUPT, - STATE_CCOUNT, - STATE_XTSYNC, - STATE_VECBASE, - STATE_EPC1, - STATE_EPC2, - STATE_EPC3, - STATE_EPC4, - STATE_EPC5, - STATE_EPC6, - STATE_EPC7, - STATE_EXCSAVE1, - STATE_EXCSAVE2, - STATE_EXCSAVE3, - STATE_EXCSAVE4, - STATE_EXCSAVE5, - STATE_EXCSAVE6, - STATE_EXCSAVE7, - STATE_EPS2, - STATE_EPS3, - STATE_EPS4, - STATE_EPS5, - STATE_EPS6, - STATE_EPS7, - STATE_EXCCAUSE, - STATE_PSINTLEVEL, - STATE_PSUM, - STATE_PSWOE, - STATE_PSEXCM, - STATE_DEPC, - STATE_EXCVADDR, - STATE_WindowBase, - STATE_WindowStart, - STATE_PSCALLINC, - STATE_PSOWB, - STATE_LBEG, - STATE_LEND, - STATE_SAR, - STATE_MISC0, - STATE_MISC1, - STATE_InOCDMode, - STATE_INTENABLE, - STATE_DBREAKA0, - STATE_DBREAKC0, - STATE_DBREAKA1, - STATE_DBREAKC1, - STATE_IBREAKA0, - STATE_IBREAKA1, - STATE_IBREAKENABLE, - STATE_ICOUNTLEVEL, - STATE_DEBUGCAUSE, - STATE_DBNUM, - STATE_CCOMPARE0, - STATE_CCOMPARE1, - STATE_CCOMPARE2, - STATE_PREFCTL, - STATE_CPENABLE, - STATE_SCOMPARE1, - STATE_ATOMCTL, - STATE_AE_OVERFLOW, - STATE_AE_SAR, - STATE_AE_BITHEAD, - STATE_AE_BITPTR, - STATE_AE_BITSUSED, - STATE_AE_TABLESIZE, - STATE_AE_FIRST_TS, - STATE_AE_NEXTOFFSET, - STATE_AE_SEARCHDONE, - STATE_AE_CBEGIN0, - STATE_AE_CEND0, - STATE_EXPSTATE, - STATE_MEPC, - STATE_MEPS, - STATE_MESAVE, - STATE_MESR, - STATE_MECR, - STATE_MEVADDR, - STATE_MEMCTL, - STATE_ACCLO, - STATE_ACCHI, - STATE_THREADPTR, -}; - - -/* Field definitions. */ - -static unsigned -Field_t_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_s_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_r_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_op2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); - return tie_t; -} - -static void -Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); -} - -static unsigned -Field_op1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_op0_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_n_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_m_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_sr_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_st_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ae_r3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_ae_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_ae_r10_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_ae_r32_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ae_s3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_ae_s3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_ae_s_non_samt_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_ae_s_non_samt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf61ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf61ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 22) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_op0_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - return tie_t; -} - -static void -Field_op0_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf330ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_ftsf330ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ftsf81ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf81ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ae_r20_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_ftsf73ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf73ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf35ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf35ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf34ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf34ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf32ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf32ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf33ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf33ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf96ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf96ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ae_s20_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); -} - -static unsigned -Field_ftsf94ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_ftsf94ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf347_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf347_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); -} - -static unsigned -Field_ftsf24ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - return tie_t; -} - -static void -Field_ftsf24ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf23ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - return tie_t; -} - -static void -Field_ftsf23ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf125ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_ftsf125ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_ftsf350ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); - return tie_t; -} - -static void -Field_ftsf350ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78) | (tie_t << 3); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf80ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf80ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf88ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf88ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 23) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf340_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf340_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_ftsf87ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf87ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x60) | (tie_t << 5); - tie_t = (val << 22) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf342ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_ftsf342ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_ftsf86ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); - return tie_t; -} - -static void -Field_ftsf86ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78) | (tie_t << 3); - tie_t = (val << 21) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf84ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); - return tie_t; -} - -static void -Field_ftsf84ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78) | (tie_t << 3); - tie_t = (val << 21) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf76ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf76ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf75ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf75ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf60ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf60ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 21) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf64ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf64ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 20) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf63ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf63ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ae_r10_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf59ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf59ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 21) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf119ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf119ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 24) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 21) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf338_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf338_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_ftsf69ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf69ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 22) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf67ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf67ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x60) | (tie_t << 5); - tie_t = (val << 21) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf66ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf66ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 20) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf25ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf25ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf36ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf36ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf103ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf103ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf349ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 23) >> 26); - return tie_t; -} - -static void -Field_ftsf349ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x1f8) | (tie_t << 3); -} - -static unsigned -Field_ftsf99ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf99ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf27ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf27ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf28ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf28ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf21ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf21ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf22ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf22ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf29ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf29ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf97ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf97ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf100ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf100ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf101ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - return tie_t; -} - -static void -Field_ftsf101ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf348ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); - return tie_t; -} - -static void -Field_ftsf348ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); -} - -static unsigned -Field_ftsf26ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf26ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf30ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf30ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf31ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf31ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf98ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf98ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf92ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); - return tie_t; -} - -static void -Field_ftsf92ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6) | (tie_t << 1); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf208_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf208_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); -} - -static unsigned -Field_ftsf91ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf91ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf90ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf90ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf126ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); - return tie_t; -} - -static void -Field_ftsf126ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); -} - -static unsigned -Field_ftsf344ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf344ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 23) >> 30; - insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); -} - -static unsigned -Field_ftsf112ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf112ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf122ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); - return tie_t; -} - -static void -Field_ftsf122ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); - tie_t = (val << 24) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf346ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf346ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf116ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); - return tie_t; -} - -static void -Field_ftsf116ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); - tie_t = (val << 20) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf109ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf109ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf111ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf111ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf104ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf104ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf105ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf105ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf107ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf107ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf113ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf113ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf118ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); - return tie_t; -} - -static void -Field_ftsf118ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); - tie_t = (val << 20) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf120ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 6) | ((insn[0] << 25) >> 26); - return tie_t; -} - -static void -Field_ftsf120ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x7e) | (tie_t << 1); - tie_t = (val << 23) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf343ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf343ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf108ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf108ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf115ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf115ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf110ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf110ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf114ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf114ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf37ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - return tie_t; -} - -static void -Field_ftsf37ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf78ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf78ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf79ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf79ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf77ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf77ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf13_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_ftsf13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf12_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - return tie_t; -} - -static void -Field_ftsf12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf82ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf82ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 24) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf341ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf341ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ftsf124ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf124ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 28) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf339ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf339ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ftsf106ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf106ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ae_r32_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ae_mul32x24fld_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ae_mul32x24fld_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf160ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf160ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf154ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf154ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf175ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf175ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf158ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf158ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf155ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf155ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf167ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf167ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf157ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf157ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf153ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf153ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf163ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf163ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf156ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf156ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf152ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf152ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf161ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf161ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf133ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf133ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf191ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf191ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf142ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf142ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf159ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf159ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf141ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf141ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf130ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf130ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf143ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf143ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf140ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf140ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf211ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_ftsf211ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_ftsf332ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf332ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_ftsf135ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf135ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf138ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf138ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf176ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf176ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf170ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf170ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf184ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf184ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf174ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf174ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf171ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf171ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf182ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf182ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf173ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf173ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf169ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf169ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf181ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf181ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf172ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf172ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf168ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf168ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf180ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf180ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf139ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf139ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf151ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf151ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf137ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf137ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf136ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf136ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf145ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf145ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf134ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf134ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf144ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf144ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf178ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf178ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf188ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf188ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf183ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf183ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf186ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf186ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf179ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf179ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf187ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf187ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf177ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf177ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf185ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf185ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf45ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf45ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf44ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf44ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf48ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf48ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf47ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf47ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf49ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf49ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf50ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf50ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf52ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf52ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf51ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf51ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf38ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf38ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf54ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf54ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf40ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf40ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf39ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf39ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf46ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf46ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf42ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf42ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf43ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf43ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf41ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf41ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf55ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf55ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf53ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf53ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf58ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf58ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf56ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf56ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf72ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf72ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 26) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf71ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf71ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 26) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf57ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf57ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf89ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_ftsf89ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_ftsf334ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf334ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_ftsf195ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf195ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf207ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf207ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf336ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; -} - -static void -Field_ftsf336ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); -} - -static unsigned -Field_ftsf199ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf199ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf210ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} - -static void -Field_ftsf210ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf337ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf337ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_ftsf194ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf194ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf197ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf197ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf196ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf196ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf198ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf198ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf200ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf200ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf203ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf203ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf201ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf201ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf202ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf202ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf204ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf204ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf206ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf206ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf205ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf205ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf209ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf209ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf127ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf127ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf129ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf129ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf128ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf128ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf146ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf146ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf149ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf149ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf148ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf148ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf150ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf150ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf162ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf162ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf165ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf165ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf164ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf164ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf166ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf166ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf189ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf189ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf192ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf192ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf190ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf190ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf193ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf193ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_combined1b97e84f_fld49_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld49_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_combined1b97e84f_fld54_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld54_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_combined1b97e84f_fld51_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld51_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined1b97e84f_fld23_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld23_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_op0_s3_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - return tie_t; -} - -static void -Field_op0_s3_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_combined1b97e84f_fld17_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld17_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); -} - -static unsigned -Field_combined1b97e84f_fld76_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld76_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2) | (tie_t << 1); -} - -static unsigned -Field_combined1b97e84f_fld73_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld73_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); -} - -static unsigned -Field_combined1b97e84f_fld62_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld62_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld24_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld24_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_combined1b97e84f_fld70_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld70_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_combined1b97e84f_fld58_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld58_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); -} - -static unsigned -Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_xt_fld0_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 9) >> 16); - return tie_t; -} - -static void -Field_xt_fld0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0x7fff80) | (tie_t << 7); -} - -static unsigned -Field_xt_fld1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_xt_fld1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_op0_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); - return tie_t; -} - -static void -Field_op0_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); -} - -static unsigned -Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - return tie_t; -} - -static void -Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_ftsf293_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_ftsf293_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_ftsf321_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf321_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_ae_s20_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); -} - -static unsigned -Field_ftsf214ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_ftsf214ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf213ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); - return tie_t; -} - -static void -Field_ftsf213ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); -} - -static unsigned -Field_ftsf212ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_ftsf212ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_ftsf281ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_ftsf281ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); - tie_t = (val << 16) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf217_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf217_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_ae_r20_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_ftsf300ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - return tie_t; -} - -static void -Field_ftsf300ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf283ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); - return tie_t; -} - -static void -Field_ftsf283ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 17) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf352ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf352ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf282ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_ftsf282ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); - tie_t = (val << 16) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf288ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); - return tie_t; -} - -static void -Field_ftsf288ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x38) | (tie_t << 3); - tie_t = (val << 21) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf359ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf359ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf286ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); - return tie_t; -} - -static void -Field_ftsf286ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf356ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf356ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf284ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 5) | ((insn[0] << 26) >> 27); - return tie_t; -} - -static void -Field_ftsf284ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x3e) | (tie_t << 1); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf354ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf354ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf295ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_ftsf295ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf358ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf358ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf325ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf325ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf215ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); - return tie_t; -} - -static void -Field_ftsf215ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); -} - -static unsigned -Field_ftsf301ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19); - return tie_t; -} - -static void -Field_ftsf301ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 19) >> 19; - insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf353_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf353_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_ftsf309ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23); - return tie_t; -} - -static void -Field_ftsf309ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0xff800) | (tie_t << 11); -} - -static unsigned -Field_ftsf360ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 21) >> 27); - return tie_t; -} - -static void -Field_ftsf360ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x7c0) | (tie_t << 6); -} - -static unsigned -Field_ftsf294ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_ftsf294ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); - tie_t = (val << 21) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf292ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_ftsf292ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); - tie_t = (val << 21) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf319_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; -} - -static void -Field_ftsf319_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); -} - -static unsigned -Field_ftsf361ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf361ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_ftsf218ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf218ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf220ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf220ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf221ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf221ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf222ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf222ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf228ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf228ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf229ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf229ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf230ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf230ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf232ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf232ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf233ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf233ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf235ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf235ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf239ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf239ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf234ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf234ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf224ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf224ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf225ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf225ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf227ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf227ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf226ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf226ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf241ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf241ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf243ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf243ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf242ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf242ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf244ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf244ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf236ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf236ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf237ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf237ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf238ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf238ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf240ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf240ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf261ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf261ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf296ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf296ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf248ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf248ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf250ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf250ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf269ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf269ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf264ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf264ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf266ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf266ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf267ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf267ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf260ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf260ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf262ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf262ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf263ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf263ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf265ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf265ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf246ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf246ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf247ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf247ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf249ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf249ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf253ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf253ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf257ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf257ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf256ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf256ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf258ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf258ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf259ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf259ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf251ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf251ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf252ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf252ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf254ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf254ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf255ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf255ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf275ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf275ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf277ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf277ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf278ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf278ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf290ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_ftsf290ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_ftsf272ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf272ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf276ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf276ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf273ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf273ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf274ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf274ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf297ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf297ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf298ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf298ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf310ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf310ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf311ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf311ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf270ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf270ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf271ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf271ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ae_r32_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf329ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); - return tie_t; -} - -static void -Field_ftsf329ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); -} - -static unsigned -Field_ftsf362ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf362ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 27) >> 29; - insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); -} - -static unsigned -Field_combined4b12daa6_fld85_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld85_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_combined4b12daa6_fld122_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld122_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x200) | (tie_t << 9); -} - -static unsigned -Field_combined4b12daa6_fld119_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld119_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x400) | (tie_t << 10); -} - -static unsigned -Field_combined4b12daa6_fld97_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); - return tie_t; -} - -static void -Field_combined4b12daa6_fld97_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); -} - -static unsigned -Field_combined4b12daa6_fld124_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld124_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_combined4b12daa6_fld79_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld79_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_combined4b12daa6_fld80_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld80_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); -} - -static unsigned -Field_combined4b12daa6_fld108_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_combined4b12daa6_fld108_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_op0_s4_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); - return tie_t; -} - -static void -Field_op0_s4_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); -} - -static unsigned -Field_combined4b12daa6_fld115_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld115_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_ftsf245ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf245ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf268ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf268ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf313ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf313ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf312ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf312ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf231ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf231ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf223ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf223ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf219ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf219ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf216ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf216ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf302ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf302ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 17) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf364ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf364ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_ftsf322ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf322ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf279ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); - return tie_t; -} - -static void -Field_ftsf279ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); - tie_t = (val << 18) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf318ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; -} - -static void -Field_ftsf318ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); - tie_t = (val << 28) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf365ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf365ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_ftsf316ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf316ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf314ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf314ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf315ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf315ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf320ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf320ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf299ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); - return tie_t; -} - -static void -Field_ftsf299ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 22) >> 22; - insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); -} - -static unsigned -Field_ftsf308ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21); - return tie_t; -} - -static void -Field_ftsf308ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 21) >> 21; - insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf366ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf366ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_ftsf306ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_ftsf306ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); - tie_t = (val << 19) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf368ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf368ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); - tie_t = (val << 29) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_ftsf304ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); - return tie_t; -} - -static void -Field_ftsf304ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6) | (tie_t << 1); - tie_t = (val << 18) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf369ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf369ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_ftsf323ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf323ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf328ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf328ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf326ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); - return tie_t; -} - -static void -Field_ftsf326ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc) | (tie_t << 2); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf357_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf357_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); -} - -static unsigned -Field_ftsf303ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf303ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 17) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf324ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf324ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf317ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf317ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld101_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld101_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); -} - -static unsigned -Field_combined1b97e84f_fld88_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld88_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2) | (tie_t << 1); -} - -static unsigned -Field_combined1b97e84f_fld39_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld39_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); -} - -static unsigned -Field_combined1b97e84f_fld115_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld115_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined1b97e84f_fld97_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); - return tie_t; -} - -static void -Field_combined1b97e84f_fld97_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); -} - -static unsigned -Field_combined1b97e84f_fld124_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld124_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld79_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld79_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_combined1b97e84f_fld80_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld80_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); -} - -static unsigned -Field_combined1b97e84f_fld108_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_combined1b97e84f_fld108_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld83_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld83_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld93_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld93_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_combined1b97e84f_fld90_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld90_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); -} - -static unsigned -Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_bbi_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); - return tie_t; -} - -static void -Field_bbi_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); -} - -static unsigned -Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); - return tie_t; -} - -static void -Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); -} - -static unsigned -Field_imm12_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_imm12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); -} - -static unsigned -Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); - return tie_t; -} - -static void -Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); -} - -static unsigned -Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); - return tie_t; -} - -static void -Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); -} - -static unsigned -Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); - return tie_t; -} - -static void -Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); -} - -static unsigned -Field_offset_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); - return tie_t; -} - -static void -Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); -} - -static unsigned -Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - return tie_t; -} - -static void -Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sae_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27); - return tie_t; -} - -static void -Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12); -} - -static unsigned -Field_sal_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); - return tie_t; -} - -static void -Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); -} - -static unsigned -Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sas_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); - return tie_t; -} - -static void -Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); -} - -static unsigned -Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_mn_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_t2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t2_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_t2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_s2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_r2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} - -static unsigned -Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} - -static unsigned -Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} - -static unsigned -Field_t4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_s4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_r4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_t8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_s8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_r8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); - return tie_t; -} - -static void -Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 17) >> 17; - insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); -} - -static unsigned -Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_ae_samt_s_t_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); - return tie_t; -} - -static void -Field_ae_samt_s_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); -} - -static unsigned -Field_ae_samt_s_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ae_samt_s_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -} - -static unsigned -Field_ae_r20_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); -} - -static unsigned -Field_ae_r10_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_ae_s20_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); -} - -static unsigned -Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_ftsf12_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf13_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf13_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_ftsf14_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf14_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); -} - -static unsigned -Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_bitindex_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s3to1_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static void -Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, - uint32 val ATTRIBUTE_UNUSED) -{ - /* Do nothing. */ -} - -static unsigned -Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 4; -} - -static unsigned -Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 8; -} - -static unsigned -Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 12; -} - -static unsigned -Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -enum xtensa_field_id { - FIELD_t, - FIELD_bbi4, - FIELD_bbi, - FIELD_imm12, - FIELD_imm8, - FIELD_s, - FIELD_imm12b, - FIELD_imm16, - FIELD_m, - FIELD_n, - FIELD_offset, - FIELD_op0, - FIELD_op1, - FIELD_op2, - FIELD_r, - FIELD_sa4, - FIELD_sae4, - FIELD_sae, - FIELD_sal, - FIELD_sargt, - FIELD_sas4, - FIELD_sas, - FIELD_sr, - FIELD_st, - FIELD_thi3, - FIELD_imm4, - FIELD_mn, - FIELD_i, - FIELD_imm6lo, - FIELD_imm6hi, - FIELD_imm7lo, - FIELD_imm7hi, - FIELD_z, - FIELD_imm6, - FIELD_imm7, - FIELD_t2, - FIELD_s2, - FIELD_r2, - FIELD_t4, - FIELD_s4, - FIELD_r4, - FIELD_t8, - FIELD_s8, - FIELD_r8, - FIELD_xt_wbr15_imm, - FIELD_xt_wbr18_imm, - FIELD_ae_r3, - FIELD_ae_s_non_samt, - FIELD_ae_s3, - FIELD_ae_r32, - FIELD_ae_samt_s_t, - FIELD_ae_r20, - FIELD_ae_r10, - FIELD_ae_s20, - FIELD_ae_fld_ohba, - FIELD_ae_fld_ohba2, - FIELD_op0_s3, - FIELD_ftsf12, - FIELD_ftsf13, - FIELD_ftsf14, - FIELD_ftsf21ae_slot1, - FIELD_ftsf22ae_slot1, - FIELD_ftsf23ae_slot1, - FIELD_ftsf24ae_slot1, - FIELD_ftsf25ae_slot1, - FIELD_ftsf26ae_slot1, - FIELD_ftsf27ae_slot1, - FIELD_ftsf28ae_slot1, - FIELD_ftsf29ae_slot1, - FIELD_ftsf30ae_slot1, - FIELD_ftsf31ae_slot1, - FIELD_ftsf32ae_slot1, - FIELD_ftsf33ae_slot1, - FIELD_ftsf34ae_slot1, - FIELD_ftsf35ae_slot1, - FIELD_ftsf36ae_slot1, - FIELD_ftsf37ae_slot1, - FIELD_ftsf38ae_slot1, - FIELD_ftsf39ae_slot1, - FIELD_ftsf40ae_slot1, - FIELD_ftsf41ae_slot1, - FIELD_ftsf42ae_slot1, - FIELD_ftsf43ae_slot1, - FIELD_ftsf44ae_slot1, - FIELD_ftsf45ae_slot1, - FIELD_ftsf46ae_slot1, - FIELD_ftsf47ae_slot1, - FIELD_ftsf48ae_slot1, - FIELD_ftsf49ae_slot1, - FIELD_ftsf50ae_slot1, - FIELD_ftsf51ae_slot1, - FIELD_ftsf52ae_slot1, - FIELD_ftsf53ae_slot1, - FIELD_ftsf54ae_slot1, - FIELD_ftsf55ae_slot1, - FIELD_ftsf56ae_slot1, - FIELD_ftsf57ae_slot1, - FIELD_ftsf58ae_slot1, - FIELD_ftsf59ae_slot1, - FIELD_ftsf60ae_slot1, - FIELD_ftsf61ae_slot1, - FIELD_ftsf63ae_slot1, - FIELD_ftsf64ae_slot1, - FIELD_ftsf66ae_slot1, - FIELD_ftsf67ae_slot1, - FIELD_ftsf69ae_slot1, - FIELD_ftsf71ae_slot1, - FIELD_ftsf72ae_slot1, - FIELD_ftsf73ae_slot1, - FIELD_ftsf75ae_slot1, - FIELD_ftsf76ae_slot1, - FIELD_ftsf77ae_slot1, - FIELD_ftsf78ae_slot1, - FIELD_ftsf79ae_slot1, - FIELD_ftsf80ae_slot1, - FIELD_ftsf81ae_slot1, - FIELD_ftsf82ae_slot1, - FIELD_ftsf84ae_slot1, - FIELD_ftsf86ae_slot1, - FIELD_ftsf87ae_slot1, - FIELD_ftsf88ae_slot1, - FIELD_ftsf89ae_slot1, - FIELD_ftsf90ae_slot1, - FIELD_ftsf91ae_slot1, - FIELD_ftsf92ae_slot1, - FIELD_ftsf94ae_slot1, - FIELD_ftsf96ae_slot1, - FIELD_ftsf97ae_slot1, - FIELD_ftsf98ae_slot1, - FIELD_ftsf99ae_slot1, - FIELD_ftsf100ae_slot1, - FIELD_ftsf101ae_slot1, - FIELD_ftsf103ae_slot1, - FIELD_ftsf104ae_slot1, - FIELD_ftsf105ae_slot1, - FIELD_ftsf106ae_slot1, - FIELD_ftsf107ae_slot1, - FIELD_ftsf108ae_slot1, - FIELD_ftsf109ae_slot1, - FIELD_ftsf110ae_slot1, - FIELD_ftsf111ae_slot1, - FIELD_ftsf112ae_slot1, - FIELD_ftsf113ae_slot1, - FIELD_ftsf114ae_slot1, - FIELD_ftsf115ae_slot1, - FIELD_ftsf116ae_slot1, - FIELD_ftsf118ae_slot1, - FIELD_ftsf119ae_slot1, - FIELD_ftsf120ae_slot1, - FIELD_ftsf122ae_slot1, - FIELD_ftsf124ae_slot1, - FIELD_ftsf125ae_slot1, - FIELD_ftsf126ae_slot1, - FIELD_ftsf127ae_slot1, - FIELD_ftsf128ae_slot1, - FIELD_ftsf129ae_slot1, - FIELD_ftsf130ae_slot1, - FIELD_ftsf131ae_slot1, - FIELD_ftsf132ae_slot1, - FIELD_ftsf133ae_slot1, - FIELD_ftsf134ae_slot1, - FIELD_ftsf135ae_slot1, - FIELD_ftsf136ae_slot1, - FIELD_ftsf137ae_slot1, - FIELD_ftsf138ae_slot1, - FIELD_ftsf139ae_slot1, - FIELD_ftsf140ae_slot1, - FIELD_ftsf141ae_slot1, - FIELD_ftsf142ae_slot1, - FIELD_ftsf143ae_slot1, - FIELD_ftsf144ae_slot1, - FIELD_ftsf145ae_slot1, - FIELD_ftsf146ae_slot1, - FIELD_ftsf147ae_slot1, - FIELD_ftsf148ae_slot1, - FIELD_ftsf149ae_slot1, - FIELD_ftsf150ae_slot1, - FIELD_ftsf151ae_slot1, - FIELD_ftsf152ae_slot1, - FIELD_ftsf153ae_slot1, - FIELD_ftsf154ae_slot1, - FIELD_ftsf155ae_slot1, - FIELD_ftsf156ae_slot1, - FIELD_ftsf157ae_slot1, - FIELD_ftsf158ae_slot1, - FIELD_ftsf159ae_slot1, - FIELD_ftsf160ae_slot1, - FIELD_ftsf161ae_slot1, - FIELD_ftsf162ae_slot1, - FIELD_ftsf163ae_slot1, - FIELD_ftsf164ae_slot1, - FIELD_ftsf165ae_slot1, - FIELD_ftsf166ae_slot1, - FIELD_ftsf167ae_slot1, - FIELD_ftsf168ae_slot1, - FIELD_ftsf169ae_slot1, - FIELD_ftsf170ae_slot1, - FIELD_ftsf171ae_slot1, - FIELD_ftsf172ae_slot1, - FIELD_ftsf173ae_slot1, - FIELD_ftsf174ae_slot1, - FIELD_ftsf175ae_slot1, - FIELD_ftsf176ae_slot1, - FIELD_ftsf177ae_slot1, - FIELD_ftsf178ae_slot1, - FIELD_ftsf179ae_slot1, - FIELD_ftsf180ae_slot1, - FIELD_ftsf181ae_slot1, - FIELD_ftsf182ae_slot1, - FIELD_ftsf183ae_slot1, - FIELD_ftsf184ae_slot1, - FIELD_ftsf185ae_slot1, - FIELD_ftsf186ae_slot1, - FIELD_ftsf187ae_slot1, - FIELD_ftsf188ae_slot1, - FIELD_ftsf189ae_slot1, - FIELD_ftsf190ae_slot1, - FIELD_ftsf191ae_slot1, - FIELD_ftsf192ae_slot1, - FIELD_ftsf193ae_slot1, - FIELD_ftsf194ae_slot1, - FIELD_ftsf195ae_slot1, - FIELD_ftsf196ae_slot1, - FIELD_ftsf197ae_slot1, - FIELD_ftsf198ae_slot1, - FIELD_ftsf199ae_slot1, - FIELD_ftsf200ae_slot1, - FIELD_ftsf201ae_slot1, - FIELD_ftsf202ae_slot1, - FIELD_ftsf203ae_slot1, - FIELD_ftsf204ae_slot1, - FIELD_ftsf205ae_slot1, - FIELD_ftsf206ae_slot1, - FIELD_ftsf207ae_slot1, - FIELD_ftsf208, - FIELD_ftsf209ae_slot1, - FIELD_ftsf210ae_slot1, - FIELD_ftsf211ae_slot1, - FIELD_ftsf330ae_slot1, - FIELD_ftsf332ae_slot1, - FIELD_ftsf334ae_slot1, - FIELD_ftsf336ae_slot1, - FIELD_ftsf337ae_slot1, - FIELD_ftsf338, - FIELD_ftsf339ae_slot1, - FIELD_ftsf340, - FIELD_ftsf341ae_slot1, - FIELD_ftsf342ae_slot1, - FIELD_ftsf343ae_slot1, - FIELD_ftsf344ae_slot1, - FIELD_ftsf346ae_slot1, - FIELD_ftsf347, - FIELD_ftsf348ae_slot1, - FIELD_ftsf349ae_slot1, - FIELD_ftsf350ae_slot1, - FIELD_op0_s4, - FIELD_ftsf212ae_slot0, - FIELD_ftsf213ae_slot0, - FIELD_ftsf214ae_slot0, - FIELD_ftsf215ae_slot0, - FIELD_ftsf216ae_slot0, - FIELD_ftsf217, - FIELD_ftsf218ae_slot0, - FIELD_ftsf219ae_slot0, - FIELD_ftsf220ae_slot0, - FIELD_ftsf221ae_slot0, - FIELD_ftsf222ae_slot0, - FIELD_ftsf223ae_slot0, - FIELD_ftsf224ae_slot0, - FIELD_ftsf225ae_slot0, - FIELD_ftsf226ae_slot0, - FIELD_ftsf227ae_slot0, - FIELD_ftsf228ae_slot0, - FIELD_ftsf229ae_slot0, - FIELD_ftsf230ae_slot0, - FIELD_ftsf231ae_slot0, - FIELD_ftsf232ae_slot0, - FIELD_ftsf233ae_slot0, - FIELD_ftsf234ae_slot0, - FIELD_ftsf235ae_slot0, - FIELD_ftsf236ae_slot0, - FIELD_ftsf237ae_slot0, - FIELD_ftsf238ae_slot0, - FIELD_ftsf239ae_slot0, - FIELD_ftsf240ae_slot0, - FIELD_ftsf241ae_slot0, - FIELD_ftsf242ae_slot0, - FIELD_ftsf243ae_slot0, - FIELD_ftsf244ae_slot0, - FIELD_ftsf245ae_slot0, - FIELD_ftsf246ae_slot0, - FIELD_ftsf247ae_slot0, - FIELD_ftsf248ae_slot0, - FIELD_ftsf249ae_slot0, - FIELD_ftsf250ae_slot0, - FIELD_ftsf251ae_slot0, - FIELD_ftsf252ae_slot0, - FIELD_ftsf253ae_slot0, - FIELD_ftsf254ae_slot0, - FIELD_ftsf255ae_slot0, - FIELD_ftsf256ae_slot0, - FIELD_ftsf257ae_slot0, - FIELD_ftsf258ae_slot0, - FIELD_ftsf259ae_slot0, - FIELD_ftsf260ae_slot0, - FIELD_ftsf261ae_slot0, - FIELD_ftsf262ae_slot0, - FIELD_ftsf263ae_slot0, - FIELD_ftsf264ae_slot0, - FIELD_ftsf265ae_slot0, - FIELD_ftsf266ae_slot0, - FIELD_ftsf267ae_slot0, - FIELD_ftsf268ae_slot0, - FIELD_ftsf269ae_slot0, - FIELD_ftsf270ae_slot0, - FIELD_ftsf271ae_slot0, - FIELD_ftsf272ae_slot0, - FIELD_ftsf273ae_slot0, - FIELD_ftsf274ae_slot0, - FIELD_ftsf275ae_slot0, - FIELD_ftsf276ae_slot0, - FIELD_ftsf277ae_slot0, - FIELD_ftsf278ae_slot0, - FIELD_ftsf279ae_slot0, - FIELD_ftsf281ae_slot0, - FIELD_ftsf282ae_slot0, - FIELD_ftsf283ae_slot0, - FIELD_ftsf284ae_slot0, - FIELD_ftsf286ae_slot0, - FIELD_ftsf288ae_slot0, - FIELD_ftsf290ae_slot0, - FIELD_ftsf292ae_slot0, - FIELD_ftsf293, - FIELD_ftsf294ae_slot0, - FIELD_ftsf295ae_slot0, - FIELD_ftsf296ae_slot0, - FIELD_ftsf297ae_slot0, - FIELD_ftsf298ae_slot0, - FIELD_ftsf299ae_slot0, - FIELD_ftsf300ae_slot0, - FIELD_ftsf301ae_slot0, - FIELD_ftsf302ae_slot0, - FIELD_ftsf303ae_slot0, - FIELD_ftsf304ae_slot0, - FIELD_ftsf306ae_slot0, - FIELD_ftsf308ae_slot0, - FIELD_ftsf309ae_slot0, - FIELD_ftsf310ae_slot0, - FIELD_ftsf311ae_slot0, - FIELD_ftsf312ae_slot0, - FIELD_ftsf313ae_slot0, - FIELD_ftsf314ae_slot0, - FIELD_ftsf315ae_slot0, - FIELD_ftsf316ae_slot0, - FIELD_ftsf317ae_slot0, - FIELD_ftsf318ae_slot0, - FIELD_ftsf319, - FIELD_ftsf320ae_slot0, - FIELD_ftsf321, - FIELD_ftsf322ae_slot0, - FIELD_ftsf323ae_slot0, - FIELD_ftsf324ae_slot0, - FIELD_ftsf325ae_slot0, - FIELD_ftsf326ae_slot0, - FIELD_ftsf328ae_slot0, - FIELD_ftsf329ae_slot0, - FIELD_ftsf352ae_slot0, - FIELD_ftsf353, - FIELD_ftsf354ae_slot0, - FIELD_ftsf356ae_slot0, - FIELD_ftsf357, - FIELD_ftsf358ae_slot0, - FIELD_ftsf359ae_slot0, - FIELD_ftsf360ae_slot0, - FIELD_ftsf361ae_slot0, - FIELD_ftsf362ae_slot0, - FIELD_ftsf364ae_slot0, - FIELD_ftsf365ae_slot0, - FIELD_ftsf366ae_slot0, - FIELD_ftsf368ae_slot0, - FIELD_ftsf369ae_slot0, - FIELD_ae_mul32x24fld, - FIELD_combined1b97e84f_fld115, - FIELD_combined1b97e84f_fld97, - FIELD_combined1b97e84f_fld124, - FIELD_combined1b97e84f_fld79, - FIELD_combined1b97e84f_fld80, - FIELD_combined1b97e84f_fld108, - FIELD_combined1b97e84f_fld101, - FIELD_combined1b97e84f_fld88, - FIELD_combined1b97e84f_fld39, - FIELD_op0_s4_s4, - FIELD_combined1b97e84f_fld83, - FIELD_combined1b97e84f_fld90, - FIELD_combined1b97e84f_fld93, - FIELD_combined1b97e84f_fld138ae_slot0, - FIELD_combined1b97e84f_fld130ae_slot0, - FIELD_combined1b97e84f_fld137ae_slot0, - FIELD_combined1b97e84f_fld135ae_slot0, - FIELD_combined1b97e84f_fld136ae_slot0, - FIELD_combined1b97e84f_fld129ae_slot0, - FIELD_combined1b97e84f_fld127ae_slot0, - FIELD_combined1b97e84f_fld128ae_slot0, - FIELD_combined1b97e84f_fld132ae_slot0, - FIELD_combined1b97e84f_fld134ae_slot0, - FIELD_combined4b12daa6_fld122, - FIELD_combined4b12daa6_fld115, - FIELD_combined4b12daa6_fld85, - FIELD_combined4b12daa6_fld119, - FIELD_combined4b12daa6_fld97, - FIELD_combined4b12daa6_fld124, - FIELD_combined4b12daa6_fld79, - FIELD_combined4b12daa6_fld80, - FIELD_combined4b12daa6_fld108, - FIELD_combined1b97e84f_fld54, - FIELD_combined1b97e84f_fld17, - FIELD_combined1b97e84f_fld76, - FIELD_combined1b97e84f_fld73, - FIELD_combined1b97e84f_fld62, - FIELD_combined1b97e84f_fld24, - FIELD_combined1b97e84f_fld70, - FIELD_combined1b97e84f_fld58, - FIELD_combined1b97e84f_fld131ae_slot1, - FIELD_op0_s3_s3, - FIELD_combined1b97e84f_fld49, - FIELD_combined1b97e84f_fld51, - FIELD_combined1b97e84f_fld23, - FIELD_xt_fld0, - FIELD_xt_fld1, - FIELD_bitindex, - FIELD_s3to1, - FIELD__ar0, - FIELD__ar4, - FIELD__ar8, - FIELD__ar12, - FIELD__bt16, - FIELD__bs16, - FIELD__br16, - FIELD__brall -}; - - -/* Functional units. */ - -static xtensa_funcUnit_internal funcUnits[] = { - { "ae_add32", 1 }, - { "ae_shift32x4", 1 }, - { "ae_shift32x5", 1 }, - { "ae_subshift", 1 } -}; - -enum xtensa_funcUnit_id { - FUNCUNIT_ae_add32, - FUNCUNIT_ae_shift32x4, - FUNCUNIT_ae_shift32x5, - FUNCUNIT_ae_subshift -}; - - -/* Register files. */ - -enum xtensa_regfile_id { - REGFILE_AR, - REGFILE_BR, - REGFILE_AE_PR, - REGFILE_AE_QR, - REGFILE_BR2, - REGFILE_BR4, - REGFILE_BR8, - REGFILE_BR16 -}; - -static xtensa_regfile_internal regfiles[] = { - { "AR", "a", REGFILE_AR, 32, 32 }, - { "BR", "b", REGFILE_BR, 1, 16 }, - { "AE_PR", "aep", REGFILE_AE_PR, 48, 8 }, - { "AE_QR", "aeq", REGFILE_AE_QR, 56, 4 }, - { "BR2", "b", REGFILE_BR, 2, 8 }, - { "BR4", "b", REGFILE_BR, 4, 4 }, - { "BR8", "b", REGFILE_BR, 8, 2 }, - { "BR16", "b", REGFILE_BR, 16, 1 } -}; - - -/* Interfaces. */ - -static xtensa_interface_internal interfaces[] = { - { "IPQ_Empty", 1, 0, 0, 'i' }, - { "IPQ", 32, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 0, 'i' }, - { "IPQ_NOTRDY", 1, 0, 0, 'i' }, - { "IPQ_KILL", 1, 0, 0, 'o' }, - { "OPQ_Full", 1, 0, 1, 'i' }, - { "OPQ", 32, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 1, 'o' }, - { "OPQ_NOTRDY", 1, 0, 1, 'i' }, - { "OPQ_KILL", 1, 0, 1, 'o' }, - { "IMPWIRE", 32, 0, 2, 'i' } -}; - -enum xtensa_interface_id { - INTERFACE_IPQ_Empty, - INTERFACE_IPQ, - INTERFACE_IPQ_NOTRDY, - INTERFACE_IPQ_KILL, - INTERFACE_OPQ_Full, - INTERFACE_OPQ, - INTERFACE_OPQ_NOTRDY, - INTERFACE_OPQ_KILL, - INTERFACE_IMPWIRE -}; - - -/* Constant tables. */ - -/* constant table ai4c */ -static const unsigned CONST_TBL_ai4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0x9, - 0xa, - 0xb, - 0xc, - 0xd, - 0xe, - 0xf, - 0 -}; - -/* constant table b4c */ -static const unsigned CONST_TBL_b4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - -/* constant table b4cu */ -static const unsigned CONST_TBL_b4cu_0[] = { - 0x8000, - 0x10000, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - - -/* Instruction operands. */ - -static int -OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) -{ - unsigned soffsetx4_out_0; - unsigned soffsetx4_in_0; - soffsetx4_in_0 = *valp & 0x3ffff; - soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); - *valp = soffsetx4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) -{ - unsigned soffsetx4_in_0; - unsigned soffsetx4_out_0; - soffsetx4_out_0 = *valp; - soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; - *valp = soffsetx4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) -{ - unsigned uimm12x8_out_0; - unsigned uimm12x8_in_0; - uimm12x8_in_0 = *valp & 0xfff; - uimm12x8_out_0 = uimm12x8_in_0 << 3; - *valp = uimm12x8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) -{ - unsigned uimm12x8_in_0; - unsigned uimm12x8_out_0; - uimm12x8_out_0 = *valp; - uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); - *valp = uimm12x8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm4_decode (uint32 *valp) -{ - unsigned simm4_out_0; - unsigned simm4_in_0; - simm4_in_0 = *valp & 0xf; - simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; - *valp = simm4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm4_encode (uint32 *valp) -{ - unsigned simm4_in_0; - unsigned simm4_out_0; - simm4_out_0 = *valp; - simm4_in_0 = (simm4_out_0 & 0xf); - *valp = simm4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_0_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_1_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_2_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_3_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_4_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_immrx4_decode (uint32 *valp) -{ - unsigned immrx4_out_0; - unsigned immrx4_in_0; - immrx4_in_0 = *valp & 0xf; - immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; - *valp = immrx4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_immrx4_encode (uint32 *valp) -{ - unsigned immrx4_in_0; - unsigned immrx4_out_0; - immrx4_out_0 = *valp; - immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); - *valp = immrx4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) -{ - unsigned lsi4x4_out_0; - unsigned lsi4x4_in_0; - lsi4x4_in_0 = *valp & 0xf; - lsi4x4_out_0 = lsi4x4_in_0 << 2; - *valp = lsi4x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) -{ - unsigned lsi4x4_in_0; - unsigned lsi4x4_out_0; - lsi4x4_out_0 = *valp; - lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); - *valp = lsi4x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm7_decode (uint32 *valp) -{ - unsigned simm7_out_0; - unsigned simm7_in_0; - simm7_in_0 = *valp & 0x7f; - simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; - *valp = simm7_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm7_encode (uint32 *valp) -{ - unsigned simm7_in_0; - unsigned simm7_out_0; - simm7_out_0 = *valp; - simm7_in_0 = (simm7_out_0 & 0x7f); - *valp = simm7_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm6_decode (uint32 *valp) -{ - unsigned uimm6_out_0; - unsigned uimm6_in_0; - uimm6_in_0 = *valp & 0x3f; - uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); - *valp = uimm6_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm6_encode (uint32 *valp) -{ - unsigned uimm6_in_0; - unsigned uimm6_out_0; - uimm6_out_0 = *valp; - uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; - *valp = uimm6_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ai4const_decode (uint32 *valp) -{ - unsigned ai4const_out_0; - unsigned ai4const_in_0; - ai4const_in_0 = *valp & 0xf; - ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; - *valp = ai4const_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ai4const_encode (uint32 *valp) -{ - unsigned ai4const_in_0; - unsigned ai4const_out_0; - ai4const_out_0 = *valp; - switch (ai4const_out_0) - { - case 0xffffffff: ai4const_in_0 = 0; break; - case 0x1: ai4const_in_0 = 0x1; break; - case 0x2: ai4const_in_0 = 0x2; break; - case 0x3: ai4const_in_0 = 0x3; break; - case 0x4: ai4const_in_0 = 0x4; break; - case 0x5: ai4const_in_0 = 0x5; break; - case 0x6: ai4const_in_0 = 0x6; break; - case 0x7: ai4const_in_0 = 0x7; break; - case 0x8: ai4const_in_0 = 0x8; break; - case 0x9: ai4const_in_0 = 0x9; break; - case 0xa: ai4const_in_0 = 0xa; break; - case 0xb: ai4const_in_0 = 0xb; break; - case 0xc: ai4const_in_0 = 0xc; break; - case 0xd: ai4const_in_0 = 0xd; break; - case 0xe: ai4const_in_0 = 0xe; break; - default: ai4const_in_0 = 0xf; break; - } - *valp = ai4const_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4const_decode (uint32 *valp) -{ - unsigned b4const_out_0; - unsigned b4const_in_0; - b4const_in_0 = *valp & 0xf; - b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; - *valp = b4const_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4const_encode (uint32 *valp) -{ - unsigned b4const_in_0; - unsigned b4const_out_0; - b4const_out_0 = *valp; - switch (b4const_out_0) - { - case 0xffffffff: b4const_in_0 = 0; break; - case 0x1: b4const_in_0 = 0x1; break; - case 0x2: b4const_in_0 = 0x2; break; - case 0x3: b4const_in_0 = 0x3; break; - case 0x4: b4const_in_0 = 0x4; break; - case 0x5: b4const_in_0 = 0x5; break; - case 0x6: b4const_in_0 = 0x6; break; - case 0x7: b4const_in_0 = 0x7; break; - case 0x8: b4const_in_0 = 0x8; break; - case 0xa: b4const_in_0 = 0x9; break; - case 0xc: b4const_in_0 = 0xa; break; - case 0x10: b4const_in_0 = 0xb; break; - case 0x20: b4const_in_0 = 0xc; break; - case 0x40: b4const_in_0 = 0xd; break; - case 0x80: b4const_in_0 = 0xe; break; - default: b4const_in_0 = 0xf; break; - } - *valp = b4const_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4constu_decode (uint32 *valp) -{ - unsigned b4constu_out_0; - unsigned b4constu_in_0; - b4constu_in_0 = *valp & 0xf; - b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; - *valp = b4constu_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4constu_encode (uint32 *valp) -{ - unsigned b4constu_in_0; - unsigned b4constu_out_0; - b4constu_out_0 = *valp; - switch (b4constu_out_0) - { - case 0x8000: b4constu_in_0 = 0; break; - case 0x10000: b4constu_in_0 = 0x1; break; - case 0x2: b4constu_in_0 = 0x2; break; - case 0x3: b4constu_in_0 = 0x3; break; - case 0x4: b4constu_in_0 = 0x4; break; - case 0x5: b4constu_in_0 = 0x5; break; - case 0x6: b4constu_in_0 = 0x6; break; - case 0x7: b4constu_in_0 = 0x7; break; - case 0x8: b4constu_in_0 = 0x8; break; - case 0xa: b4constu_in_0 = 0x9; break; - case 0xc: b4constu_in_0 = 0xa; break; - case 0x10: b4constu_in_0 = 0xb; break; - case 0x20: b4constu_in_0 = 0xc; break; - case 0x40: b4constu_in_0 = 0xd; break; - case 0x80: b4constu_in_0 = 0xe; break; - default: b4constu_in_0 = 0xf; break; - } - *valp = b4constu_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8_decode (uint32 *valp) -{ - unsigned uimm8_out_0; - unsigned uimm8_in_0; - uimm8_in_0 = *valp & 0xff; - uimm8_out_0 = uimm8_in_0; - *valp = uimm8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8_encode (uint32 *valp) -{ - unsigned uimm8_in_0; - unsigned uimm8_out_0; - uimm8_out_0 = *valp; - uimm8_in_0 = (uimm8_out_0 & 0xff); - *valp = uimm8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) -{ - unsigned uimm8x2_out_0; - unsigned uimm8x2_in_0; - uimm8x2_in_0 = *valp & 0xff; - uimm8x2_out_0 = uimm8x2_in_0 << 1; - *valp = uimm8x2_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) -{ - unsigned uimm8x2_in_0; - unsigned uimm8x2_out_0; - uimm8x2_out_0 = *valp; - uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); - *valp = uimm8x2_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) -{ - unsigned uimm8x4_out_0; - unsigned uimm8x4_in_0; - uimm8x4_in_0 = *valp & 0xff; - uimm8x4_out_0 = uimm8x4_in_0 << 2; - *valp = uimm8x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) -{ - unsigned uimm8x4_in_0; - unsigned uimm8x4_out_0; - uimm8x4_out_0 = *valp; - uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); - *valp = uimm8x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) -{ - unsigned uimm4x16_out_0; - unsigned uimm4x16_in_0; - uimm4x16_in_0 = *valp & 0xf; - uimm4x16_out_0 = uimm4x16_in_0 << 4; - *valp = uimm4x16_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) -{ - unsigned uimm4x16_in_0; - unsigned uimm4x16_out_0; - uimm4x16_out_0 = *valp; - uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); - *valp = uimm4x16_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8_decode (uint32 *valp) -{ - unsigned simm8_out_0; - unsigned simm8_in_0; - simm8_in_0 = *valp & 0xff; - simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; - *valp = simm8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8_encode (uint32 *valp) -{ - unsigned simm8_in_0; - unsigned simm8_out_0; - simm8_out_0 = *valp; - simm8_in_0 = (simm8_out_0 & 0xff); - *valp = simm8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) -{ - unsigned simm8x256_out_0; - unsigned simm8x256_in_0; - simm8x256_in_0 = *valp & 0xff; - simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; - *valp = simm8x256_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) -{ - unsigned simm8x256_in_0; - unsigned simm8x256_out_0; - simm8x256_out_0 = *valp; - simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); - *valp = simm8x256_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm12b_decode (uint32 *valp) -{ - unsigned simm12b_out_0; - unsigned simm12b_in_0; - simm12b_in_0 = *valp & 0xfff; - simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; - *valp = simm12b_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm12b_encode (uint32 *valp) -{ - unsigned simm12b_in_0; - unsigned simm12b_out_0; - simm12b_out_0 = *valp; - simm12b_in_0 = (simm12b_out_0 & 0xfff); - *valp = simm12b_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_msalp32_decode (uint32 *valp) -{ - unsigned msalp32_out_0; - unsigned msalp32_in_0; - msalp32_in_0 = *valp & 0x1f; - msalp32_out_0 = 0x20 - msalp32_in_0; - *valp = msalp32_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_msalp32_encode (uint32 *valp) -{ - unsigned msalp32_in_0; - unsigned msalp32_out_0; - msalp32_out_0 = *valp; - msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; - *valp = msalp32_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_op2p1_decode (uint32 *valp) -{ - unsigned op2p1_out_0; - unsigned op2p1_in_0; - op2p1_in_0 = *valp & 0xf; - op2p1_out_0 = op2p1_in_0 + 0x1; - *valp = op2p1_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_op2p1_encode (uint32 *valp) -{ - unsigned op2p1_in_0; - unsigned op2p1_out_0; - op2p1_out_0 = *valp; - op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; - *valp = op2p1_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_label8_decode (uint32 *valp) -{ - unsigned label8_out_0; - unsigned label8_in_0; - label8_in_0 = *valp & 0xff; - label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); - *valp = label8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_label8_encode (uint32 *valp) -{ - unsigned label8_in_0; - unsigned label8_out_0; - label8_out_0 = *valp; - label8_in_0 = (label8_out_0 - 0x4) & 0xff; - *valp = label8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) -{ - unsigned ulabel8_out_0; - unsigned ulabel8_in_0; - ulabel8_in_0 = *valp & 0xff; - ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); - *valp = ulabel8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) -{ - unsigned ulabel8_in_0; - unsigned ulabel8_out_0; - ulabel8_out_0 = *valp; - ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; - *valp = ulabel8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_label12_decode (uint32 *valp) -{ - unsigned label12_out_0; - unsigned label12_in_0; - label12_in_0 = *valp & 0xfff; - label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); - *valp = label12_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_label12_encode (uint32 *valp) -{ - unsigned label12_in_0; - unsigned label12_out_0; - label12_out_0 = *valp; - label12_in_0 = (label12_out_0 - 0x4) & 0xfff; - *valp = label12_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffset_decode (uint32 *valp) -{ - unsigned soffset_out_0; - unsigned soffset_in_0; - soffset_in_0 = *valp & 0x3ffff; - soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); - *valp = soffset_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffset_encode (uint32 *valp) -{ - unsigned soffset_in_0; - unsigned soffset_out_0; - soffset_out_0 = *valp; - soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; - *valp = soffset_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) -{ - unsigned uimm16x4_out_0; - unsigned uimm16x4_in_0; - uimm16x4_in_0 = *valp & 0xffff; - uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; - *valp = uimm16x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) -{ - unsigned uimm16x4_in_0; - unsigned uimm16x4_out_0; - uimm16x4_out_0 = *valp; - uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; - *valp = uimm16x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_bbi_decode (uint32 *valp) -{ - unsigned bbi_out_0; - unsigned bbi_in_0; - bbi_in_0 = *valp & 0x1f; - bbi_out_0 = (0 << 5) | bbi_in_0; - *valp = bbi_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_bbi_encode (uint32 *valp) -{ - unsigned bbi_in_0; - unsigned bbi_out_0; - bbi_out_0 = *valp; - bbi_in_0 = (bbi_out_0 & 0x1f); - *valp = bbi_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_s_decode (uint32 *valp) -{ - unsigned s_out_0; - unsigned s_in_0; - s_in_0 = *valp & 0xf; - s_out_0 = (0 << 4) | s_in_0; - *valp = s_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_s_encode (uint32 *valp) -{ - unsigned s_in_0; - unsigned s_out_0; - s_out_0 = *valp; - s_in_0 = (s_out_0 & 0xf); - *valp = s_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_immt_decode (uint32 *valp) -{ - unsigned immt_out_0; - unsigned immt_in_0; - immt_in_0 = *valp & 0xf; - immt_out_0 = immt_in_0; - *valp = immt_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_immt_encode (uint32 *valp) -{ - unsigned immt_in_0; - unsigned immt_out_0; - immt_out_0 = *valp; - immt_in_0 = immt_out_0 & 0xf; - *valp = immt_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_BR_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16); - return error; -} - -static int -OperandSem_opnd_sem_BR2_decode (uint32 *valp) -{ - *valp = *valp << 1; - return 0; -} - -static int -OperandSem_opnd_sem_BR2_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16) || ((*valp & 1) != 0); - *valp = *valp >> 1; - return error; -} - -static int -OperandSem_opnd_sem_BR4_decode (uint32 *valp) -{ - *valp = *valp << 2; - return 0; -} - -static int -OperandSem_opnd_sem_BR4_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16) || ((*valp & 3) != 0); - *valp = *valp >> 2; - return error; -} - -static int -OperandSem_opnd_sem_BR8_decode (uint32 *valp) -{ - *valp = *valp << 3; - return 0; -} - -static int -OperandSem_opnd_sem_BR8_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16) || ((*valp & 7) != 0); - *valp = *valp >> 3; - return error; -} - -static int -OperandSem_opnd_sem_BR16_decode (uint32 *valp) -{ - *valp = *valp << 4; - return 0; -} - -static int -OperandSem_opnd_sem_BR16_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16) || ((*valp & 15) != 0); - *valp = *valp >> 4; - return error; -} - -static int -OperandSem_opnd_sem_tp7_decode (uint32 *valp) -{ - unsigned tp7_out_0; - unsigned tp7_in_0; - tp7_in_0 = *valp & 0xf; - tp7_out_0 = tp7_in_0 + 0x7; - *valp = tp7_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_tp7_encode (uint32 *valp) -{ - unsigned tp7_in_0; - unsigned tp7_out_0; - tp7_out_0 = *valp; - tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; - *valp = tp7_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) -{ - unsigned xt_wbr15_label_out_0; - unsigned xt_wbr15_label_in_0; - xt_wbr15_label_in_0 = *valp & 0x7fff; - xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); - *valp = xt_wbr15_label_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) -{ - unsigned xt_wbr15_label_in_0; - unsigned xt_wbr15_label_out_0; - xt_wbr15_label_out_0 = *valp; - xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; - *valp = xt_wbr15_label_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_samt32_decode (uint32 *valp) -{ - unsigned ae_samt32_out_0; - unsigned ae_samt32_in_0; - ae_samt32_in_0 = *valp & 0x1f; - ae_samt32_out_0 = (0 << 5) | ae_samt32_in_0; - *valp = ae_samt32_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_samt32_encode (uint32 *valp) -{ - unsigned ae_samt32_in_0; - unsigned ae_samt32_out_0; - ae_samt32_out_0 = *valp; - ae_samt32_in_0 = (ae_samt32_out_0 & 0x1f); - *valp = ae_samt32_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_AE_PR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AE_PR_encode (uint32 *valp) -{ - int error; - error = (*valp >= 8); - return error; -} - -static int -OperandSem_opnd_sem_AE_QR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AE_QR_encode (uint32 *valp) -{ - int error; - error = (*valp >= 4); - return error; -} - -static int -OperandSem_opnd_sem_ae_lsimm16_decode (uint32 *valp) -{ - unsigned ae_lsimm16_out_0; - unsigned ae_lsimm16_in_0; - ae_lsimm16_in_0 = *valp & 0xf; - ae_lsimm16_out_0 = (((int) ae_lsimm16_in_0 << 28) >> 28) << 1; - *valp = ae_lsimm16_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm16_encode (uint32 *valp) -{ - unsigned ae_lsimm16_in_0; - unsigned ae_lsimm16_out_0; - ae_lsimm16_out_0 = *valp; - ae_lsimm16_in_0 = ((ae_lsimm16_out_0 >> 1) & 0xf); - *valp = ae_lsimm16_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm32_decode (uint32 *valp) -{ - unsigned ae_lsimm32_out_0; - unsigned ae_lsimm32_in_0; - ae_lsimm32_in_0 = *valp & 0xf; - ae_lsimm32_out_0 = (((int) ae_lsimm32_in_0 << 28) >> 28) << 2; - *valp = ae_lsimm32_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm32_encode (uint32 *valp) -{ - unsigned ae_lsimm32_in_0; - unsigned ae_lsimm32_out_0; - ae_lsimm32_out_0 = *valp; - ae_lsimm32_in_0 = ((ae_lsimm32_out_0 >> 2) & 0xf); - *valp = ae_lsimm32_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm64_decode (uint32 *valp) -{ - unsigned ae_lsimm64_out_0; - unsigned ae_lsimm64_in_0; - ae_lsimm64_in_0 = *valp & 0xf; - ae_lsimm64_out_0 = (((int) ae_lsimm64_in_0 << 28) >> 28) << 3; - *valp = ae_lsimm64_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm64_encode (uint32 *valp) -{ - unsigned ae_lsimm64_in_0; - unsigned ae_lsimm64_out_0; - ae_lsimm64_out_0 = *valp; - ae_lsimm64_in_0 = ((ae_lsimm64_out_0 >> 3) & 0xf); - *valp = ae_lsimm64_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_samt64_decode (uint32 *valp) -{ - unsigned ae_samt64_out_0; - unsigned ae_samt64_in_0; - ae_samt64_in_0 = *valp & 0x3f; - ae_samt64_out_0 = (0 << 6) | ae_samt64_in_0; - *valp = ae_samt64_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_samt64_encode (uint32 *valp) -{ - unsigned ae_samt64_in_0; - unsigned ae_samt64_out_0; - ae_samt64_out_0 = *valp; - ae_samt64_in_0 = (ae_samt64_out_0 & 0x3f); - *valp = ae_samt64_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp) -{ - unsigned ae_ohba_out_0; - unsigned ae_ohba_in_0; - ae_ohba_in_0 = *valp & 0xf; - ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf)); - *valp = ae_ohba_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp) -{ - unsigned ae_ohba_in_0; - unsigned ae_ohba_out_0; - ae_ohba_out_0 = *valp; - ae_ohba_in_0 = (ae_ohba_out_0 & 0xf); - *valp = ae_ohba_in_0; - return 0; -} - -static int -Operand_soffsetx4_ator (uint32 *valp, uint32 pc) -{ - *valp -= (pc & ~0x3); - return 0; -} - -static int -Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += (pc & ~0x3); - return 0; -} - -static int -Operand_uimm6_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_uimm6_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_label8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ulabel8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_label12_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label12_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_soffset_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_soffset_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_uimm16x4_ator (uint32 *valp, uint32 pc) -{ - *valp -= ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static xtensa_operand_internal operands[] = { - { "soffsetx4", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, - Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, - { "uimm12x8", FIELD_imm12, -1, 0, - 0, - OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, - 0, 0 }, - { "simm4", FIELD_mn, -1, 0, - 0, - OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, - 0, 0 }, - { "arr", FIELD_r, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "ars", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "*ars_invisible", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "art", FIELD_t, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "ar0", FIELD__ar0, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, - 0, 0 }, - { "ar4", FIELD__ar4, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode, - 0, 0 }, - { "ar8", FIELD__ar8, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode, - 0, 0 }, - { "ar12", FIELD__ar12, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode, - 0, 0 }, - { "ars_entry", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, - 0, 0 }, - { "immrx4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, - 0, 0 }, - { "lsi4x4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, - 0, 0 }, - { "simm7", FIELD_imm7, -1, 0, - 0, - OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, - 0, 0 }, - { "uimm6", FIELD_imm6, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, - Operand_uimm6_ator, Operand_uimm6_rtoa }, - { "ai4const", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, - 0, 0 }, - { "b4const", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, - 0, 0 }, - { "b4constu", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, - 0, 0 }, - { "uimm8", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, - 0, 0 }, - { "uimm8x2", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, - 0, 0 }, - { "uimm8x4", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, - 0, 0 }, - { "uimm4x16", FIELD_op2, -1, 0, - 0, - OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, - 0, 0 }, - { "uimmrx4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, - 0, 0 }, - { "simm8", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, - 0, 0 }, - { "simm8x256", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, - 0, 0 }, - { "simm12b", FIELD_imm12b, -1, 0, - 0, - OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, - 0, 0 }, - { "msalp32", FIELD_sal, -1, 0, - 0, - OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, - 0, 0 }, - { "op2p1", FIELD_op2, -1, 0, - 0, - OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, - 0, 0 }, - { "label8", FIELD_imm8, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, - Operand_label8_ator, Operand_label8_rtoa }, - { "ulabel8", FIELD_imm8, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, - Operand_ulabel8_ator, Operand_ulabel8_rtoa }, - { "label12", FIELD_imm12, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, - Operand_label12_ator, Operand_label12_rtoa }, - { "soffset", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, - Operand_soffset_ator, Operand_soffset_rtoa }, - { "uimm16x4", FIELD_imm16, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, - Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, - { "bbi", FIELD_bbi, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sae", FIELD_sae, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sas", FIELD_sas, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sargt", FIELD_sargt, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "s", FIELD_s, -1, 0, - 0, - OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, - 0, 0 }, - { "immt", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, - 0, 0 }, - { "imms", FIELD_s, -1, 0, - 0, - OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, - 0, 0 }, - { "bt", FIELD_t, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, - 0, 0 }, - { "bs", FIELD_s, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, - 0, 0 }, - { "br", FIELD_r, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, - 0, 0 }, - { "bt2", FIELD_t2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, - 0, 0 }, - { "bs2", FIELD_s2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, - 0, 0 }, - { "br2", FIELD_r2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, - 0, 0 }, - { "bt4", FIELD_t4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, - 0, 0 }, - { "bs4", FIELD_s4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, - 0, 0 }, - { "br4", FIELD_r4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, - 0, 0 }, - { "bt8", FIELD_t8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, - 0, 0 }, - { "bs8", FIELD_s8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, - 0, 0 }, - { "br8", FIELD_r8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, - 0, 0 }, - { "bt16", FIELD__bt16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, - 0, 0 }, - { "bs16", FIELD__bs16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, - 0, 0 }, - { "br16", FIELD__br16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, - 0, 0 }, - { "brall", FIELD__brall, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, - 0, 0 }, - { "tp7", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, - 0, 0 }, - { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, - Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, - { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, - Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, - { "ae_samt32", FIELD_ftsf14, -1, 0, - 0, - OperandSem_opnd_sem_ae_samt32_encode, OperandSem_opnd_sem_ae_samt32_decode, - 0, 0 }, - { "pr0", FIELD_ftsf12, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "qr0", FIELD_ftsf13, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "mac_qr0", FIELD_ftsf13, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "ae_lsimm16", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ae_lsimm16_encode, OperandSem_opnd_sem_ae_lsimm16_decode, - 0, 0 }, - { "ae_lsimm32", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ae_lsimm32_encode, OperandSem_opnd_sem_ae_lsimm32_decode, - 0, 0 }, - { "ae_lsimm64", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ae_lsimm64_encode, OperandSem_opnd_sem_ae_lsimm64_decode, - 0, 0 }, - { "ae_samt64", FIELD_ae_samt_s_t, -1, 0, - 0, - OperandSem_opnd_sem_ae_samt64_encode, OperandSem_opnd_sem_ae_samt64_decode, - 0, 0 }, - { "ae_ohba", FIELD_ae_fld_ohba, -1, 0, - 0, - OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, - 0, 0 }, - { "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0, - 0, - OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, - 0, 0 }, - { "pr", FIELD_ae_r20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "ps", FIELD_ae_s20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "bitindex", FIELD_bitindex, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, - { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, - { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, - { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, - { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, - { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, - { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, - { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, - { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, - { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, - { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, - { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, - { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, - { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, - { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, - { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, - { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, - { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, - { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, - { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, - { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, - { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, - { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, - { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, - { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, - { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, - { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, - { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, - { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, - { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, - { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r3", FIELD_ae_r3, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s_non_samt", FIELD_ae_s_non_samt, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s3", FIELD_ae_s3, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r32", FIELD_ae_r32, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_samt_s_t", FIELD_ae_samt_s_t, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf14", FIELD_ftsf14, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf21ae_slot1", FIELD_ftsf21ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf22ae_slot1", FIELD_ftsf22ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf23ae_slot1", FIELD_ftsf23ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf24ae_slot1", FIELD_ftsf24ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf25ae_slot1", FIELD_ftsf25ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf26ae_slot1", FIELD_ftsf26ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf27ae_slot1", FIELD_ftsf27ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf28ae_slot1", FIELD_ftsf28ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf29ae_slot1", FIELD_ftsf29ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf30ae_slot1", FIELD_ftsf30ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf31ae_slot1", FIELD_ftsf31ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf32ae_slot1", FIELD_ftsf32ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf33ae_slot1", FIELD_ftsf33ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf34ae_slot1", FIELD_ftsf34ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf35ae_slot1", FIELD_ftsf35ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf36ae_slot1", FIELD_ftsf36ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf37ae_slot1", FIELD_ftsf37ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf38ae_slot1", FIELD_ftsf38ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf39ae_slot1", FIELD_ftsf39ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf40ae_slot1", FIELD_ftsf40ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf41ae_slot1", FIELD_ftsf41ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf42ae_slot1", FIELD_ftsf42ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf43ae_slot1", FIELD_ftsf43ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf44ae_slot1", FIELD_ftsf44ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf45ae_slot1", FIELD_ftsf45ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf46ae_slot1", FIELD_ftsf46ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf47ae_slot1", FIELD_ftsf47ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf48ae_slot1", FIELD_ftsf48ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf49ae_slot1", FIELD_ftsf49ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf50ae_slot1", FIELD_ftsf50ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf51ae_slot1", FIELD_ftsf51ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf52ae_slot1", FIELD_ftsf52ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf53ae_slot1", FIELD_ftsf53ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf54ae_slot1", FIELD_ftsf54ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf55ae_slot1", FIELD_ftsf55ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf56ae_slot1", FIELD_ftsf56ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf57ae_slot1", FIELD_ftsf57ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf58ae_slot1", FIELD_ftsf58ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf59ae_slot1", FIELD_ftsf59ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf60ae_slot1", FIELD_ftsf60ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf61ae_slot1", FIELD_ftsf61ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf63ae_slot1", FIELD_ftsf63ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf64ae_slot1", FIELD_ftsf64ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf66ae_slot1", FIELD_ftsf66ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf67ae_slot1", FIELD_ftsf67ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf69ae_slot1", FIELD_ftsf69ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf71ae_slot1", FIELD_ftsf71ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf72ae_slot1", FIELD_ftsf72ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf73ae_slot1", FIELD_ftsf73ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf75ae_slot1", FIELD_ftsf75ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf76ae_slot1", FIELD_ftsf76ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf77ae_slot1", FIELD_ftsf77ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf78ae_slot1", FIELD_ftsf78ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf79ae_slot1", FIELD_ftsf79ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf80ae_slot1", FIELD_ftsf80ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf81ae_slot1", FIELD_ftsf81ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf82ae_slot1", FIELD_ftsf82ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf84ae_slot1", FIELD_ftsf84ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf86ae_slot1", FIELD_ftsf86ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf87ae_slot1", FIELD_ftsf87ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf88ae_slot1", FIELD_ftsf88ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf89ae_slot1", FIELD_ftsf89ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf90ae_slot1", FIELD_ftsf90ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf91ae_slot1", FIELD_ftsf91ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf92ae_slot1", FIELD_ftsf92ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf94ae_slot1", FIELD_ftsf94ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf96ae_slot1", FIELD_ftsf96ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf97ae_slot1", FIELD_ftsf97ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf98ae_slot1", FIELD_ftsf98ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf99ae_slot1", FIELD_ftsf99ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf100ae_slot1", FIELD_ftsf100ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf101ae_slot1", FIELD_ftsf101ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf103ae_slot1", FIELD_ftsf103ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf104ae_slot1", FIELD_ftsf104ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf105ae_slot1", FIELD_ftsf105ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf106ae_slot1", FIELD_ftsf106ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf107ae_slot1", FIELD_ftsf107ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf108ae_slot1", FIELD_ftsf108ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf109ae_slot1", FIELD_ftsf109ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf110ae_slot1", FIELD_ftsf110ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf111ae_slot1", FIELD_ftsf111ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf112ae_slot1", FIELD_ftsf112ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf113ae_slot1", FIELD_ftsf113ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf114ae_slot1", FIELD_ftsf114ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf115ae_slot1", FIELD_ftsf115ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf116ae_slot1", FIELD_ftsf116ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf118ae_slot1", FIELD_ftsf118ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf119ae_slot1", FIELD_ftsf119ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf120ae_slot1", FIELD_ftsf120ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf122ae_slot1", FIELD_ftsf122ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf124ae_slot1", FIELD_ftsf124ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf125ae_slot1", FIELD_ftsf125ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf126ae_slot1", FIELD_ftsf126ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf127ae_slot1", FIELD_ftsf127ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf128ae_slot1", FIELD_ftsf128ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf129ae_slot1", FIELD_ftsf129ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf130ae_slot1", FIELD_ftsf130ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf131ae_slot1", FIELD_ftsf131ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf132ae_slot1", FIELD_ftsf132ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf133ae_slot1", FIELD_ftsf133ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf134ae_slot1", FIELD_ftsf134ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf135ae_slot1", FIELD_ftsf135ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf136ae_slot1", FIELD_ftsf136ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf137ae_slot1", FIELD_ftsf137ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf138ae_slot1", FIELD_ftsf138ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf139ae_slot1", FIELD_ftsf139ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf140ae_slot1", FIELD_ftsf140ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf141ae_slot1", FIELD_ftsf141ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf142ae_slot1", FIELD_ftsf142ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf143ae_slot1", FIELD_ftsf143ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf144ae_slot1", FIELD_ftsf144ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf145ae_slot1", FIELD_ftsf145ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf146ae_slot1", FIELD_ftsf146ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf147ae_slot1", FIELD_ftsf147ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf148ae_slot1", FIELD_ftsf148ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf149ae_slot1", FIELD_ftsf149ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf150ae_slot1", FIELD_ftsf150ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf151ae_slot1", FIELD_ftsf151ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf152ae_slot1", FIELD_ftsf152ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf153ae_slot1", FIELD_ftsf153ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf154ae_slot1", FIELD_ftsf154ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf155ae_slot1", FIELD_ftsf155ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf156ae_slot1", FIELD_ftsf156ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf157ae_slot1", FIELD_ftsf157ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - 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{ "ftsf295ae_slot0", FIELD_ftsf295ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf296ae_slot0", FIELD_ftsf296ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf297ae_slot0", FIELD_ftsf297ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf298ae_slot0", FIELD_ftsf298ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf299ae_slot0", FIELD_ftsf299ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf300ae_slot0", FIELD_ftsf300ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf301ae_slot0", FIELD_ftsf301ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf302ae_slot0", FIELD_ftsf302ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf303ae_slot0", FIELD_ftsf303ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf304ae_slot0", FIELD_ftsf304ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf306ae_slot0", FIELD_ftsf306ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf308ae_slot0", FIELD_ftsf308ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf309ae_slot0", FIELD_ftsf309ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf310ae_slot0", FIELD_ftsf310ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf311ae_slot0", FIELD_ftsf311ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf312ae_slot0", FIELD_ftsf312ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf313ae_slot0", FIELD_ftsf313ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf314ae_slot0", FIELD_ftsf314ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf315ae_slot0", FIELD_ftsf315ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf316ae_slot0", FIELD_ftsf316ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf317ae_slot0", FIELD_ftsf317ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf318ae_slot0", FIELD_ftsf318ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf319", FIELD_ftsf319, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf320ae_slot0", FIELD_ftsf320ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf321", FIELD_ftsf321, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf322ae_slot0", FIELD_ftsf322ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf323ae_slot0", FIELD_ftsf323ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf324ae_slot0", FIELD_ftsf324ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf325ae_slot0", FIELD_ftsf325ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf326ae_slot0", FIELD_ftsf326ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf328ae_slot0", FIELD_ftsf328ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf329ae_slot0", FIELD_ftsf329ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf352ae_slot0", FIELD_ftsf352ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf353", FIELD_ftsf353, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf354ae_slot0", FIELD_ftsf354ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf356ae_slot0", FIELD_ftsf356ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf357", FIELD_ftsf357, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf358ae_slot0", FIELD_ftsf358ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf359ae_slot0", FIELD_ftsf359ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf360ae_slot0", FIELD_ftsf360ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf361ae_slot0", FIELD_ftsf361ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf362ae_slot0", FIELD_ftsf362ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf364ae_slot0", FIELD_ftsf364ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf365ae_slot0", FIELD_ftsf365ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf366ae_slot0", FIELD_ftsf366ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf368ae_slot0", FIELD_ftsf368ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf369ae_slot0", FIELD_ftsf369ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_mul32x24fld", FIELD_ae_mul32x24fld, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld115", FIELD_combined1b97e84f_fld115, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld97", FIELD_combined1b97e84f_fld97, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld124", FIELD_combined1b97e84f_fld124, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld79", FIELD_combined1b97e84f_fld79, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld80", FIELD_combined1b97e84f_fld80, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld108", FIELD_combined1b97e84f_fld108, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld101", FIELD_combined1b97e84f_fld101, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld88", FIELD_combined1b97e84f_fld88, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld39", FIELD_combined1b97e84f_fld39, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s4_s4", FIELD_op0_s4_s4, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld83", FIELD_combined1b97e84f_fld83, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld90", FIELD_combined1b97e84f_fld90, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld93", FIELD_combined1b97e84f_fld93, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld138ae_slot0", FIELD_combined1b97e84f_fld138ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld130ae_slot0", FIELD_combined1b97e84f_fld130ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld137ae_slot0", FIELD_combined1b97e84f_fld137ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld135ae_slot0", FIELD_combined1b97e84f_fld135ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld136ae_slot0", FIELD_combined1b97e84f_fld136ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld129ae_slot0", FIELD_combined1b97e84f_fld129ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld127ae_slot0", FIELD_combined1b97e84f_fld127ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld128ae_slot0", FIELD_combined1b97e84f_fld128ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld132ae_slot0", FIELD_combined1b97e84f_fld132ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld134ae_slot0", FIELD_combined1b97e84f_fld134ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld122", FIELD_combined4b12daa6_fld122, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld115", FIELD_combined4b12daa6_fld115, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld85", FIELD_combined4b12daa6_fld85, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld119", FIELD_combined4b12daa6_fld119, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld97", FIELD_combined4b12daa6_fld97, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld124", FIELD_combined4b12daa6_fld124, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld79", FIELD_combined4b12daa6_fld79, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld80", FIELD_combined4b12daa6_fld80, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld108", FIELD_combined4b12daa6_fld108, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld54", FIELD_combined1b97e84f_fld54, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld17", FIELD_combined1b97e84f_fld17, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld76", FIELD_combined1b97e84f_fld76, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld73", FIELD_combined1b97e84f_fld73, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld62", FIELD_combined1b97e84f_fld62, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld24", FIELD_combined1b97e84f_fld24, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld70", FIELD_combined1b97e84f_fld70, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld58", FIELD_combined1b97e84f_fld58, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld131ae_slot1", FIELD_combined1b97e84f_fld131ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s3_s3", FIELD_op0_s3_s3, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld49", FIELD_combined1b97e84f_fld49, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld51", FIELD_combined1b97e84f_fld51, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld23", FIELD_combined1b97e84f_fld23, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_fld0", FIELD_xt_fld0, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_fld1", FIELD_xt_fld1, -1, 0, 0, 0, 0, 0, 0 }, - { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } -}; - -enum xtensa_operand_id { - OPERAND_soffsetx4, - OPERAND_uimm12x8, - OPERAND_simm4, - OPERAND_arr, - OPERAND_ars, - OPERAND__ars_invisible, - OPERAND_art, - OPERAND_ar0, - OPERAND_ar4, - OPERAND_ar8, - OPERAND_ar12, - OPERAND_ars_entry, - OPERAND_immrx4, - OPERAND_lsi4x4, - OPERAND_simm7, - OPERAND_uimm6, - OPERAND_ai4const, - OPERAND_b4const, - OPERAND_b4constu, - OPERAND_uimm8, - OPERAND_uimm8x2, - OPERAND_uimm8x4, - OPERAND_uimm4x16, - OPERAND_uimmrx4, - OPERAND_simm8, - OPERAND_simm8x256, - OPERAND_simm12b, - OPERAND_msalp32, - OPERAND_op2p1, - OPERAND_label8, - OPERAND_ulabel8, - OPERAND_label12, - OPERAND_soffset, - OPERAND_uimm16x4, - OPERAND_bbi, - OPERAND_sae, - OPERAND_sas, - OPERAND_sargt, - OPERAND_s, - OPERAND_immt, - OPERAND_imms, - OPERAND_bt, - OPERAND_bs, - OPERAND_br, - OPERAND_bt2, - OPERAND_bs2, - OPERAND_br2, - OPERAND_bt4, - OPERAND_bs4, - OPERAND_br4, - OPERAND_bt8, - OPERAND_bs8, - OPERAND_br8, - OPERAND_bt16, - OPERAND_bs16, - OPERAND_br16, - OPERAND_brall, - OPERAND_tp7, - OPERAND_xt_wbr15_label, - OPERAND_xt_wbr18_label, - OPERAND_ae_samt32, - OPERAND_pr0, - OPERAND_qr0, - OPERAND_mac_qr0, - OPERAND_ae_lsimm16, - OPERAND_ae_lsimm32, - OPERAND_ae_lsimm64, - OPERAND_ae_samt64, - OPERAND_ae_ohba, - OPERAND_ae_ohba2, - OPERAND_pr, - OPERAND_cvt_pr, - OPERAND_qr0_rw, - OPERAND_mac_qr0_rw, - OPERAND_qr1_w, - OPERAND_mac_qr1_w, - OPERAND_ps, - OPERAND_alupppb_ps, - OPERAND_bitindex, - OPERAND_t, - OPERAND_bbi4, - OPERAND_imm12, - OPERAND_imm8, - OPERAND_imm12b, - OPERAND_imm16, - OPERAND_m, - OPERAND_n, - OPERAND_offset, - OPERAND_op0, - OPERAND_op1, - OPERAND_op2, - OPERAND_r, - OPERAND_sa4, - OPERAND_sae4, - OPERAND_sal, - OPERAND_sas4, - OPERAND_sr, - OPERAND_st, - OPERAND_thi3, - OPERAND_imm4, - OPERAND_mn, - OPERAND_i, - OPERAND_imm6lo, - OPERAND_imm6hi, - OPERAND_imm7lo, - OPERAND_imm7hi, - OPERAND_z, - OPERAND_imm6, - OPERAND_imm7, - OPERAND_t2, - OPERAND_s2, - OPERAND_r2, - OPERAND_t4, - OPERAND_s4, - OPERAND_r4, - OPERAND_t8, - OPERAND_s8, - OPERAND_r8, - OPERAND_xt_wbr15_imm, - OPERAND_xt_wbr18_imm, - OPERAND_ae_r3, - OPERAND_ae_s_non_samt, - OPERAND_ae_s3, - OPERAND_ae_r32, - OPERAND_ae_samt_s_t, - OPERAND_ae_r20, - OPERAND_ae_r10, - OPERAND_ae_s20, - OPERAND_ae_fld_ohba, - OPERAND_ae_fld_ohba2, - OPERAND_op0_s3, - OPERAND_ftsf12, - OPERAND_ftsf13, - OPERAND_ftsf14, - OPERAND_ftsf21ae_slot1, - OPERAND_ftsf22ae_slot1, - OPERAND_ftsf23ae_slot1, - OPERAND_ftsf24ae_slot1, - OPERAND_ftsf25ae_slot1, - OPERAND_ftsf26ae_slot1, - OPERAND_ftsf27ae_slot1, - OPERAND_ftsf28ae_slot1, - OPERAND_ftsf29ae_slot1, - OPERAND_ftsf30ae_slot1, - OPERAND_ftsf31ae_slot1, - OPERAND_ftsf32ae_slot1, - OPERAND_ftsf33ae_slot1, - OPERAND_ftsf34ae_slot1, - OPERAND_ftsf35ae_slot1, - OPERAND_ftsf36ae_slot1, - OPERAND_ftsf37ae_slot1, - OPERAND_ftsf38ae_slot1, - OPERAND_ftsf39ae_slot1, - OPERAND_ftsf40ae_slot1, - OPERAND_ftsf41ae_slot1, - OPERAND_ftsf42ae_slot1, - OPERAND_ftsf43ae_slot1, - OPERAND_ftsf44ae_slot1, - OPERAND_ftsf45ae_slot1, - OPERAND_ftsf46ae_slot1, - OPERAND_ftsf47ae_slot1, - OPERAND_ftsf48ae_slot1, - OPERAND_ftsf49ae_slot1, - OPERAND_ftsf50ae_slot1, - OPERAND_ftsf51ae_slot1, - OPERAND_ftsf52ae_slot1, - OPERAND_ftsf53ae_slot1, - OPERAND_ftsf54ae_slot1, - OPERAND_ftsf55ae_slot1, - OPERAND_ftsf56ae_slot1, - OPERAND_ftsf57ae_slot1, - OPERAND_ftsf58ae_slot1, - OPERAND_ftsf59ae_slot1, - OPERAND_ftsf60ae_slot1, - OPERAND_ftsf61ae_slot1, - OPERAND_ftsf63ae_slot1, - OPERAND_ftsf64ae_slot1, - OPERAND_ftsf66ae_slot1, - OPERAND_ftsf67ae_slot1, - OPERAND_ftsf69ae_slot1, - OPERAND_ftsf71ae_slot1, - OPERAND_ftsf72ae_slot1, - OPERAND_ftsf73ae_slot1, - OPERAND_ftsf75ae_slot1, - OPERAND_ftsf76ae_slot1, - OPERAND_ftsf77ae_slot1, - OPERAND_ftsf78ae_slot1, - OPERAND_ftsf79ae_slot1, - OPERAND_ftsf80ae_slot1, - OPERAND_ftsf81ae_slot1, - OPERAND_ftsf82ae_slot1, - OPERAND_ftsf84ae_slot1, - OPERAND_ftsf86ae_slot1, - OPERAND_ftsf87ae_slot1, - OPERAND_ftsf88ae_slot1, - OPERAND_ftsf89ae_slot1, - OPERAND_ftsf90ae_slot1, - OPERAND_ftsf91ae_slot1, - OPERAND_ftsf92ae_slot1, - OPERAND_ftsf94ae_slot1, - OPERAND_ftsf96ae_slot1, - OPERAND_ftsf97ae_slot1, - OPERAND_ftsf98ae_slot1, - OPERAND_ftsf99ae_slot1, - OPERAND_ftsf100ae_slot1, - OPERAND_ftsf101ae_slot1, - OPERAND_ftsf103ae_slot1, - OPERAND_ftsf104ae_slot1, - OPERAND_ftsf105ae_slot1, - OPERAND_ftsf106ae_slot1, - OPERAND_ftsf107ae_slot1, - OPERAND_ftsf108ae_slot1, - OPERAND_ftsf109ae_slot1, - OPERAND_ftsf110ae_slot1, - OPERAND_ftsf111ae_slot1, - OPERAND_ftsf112ae_slot1, - OPERAND_ftsf113ae_slot1, - OPERAND_ftsf114ae_slot1, - OPERAND_ftsf115ae_slot1, - OPERAND_ftsf116ae_slot1, - OPERAND_ftsf118ae_slot1, - OPERAND_ftsf119ae_slot1, - OPERAND_ftsf120ae_slot1, - OPERAND_ftsf122ae_slot1, - OPERAND_ftsf124ae_slot1, - OPERAND_ftsf125ae_slot1, - OPERAND_ftsf126ae_slot1, - OPERAND_ftsf127ae_slot1, - OPERAND_ftsf128ae_slot1, - OPERAND_ftsf129ae_slot1, - OPERAND_ftsf130ae_slot1, - OPERAND_ftsf131ae_slot1, - OPERAND_ftsf132ae_slot1, - OPERAND_ftsf133ae_slot1, - OPERAND_ftsf134ae_slot1, - OPERAND_ftsf135ae_slot1, - OPERAND_ftsf136ae_slot1, - OPERAND_ftsf137ae_slot1, - OPERAND_ftsf138ae_slot1, - OPERAND_ftsf139ae_slot1, - OPERAND_ftsf140ae_slot1, - OPERAND_ftsf141ae_slot1, - OPERAND_ftsf142ae_slot1, - OPERAND_ftsf143ae_slot1, - OPERAND_ftsf144ae_slot1, - OPERAND_ftsf145ae_slot1, - OPERAND_ftsf146ae_slot1, - OPERAND_ftsf147ae_slot1, - OPERAND_ftsf148ae_slot1, - OPERAND_ftsf149ae_slot1, - OPERAND_ftsf150ae_slot1, - OPERAND_ftsf151ae_slot1, - OPERAND_ftsf152ae_slot1, - OPERAND_ftsf153ae_slot1, - OPERAND_ftsf154ae_slot1, - OPERAND_ftsf155ae_slot1, - OPERAND_ftsf156ae_slot1, - OPERAND_ftsf157ae_slot1, - OPERAND_ftsf158ae_slot1, - OPERAND_ftsf159ae_slot1, - OPERAND_ftsf160ae_slot1, - OPERAND_ftsf161ae_slot1, - OPERAND_ftsf162ae_slot1, - OPERAND_ftsf163ae_slot1, - OPERAND_ftsf164ae_slot1, - OPERAND_ftsf165ae_slot1, - OPERAND_ftsf166ae_slot1, - OPERAND_ftsf167ae_slot1, - OPERAND_ftsf168ae_slot1, - OPERAND_ftsf169ae_slot1, - OPERAND_ftsf170ae_slot1, - OPERAND_ftsf171ae_slot1, - OPERAND_ftsf172ae_slot1, - OPERAND_ftsf173ae_slot1, - OPERAND_ftsf174ae_slot1, - OPERAND_ftsf175ae_slot1, - OPERAND_ftsf176ae_slot1, - OPERAND_ftsf177ae_slot1, - OPERAND_ftsf178ae_slot1, - OPERAND_ftsf179ae_slot1, - OPERAND_ftsf180ae_slot1, - OPERAND_ftsf181ae_slot1, - OPERAND_ftsf182ae_slot1, - OPERAND_ftsf183ae_slot1, - OPERAND_ftsf184ae_slot1, - OPERAND_ftsf185ae_slot1, - OPERAND_ftsf186ae_slot1, - OPERAND_ftsf187ae_slot1, - OPERAND_ftsf188ae_slot1, - OPERAND_ftsf189ae_slot1, - OPERAND_ftsf190ae_slot1, - OPERAND_ftsf191ae_slot1, - OPERAND_ftsf192ae_slot1, - OPERAND_ftsf193ae_slot1, - OPERAND_ftsf194ae_slot1, - OPERAND_ftsf195ae_slot1, - OPERAND_ftsf196ae_slot1, - OPERAND_ftsf197ae_slot1, - OPERAND_ftsf198ae_slot1, - OPERAND_ftsf199ae_slot1, - OPERAND_ftsf200ae_slot1, - OPERAND_ftsf201ae_slot1, - OPERAND_ftsf202ae_slot1, - OPERAND_ftsf203ae_slot1, - OPERAND_ftsf204ae_slot1, - OPERAND_ftsf205ae_slot1, - OPERAND_ftsf206ae_slot1, - OPERAND_ftsf207ae_slot1, - OPERAND_ftsf208, - OPERAND_ftsf209ae_slot1, - OPERAND_ftsf210ae_slot1, - OPERAND_ftsf211ae_slot1, - OPERAND_ftsf330ae_slot1, - OPERAND_ftsf332ae_slot1, - OPERAND_ftsf334ae_slot1, - OPERAND_ftsf336ae_slot1, - OPERAND_ftsf337ae_slot1, - OPERAND_ftsf338, - OPERAND_ftsf339ae_slot1, - OPERAND_ftsf340, - OPERAND_ftsf341ae_slot1, - OPERAND_ftsf342ae_slot1, - OPERAND_ftsf343ae_slot1, - OPERAND_ftsf344ae_slot1, - OPERAND_ftsf346ae_slot1, - OPERAND_ftsf347, - OPERAND_ftsf348ae_slot1, - OPERAND_ftsf349ae_slot1, - OPERAND_ftsf350ae_slot1, - OPERAND_op0_s4, - OPERAND_ftsf212ae_slot0, - OPERAND_ftsf213ae_slot0, - OPERAND_ftsf214ae_slot0, - OPERAND_ftsf215ae_slot0, - OPERAND_ftsf216ae_slot0, - OPERAND_ftsf217, - OPERAND_ftsf218ae_slot0, - OPERAND_ftsf219ae_slot0, - OPERAND_ftsf220ae_slot0, - OPERAND_ftsf221ae_slot0, - OPERAND_ftsf222ae_slot0, - OPERAND_ftsf223ae_slot0, - OPERAND_ftsf224ae_slot0, - OPERAND_ftsf225ae_slot0, - OPERAND_ftsf226ae_slot0, - OPERAND_ftsf227ae_slot0, - OPERAND_ftsf228ae_slot0, - OPERAND_ftsf229ae_slot0, - OPERAND_ftsf230ae_slot0, - OPERAND_ftsf231ae_slot0, - OPERAND_ftsf232ae_slot0, - OPERAND_ftsf233ae_slot0, - OPERAND_ftsf234ae_slot0, - OPERAND_ftsf235ae_slot0, - OPERAND_ftsf236ae_slot0, - OPERAND_ftsf237ae_slot0, - OPERAND_ftsf238ae_slot0, - OPERAND_ftsf239ae_slot0, - OPERAND_ftsf240ae_slot0, - OPERAND_ftsf241ae_slot0, - OPERAND_ftsf242ae_slot0, - OPERAND_ftsf243ae_slot0, - OPERAND_ftsf244ae_slot0, - OPERAND_ftsf245ae_slot0, - OPERAND_ftsf246ae_slot0, - OPERAND_ftsf247ae_slot0, - OPERAND_ftsf248ae_slot0, - OPERAND_ftsf249ae_slot0, - OPERAND_ftsf250ae_slot0, - OPERAND_ftsf251ae_slot0, - OPERAND_ftsf252ae_slot0, - OPERAND_ftsf253ae_slot0, - OPERAND_ftsf254ae_slot0, - OPERAND_ftsf255ae_slot0, - OPERAND_ftsf256ae_slot0, - OPERAND_ftsf257ae_slot0, - OPERAND_ftsf258ae_slot0, - OPERAND_ftsf259ae_slot0, - OPERAND_ftsf260ae_slot0, - OPERAND_ftsf261ae_slot0, - OPERAND_ftsf262ae_slot0, - OPERAND_ftsf263ae_slot0, - OPERAND_ftsf264ae_slot0, - OPERAND_ftsf265ae_slot0, - OPERAND_ftsf266ae_slot0, - OPERAND_ftsf267ae_slot0, - OPERAND_ftsf268ae_slot0, - OPERAND_ftsf269ae_slot0, - OPERAND_ftsf270ae_slot0, - OPERAND_ftsf271ae_slot0, - OPERAND_ftsf272ae_slot0, - OPERAND_ftsf273ae_slot0, - OPERAND_ftsf274ae_slot0, - OPERAND_ftsf275ae_slot0, - OPERAND_ftsf276ae_slot0, - OPERAND_ftsf277ae_slot0, - OPERAND_ftsf278ae_slot0, - OPERAND_ftsf279ae_slot0, - OPERAND_ftsf281ae_slot0, - OPERAND_ftsf282ae_slot0, - OPERAND_ftsf283ae_slot0, - OPERAND_ftsf284ae_slot0, - OPERAND_ftsf286ae_slot0, - OPERAND_ftsf288ae_slot0, - OPERAND_ftsf290ae_slot0, - OPERAND_ftsf292ae_slot0, - OPERAND_ftsf293, - OPERAND_ftsf294ae_slot0, - OPERAND_ftsf295ae_slot0, - OPERAND_ftsf296ae_slot0, - OPERAND_ftsf297ae_slot0, - OPERAND_ftsf298ae_slot0, - OPERAND_ftsf299ae_slot0, - OPERAND_ftsf300ae_slot0, - OPERAND_ftsf301ae_slot0, - OPERAND_ftsf302ae_slot0, - OPERAND_ftsf303ae_slot0, - OPERAND_ftsf304ae_slot0, - OPERAND_ftsf306ae_slot0, - OPERAND_ftsf308ae_slot0, - OPERAND_ftsf309ae_slot0, - OPERAND_ftsf310ae_slot0, - OPERAND_ftsf311ae_slot0, - OPERAND_ftsf312ae_slot0, - OPERAND_ftsf313ae_slot0, - OPERAND_ftsf314ae_slot0, - OPERAND_ftsf315ae_slot0, - OPERAND_ftsf316ae_slot0, - OPERAND_ftsf317ae_slot0, - OPERAND_ftsf318ae_slot0, - OPERAND_ftsf319, - OPERAND_ftsf320ae_slot0, - OPERAND_ftsf321, - OPERAND_ftsf322ae_slot0, - OPERAND_ftsf323ae_slot0, - OPERAND_ftsf324ae_slot0, - OPERAND_ftsf325ae_slot0, - OPERAND_ftsf326ae_slot0, - OPERAND_ftsf328ae_slot0, - OPERAND_ftsf329ae_slot0, - OPERAND_ftsf352ae_slot0, - OPERAND_ftsf353, - OPERAND_ftsf354ae_slot0, - OPERAND_ftsf356ae_slot0, - OPERAND_ftsf357, - OPERAND_ftsf358ae_slot0, - OPERAND_ftsf359ae_slot0, - OPERAND_ftsf360ae_slot0, - OPERAND_ftsf361ae_slot0, - OPERAND_ftsf362ae_slot0, - OPERAND_ftsf364ae_slot0, - OPERAND_ftsf365ae_slot0, - OPERAND_ftsf366ae_slot0, - OPERAND_ftsf368ae_slot0, - OPERAND_ftsf369ae_slot0, - OPERAND_ae_mul32x24fld, - OPERAND_combined1b97e84f_fld115, - OPERAND_combined1b97e84f_fld97, - OPERAND_combined1b97e84f_fld124, - OPERAND_combined1b97e84f_fld79, - OPERAND_combined1b97e84f_fld80, - OPERAND_combined1b97e84f_fld108, - OPERAND_combined1b97e84f_fld101, - OPERAND_combined1b97e84f_fld88, - OPERAND_combined1b97e84f_fld39, - OPERAND_op0_s4_s4, - OPERAND_combined1b97e84f_fld83, - OPERAND_combined1b97e84f_fld90, - OPERAND_combined1b97e84f_fld93, - OPERAND_combined1b97e84f_fld138ae_slot0, - OPERAND_combined1b97e84f_fld130ae_slot0, - OPERAND_combined1b97e84f_fld137ae_slot0, - OPERAND_combined1b97e84f_fld135ae_slot0, - OPERAND_combined1b97e84f_fld136ae_slot0, - OPERAND_combined1b97e84f_fld129ae_slot0, - OPERAND_combined1b97e84f_fld127ae_slot0, - OPERAND_combined1b97e84f_fld128ae_slot0, - OPERAND_combined1b97e84f_fld132ae_slot0, - OPERAND_combined1b97e84f_fld134ae_slot0, - OPERAND_combined4b12daa6_fld122, - OPERAND_combined4b12daa6_fld115, - OPERAND_combined4b12daa6_fld85, - OPERAND_combined4b12daa6_fld119, - OPERAND_combined4b12daa6_fld97, - OPERAND_combined4b12daa6_fld124, - OPERAND_combined4b12daa6_fld79, - OPERAND_combined4b12daa6_fld80, - OPERAND_combined4b12daa6_fld108, - OPERAND_combined1b97e84f_fld54, - OPERAND_combined1b97e84f_fld17, - OPERAND_combined1b97e84f_fld76, - OPERAND_combined1b97e84f_fld73, - OPERAND_combined1b97e84f_fld62, - OPERAND_combined1b97e84f_fld24, - OPERAND_combined1b97e84f_fld70, - OPERAND_combined1b97e84f_fld58, - OPERAND_combined1b97e84f_fld131ae_slot1, - OPERAND_op0_s3_s3, - OPERAND_combined1b97e84f_fld49, - OPERAND_combined1b97e84f_fld51, - OPERAND_combined1b97e84f_fld23, - OPERAND_xt_fld0, - OPERAND_xt_fld1, - OPERAND_s3to1 -}; - - -/* Iclass table. */ - -static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { - { { STATE_PSEXCM }, 'o' }, - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfme_stateArgs[] = { - { { STATE_MESR }, 'o' }, - { { STATE_MEPC }, 'i' }, - { { STATE_MEPS }, 'i' }, - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { - { { OPERAND_ars_entry }, 's' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm12x8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { - { { STATE_WindowBase }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { - { { OPERAND_simm4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { - { { STATE_EPC1 }, 'i' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSOWB }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ai4const }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_simm7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8x256 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4const }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_bbi }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4constu }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_label12 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sae }, 'i' }, - { { OPERAND_op2p1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { - { { OPERAND_soffset }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_uimm16x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ulabel8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ulabel8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_simm12b }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { - { { OPERAND_arr }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimmrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { - { { OPERAND_sas }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_msalp32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sargt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { - { { STATE_LEND }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { - { { STATE_LEND }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { - { { STATE_LEND }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { - { { STATE_LCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { - { { STATE_SAR }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { - { { STATE_SAR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { - { { OPERAND_art }, 'm' } -}; - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { - { { OPERAND_art }, 'm' } -}; - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_243_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'm' }, - { { STATE_PSCALLINC }, 'm' }, - { { STATE_PSOWB }, 'm' }, - { { STATE_PSUM }, 'm' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'i' }, - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { - { { STATE_MISC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { - { { STATE_MISC0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { - { { STATE_MISC0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { - { { STATE_MISC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { - { { STATE_MISC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { - { { STATE_MISC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_mul16_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_mul32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPC1 }, 'i' }, - { { STATE_EPC2 }, 'i' }, - { { STATE_EPC3 }, 'i' }, - { { STATE_EPC4 }, 'i' }, - { { STATE_EPC5 }, 'i' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_EPC7 }, 'i' }, - { { STATE_EPS2 }, 'i' }, - { { STATE_EPS3 }, 'i' }, - { { STATE_EPS4 }, 'i' }, - { { STATE_EPS5 }, 'i' }, - { { STATE_EPS6 }, 'i' }, - { { STATE_EPS7 }, 'i' }, - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { - { { STATE_INTERRUPT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { - { { OPERAND_imms }, 'i' }, - { { OPERAND_immt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'i' }, - { { STATE_DBNUM }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'o' }, - { { STATE_DBNUM }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'm' }, - { { STATE_DBNUM }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { - { { STATE_ICOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { - { { STATE_DDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_InOCDMode }, 'i' }, - { { STATE_DDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { - { { STATE_InOCDMode }, 'i' }, - { { STATE_DDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { - { { STATE_InOCDMode }, 'm' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_bs }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_bs4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_bs8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { - { { OPERAND_bs }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { - { { OPERAND_arr }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_brall }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_brall }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_brall }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { - { { STATE_CCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'm' } -}; - - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mepc_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mepc_stateArgs[] = { - { { STATE_MEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mepc_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mepc_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MEPC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mepc_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mepc_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MEPC }, 'm' } -}; - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_meps_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_meps_stateArgs[] = { - { { STATE_MEPS }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_meps_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_meps_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MEPS }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_meps_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_meps_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MEPS }, 'm' } -}; - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mesave_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mesave_stateArgs[] = { - { { STATE_MESAVE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mesave_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mesave_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MESAVE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mesave_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mesave_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MESAVE }, 'm' } -}; - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mesr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mesr_stateArgs[] = { - { { STATE_MESR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mesr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mesr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MESR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mesr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mesr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MESR }, 'm' } -}; - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mecr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mecr_stateArgs[] = { - { { STATE_MECR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mecr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mecr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MECR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mecr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mecr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MECR }, 'm' } -}; - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mevaddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_mevaddr_stateArgs[] = { - { { STATE_MEVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mevaddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mevaddr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MEVADDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mevaddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_mevaddr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_MEVADDR }, 'm' } -}; - - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_stateArgs[] = { - { { STATE_PREFCTL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_stateArgs[] = { - { { STATE_PREFCTL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_stateArgs[] = { - { { STATE_PREFCTL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { - { { STATE_CPENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { - { { STATE_CPENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_tp7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_tp7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' }, - { { STATE_XTSYNC }, 'i' }, - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'i' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'o' }, - { { STATE_AE_SAR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = { - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = { - { { STATE_AE_BITHEAD }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_TABLESIZE }, 'i' }, - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = { - { { STATE_AE_BITPTR }, 'o' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_sd_no_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_sd_no_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_sd_no_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_sd_no_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_stateArgs[] = { - { { STATE_AE_SAR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_stateArgs[] = { - { { STATE_AE_BITPTR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_stateArgs[] = { - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_stateArgs[] = { - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_stateArgs[] = { - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_stateArgs[] = { - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_rur_threadptr_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_iclass_rur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'i' }, -}; - -static xtensa_arg_internal Iclass_iclass_wur_threadptr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_wur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'o' }, -}; - - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_i_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_x_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zerop48_args[] = { - { { OPERAND_ps }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zerop48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp48_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp48_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp16_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp16_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zeroq56_args[] = { - { { OPERAND_qr1_w }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zeroq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtq56_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bs }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfq56_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bs }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_cvt_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_cvt_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_satq48s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_satq48s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncq32_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncq32_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = { - { { OPERAND_alupppb_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = { - { { OPERAND_alupppb_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltp24s_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lep24s_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lep24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqp24_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bt }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bt }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_slliq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_slliq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srliq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srliq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraiq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraiq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltq56s_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_leq56s_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_leq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqq56_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sha32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl32t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl32t_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16t_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16c_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16c_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldsht_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldsht_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lb_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ae_ohba2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbk_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_ohba2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_db_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_db_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_dbi_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_ohba }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_dbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel32t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel32t_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel16t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel16t_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sb_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sb_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbi_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_ae_ohba }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vles16c_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vles16c_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbf_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbf_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_ADDBRBA32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cbegin0_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cbegin0_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cbegin0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cbegin0_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cend0_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cend0_stateArgs[] = { - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cend0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cend0_stateArgs[] = { - { { STATE_AE_CEND0 }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ56_C_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ56_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_READ_IPQ_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_interface Iclass_iclass_READ_IPQ_intfArgs[] = { - INTERFACE_IPQ -}; - -static xtensa_arg_internal Iclass_iclass_CHECK_IPQ_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_interface Iclass_iclass_CHECK_IPQ_intfArgs[] = { - INTERFACE_IPQ_NOTRDY -}; - -static xtensa_arg_internal Iclass_iclass_WRITE_OPQ_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_interface Iclass_iclass_WRITE_OPQ_intfArgs[] = { - INTERFACE_OPQ -}; - -static xtensa_arg_internal Iclass_iclass_CHECK_OPQ_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_interface Iclass_iclass_CHECK_OPQ_intfArgs[] = { - INTERFACE_OPQ_NOTRDY -}; - -static xtensa_arg_internal Iclass_rur_expstate_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { - { { STATE_EXPSTATE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_expstate_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { - { { STATE_EXPSTATE }, 'o' } -}; - -static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { - INTERFACE_IMPWIRE -}; - -static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { - { { OPERAND_bitindex }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' } -}; - -static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { - { { OPERAND_bitindex }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' } -}; - -static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' } -}; - -static xtensa_iclass_internal iclasses[] = { - { 0, 0 /* xt_iclass_excw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_rfe */, - 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfme */, - 9, Iclass_xt_iclass_rfme_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfde */, - 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_syscall */, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call12_args, - 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call8_args, - 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call4_args, - 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx12_args, - 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx8_args, - 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx4_args, - 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_entry_args, - 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movsp_args, - 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rotw_args, - 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_retw_args, - 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfwou */, - 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_l32e_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32e_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowbase_args, - 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowbase_args, - 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowbase_args, - 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowstart_args, - 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowstart_args, - 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowstart_args, - 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_add_n_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addi_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bz6_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill_n */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_loadi4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_mov_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_movi_n_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nopn */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_retn_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_storei4_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addmi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addsub_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bit_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8b_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8u_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bst8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bsz12_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_callx0_args, - 0, 0, 0, 0 }, - { 4, Iclass_xt_iclass_exti_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jump_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jumpx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16ui_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16si_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_l32r_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l8i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_loop_args, - 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_loopz_args, - 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_movz_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_neg_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nop */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_return_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_simcall */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s16i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32nb_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s8i_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_sar_args, - 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_sari_args, - 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shifts_args, - 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_shiftst_args, - 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shiftt_args, - 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_slli_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srli_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_memw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_extw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_isync */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_sync */, - 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rsil_args, - 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lend_args, - 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lend_args, - 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lend_args, - 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lcount_args, - 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lcount_args, - 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lcount_args, - 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lbeg_args, - 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lbeg_args, - 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lbeg_args, - 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_sar_args, - 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_sar_args, - 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_sar_args, - 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_acclo_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acclo_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acclo_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_acchi_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acchi_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acchi_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_memctl_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_memctl_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_memctl_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_mepc_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mepc_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_mepc_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_meps_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_meps_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_meps_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_mesave_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mesave_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_mesave_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_mesr_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mesr_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_mesr_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_mecr_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mecr_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_mecr_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_mevaddr_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mevaddr_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_mevaddr_args, - 0, 0, 0, 0 }, - - { 1, Iclass_xt_iclass_rsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_configid0_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_configid0_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_configid1_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_243_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ps_args, - 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ps_args, - 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ps_args, - 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc1_args, - 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc1_args, - 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc1_args, - 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave1_args, - 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave1_args, - 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave1_args, - 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc2_args, - 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc2_args, - 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc2_args, - 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave2_args, - 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave2_args, - 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave2_args, - 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc3_args, - 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc3_args, - 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc3_args, - 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave3_args, - 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave3_args, - 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave3_args, - 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc4_args, - 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc4_args, - 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc4_args, - 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave4_args, - 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave4_args, - 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave4_args, - 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc5_args, - 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc5_args, - 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc5_args, - 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave5_args, - 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave5_args, - 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave5_args, - 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc6_args, - 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc6_args, - 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc6_args, - 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave6_args, - 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave6_args, - 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave6_args, - 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc7_args, - 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc7_args, - 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc7_args, - 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave7_args, - 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave7_args, - 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave7_args, - 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps2_args, - 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps2_args, - 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps2_args, - 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps3_args, - 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps3_args, - 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps3_args, - 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps4_args, - 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps4_args, - 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps4_args, - 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps5_args, - 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps5_args, - 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps5_args, - 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps6_args, - 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps6_args, - 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps6_args, - 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps7_args, - 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps7_args, - 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps7_args, - 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excvaddr_args, - 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excvaddr_args, - 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excvaddr_args, - 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_depc_args, - 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_depc_args, - 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_depc_args, - 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_exccause_args, - 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_exccause_args, - 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_exccause_args, - 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc0_args, - 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc0_args, - 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc0_args, - 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc1_args, - 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc1_args, - 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc1_args, - 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_prid_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_vecbase_args, - 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_vecbase_args, - 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_vecbase_args, - 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, - { 3, Iclass_xt_mul16_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_mul32_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rfi_args, - 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wait_args, - 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_interrupt_args, - 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intset_args, - 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intclear_args, - 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_intenable_args, - 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intenable_args, - 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_intenable_args, - 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_break_args, - 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_break_n_args, - 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka0_args, - 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka0_args, - 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka0_args, - 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc0_args, - 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc0_args, - 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc0_args, - 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka1_args, - 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka1_args, - 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka1_args, - 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc1_args, - 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc1_args, - 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc1_args, - 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka0_args, - 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka0_args, - 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka0_args, - 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka1_args, - 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka1_args, - 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka1_args, - 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreakenable_args, - 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreakenable_args, - 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreakenable_args, - 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_debugcause_args, - 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_debugcause_args, - 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_debugcause_args, - 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icount_args, - 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icount_args, - 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icount_args, - 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icountlevel_args, - 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icountlevel_args, - 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icountlevel_args, - 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ddr_args, - 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ddr_args, - 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ddr_args, - 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_lddr32_p_args, - 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_sddr32_p_args, - 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfdo_args, - 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfdd */, - 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mmid_args, - 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_bbool1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbool4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbool8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbranch_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bmove_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_RSR_BR_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_WSR_BR_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_XSR_BR_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccount_args, - 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccount_args, - 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccount_args, - 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare0_args, - 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare0_args, - 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare0_args, - 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare1_args, - 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare1_args, - 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare1_args, - 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare2_args, - 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare2_args, - 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare2_args, - 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_icache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_icache_lock_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_icache_inv_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_licx_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_sicx_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_dcache_dyn_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_ind_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_inv_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dpf_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_lock_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_sdct_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_ldct_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_prefctl_args, - 1, Iclass_xt_iclass_rsr_prefctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_prefctl_args, - 1, Iclass_xt_iclass_wsr_prefctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_prefctl_args, - 1, Iclass_xt_iclass_xsr_prefctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_idtlb_args, - 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rdtlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wdtlb_args, - 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_iitlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_ritlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_witlb_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_cpenable_args, - 1, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_cpenable_args, - 1, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_cpenable_args, - 1, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_clamp_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_minmax_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_nsa_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_sx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32ai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32ri_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32c1i_args, - 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_scompare1_args, - 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_scompare1_args, - 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_scompare1_args, - 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_atomctl_args, - 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_atomctl_args, - 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_atomctl_args, - 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_div_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rer_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wer_args, - 0, 0, 0, 0 }, - { 1, Iclass_rur_ae_ovf_sar_args, - 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_ovf_sar_args, - 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_bithead_args, - 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_bithead_args, - 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_ts_fts_bu_bp_args, - 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_ts_fts_bu_bp_args, - 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_sd_no_args, - 3, Iclass_rur_ae_sd_no_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_sd_no_args, - 3, Iclass_wur_ae_sd_no_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_overflow_args, - 2, Iclass_ae_iclass_rur_ae_overflow_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_overflow_args, - 2, Iclass_ae_iclass_wur_ae_overflow_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_sar_args, - 2, Iclass_ae_iclass_rur_ae_sar_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_sar_args, - 2, Iclass_ae_iclass_wur_ae_sar_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_bitptr_args, - 2, Iclass_ae_iclass_rur_ae_bitptr_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_bitptr_args, - 2, Iclass_ae_iclass_wur_ae_bitptr_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_bitsused_args, - 2, Iclass_ae_iclass_rur_ae_bitsused_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_bitsused_args, - 2, Iclass_ae_iclass_wur_ae_bitsused_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_tablesize_args, - 2, Iclass_ae_iclass_rur_ae_tablesize_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_tablesize_args, - 2, Iclass_ae_iclass_wur_ae_tablesize_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_first_ts_args, - 2, Iclass_ae_iclass_rur_ae_first_ts_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_first_ts_args, - 2, Iclass_ae_iclass_wur_ae_first_ts_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_nextoffset_args, - 2, Iclass_ae_iclass_rur_ae_nextoffset_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_nextoffset_args, - 2, Iclass_ae_iclass_wur_ae_nextoffset_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_searchdone_args, - 2, Iclass_ae_iclass_rur_ae_searchdone_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_searchdone_args, - 2, Iclass_ae_iclass_wur_ae_searchdone_stateArgs, 0, 0 }, - - { 1, Iclass_iclass_rur_threadptr_args, - 2, Iclass_iclass_rur_threadptr_stateArgs, 0, 0 }, - { 1, Iclass_iclass_wur_threadptr_args, - 2, Iclass_iclass_wur_threadptr_stateArgs, 0, 0 }, - - { 3, Iclass_ae_iclass_lp16f_i_args, - 1, Iclass_ae_iclass_lp16f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_iu_args, - 1, Iclass_ae_iclass_lp16f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_x_args, - 1, Iclass_ae_iclass_lp16f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_xu_args, - 1, Iclass_ae_iclass_lp16f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_i_args, - 1, Iclass_ae_iclass_lp24_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_iu_args, - 1, Iclass_ae_iclass_lp24_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_x_args, - 1, Iclass_ae_iclass_lp24_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_xu_args, - 1, Iclass_ae_iclass_lp24_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_i_args, - 1, Iclass_ae_iclass_lp24f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_iu_args, - 1, Iclass_ae_iclass_lp24f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_x_args, - 1, Iclass_ae_iclass_lp24f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_xu_args, - 1, Iclass_ae_iclass_lp24f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_i_args, - 1, Iclass_ae_iclass_lp16x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_iu_args, - 1, Iclass_ae_iclass_lp16x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_x_args, - 1, Iclass_ae_iclass_lp16x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_xu_args, - 1, Iclass_ae_iclass_lp16x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_i_args, - 1, Iclass_ae_iclass_lp24x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_iu_args, - 1, Iclass_ae_iclass_lp24x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_x_args, - 1, Iclass_ae_iclass_lp24x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_xu_args, - 1, Iclass_ae_iclass_lp24x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_i_args, - 1, Iclass_ae_iclass_lp24x2_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_iu_args, - 1, Iclass_ae_iclass_lp24x2_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_x_args, - 1, Iclass_ae_iclass_lp24x2_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_xu_args, - 1, Iclass_ae_iclass_lp24x2_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_i_args, - 1, Iclass_ae_iclass_sp16x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_iu_args, - 1, Iclass_ae_iclass_sp16x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_x_args, - 1, Iclass_ae_iclass_sp16x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_xu_args, - 1, Iclass_ae_iclass_sp16x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_i_args, - 1, Iclass_ae_iclass_sp24x2s_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_iu_args, - 1, Iclass_ae_iclass_sp24x2s_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_x_args, - 1, Iclass_ae_iclass_sp24x2s_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_xu_args, - 1, Iclass_ae_iclass_sp24x2s_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_i_args, - 1, Iclass_ae_iclass_sp24x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_iu_args, - 1, Iclass_ae_iclass_sp24x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_x_args, - 1, Iclass_ae_iclass_sp24x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_xu_args, - 1, Iclass_ae_iclass_sp24x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_i_args, - 1, Iclass_ae_iclass_sp16f_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_iu_args, - 1, Iclass_ae_iclass_sp16f_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_x_args, - 1, Iclass_ae_iclass_sp16f_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_xu_args, - 1, Iclass_ae_iclass_sp16f_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_i_args, - 1, Iclass_ae_iclass_sp24s_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_iu_args, - 1, Iclass_ae_iclass_sp24s_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_x_args, - 1, Iclass_ae_iclass_sp24s_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_xu_args, - 1, Iclass_ae_iclass_sp24s_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_i_args, - 1, Iclass_ae_iclass_sp24f_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_iu_args, - 1, Iclass_ae_iclass_sp24f_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_x_args, - 1, Iclass_ae_iclass_sp24f_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_xu_args, - 1, Iclass_ae_iclass_sp24f_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_i_args, - 1, Iclass_ae_iclass_lq56_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_iu_args, - 1, Iclass_ae_iclass_lq56_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_x_args, - 1, Iclass_ae_iclass_lq56_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_xu_args, - 1, Iclass_ae_iclass_lq56_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_i_args, - 1, Iclass_ae_iclass_lq32f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_iu_args, - 1, Iclass_ae_iclass_lq32f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_x_args, - 1, Iclass_ae_iclass_lq32f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_xu_args, - 1, Iclass_ae_iclass_lq32f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_i_args, - 1, Iclass_ae_iclass_sq56s_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_iu_args, - 1, Iclass_ae_iclass_sq56s_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_x_args, - 1, Iclass_ae_iclass_sq56s_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_xu_args, - 1, Iclass_ae_iclass_sq56s_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_i_args, - 1, Iclass_ae_iclass_sq32f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_iu_args, - 1, Iclass_ae_iclass_sq32f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_x_args, - 1, Iclass_ae_iclass_sq32f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_xu_args, - 1, Iclass_ae_iclass_sq32f_xu_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_zerop48_args, - 1, Iclass_ae_iclass_zerop48_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movp48_args, - 1, Iclass_ae_iclass_movp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_ll_args, - 1, Iclass_ae_iclass_selp24_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_lh_args, - 1, Iclass_ae_iclass_selp24_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_hl_args, - 1, Iclass_ae_iclass_selp24_hl_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_hh_args, - 1, Iclass_ae_iclass_selp24_hh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movtp24x2_args, - 1, Iclass_ae_iclass_movtp24x2_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movfp24x2_args, - 1, Iclass_ae_iclass_movfp24x2_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movtp48_args, - 1, Iclass_ae_iclass_movtp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movfp48_args, - 1, Iclass_ae_iclass_movfp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movpa24x2_args, - 1, Iclass_ae_iclass_movpa24x2_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_truncp24a32x2_args, - 1, Iclass_ae_iclass_truncp24a32x2_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvta32p24_l_args, - 1, Iclass_ae_iclass_cvta32p24_l_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvta32p24_h_args, - 1, Iclass_ae_iclass_cvta32p24_h_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_ll_args, - 1, Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_lh_args, - 1, Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_hl_args, - 1, Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_hh_args, - 1, Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_truncp24q48x2_args, - 1, Iclass_ae_iclass_truncp24q48x2_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_truncp16_args, - 1, Iclass_ae_iclass_truncp16_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp24q48sym_args, - 2, Iclass_ae_iclass_roundsp24q48sym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp24q48asym_args, - 2, Iclass_ae_iclass_roundsp24q48asym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp16q48sym_args, - 2, Iclass_ae_iclass_roundsp16q48sym_stateArgs, 0, 0 }, - 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3, Iclass_icls_AE_LQ56_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SQ56S_C_args, - 3, Iclass_icls_AE_SQ56S_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LQ32F_C_args, - 3, Iclass_icls_AE_LQ32F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SQ32F_C_args, - 3, Iclass_icls_AE_SQ32F_C_stateArgs, 0, 0 }, - { 1, Iclass_iclass_READ_IPQ_args, - 0, 0, 1, Iclass_iclass_READ_IPQ_intfArgs }, - { 1, Iclass_iclass_CHECK_IPQ_args, - 0, 0, 1, Iclass_iclass_CHECK_IPQ_intfArgs }, - { 1, Iclass_iclass_WRITE_OPQ_args, - 0, 0, 1, Iclass_iclass_WRITE_OPQ_intfArgs }, - { 1, Iclass_iclass_CHECK_OPQ_args, - 0, 0, 1, Iclass_iclass_CHECK_OPQ_intfArgs }, - { 1, Iclass_rur_expstate_args, - 1, Iclass_rur_expstate_stateArgs, 0, 0 }, - { 1, Iclass_wur_expstate_args, - 1, Iclass_wur_expstate_stateArgs, 0, 0 }, - { 1, Iclass_iclass_READ_IMPWIRE_args, - 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, - { 1, Iclass_iclass_SETB_EXPSTATE_args, - 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, - { 1, Iclass_iclass_CLRB_EXPSTATE_args, - 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, - { 2, Iclass_iclass_WRMSK_EXPSTATE_args, - 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } -}; - -enum xtensa_iclass_id { - ICLASS_xt_iclass_excw, - ICLASS_xt_iclass_rfe, - ICLASS_xt_iclass_rfme, - ICLASS_xt_iclass_rfde, - ICLASS_xt_iclass_syscall, - ICLASS_xt_iclass_call12, - ICLASS_xt_iclass_call8, - ICLASS_xt_iclass_call4, - ICLASS_xt_iclass_callx12, - ICLASS_xt_iclass_callx8, - ICLASS_xt_iclass_callx4, - ICLASS_xt_iclass_entry, - ICLASS_xt_iclass_movsp, - ICLASS_xt_iclass_rotw, - ICLASS_xt_iclass_retw, - ICLASS_xt_iclass_rfwou, - ICLASS_xt_iclass_l32e, - ICLASS_xt_iclass_s32e, - ICLASS_xt_iclass_rsr_windowbase, - ICLASS_xt_iclass_wsr_windowbase, - ICLASS_xt_iclass_xsr_windowbase, - ICLASS_xt_iclass_rsr_windowstart, - ICLASS_xt_iclass_wsr_windowstart, - ICLASS_xt_iclass_xsr_windowstart, - ICLASS_xt_iclass_add_n, - ICLASS_xt_iclass_addi_n, - ICLASS_xt_iclass_bz6, - ICLASS_xt_iclass_ill_n, - ICLASS_xt_iclass_loadi4, - ICLASS_xt_iclass_mov_n, - ICLASS_xt_iclass_movi_n, - ICLASS_xt_iclass_nopn, - ICLASS_xt_iclass_retn, - ICLASS_xt_iclass_storei4, - ICLASS_xt_iclass_addi, - ICLASS_xt_iclass_addmi, - ICLASS_xt_iclass_addsub, - ICLASS_xt_iclass_bit, - ICLASS_xt_iclass_bsi8, - ICLASS_xt_iclass_bsi8b, - ICLASS_xt_iclass_bsi8u, - ICLASS_xt_iclass_bst8, - ICLASS_xt_iclass_bsz12, - ICLASS_xt_iclass_call0, - ICLASS_xt_iclass_callx0, - ICLASS_xt_iclass_exti, - ICLASS_xt_iclass_ill, - ICLASS_xt_iclass_jump, - ICLASS_xt_iclass_jumpx, - ICLASS_xt_iclass_l16ui, - ICLASS_xt_iclass_l16si, - ICLASS_xt_iclass_l32i, - ICLASS_xt_iclass_l32r, - ICLASS_xt_iclass_l8i, - ICLASS_xt_iclass_loop, - ICLASS_xt_iclass_loopz, - ICLASS_xt_iclass_movi, - ICLASS_xt_iclass_movz, - ICLASS_xt_iclass_neg, - ICLASS_xt_iclass_nop, - ICLASS_xt_iclass_return, - ICLASS_xt_iclass_simcall, - ICLASS_xt_iclass_s16i, - ICLASS_xt_iclass_s32i, - ICLASS_xt_iclass_s32nb, - ICLASS_xt_iclass_s8i, - ICLASS_xt_iclass_sar, - ICLASS_xt_iclass_sari, - ICLASS_xt_iclass_shifts, - ICLASS_xt_iclass_shiftst, - ICLASS_xt_iclass_shiftt, - ICLASS_xt_iclass_slli, - ICLASS_xt_iclass_srai, - ICLASS_xt_iclass_srli, - ICLASS_xt_iclass_memw, - ICLASS_xt_iclass_extw, - ICLASS_xt_iclass_isync, - ICLASS_xt_iclass_sync, - ICLASS_xt_iclass_rsil, - ICLASS_xt_iclass_rsr_lend, - ICLASS_xt_iclass_wsr_lend, - ICLASS_xt_iclass_xsr_lend, - ICLASS_xt_iclass_rsr_lcount, - ICLASS_xt_iclass_wsr_lcount, - ICLASS_xt_iclass_xsr_lcount, - ICLASS_xt_iclass_rsr_lbeg, - ICLASS_xt_iclass_wsr_lbeg, - ICLASS_xt_iclass_xsr_lbeg, - ICLASS_xt_iclass_rsr_sar, - ICLASS_xt_iclass_wsr_sar, - ICLASS_xt_iclass_xsr_sar, - - ICLASS_xt_iclass_rsr_acclo, - ICLASS_xt_iclass_wsr_acclo, - ICLASS_xt_iclass_xsr_acclo, - - ICLASS_xt_iclass_rsr_acchi, - ICLASS_xt_iclass_wsr_acchi, - ICLASS_xt_iclass_xsr_acchi, - - ICLASS_xt_iclass_rsr_memctl, - ICLASS_xt_iclass_wsr_memctl, - ICLASS_xt_iclass_xsr_memctl, - - ICLASS_xt_iclass_rsr_mepc, - ICLASS_xt_iclass_wsr_mepc, - ICLASS_xt_iclass_xsr_mepc, - ICLASS_xt_iclass_rsr_meps, - ICLASS_xt_iclass_wsr_meps, - ICLASS_xt_iclass_xsr_meps, - ICLASS_xt_iclass_rsr_mesave, - ICLASS_xt_iclass_wsr_mesave, - ICLASS_xt_iclass_xsr_mesave, - ICLASS_xt_iclass_rsr_mesr, - ICLASS_xt_iclass_wsr_mesr, - ICLASS_xt_iclass_xsr_mesr, - ICLASS_xt_iclass_rsr_mecr, - ICLASS_xt_iclass_wsr_mecr, - ICLASS_xt_iclass_xsr_mecr, - ICLASS_xt_iclass_rsr_mevaddr, - ICLASS_xt_iclass_wsr_mevaddr, - ICLASS_xt_iclass_xsr_mevaddr, - - ICLASS_xt_iclass_rsr_litbase, - ICLASS_xt_iclass_wsr_litbase, - ICLASS_xt_iclass_xsr_litbase, - ICLASS_xt_iclass_rsr_configid0, - ICLASS_xt_iclass_wsr_configid0, - ICLASS_xt_iclass_rsr_configid1, - ICLASS_xt_iclass_rsr_243, - ICLASS_xt_iclass_rsr_ps, - ICLASS_xt_iclass_wsr_ps, - ICLASS_xt_iclass_xsr_ps, - ICLASS_xt_iclass_rsr_epc1, - ICLASS_xt_iclass_wsr_epc1, - ICLASS_xt_iclass_xsr_epc1, - ICLASS_xt_iclass_rsr_excsave1, - ICLASS_xt_iclass_wsr_excsave1, - ICLASS_xt_iclass_xsr_excsave1, - ICLASS_xt_iclass_rsr_epc2, - ICLASS_xt_iclass_wsr_epc2, - ICLASS_xt_iclass_xsr_epc2, - ICLASS_xt_iclass_rsr_excsave2, - ICLASS_xt_iclass_wsr_excsave2, - ICLASS_xt_iclass_xsr_excsave2, - ICLASS_xt_iclass_rsr_epc3, - ICLASS_xt_iclass_wsr_epc3, - ICLASS_xt_iclass_xsr_epc3, - ICLASS_xt_iclass_rsr_excsave3, - ICLASS_xt_iclass_wsr_excsave3, - ICLASS_xt_iclass_xsr_excsave3, - ICLASS_xt_iclass_rsr_epc4, - ICLASS_xt_iclass_wsr_epc4, - ICLASS_xt_iclass_xsr_epc4, - ICLASS_xt_iclass_rsr_excsave4, - ICLASS_xt_iclass_wsr_excsave4, - ICLASS_xt_iclass_xsr_excsave4, - ICLASS_xt_iclass_rsr_epc5, - ICLASS_xt_iclass_wsr_epc5, - ICLASS_xt_iclass_xsr_epc5, - ICLASS_xt_iclass_rsr_excsave5, - ICLASS_xt_iclass_wsr_excsave5, - ICLASS_xt_iclass_xsr_excsave5, - ICLASS_xt_iclass_rsr_epc6, - ICLASS_xt_iclass_wsr_epc6, - ICLASS_xt_iclass_xsr_epc6, - ICLASS_xt_iclass_rsr_excsave6, - ICLASS_xt_iclass_wsr_excsave6, - ICLASS_xt_iclass_xsr_excsave6, - ICLASS_xt_iclass_rsr_epc7, - ICLASS_xt_iclass_wsr_epc7, - ICLASS_xt_iclass_xsr_epc7, - ICLASS_xt_iclass_rsr_excsave7, - ICLASS_xt_iclass_wsr_excsave7, - ICLASS_xt_iclass_xsr_excsave7, - ICLASS_xt_iclass_rsr_eps2, - ICLASS_xt_iclass_wsr_eps2, - ICLASS_xt_iclass_xsr_eps2, - ICLASS_xt_iclass_rsr_eps3, - ICLASS_xt_iclass_wsr_eps3, - ICLASS_xt_iclass_xsr_eps3, - ICLASS_xt_iclass_rsr_eps4, - ICLASS_xt_iclass_wsr_eps4, - ICLASS_xt_iclass_xsr_eps4, - ICLASS_xt_iclass_rsr_eps5, - ICLASS_xt_iclass_wsr_eps5, - ICLASS_xt_iclass_xsr_eps5, - ICLASS_xt_iclass_rsr_eps6, - ICLASS_xt_iclass_wsr_eps6, - ICLASS_xt_iclass_xsr_eps6, - ICLASS_xt_iclass_rsr_eps7, - ICLASS_xt_iclass_wsr_eps7, - ICLASS_xt_iclass_xsr_eps7, - ICLASS_xt_iclass_rsr_excvaddr, - ICLASS_xt_iclass_wsr_excvaddr, - ICLASS_xt_iclass_xsr_excvaddr, - ICLASS_xt_iclass_rsr_depc, - ICLASS_xt_iclass_wsr_depc, - ICLASS_xt_iclass_xsr_depc, - ICLASS_xt_iclass_rsr_exccause, - ICLASS_xt_iclass_wsr_exccause, - ICLASS_xt_iclass_xsr_exccause, - ICLASS_xt_iclass_rsr_misc0, - ICLASS_xt_iclass_wsr_misc0, - ICLASS_xt_iclass_xsr_misc0, - ICLASS_xt_iclass_rsr_misc1, - ICLASS_xt_iclass_wsr_misc1, - ICLASS_xt_iclass_xsr_misc1, - ICLASS_xt_iclass_rsr_prid, - ICLASS_xt_iclass_rsr_vecbase, - ICLASS_xt_iclass_wsr_vecbase, - ICLASS_xt_iclass_xsr_vecbase, - ICLASS_xt_mul16, - ICLASS_xt_mul32, - ICLASS_xt_iclass_rfi, - ICLASS_xt_iclass_wait, - ICLASS_xt_iclass_rsr_interrupt, - ICLASS_xt_iclass_wsr_intset, - ICLASS_xt_iclass_wsr_intclear, - ICLASS_xt_iclass_rsr_intenable, - ICLASS_xt_iclass_wsr_intenable, - ICLASS_xt_iclass_xsr_intenable, - ICLASS_xt_iclass_break, - ICLASS_xt_iclass_break_n, - ICLASS_xt_iclass_rsr_dbreaka0, - ICLASS_xt_iclass_wsr_dbreaka0, - ICLASS_xt_iclass_xsr_dbreaka0, - ICLASS_xt_iclass_rsr_dbreakc0, - ICLASS_xt_iclass_wsr_dbreakc0, - ICLASS_xt_iclass_xsr_dbreakc0, - ICLASS_xt_iclass_rsr_dbreaka1, - ICLASS_xt_iclass_wsr_dbreaka1, - ICLASS_xt_iclass_xsr_dbreaka1, - ICLASS_xt_iclass_rsr_dbreakc1, - ICLASS_xt_iclass_wsr_dbreakc1, - ICLASS_xt_iclass_xsr_dbreakc1, - ICLASS_xt_iclass_rsr_ibreaka0, - ICLASS_xt_iclass_wsr_ibreaka0, - ICLASS_xt_iclass_xsr_ibreaka0, - ICLASS_xt_iclass_rsr_ibreaka1, - ICLASS_xt_iclass_wsr_ibreaka1, - ICLASS_xt_iclass_xsr_ibreaka1, - ICLASS_xt_iclass_rsr_ibreakenable, - ICLASS_xt_iclass_wsr_ibreakenable, - ICLASS_xt_iclass_xsr_ibreakenable, - ICLASS_xt_iclass_rsr_debugcause, - ICLASS_xt_iclass_wsr_debugcause, - ICLASS_xt_iclass_xsr_debugcause, - ICLASS_xt_iclass_rsr_icount, - ICLASS_xt_iclass_wsr_icount, - ICLASS_xt_iclass_xsr_icount, - ICLASS_xt_iclass_rsr_icountlevel, - ICLASS_xt_iclass_wsr_icountlevel, - ICLASS_xt_iclass_xsr_icountlevel, - ICLASS_xt_iclass_rsr_ddr, - ICLASS_xt_iclass_wsr_ddr, - ICLASS_xt_iclass_xsr_ddr, - ICLASS_xt_iclass_lddr32_p, - ICLASS_xt_iclass_sddr32_p, - ICLASS_xt_iclass_rfdo, - ICLASS_xt_iclass_rfdd, - ICLASS_xt_iclass_wsr_mmid, - ICLASS_xt_iclass_bbool1, - ICLASS_xt_iclass_bbool4, - ICLASS_xt_iclass_bbool8, - ICLASS_xt_iclass_bbranch, - ICLASS_xt_iclass_bmove, - ICLASS_xt_iclass_RSR_BR, - ICLASS_xt_iclass_WSR_BR, - ICLASS_xt_iclass_XSR_BR, - ICLASS_xt_iclass_rsr_ccount, - ICLASS_xt_iclass_wsr_ccount, - ICLASS_xt_iclass_xsr_ccount, - ICLASS_xt_iclass_rsr_ccompare0, - ICLASS_xt_iclass_wsr_ccompare0, - ICLASS_xt_iclass_xsr_ccompare0, - ICLASS_xt_iclass_rsr_ccompare1, - ICLASS_xt_iclass_wsr_ccompare1, - ICLASS_xt_iclass_xsr_ccompare1, - ICLASS_xt_iclass_rsr_ccompare2, - ICLASS_xt_iclass_wsr_ccompare2, - ICLASS_xt_iclass_xsr_ccompare2, - ICLASS_xt_iclass_icache, - ICLASS_xt_iclass_icache_lock, - ICLASS_xt_iclass_icache_inv, - ICLASS_xt_iclass_licx, - ICLASS_xt_iclass_sicx, - ICLASS_xt_iclass_dcache, - ICLASS_xt_iclass_dcache_dyn, - ICLASS_xt_iclass_dcache_ind, - ICLASS_xt_iclass_dcache_inv, - ICLASS_xt_iclass_dpf, - ICLASS_xt_iclass_dcache_lock, - ICLASS_xt_iclass_sdct, - ICLASS_xt_iclass_ldct, - ICLASS_xt_iclass_rsr_prefctl, - ICLASS_xt_iclass_wsr_prefctl, - ICLASS_xt_iclass_xsr_prefctl, - ICLASS_xt_iclass_idtlb, - ICLASS_xt_iclass_rdtlb, - ICLASS_xt_iclass_wdtlb, - ICLASS_xt_iclass_iitlb, - ICLASS_xt_iclass_ritlb, - ICLASS_xt_iclass_witlb, - ICLASS_xt_iclass_rsr_cpenable, - ICLASS_xt_iclass_wsr_cpenable, - ICLASS_xt_iclass_xsr_cpenable, - ICLASS_xt_iclass_clamp, - ICLASS_xt_iclass_minmax, - ICLASS_xt_iclass_nsa, - ICLASS_xt_iclass_sx, - ICLASS_xt_iclass_l32ai, - ICLASS_xt_iclass_s32ri, - ICLASS_xt_iclass_s32c1i, - ICLASS_xt_iclass_rsr_scompare1, - ICLASS_xt_iclass_wsr_scompare1, - ICLASS_xt_iclass_xsr_scompare1, - ICLASS_xt_iclass_rsr_atomctl, - ICLASS_xt_iclass_wsr_atomctl, - ICLASS_xt_iclass_xsr_atomctl, - ICLASS_xt_iclass_div, - ICLASS_xt_iclass_rer, - ICLASS_xt_iclass_wer, - ICLASS_rur_ae_ovf_sar, - ICLASS_wur_ae_ovf_sar, - ICLASS_rur_ae_bithead, - ICLASS_wur_ae_bithead, - ICLASS_rur_ae_ts_fts_bu_bp, - ICLASS_wur_ae_ts_fts_bu_bp, - ICLASS_rur_ae_sd_no, - ICLASS_wur_ae_sd_no, - ICLASS_ae_iclass_rur_ae_overflow, - ICLASS_ae_iclass_wur_ae_overflow, - ICLASS_ae_iclass_rur_ae_sar, - ICLASS_ae_iclass_wur_ae_sar, - ICLASS_ae_iclass_rur_ae_bitptr, - ICLASS_ae_iclass_wur_ae_bitptr, - ICLASS_ae_iclass_rur_ae_bitsused, - ICLASS_ae_iclass_wur_ae_bitsused, - ICLASS_ae_iclass_rur_ae_tablesize, - ICLASS_ae_iclass_wur_ae_tablesize, - ICLASS_ae_iclass_rur_ae_first_ts, - ICLASS_ae_iclass_wur_ae_first_ts, - ICLASS_ae_iclass_rur_ae_nextoffset, - ICLASS_ae_iclass_wur_ae_nextoffset, - ICLASS_ae_iclass_rur_ae_searchdone, - ICLASS_ae_iclass_wur_ae_searchdone, - ICLASS_iclass_rur_threadptr, - ICLASS_iclass_wur_threadptr, - ICLASS_ae_iclass_lp16f_i, - ICLASS_ae_iclass_lp16f_iu, - ICLASS_ae_iclass_lp16f_x, - ICLASS_ae_iclass_lp16f_xu, - ICLASS_ae_iclass_lp24_i, - ICLASS_ae_iclass_lp24_iu, - ICLASS_ae_iclass_lp24_x, - ICLASS_ae_iclass_lp24_xu, - ICLASS_ae_iclass_lp24f_i, - ICLASS_ae_iclass_lp24f_iu, - ICLASS_ae_iclass_lp24f_x, - ICLASS_ae_iclass_lp24f_xu, - ICLASS_ae_iclass_lp16x2f_i, - ICLASS_ae_iclass_lp16x2f_iu, - ICLASS_ae_iclass_lp16x2f_x, - ICLASS_ae_iclass_lp16x2f_xu, - ICLASS_ae_iclass_lp24x2f_i, - ICLASS_ae_iclass_lp24x2f_iu, - ICLASS_ae_iclass_lp24x2f_x, - ICLASS_ae_iclass_lp24x2f_xu, - ICLASS_ae_iclass_lp24x2_i, - ICLASS_ae_iclass_lp24x2_iu, - ICLASS_ae_iclass_lp24x2_x, - ICLASS_ae_iclass_lp24x2_xu, - ICLASS_ae_iclass_sp16x2f_i, - ICLASS_ae_iclass_sp16x2f_iu, - ICLASS_ae_iclass_sp16x2f_x, - ICLASS_ae_iclass_sp16x2f_xu, - ICLASS_ae_iclass_sp24x2s_i, - ICLASS_ae_iclass_sp24x2s_iu, - ICLASS_ae_iclass_sp24x2s_x, - ICLASS_ae_iclass_sp24x2s_xu, - ICLASS_ae_iclass_sp24x2f_i, - ICLASS_ae_iclass_sp24x2f_iu, - ICLASS_ae_iclass_sp24x2f_x, - ICLASS_ae_iclass_sp24x2f_xu, - ICLASS_ae_iclass_sp16f_l_i, - ICLASS_ae_iclass_sp16f_l_iu, - ICLASS_ae_iclass_sp16f_l_x, - ICLASS_ae_iclass_sp16f_l_xu, - ICLASS_ae_iclass_sp24s_l_i, - ICLASS_ae_iclass_sp24s_l_iu, - ICLASS_ae_iclass_sp24s_l_x, - ICLASS_ae_iclass_sp24s_l_xu, - ICLASS_ae_iclass_sp24f_l_i, - ICLASS_ae_iclass_sp24f_l_iu, - ICLASS_ae_iclass_sp24f_l_x, - ICLASS_ae_iclass_sp24f_l_xu, - ICLASS_ae_iclass_lq56_i, - ICLASS_ae_iclass_lq56_iu, - ICLASS_ae_iclass_lq56_x, - ICLASS_ae_iclass_lq56_xu, - ICLASS_ae_iclass_lq32f_i, - ICLASS_ae_iclass_lq32f_iu, - ICLASS_ae_iclass_lq32f_x, - ICLASS_ae_iclass_lq32f_xu, - ICLASS_ae_iclass_sq56s_i, - ICLASS_ae_iclass_sq56s_iu, - ICLASS_ae_iclass_sq56s_x, - ICLASS_ae_iclass_sq56s_xu, - ICLASS_ae_iclass_sq32f_i, - ICLASS_ae_iclass_sq32f_iu, - ICLASS_ae_iclass_sq32f_x, - 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ICLASS_ae_iclass_mulzasp24s_hl_lh, - ICLASS_ae_iclass_mulzsafp24s_hh_ll, - ICLASS_ae_iclass_mulzsap24s_hh_ll, - ICLASS_ae_iclass_mulzsafp24s_hl_lh, - ICLASS_ae_iclass_mulzsap24s_hl_lh, - ICLASS_ae_iclass_mulzssfp24s_hh_ll, - ICLASS_ae_iclass_mulzssp24s_hh_ll, - ICLASS_ae_iclass_mulzssfp24s_hl_lh, - ICLASS_ae_iclass_mulzssp24s_hl_lh, - ICLASS_ae_iclass_mulaafp24s_hh_ll, - ICLASS_ae_iclass_mulaap24s_hh_ll, - ICLASS_ae_iclass_mulaafp24s_hl_lh, - ICLASS_ae_iclass_mulaap24s_hl_lh, - ICLASS_ae_iclass_mulasfp24s_hh_ll, - ICLASS_ae_iclass_mulasp24s_hh_ll, - ICLASS_ae_iclass_mulasfp24s_hl_lh, - ICLASS_ae_iclass_mulasp24s_hl_lh, - ICLASS_ae_iclass_mulsafp24s_hh_ll, - ICLASS_ae_iclass_mulsap24s_hh_ll, - ICLASS_ae_iclass_mulsafp24s_hl_lh, - ICLASS_ae_iclass_mulsap24s_hl_lh, - ICLASS_ae_iclass_mulssfp24s_hh_ll, - ICLASS_ae_iclass_mulssp24s_hh_ll, - ICLASS_ae_iclass_mulssfp24s_hl_lh, - ICLASS_ae_iclass_mulssp24s_hl_lh, - ICLASS_ae_iclass_sha32, - ICLASS_ae_iclass_vldl32t, - ICLASS_ae_iclass_vldl16t, - ICLASS_ae_iclass_vldl16c, - ICLASS_ae_iclass_vldsht, - ICLASS_ae_iclass_lb, - ICLASS_ae_iclass_lbi, - ICLASS_ae_iclass_lbk, - ICLASS_ae_iclass_lbki, - ICLASS_ae_iclass_db, - ICLASS_ae_iclass_dbi, - ICLASS_ae_iclass_vlel32t, - ICLASS_ae_iclass_vlel16t, - ICLASS_ae_iclass_sb, - ICLASS_ae_iclass_sbi, - ICLASS_ae_iclass_vles16c, - ICLASS_ae_iclass_sbf, - ICLASS_icls_AE_SLAASQ56S, - ICLASS_icls_AE_ADDBRBA32, - ICLASS_icls_AE_MINABSSP24S, - ICLASS_icls_AE_MAXABSSP24S, - ICLASS_icls_AE_MINABSSQ56S, - ICLASS_icls_AE_MAXABSSQ56S, - ICLASS_rur_ae_cbegin0, - ICLASS_wur_ae_cbegin0, - ICLASS_rur_ae_cend0, - ICLASS_wur_ae_cend0, - ICLASS_icls_AE_LP24X2_C, - ICLASS_icls_AE_SP24X2S_C, - ICLASS_icls_AE_LP24X2F_C, - ICLASS_icls_AE_SP24X2F_C, - ICLASS_icls_AE_LP16X2F_C, - ICLASS_icls_AE_SP16X2F_C, - ICLASS_icls_AE_LP24_C, - ICLASS_icls_AE_SP24S_L_C, - ICLASS_icls_AE_LP24F_C, - ICLASS_icls_AE_SP24F_L_C, - ICLASS_icls_AE_LP16F_C, - ICLASS_icls_AE_SP16F_L_C, - ICLASS_icls_AE_LQ56_C, - ICLASS_icls_AE_SQ56S_C, - ICLASS_icls_AE_LQ32F_C, - ICLASS_icls_AE_SQ32F_C, - ICLASS_iclass_READ_IPQ, - ICLASS_iclass_CHECK_IPQ, - ICLASS_iclass_WRITE_OPQ, - ICLASS_iclass_CHECK_OPQ, - ICLASS_rur_expstate, - ICLASS_wur_expstate, - ICLASS_iclass_READ_IMPWIRE, - ICLASS_iclass_SETB_EXPSTATE, - ICLASS_iclass_CLRB_EXPSTATE, - ICLASS_iclass_WRMSK_EXPSTATE -}; - - -/* Opcode encodings. */ - -static void -Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2080; -} - -static void -Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000; -} - -static void -Opcode_rfme_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3020; -} - -static void -Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3200; -} - -static void -Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5000; -} - -static void -Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35; -} - -static void -Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x25; -} - -static void -Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15; -} - -static void -Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf0; -} - -static void -Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0; -} - -static void -Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd0; -} - -static void -Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36; -} - -static void -Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1000; -} - -static void -Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x408000; -} - -static void -Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90; -} - -static void -Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf01d; -} - -static void -Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3400; -} - -static void -Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3500; -} - -static void -Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90000; -} - -static void -Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x490000; -} - -static void -Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34800; -} - -static void -Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134800; -} - -static void -Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614800; -} - -static void -Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34900; -} - -static void -Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134900; -} - -static void -Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614900; -} - -static void -Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa; -} - -static void -Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb; -} - -static void -Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8c; -} - -static void -Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcc; -} - -static void -Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf06d; -} - -static void -Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8; -} - -static void -Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd; -} - -static void -Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc; -} - -static void -Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf03d; -} - -static void -Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00d; -} - -static void -Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9; -} - -static void -Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc002; -} - -static void -Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200040; -} - -static void -Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd002; -} - -static void -Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200080; -} - -static void -Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800000; -} - -static void -Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b2000; -} - -static void -Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc00000; -} - -static void -Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ca000; -} - -static void -Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900000; -} - -static void -Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b4000; -} - -static void -Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00000; -} - -static void -Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b8000; -} - -static void -Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb00000; -} - -static void -Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b3000; -} - -static void -Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd00000; -} - -static void -Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cc000; -} - -static void -Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00000; -} - -static void -Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cb000; -} - -static void -Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00000; -} - -static void -Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cd000; -} - -static void -Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b5000; -} - -static void -Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e0000; -} - -static void -Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300000; -} - -static void -Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ce000; -} - -static void -Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x26; -} - -static void -Opcode_beqi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300000; -} - -static void -Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x66; -} - -static void -Opcode_bnei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300003; -} - -static void -Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe6; -} - -static void -Opcode_bgei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300001; -} - -static void -Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa6; -} - -static void -Opcode_blti_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300004; -} - -static void -Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6007; -} - -static void -Opcode_bbci_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe007; -} - -static void -Opcode_bbsi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200020; -} - -static void -Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf6; -} - -static void -Opcode_bgeui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300002; -} - -static void -Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb6; -} - -static void -Opcode_bltui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300008; -} - -static void -Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1007; -} - -static void -Opcode_beq_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000a0; -} - -static void -Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9007; -} - -static void -Opcode_bne_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400000; -} - -static void -Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa007; -} - -static void -Opcode_bge_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000c0; -} - -static void -Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2007; -} - -static void -Opcode_blt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000d0; -} - -static void -Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb007; -} - -static void -Opcode_bgeu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000b0; -} - -static void -Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3007; -} - -static void -Opcode_bltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000e0; -} - -static void -Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8007; -} - -static void -Opcode_bany_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200060; -} - -static void -Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7; -} - -static void -Opcode_bnone_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400010; -} - -static void -Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4007; -} - -static void -Opcode_ball_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200050; -} - -static void -Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc007; -} - -static void -Opcode_bnall_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000f0; -} - -static void -Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5007; -} - -static void -Opcode_bbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200070; -} - -static void -Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd007; -} - -static void -Opcode_bbs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200090; -} - -static void -Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16; -} - -static void -Opcode_beqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180000; -} - -static void -Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x56; -} - -static void -Opcode_bnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x190000; -} - -static void -Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd6; -} - -static void -Opcode_bgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x160000; -} - -static void -Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x96; -} - -static void -Opcode_bltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x170000; -} - -static void -Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5; -} - -static void -Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc0; -} - -static void -Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000; -} - -static void -Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x140000; -} - -static void -Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0; -} - -static void -Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6; -} - -static void -Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0; -} - -static void -Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee031; -} - -static void -Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1002; -} - -static void -Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400040; -} - -static void -Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9002; -} - -static void -Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400020; -} - -static void -Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2002; -} - -static void -Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400080; -} - -static void -Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1; -} - -static void -Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500000; -} - -static void -Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2; -} - -static void -Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400030; -} - -static void -Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8076; -} - -static void -Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9076; -} - -static void -Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa076; -} - -static void -Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa002; -} - -static void -Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a0000; -} - -static void -Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x830000; -} - -static void -Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1be000; -} - -static void -Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x930000; -} - -static void -Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c8000; -} - -static void -Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa30000; -} - -static void -Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c4000; -} - -static void -Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb30000; -} - -static void -Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c2000; -} - -static void -Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600000; -} - -static void -Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1d00; -} - -static void -Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600100; -} - -static void -Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1c00; -} - -static void -Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20f0; -} - -static void -Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16105; -} - -static void -Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee0b1; -} - -static void -Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80; -} - -static void -Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5100; -} - -static void -Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5002; -} - -static void -Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400050; -} - -static void -Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6002; -} - -static void -Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400060; -} - -static void -Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x590000; -} - -static void -Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4002; -} - -static void -Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400070; -} - -static void -Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400000; -} - -static void -Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee071; -} - -static void -Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x401000; -} - -static void -Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee038; -} - -static void -Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x402000; -} - -static void -Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee034; -} - -static void -Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x403000; -} - -static void -Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee032; -} - -static void -Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x404000; -} - -static void -Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef0a0; -} - -static void -Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa10000; -} - -static void -Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5003; -} - -static void -Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x810000; -} - -static void -Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c7000; -} - -static void -Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x910000; -} - -static void -Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1f00; -} - -static void -Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb10000; -} - -static void -Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1e00; -} - -static void -Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10000; -} - -static void -Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c0000; -} - -static void -Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x210000; -} - -static void -Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b0000; -} - -static void -Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x410000; -} - -static void -Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c9000; -} - -static void -Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20c0; -} - -static void -Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20d0; -} - -static void -Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000; -} - -static void -Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2010; -} - -static void -Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2020; -} - -static void -Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2030; -} - -static void -Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000; -} - -static void -Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30100; -} - -static void -Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130100; -} - -static void -Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610100; -} - -static void -Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30200; -} - -static void -Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130200; -} - -static void -Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610200; -} - -static void -Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000; -} - -static void -Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130000; -} - -static void -Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610000; -} - -static void -Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30300; -} - -static void -Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130300; -} - -static void -Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610300; -} - -static void -Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31000; -} - -static void -Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131000; -} - -static void -Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x611000; -} - -static void -Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31100; -} - -static void -Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131100; -} - -static void -Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x611100; -} - -static void -Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36100; -} - -static void -Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136100; -} - -static void -Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616100; -} - -static void -Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30500; -} - -static void -Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130500; -} - -static void -Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610500; -} - -static void -Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b000; -} - -static void -Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b000; -} - -static void -Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d000; -} - -static void -Opcode_rsr_243_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f300; -} - -static void -Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e600; -} - -static void -Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e600; -} - -static void -Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e600; -} - -static void -Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b100; -} - -static void -Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b100; -} - -static void -Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b100; -} - -static void -Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d100; -} - -static void -Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d100; -} - -static void -Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d100; -} - -static void -Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b200; -} - -static void -Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b200; -} - -static void -Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b200; -} - -static void -Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d200; -} - -static void -Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d200; -} - -static void -Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d200; -} - -static void -Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b300; -} - -static void -Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b300; -} - -static void -Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b300; -} - -static void -Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d300; -} - -static void -Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d300; -} - -static void -Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d300; -} - -static void -Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b400; -} - -static void -Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b400; -} - -static void -Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b400; -} - -static void -Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d400; -} - -static void -Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d400; -} - -static void -Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d400; -} - -static void -Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b500; -} - -static void -Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b500; -} - -static void -Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b500; -} - -static void -Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d500; -} - -static void -Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d500; -} - -static void -Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d500; -} - -static void -Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b600; -} - -static void -Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b600; -} - -static void -Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b600; -} - -static void -Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d600; -} - -static void -Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d600; -} - -static void -Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d600; -} - -static void -Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b700; -} - -static void -Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b700; -} - -static void -Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b700; -} - -static void -Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d700; -} - -static void -Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d700; -} - -static void -Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d700; -} - -static void -Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c200; -} - -static void -Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c200; -} - -static void -Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c200; -} - -static void -Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c300; -} - -static void -Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c300; -} - -static void -Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c300; -} - -static void -Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c400; -} - -static void -Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c400; -} - -static void -Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c400; -} - -static void -Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c500; -} - -static void -Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c500; -} - -static void -Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c500; -} - -static void -Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c600; -} - -static void -Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c600; -} - -static void -Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c600; -} - -static void -Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c700; -} - -static void -Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c700; -} - -static void -Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c700; -} - -static void -Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ee00; -} - -static void -Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ee00; -} - -static void -Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ee00; -} - -static void -Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c000; -} - -static void -Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c000; -} - -static void -Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c000; -} - -static void -Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e800; -} - -static void -Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e800; -} - -static void -Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e800; -} - -static void -Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f400; -} - -static void -Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f400; -} - -static void -Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f400; -} - -static void -Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f500; -} - -static void -Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f500; -} - -static void -Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f500; -} - -static void -Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3eb00; -} - -static void -Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e700; -} - -static void -Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e700; -} - -static void -Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e700; -} - -static void -Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc10000; -} - -static void -Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd10000; -} - -static void -Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x820000; -} - -static void -Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3010; -} - -static void -Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7000; -} - -static void -Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e200; -} - -static void -Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e200; -} - -static void -Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e300; -} - -static void -Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e400; -} - -static void -Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e400; -} - -static void -Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e400; -} - -static void -Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000; -} - -static void -Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf02d; -} - -static void -Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39000; -} - -static void -Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139000; -} - -static void -Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619000; -} - -static void -Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a000; -} - -static void -Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a000; -} - -static void -Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a000; -} - -static void -Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39100; -} - -static void -Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139100; -} - -static void -Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619100; -} - -static void -Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a100; -} - -static void -Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a100; -} - -static void -Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a100; -} - -static void -Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38000; -} - -static void -Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138000; -} - -static void -Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618000; -} - -static void -Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38100; -} - -static void -Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138100; -} - -static void -Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618100; -} - -static void -Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36000; -} - -static void -Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136000; -} - -static void -Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616000; -} - -static void -Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e900; -} - -static void -Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e900; -} - -static void -Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e900; -} - -static void -Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ec00; -} - -static void -Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ec00; -} - -static void -Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ec00; -} - -static void -Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ed00; -} - -static void -Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ed00; -} - -static void -Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ed00; -} - -static void -Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36800; -} - -static void -Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136800; -} - -static void -Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616800; -} - -static void -Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70e0; -} - -static void -Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70f0; -} - -static void -Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e000; -} - -static void -Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e010; -} - -static void -Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135900; -} - -static void -Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20000; -} - -static void -Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b6000; -} - -static void -Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x120000; -} - -static void -Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b7000; -} - -static void -Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x220000; -} - -static void -Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c3000; -} - -static void -Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x320000; -} - -static void -Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c5000; -} - -static void -Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x420000; -} - -static void -Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cf000; -} - -static void -Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8000; -} - -static void -Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2480; -} - -static void -Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9000; -} - -static void -Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2800; -} - -static void -Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa000; -} - -static void -Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef060; -} - -static void -Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb000; -} - -static void -Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef020; -} - -static void -Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x76; -} - -static void -Opcode_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300005; -} - -static void -Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1076; -} - -static void -Opcode_bt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300006; -} - -static void -Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc30000; -} - -static void -Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bf000; -} - -static void -Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd30000; -} - -static void -Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d0000; -} - -static void -Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30400; -} - -static void -Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130400; -} - -static void -Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610400; -} - -static void -Opcode_rsr_mevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36f00; -} - -static void -Opcode_wsr_mevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136f00; -} - -static void -Opcode_xsr_mevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616f00; -} - -static void -Opcode_rsr_mecr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36e00; -} - -static void -Opcode_wsr_mecr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136e00; -} - -static void -Opcode_xsr_mecr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616e00; -} - -static void -Opcode_rsr_mesr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36d00; -} - -static void -Opcode_wsr_mesr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136d00; -} - -static void -Opcode_xsr_mesr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616d00; -} - -static void -Opcode_rsr_mesave_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36c00; -} - -static void -Opcode_wsr_mesave_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136c00; -} - -static void -Opcode_xsr_mesave_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616c00; -} - -static void -Opcode_rsr_meps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36b00; -} - -static void -Opcode_wsr_meps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136b00; -} - -static void -Opcode_xsr_meps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616b00; -} - -static void -Opcode_rsr_mepc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36a00; -} - -static void -Opcode_wsr_mepc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136a00; -} - -static void -Opcode_xsr_mepc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616a00; -} - -static void -Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ea00; -} - -static void -Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ea00; -} - -static void -Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ea00; -} - -static void -Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f000; -} - -static void -Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f000; -} - -static void -Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f000; -} - -static void -Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f100; -} - -static void -Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f100; -} - -static void -Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f100; -} - -static void -Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f200; -} - -static void -Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f200; -} - -static void -Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f200; -} - -static void -Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70c2; -} - -static void -Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70e2; -} - -static void -Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70d2; -} - -static void -Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x270d2; -} - -static void -Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x370d2; -} - -static void -Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70f2; -} - -static void -Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf10000; -} - -static void -Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf12000; -} - -static void -Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf11000; -} - -static void -Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf13000; -} - -static void -Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7042; -} - -static void -Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7052; -} - -static void -Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf7082; -} - -static void -Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x47082; -} - -static void -Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x57082; -} - -static void -Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7062; -} - -static void -Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7072; -} - -static void -Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7002; -} - -static void -Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7012; -} - -static void -Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7022; -} - -static void -Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7032; -} - -static void -Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7082; -} - -static void -Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x27082; -} - -static void -Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x37082; -} - -static void -Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf19000; -} - -static void -Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf18000; -} - -static void -Opcode_rsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32800; -} - -static void -Opcode_wsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132800; -} - -static void -Opcode_xsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612800; -} - -static void -Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50c000; -} - -static void -Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50d000; -} - -static void -Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50b000; -} - -static void -Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50f000; -} - -static void -Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50e000; -} - -static void -Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x504000; -} - -static void -Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x505000; -} - -static void -Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x503000; -} - -static void -Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x507000; -} - -static void -Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x506000; -} - -static void -Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e000; -} - -static void -Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e000; -} - -static void -Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e000; -} - -static void -Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x330000; -} - -static void -Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b9000; -} - -static void -Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x430000; -} - -static void -Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bb000; -} - -static void -Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x530000; -} - -static void -Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ba000; -} - -static void -Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x630000; -} - -static void -Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bd000; -} - -static void -Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x730000; -} - -static void -Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bc000; -} - -static void -Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40e000; -} - -static void -Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40f000; -} - -static void -Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x230000; -} - -static void -Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c6000; -} - -static void -Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb002; -} - -static void -Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf002; -} - -static void -Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe002; -} - -static void -Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30c00; -} - -static void -Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130c00; -} - -static void -Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610c00; -} - -static void -Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36300; -} - -static void -Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136300; -} - -static void -Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616300; -} - -static void -Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc20000; -} - -static void -Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd20000; -} - -static void -Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe20000; -} - -static void -Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf20000; -} - -static void -Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x406000; -} - -static void -Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x407000; -} - -static void -Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f00; -} - -static void -Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f000; -} - -static void -Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f10; -} - -static void -Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f100; -} - -static void -Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f20; -} - -static void -Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f200; -} - -static void -Opcode_rur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f30; -} - -static void -Opcode_wur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f300; -} - -static void -Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90804; -} - -static void -Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca0004; -} - -static void -Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90904; -} - -static void -Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca1004; -} - -static void -Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90a04; -} - -static void -Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca2004; -} - -static void -Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90b04; -} - -static void -Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca3004; -} - -static void -Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90c04; -} - -static void -Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca4004; -} - -static void -Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90d04; -} - -static void -Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca5004; -} - -static void -Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90e04; -} - -static void -Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca6004; -} - -static void -Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90f04; -} - -static void -Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca7004; -} - -static void -Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30e70; -} - -static void -Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3e700; -} - -static void -Opcode_ae_lp16f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d1080; -} - -static void -Opcode_ae_lp16f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa50004; -} - -static void -Opcode_ae_lp16f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d2080; -} - -static void -Opcode_ae_lp16f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa90004; -} - -static void -Opcode_ae_lp16f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d3000; -} - -static void -Opcode_ae_lp16f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xac0004; -} - -static void -Opcode_ae_lp16f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d3080; -} - -static void -Opcode_ae_lp16f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaf0004; -} - -static void -Opcode_ae_lp24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d6080; -} - -static void -Opcode_ae_lp24_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa58004; -} - -static void -Opcode_ae_lp24_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d7000; -} - -static void -Opcode_ae_lp24_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa98004; -} - -static void -Opcode_ae_lp24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d7080; -} - -static void -Opcode_ae_lp24_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xac8004; -} - -static void -Opcode_ae_lp24_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d8080; -} - -static void -Opcode_ae_lp24_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaf8004; -} - -static void -Opcode_ae_lp24f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d9000; -} - -static void -Opcode_ae_lp24f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa60004; -} - -static void -Opcode_ae_lp24f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1da000; -} - -static void -Opcode_ae_lp24f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaa0004; -} - -static void -Opcode_ae_lp24f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dc000; -} - -static void -Opcode_ae_lp24f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xad0004; -} - -static void -Opcode_ae_lp24f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d9080; -} - -static void -Opcode_ae_lp24f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb00004; -} - -static void -Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d4080; -} - -static void -Opcode_ae_lp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa68004; -} - -static void -Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d5000; -} - -static void -Opcode_ae_lp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaa8004; -} - -static void -Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d6000; -} - -static void -Opcode_ae_lp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xad8004; -} - -static void -Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d5080; -} - -static void -Opcode_ae_lp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb08004; -} - -static void -Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dd000; -} - -static void -Opcode_ae_lp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa70004; -} - -static void -Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1de000; -} - -static void -Opcode_ae_lp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xab0004; -} - -static void -Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dd080; -} - -static void -Opcode_ae_lp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xae0004; -} - -static void -Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1de080; -} - -static void -Opcode_ae_lp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb10004; -} - -static void -Opcode_ae_lp24x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1da080; -} - -static void -Opcode_ae_lp24x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa78004; -} - -static void -Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1db000; -} - -static void -Opcode_ae_lp24x2_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xab8004; -} - -static void -Opcode_ae_lp24x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1db080; -} - -static void -Opcode_ae_lp24x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xae8004; -} - -static void -Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dc080; -} - -static void -Opcode_ae_lp24x2_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb18004; -} - -static void -Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e8000; -} - -static void -Opcode_ae_sp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb20004; -} - -static void -Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f0000; -} - -static void -Opcode_ae_sp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb50004; -} - -static void -Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e1080; -} - -static void -Opcode_ae_sp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb80004; -} - -static void -Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e2080; -} - -static void -Opcode_ae_sp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbb0004; -} - -static void -Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ec000; -} - -static void -Opcode_ae_sp24x2s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb28004; -} - -static void -Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e9080; -} - -static void -Opcode_ae_sp24x2s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb58004; -} - -static void -Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ea080; -} - -static void -Opcode_ae_sp24x2s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb88004; -} - -static void -Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1eb000; -} - -static void -Opcode_ae_sp24x2s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbb8004; -} - -static void -Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e7080; -} - -static void -Opcode_ae_sp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb30004; -} - -static void -Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e8080; -} - -static void -Opcode_ae_sp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb60004; -} - -static void -Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e9000; -} - -static void -Opcode_ae_sp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb90004; -} - -static void -Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ea000; -} - -static void -Opcode_ae_sp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbc0004; -} - -static void -Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1df080; -} - -static void -Opcode_ae_sp16f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb38004; -} - -static void -Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e1000; -} - -static void -Opcode_ae_sp16f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb68004; -} - -static void -Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e2000; -} - -static void -Opcode_ae_sp16f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb98004; -} - -static void -Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e4000; -} - -static void -Opcode_ae_sp16f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbc8004; -} - -static void -Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e6000; -} - -static void -Opcode_ae_sp24s_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb40004; -} - -static void -Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e5080; -} - -static void -Opcode_ae_sp24s_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb70004; -} - -static void -Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e6080; -} - -static void -Opcode_ae_sp24s_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xba0004; -} - -static void -Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e7000; -} - -static void -Opcode_ae_sp24s_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbd0004; -} - -static void -Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e3000; -} - -static void -Opcode_ae_sp24f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb48004; -} - -static void -Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e3080; -} - -static void -Opcode_ae_sp24f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb78004; -} - -static void -Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e4080; -} - -static void -Opcode_ae_sp24f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xba8004; -} - -static void -Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e5000; -} - -static void -Opcode_ae_sp24f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbd8004; -} - -static void -Opcode_ae_lq56_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed030; -} - -static void -Opcode_ae_lq56_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc10004; -} - -static void -Opcode_ae_lq56_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee010; -} - -static void -Opcode_ae_lq56_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc12004; -} - -static void -Opcode_ae_lq56_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee020; -} - -static void -Opcode_ae_lq56_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc20004; -} - -static void -Opcode_ae_lq56_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef000; -} - -static void -Opcode_ae_lq56_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc22004; -} - -static void -Opcode_ae_lq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed000; -} - -static void -Opcode_ae_lq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc11004; -} - -static void -Opcode_ae_lq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee000; -} - -static void -Opcode_ae_lq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc13004; -} - -static void -Opcode_ae_lq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed010; -} - -static void -Opcode_ae_lq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc21004; -} - -static void -Opcode_ae_lq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed020; -} - -static void -Opcode_ae_lq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc23004; -} - -static void -Opcode_ae_sq56s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f0080; -} - -static void -Opcode_ae_sq56s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc30004; -} - -static void -Opcode_ae_sq56s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f00c0; -} - -static void -Opcode_ae_sq56s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc38004; -} - -static void -Opcode_ae_sq56s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3000; -} - -static void -Opcode_ae_sq56s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc40004; -} - -static void -Opcode_ae_sq56s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3040; -} - -static void -Opcode_ae_sq56s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc48004; -} - -static void -Opcode_ae_sq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ec080; -} - -static void -Opcode_ae_sq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc34004; -} - -static void -Opcode_ae_sq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ec0c0; -} - -static void -Opcode_ae_sq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc3c004; -} - -static void -Opcode_ae_sq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f4000; -} - -static void -Opcode_ae_sq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc44004; -} - -static void -Opcode_ae_sq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f8000; -} - -static void -Opcode_ae_sq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc4c004; -} - -static void -Opcode_ae_zerop48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16b88; -} - -static void -Opcode_ae_movp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16808; -} - -static void -Opcode_ae_movp48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2400; -} - -static void -Opcode_ae_movp48_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90004; -} - -static void -Opcode_ae_selp24_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10780; -} - -static void -Opcode_ae_selp24_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2e00; -} - -static void -Opcode_ae_selp24_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10708; -} - -static void -Opcode_ae_selp24_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fa600; -} - -static void -Opcode_ae_selp24_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10688; -} - -static void -Opcode_ae_selp24_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fa200; -} - -static void -Opcode_ae_selp24_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10700; -} - -static void -Opcode_ae_selp24_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fa000; -} - -static void -Opcode_ae_movtp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c200; -} - -static void -Opcode_ae_movfp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c004; -} - -static void -Opcode_ae_movtp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10480; -} - -static void -Opcode_ae_movfp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10400; -} - -static void -Opcode_ae_movpa24x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1df000; -} - -static void -Opcode_ae_movpa24x2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc00004; -} - -static void -Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1eb080; -} - -static void -Opcode_ae_truncp24a32x2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc08004; -} - -static void -Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3081; -} - -static void -Opcode_ae_cvta32p24_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcb0004; -} - -static void -Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3080; -} - -static void -Opcode_ae_cvta32p24_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcb8004; -} - -static void -Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d8000; -} - -static void -Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbe0004; -} - -static void -Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d4000; -} - -static void -Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbe8004; -} - -static void -Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d2000; -} - -static void -Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbf0004; -} - -static void -Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d1000; -} - -static void -Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbf8004; -} - -static void -Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x51000; -} - -static void -Opcode_ae_truncp16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16b08; -} - -static void -Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e48; -} - -static void -Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e28; -} - -static void -Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e18; -} - -static void -Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e08; -} - -static void -Opcode_ae_roundsp16sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16908; -} - -static void -Opcode_ae_roundsp16asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16888; -} - -static void -Opcode_ae_zeroq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16085; -} - -static void -Opcode_ae_movq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16007; -} - -static void -Opcode_ae_movq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2500; -} - -static void -Opcode_ae_movq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90414; -} - -static void -Opcode_ae_movtq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f6000; -} - -static void -Opcode_ae_movtq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe50014; -} - -static void -Opcode_ae_movfq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5000; -} - -static void -Opcode_ae_movfq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe60014; -} - -static void -Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee030; -} - -static void -Opcode_ae_cvtq48a32s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe72034; -} - -static void -Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16006; -} - -static void -Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16005; -} - -static void -Opcode_ae_satq48s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50139; -} - -static void -Opcode_ae_truncq32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16047; -} - -static void -Opcode_ae_roundsq32sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16027; -} - -static void -Opcode_ae_roundsq32asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16017; -} - -static void -Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3086; -} - -static void -Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe70014; -} - -static void -Opcode_ae_movap24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3084; -} - -static void -Opcode_ae_movap24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc70004; -} - -static void -Opcode_ae_movap24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3082; -} - -static void -Opcode_ae_movap24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc78004; -} - -static void -Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3083; -} - -static void -Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc80004; -} - -static void -Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3088; -} - -static void -Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc88004; -} - -static void -Opcode_ae_addp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10500; -} - -static void -Opcode_ae_subp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10788; -} - -static void -Opcode_ae_negp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c600; -} - -static void -Opcode_ae_absp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c480; -} - -static void -Opcode_ae_maxp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10580; -} - -static void -Opcode_ae_minp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10588; -} - -static void -Opcode_ae_maxbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10000; -} - -static void -Opcode_ae_minbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10200; -} - -static void -Opcode_ae_addsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10600; -} - -static void -Opcode_ae_subsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c400; -} - -static void -Opcode_ae_negsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c488; -} - -static void -Opcode_ae_abssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c500; -} - -static void -Opcode_ae_andp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10508; -} - -static void -Opcode_ae_nandp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10608; -} - -static void -Opcode_ae_orp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10680; -} - -static void -Opcode_ae_xorp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c408; -} - -static void -Opcode_ae_ltp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c002; -} - -static void -Opcode_ae_lep24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c001; -} - -static void -Opcode_ae_eqp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c000; -} - -static void -Opcode_ae_addq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x52000; -} - -static void -Opcode_ae_subq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50035; -} - -static void -Opcode_ae_negq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5003c; -} - -static void -Opcode_ae_absq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50039; -} - -static void -Opcode_ae_maxq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50032; -} - -static void -Opcode_ae_minq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50034; -} - -static void -Opcode_ae_maxbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50000; -} - -static void -Opcode_ae_minbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50010; -} - -static void -Opcode_ae_addsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50030; -} - -static void -Opcode_ae_subsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50036; -} - -static void -Opcode_ae_negsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500b9; -} - -static void -Opcode_ae_abssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5003a; -} - -static void -Opcode_ae_andq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50031; -} - -static void -Opcode_ae_nandq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50038; -} - -static void -Opcode_ae_orq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50033; -} - -static void -Opcode_ae_xorq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50037; -} - -static void -Opcode_ae_sllip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x14000; -} - -static void -Opcode_ae_srlip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15000; -} - -static void -Opcode_ae_sraip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x14800; -} - -static void -Opcode_ae_sllsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16a08; -} - -static void -Opcode_ae_srlsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16a88; -} - -static void -Opcode_ae_srasp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16988; -} - -static void -Opcode_ae_sllisp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x18000; -} - -static void -Opcode_ae_sllssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16c08; -} - -static void -Opcode_ae_slliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1000; -} - -static void -Opcode_ae_slliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50004; -} - -static void -Opcode_ae_srliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1800; -} - -static void -Opcode_ae_srliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50404; -} - -static void -Opcode_ae_sraiq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1400; -} - -static void -Opcode_ae_sraiq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50804; -} - -static void -Opcode_ae_sllsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2600; -} - -static void -Opcode_ae_sllsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90014; -} - -static void -Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2504; -} - -static void -Opcode_ae_srlsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90114; -} - -static void -Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2502; -} - -static void -Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90214; -} - -static void -Opcode_ae_sllaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5001; -} - -static void -Opcode_ae_sllaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe10014; -} - -static void -Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5008; -} - -static void -Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe20014; -} - -static void -Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5004; -} - -static void -Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30014; -} - -static void -Opcode_ae_sllisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2000; -} - -static void -Opcode_ae_sllisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50c04; -} - -static void -Opcode_ae_sllssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2501; -} - -static void -Opcode_ae_sllssq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90314; -} - -static void -Opcode_ae_sllasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5002; -} - -static void -Opcode_ae_sllasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe40014; -} - -static void -Opcode_ae_ltq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50800; -} - -static void -Opcode_ae_leq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50040; -} - -static void -Opcode_ae_eqq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50020; -} - -static void -Opcode_ae_nsaq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3085; -} - -static void -Opcode_ae_nsaq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe74014; -} - -static void -Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19004; -} - -static void -Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19005; -} - -static void -Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19002; -} - -static void -Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19003; -} - -static void -Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19000; -} - -static void -Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19001; -} - -static void -Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1900a; -} - -static void -Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1900b; -} - -static void -Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19008; -} - -static void -Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19009; -} - -static void -Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19006; -} - -static void -Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19007; -} - -static void -Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60101; -} - -static void -Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008b; -} - -static void -Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60180; -} - -static void -Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008f; -} - -static void -Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008c; -} - -static void -Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60108; -} - -static void -Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008e; -} - -static void -Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008a; -} - -static void -Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60104; -} - -static void -Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008d; -} - -static void -Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60089; -} - -static void -Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60102; -} - -static void -Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60006; -} - -static void -Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64000; -} - -static void -Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000f; -} - -static void -Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60005; -} - -static void -Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60100; -} - -static void -Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000e; -} - -static void -Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60003; -} - -static void -Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60080; -} - -static void -Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000d; -} - -static void -Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x68000; -} - -static void -Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60008; -} - -static void -Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000b; -} - -static void -Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60181; -} - -static void -Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010b; -} - -static void -Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60189; -} - -static void -Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010f; -} - -static void -Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010c; -} - -static void -Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60187; -} - -static void -Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010e; -} - -static void -Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010a; -} - -static void -Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60186; -} - -static void -Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010d; -} - -static void -Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60109; -} - -static void -Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60185; -} - -static void -Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000c; -} - -static void -Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60088; -} - -static void -Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000a; -} - -static void -Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60084; -} - -static void -Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60009; -} - -static void -Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60082; -} - -static void -Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60007; -} - -static void -Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60081; -} - -static void -Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60183; -} - -static void -Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018d; -} - -static void -Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60188; -} - -static void -Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018b; -} - -static void -Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60184; -} - -static void -Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018c; -} - -static void -Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60182; -} - -static void -Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018a; -} - -static void -Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15807; -} - -static void -Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15806; -} - -static void -Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580a; -} - -static void -Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15809; -} - -static void -Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580b; -} - -static void -Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580c; -} - -static void -Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580e; -} - -static void -Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580d; -} - -static void -Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15800; -} - -static void -Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16000; -} - -static void -Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15802; -} - -static void -Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15801; -} - -static void -Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15808; -} - -static void -Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15804; -} - -static void -Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15805; -} - -static void -Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15803; -} - -static void -Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16001; -} - -static void -Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580f; -} - -static void -Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16004; -} - -static void -Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16002; -} - -static void -Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16800; -} - -static void -Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16008; -} - -static void -Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16003; -} - -static void -Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x17000; -} - -static void -Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20007; -} - -static void -Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20002; -} - -static void -Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000c; -} - -static void -Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20003; -} - -static void -Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20005; -} - -static void -Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20000; -} - -static void -Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20009; -} - -static void -Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20004; -} - -static void -Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20006; -} - -static void -Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20001; -} - -static void -Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000a; -} - -static void -Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20008; -} - -static void -Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30008; -} - -static void -Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000e; -} - -static void -Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30006; -} - -static void -Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30001; -} - -static void -Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30002; -} - -static void -Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000b; -} - -static void -Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30003; -} - -static void -Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000f; -} - -static void -Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30004; -} - -static void -Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000d; -} - -static void -Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30005; -} - -static void -Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000; -} - -static void -Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000; -} - -static void -Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000a; -} - -static void -Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40004; -} - -static void -Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000d; -} - -static void -Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000e; -} - -static void -Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30007; -} - -static void -Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40001; -} - -static void -Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000c; -} - -static void -Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000f; -} - -static void -Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30009; -} - -static void -Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40002; -} - -static void -Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000b; -} - -static void -Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000b; -} - -static void -Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40005; -} - -static void -Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000f; -} - -static void -Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40009; -} - -static void -Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000a; -} - -static void -Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40008; -} - -static void -Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000d; -} - -static void -Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40006; -} - -static void -Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000c; -} - -static void -Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40003; -} - -static void -Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000e; -} - -static void -Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40007; -} - -static void -Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64004; -} - -static void -Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64080; -} - -static void -Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64008; -} - -static void -Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64100; -} - -static void -Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64003; -} - -static void -Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64006; -} - -static void -Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64005; -} - -static void -Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64007; -} - -static void -Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64009; -} - -static void -Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400c; -} - -static void -Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400a; -} - -static void -Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400b; -} - -static void -Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400d; -} - -static void -Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400f; -} - -static void -Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400e; -} - -static void -Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64081; -} - -static void -Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60000; -} - -static void -Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60002; -} - -static void -Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60001; -} - -static void -Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60004; -} - -static void -Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60083; -} - -static void -Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60086; -} - -static void -Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60085; -} - -static void -Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60087; -} - -static void -Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60103; -} - -static void -Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60106; -} - -static void -Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60105; -} - -static void -Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60107; -} - -static void -Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018e; -} - -static void -Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64001; -} - -static void -Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018f; -} - -static void -Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64002; -} - -static void -Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00014; -} - -static void -Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00004; -} - -static void -Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa10004; -} - -static void -Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe7e014; -} - -static void -Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca8004; -} - -static void -Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc60004; -} - -static void -Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00024; -} - -static void -Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa20004; -} - -static void -Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00004; -} - -static void -Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf01004; -} - -static void -Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf02004; -} - -static void -Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa30004; -} - -static void -Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa40004; -} - -static void -Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf11004; -} - -static void -Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00004; -} - -static void -Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe7c014; -} - -static void -Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe7d014; -} - -static void -Opcode_ae_slaasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f6008; -} - -static void -Opcode_ae_addbrba32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f7000; -} - -static void -Opcode_ae_minabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c508; -} - -static void -Opcode_ae_maxabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c580; -} - -static void -Opcode_ae_minabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x52004; -} - -static void -Opcode_ae_maxabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x52008; -} - -static void -Opcode_rur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f60; -} - -static void -Opcode_wur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f600; -} - -static void -Opcode_rur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f70; -} - -static void -Opcode_wur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f700; -} - -static void -Opcode_ae_lp24x2_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fe080; -} - -static void -Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900000; -} - -static void -Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ff000; -} - -static void -Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800000; -} - -static void -Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f4080; -} - -static void -Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0; -} - -static void -Opcode_ae_lp24_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fc080; -} - -static void -Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700000; -} - -static void -Opcode_ae_lp24f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fe000; -} - -static void -Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600000; -} - -static void -Opcode_ae_lp16f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fc000; -} - -static void -Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ff080; -} - -static void -Opcode_ae_lq56_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00000; -} - -static void -Opcode_ae_sq56s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f8080; -} - -static void -Opcode_ae_lq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef010; -} - -static void -Opcode_ae_sq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f8040; -} - -static void -Opcode_read_ipq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe4000; -} - -static void -Opcode_read_ipq_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a020; -} - -static void -Opcode_check_ipq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe5000; -} - -static void -Opcode_check_ipq_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a000; -} - -static void -Opcode_write_opq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe6000; -} - -static void -Opcode_write_opq_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a030; -} - -static void -Opcode_check_opq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe7000; -} - -static void -Opcode_check_opq_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a010; -} - -static void -Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30e60; -} - -static void -Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3e600; -} - -static void -Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0000; -} - -static void -Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe1000; -} - -static void -Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe1200; -} - -static void -Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe2000; -} - -xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { - Opcode_excw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { - Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfme_encode_fns[] = { - Opcode_rfme_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { - Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { - Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { - Opcode_call12_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { - Opcode_call8_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { - Opcode_call4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { - Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { - Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { - Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { - Opcode_entry_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { - Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { - Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { - Opcode_retw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { - 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { - Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { - Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { - Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { - Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { - Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { - Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { - Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { - Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { - Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { - Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { - 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { - 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { - 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { - 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { - 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { - 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { - 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { - 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { - 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { - 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { - 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { - Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { - Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { - Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { - Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { - Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { - Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { - Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { - Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { - Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { - Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { - Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { - Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { - Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { - Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { - Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { - Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { - Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { - Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { - Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { - Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { - Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { - Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { - Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { - Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { - Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { - Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { - Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { - Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { - Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { - Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { - Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { - Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { - Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { - Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { - Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { - Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { - Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { - Opcode_call0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { - Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { - Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { - Opcode_ill_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { - Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { - Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { - Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { - Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { - Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { - Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { - Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { - Opcode_loop_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { - Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { - Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { - Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { - Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { - Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { - Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { - Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { - Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { - Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { - Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { - Opcode_ret_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { - Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { - Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { - Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { - Opcode_s32nb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { - Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { - Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { - Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { - Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { - Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { - Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { - Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { - Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { - Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { - Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { - Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { - Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { - Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { - Opcode_memw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { - Opcode_extw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { - Opcode_isync_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { - Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { - Opcode_esync_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { - Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { - Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { - Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { - Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { - Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { - Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { - Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { - Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { - Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { - Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { - Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { - Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { - Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { - Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { - Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { - Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { - Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { - Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { - Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { - Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_243_encode_fns[] = { - Opcode_rsr_243_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { - Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { - Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { - Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { - Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { - Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { - Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { - Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { - Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { - Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { - Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { - Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { - Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { - Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { - Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { - Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { - Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { - Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { - Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { - Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { - Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { - Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { - Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { - Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { - Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { - Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { - Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { - Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { - Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { - Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { - Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { - Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { - Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { - Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { - Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { - Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { - Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { - Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { - Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { - Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { - Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { - Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { - Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { - Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { - Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { - Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { - Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { - Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { - Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { - Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { - Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { - Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { - Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { - Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { - Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { - Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { - Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { - Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { - Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { - Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { - Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { - Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { - Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { - Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { - Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { - Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { - Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { - Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { - Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { - Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { - Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { - Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { - Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { - Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { - Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { - Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { - Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { - Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { - Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { - Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { - Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { - Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { - Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { - Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { - Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { - Opcode_mull_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { - Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { - Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { - Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { - Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { - Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { - Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { - Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { - Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { - Opcode_break_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { - 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { - Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { - Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { - Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { - Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { - Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { - Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { - Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { - Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { - Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { - Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { - Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { - Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { - Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { - Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { - Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { - Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { - Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { - Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { - Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { - Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { - Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { - Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { - Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { - Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { - Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { - Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { - Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { - Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { - Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { - Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { - Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { - Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { - Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { - Opcode_lddr32_p_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { - Opcode_sddr32_p_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { - Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { - Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { - Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { - Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { - Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { - Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { - Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { - Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { - Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { - Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { - Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { - Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { - Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { - Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { - Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { - Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { - Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { - Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { - Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { - Opcode_rsr_memctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { - Opcode_wsr_memctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { - Opcode_xsr_memctl_Slot_inst_encode, 0, 0, 0, 0 -}; - - -xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { - Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { - Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { - Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { - Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { - Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { - Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_mepc_encode_fns[] = { - Opcode_rsr_mepc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_mepc_encode_fns[] = { - Opcode_wsr_mepc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_mepc_encode_fns[] = { - Opcode_xsr_mepc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_meps_encode_fns[] = { - Opcode_rsr_meps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_meps_encode_fns[] = { - Opcode_wsr_meps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_meps_encode_fns[] = { - Opcode_xsr_meps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_mesave_encode_fns[] = { - Opcode_rsr_mesave_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_mesave_encode_fns[] = { - Opcode_wsr_mesave_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_mesave_encode_fns[] = { - Opcode_xsr_mesave_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_mesr_encode_fns[] = { - Opcode_rsr_mesr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_mesr_encode_fns[] = { - Opcode_wsr_mesr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_mesr_encode_fns[] = { - Opcode_xsr_mesr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_mecr_encode_fns[] = { - Opcode_rsr_mecr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_mecr_encode_fns[] = { - Opcode_wsr_mecr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_mecr_encode_fns[] = { - Opcode_xsr_mecr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_mevaddr_encode_fns[] = { - Opcode_rsr_mevaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_mevaddr_encode_fns[] = { - Opcode_wsr_mevaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_mevaddr_encode_fns[] = { - Opcode_xsr_mevaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { - Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { - Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { - Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { - Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { - Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { - Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { - Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { - Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { - Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { - Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { - Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { - Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { - Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { - Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { - Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { - Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { - Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { - Opcode_iii_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { - Opcode_lict_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { - Opcode_licw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { - Opcode_sict_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { - Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { - Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { - Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = { - Opcode_diwbui_p_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { - Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { - Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { - Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { - Opcode_dii_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { - Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { - Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { - Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { - Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { - Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { - Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { - Opcode_diu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { - Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { - Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_prefctl_encode_fns[] = { - Opcode_rsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_prefctl_encode_fns[] = { - Opcode_wsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_prefctl_encode_fns[] = { - Opcode_xsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { - Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { - Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { - Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { - Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { - Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { - Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { - Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { - Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { - Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { - Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { - Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { - Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { - Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { - Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { - Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { - Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { - Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { - Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { - Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { - Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { - Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { - Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { - Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { - Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { - Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { - Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { - Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { - Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { - Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { - Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { - Opcode_quou_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { - Opcode_quos_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { - Opcode_remu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { - Opcode_rems_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { - Opcode_rer_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { - Opcode_wer_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { - Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { - Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { - Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { - Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { - Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { - Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = { - Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = { - Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { - Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { - Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { - Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { - Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { - Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { - Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { - Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { - Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { - Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { - Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { - Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { - Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { - Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { - Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { - Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { - Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { - Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { - Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = { - Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = { - Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = { - Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = { - Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = { - Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = { - Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = { - Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = { - Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = { - Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = { - Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = { - Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = { - Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = { - Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = { - Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = { - Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = { - Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = { - Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = { - Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = { - Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = { - Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = { - Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = { - Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = { - Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = { - Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = { - Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = { - Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = { - Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = { - Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = { - Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = { - Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = { - Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = { - Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = { - Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = { - Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = { - Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = { - Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = { - Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = { - Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = { - Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = { - Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = { - Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = { - Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = { - Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = { - Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = { - Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = { - Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = { - Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = { - Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = { - Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = { - Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = { - Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = { - Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = { - Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = { - Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = { - Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = { - Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = { - Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = { - Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = { - Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = { - Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = { - Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = { - Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = { - Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = { - Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = { - 0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = { - Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, Opcode_ae_selp24_ll_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, Opcode_ae_selp24_lh_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, Opcode_ae_selp24_hl_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, Opcode_ae_selp24_hh_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = { - Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { - Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = { - Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = { - Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { - Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { - Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { - Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { - Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = { - Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = { - Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = { - Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = { - Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = { - 0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { - Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = { - Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = { - Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { - Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { - Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = { - Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = { - Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = { - Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = { - Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { - Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { - Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = { - Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { - Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { - Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = { - Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = { - Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = { - Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = { - Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { - Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { - Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { - Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { - Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { - Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { - Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { - Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { - Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { - Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { - Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { - Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { - Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { - Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { - Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { - Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { - Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { - Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_slaasq56s_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_addbrba32_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_minabssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minabssp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxabssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxabssp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minabssq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minabssq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxabssq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxabssq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_cbegin0_encode_fns[] = { - Opcode_rur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_cbegin0_encode_fns[] = { - Opcode_wur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_cend0_encode_fns[] = { - Opcode_rur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_cend0_encode_fns[] = { - Opcode_wur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24x2_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp16f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lq56_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sq56s_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lq32f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sq32f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_read_ipq_encode_fns[] = { - Opcode_read_ipq_Slot_inst_encode, 0, 0, Opcode_read_ipq_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_check_ipq_encode_fns[] = { - Opcode_check_ipq_Slot_inst_encode, 0, 0, Opcode_check_ipq_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_write_opq_encode_fns[] = { - Opcode_write_opq_Slot_inst_encode, 0, 0, Opcode_write_opq_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_check_opq_encode_fns[] = { - Opcode_check_opq_Slot_inst_encode, 0, 0, Opcode_check_opq_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { - Opcode_rur_expstate_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { - Opcode_wur_expstate_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { - Opcode_read_impwire_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { - Opcode_setb_expstate_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { - Opcode_clrb_expstate_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { - Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0, 0, 0 -}; - -int num_bypass_groups() { - return 0; -} - -int num_bypass_group_chunks() { - return 0; -} - -uint32 *bypass_entry(int i) { - return 0; -} - - -/* Opcode table. */ - -static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_shift32x5, 3 }, - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_shift32x5, 3 }, - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_opcode_internal opcodes[] = { - { "excw", ICLASS_xt_iclass_excw, - 0, - Opcode_excw_encode_fns, 0, 0 }, - { "rfe", ICLASS_xt_iclass_rfe, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfe_encode_fns, 0, 0 }, - { "rfme", ICLASS_xt_iclass_rfme, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfme_encode_fns, 0, 0 }, - { "rfde", ICLASS_xt_iclass_rfde, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfde_encode_fns, 0, 0 }, - { "syscall", ICLASS_xt_iclass_syscall, - 0, - Opcode_syscall_encode_fns, 0, 0 }, - { "call12", ICLASS_xt_iclass_call12, - XTENSA_OPCODE_IS_CALL, - Opcode_call12_encode_fns, 0, 0 }, - { "call8", ICLASS_xt_iclass_call8, - XTENSA_OPCODE_IS_CALL, - Opcode_call8_encode_fns, 0, 0 }, - { "call4", ICLASS_xt_iclass_call4, - XTENSA_OPCODE_IS_CALL, - Opcode_call4_encode_fns, 0, 0 }, - { "callx12", ICLASS_xt_iclass_callx12, - XTENSA_OPCODE_IS_CALL, - Opcode_callx12_encode_fns, 0, 0 }, - { "callx8", ICLASS_xt_iclass_callx8, - XTENSA_OPCODE_IS_CALL, - Opcode_callx8_encode_fns, 0, 0 }, - { "callx4", ICLASS_xt_iclass_callx4, - XTENSA_OPCODE_IS_CALL, - Opcode_callx4_encode_fns, 0, 0 }, - { "entry", ICLASS_xt_iclass_entry, - 0, - Opcode_entry_encode_fns, 0, 0 }, - { "movsp", ICLASS_xt_iclass_movsp, - 0, - Opcode_movsp_encode_fns, 0, 0 }, - { "rotw", ICLASS_xt_iclass_rotw, - 0, - Opcode_rotw_encode_fns, 0, 0 }, - { "retw", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_encode_fns, 0, 0 }, - { "retw.n", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_n_encode_fns, 0, 0 }, - { "rfwo", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwo_encode_fns, 0, 0 }, - { "rfwu", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwu_encode_fns, 0, 0 }, - { "l32e", ICLASS_xt_iclass_l32e, - 0, - Opcode_l32e_encode_fns, 0, 0 }, - { "s32e", ICLASS_xt_iclass_s32e, - 0, - Opcode_s32e_encode_fns, 0, 0 }, - { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, - 0, - Opcode_rsr_windowbase_encode_fns, 0, 0 }, - { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, - 0, - Opcode_wsr_windowbase_encode_fns, 0, 0 }, - { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, - 0, - Opcode_xsr_windowbase_encode_fns, 0, 0 }, - { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, - 0, - Opcode_rsr_windowstart_encode_fns, 0, 0 }, - { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, - 0, - Opcode_wsr_windowstart_encode_fns, 0, 0 }, - { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, - 0, - Opcode_xsr_windowstart_encode_fns, 0, 0 }, - { "add.n", ICLASS_xt_iclass_add_n, - 0, - Opcode_add_n_encode_fns, 0, 0 }, - { "addi.n", ICLASS_xt_iclass_addi_n, - 0, - Opcode_addi_n_encode_fns, 0, 0 }, - { "beqz.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_n_encode_fns, 0, 0 }, - { "bnez.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_n_encode_fns, 0, 0 }, - { "ill.n", ICLASS_xt_iclass_ill_n, - 0, - Opcode_ill_n_encode_fns, 0, 0 }, - { "l32i.n", ICLASS_xt_iclass_loadi4, - 0, - Opcode_l32i_n_encode_fns, 0, 0 }, - { "mov.n", ICLASS_xt_iclass_mov_n, - 0, - Opcode_mov_n_encode_fns, 0, 0 }, - { "movi.n", ICLASS_xt_iclass_movi_n, - 0, - Opcode_movi_n_encode_fns, 0, 0 }, - { "nop.n", ICLASS_xt_iclass_nopn, - 0, - Opcode_nop_n_encode_fns, 0, 0 }, - { "ret.n", ICLASS_xt_iclass_retn, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_n_encode_fns, 0, 0 }, - { "s32i.n", ICLASS_xt_iclass_storei4, - 0, - Opcode_s32i_n_encode_fns, 0, 0 }, - { "addi", ICLASS_xt_iclass_addi, - 0, - Opcode_addi_encode_fns, 0, 0 }, - { "addmi", ICLASS_xt_iclass_addmi, - 0, - Opcode_addmi_encode_fns, 0, 0 }, - { "add", ICLASS_xt_iclass_addsub, - 0, - Opcode_add_encode_fns, 0, 0 }, - { "sub", ICLASS_xt_iclass_addsub, - 0, - Opcode_sub_encode_fns, 0, 0 }, - { "addx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx2_encode_fns, 0, 0 }, - { "addx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx4_encode_fns, 0, 0 }, - { "addx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx8_encode_fns, 0, 0 }, - { "subx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx2_encode_fns, 0, 0 }, - { "subx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx4_encode_fns, 0, 0 }, - { "subx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx8_encode_fns, 0, 0 }, - { "and", ICLASS_xt_iclass_bit, - 0, - Opcode_and_encode_fns, 0, 0 }, - { "or", ICLASS_xt_iclass_bit, - 0, - Opcode_or_encode_fns, 0, 0 }, - { "xor", ICLASS_xt_iclass_bit, - 0, - Opcode_xor_encode_fns, 0, 0 }, - { "beqi", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqi_encode_fns, 0, 0 }, - { "bnei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnei_encode_fns, 0, 0 }, - { "bgei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgei_encode_fns, 0, 0 }, - { "blti", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blti_encode_fns, 0, 0 }, - { "bbci", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbci_encode_fns, 0, 0 }, - { "bbsi", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbsi_encode_fns, 0, 0 }, - { "bgeui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeui_encode_fns, 0, 0 }, - { "bltui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltui_encode_fns, 0, 0 }, - { "beq", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beq_encode_fns, 0, 0 }, - { "bne", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bne_encode_fns, 0, 0 }, - { "bge", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bge_encode_fns, 0, 0 }, - { "blt", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blt_encode_fns, 0, 0 }, - { "bgeu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeu_encode_fns, 0, 0 }, - { "bltu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltu_encode_fns, 0, 0 }, - { "bany", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bany_encode_fns, 0, 0 }, - { "bnone", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnone_encode_fns, 0, 0 }, - { "ball", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_ball_encode_fns, 0, 0 }, - { "bnall", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnall_encode_fns, 0, 0 }, - { "bbc", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbc_encode_fns, 0, 0 }, - { "bbs", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbs_encode_fns, 0, 0 }, - { "beqz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_encode_fns, 0, 0 }, - { "bnez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_encode_fns, 0, 0 }, - { "bgez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgez_encode_fns, 0, 0 }, - { "bltz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltz_encode_fns, 0, 0 }, - { "call0", ICLASS_xt_iclass_call0, - XTENSA_OPCODE_IS_CALL, - Opcode_call0_encode_fns, 0, 0 }, - { "callx0", ICLASS_xt_iclass_callx0, - XTENSA_OPCODE_IS_CALL, - Opcode_callx0_encode_fns, 0, 0 }, - { "extui", ICLASS_xt_iclass_exti, - 0, - Opcode_extui_encode_fns, 0, 0 }, - { "ill", ICLASS_xt_iclass_ill, - 0, - Opcode_ill_encode_fns, 0, 0 }, - { "j", ICLASS_xt_iclass_jump, - XTENSA_OPCODE_IS_JUMP, - Opcode_j_encode_fns, 0, 0 }, - { "jx", ICLASS_xt_iclass_jumpx, - XTENSA_OPCODE_IS_JUMP, - Opcode_jx_encode_fns, 0, 0 }, - { "l16ui", ICLASS_xt_iclass_l16ui, - 0, - Opcode_l16ui_encode_fns, 0, 0 }, - { "l16si", ICLASS_xt_iclass_l16si, - 0, - Opcode_l16si_encode_fns, 0, 0 }, - { "l32i", ICLASS_xt_iclass_l32i, - 0, - Opcode_l32i_encode_fns, 0, 0 }, - { "l32r", ICLASS_xt_iclass_l32r, - 0, - Opcode_l32r_encode_fns, 0, 0 }, - { "l8ui", ICLASS_xt_iclass_l8i, - 0, - Opcode_l8ui_encode_fns, 0, 0 }, - { "loop", ICLASS_xt_iclass_loop, - XTENSA_OPCODE_IS_LOOP, - Opcode_loop_encode_fns, 0, 0 }, - { "loopnez", ICLASS_xt_iclass_loopz, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopnez_encode_fns, 0, 0 }, - { "loopgtz", ICLASS_xt_iclass_loopz, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopgtz_encode_fns, 0, 0 }, - { "movi", ICLASS_xt_iclass_movi, - 0, - Opcode_movi_encode_fns, 0, 0 }, - { "moveqz", ICLASS_xt_iclass_movz, - 0, - Opcode_moveqz_encode_fns, 0, 0 }, - { "movnez", ICLASS_xt_iclass_movz, - 0, - Opcode_movnez_encode_fns, 0, 0 }, - { "movltz", ICLASS_xt_iclass_movz, - 0, - Opcode_movltz_encode_fns, 0, 0 }, - { "movgez", ICLASS_xt_iclass_movz, - 0, - Opcode_movgez_encode_fns, 0, 0 }, - { "neg", ICLASS_xt_iclass_neg, - 0, - Opcode_neg_encode_fns, 0, 0 }, - { "abs", ICLASS_xt_iclass_neg, - 0, - Opcode_abs_encode_fns, 0, 0 }, - { "nop", ICLASS_xt_iclass_nop, - 0, - Opcode_nop_encode_fns, 0, 0 }, - { "ret", ICLASS_xt_iclass_return, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_encode_fns, 0, 0 }, - { "simcall", ICLASS_xt_iclass_simcall, - 0, - Opcode_simcall_encode_fns, 0, 0 }, - { "s16i", ICLASS_xt_iclass_s16i, - 0, - Opcode_s16i_encode_fns, 0, 0 }, - { "s32i", ICLASS_xt_iclass_s32i, - 0, - Opcode_s32i_encode_fns, 0, 0 }, - { "s32nb", ICLASS_xt_iclass_s32nb, - 0, - Opcode_s32nb_encode_fns, 0, 0 }, - { "s8i", ICLASS_xt_iclass_s8i, - 0, - Opcode_s8i_encode_fns, 0, 0 }, - { "ssr", ICLASS_xt_iclass_sar, - 0, - Opcode_ssr_encode_fns, 0, 0 }, - { "ssl", ICLASS_xt_iclass_sar, - 0, - Opcode_ssl_encode_fns, 0, 0 }, - { "ssa8l", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8l_encode_fns, 0, 0 }, - { "ssa8b", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8b_encode_fns, 0, 0 }, - { "ssai", ICLASS_xt_iclass_sari, - 0, - Opcode_ssai_encode_fns, 0, 0 }, - { "sll", ICLASS_xt_iclass_shifts, - 0, - Opcode_sll_encode_fns, 0, 0 }, - { "src", ICLASS_xt_iclass_shiftst, - 0, - Opcode_src_encode_fns, 0, 0 }, - { "srl", ICLASS_xt_iclass_shiftt, - 0, - Opcode_srl_encode_fns, 0, 0 }, - { "sra", ICLASS_xt_iclass_shiftt, - 0, - Opcode_sra_encode_fns, 0, 0 }, - { "slli", ICLASS_xt_iclass_slli, - 0, - Opcode_slli_encode_fns, 0, 0 }, - { "srai", ICLASS_xt_iclass_srai, - 0, - Opcode_srai_encode_fns, 0, 0 }, - { "srli", ICLASS_xt_iclass_srli, - 0, - Opcode_srli_encode_fns, 0, 0 }, - { "memw", ICLASS_xt_iclass_memw, - 0, - Opcode_memw_encode_fns, 0, 0 }, - { "extw", ICLASS_xt_iclass_extw, - 0, - Opcode_extw_encode_fns, 0, 0 }, - { "isync", ICLASS_xt_iclass_isync, - 0, - Opcode_isync_encode_fns, 0, 0 }, - { "rsync", ICLASS_xt_iclass_sync, - 0, - Opcode_rsync_encode_fns, 0, 0 }, - { "esync", ICLASS_xt_iclass_sync, - 0, - Opcode_esync_encode_fns, 0, 0 }, - { "dsync", ICLASS_xt_iclass_sync, - 0, - Opcode_dsync_encode_fns, 0, 0 }, - { "rsil", ICLASS_xt_iclass_rsil, - 0, - Opcode_rsil_encode_fns, 0, 0 }, - { "rsr.lend", ICLASS_xt_iclass_rsr_lend, - 0, - Opcode_rsr_lend_encode_fns, 0, 0 }, - { "wsr.lend", ICLASS_xt_iclass_wsr_lend, - 0, - Opcode_wsr_lend_encode_fns, 0, 0 }, - { "xsr.lend", ICLASS_xt_iclass_xsr_lend, - 0, - Opcode_xsr_lend_encode_fns, 0, 0 }, - { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, - 0, - Opcode_rsr_lcount_encode_fns, 0, 0 }, - { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, - 0, - Opcode_wsr_lcount_encode_fns, 0, 0 }, - { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, - 0, - Opcode_xsr_lcount_encode_fns, 0, 0 }, - { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, - 0, - Opcode_rsr_lbeg_encode_fns, 0, 0 }, - { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, - 0, - Opcode_wsr_lbeg_encode_fns, 0, 0 }, - { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, - 0, - Opcode_xsr_lbeg_encode_fns, 0, 0 }, - { "rsr.sar", ICLASS_xt_iclass_rsr_sar, - 0, - Opcode_rsr_sar_encode_fns, 0, 0 }, - { "wsr.sar", ICLASS_xt_iclass_wsr_sar, - 0, - Opcode_wsr_sar_encode_fns, 0, 0 }, - { "xsr.sar", ICLASS_xt_iclass_xsr_sar, - 0, - Opcode_xsr_sar_encode_fns, 0, 0 }, - - - - { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo, - 0, - Opcode_rsr_acclo_encode_fns, 0, 0 }, - { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo, - 0, - Opcode_wsr_acclo_encode_fns, 0, 0 }, - { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo, - 0, - Opcode_xsr_acclo_encode_fns, 0, 0 }, - - { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi, - 0, - Opcode_rsr_acchi_encode_fns, 0, 0 }, - { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi, - 0, - Opcode_wsr_acchi_encode_fns, 0, 0 }, - { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi, - 0, - Opcode_xsr_acchi_encode_fns, 0, 0 }, - - { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, - 0, - Opcode_rsr_memctl_encode_fns, 0, 0 }, - { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, - 0, - Opcode_wsr_memctl_encode_fns, 0, 0 }, - { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, - 0, - Opcode_xsr_memctl_encode_fns, 0, 0 }, - - - { "rsr.mepc", ICLASS_xt_iclass_rsr_mepc, - 0, - Opcode_rsr_mepc_encode_fns, 0, 0 }, - { "wsr.mepc", ICLASS_xt_iclass_wsr_mepc, - 0, - Opcode_wsr_mepc_encode_fns, 0, 0 }, - { "xsr.mepc", ICLASS_xt_iclass_xsr_mepc, - 0, - Opcode_xsr_mepc_encode_fns, 0, 0 }, - - { "rsr.meps", ICLASS_xt_iclass_rsr_meps, - 0, - Opcode_rsr_meps_encode_fns, 0, 0 }, - { "wsr.meps", ICLASS_xt_iclass_wsr_meps, - 0, - Opcode_wsr_meps_encode_fns, 0, 0 }, - { "xsr.meps", ICLASS_xt_iclass_xsr_meps, - 0, - Opcode_xsr_meps_encode_fns, 0, 0 }, - - { "rsr.mesave", ICLASS_xt_iclass_rsr_mesave, - 0, - Opcode_rsr_mesave_encode_fns, 0, 0 }, - { "wsr.mesave", ICLASS_xt_iclass_wsr_mesave, - 0, - Opcode_wsr_mesave_encode_fns, 0, 0 }, - { "xsr.mesave", ICLASS_xt_iclass_xsr_mesave, - 0, - Opcode_xsr_mesave_encode_fns, 0, 0 }, - - { "rsr.mesr", ICLASS_xt_iclass_rsr_mesr, - 0, - Opcode_rsr_mesr_encode_fns, 0, 0 }, - { "wsr.mesr", ICLASS_xt_iclass_wsr_mesr, - 0, - Opcode_wsr_mesr_encode_fns, 0, 0 }, - { "xsr.mesr", ICLASS_xt_iclass_xsr_mesr, - 0, - Opcode_xsr_mesr_encode_fns, 0, 0 }, - - { "rsr.mecr", ICLASS_xt_iclass_rsr_mecr, - 0, - Opcode_rsr_mecr_encode_fns, 0, 0 }, - { "wsr.mecr", ICLASS_xt_iclass_wsr_mecr, - 0, - Opcode_wsr_mecr_encode_fns, 0, 0 }, - { "xsr.mecr", ICLASS_xt_iclass_xsr_mecr, - 0, - Opcode_xsr_mecr_encode_fns, 0, 0 }, - - { "rsr.mevaddr", ICLASS_xt_iclass_rsr_mevaddr, - 0, - Opcode_rsr_mevaddr_encode_fns, 0, 0 }, - { "wsr.mevaddr", ICLASS_xt_iclass_wsr_mevaddr, - 0, - Opcode_wsr_mevaddr_encode_fns, 0, 0 }, - { "xsr.mevaddr", ICLASS_xt_iclass_xsr_mevaddr, - 0, - Opcode_xsr_mevaddr_encode_fns, 0, 0 }, - - { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, - 0, - Opcode_rsr_litbase_encode_fns, 0, 0 }, - { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, - 0, - Opcode_wsr_litbase_encode_fns, 0, 0 }, - { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, - 0, - Opcode_xsr_litbase_encode_fns, 0, 0 }, - { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, - 0, - Opcode_rsr_configid0_encode_fns, 0, 0 }, - { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, - 0, - Opcode_wsr_configid0_encode_fns, 0, 0 }, - { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, - 0, - Opcode_rsr_configid1_encode_fns, 0, 0 }, - { "rsr.243", ICLASS_xt_iclass_rsr_243, - 0, - Opcode_rsr_243_encode_fns, 0, 0 }, - { "rsr.ps", ICLASS_xt_iclass_rsr_ps, - 0, - Opcode_rsr_ps_encode_fns, 0, 0 }, - { "wsr.ps", ICLASS_xt_iclass_wsr_ps, - 0, - Opcode_wsr_ps_encode_fns, 0, 0 }, - { "xsr.ps", ICLASS_xt_iclass_xsr_ps, - 0, - Opcode_xsr_ps_encode_fns, 0, 0 }, - { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, - 0, - Opcode_rsr_epc1_encode_fns, 0, 0 }, - { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, - 0, - Opcode_wsr_epc1_encode_fns, 0, 0 }, - { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, - 0, - Opcode_xsr_epc1_encode_fns, 0, 0 }, - { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, - 0, - Opcode_rsr_excsave1_encode_fns, 0, 0 }, - { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, - 0, - Opcode_wsr_excsave1_encode_fns, 0, 0 }, - { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, - 0, - Opcode_xsr_excsave1_encode_fns, 0, 0 }, - { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, - 0, - Opcode_rsr_epc2_encode_fns, 0, 0 }, - { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, - 0, - Opcode_wsr_epc2_encode_fns, 0, 0 }, - { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, - 0, - Opcode_xsr_epc2_encode_fns, 0, 0 }, - { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, - 0, - Opcode_rsr_excsave2_encode_fns, 0, 0 }, - { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, - 0, - Opcode_wsr_excsave2_encode_fns, 0, 0 }, - { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, - 0, - Opcode_xsr_excsave2_encode_fns, 0, 0 }, - { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, - 0, - Opcode_rsr_epc3_encode_fns, 0, 0 }, - { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, - 0, - Opcode_wsr_epc3_encode_fns, 0, 0 }, - { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, - 0, - Opcode_xsr_epc3_encode_fns, 0, 0 }, - { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, - 0, - Opcode_rsr_excsave3_encode_fns, 0, 0 }, - { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, - 0, - Opcode_wsr_excsave3_encode_fns, 0, 0 }, - { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, - 0, - Opcode_xsr_excsave3_encode_fns, 0, 0 }, - { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, - 0, - Opcode_rsr_epc4_encode_fns, 0, 0 }, - { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, - 0, - Opcode_wsr_epc4_encode_fns, 0, 0 }, - { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, - 0, - Opcode_xsr_epc4_encode_fns, 0, 0 }, - { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, - 0, - Opcode_rsr_excsave4_encode_fns, 0, 0 }, - { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, - 0, - Opcode_wsr_excsave4_encode_fns, 0, 0 }, - { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, - 0, - Opcode_xsr_excsave4_encode_fns, 0, 0 }, - { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, - 0, - Opcode_rsr_epc5_encode_fns, 0, 0 }, - { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, - 0, - Opcode_wsr_epc5_encode_fns, 0, 0 }, - { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, - 0, - Opcode_xsr_epc5_encode_fns, 0, 0 }, - { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, - 0, - Opcode_rsr_excsave5_encode_fns, 0, 0 }, - { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, - 0, - Opcode_wsr_excsave5_encode_fns, 0, 0 }, - { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, - 0, - Opcode_xsr_excsave5_encode_fns, 0, 0 }, - { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, - 0, - Opcode_rsr_epc6_encode_fns, 0, 0 }, - { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, - 0, - Opcode_wsr_epc6_encode_fns, 0, 0 }, - { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, - 0, - Opcode_xsr_epc6_encode_fns, 0, 0 }, - { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, - 0, - Opcode_rsr_excsave6_encode_fns, 0, 0 }, - { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, - 0, - Opcode_wsr_excsave6_encode_fns, 0, 0 }, - { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, - 0, - Opcode_xsr_excsave6_encode_fns, 0, 0 }, - { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, - 0, - Opcode_rsr_epc7_encode_fns, 0, 0 }, - { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, - 0, - Opcode_wsr_epc7_encode_fns, 0, 0 }, - { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, - 0, - Opcode_xsr_epc7_encode_fns, 0, 0 }, - { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, - 0, - Opcode_rsr_excsave7_encode_fns, 0, 0 }, - { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, - 0, - Opcode_wsr_excsave7_encode_fns, 0, 0 }, - { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, - 0, - Opcode_xsr_excsave7_encode_fns, 0, 0 }, - { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, - 0, - Opcode_rsr_eps2_encode_fns, 0, 0 }, - { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, - 0, - Opcode_wsr_eps2_encode_fns, 0, 0 }, - { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, - 0, - Opcode_xsr_eps2_encode_fns, 0, 0 }, - { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, - 0, - Opcode_rsr_eps3_encode_fns, 0, 0 }, - { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, - 0, - Opcode_wsr_eps3_encode_fns, 0, 0 }, - { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, - 0, - Opcode_xsr_eps3_encode_fns, 0, 0 }, - { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, - 0, - Opcode_rsr_eps4_encode_fns, 0, 0 }, - { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, - 0, - Opcode_wsr_eps4_encode_fns, 0, 0 }, - { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, - 0, - Opcode_xsr_eps4_encode_fns, 0, 0 }, - { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, - 0, - Opcode_rsr_eps5_encode_fns, 0, 0 }, - { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, - 0, - Opcode_wsr_eps5_encode_fns, 0, 0 }, - { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, - 0, - Opcode_xsr_eps5_encode_fns, 0, 0 }, - { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, - 0, - Opcode_rsr_eps6_encode_fns, 0, 0 }, - { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, - 0, - Opcode_wsr_eps6_encode_fns, 0, 0 }, - { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, - 0, - Opcode_xsr_eps6_encode_fns, 0, 0 }, - { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, - 0, - Opcode_rsr_eps7_encode_fns, 0, 0 }, - { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, - 0, - Opcode_wsr_eps7_encode_fns, 0, 0 }, - { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, - 0, - Opcode_xsr_eps7_encode_fns, 0, 0 }, - { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, - 0, - Opcode_rsr_excvaddr_encode_fns, 0, 0 }, - { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, - 0, - Opcode_wsr_excvaddr_encode_fns, 0, 0 }, - { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, - 0, - Opcode_xsr_excvaddr_encode_fns, 0, 0 }, - { "rsr.depc", ICLASS_xt_iclass_rsr_depc, - 0, - Opcode_rsr_depc_encode_fns, 0, 0 }, - { "wsr.depc", ICLASS_xt_iclass_wsr_depc, - 0, - Opcode_wsr_depc_encode_fns, 0, 0 }, - { "xsr.depc", ICLASS_xt_iclass_xsr_depc, - 0, - Opcode_xsr_depc_encode_fns, 0, 0 }, - { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, - 0, - Opcode_rsr_exccause_encode_fns, 0, 0 }, - { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, - 0, - Opcode_wsr_exccause_encode_fns, 0, 0 }, - { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, - 0, - Opcode_xsr_exccause_encode_fns, 0, 0 }, - { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, - 0, - Opcode_rsr_misc0_encode_fns, 0, 0 }, - { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, - 0, - Opcode_wsr_misc0_encode_fns, 0, 0 }, - { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, - 0, - Opcode_xsr_misc0_encode_fns, 0, 0 }, - { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, - 0, - Opcode_rsr_misc1_encode_fns, 0, 0 }, - { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, - 0, - Opcode_wsr_misc1_encode_fns, 0, 0 }, - { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, - 0, - Opcode_xsr_misc1_encode_fns, 0, 0 }, - { "rsr.prid", ICLASS_xt_iclass_rsr_prid, - 0, - Opcode_rsr_prid_encode_fns, 0, 0 }, - { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, - 0, - Opcode_rsr_vecbase_encode_fns, 0, 0 }, - { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, - 0, - Opcode_wsr_vecbase_encode_fns, 0, 0 }, - { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, - 0, - Opcode_xsr_vecbase_encode_fns, 0, 0 }, - { "mul16u", ICLASS_xt_mul16, - 0, - Opcode_mul16u_encode_fns, 0, 0 }, - { "mul16s", ICLASS_xt_mul16, - 0, - Opcode_mul16s_encode_fns, 0, 0 }, - { "mull", ICLASS_xt_mul32, - 0, - Opcode_mull_encode_fns, 0, 0 }, - { "rfi", ICLASS_xt_iclass_rfi, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfi_encode_fns, 0, 0 }, - { "waiti", ICLASS_xt_iclass_wait, - 0, - Opcode_waiti_encode_fns, 0, 0 }, - { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, - 0, - Opcode_rsr_interrupt_encode_fns, 0, 0 }, - { "wsr.intset", ICLASS_xt_iclass_wsr_intset, - 0, - Opcode_wsr_intset_encode_fns, 0, 0 }, - { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, - 0, - Opcode_wsr_intclear_encode_fns, 0, 0 }, - { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, - 0, - Opcode_rsr_intenable_encode_fns, 0, 0 }, - { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, - 0, - Opcode_wsr_intenable_encode_fns, 0, 0 }, - { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, - 0, - Opcode_xsr_intenable_encode_fns, 0, 0 }, - { "break", ICLASS_xt_iclass_break, - 0, - Opcode_break_encode_fns, 0, 0 }, - { "break.n", ICLASS_xt_iclass_break_n, - 0, - Opcode_break_n_encode_fns, 0, 0 }, - { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, - 0, - Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, - { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, - 0, - Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, - { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, - 0, - Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, - { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, - 0, - Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, - { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, - 0, - Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, - { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, - 0, - Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, - { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, - 0, - Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, - { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, - 0, - Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, - { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, - 0, - Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, - { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, - 0, - Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, - { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, - 0, - Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, - { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, - 0, - Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, - { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, - 0, - Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, - { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, - 0, - Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, - { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, - 0, - Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, - { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, - 0, - Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, - { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, - 0, - Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, - { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, - 0, - Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, - { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, - 0, - Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, - { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, - 0, - Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, - { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, - 0, - Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, - { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, - 0, - Opcode_rsr_debugcause_encode_fns, 0, 0 }, - { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, - 0, - Opcode_wsr_debugcause_encode_fns, 0, 0 }, - { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, - 0, - Opcode_xsr_debugcause_encode_fns, 0, 0 }, - { "rsr.icount", ICLASS_xt_iclass_rsr_icount, - 0, - Opcode_rsr_icount_encode_fns, 0, 0 }, - { "wsr.icount", ICLASS_xt_iclass_wsr_icount, - 0, - Opcode_wsr_icount_encode_fns, 0, 0 }, - { "xsr.icount", ICLASS_xt_iclass_xsr_icount, - 0, - Opcode_xsr_icount_encode_fns, 0, 0 }, - { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, - 0, - Opcode_rsr_icountlevel_encode_fns, 0, 0 }, - { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, - 0, - Opcode_wsr_icountlevel_encode_fns, 0, 0 }, - { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, - 0, - Opcode_xsr_icountlevel_encode_fns, 0, 0 }, - { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, - 0, - Opcode_rsr_ddr_encode_fns, 0, 0 }, - { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, - 0, - Opcode_wsr_ddr_encode_fns, 0, 0 }, - { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, - 0, - Opcode_xsr_ddr_encode_fns, 0, 0 }, - { "lddr32.p", ICLASS_xt_iclass_lddr32_p, - 0, - Opcode_lddr32_p_encode_fns, 0, 0 }, - { "sddr32.p", ICLASS_xt_iclass_sddr32_p, - 0, - Opcode_sddr32_p_encode_fns, 0, 0 }, - { "rfdo", ICLASS_xt_iclass_rfdo, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdo_encode_fns, 0, 0 }, - { "rfdd", ICLASS_xt_iclass_rfdd, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdd_encode_fns, 0, 0 }, - { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, - 0, - Opcode_wsr_mmid_encode_fns, 0, 0 }, - { "andb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_andb_encode_fns, 0, 0 }, - { "andbc", ICLASS_xt_iclass_bbool1, - 0, - Opcode_andbc_encode_fns, 0, 0 }, - { "orb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_orb_encode_fns, 0, 0 }, - { "orbc", ICLASS_xt_iclass_bbool1, - 0, - Opcode_orbc_encode_fns, 0, 0 }, - { "xorb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_xorb_encode_fns, 0, 0 }, - { "any4", ICLASS_xt_iclass_bbool4, - 0, - Opcode_any4_encode_fns, 0, 0 }, - { "all4", ICLASS_xt_iclass_bbool4, - 0, - Opcode_all4_encode_fns, 0, 0 }, - { "any8", ICLASS_xt_iclass_bbool8, - 0, - Opcode_any8_encode_fns, 0, 0 }, - { "all8", ICLASS_xt_iclass_bbool8, - 0, - Opcode_all8_encode_fns, 0, 0 }, - { "bf", ICLASS_xt_iclass_bbranch, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bf_encode_fns, 0, 0 }, - { "bt", ICLASS_xt_iclass_bbranch, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bt_encode_fns, 0, 0 }, - { "movf", ICLASS_xt_iclass_bmove, - 0, - Opcode_movf_encode_fns, 0, 0 }, - { "movt", ICLASS_xt_iclass_bmove, - 0, - Opcode_movt_encode_fns, 0, 0 }, - { "rsr.br", ICLASS_xt_iclass_RSR_BR, - 0, - Opcode_rsr_br_encode_fns, 0, 0 }, - { "wsr.br", ICLASS_xt_iclass_WSR_BR, - 0, - Opcode_wsr_br_encode_fns, 0, 0 }, - { "xsr.br", ICLASS_xt_iclass_XSR_BR, - 0, - Opcode_xsr_br_encode_fns, 0, 0 }, - { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, - 0, - Opcode_rsr_ccount_encode_fns, 0, 0 }, - { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, - 0, - Opcode_wsr_ccount_encode_fns, 0, 0 }, - { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, - 0, - Opcode_xsr_ccount_encode_fns, 0, 0 }, - { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, - 0, - Opcode_rsr_ccompare0_encode_fns, 0, 0 }, - { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, - 0, - Opcode_wsr_ccompare0_encode_fns, 0, 0 }, - { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, - 0, - Opcode_xsr_ccompare0_encode_fns, 0, 0 }, - { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, - 0, - Opcode_rsr_ccompare1_encode_fns, 0, 0 }, - { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, - 0, - Opcode_wsr_ccompare1_encode_fns, 0, 0 }, - { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, - 0, - Opcode_xsr_ccompare1_encode_fns, 0, 0 }, - { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, - 0, - Opcode_rsr_ccompare2_encode_fns, 0, 0 }, - { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, - 0, - Opcode_wsr_ccompare2_encode_fns, 0, 0 }, - { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, - 0, - Opcode_xsr_ccompare2_encode_fns, 0, 0 }, - { "ipf", ICLASS_xt_iclass_icache, - 0, - Opcode_ipf_encode_fns, 0, 0 }, - { "ihi", ICLASS_xt_iclass_icache, - 0, - Opcode_ihi_encode_fns, 0, 0 }, - { "ipfl", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_ipfl_encode_fns, 0, 0 }, - { "ihu", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_ihu_encode_fns, 0, 0 }, - { "iiu", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_iiu_encode_fns, 0, 0 }, - { "iii", ICLASS_xt_iclass_icache_inv, - 0, - Opcode_iii_encode_fns, 0, 0 }, - { "lict", ICLASS_xt_iclass_licx, - 0, - Opcode_lict_encode_fns, 0, 0 }, - { "licw", ICLASS_xt_iclass_licx, - 0, - Opcode_licw_encode_fns, 0, 0 }, - { "sict", ICLASS_xt_iclass_sicx, - 0, - Opcode_sict_encode_fns, 0, 0 }, - { "sicw", ICLASS_xt_iclass_sicx, - 0, - Opcode_sicw_encode_fns, 0, 0 }, - { "dhwb", ICLASS_xt_iclass_dcache, - 0, - Opcode_dhwb_encode_fns, 0, 0 }, - { "dhwbi", ICLASS_xt_iclass_dcache, - 0, - Opcode_dhwbi_encode_fns, 0, 0 }, - { "diwbui.p", ICLASS_xt_iclass_dcache_dyn, - 0, - Opcode_diwbui_p_encode_fns, 0, 0 }, - { "diwb", ICLASS_xt_iclass_dcache_ind, - 0, - Opcode_diwb_encode_fns, 0, 0 }, - { "diwbi", ICLASS_xt_iclass_dcache_ind, - 0, - Opcode_diwbi_encode_fns, 0, 0 }, - { "dhi", ICLASS_xt_iclass_dcache_inv, - 0, - Opcode_dhi_encode_fns, 0, 0 }, - { "dii", ICLASS_xt_iclass_dcache_inv, - 0, - Opcode_dii_encode_fns, 0, 0 }, - { "dpfr", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfr_encode_fns, 0, 0 }, - { "dpfw", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfw_encode_fns, 0, 0 }, - { "dpfro", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfro_encode_fns, 0, 0 }, - { "dpfwo", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfwo_encode_fns, 0, 0 }, - { "dpfl", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_dpfl_encode_fns, 0, 0 }, - { "dhu", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_dhu_encode_fns, 0, 0 }, - { "diu", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_diu_encode_fns, 0, 0 }, - { "sdct", ICLASS_xt_iclass_sdct, - 0, - Opcode_sdct_encode_fns, 0, 0 }, - { "ldct", ICLASS_xt_iclass_ldct, - 0, - Opcode_ldct_encode_fns, 0, 0 }, - { "rsr.prefctl", ICLASS_xt_iclass_rsr_prefctl, - 0, - Opcode_rsr_prefctl_encode_fns, 0, 0 }, - { "wsr.prefctl", ICLASS_xt_iclass_wsr_prefctl, - 0, - Opcode_wsr_prefctl_encode_fns, 0, 0 }, - { "xsr.prefctl", ICLASS_xt_iclass_xsr_prefctl, - 0, - Opcode_xsr_prefctl_encode_fns, 0, 0 }, - { "idtlb", ICLASS_xt_iclass_idtlb, - 0, - Opcode_idtlb_encode_fns, 0, 0 }, - { "pdtlb", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_pdtlb_encode_fns, 0, 0 }, - { "rdtlb0", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb0_encode_fns, 0, 0 }, - { "rdtlb1", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb1_encode_fns, 0, 0 }, - { "wdtlb", ICLASS_xt_iclass_wdtlb, - 0, - Opcode_wdtlb_encode_fns, 0, 0 }, - { "iitlb", ICLASS_xt_iclass_iitlb, - 0, - Opcode_iitlb_encode_fns, 0, 0 }, - { "pitlb", ICLASS_xt_iclass_ritlb, - 0, - Opcode_pitlb_encode_fns, 0, 0 }, - { "ritlb0", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb0_encode_fns, 0, 0 }, - { "ritlb1", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb1_encode_fns, 0, 0 }, - { "witlb", ICLASS_xt_iclass_witlb, - 0, - Opcode_witlb_encode_fns, 0, 0 }, - { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, - 0, - Opcode_rsr_cpenable_encode_fns, 0, 0 }, - { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, - 0, - Opcode_wsr_cpenable_encode_fns, 0, 0 }, - { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, - 0, - Opcode_xsr_cpenable_encode_fns, 0, 0 }, - { "clamps", ICLASS_xt_iclass_clamp, - 0, - Opcode_clamps_encode_fns, 0, 0 }, - { "min", ICLASS_xt_iclass_minmax, - 0, - Opcode_min_encode_fns, 0, 0 }, - { "max", ICLASS_xt_iclass_minmax, - 0, - Opcode_max_encode_fns, 0, 0 }, - { "minu", ICLASS_xt_iclass_minmax, - 0, - Opcode_minu_encode_fns, 0, 0 }, - { "maxu", ICLASS_xt_iclass_minmax, - 0, - Opcode_maxu_encode_fns, 0, 0 }, - { "nsa", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsa_encode_fns, 0, 0 }, - { "nsau", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsau_encode_fns, 0, 0 }, - { "sext", ICLASS_xt_iclass_sx, - 0, - Opcode_sext_encode_fns, 0, 0 }, - { "l32ai", ICLASS_xt_iclass_l32ai, - 0, - Opcode_l32ai_encode_fns, 0, 0 }, - { "s32ri", ICLASS_xt_iclass_s32ri, - 0, - Opcode_s32ri_encode_fns, 0, 0 }, - { "s32c1i", ICLASS_xt_iclass_s32c1i, - 0, - Opcode_s32c1i_encode_fns, 0, 0 }, - { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, - 0, - Opcode_rsr_scompare1_encode_fns, 0, 0 }, - { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, - 0, - Opcode_wsr_scompare1_encode_fns, 0, 0 }, - { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, - 0, - Opcode_xsr_scompare1_encode_fns, 0, 0 }, - { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, - 0, - Opcode_rsr_atomctl_encode_fns, 0, 0 }, - { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, - 0, - Opcode_wsr_atomctl_encode_fns, 0, 0 }, - { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, - 0, - Opcode_xsr_atomctl_encode_fns, 0, 0 }, - { "quou", ICLASS_xt_iclass_div, - 0, - Opcode_quou_encode_fns, 0, 0 }, - { "quos", ICLASS_xt_iclass_div, - 0, - Opcode_quos_encode_fns, 0, 0 }, - { "remu", ICLASS_xt_iclass_div, - 0, - Opcode_remu_encode_fns, 0, 0 }, - { "rems", ICLASS_xt_iclass_div, - 0, - Opcode_rems_encode_fns, 0, 0 }, - { "rer", ICLASS_xt_iclass_rer, - 0, - Opcode_rer_encode_fns, 0, 0 }, - { "wer", ICLASS_xt_iclass_wer, - 0, - Opcode_wer_encode_fns, 0, 0 }, - { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar, - 0, - Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 }, - { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar, - 0, - Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 }, - { "rur.ae_bithead", ICLASS_rur_ae_bithead, - 0, - Opcode_rur_ae_bithead_encode_fns, 0, 0 }, - { "wur.ae_bithead", ICLASS_wur_ae_bithead, - 0, - Opcode_wur_ae_bithead_encode_fns, 0, 0 }, - { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp, - 0, - Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, - { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp, - 0, - Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, - { "rur.ae_sd_no", ICLASS_rur_ae_sd_no, - 0, - Opcode_rur_ae_sd_no_encode_fns, 0, 0 }, - { "wur.ae_sd_no", ICLASS_wur_ae_sd_no, - 0, - Opcode_wur_ae_sd_no_encode_fns, 0, 0 }, - { "rur.ae_overflow", ICLASS_ae_iclass_rur_ae_overflow, - 0, - Opcode_rur_ae_overflow_encode_fns, 0, 0 }, - { "wur.ae_overflow", ICLASS_ae_iclass_wur_ae_overflow, - 0, - Opcode_wur_ae_overflow_encode_fns, 0, 0 }, - { "rur.ae_sar", ICLASS_ae_iclass_rur_ae_sar, - 0, - Opcode_rur_ae_sar_encode_fns, 0, 0 }, - { "wur.ae_sar", ICLASS_ae_iclass_wur_ae_sar, - 0, - Opcode_wur_ae_sar_encode_fns, 0, 0 }, - { "rur.ae_bitptr", ICLASS_ae_iclass_rur_ae_bitptr, - 0, - Opcode_rur_ae_bitptr_encode_fns, 0, 0 }, - { "wur.ae_bitptr", ICLASS_ae_iclass_wur_ae_bitptr, - 0, - Opcode_wur_ae_bitptr_encode_fns, 0, 0 }, - { "rur.ae_bitsused", ICLASS_ae_iclass_rur_ae_bitsused, - 0, - Opcode_rur_ae_bitsused_encode_fns, 0, 0 }, - { "wur.ae_bitsused", ICLASS_ae_iclass_wur_ae_bitsused, - 0, - Opcode_wur_ae_bitsused_encode_fns, 0, 0 }, - { "rur.ae_tablesize", ICLASS_ae_iclass_rur_ae_tablesize, - 0, - Opcode_rur_ae_tablesize_encode_fns, 0, 0 }, - { "wur.ae_tablesize", ICLASS_ae_iclass_wur_ae_tablesize, - 0, - Opcode_wur_ae_tablesize_encode_fns, 0, 0 }, - { "rur.ae_first_ts", ICLASS_ae_iclass_rur_ae_first_ts, - 0, - Opcode_rur_ae_first_ts_encode_fns, 0, 0 }, - { "wur.ae_first_ts", ICLASS_ae_iclass_wur_ae_first_ts, - 0, - Opcode_wur_ae_first_ts_encode_fns, 0, 0 }, - { "rur.ae_nextoffset", ICLASS_ae_iclass_rur_ae_nextoffset, - 0, - Opcode_rur_ae_nextoffset_encode_fns, 0, 0 }, - { "wur.ae_nextoffset", ICLASS_ae_iclass_wur_ae_nextoffset, - 0, - Opcode_wur_ae_nextoffset_encode_fns, 0, 0 }, - { "rur.ae_searchdone", ICLASS_ae_iclass_rur_ae_searchdone, - 0, - Opcode_rur_ae_searchdone_encode_fns, 0, 0 }, - { "wur.ae_searchdone", ICLASS_ae_iclass_wur_ae_searchdone, - 0, - Opcode_wur_ae_searchdone_encode_fns, 0, 0 }, - { "rur.threadptr", ICLASS_iclass_rur_threadptr, - 0, - Opcode_rur_threadptr_encode_fns, 0, 0 }, - { "wur.threadptr", ICLASS_iclass_wur_threadptr, - 0, - Opcode_wur_threadptr_encode_fns, 0, 0 }, - { "ae_lp16f.i", ICLASS_ae_iclass_lp16f_i, - 0, - Opcode_ae_lp16f_i_encode_fns, 0, 0 }, - { "ae_lp16f.iu", ICLASS_ae_iclass_lp16f_iu, - 0, - Opcode_ae_lp16f_iu_encode_fns, 0, 0 }, - { "ae_lp16f.x", ICLASS_ae_iclass_lp16f_x, - 0, - Opcode_ae_lp16f_x_encode_fns, 0, 0 }, - { "ae_lp16f.xu", ICLASS_ae_iclass_lp16f_xu, - 0, - Opcode_ae_lp16f_xu_encode_fns, 0, 0 }, - { "ae_lp24.i", ICLASS_ae_iclass_lp24_i, - 0, - Opcode_ae_lp24_i_encode_fns, 0, 0 }, - { "ae_lp24.iu", ICLASS_ae_iclass_lp24_iu, - 0, - Opcode_ae_lp24_iu_encode_fns, 0, 0 }, - { "ae_lp24.x", ICLASS_ae_iclass_lp24_x, - 0, - Opcode_ae_lp24_x_encode_fns, 0, 0 }, - { "ae_lp24.xu", ICLASS_ae_iclass_lp24_xu, - 0, - Opcode_ae_lp24_xu_encode_fns, 0, 0 }, - { "ae_lp24f.i", ICLASS_ae_iclass_lp24f_i, - 0, - Opcode_ae_lp24f_i_encode_fns, 0, 0 }, - { "ae_lp24f.iu", ICLASS_ae_iclass_lp24f_iu, - 0, - Opcode_ae_lp24f_iu_encode_fns, 0, 0 }, - { "ae_lp24f.x", ICLASS_ae_iclass_lp24f_x, - 0, - Opcode_ae_lp24f_x_encode_fns, 0, 0 }, - { "ae_lp24f.xu", ICLASS_ae_iclass_lp24f_xu, - 0, - Opcode_ae_lp24f_xu_encode_fns, 0, 0 }, - { "ae_lp16x2f.i", ICLASS_ae_iclass_lp16x2f_i, - 0, - Opcode_ae_lp16x2f_i_encode_fns, 0, 0 }, - { "ae_lp16x2f.iu", ICLASS_ae_iclass_lp16x2f_iu, - 0, - Opcode_ae_lp16x2f_iu_encode_fns, 0, 0 }, - { "ae_lp16x2f.x", ICLASS_ae_iclass_lp16x2f_x, - 0, - Opcode_ae_lp16x2f_x_encode_fns, 0, 0 }, - { "ae_lp16x2f.xu", ICLASS_ae_iclass_lp16x2f_xu, - 0, - Opcode_ae_lp16x2f_xu_encode_fns, 0, 0 }, - { "ae_lp24x2f.i", ICLASS_ae_iclass_lp24x2f_i, - 0, - Opcode_ae_lp24x2f_i_encode_fns, 0, 0 }, - { "ae_lp24x2f.iu", ICLASS_ae_iclass_lp24x2f_iu, - 0, - Opcode_ae_lp24x2f_iu_encode_fns, 0, 0 }, - { "ae_lp24x2f.x", ICLASS_ae_iclass_lp24x2f_x, - 0, - Opcode_ae_lp24x2f_x_encode_fns, 0, 0 }, - { "ae_lp24x2f.xu", ICLASS_ae_iclass_lp24x2f_xu, - 0, - Opcode_ae_lp24x2f_xu_encode_fns, 0, 0 }, - { "ae_lp24x2.i", ICLASS_ae_iclass_lp24x2_i, - 0, - Opcode_ae_lp24x2_i_encode_fns, 0, 0 }, - { "ae_lp24x2.iu", ICLASS_ae_iclass_lp24x2_iu, - 0, - Opcode_ae_lp24x2_iu_encode_fns, 0, 0 }, - { "ae_lp24x2.x", ICLASS_ae_iclass_lp24x2_x, - 0, - Opcode_ae_lp24x2_x_encode_fns, 0, 0 }, - { "ae_lp24x2.xu", ICLASS_ae_iclass_lp24x2_xu, - 0, - Opcode_ae_lp24x2_xu_encode_fns, 0, 0 }, - { "ae_sp16x2f.i", ICLASS_ae_iclass_sp16x2f_i, - 0, - Opcode_ae_sp16x2f_i_encode_fns, 0, 0 }, - { "ae_sp16x2f.iu", ICLASS_ae_iclass_sp16x2f_iu, - 0, - Opcode_ae_sp16x2f_iu_encode_fns, 0, 0 }, - { "ae_sp16x2f.x", ICLASS_ae_iclass_sp16x2f_x, - 0, - Opcode_ae_sp16x2f_x_encode_fns, 0, 0 }, - { "ae_sp16x2f.xu", ICLASS_ae_iclass_sp16x2f_xu, - 0, - Opcode_ae_sp16x2f_xu_encode_fns, 0, 0 }, - { "ae_sp24x2s.i", ICLASS_ae_iclass_sp24x2s_i, - 0, - Opcode_ae_sp24x2s_i_encode_fns, 0, 0 }, - { "ae_sp24x2s.iu", ICLASS_ae_iclass_sp24x2s_iu, - 0, - Opcode_ae_sp24x2s_iu_encode_fns, 0, 0 }, - { "ae_sp24x2s.x", ICLASS_ae_iclass_sp24x2s_x, - 0, - Opcode_ae_sp24x2s_x_encode_fns, 0, 0 }, - { "ae_sp24x2s.xu", ICLASS_ae_iclass_sp24x2s_xu, - 0, - Opcode_ae_sp24x2s_xu_encode_fns, 0, 0 }, - { "ae_sp24x2f.i", ICLASS_ae_iclass_sp24x2f_i, - 0, - Opcode_ae_sp24x2f_i_encode_fns, 0, 0 }, - { "ae_sp24x2f.iu", ICLASS_ae_iclass_sp24x2f_iu, - 0, - Opcode_ae_sp24x2f_iu_encode_fns, 0, 0 }, - { "ae_sp24x2f.x", ICLASS_ae_iclass_sp24x2f_x, - 0, - Opcode_ae_sp24x2f_x_encode_fns, 0, 0 }, - { "ae_sp24x2f.xu", ICLASS_ae_iclass_sp24x2f_xu, - 0, - Opcode_ae_sp24x2f_xu_encode_fns, 0, 0 }, - { "ae_sp16f.l.i", ICLASS_ae_iclass_sp16f_l_i, - 0, - Opcode_ae_sp16f_l_i_encode_fns, 0, 0 }, - { "ae_sp16f.l.iu", ICLASS_ae_iclass_sp16f_l_iu, - 0, - Opcode_ae_sp16f_l_iu_encode_fns, 0, 0 }, - { "ae_sp16f.l.x", ICLASS_ae_iclass_sp16f_l_x, - 0, - Opcode_ae_sp16f_l_x_encode_fns, 0, 0 }, - { "ae_sp16f.l.xu", ICLASS_ae_iclass_sp16f_l_xu, - 0, - Opcode_ae_sp16f_l_xu_encode_fns, 0, 0 }, - { "ae_sp24s.l.i", ICLASS_ae_iclass_sp24s_l_i, - 0, - Opcode_ae_sp24s_l_i_encode_fns, 0, 0 }, - { "ae_sp24s.l.iu", ICLASS_ae_iclass_sp24s_l_iu, - 0, - Opcode_ae_sp24s_l_iu_encode_fns, 0, 0 }, - { "ae_sp24s.l.x", ICLASS_ae_iclass_sp24s_l_x, - 0, - Opcode_ae_sp24s_l_x_encode_fns, 0, 0 }, - { "ae_sp24s.l.xu", ICLASS_ae_iclass_sp24s_l_xu, - 0, - Opcode_ae_sp24s_l_xu_encode_fns, 0, 0 }, - { "ae_sp24f.l.i", ICLASS_ae_iclass_sp24f_l_i, - 0, - Opcode_ae_sp24f_l_i_encode_fns, 0, 0 }, - { "ae_sp24f.l.iu", ICLASS_ae_iclass_sp24f_l_iu, - 0, - Opcode_ae_sp24f_l_iu_encode_fns, 0, 0 }, - { "ae_sp24f.l.x", ICLASS_ae_iclass_sp24f_l_x, - 0, - Opcode_ae_sp24f_l_x_encode_fns, 0, 0 }, - { "ae_sp24f.l.xu", ICLASS_ae_iclass_sp24f_l_xu, - 0, - Opcode_ae_sp24f_l_xu_encode_fns, 0, 0 }, - { "ae_lq56.i", ICLASS_ae_iclass_lq56_i, - 0, - Opcode_ae_lq56_i_encode_fns, 0, 0 }, - { "ae_lq56.iu", ICLASS_ae_iclass_lq56_iu, - 0, - Opcode_ae_lq56_iu_encode_fns, 0, 0 }, - { "ae_lq56.x", ICLASS_ae_iclass_lq56_x, - 0, - Opcode_ae_lq56_x_encode_fns, 0, 0 }, - { "ae_lq56.xu", ICLASS_ae_iclass_lq56_xu, - 0, - Opcode_ae_lq56_xu_encode_fns, 0, 0 }, - { "ae_lq32f.i", ICLASS_ae_iclass_lq32f_i, - 0, - Opcode_ae_lq32f_i_encode_fns, 0, 0 }, - { "ae_lq32f.iu", ICLASS_ae_iclass_lq32f_iu, - 0, - Opcode_ae_lq32f_iu_encode_fns, 0, 0 }, - { "ae_lq32f.x", ICLASS_ae_iclass_lq32f_x, - 0, - Opcode_ae_lq32f_x_encode_fns, 0, 0 }, - { "ae_lq32f.xu", ICLASS_ae_iclass_lq32f_xu, - 0, - Opcode_ae_lq32f_xu_encode_fns, 0, 0 }, - { "ae_sq56s.i", ICLASS_ae_iclass_sq56s_i, - 0, - Opcode_ae_sq56s_i_encode_fns, 0, 0 }, - { "ae_sq56s.iu", ICLASS_ae_iclass_sq56s_iu, - 0, - Opcode_ae_sq56s_iu_encode_fns, 0, 0 }, - { "ae_sq56s.x", ICLASS_ae_iclass_sq56s_x, - 0, - Opcode_ae_sq56s_x_encode_fns, 0, 0 }, - { "ae_sq56s.xu", ICLASS_ae_iclass_sq56s_xu, - 0, - Opcode_ae_sq56s_xu_encode_fns, 0, 0 }, - { "ae_sq32f.i", ICLASS_ae_iclass_sq32f_i, - 0, - Opcode_ae_sq32f_i_encode_fns, 0, 0 }, - { "ae_sq32f.iu", ICLASS_ae_iclass_sq32f_iu, - 0, - Opcode_ae_sq32f_iu_encode_fns, 0, 0 }, - { "ae_sq32f.x", ICLASS_ae_iclass_sq32f_x, - 0, - Opcode_ae_sq32f_x_encode_fns, 0, 0 }, - { "ae_sq32f.xu", ICLASS_ae_iclass_sq32f_xu, - 0, - Opcode_ae_sq32f_xu_encode_fns, 0, 0 }, - { "ae_zerop48", ICLASS_ae_iclass_zerop48, - 0, - Opcode_ae_zerop48_encode_fns, 0, 0 }, - { "ae_movp48", ICLASS_ae_iclass_movp48, - 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0, - Opcode_ae_mulzssq32sp16u_ll_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16u.ll", ICLASS_ae_iclass_mulzssfq32sp16u_ll, - 0, - Opcode_ae_mulzssfq32sp16u_ll_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16s.hh", ICLASS_ae_iclass_mulzssq32sp16s_hh, - 0, - Opcode_ae_mulzssq32sp16s_hh_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16s.hh", ICLASS_ae_iclass_mulzssfq32sp16s_hh, - 0, - Opcode_ae_mulzssfq32sp16s_hh_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16u.hh", ICLASS_ae_iclass_mulzssq32sp16u_hh, - 0, - Opcode_ae_mulzssq32sp16u_hh_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16u.hh", ICLASS_ae_iclass_mulzssfq32sp16u_hh, - 0, - Opcode_ae_mulzssfq32sp16u_hh_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16s.lh", ICLASS_ae_iclass_mulzssq32sp16s_lh, - 0, - Opcode_ae_mulzssq32sp16s_lh_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16s.lh", ICLASS_ae_iclass_mulzssfq32sp16s_lh, - 0, - Opcode_ae_mulzssfq32sp16s_lh_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16u.lh", ICLASS_ae_iclass_mulzssq32sp16u_lh, - 0, - Opcode_ae_mulzssq32sp16u_lh_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16u.lh", ICLASS_ae_iclass_mulzssfq32sp16u_lh, - 0, - Opcode_ae_mulzssfq32sp16u_lh_encode_fns, 0, 0 }, - { "ae_mulzaafp24s.hh.ll", ICLASS_ae_iclass_mulzaafp24s_hh_ll, - 0, - Opcode_ae_mulzaafp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzaap24s.hh.ll", ICLASS_ae_iclass_mulzaap24s_hh_ll, - 0, - Opcode_ae_mulzaap24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzaafp24s.hl.lh", ICLASS_ae_iclass_mulzaafp24s_hl_lh, - 0, - Opcode_ae_mulzaafp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzaap24s.hl.lh", ICLASS_ae_iclass_mulzaap24s_hl_lh, - 0, - Opcode_ae_mulzaap24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzasfp24s.hh.ll", ICLASS_ae_iclass_mulzasfp24s_hh_ll, - 0, - Opcode_ae_mulzasfp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzasp24s.hh.ll", ICLASS_ae_iclass_mulzasp24s_hh_ll, - 0, - Opcode_ae_mulzasp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzasfp24s.hl.lh", ICLASS_ae_iclass_mulzasfp24s_hl_lh, - 0, - Opcode_ae_mulzasfp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzasp24s.hl.lh", ICLASS_ae_iclass_mulzasp24s_hl_lh, - 0, - Opcode_ae_mulzasp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzsafp24s.hh.ll", ICLASS_ae_iclass_mulzsafp24s_hh_ll, - 0, - Opcode_ae_mulzsafp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzsap24s.hh.ll", ICLASS_ae_iclass_mulzsap24s_hh_ll, - 0, - Opcode_ae_mulzsap24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzsafp24s.hl.lh", ICLASS_ae_iclass_mulzsafp24s_hl_lh, - 0, - Opcode_ae_mulzsafp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzsap24s.hl.lh", ICLASS_ae_iclass_mulzsap24s_hl_lh, - 0, - Opcode_ae_mulzsap24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzssfp24s.hh.ll", ICLASS_ae_iclass_mulzssfp24s_hh_ll, - 0, - Opcode_ae_mulzssfp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzssp24s.hh.ll", ICLASS_ae_iclass_mulzssp24s_hh_ll, - 0, - Opcode_ae_mulzssp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzssfp24s.hl.lh", ICLASS_ae_iclass_mulzssfp24s_hl_lh, - 0, - Opcode_ae_mulzssfp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzssp24s.hl.lh", ICLASS_ae_iclass_mulzssp24s_hl_lh, - 0, - Opcode_ae_mulzssp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulaafp24s.hh.ll", ICLASS_ae_iclass_mulaafp24s_hh_ll, - 0, - Opcode_ae_mulaafp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulaap24s.hh.ll", ICLASS_ae_iclass_mulaap24s_hh_ll, - 0, - Opcode_ae_mulaap24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulaafp24s.hl.lh", ICLASS_ae_iclass_mulaafp24s_hl_lh, - 0, - Opcode_ae_mulaafp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulaap24s.hl.lh", ICLASS_ae_iclass_mulaap24s_hl_lh, - 0, - Opcode_ae_mulaap24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulasfp24s.hh.ll", ICLASS_ae_iclass_mulasfp24s_hh_ll, - 0, - Opcode_ae_mulasfp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulasp24s.hh.ll", ICLASS_ae_iclass_mulasp24s_hh_ll, - 0, - Opcode_ae_mulasp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulasfp24s.hl.lh", ICLASS_ae_iclass_mulasfp24s_hl_lh, - 0, - Opcode_ae_mulasfp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulasp24s.hl.lh", ICLASS_ae_iclass_mulasp24s_hl_lh, - 0, - Opcode_ae_mulasp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulsafp24s.hh.ll", ICLASS_ae_iclass_mulsafp24s_hh_ll, - 0, - Opcode_ae_mulsafp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulsap24s.hh.ll", ICLASS_ae_iclass_mulsap24s_hh_ll, - 0, - Opcode_ae_mulsap24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulsafp24s.hl.lh", ICLASS_ae_iclass_mulsafp24s_hl_lh, - 0, - Opcode_ae_mulsafp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulsap24s.hl.lh", ICLASS_ae_iclass_mulsap24s_hl_lh, - 0, - Opcode_ae_mulsap24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulssfp24s.hh.ll", ICLASS_ae_iclass_mulssfp24s_hh_ll, - 0, - Opcode_ae_mulssfp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulssp24s.hh.ll", ICLASS_ae_iclass_mulssp24s_hh_ll, - 0, - Opcode_ae_mulssp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulssfp24s.hl.lh", ICLASS_ae_iclass_mulssfp24s_hl_lh, - 0, - Opcode_ae_mulssfp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulssp24s.hl.lh", ICLASS_ae_iclass_mulssp24s_hl_lh, - 0, - Opcode_ae_mulssp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_sha32", ICLASS_ae_iclass_sha32, - 0, - Opcode_ae_sha32_encode_fns, 0, 0 }, - { "ae_vldl32t", ICLASS_ae_iclass_vldl32t, - 0, - Opcode_ae_vldl32t_encode_fns, 1, Opcode_ae_vldl32t_funcUnit_uses }, - { "ae_vldl16t", ICLASS_ae_iclass_vldl16t, - 0, - Opcode_ae_vldl16t_encode_fns, 1, Opcode_ae_vldl16t_funcUnit_uses }, - { "ae_vldl16c", ICLASS_ae_iclass_vldl16c, - 0, - Opcode_ae_vldl16c_encode_fns, 3, Opcode_ae_vldl16c_funcUnit_uses }, - { "ae_vldsht", ICLASS_ae_iclass_vldsht, - 0, - Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses }, - { "ae_lb", ICLASS_ae_iclass_lb, - 0, - Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses }, - { "ae_lbi", ICLASS_ae_iclass_lbi, - 0, - Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses }, - { "ae_lbk", ICLASS_ae_iclass_lbk, - 0, - Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses }, - { "ae_lbki", ICLASS_ae_iclass_lbki, - 0, - Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses }, - { "ae_db", ICLASS_ae_iclass_db, - 0, - Opcode_ae_db_encode_fns, 2, Opcode_ae_db_funcUnit_uses }, - { "ae_dbi", ICLASS_ae_iclass_dbi, - 0, - Opcode_ae_dbi_encode_fns, 2, Opcode_ae_dbi_funcUnit_uses }, - { "ae_vlel32t", ICLASS_ae_iclass_vlel32t, - 0, - Opcode_ae_vlel32t_encode_fns, 1, Opcode_ae_vlel32t_funcUnit_uses }, - { "ae_vlel16t", ICLASS_ae_iclass_vlel16t, - 0, - Opcode_ae_vlel16t_encode_fns, 1, Opcode_ae_vlel16t_funcUnit_uses }, - { "ae_sb", ICLASS_ae_iclass_sb, - 0, - Opcode_ae_sb_encode_fns, 2, Opcode_ae_sb_funcUnit_uses }, - { "ae_sbi", ICLASS_ae_iclass_sbi, - 0, - Opcode_ae_sbi_encode_fns, 2, Opcode_ae_sbi_funcUnit_uses }, - { "ae_vles16c", ICLASS_ae_iclass_vles16c, - 0, - Opcode_ae_vles16c_encode_fns, 2, Opcode_ae_vles16c_funcUnit_uses }, - { "ae_sbf", ICLASS_ae_iclass_sbf, - 0, - Opcode_ae_sbf_encode_fns, 2, Opcode_ae_sbf_funcUnit_uses }, - { "ae_slaasq56s", ICLASS_icls_AE_SLAASQ56S, - 0, - Opcode_ae_slaasq56s_encode_fns, 0, 0 }, - { "ae_addbrba32", ICLASS_icls_AE_ADDBRBA32, - 0, - Opcode_ae_addbrba32_encode_fns, 0, 0 }, - { "ae_minabssp24s", ICLASS_icls_AE_MINABSSP24S, - 0, - Opcode_ae_minabssp24s_encode_fns, 0, 0 }, - { "ae_maxabssp24s", ICLASS_icls_AE_MAXABSSP24S, - 0, - Opcode_ae_maxabssp24s_encode_fns, 0, 0 }, - { "ae_minabssq56s", ICLASS_icls_AE_MINABSSQ56S, - 0, - Opcode_ae_minabssq56s_encode_fns, 0, 0 }, - { "ae_maxabssq56s", ICLASS_icls_AE_MAXABSSQ56S, - 0, - Opcode_ae_maxabssq56s_encode_fns, 0, 0 }, - { "rur.ae_cbegin0", ICLASS_rur_ae_cbegin0, - 0, - Opcode_rur_ae_cbegin0_encode_fns, 0, 0 }, - { "wur.ae_cbegin0", ICLASS_wur_ae_cbegin0, - 0, - Opcode_wur_ae_cbegin0_encode_fns, 0, 0 }, - { "rur.ae_cend0", ICLASS_rur_ae_cend0, - 0, - Opcode_rur_ae_cend0_encode_fns, 0, 0 }, - { "wur.ae_cend0", ICLASS_wur_ae_cend0, - 0, - Opcode_wur_ae_cend0_encode_fns, 0, 0 }, - { "ae_lp24x2.c", ICLASS_icls_AE_LP24X2_C, - 0, - Opcode_ae_lp24x2_c_encode_fns, 0, 0 }, - { "ae_sp24x2s.c", ICLASS_icls_AE_SP24X2S_C, - 0, - Opcode_ae_sp24x2s_c_encode_fns, 0, 0 }, - { "ae_lp24x2f.c", ICLASS_icls_AE_LP24X2F_C, - 0, - Opcode_ae_lp24x2f_c_encode_fns, 0, 0 }, - { "ae_sp24x2f.c", ICLASS_icls_AE_SP24X2F_C, - 0, - Opcode_ae_sp24x2f_c_encode_fns, 0, 0 }, - { "ae_lp16x2f.c", ICLASS_icls_AE_LP16X2F_C, - 0, - Opcode_ae_lp16x2f_c_encode_fns, 0, 0 }, - { "ae_sp16x2f.c", ICLASS_icls_AE_SP16X2F_C, - 0, - Opcode_ae_sp16x2f_c_encode_fns, 0, 0 }, - { "ae_lp24.c", ICLASS_icls_AE_LP24_C, - 0, - Opcode_ae_lp24_c_encode_fns, 0, 0 }, - { "ae_sp24s.l.c", ICLASS_icls_AE_SP24S_L_C, - 0, - Opcode_ae_sp24s_l_c_encode_fns, 0, 0 }, - { "ae_lp24f.c", ICLASS_icls_AE_LP24F_C, - 0, - Opcode_ae_lp24f_c_encode_fns, 0, 0 }, - { "ae_sp24f.l.c", ICLASS_icls_AE_SP24F_L_C, - 0, - Opcode_ae_sp24f_l_c_encode_fns, 0, 0 }, - { "ae_lp16f.c", ICLASS_icls_AE_LP16F_C, - 0, - Opcode_ae_lp16f_c_encode_fns, 0, 0 }, - { "ae_sp16f.l.c", ICLASS_icls_AE_SP16F_L_C, - 0, - Opcode_ae_sp16f_l_c_encode_fns, 0, 0 }, - { "ae_lq56.c", ICLASS_icls_AE_LQ56_C, - 0, - Opcode_ae_lq56_c_encode_fns, 0, 0 }, - { "ae_sq56s.c", ICLASS_icls_AE_SQ56S_C, - 0, - Opcode_ae_sq56s_c_encode_fns, 0, 0 }, - { "ae_lq32f.c", ICLASS_icls_AE_LQ32F_C, - 0, - Opcode_ae_lq32f_c_encode_fns, 0, 0 }, - { "ae_sq32f.c", ICLASS_icls_AE_SQ32F_C, - 0, - Opcode_ae_sq32f_c_encode_fns, 0, 0 }, - { "read_ipq", ICLASS_iclass_READ_IPQ, - 0, - Opcode_read_ipq_encode_fns, 0, 0 }, - { "check_ipq", ICLASS_iclass_CHECK_IPQ, - 0, - Opcode_check_ipq_encode_fns, 0, 0 }, - { "write_opq", ICLASS_iclass_WRITE_OPQ, - 0, - Opcode_write_opq_encode_fns, 0, 0 }, - { "check_opq", ICLASS_iclass_CHECK_OPQ, - 0, - Opcode_check_opq_encode_fns, 0, 0 }, - { "rur.expstate", ICLASS_rur_expstate, - 0, - Opcode_rur_expstate_encode_fns, 0, 0 }, - { "wur.expstate", ICLASS_wur_expstate, - 0, - Opcode_wur_expstate_encode_fns, 0, 0 }, - { "read_impwire", ICLASS_iclass_READ_IMPWIRE, - 0, - Opcode_read_impwire_encode_fns, 0, 0 }, - { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, - 0, - Opcode_setb_expstate_encode_fns, 0, 0 }, - { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, - 0, - Opcode_clrb_expstate_encode_fns, 0, 0 }, - { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, - 0, - Opcode_wrmsk_expstate_encode_fns, 0, 0 } -}; - -enum xtensa_opcode_id { - OPCODE_EXCW, - OPCODE_RFE, - OPCODE_RFME, - OPCODE_RFDE, - OPCODE_SYSCALL, - OPCODE_CALL12, - OPCODE_CALL8, - OPCODE_CALL4, - OPCODE_CALLX12, - OPCODE_CALLX8, - OPCODE_CALLX4, - OPCODE_ENTRY, - OPCODE_MOVSP, - OPCODE_ROTW, - OPCODE_RETW, - OPCODE_RETW_N, - OPCODE_RFWO, - OPCODE_RFWU, - OPCODE_L32E, - OPCODE_S32E, - OPCODE_RSR_WINDOWBASE, - OPCODE_WSR_WINDOWBASE, - OPCODE_XSR_WINDOWBASE, - OPCODE_RSR_WINDOWSTART, - OPCODE_WSR_WINDOWSTART, - OPCODE_XSR_WINDOWSTART, - OPCODE_ADD_N, - OPCODE_ADDI_N, - OPCODE_BEQZ_N, - OPCODE_BNEZ_N, - OPCODE_ILL_N, - OPCODE_L32I_N, - OPCODE_MOV_N, - OPCODE_MOVI_N, - OPCODE_NOP_N, - OPCODE_RET_N, - OPCODE_S32I_N, - OPCODE_ADDI, - OPCODE_ADDMI, - OPCODE_ADD, - OPCODE_SUB, - OPCODE_ADDX2, - OPCODE_ADDX4, - OPCODE_ADDX8, - OPCODE_SUBX2, - OPCODE_SUBX4, - OPCODE_SUBX8, - OPCODE_AND, - OPCODE_OR, - OPCODE_XOR, - OPCODE_BEQI, - OPCODE_BNEI, - OPCODE_BGEI, - OPCODE_BLTI, - OPCODE_BBCI, - OPCODE_BBSI, - OPCODE_BGEUI, - OPCODE_BLTUI, - OPCODE_BEQ, - OPCODE_BNE, - OPCODE_BGE, - OPCODE_BLT, - OPCODE_BGEU, - OPCODE_BLTU, - OPCODE_BANY, - OPCODE_BNONE, - OPCODE_BALL, - OPCODE_BNALL, - OPCODE_BBC, - OPCODE_BBS, - OPCODE_BEQZ, - OPCODE_BNEZ, - OPCODE_BGEZ, - OPCODE_BLTZ, - OPCODE_CALL0, - OPCODE_CALLX0, - OPCODE_EXTUI, - OPCODE_ILL, - OPCODE_J, - OPCODE_JX, - OPCODE_L16UI, - OPCODE_L16SI, - OPCODE_L32I, - OPCODE_L32R, - OPCODE_L8UI, - OPCODE_LOOP, - OPCODE_LOOPNEZ, - OPCODE_LOOPGTZ, - OPCODE_MOVI, - OPCODE_MOVEQZ, - OPCODE_MOVNEZ, - OPCODE_MOVLTZ, - OPCODE_MOVGEZ, - OPCODE_NEG, - OPCODE_ABS, - OPCODE_NOP, - OPCODE_RET, - OPCODE_SIMCALL, - OPCODE_S16I, - OPCODE_S32I, - OPCODE_S32NB, - OPCODE_S8I, - OPCODE_SSR, - OPCODE_SSL, - OPCODE_SSA8L, - OPCODE_SSA8B, - OPCODE_SSAI, - OPCODE_SLL, - OPCODE_SRC, - OPCODE_SRL, - OPCODE_SRA, - OPCODE_SLLI, - OPCODE_SRAI, - OPCODE_SRLI, - OPCODE_MEMW, - OPCODE_EXTW, - OPCODE_ISYNC, - OPCODE_RSYNC, - OPCODE_ESYNC, - OPCODE_DSYNC, - OPCODE_RSIL, - OPCODE_RSR_LEND, - OPCODE_WSR_LEND, - OPCODE_XSR_LEND, - OPCODE_RSR_LCOUNT, - OPCODE_WSR_LCOUNT, - OPCODE_XSR_LCOUNT, - OPCODE_RSR_LBEG, - OPCODE_WSR_LBEG, - OPCODE_XSR_LBEG, - OPCODE_RSR_SAR, - OPCODE_WSR_SAR, - OPCODE_XSR_SAR, - - OPCODE_RSR_ACCLO, - OPCODE_WSR_ACCLO, - OPCODE_XSR_ACCLO, - - OPCODE_RSR_ACCHI, - OPCODE_WSR_ACCHI, - OPCODE_XSR_ACCHI, - - OPCODE_RSR_MEMCTL, - OPCODE_WSR_MEMCTL, - OPCODE_XSR_MEMCTL, - - OPCODE_RSR_MEPC, - OPCODE_WSR_MEPC, - OPCODE_XSR_MEPC, - OPCODE_RSR_MEPS, - OPCODE_WSR_MEPS, - OPCODE_XSR_MEPS, - OPCODE_RSR_MESAVE, - OPCODE_WSR_MESAVE, - OPCODE_XSR_MESAVE, - OPCODE_RSR_MESR, - OPCODE_WSR_MESR, - OPCODE_XSR_MESR, - OPCODE_RSR_MECR, - OPCODE_WSR_MECR, - OPCODE_XSR_MECR, - OPCODE_RSR_MEVADDR, - OPCODE_WSR_MEVADDR, - OPCODE_XSR_MEVADDR, - - - OPCODE_RSR_LITBASE, - OPCODE_WSR_LITBASE, - OPCODE_XSR_LITBASE, - OPCODE_RSR_CONFIGID0, - OPCODE_WSR_CONFIGID0, - OPCODE_RSR_CONFIGID1, - OPCODE_RSR_243, - OPCODE_RSR_PS, - OPCODE_WSR_PS, - OPCODE_XSR_PS, - OPCODE_RSR_EPC1, - OPCODE_WSR_EPC1, - OPCODE_XSR_EPC1, - OPCODE_RSR_EXCSAVE1, - OPCODE_WSR_EXCSAVE1, - OPCODE_XSR_EXCSAVE1, - OPCODE_RSR_EPC2, - OPCODE_WSR_EPC2, - OPCODE_XSR_EPC2, - OPCODE_RSR_EXCSAVE2, - OPCODE_WSR_EXCSAVE2, - OPCODE_XSR_EXCSAVE2, - OPCODE_RSR_EPC3, - OPCODE_WSR_EPC3, - OPCODE_XSR_EPC3, - OPCODE_RSR_EXCSAVE3, - OPCODE_WSR_EXCSAVE3, - OPCODE_XSR_EXCSAVE3, - OPCODE_RSR_EPC4, - OPCODE_WSR_EPC4, - OPCODE_XSR_EPC4, - OPCODE_RSR_EXCSAVE4, - OPCODE_WSR_EXCSAVE4, - OPCODE_XSR_EXCSAVE4, - OPCODE_RSR_EPC5, - OPCODE_WSR_EPC5, - OPCODE_XSR_EPC5, - OPCODE_RSR_EXCSAVE5, - OPCODE_WSR_EXCSAVE5, - OPCODE_XSR_EXCSAVE5, - OPCODE_RSR_EPC6, - OPCODE_WSR_EPC6, - OPCODE_XSR_EPC6, - OPCODE_RSR_EXCSAVE6, - OPCODE_WSR_EXCSAVE6, - OPCODE_XSR_EXCSAVE6, - OPCODE_RSR_EPC7, - OPCODE_WSR_EPC7, - OPCODE_XSR_EPC7, - OPCODE_RSR_EXCSAVE7, - OPCODE_WSR_EXCSAVE7, - OPCODE_XSR_EXCSAVE7, - OPCODE_RSR_EPS2, - OPCODE_WSR_EPS2, - OPCODE_XSR_EPS2, - OPCODE_RSR_EPS3, - OPCODE_WSR_EPS3, - OPCODE_XSR_EPS3, - OPCODE_RSR_EPS4, - OPCODE_WSR_EPS4, - OPCODE_XSR_EPS4, - OPCODE_RSR_EPS5, - OPCODE_WSR_EPS5, - OPCODE_XSR_EPS5, - OPCODE_RSR_EPS6, - OPCODE_WSR_EPS6, - OPCODE_XSR_EPS6, - OPCODE_RSR_EPS7, - OPCODE_WSR_EPS7, - OPCODE_XSR_EPS7, - OPCODE_RSR_EXCVADDR, - OPCODE_WSR_EXCVADDR, - OPCODE_XSR_EXCVADDR, - OPCODE_RSR_DEPC, - OPCODE_WSR_DEPC, - OPCODE_XSR_DEPC, - OPCODE_RSR_EXCCAUSE, - OPCODE_WSR_EXCCAUSE, - OPCODE_XSR_EXCCAUSE, - OPCODE_RSR_MISC0, - OPCODE_WSR_MISC0, - OPCODE_XSR_MISC0, - OPCODE_RSR_MISC1, - OPCODE_WSR_MISC1, - OPCODE_XSR_MISC1, - OPCODE_RSR_PRID, - OPCODE_RSR_VECBASE, - OPCODE_WSR_VECBASE, - OPCODE_XSR_VECBASE, - OPCODE_MUL16U, - OPCODE_MUL16S, - OPCODE_MULL, - OPCODE_RFI, - OPCODE_WAITI, - OPCODE_RSR_INTERRUPT, - OPCODE_WSR_INTSET, - OPCODE_WSR_INTCLEAR, - OPCODE_RSR_INTENABLE, - OPCODE_WSR_INTENABLE, - OPCODE_XSR_INTENABLE, - OPCODE_BREAK, - OPCODE_BREAK_N, - OPCODE_RSR_DBREAKA0, - OPCODE_WSR_DBREAKA0, - OPCODE_XSR_DBREAKA0, - OPCODE_RSR_DBREAKC0, - OPCODE_WSR_DBREAKC0, - OPCODE_XSR_DBREAKC0, - OPCODE_RSR_DBREAKA1, - OPCODE_WSR_DBREAKA1, - OPCODE_XSR_DBREAKA1, - OPCODE_RSR_DBREAKC1, - OPCODE_WSR_DBREAKC1, - OPCODE_XSR_DBREAKC1, - OPCODE_RSR_IBREAKA0, - OPCODE_WSR_IBREAKA0, - OPCODE_XSR_IBREAKA0, - OPCODE_RSR_IBREAKA1, - OPCODE_WSR_IBREAKA1, - OPCODE_XSR_IBREAKA1, - OPCODE_RSR_IBREAKENABLE, - OPCODE_WSR_IBREAKENABLE, - OPCODE_XSR_IBREAKENABLE, - OPCODE_RSR_DEBUGCAUSE, - OPCODE_WSR_DEBUGCAUSE, - OPCODE_XSR_DEBUGCAUSE, - OPCODE_RSR_ICOUNT, - OPCODE_WSR_ICOUNT, - OPCODE_XSR_ICOUNT, - OPCODE_RSR_ICOUNTLEVEL, - OPCODE_WSR_ICOUNTLEVEL, - OPCODE_XSR_ICOUNTLEVEL, - OPCODE_RSR_DDR, - OPCODE_WSR_DDR, - OPCODE_XSR_DDR, - OPCODE_LDDR32_P, - OPCODE_SDDR32_P, - OPCODE_RFDO, - OPCODE_RFDD, - OPCODE_WSR_MMID, - OPCODE_ANDB, - OPCODE_ANDBC, - OPCODE_ORB, - OPCODE_ORBC, - OPCODE_XORB, - OPCODE_ANY4, - OPCODE_ALL4, - OPCODE_ANY8, - OPCODE_ALL8, - OPCODE_BF, - OPCODE_BT, - OPCODE_MOVF, - OPCODE_MOVT, - OPCODE_RSR_BR, - OPCODE_WSR_BR, - OPCODE_XSR_BR, - OPCODE_RSR_CCOUNT, - OPCODE_WSR_CCOUNT, - OPCODE_XSR_CCOUNT, - OPCODE_RSR_CCOMPARE0, - OPCODE_WSR_CCOMPARE0, - OPCODE_XSR_CCOMPARE0, - OPCODE_RSR_CCOMPARE1, - OPCODE_WSR_CCOMPARE1, - OPCODE_XSR_CCOMPARE1, - OPCODE_RSR_CCOMPARE2, - OPCODE_WSR_CCOMPARE2, - OPCODE_XSR_CCOMPARE2, - OPCODE_IPF, - OPCODE_IHI, - OPCODE_IPFL, - OPCODE_IHU, - OPCODE_IIU, - OPCODE_III, - OPCODE_LICT, - OPCODE_LICW, - OPCODE_SICT, - OPCODE_SICW, - OPCODE_DHWB, - OPCODE_DHWBI, - OPCODE_DIWBUI_P, - OPCODE_DIWB, - OPCODE_DIWBI, - OPCODE_DHI, - OPCODE_DII, - OPCODE_DPFR, - OPCODE_DPFW, - OPCODE_DPFRO, - OPCODE_DPFWO, - OPCODE_DPFL, - OPCODE_DHU, - OPCODE_DIU, - OPCODE_SDCT, - OPCODE_LDCT, - OPCODE_RSR_PREFCTL, - OPCODE_WSR_PREFCTL, - OPCODE_XSR_PREFCTL, - OPCODE_IDTLB, - OPCODE_PDTLB, - OPCODE_RDTLB0, - OPCODE_RDTLB1, - OPCODE_WDTLB, - OPCODE_IITLB, - OPCODE_PITLB, - OPCODE_RITLB0, - OPCODE_RITLB1, - OPCODE_WITLB, - OPCODE_RSR_CPENABLE, - OPCODE_WSR_CPENABLE, - OPCODE_XSR_CPENABLE, - OPCODE_CLAMPS, - OPCODE_MIN, - OPCODE_MAX, - OPCODE_MINU, - OPCODE_MAXU, - OPCODE_NSA, - OPCODE_NSAU, - OPCODE_SEXT, - OPCODE_L32AI, - OPCODE_S32RI, - OPCODE_S32C1I, - OPCODE_RSR_SCOMPARE1, - OPCODE_WSR_SCOMPARE1, - OPCODE_XSR_SCOMPARE1, - OPCODE_RSR_ATOMCTL, - OPCODE_WSR_ATOMCTL, - OPCODE_XSR_ATOMCTL, - OPCODE_QUOU, - OPCODE_QUOS, - OPCODE_REMU, - OPCODE_REMS, - OPCODE_RER, - OPCODE_WER, - OPCODE_RUR_AE_OVF_SAR, - OPCODE_WUR_AE_OVF_SAR, - OPCODE_RUR_AE_BITHEAD, - OPCODE_WUR_AE_BITHEAD, - OPCODE_RUR_AE_TS_FTS_BU_BP, - OPCODE_WUR_AE_TS_FTS_BU_BP, - OPCODE_RUR_AE_SD_NO, - OPCODE_WUR_AE_SD_NO, - OPCODE_RUR_AE_OVERFLOW, - OPCODE_WUR_AE_OVERFLOW, - OPCODE_RUR_AE_SAR, - OPCODE_WUR_AE_SAR, - OPCODE_RUR_AE_BITPTR, - OPCODE_WUR_AE_BITPTR, - OPCODE_RUR_AE_BITSUSED, - OPCODE_WUR_AE_BITSUSED, - OPCODE_RUR_AE_TABLESIZE, - OPCODE_WUR_AE_TABLESIZE, - OPCODE_RUR_AE_FIRST_TS, - OPCODE_WUR_AE_FIRST_TS, - OPCODE_RUR_AE_NEXTOFFSET, - OPCODE_WUR_AE_NEXTOFFSET, - OPCODE_RUR_AE_SEARCHDONE, - OPCODE_WUR_AE_SEARCHDONE, - OPCODE_RUR_THREADPTR, - OPCODE_WUR_THREADPTR, - OPCODE_AE_LP16F_I, - OPCODE_AE_LP16F_IU, - OPCODE_AE_LP16F_X, - OPCODE_AE_LP16F_XU, - OPCODE_AE_LP24_I, - OPCODE_AE_LP24_IU, - OPCODE_AE_LP24_X, - OPCODE_AE_LP24_XU, - OPCODE_AE_LP24F_I, - OPCODE_AE_LP24F_IU, - OPCODE_AE_LP24F_X, - OPCODE_AE_LP24F_XU, - OPCODE_AE_LP16X2F_I, - OPCODE_AE_LP16X2F_IU, - OPCODE_AE_LP16X2F_X, - OPCODE_AE_LP16X2F_XU, - OPCODE_AE_LP24X2F_I, - OPCODE_AE_LP24X2F_IU, - OPCODE_AE_LP24X2F_X, - OPCODE_AE_LP24X2F_XU, - OPCODE_AE_LP24X2_I, - OPCODE_AE_LP24X2_IU, - OPCODE_AE_LP24X2_X, - OPCODE_AE_LP24X2_XU, - OPCODE_AE_SP16X2F_I, - OPCODE_AE_SP16X2F_IU, - OPCODE_AE_SP16X2F_X, - OPCODE_AE_SP16X2F_XU, - OPCODE_AE_SP24X2S_I, - OPCODE_AE_SP24X2S_IU, - OPCODE_AE_SP24X2S_X, - OPCODE_AE_SP24X2S_XU, - OPCODE_AE_SP24X2F_I, - OPCODE_AE_SP24X2F_IU, - OPCODE_AE_SP24X2F_X, - OPCODE_AE_SP24X2F_XU, - OPCODE_AE_SP16F_L_I, - OPCODE_AE_SP16F_L_IU, - OPCODE_AE_SP16F_L_X, - OPCODE_AE_SP16F_L_XU, - OPCODE_AE_SP24S_L_I, - OPCODE_AE_SP24S_L_IU, - OPCODE_AE_SP24S_L_X, - OPCODE_AE_SP24S_L_XU, - OPCODE_AE_SP24F_L_I, - OPCODE_AE_SP24F_L_IU, - OPCODE_AE_SP24F_L_X, - OPCODE_AE_SP24F_L_XU, - OPCODE_AE_LQ56_I, - OPCODE_AE_LQ56_IU, - OPCODE_AE_LQ56_X, - OPCODE_AE_LQ56_XU, - OPCODE_AE_LQ32F_I, - OPCODE_AE_LQ32F_IU, - OPCODE_AE_LQ32F_X, - OPCODE_AE_LQ32F_XU, - OPCODE_AE_SQ56S_I, - OPCODE_AE_SQ56S_IU, - OPCODE_AE_SQ56S_X, - OPCODE_AE_SQ56S_XU, - OPCODE_AE_SQ32F_I, - OPCODE_AE_SQ32F_IU, - OPCODE_AE_SQ32F_X, - OPCODE_AE_SQ32F_XU, - OPCODE_AE_ZEROP48, - OPCODE_AE_MOVP48, - OPCODE_AE_SELP24_LL, - OPCODE_AE_SELP24_LH, - OPCODE_AE_SELP24_HL, - OPCODE_AE_SELP24_HH, - OPCODE_AE_MOVTP24X2, - OPCODE_AE_MOVFP24X2, - OPCODE_AE_MOVTP48, - OPCODE_AE_MOVFP48, - OPCODE_AE_MOVPA24X2, - OPCODE_AE_TRUNCP24A32X2, - OPCODE_AE_CVTA32P24_L, - OPCODE_AE_CVTA32P24_H, - OPCODE_AE_CVTP24A16X2_LL, - OPCODE_AE_CVTP24A16X2_LH, - OPCODE_AE_CVTP24A16X2_HL, - OPCODE_AE_CVTP24A16X2_HH, - OPCODE_AE_TRUNCP24Q48X2, - OPCODE_AE_TRUNCP16, - OPCODE_AE_ROUNDSP24Q48SYM, - OPCODE_AE_ROUNDSP24Q48ASYM, - OPCODE_AE_ROUNDSP16Q48SYM, - OPCODE_AE_ROUNDSP16Q48ASYM, - OPCODE_AE_ROUNDSP16SYM, - OPCODE_AE_ROUNDSP16ASYM, - OPCODE_AE_ZEROQ56, - OPCODE_AE_MOVQ56, - OPCODE_AE_MOVTQ56, - OPCODE_AE_MOVFQ56, - OPCODE_AE_CVTQ48A32S, - OPCODE_AE_CVTQ48P24S_L, - OPCODE_AE_CVTQ48P24S_H, - OPCODE_AE_SATQ48S, - OPCODE_AE_TRUNCQ32, - OPCODE_AE_ROUNDSQ32SYM, - OPCODE_AE_ROUNDSQ32ASYM, - OPCODE_AE_TRUNCA32Q48, - OPCODE_AE_MOVAP24S_L, - OPCODE_AE_MOVAP24S_H, - OPCODE_AE_TRUNCA16P24S_L, - OPCODE_AE_TRUNCA16P24S_H, - OPCODE_AE_ADDP24, - OPCODE_AE_SUBP24, - OPCODE_AE_NEGP24, - OPCODE_AE_ABSP24, - OPCODE_AE_MAXP24S, - OPCODE_AE_MINP24S, - OPCODE_AE_MAXBP24S, - OPCODE_AE_MINBP24S, - OPCODE_AE_ADDSP24S, - OPCODE_AE_SUBSP24S, - OPCODE_AE_NEGSP24S, - OPCODE_AE_ABSSP24S, - OPCODE_AE_ANDP48, - OPCODE_AE_NANDP48, - OPCODE_AE_ORP48, - OPCODE_AE_XORP48, - OPCODE_AE_LTP24S, - OPCODE_AE_LEP24S, - OPCODE_AE_EQP24, - OPCODE_AE_ADDQ56, - OPCODE_AE_SUBQ56, - OPCODE_AE_NEGQ56, - OPCODE_AE_ABSQ56, - OPCODE_AE_MAXQ56S, - OPCODE_AE_MINQ56S, - OPCODE_AE_MAXBQ56S, - OPCODE_AE_MINBQ56S, - OPCODE_AE_ADDSQ56S, - OPCODE_AE_SUBSQ56S, - OPCODE_AE_NEGSQ56S, - OPCODE_AE_ABSSQ56S, - OPCODE_AE_ANDQ56, - OPCODE_AE_NANDQ56, - OPCODE_AE_ORQ56, - OPCODE_AE_XORQ56, - OPCODE_AE_SLLIP24, - OPCODE_AE_SRLIP24, - OPCODE_AE_SRAIP24, - OPCODE_AE_SLLSP24, - OPCODE_AE_SRLSP24, - OPCODE_AE_SRASP24, - OPCODE_AE_SLLISP24S, - OPCODE_AE_SLLSSP24S, - OPCODE_AE_SLLIQ56, - OPCODE_AE_SRLIQ56, - OPCODE_AE_SRAIQ56, - OPCODE_AE_SLLSQ56, - OPCODE_AE_SRLSQ56, - OPCODE_AE_SRASQ56, - OPCODE_AE_SLLAQ56, - OPCODE_AE_SRLAQ56, - OPCODE_AE_SRAAQ56, - OPCODE_AE_SLLISQ56S, - OPCODE_AE_SLLSSQ56S, - OPCODE_AE_SLLASQ56S, - OPCODE_AE_LTQ56S, - OPCODE_AE_LEQ56S, - OPCODE_AE_EQQ56, - OPCODE_AE_NSAQ56S, - OPCODE_AE_MULSRFQ32SP24S_H, - OPCODE_AE_MULSRFQ32SP24S_L, - OPCODE_AE_MULARFQ32SP24S_H, - OPCODE_AE_MULARFQ32SP24S_L, - OPCODE_AE_MULRFQ32SP24S_H, - OPCODE_AE_MULRFQ32SP24S_L, - OPCODE_AE_MULSFQ32SP24S_H, - OPCODE_AE_MULSFQ32SP24S_L, - OPCODE_AE_MULAFQ32SP24S_H, - OPCODE_AE_MULAFQ32SP24S_L, - OPCODE_AE_MULFQ32SP24S_H, - OPCODE_AE_MULFQ32SP24S_L, - OPCODE_AE_MULFS32P16S_LL, - OPCODE_AE_MULFP24S_LL, - OPCODE_AE_MULP24S_LL, - OPCODE_AE_MULFS32P16S_LH, - OPCODE_AE_MULFP24S_LH, - OPCODE_AE_MULP24S_LH, - OPCODE_AE_MULFS32P16S_HL, - OPCODE_AE_MULFP24S_HL, - OPCODE_AE_MULP24S_HL, - OPCODE_AE_MULFS32P16S_HH, - OPCODE_AE_MULFP24S_HH, - OPCODE_AE_MULP24S_HH, - OPCODE_AE_MULAFS32P16S_LL, - OPCODE_AE_MULAFP24S_LL, - OPCODE_AE_MULAP24S_LL, - OPCODE_AE_MULAFS32P16S_LH, - OPCODE_AE_MULAFP24S_LH, - OPCODE_AE_MULAP24S_LH, - OPCODE_AE_MULAFS32P16S_HL, - OPCODE_AE_MULAFP24S_HL, - OPCODE_AE_MULAP24S_HL, - OPCODE_AE_MULAFS32P16S_HH, - OPCODE_AE_MULAFP24S_HH, - OPCODE_AE_MULAP24S_HH, - OPCODE_AE_MULSFS32P16S_LL, - OPCODE_AE_MULSFP24S_LL, - OPCODE_AE_MULSP24S_LL, - OPCODE_AE_MULSFS32P16S_LH, - OPCODE_AE_MULSFP24S_LH, - OPCODE_AE_MULSP24S_LH, - OPCODE_AE_MULSFS32P16S_HL, - OPCODE_AE_MULSFP24S_HL, - OPCODE_AE_MULSP24S_HL, - OPCODE_AE_MULSFS32P16S_HH, - OPCODE_AE_MULSFP24S_HH, - OPCODE_AE_MULSP24S_HH, - OPCODE_AE_MULAFS56P24S_LL, - OPCODE_AE_MULAS56P24S_LL, - OPCODE_AE_MULAFS56P24S_LH, - OPCODE_AE_MULAS56P24S_LH, - OPCODE_AE_MULAFS56P24S_HL, - OPCODE_AE_MULAS56P24S_HL, - OPCODE_AE_MULAFS56P24S_HH, - OPCODE_AE_MULAS56P24S_HH, - OPCODE_AE_MULSFS56P24S_LL, - OPCODE_AE_MULSS56P24S_LL, - OPCODE_AE_MULSFS56P24S_LH, - OPCODE_AE_MULSS56P24S_LH, - OPCODE_AE_MULSFS56P24S_HL, - OPCODE_AE_MULSS56P24S_HL, - OPCODE_AE_MULSFS56P24S_HH, - OPCODE_AE_MULSS56P24S_HH, - OPCODE_AE_MULFQ32SP16S_L, - OPCODE_AE_MULFQ32SP16S_H, - OPCODE_AE_MULFQ32SP16U_L, - OPCODE_AE_MULFQ32SP16U_H, - OPCODE_AE_MULQ32SP16S_L, - OPCODE_AE_MULQ32SP16S_H, - OPCODE_AE_MULQ32SP16U_L, - OPCODE_AE_MULQ32SP16U_H, - OPCODE_AE_MULAFQ32SP16S_L, - OPCODE_AE_MULAFQ32SP16S_H, - OPCODE_AE_MULAFQ32SP16U_L, - OPCODE_AE_MULAFQ32SP16U_H, - OPCODE_AE_MULAQ32SP16S_L, - OPCODE_AE_MULAQ32SP16S_H, - OPCODE_AE_MULAQ32SP16U_L, - OPCODE_AE_MULAQ32SP16U_H, - OPCODE_AE_MULSFQ32SP16S_L, - OPCODE_AE_MULSFQ32SP16S_H, - OPCODE_AE_MULSFQ32SP16U_L, - OPCODE_AE_MULSFQ32SP16U_H, - OPCODE_AE_MULSQ32SP16S_L, - OPCODE_AE_MULSQ32SP16S_H, - OPCODE_AE_MULSQ32SP16U_L, - OPCODE_AE_MULSQ32SP16U_H, - OPCODE_AE_MULZAAQ32SP16S_LL, - OPCODE_AE_MULZAAFQ32SP16S_LL, - OPCODE_AE_MULZAAQ32SP16U_LL, - OPCODE_AE_MULZAAFQ32SP16U_LL, - OPCODE_AE_MULZAAQ32SP16S_HH, - OPCODE_AE_MULZAAFQ32SP16S_HH, - OPCODE_AE_MULZAAQ32SP16U_HH, - OPCODE_AE_MULZAAFQ32SP16U_HH, - OPCODE_AE_MULZAAQ32SP16S_LH, - OPCODE_AE_MULZAAFQ32SP16S_LH, - OPCODE_AE_MULZAAQ32SP16U_LH, - OPCODE_AE_MULZAAFQ32SP16U_LH, - OPCODE_AE_MULZASQ32SP16S_LL, - OPCODE_AE_MULZASFQ32SP16S_LL, - OPCODE_AE_MULZASQ32SP16U_LL, - OPCODE_AE_MULZASFQ32SP16U_LL, - OPCODE_AE_MULZASQ32SP16S_HH, - OPCODE_AE_MULZASFQ32SP16S_HH, - OPCODE_AE_MULZASQ32SP16U_HH, - OPCODE_AE_MULZASFQ32SP16U_HH, - OPCODE_AE_MULZASQ32SP16S_LH, - OPCODE_AE_MULZASFQ32SP16S_LH, - OPCODE_AE_MULZASQ32SP16U_LH, - OPCODE_AE_MULZASFQ32SP16U_LH, - OPCODE_AE_MULZSAQ32SP16S_LL, - OPCODE_AE_MULZSAFQ32SP16S_LL, - OPCODE_AE_MULZSAQ32SP16U_LL, - OPCODE_AE_MULZSAFQ32SP16U_LL, - OPCODE_AE_MULZSAQ32SP16S_HH, - OPCODE_AE_MULZSAFQ32SP16S_HH, - OPCODE_AE_MULZSAQ32SP16U_HH, - OPCODE_AE_MULZSAFQ32SP16U_HH, - OPCODE_AE_MULZSAQ32SP16S_LH, - OPCODE_AE_MULZSAFQ32SP16S_LH, - OPCODE_AE_MULZSAQ32SP16U_LH, - OPCODE_AE_MULZSAFQ32SP16U_LH, - OPCODE_AE_MULZSSQ32SP16S_LL, - OPCODE_AE_MULZSSFQ32SP16S_LL, - OPCODE_AE_MULZSSQ32SP16U_LL, - OPCODE_AE_MULZSSFQ32SP16U_LL, - OPCODE_AE_MULZSSQ32SP16S_HH, - OPCODE_AE_MULZSSFQ32SP16S_HH, - OPCODE_AE_MULZSSQ32SP16U_HH, - OPCODE_AE_MULZSSFQ32SP16U_HH, - OPCODE_AE_MULZSSQ32SP16S_LH, - OPCODE_AE_MULZSSFQ32SP16S_LH, - OPCODE_AE_MULZSSQ32SP16U_LH, - OPCODE_AE_MULZSSFQ32SP16U_LH, - OPCODE_AE_MULZAAFP24S_HH_LL, - OPCODE_AE_MULZAAP24S_HH_LL, - OPCODE_AE_MULZAAFP24S_HL_LH, - OPCODE_AE_MULZAAP24S_HL_LH, - OPCODE_AE_MULZASFP24S_HH_LL, - OPCODE_AE_MULZASP24S_HH_LL, - OPCODE_AE_MULZASFP24S_HL_LH, - OPCODE_AE_MULZASP24S_HL_LH, - OPCODE_AE_MULZSAFP24S_HH_LL, - OPCODE_AE_MULZSAP24S_HH_LL, - OPCODE_AE_MULZSAFP24S_HL_LH, - OPCODE_AE_MULZSAP24S_HL_LH, - OPCODE_AE_MULZSSFP24S_HH_LL, - OPCODE_AE_MULZSSP24S_HH_LL, - OPCODE_AE_MULZSSFP24S_HL_LH, - OPCODE_AE_MULZSSP24S_HL_LH, - OPCODE_AE_MULAAFP24S_HH_LL, - OPCODE_AE_MULAAP24S_HH_LL, - OPCODE_AE_MULAAFP24S_HL_LH, - OPCODE_AE_MULAAP24S_HL_LH, - OPCODE_AE_MULASFP24S_HH_LL, - OPCODE_AE_MULASP24S_HH_LL, - OPCODE_AE_MULASFP24S_HL_LH, - OPCODE_AE_MULASP24S_HL_LH, - OPCODE_AE_MULSAFP24S_HH_LL, - OPCODE_AE_MULSAP24S_HH_LL, - OPCODE_AE_MULSAFP24S_HL_LH, - OPCODE_AE_MULSAP24S_HL_LH, - OPCODE_AE_MULSSFP24S_HH_LL, - OPCODE_AE_MULSSP24S_HH_LL, - OPCODE_AE_MULSSFP24S_HL_LH, - OPCODE_AE_MULSSP24S_HL_LH, - OPCODE_AE_SHA32, - OPCODE_AE_VLDL32T, - OPCODE_AE_VLDL16T, - OPCODE_AE_VLDL16C, - OPCODE_AE_VLDSHT, - OPCODE_AE_LB, - OPCODE_AE_LBI, - OPCODE_AE_LBK, - OPCODE_AE_LBKI, - OPCODE_AE_DB, - OPCODE_AE_DBI, - OPCODE_AE_VLEL32T, - OPCODE_AE_VLEL16T, - OPCODE_AE_SB, - OPCODE_AE_SBI, - OPCODE_AE_VLES16C, - OPCODE_AE_SBF, - OPCODE_AE_SLAASQ56S, - OPCODE_AE_ADDBRBA32, - OPCODE_AE_MINABSSP24S, - OPCODE_AE_MAXABSSP24S, - OPCODE_AE_MINABSSQ56S, - OPCODE_AE_MAXABSSQ56S, - OPCODE_RUR_AE_CBEGIN0, - OPCODE_WUR_AE_CBEGIN0, - OPCODE_RUR_AE_CEND0, - OPCODE_WUR_AE_CEND0, - OPCODE_AE_LP24X2_C, - OPCODE_AE_SP24X2S_C, - OPCODE_AE_LP24X2F_C, - OPCODE_AE_SP24X2F_C, - OPCODE_AE_LP16X2F_C, - OPCODE_AE_SP16X2F_C, - OPCODE_AE_LP24_C, - OPCODE_AE_SP24S_L_C, - OPCODE_AE_LP24F_C, - OPCODE_AE_SP24F_L_C, - OPCODE_AE_LP16F_C, - OPCODE_AE_SP16F_L_C, - OPCODE_AE_LQ56_C, - OPCODE_AE_SQ56S_C, - OPCODE_AE_LQ32F_C, - OPCODE_AE_SQ32F_C, - OPCODE_READ_IPQ, - OPCODE_CHECK_IPQ, - OPCODE_WRITE_OPQ, - OPCODE_CHECK_OPQ, - OPCODE_RUR_EXPSTATE, - OPCODE_WUR_EXPSTATE, - OPCODE_READ_IMPWIRE, - OPCODE_SETB_EXPSTATE, - OPCODE_CLRB_EXPSTATE, - OPCODE_WRMSK_EXPSTATE -}; - - -/* Slot-specific opcode decode functions. */ - -static int -Slot_inst_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst_get (insn) == 0) - { - if (Field_op1_Slot_inst_get (insn) == 0) - { - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_r_Slot_inst_get (insn) == 0) - { - if (Field_m_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_n_Slot_inst_get (insn) == 0) - return OPCODE_ILL; - if (Field_m_Slot_inst_get (insn) == 2) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_RET; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_RETW; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_JX; - } - if (Field_m_Slot_inst_get (insn) == 3) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_CALLX0; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_CALLX4; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_CALLX8; - if (Field_n_Slot_inst_get (insn) == 3) - return OPCODE_CALLX12; - } - } - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_MOVSP; - if (Field_r_Slot_inst_get (insn) == 2) - { - if (Field_s_Slot_inst_get (insn) == 0) - { - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_ISYNC; - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RSYNC; - if (Field_t_Slot_inst_get (insn) == 2) - return OPCODE_ESYNC; - if (Field_t_Slot_inst_get (insn) == 3) - return OPCODE_DSYNC; - if (Field_t_Slot_inst_get (insn) == 8) - return OPCODE_EXCW; - if (Field_t_Slot_inst_get (insn) == 12) - return OPCODE_MEMW; - if (Field_t_Slot_inst_get (insn) == 13) - return OPCODE_EXTW; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_NOP; - } - } - if (Field_r_Slot_inst_get (insn) == 3) - { - if (Field_t_Slot_inst_get (insn) == 0) - { - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_RFE; - if (Field_s_Slot_inst_get (insn) == 2) - return OPCODE_RFDE; - if (Field_s_Slot_inst_get (insn) == 4) - return OPCODE_RFWO; - if (Field_s_Slot_inst_get (insn) == 5) - return OPCODE_RFWU; - } - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFI; - if (Field_t_Slot_inst_get (insn) == 2) - return OPCODE_RFME; - } - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_BREAK; - if (Field_r_Slot_inst_get (insn) == 5) - { - if (Field_s_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SYSCALL; - if (Field_s_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SIMCALL; - } - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_RSIL; - if (Field_r_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_WAITI; - if (Field_r_Slot_inst_get (insn) == 7) - { - if (Field_t_Slot_inst_get (insn) == 14) - return OPCODE_LDDR32_P; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_SDDR32_P; - } - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_ANY4; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_ALL4; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_ANY8; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_ALL8; - } - if (Field_op2_Slot_inst_get (insn) == 1) - return OPCODE_AND; - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_OR; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_XOR; - if (Field_op2_Slot_inst_get (insn) == 4) - { - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSR; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSL; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8L; - if (Field_r_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8B; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_thi3_Slot_inst_get (insn) == 0) - return OPCODE_SSAI; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_RER; - if (Field_r_Slot_inst_get (insn) == 7) - return OPCODE_WER; - if (Field_r_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_ROTW; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_NSA; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_NSAU; - } - if (Field_op2_Slot_inst_get (insn) == 5) - { - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_RITLB0; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IITLB; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_PITLB; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_WITLB; - if (Field_r_Slot_inst_get (insn) == 7) - return OPCODE_RITLB1; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_RDTLB0; - if (Field_r_Slot_inst_get (insn) == 12 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IDTLB; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_PDTLB; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_WDTLB; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_RDTLB1; - } - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_NEG; - if (Field_s_Slot_inst_get (insn) == 1) - return OPCODE_ABS; - } - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_ADD; - if (Field_op2_Slot_inst_get (insn) == 9) - return OPCODE_ADDX2; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_ADDX4; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_ADDX8; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_SUB; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_SUBX2; - if (Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_SUBX4; - if (Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_SUBX8; - } - if (Field_op1_Slot_inst_get (insn) == 1) - { - if ((Field_op2_Slot_inst_get (insn) == 0 || - Field_op2_Slot_inst_get (insn) == 1)) - return OPCODE_SLLI; - if ((Field_op2_Slot_inst_get (insn) == 2 || - Field_op2_Slot_inst_get (insn) == 3)) - return OPCODE_SRAI; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_SRLI; - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_XSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_XSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_XSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_XSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_XSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_XSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_XSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_XSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_XSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 40) - return OPCODE_XSR_PREFCTL; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_XSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_XSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_XSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 97) - return OPCODE_XSR_MEMCTL; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_XSR_ATOMCTL; - - if (Field_sr_Slot_inst_get (insn) == 106) - return OPCODE_XSR_MEPC; - if (Field_sr_Slot_inst_get (insn) == 107) - return OPCODE_XSR_MEPS; - if (Field_sr_Slot_inst_get (insn) == 108) - return OPCODE_XSR_MESAVE; - if (Field_sr_Slot_inst_get (insn) == 109) - return OPCODE_XSR_MESR; - if (Field_sr_Slot_inst_get (insn) == 110) - return OPCODE_XSR_MECR; - if (Field_sr_Slot_inst_get (insn) == 111) - return OPCODE_XSR_MEVADDR; - - - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_XSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_XSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_XSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_XSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_XSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_XSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_XSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_XSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_XSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_XSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_XSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_XSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_XSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_XSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_XSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_XSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_XSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_XSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_XSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_XSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_XSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_XSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_XSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_XSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_XSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_XSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_XSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_XSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_XSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_XSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_XSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_XSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_XSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_XSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_XSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_XSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_XSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_XSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_XSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_XSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_XSR_CCOMPARE2; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_XSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_XSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_SRC; - if (Field_op2_Slot_inst_get (insn) == 9 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRL; - if (Field_op2_Slot_inst_get (insn) == 10 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SLL; - if (Field_op2_Slot_inst_get (insn) == 11 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRA; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_MUL16U; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_MUL16S; - if (Field_op2_Slot_inst_get (insn) == 15) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_LICT; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_SICT; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_LICW; - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_SICW; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_LDCT; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_SDCT; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_RFDO; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFDD; - } - } - if (Field_op1_Slot_inst_get (insn) == 2) - { - if (Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_ANDB; - if (Field_op2_Slot_inst_get (insn) == 1) - return OPCODE_ANDBC; - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_ORB; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_ORBC; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_XORB; - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_MULL; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_QUOU; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_QUOS; - if (Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_REMU; - if (Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_REMS; - } - if (Field_op1_Slot_inst_get (insn) == 3) - { - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_RSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_RSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_RSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_RSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_RSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_RSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_RSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_RSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_RSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 40) - return OPCODE_RSR_PREFCTL; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_RSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_RSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_RSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 97) - return OPCODE_RSR_MEMCTL; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_RSR_ATOMCTL; - - if (Field_sr_Slot_inst_get (insn) == 106) - return OPCODE_RSR_MEPC; - if (Field_sr_Slot_inst_get (insn) == 107) - return OPCODE_RSR_MEPS; - if (Field_sr_Slot_inst_get (insn) == 108) - return OPCODE_RSR_MESAVE; - if (Field_sr_Slot_inst_get (insn) == 109) - return OPCODE_RSR_MESR; - if (Field_sr_Slot_inst_get (insn) == 110) - return OPCODE_RSR_MECR; - if (Field_sr_Slot_inst_get (insn) == 111) - return OPCODE_RSR_MEVADDR; - - - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_RSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_RSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_RSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_RSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_RSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_RSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_RSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 176) - return OPCODE_RSR_CONFIGID0; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_RSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_RSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_RSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_RSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_RSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_RSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_RSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_RSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_RSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_RSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_RSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_RSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_RSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_RSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 208) - return OPCODE_RSR_CONFIGID1; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_RSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_RSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_RSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_RSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_RSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_RSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_RSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_RSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 226) - return OPCODE_RSR_INTERRUPT; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_RSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_RSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_RSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_RSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_RSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_RSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 235) - return OPCODE_RSR_PRID; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_RSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_RSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_RSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_RSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_RSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_RSR_CCOMPARE2; - if (Field_sr_Slot_inst_get (insn) == 243) - return OPCODE_RSR_243; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_RSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_RSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 1) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_WSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_WSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_WSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_WSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_WSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_WSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_WSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_WSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_WSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 40) - return OPCODE_WSR_PREFCTL; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_WSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_WSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 89) - return OPCODE_WSR_MMID; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_WSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 97) - return OPCODE_WSR_MEMCTL; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_WSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 106) - return OPCODE_WSR_MEPC; - if (Field_sr_Slot_inst_get (insn) == 107) - return OPCODE_WSR_MEPS; - if (Field_sr_Slot_inst_get (insn) == 108) - return OPCODE_WSR_MESAVE; - if (Field_sr_Slot_inst_get (insn) == 109) - return OPCODE_WSR_MESR; - if (Field_sr_Slot_inst_get (insn) == 110) - return OPCODE_WSR_MECR; - if (Field_sr_Slot_inst_get (insn) == 111) - return OPCODE_WSR_MEVADDR; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_WSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_WSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_WSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_WSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_WSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_WSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_WSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 176) - return OPCODE_WSR_CONFIGID0; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_WSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_WSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_WSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_WSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_WSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_WSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_WSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_WSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_WSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_WSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_WSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_WSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_WSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_WSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_WSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_WSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_WSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_WSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_WSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_WSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_WSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_WSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 226) - return OPCODE_WSR_INTSET; - if (Field_sr_Slot_inst_get (insn) == 227) - return OPCODE_WSR_INTCLEAR; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_WSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_WSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_WSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_WSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_WSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_WSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_WSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_WSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_WSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_WSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_WSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_WSR_CCOMPARE2; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_WSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_WSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_SEXT; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_CLAMPS; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_MIN; - if (Field_op2_Slot_inst_get (insn) == 5) - return OPCODE_MAX; - if (Field_op2_Slot_inst_get (insn) == 6) - return OPCODE_MINU; - if (Field_op2_Slot_inst_get (insn) == 7) - return OPCODE_MAXU; - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_MOVEQZ; - if (Field_op2_Slot_inst_get (insn) == 9) - return OPCODE_MOVNEZ; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_MOVLTZ; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_MOVGEZ; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_MOVF; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_MOVT; - if (Field_op2_Slot_inst_get (insn) == 14) - { - if (Field_st_Slot_inst_get (insn) == 230) - return OPCODE_RUR_EXPSTATE; - if (Field_st_Slot_inst_get (insn) == 231) - return OPCODE_RUR_THREADPTR; - if (Field_st_Slot_inst_get (insn) == 240) - return OPCODE_RUR_AE_OVF_SAR; - if (Field_st_Slot_inst_get (insn) == 241) - return OPCODE_RUR_AE_BITHEAD; - if (Field_st_Slot_inst_get (insn) == 242) - return OPCODE_RUR_AE_TS_FTS_BU_BP; - if (Field_st_Slot_inst_get (insn) == 243) - return OPCODE_RUR_AE_SD_NO; - if (Field_st_Slot_inst_get (insn) == 246) - return OPCODE_RUR_AE_CBEGIN0; - if (Field_st_Slot_inst_get (insn) == 247) - return OPCODE_RUR_AE_CEND0; - } - if (Field_op2_Slot_inst_get (insn) == 15) - { - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_WUR_EXPSTATE; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_WUR_THREADPTR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_WUR_AE_OVF_SAR; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_WUR_AE_BITHEAD; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_WUR_AE_TS_FTS_BU_BP; - if (Field_sr_Slot_inst_get (insn) == 243) - return OPCODE_WUR_AE_SD_NO; - if (Field_sr_Slot_inst_get (insn) == 246) - return OPCODE_WUR_AE_CBEGIN0; - if (Field_sr_Slot_inst_get (insn) == 247) - return OPCODE_WUR_AE_CEND0; - } - } - if ((Field_op1_Slot_inst_get (insn) == 4 || - Field_op1_Slot_inst_get (insn) == 5)) - return OPCODE_EXTUI; - if (Field_op1_Slot_inst_get (insn) == 9) - { - if (Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_L32E; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_S32E; - if (Field_op2_Slot_inst_get (insn) == 5) - return OPCODE_S32NB; - } - if (Field_r_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_READ_IMPWIRE; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_s3to1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_SETB_EXPSTATE; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_s3to1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_CLRB_EXPSTATE; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_WRMSK_EXPSTATE; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_READ_IPQ; - if (Field_r_Slot_inst_get (insn) == 5 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_CHECK_IPQ; - if (Field_r_Slot_inst_get (insn) == 6 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_WRITE_OPQ; - if (Field_r_Slot_inst_get (insn) == 7 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_CHECK_OPQ; - } - if (Field_op0_Slot_inst_get (insn) == 1) - return OPCODE_L32R; - if (Field_op0_Slot_inst_get (insn) == 2) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_L8UI; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_L16UI; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_L32I; - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_S8I; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_S16I; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_S32I; - if (Field_r_Slot_inst_get (insn) == 7) - { - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_DPFR; - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_DPFW; - if (Field_t_Slot_inst_get (insn) == 2) - return OPCODE_DPFRO; - if (Field_t_Slot_inst_get (insn) == 3) - return OPCODE_DPFWO; - if (Field_t_Slot_inst_get (insn) == 4) - return OPCODE_DHWB; - if (Field_t_Slot_inst_get (insn) == 5) - return OPCODE_DHWBI; - if (Field_t_Slot_inst_get (insn) == 6) - return OPCODE_DHI; - if (Field_t_Slot_inst_get (insn) == 7) - return OPCODE_DII; - if (Field_t_Slot_inst_get (insn) == 8) - { - if (Field_op1_Slot_inst_get (insn) == 0) - return OPCODE_DPFL; - if (Field_op1_Slot_inst_get (insn) == 2) - return OPCODE_DHU; - if (Field_op1_Slot_inst_get (insn) == 3) - return OPCODE_DIU; - if (Field_op1_Slot_inst_get (insn) == 4) - return OPCODE_DIWB; - if (Field_op1_Slot_inst_get (insn) == 5) - return OPCODE_DIWBI; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_DIWBUI_P; - } - if (Field_t_Slot_inst_get (insn) == 12) - return OPCODE_IPF; - if (Field_t_Slot_inst_get (insn) == 13) - { - if (Field_op1_Slot_inst_get (insn) == 0) - return OPCODE_IPFL; - if (Field_op1_Slot_inst_get (insn) == 2) - return OPCODE_IHU; - if (Field_op1_Slot_inst_get (insn) == 3) - return OPCODE_IIU; - } - if (Field_t_Slot_inst_get (insn) == 14) - return OPCODE_IHI; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_III; - } - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_L16SI; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_MOVI; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_L32AI; - if (Field_r_Slot_inst_get (insn) == 12) - return OPCODE_ADDI; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_ADDMI; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_S32C1I; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_S32RI; - } - if (Field_op0_Slot_inst_get (insn) == 4) - { - if (Field_ae_r10_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_I; - if (Field_ae_r10_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_X; - if (Field_ae_r10_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_I; - if (Field_ae_r10_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_X; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_IU; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_XU; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_CVTQ48A32S; - if (Field_ae_r10_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_IU; - if (Field_ae_r10_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_ae_s3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVP48; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVPA24X2; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_CVTA32P24_L; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_LL; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_HL; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVAP24S_L; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCA16P24S_L; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP16X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24X2_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCP24A32X2; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_CVTA32P24_H; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_LH; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_HH; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVAP24S_H; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCA16P24S_H; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_I; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_X; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_TRUNCA32Q48; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_I; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_X; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_NSAQ56S; - if (Field_ae_r32_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_IU; - if (Field_ae_r32_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_XU; - if (Field_ae_r32_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_IU; - if (Field_ae_r32_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_XU; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRLIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRAIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLISQ56S; - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SHA32; - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLDL32T; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SLLAQ56; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLDL16T; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SRLAQ56; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LBK; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SRAAQ56; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLEL32T; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SLLASQ56S; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLEL16T; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_MOVTQ56; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_MOVFQ56; - if (Field_r_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_OVERFLOW; - if (Field_r_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_SBI; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_SAR; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_DB; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_SB; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_BITPTR; - if (Field_r_Slot_inst_get (insn) == 3 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_BITSUSED; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_TABLESIZE; - if (Field_r_Slot_inst_get (insn) == 5 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_FIRST_TS; - if (Field_r_Slot_inst_get (insn) == 6 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_NEXTOFFSET; - if (Field_r_Slot_inst_get (insn) == 7 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_SEARCHDONE; - if (Field_r_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_VLDSHT; - if (Field_r_Slot_inst_get (insn) == 12 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_VLES16C; - if (Field_r_Slot_inst_get (insn) == 13 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SBF; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_VLDL16C; - if (Field_s_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLSQ56; - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LB; - if (Field_s_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRLSQ56; - if (Field_s_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRASQ56; - if (Field_s_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLSSQ56S; - if (Field_s_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVQ56; - if (Field_s_Slot_inst_get (insn) == 8 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_OVERFLOW; - if (Field_s_Slot_inst_get (insn) == 9 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_SAR; - if (Field_s_Slot_inst_get (insn) == 10 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_BITPTR; - if (Field_s_Slot_inst_get (insn) == 11 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_BITSUSED; - if (Field_s_Slot_inst_get (insn) == 12 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_TABLESIZE; - if (Field_s_Slot_inst_get (insn) == 13 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_FIRST_TS; - if (Field_s_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_NEXTOFFSET; - if (Field_s_Slot_inst_get (insn) == 15 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_SEARCHDONE; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_LBKI; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_r_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_DBI; - if (Field_t_Slot_inst_get (insn) == 2 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_LBI; - } - if (Field_op0_Slot_inst_get (insn) == 5) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_CALL0; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_CALL4; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_CALL8; - if (Field_n_Slot_inst_get (insn) == 3) - return OPCODE_CALL12; - } - if (Field_op0_Slot_inst_get (insn) == 6) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_J; - if (Field_n_Slot_inst_get (insn) == 1) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_BEQZ; - if (Field_m_Slot_inst_get (insn) == 1) - return OPCODE_BNEZ; - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTZ; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEZ; - } - if (Field_n_Slot_inst_get (insn) == 2) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_BEQI; - if (Field_m_Slot_inst_get (insn) == 1) - return OPCODE_BNEI; - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTI; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEI; - } - if (Field_n_Slot_inst_get (insn) == 3) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_ENTRY; - if (Field_m_Slot_inst_get (insn) == 1) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_BF; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_BT; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_LOOP; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_LOOPNEZ; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_LOOPGTZ; - } - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTUI; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEUI; - } - } - if (Field_op0_Slot_inst_get (insn) == 7) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_BNONE; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_BEQ; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_BLT; - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_BLTU; - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_BALL; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_BBC; - if ((Field_r_Slot_inst_get (insn) == 6 || - Field_r_Slot_inst_get (insn) == 7)) - return OPCODE_BBCI; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_BANY; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_BNE; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_BGE; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_BGEU; - if (Field_r_Slot_inst_get (insn) == 12) - return OPCODE_BNALL; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_BBS; - if ((Field_r_Slot_inst_get (insn) == 14 || - Field_r_Slot_inst_get (insn) == 15)) - return OPCODE_BBSI; - } - return 0; -} - -static int -Slot_inst16b_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst16b_get (insn) == 12) - { - if (Field_i_Slot_inst16b_get (insn) == 0) - return OPCODE_MOVI_N; - if (Field_i_Slot_inst16b_get (insn) == 1) - { - if (Field_z_Slot_inst16b_get (insn) == 0) - return OPCODE_BEQZ_N; - if (Field_z_Slot_inst16b_get (insn) == 1) - return OPCODE_BNEZ_N; - } - } - if (Field_op0_Slot_inst16b_get (insn) == 13) - { - if (Field_r_Slot_inst16b_get (insn) == 0) - return OPCODE_MOV_N; - if (Field_r_Slot_inst16b_get (insn) == 15) - { - if (Field_t_Slot_inst16b_get (insn) == 0) - return OPCODE_RET_N; - if (Field_t_Slot_inst16b_get (insn) == 1) - return OPCODE_RETW_N; - if (Field_t_Slot_inst16b_get (insn) == 2) - return OPCODE_BREAK_N; - if (Field_t_Slot_inst16b_get (insn) == 3 && - Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_NOP_N; - if (Field_t_Slot_inst16b_get (insn) == 6 && - Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_ILL_N; - } - } - return 0; -} - -static int -Slot_inst16a_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst16a_get (insn) == 8) - return OPCODE_L32I_N; - if (Field_op0_Slot_inst16a_get (insn) == 9) - return OPCODE_S32I_N; - if (Field_op0_Slot_inst16a_get (insn) == 10) - return OPCODE_ADD_N; - if (Field_op0_Slot_inst16a_get (insn) == 11) - return OPCODE_ADDI_N; - return 0; -} - -static int -Slot_ae_slot0_decode (const xtensa_insnbuf insn) -{ - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_ADDBRBA32; - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 2 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_C; - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 2 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_C; - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 2 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_C; - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf353_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_C; - if (Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_C; - if (Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_C; - if (Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_get (insn) == 2 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_C; - if (Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_C; - if (Field_combined1b97e84f_fld93_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld90_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_C; - if (Field_combined4b12daa6_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld85_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld122_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld119_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld97_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SELP24_LH; - if (Field_combined4b12daa6_fld122_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld85_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld119_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld97_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SELP24_HH; - if (Field_combined4b12daa6_fld122_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld85_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld119_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld97_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SELP24_HL; - if (Field_combined4b12daa6_fld85_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld122_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld119_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld97_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld115_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SELP24_LL; - if (Field_ftsf212ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_J; - if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_EXTUI; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BGEZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BLTZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 8 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BEQZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 9 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BNEZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVI; - if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 88 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRAI; - if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 96 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SLLI; - if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 123 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVTQ56; - if (Field_ftsf216ae_slot0_Slot_ae_slot0_get (insn) == 418 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_HH; - if (Field_ftsf217_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4 && - Field_ae_r20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_L32I; - if (Field_ftsf218ae_slot0_Slot_ae_slot0_get (insn) == 419 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_I; - if (Field_ftsf219ae_slot0_Slot_ae_slot0_get (insn) == 420 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_HL; - if (Field_ftsf220ae_slot0_Slot_ae_slot0_get (insn) == 421 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_IU; - if (Field_ftsf221ae_slot0_Slot_ae_slot0_get (insn) == 422 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_X; - if (Field_ftsf222ae_slot0_Slot_ae_slot0_get (insn) == 423 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_XU; - if (Field_ftsf223ae_slot0_Slot_ae_slot0_get (insn) == 424 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_LH; - if (Field_ftsf224ae_slot0_Slot_ae_slot0_get (insn) == 425 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_I; - if (Field_ftsf225ae_slot0_Slot_ae_slot0_get (insn) == 426 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_IU; - if (Field_ftsf226ae_slot0_Slot_ae_slot0_get (insn) == 427 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_XU; - if (Field_ftsf227ae_slot0_Slot_ae_slot0_get (insn) == 428 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_X; - if (Field_ftsf228ae_slot0_Slot_ae_slot0_get (insn) == 429 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_I; - if (Field_ftsf229ae_slot0_Slot_ae_slot0_get (insn) == 430 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_IU; - if (Field_ftsf230ae_slot0_Slot_ae_slot0_get (insn) == 431 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_X; - if (Field_ftsf231ae_slot0_Slot_ae_slot0_get (insn) == 432 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_LL; - if (Field_ftsf232ae_slot0_Slot_ae_slot0_get (insn) == 433 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_XU; - if (Field_ftsf233ae_slot0_Slot_ae_slot0_get (insn) == 434 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_I; - if (Field_ftsf234ae_slot0_Slot_ae_slot0_get (insn) == 435 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_XU; - if (Field_ftsf235ae_slot0_Slot_ae_slot0_get (insn) == 436 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_IU; - if (Field_ftsf236ae_slot0_Slot_ae_slot0_get (insn) == 437 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_I; - if (Field_ftsf237ae_slot0_Slot_ae_slot0_get (insn) == 438 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_IU; - if (Field_ftsf238ae_slot0_Slot_ae_slot0_get (insn) == 439 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_X; - if (Field_ftsf239ae_slot0_Slot_ae_slot0_get (insn) == 440 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_X; - if (Field_ftsf240ae_slot0_Slot_ae_slot0_get (insn) == 441 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_XU; - if (Field_ftsf241ae_slot0_Slot_ae_slot0_get (insn) == 442 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_I; - if (Field_ftsf242ae_slot0_Slot_ae_slot0_get (insn) == 443 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_X; - if (Field_ftsf243ae_slot0_Slot_ae_slot0_get (insn) == 444 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_IU; - if (Field_ftsf244ae_slot0_Slot_ae_slot0_get (insn) == 445 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_XU; - if (Field_ftsf245ae_slot0_Slot_ae_slot0_get (insn) == 446 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVPA24X2; - if (Field_ftsf246ae_slot0_Slot_ae_slot0_get (insn) == 447 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_I; - if (Field_ftsf247ae_slot0_Slot_ae_slot0_get (insn) == 450 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_IU; - if (Field_ftsf248ae_slot0_Slot_ae_slot0_get (insn) == 451 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_X; - if (Field_ftsf249ae_slot0_Slot_ae_slot0_get (insn) == 452 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_X; - if (Field_ftsf250ae_slot0_Slot_ae_slot0_get (insn) == 453 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_XU; - if (Field_ftsf251ae_slot0_Slot_ae_slot0_get (insn) == 454 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_I; - if (Field_ftsf252ae_slot0_Slot_ae_slot0_get (insn) == 455 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_IU; - if (Field_ftsf253ae_slot0_Slot_ae_slot0_get (insn) == 456 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_XU; - if (Field_ftsf254ae_slot0_Slot_ae_slot0_get (insn) == 457 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_X; - if (Field_ftsf255ae_slot0_Slot_ae_slot0_get (insn) == 458 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_XU; - if (Field_ftsf256ae_slot0_Slot_ae_slot0_get (insn) == 459 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_IU; - if (Field_ftsf257ae_slot0_Slot_ae_slot0_get (insn) == 460 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_I; - if (Field_ftsf258ae_slot0_Slot_ae_slot0_get (insn) == 461 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_X; - if (Field_ftsf259ae_slot0_Slot_ae_slot0_get (insn) == 462 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_XU; - if (Field_ftsf260ae_slot0_Slot_ae_slot0_get (insn) == 463 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_I; - if (Field_ftsf261ae_slot0_Slot_ae_slot0_get (insn) == 464 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_I; - if (Field_ftsf262ae_slot0_Slot_ae_slot0_get (insn) == 465 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_IU; - if (Field_ftsf263ae_slot0_Slot_ae_slot0_get (insn) == 466 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_X; - if (Field_ftsf264ae_slot0_Slot_ae_slot0_get (insn) == 467 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_IU; - if (Field_ftsf265ae_slot0_Slot_ae_slot0_get (insn) == 468 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_XU; - if (Field_ftsf266ae_slot0_Slot_ae_slot0_get (insn) == 469 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_X; - if (Field_ftsf267ae_slot0_Slot_ae_slot0_get (insn) == 470 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_XU; - if (Field_ftsf268ae_slot0_Slot_ae_slot0_get (insn) == 471 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_TRUNCP24A32X2; - if (Field_ftsf269ae_slot0_Slot_ae_slot0_get (insn) == 472 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_I; - if (Field_ftsf270ae_slot0_Slot_ae_slot0_get (insn) == 946 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_I; - if (Field_ftsf271ae_slot0_Slot_ae_slot0_get (insn) == 947 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_IU; - if (Field_ftsf272ae_slot0_Slot_ae_slot0_get (insn) == 948 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_I; - if (Field_ftsf273ae_slot0_Slot_ae_slot0_get (insn) == 949 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_X; - if (Field_ftsf274ae_slot0_Slot_ae_slot0_get (insn) == 950 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_XU; - if (Field_ftsf275ae_slot0_Slot_ae_slot0_get (insn) == 951 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_I; - if (Field_ftsf276ae_slot0_Slot_ae_slot0_get (insn) == 952 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_IU; - if (Field_ftsf277ae_slot0_Slot_ae_slot0_get (insn) == 953 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_IU; - if (Field_ftsf278ae_slot0_Slot_ae_slot0_get (insn) == 954 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_X; - if (Field_ftsf279ae_slot0_Slot_ae_slot0_get (insn) == 15280 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTQ48A32S; - if (Field_ftsf281ae_slot0_Slot_ae_slot0_get (insn) == 60977 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_JX; - if (Field_ftsf282ae_slot0_Slot_ae_slot0_get (insn) == 61041 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SSR; - if (Field_ftsf283ae_slot0_Slot_ae_slot0_get (insn) == 30577 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf352ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_NOP; - if (Field_ftsf284ae_slot0_Slot_ae_slot0_get (insn) == 7641 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf354ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSA8B; - if (Field_ftsf286ae_slot0_Slot_ae_slot0_get (insn) == 3821 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf356ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSA8L; - if (Field_ftsf288ae_slot0_Slot_ae_slot0_get (insn) == 1911 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf359ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSL; - if (Field_ftsf290ae_slot0_Slot_ae_slot0_get (insn) == 478 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s8_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_LQ56_XU; - if (Field_ftsf292ae_slot0_Slot_ae_slot0_get (insn) == 1913 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ALL8; - if (Field_ftsf293_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBCI; - if (Field_ftsf293_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBSI; - if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 1915 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ANY8; - if (Field_ftsf295ae_slot0_Slot_ae_slot0_get (insn) == 959 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf358ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSAI; - if (Field_ftsf296ae_slot0_Slot_ae_slot0_get (insn) == 480 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_IU; - if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 962 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_I; - if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 963 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_IU; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 964 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLIQ56; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 965 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SRAIQ56; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 966 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SRLIQ56; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 968 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLISQ56S; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3868 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ABS; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3869 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_NEG; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3870 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRA; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3871 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRL; - if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7752 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf321_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVP48; - if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7753 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf353_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ANY4; - if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 31016 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf321_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVQ56; - if (Field_ftsf303ae_slot0_Slot_ae_slot0_get (insn) == 31017 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf321_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SLLSSQ56S; - if (Field_ftsf304ae_slot0_Slot_ae_slot0_get (insn) == 15509 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf369ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRASQ56; - if (Field_ftsf306ae_slot0_Slot_ae_slot0_get (insn) == 7755 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf368ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRLSQ56; - if (Field_ftsf308ae_slot0_Slot_ae_slot0_get (insn) == 1939 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf366ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SLLSQ56; - if (Field_ftsf309ae_slot0_Slot_ae_slot0_get (insn) == 485 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ALL4; - if (Field_ftsf310ae_slot0_Slot_ae_slot0_get (insn) == 972 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_X; - if (Field_ftsf311ae_slot0_Slot_ae_slot0_get (insn) == 973 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_XU; - if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 7792 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTA32P24_H; - if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 7793 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTA32P24_L; - if (Field_ftsf314ae_slot0_Slot_ae_slot0_get (insn) == 7794 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVAP24S_H; - if (Field_ftsf315ae_slot0_Slot_ae_slot0_get (insn) == 7795 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_TRUNCA16P24S_L; - if (Field_ftsf316ae_slot0_Slot_ae_slot0_get (insn) == 7796 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVAP24S_L; - if (Field_ftsf317ae_slot0_Slot_ae_slot0_get (insn) == 7797 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf353_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_NSAQ56S; - if (Field_ftsf318ae_slot0_Slot_ae_slot0_get (insn) == 3899 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf365ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_TRUNCA32Q48; - if (Field_ftsf319_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_ftsf361ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BT; - if (Field_ftsf320ae_slot0_Slot_ae_slot0_get (insn) == 975 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_TRUNCA16P24S_H; - if (Field_ftsf321_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_ae_s20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BLTUI; - if (Field_ftsf321_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld101_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld88_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld39_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLAASQ56S; - if (Field_ftsf322ae_slot0_Slot_ae_slot0_get (insn) == 3920 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVFQ56; - if (Field_ftsf323ae_slot0_Slot_ae_slot0_get (insn) == 3921 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLAQ56; - if (Field_ftsf324ae_slot0_Slot_ae_slot0_get (insn) == 3922 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLASQ56S; - if (Field_ftsf325ae_slot0_Slot_ae_slot0_get (insn) == 3923 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SLL; - if (Field_ftsf326ae_slot0_Slot_ae_slot0_get (insn) == 981 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf357_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRAAQ56; - if (Field_ftsf328ae_slot0_Slot_ae_slot0_get (insn) == 491 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRLAQ56; - if (Field_ftsf329ae_slot0_Slot_ae_slot0_get (insn) == 31 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SQ32F_XU; - if (Field_ftsf353_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_C; - if (Field_imm8_Slot_ae_slot0_get (insn) == 178 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADD; - if (Field_imm8_Slot_ae_slot0_get (insn) == 179 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX8; - if (Field_imm8_Slot_ae_slot0_get (insn) == 180 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX2; - if (Field_imm8_Slot_ae_slot0_get (insn) == 181 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AND; - if (Field_imm8_Slot_ae_slot0_get (insn) == 182 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ANDB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 183 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ANDBC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 184 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX4; - if (Field_imm8_Slot_ae_slot0_get (insn) == 185 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_CLAMPS; - if (Field_imm8_Slot_ae_slot0_get (insn) == 186 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MAX; - if (Field_imm8_Slot_ae_slot0_get (insn) == 187 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MIN; - if (Field_imm8_Slot_ae_slot0_get (insn) == 188 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MAXU; - if (Field_imm8_Slot_ae_slot0_get (insn) == 189 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MINU; - if (Field_imm8_Slot_ae_slot0_get (insn) == 190 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVEQZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 191 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVF; - if (Field_imm8_Slot_ae_slot0_get (insn) == 194 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVGEZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 195 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ORB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 196 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVLTZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 197 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ORBC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 198 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SEXT; - if (Field_imm8_Slot_ae_slot0_get (insn) == 199 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 200 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVNEZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 201 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRLI; - if (Field_imm8_Slot_ae_slot0_get (insn) == 202 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 203 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX4; - if (Field_imm8_Slot_ae_slot0_get (insn) == 204 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX2; - if (Field_imm8_Slot_ae_slot0_get (insn) == 205 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX8; - if (Field_imm8_Slot_ae_slot0_get (insn) == 206 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_XOR; - if (Field_imm8_Slot_ae_slot0_get (insn) == 207 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_XORB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 208 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVT; - if (Field_imm8_Slot_ae_slot0_get (insn) == 224 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_OR; - if (Field_imm8_Slot_ae_slot0_get (insn) == 244 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_r32_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SQ32F_X; - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5) - return OPCODE_L32R; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP16X2F_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 6 && - Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP24F_L_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 7 && - Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP24S_L_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 8 && - Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP24X2F_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 9 && - Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP24X2S_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 10 && - Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_LQ56_C; - if (Field_r_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_BNE; - if (Field_r_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_BNONE; - if (Field_r_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L16SI; - if (Field_r_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L8UI; - if (Field_r_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_ADDI; - if (Field_r_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L16UI; - if (Field_r_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BALL; - if (Field_r_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S16I; - if (Field_r_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BANY; - if (Field_r_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S32I; - if (Field_r_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBC; - if (Field_r_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S8I; - if (Field_r_Slot_ae_slot0_get (insn) == 8 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_ADDMI; - if (Field_r_Slot_ae_slot0_get (insn) == 9 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBS; - if (Field_r_Slot_ae_slot0_get (insn) == 10 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BEQ; - if (Field_r_Slot_ae_slot0_get (insn) == 11 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BGEU; - if (Field_r_Slot_ae_slot0_get (insn) == 12 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BGE; - if (Field_r_Slot_ae_slot0_get (insn) == 13 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BLT; - if (Field_r_Slot_ae_slot0_get (insn) == 14 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BLTU; - if (Field_r_Slot_ae_slot0_get (insn) == 15 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BNALL; - if (Field_t_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BEQI; - if (Field_t_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BGEI; - if (Field_t_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BGEUI; - if (Field_t_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BNEI; - if (Field_t_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BLTI; - if (Field_t_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_r_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BF; - return 0; -} - -static int -Slot_ae_slot1_decode (const xtensa_insnbuf insn) -{ - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 288 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULRFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 289 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULRFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 290 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULARFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 291 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULARFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 292 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSRFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 293 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSRFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 294 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 295 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 296 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 297 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 298 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 299 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP24S_L; - if (Field_combined1b97e84f_fld17_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld76_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf208_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld73_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld62_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld24_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld70_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld58_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5 && - Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MINABSSQ56S; - if (Field_combined1b97e84f_fld49_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf338_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld54_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r32_Slot_ae_slot1_get (insn) == 2 && - Field_combined1b97e84f_fld51_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld23_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MINABSSP24S; - if (Field_combined1b97e84f_fld49_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf338_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld54_Slot_ae_slot1_get (insn) == 0 && - Field_ae_r32_Slot_ae_slot1_get (insn) == 2 && - Field_combined1b97e84f_fld51_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld23_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MAXABSSP24S; - if (Field_combined1b97e84f_fld54_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld17_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld76_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf208_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld73_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld62_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld24_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld70_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld58_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MAXABSSQ56S; - if (Field_ftsf100ae_slot1_Slot_ae_slot1_get (insn) == 115 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_NEGSP24S; - if (Field_ftsf101ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf348ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ABSSP24S; - if (Field_ftsf103ae_slot1_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf349ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_NEGP24; - if (Field_ftsf104ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MAXBQ56S; - if (Field_ftsf105ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MINBQ56S; - if (Field_ftsf106ae_slot1_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ae_r32_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_EQQ56; - if (Field_ftsf107ae_slot1_Slot_ae_slot1_get (insn) == 48 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ADDSQ56S; - if (Field_ftsf108ae_slot1_Slot_ae_slot1_get (insn) == 49 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ANDQ56; - if (Field_ftsf109ae_slot1_Slot_ae_slot1_get (insn) == 50 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MAXQ56S; - if (Field_ftsf110ae_slot1_Slot_ae_slot1_get (insn) == 51 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ORQ56; - if (Field_ftsf111ae_slot1_Slot_ae_slot1_get (insn) == 52 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MINQ56S; - if (Field_ftsf112ae_slot1_Slot_ae_slot1_get (insn) == 53 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_SUBQ56; - if (Field_ftsf113ae_slot1_Slot_ae_slot1_get (insn) == 54 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_SUBSQ56S; - if (Field_ftsf114ae_slot1_Slot_ae_slot1_get (insn) == 55 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_XORQ56; - if (Field_ftsf115ae_slot1_Slot_ae_slot1_get (insn) == 56 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_NANDQ56; - if (Field_ftsf116ae_slot1_Slot_ae_slot1_get (insn) == 57 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ABSQ56; - if (Field_ftsf118ae_slot1_Slot_ae_slot1_get (insn) == 185 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_NEGSQ56S; - if (Field_ftsf119ae_slot1_Slot_ae_slot1_get (insn) == 185 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf338_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_SATQ48S; - if (Field_ftsf12_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf341ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LTQ56S; - if (Field_ftsf120ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf343ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ABSSQ56S; - if (Field_ftsf122ae_slot1_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf346ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_NEGQ56; - if (Field_ftsf124ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf339ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LEQ56S; - if (Field_ftsf125ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf350ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_TRUNCP24Q48X2; - if (Field_ftsf126ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ADDQ56; - if (Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAFP24S_HH_LL; - if (Field_ftsf128ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAFP24S_HL_LH; - if (Field_ftsf129ae_slot1_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAP24S_HH_LL; - if (Field_ftsf13_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf12_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_SLLISP24S; - if (Field_ftsf130ae_slot1_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_HL; - if (Field_ftsf131ae_slot1_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAP24S_HL_LH; - if (Field_ftsf132ae_slot1_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_LH; - if (Field_ftsf133ae_slot1_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_LL; - if (Field_ftsf134ae_slot1_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_HH; - if (Field_ftsf135ae_slot1_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_HH; - if (Field_ftsf136ae_slot1_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_HL; - if (Field_ftsf137ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_LH; - if (Field_ftsf138ae_slot1_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_HH; - if (Field_ftsf139ae_slot1_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_LL; - if (Field_ftsf140ae_slot1_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_HL; - if (Field_ftsf141ae_slot1_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_LH; - if (Field_ftsf142ae_slot1_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_LL; - if (Field_ftsf143ae_slot1_Slot_ae_slot1_get (insn) == 16 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_HL; - if (Field_ftsf144ae_slot1_Slot_ae_slot1_get (insn) == 17 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_HH; - if (Field_ftsf145ae_slot1_Slot_ae_slot1_get (insn) == 18 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_HL; - if (Field_ftsf146ae_slot1_Slot_ae_slot1_get (insn) == 19 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASFP24S_HH_LL; - if (Field_ftsf147ae_slot1_Slot_ae_slot1_get (insn) == 20 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_LH; - if (Field_ftsf148ae_slot1_Slot_ae_slot1_get (insn) == 21 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASFP24S_HL_LH; - if (Field_ftsf149ae_slot1_Slot_ae_slot1_get (insn) == 22 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASP24S_HH_LL; - if (Field_ftsf150ae_slot1_Slot_ae_slot1_get (insn) == 23 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASP24S_HL_LH; - if (Field_ftsf151ae_slot1_Slot_ae_slot1_get (insn) == 24 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_LL; - if (Field_ftsf152ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_HH; - if (Field_ftsf153ae_slot1_Slot_ae_slot1_get (insn) == 26 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_HL; - if (Field_ftsf154ae_slot1_Slot_ae_slot1_get (insn) == 27 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_LL; - if (Field_ftsf155ae_slot1_Slot_ae_slot1_get (insn) == 28 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_LH; - if (Field_ftsf156ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_HH; - if (Field_ftsf157ae_slot1_Slot_ae_slot1_get (insn) == 30 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_HL; - if (Field_ftsf158ae_slot1_Slot_ae_slot1_get (insn) == 31 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_LH; - if (Field_ftsf159ae_slot1_Slot_ae_slot1_get (insn) == 32 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_LH; - if (Field_ftsf160ae_slot1_Slot_ae_slot1_get (insn) == 33 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_LL; - if (Field_ftsf161ae_slot1_Slot_ae_slot1_get (insn) == 34 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_HH; - if (Field_ftsf162ae_slot1_Slot_ae_slot1_get (insn) == 35 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAFP24S_HH_LL; - if (Field_ftsf163ae_slot1_Slot_ae_slot1_get (insn) == 36 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_HL; - if (Field_ftsf164ae_slot1_Slot_ae_slot1_get (insn) == 37 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAFP24S_HL_LH; - if (Field_ftsf165ae_slot1_Slot_ae_slot1_get (insn) == 38 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAP24S_HH_LL; - if (Field_ftsf166ae_slot1_Slot_ae_slot1_get (insn) == 39 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAP24S_HL_LH; - if (Field_ftsf167ae_slot1_Slot_ae_slot1_get (insn) == 40 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_LH; - if (Field_ftsf168ae_slot1_Slot_ae_slot1_get (insn) == 41 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_HH; - if (Field_ftsf169ae_slot1_Slot_ae_slot1_get (insn) == 42 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_HL; - if (Field_ftsf170ae_slot1_Slot_ae_slot1_get (insn) == 43 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_LL; - if (Field_ftsf171ae_slot1_Slot_ae_slot1_get (insn) == 44 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_LH; - if (Field_ftsf172ae_slot1_Slot_ae_slot1_get (insn) == 45 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_HH; - if (Field_ftsf173ae_slot1_Slot_ae_slot1_get (insn) == 46 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_HL; - if (Field_ftsf174ae_slot1_Slot_ae_slot1_get (insn) == 47 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_LH; - if (Field_ftsf175ae_slot1_Slot_ae_slot1_get (insn) == 48 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_LL; - if (Field_ftsf176ae_slot1_Slot_ae_slot1_get (insn) == 49 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_LL; - if (Field_ftsf177ae_slot1_Slot_ae_slot1_get (insn) == 50 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_HH; - if (Field_ftsf178ae_slot1_Slot_ae_slot1_get (insn) == 51 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_LL; - if (Field_ftsf179ae_slot1_Slot_ae_slot1_get (insn) == 52 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_HL; - if (Field_ftsf180ae_slot1_Slot_ae_slot1_get (insn) == 53 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_HH; - if (Field_ftsf181ae_slot1_Slot_ae_slot1_get (insn) == 54 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_HL; - if (Field_ftsf182ae_slot1_Slot_ae_slot1_get (insn) == 55 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_LH; - if (Field_ftsf183ae_slot1_Slot_ae_slot1_get (insn) == 56 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_LH; - if (Field_ftsf184ae_slot1_Slot_ae_slot1_get (insn) == 57 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_LL; - if (Field_ftsf185ae_slot1_Slot_ae_slot1_get (insn) == 58 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_HH; - if (Field_ftsf186ae_slot1_Slot_ae_slot1_get (insn) == 59 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_LH; - if (Field_ftsf187ae_slot1_Slot_ae_slot1_get (insn) == 60 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_HL; - if (Field_ftsf188ae_slot1_Slot_ae_slot1_get (insn) == 61 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_LL; - if (Field_ftsf189ae_slot1_Slot_ae_slot1_get (insn) == 62 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSFP24S_HH_LL; - if (Field_ftsf190ae_slot1_Slot_ae_slot1_get (insn) == 63 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSFP24S_HL_LH; - if (Field_ftsf191ae_slot1_Slot_ae_slot1_get (insn) == 64 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_LL; - if (Field_ftsf192ae_slot1_Slot_ae_slot1_get (insn) == 65 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSP24S_HH_LL; - if (Field_ftsf193ae_slot1_Slot_ae_slot1_get (insn) == 66 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSP24S_HL_LH; - if (Field_ftsf194ae_slot1_Slot_ae_slot1_get (insn) == 67 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASFP24S_HH_LL; - if (Field_ftsf195ae_slot1_Slot_ae_slot1_get (insn) == 68 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZAAFP24S_HH_LL; - if (Field_ftsf196ae_slot1_Slot_ae_slot1_get (insn) == 69 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASFP24S_HL_LH; - if (Field_ftsf197ae_slot1_Slot_ae_slot1_get (insn) == 70 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASP24S_HH_LL; - if (Field_ftsf198ae_slot1_Slot_ae_slot1_get (insn) == 71 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASP24S_HL_LH; - if (Field_ftsf199ae_slot1_Slot_ae_slot1_get (insn) == 72 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZAAFP24S_HL_LH; - if (Field_ftsf200ae_slot1_Slot_ae_slot1_get (insn) == 73 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAFP24S_HH_LL; - if (Field_ftsf201ae_slot1_Slot_ae_slot1_get (insn) == 74 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAFP24S_HL_LH; - if (Field_ftsf202ae_slot1_Slot_ae_slot1_get (insn) == 75 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAP24S_HL_LH; - if (Field_ftsf203ae_slot1_Slot_ae_slot1_get (insn) == 76 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAP24S_HH_LL; - if (Field_ftsf204ae_slot1_Slot_ae_slot1_get (insn) == 77 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSFP24S_HH_LL; - if (Field_ftsf205ae_slot1_Slot_ae_slot1_get (insn) == 78 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSFP24S_HL_LH; - if (Field_ftsf206ae_slot1_Slot_ae_slot1_get (insn) == 79 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSP24S_HH_LL; - if (Field_ftsf207ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZAAP24S_HH_LL; - if (Field_ftsf209ae_slot1_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZSSP24S_HL_LH; - if (Field_ftsf210ae_slot1_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf337ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZAAP24S_HL_LH; - if (Field_ftsf211ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf332ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULAFS32P16S_HH; - if (Field_ftsf21ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MAXBP24S; - if (Field_ftsf22ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MINBP24S; - if (Field_ftsf23ae_slot1_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVFP48; - if (Field_ftsf24ae_slot1_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVTP48; - if (Field_ftsf25ae_slot1_Slot_ae_slot1_get (insn) == 20 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ADDP24; - if (Field_ftsf26ae_slot1_Slot_ae_slot1_get (insn) == 21 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ANDP48; - if (Field_ftsf27ae_slot1_Slot_ae_slot1_get (insn) == 22 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MAXP24S; - if (Field_ftsf28ae_slot1_Slot_ae_slot1_get (insn) == 23 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MINP24S; - if (Field_ftsf29ae_slot1_Slot_ae_slot1_get (insn) == 24 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ADDSP24S; - if (Field_ftsf30ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_NANDP48; - if (Field_ftsf31ae_slot1_Slot_ae_slot1_get (insn) == 26 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ORP48; - if (Field_ftsf32ae_slot1_Slot_ae_slot1_get (insn) == 27 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_HL; - if (Field_ftsf33ae_slot1_Slot_ae_slot1_get (insn) == 28 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_HH; - if (Field_ftsf34ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_LH; - if (Field_ftsf35ae_slot1_Slot_ae_slot1_get (insn) == 30 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_LL; - if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 31 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SUBP24; - if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SLLIP24; - if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRAIP24; - if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRLIP24; - if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 176 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16S_L; - if (Field_ftsf39ae_slot1_Slot_ae_slot1_get (insn) == 177 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16U_H; - if (Field_ftsf40ae_slot1_Slot_ae_slot1_get (insn) == 178 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16U_L; - if (Field_ftsf41ae_slot1_Slot_ae_slot1_get (insn) == 179 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16U_H; - if (Field_ftsf42ae_slot1_Slot_ae_slot1_get (insn) == 180 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16S_H; - if (Field_ftsf43ae_slot1_Slot_ae_slot1_get (insn) == 181 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16U_L; - if (Field_ftsf44ae_slot1_Slot_ae_slot1_get (insn) == 182 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16S_H; - if (Field_ftsf45ae_slot1_Slot_ae_slot1_get (insn) == 183 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16S_L; - if (Field_ftsf46ae_slot1_Slot_ae_slot1_get (insn) == 184 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16S_L; - if (Field_ftsf47ae_slot1_Slot_ae_slot1_get (insn) == 185 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16U_H; - if (Field_ftsf48ae_slot1_Slot_ae_slot1_get (insn) == 186 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16U_L; - if (Field_ftsf49ae_slot1_Slot_ae_slot1_get (insn) == 187 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16S_L; - if (Field_ftsf50ae_slot1_Slot_ae_slot1_get (insn) == 188 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16S_H; - if (Field_ftsf51ae_slot1_Slot_ae_slot1_get (insn) == 189 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16U_H; - if (Field_ftsf52ae_slot1_Slot_ae_slot1_get (insn) == 190 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16U_L; - if (Field_ftsf53ae_slot1_Slot_ae_slot1_get (insn) == 191 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16S_H; - if (Field_ftsf54ae_slot1_Slot_ae_slot1_get (insn) == 192 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16S_H; - if (Field_ftsf55ae_slot1_Slot_ae_slot1_get (insn) == 193 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16S_L; - if (Field_ftsf56ae_slot1_Slot_ae_slot1_get (insn) == 194 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16U_H; - if (Field_ftsf57ae_slot1_Slot_ae_slot1_get (insn) == 195 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSQ32SP16U_L; - if (Field_ftsf58ae_slot1_Slot_ae_slot1_get (insn) == 196 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16U_L; - if (Field_ftsf59ae_slot1_Slot_ae_slot1_get (insn) == 773 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_CVTQ48P24S_H; - if (Field_ftsf60ae_slot1_Slot_ae_slot1_get (insn) == 789 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ZEROQ56; - if (Field_ftsf61ae_slot1_Slot_ae_slot1_get (insn) == 405 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf330ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_NOP; - if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 198 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r10_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_CVTQ48P24S_L; - if (Field_ftsf64ae_slot1_Slot_ae_slot1_get (insn) == 1543 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVQ56; - if (Field_ftsf66ae_slot1_Slot_ae_slot1_get (insn) == 1559 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSQ32ASYM; - if (Field_ftsf67ae_slot1_Slot_ae_slot1_get (insn) == 791 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSQ32SYM; - if (Field_ftsf69ae_slot1_Slot_ae_slot1_get (insn) == 407 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf340_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_TRUNCQ32; - if (Field_ftsf71ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULSQ32SP16S_H; - if (Field_ftsf72ae_slot1_Slot_ae_slot1_get (insn) == 26 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULSQ32SP16S_L; - if (Field_ftsf73ae_slot1_Slot_ae_slot1_get (insn) == 417 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVP48; - if (Field_ftsf75ae_slot1_Slot_ae_slot1_get (insn) == 419 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16ASYM; - if (Field_ftsf76ae_slot1_Slot_ae_slot1_get (insn) == 421 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16SYM; - if (Field_ftsf77ae_slot1_Slot_ae_slot1_get (insn) == 423 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRASP24; - if (Field_ftsf78ae_slot1_Slot_ae_slot1_get (insn) == 425 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SLLSP24; - if (Field_ftsf79ae_slot1_Slot_ae_slot1_get (insn) == 427 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRLSP24; - if (Field_ftsf80ae_slot1_Slot_ae_slot1_get (insn) == 429 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_TRUNCP16; - if (Field_ftsf81ae_slot1_Slot_ae_slot1_get (insn) == 431 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ZEROP48; - if (Field_ftsf82ae_slot1_Slot_ae_slot1_get (insn) == 109 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r10_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_SLLSSP24S; - if (Field_ftsf84ae_slot1_Slot_ae_slot1_get (insn) == 881 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16Q48ASYM; - if (Field_ftsf86ae_slot1_Slot_ae_slot1_get (insn) == 883 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16Q48SYM; - if (Field_ftsf87ae_slot1_Slot_ae_slot1_get (insn) == 443 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSP24Q48ASYM; - if (Field_ftsf88ae_slot1_Slot_ae_slot1_get (insn) == 223 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf340_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSP24Q48SYM; - if (Field_ftsf89ae_slot1_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf334ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULSQ32SP16U_H; - if (Field_ftsf90ae_slot1_Slot_ae_slot1_get (insn) == 96 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_EQP24; - if (Field_ftsf91ae_slot1_Slot_ae_slot1_get (insn) == 97 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_LEP24S; - if (Field_ftsf92ae_slot1_Slot_ae_slot1_get (insn) == 49 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf208_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LTP24S; - if (Field_ftsf94ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf347_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MOVFP24X2; - if (Field_ftsf96ae_slot1_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MOVTP24X2; - if (Field_ftsf97ae_slot1_Slot_ae_slot1_get (insn) == 112 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SUBSP24S; - if (Field_ftsf98ae_slot1_Slot_ae_slot1_get (insn) == 113 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_XORP48; - if (Field_ftsf99ae_slot1_Slot_ae_slot1_get (insn) == 114 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ABSP24; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_LL; - if (Field_xt_fld0_Slot_ae_slot1_get (insn) == 832 && - Field_xt_fld1_Slot_ae_slot1_get (insn) == 2) - return OPCODE_READ_IPQ; - if (Field_xt_fld0_Slot_ae_slot1_get (insn) == 832 && - Field_xt_fld1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_CHECK_IPQ; - if (Field_xt_fld0_Slot_ae_slot1_get (insn) == 832 && - Field_xt_fld1_Slot_ae_slot1_get (insn) == 3) - return OPCODE_WRITE_OPQ; - if (Field_xt_fld0_Slot_ae_slot1_get (insn) == 832 && - Field_xt_fld1_Slot_ae_slot1_get (insn) == 1) - return OPCODE_CHECK_OPQ; - return 0; -} - - -/* Instruction slots. */ - -static void -Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffffff); -} - -static void -Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); -} - -static void -Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static void -Slot_ae_format_Format_ae_slot1_31_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[0] & 0x80000000) >> 31); - slotbuf[0] = (slotbuf[0] & ~0x7ffffe) | ((insn[1] & 0x3fffff) << 1); -} - -static void -Slot_ae_format_Format_ae_slot1_31_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0x80000000) | ((slotbuf[0] & 0x1) << 31); - insn[1] = (insn[1] & ~0x3fffff) | ((slotbuf[0] & 0x7ffffe) >> 1); -} - -static void -Slot_ae_format_Format_ae_slot0_4_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[0] & 0x7ffffff0) >> 4); -} - -static void -Slot_ae_format_Format_ae_slot0_4_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0x7ffffff0) | ((slotbuf[0] & 0x7ffffff) << 4); -} - -static xtensa_get_field_fn -Slot_inst_get_field_fns[] = { - Field_t_Slot_inst_get, - Field_bbi4_Slot_inst_get, - Field_bbi_Slot_inst_get, - Field_imm12_Slot_inst_get, - Field_imm8_Slot_inst_get, - Field_s_Slot_inst_get, - Field_imm12b_Slot_inst_get, - Field_imm16_Slot_inst_get, - Field_m_Slot_inst_get, - Field_n_Slot_inst_get, - Field_offset_Slot_inst_get, - Field_op0_Slot_inst_get, - Field_op1_Slot_inst_get, - Field_op2_Slot_inst_get, - Field_r_Slot_inst_get, - Field_sa4_Slot_inst_get, - Field_sae4_Slot_inst_get, - Field_sae_Slot_inst_get, - Field_sal_Slot_inst_get, - Field_sargt_Slot_inst_get, - Field_sas4_Slot_inst_get, - Field_sas_Slot_inst_get, - Field_sr_Slot_inst_get, - Field_st_Slot_inst_get, - Field_thi3_Slot_inst_get, - Field_imm4_Slot_inst_get, - Field_mn_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst_get, - Field_s2_Slot_inst_get, - Field_r2_Slot_inst_get, - Field_t4_Slot_inst_get, - Field_s4_Slot_inst_get, - Field_r4_Slot_inst_get, - Field_t8_Slot_inst_get, - Field_s8_Slot_inst_get, - Field_r8_Slot_inst_get, - Field_xt_wbr15_imm_Slot_inst_get, - Field_xt_wbr18_imm_Slot_inst_get, - Field_ae_r3_Slot_inst_get, - Field_ae_s_non_samt_Slot_inst_get, - Field_ae_s3_Slot_inst_get, - Field_ae_r32_Slot_inst_get, - Field_ae_samt_s_t_Slot_inst_get, - Field_ae_r20_Slot_inst_get, - Field_ae_r10_Slot_inst_get, - Field_ae_s20_Slot_inst_get, - Field_ae_fld_ohba_Slot_inst_get, - Field_ae_fld_ohba2_Slot_inst_get, - 0, - Field_ftsf12_Slot_inst_get, - Field_ftsf13_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst_get, - Field_s3to1_Slot_inst_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst_set_field_fns[] = { - Field_t_Slot_inst_set, - Field_bbi4_Slot_inst_set, - Field_bbi_Slot_inst_set, - Field_imm12_Slot_inst_set, - Field_imm8_Slot_inst_set, - Field_s_Slot_inst_set, - Field_imm12b_Slot_inst_set, - Field_imm16_Slot_inst_set, - Field_m_Slot_inst_set, - Field_n_Slot_inst_set, - Field_offset_Slot_inst_set, - Field_op0_Slot_inst_set, - Field_op1_Slot_inst_set, - Field_op2_Slot_inst_set, - Field_r_Slot_inst_set, - Field_sa4_Slot_inst_set, - Field_sae4_Slot_inst_set, - Field_sae_Slot_inst_set, - Field_sal_Slot_inst_set, - Field_sargt_Slot_inst_set, - Field_sas4_Slot_inst_set, - Field_sas_Slot_inst_set, - Field_sr_Slot_inst_set, - Field_st_Slot_inst_set, - Field_thi3_Slot_inst_set, - Field_imm4_Slot_inst_set, - Field_mn_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst_set, - Field_s2_Slot_inst_set, - Field_r2_Slot_inst_set, - Field_t4_Slot_inst_set, - Field_s4_Slot_inst_set, - Field_r4_Slot_inst_set, - Field_t8_Slot_inst_set, - Field_s8_Slot_inst_set, - Field_r8_Slot_inst_set, - Field_xt_wbr15_imm_Slot_inst_set, - Field_xt_wbr18_imm_Slot_inst_set, - Field_ae_r3_Slot_inst_set, - Field_ae_s_non_samt_Slot_inst_set, - Field_ae_s3_Slot_inst_set, - Field_ae_r32_Slot_inst_set, - Field_ae_samt_s_t_Slot_inst_set, - Field_ae_r20_Slot_inst_set, - Field_ae_r10_Slot_inst_set, - Field_ae_s20_Slot_inst_set, - Field_ae_fld_ohba_Slot_inst_set, - Field_ae_fld_ohba2_Slot_inst_set, - 0, - Field_ftsf12_Slot_inst_set, - Field_ftsf13_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst_set, - Field_s3to1_Slot_inst_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16a_get_field_fns[] = { - Field_t_Slot_inst16a_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_get, - 0, - 0, - Field_r_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_get, - Field_st_Slot_inst16a_get, - 0, - Field_imm4_Slot_inst16a_get, - 0, - Field_i_Slot_inst16a_get, - Field_imm6lo_Slot_inst16a_get, - Field_imm6hi_Slot_inst16a_get, - Field_imm7lo_Slot_inst16a_get, - Field_imm7hi_Slot_inst16a_get, - Field_z_Slot_inst16a_get, - Field_imm6_Slot_inst16a_get, - Field_imm7_Slot_inst16a_get, - Field_t2_Slot_inst16a_get, - Field_s2_Slot_inst16a_get, - Field_r2_Slot_inst16a_get, - Field_t4_Slot_inst16a_get, - Field_s4_Slot_inst16a_get, - Field_r4_Slot_inst16a_get, - Field_t8_Slot_inst16a_get, - Field_s8_Slot_inst16a_get, - Field_r8_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16a_get, - Field_s3to1_Slot_inst16a_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst16a_set_field_fns[] = { - Field_t_Slot_inst16a_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_set, - 0, - 0, - Field_r_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_set, - Field_st_Slot_inst16a_set, - 0, - Field_imm4_Slot_inst16a_set, - 0, - Field_i_Slot_inst16a_set, - Field_imm6lo_Slot_inst16a_set, - Field_imm6hi_Slot_inst16a_set, - Field_imm7lo_Slot_inst16a_set, - Field_imm7hi_Slot_inst16a_set, - Field_z_Slot_inst16a_set, - Field_imm6_Slot_inst16a_set, - Field_imm7_Slot_inst16a_set, - Field_t2_Slot_inst16a_set, - Field_s2_Slot_inst16a_set, - Field_r2_Slot_inst16a_set, - Field_t4_Slot_inst16a_set, - Field_s4_Slot_inst16a_set, - Field_r4_Slot_inst16a_set, - Field_t8_Slot_inst16a_set, - Field_s8_Slot_inst16a_set, - Field_r8_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16a_set, - Field_s3to1_Slot_inst16a_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16b_get_field_fns[] = { - Field_t_Slot_inst16b_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_get, - 0, - 0, - Field_r_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_get, - Field_st_Slot_inst16b_get, - 0, - Field_imm4_Slot_inst16b_get, - 0, - Field_i_Slot_inst16b_get, - Field_imm6lo_Slot_inst16b_get, - Field_imm6hi_Slot_inst16b_get, - Field_imm7lo_Slot_inst16b_get, - Field_imm7hi_Slot_inst16b_get, - Field_z_Slot_inst16b_get, - Field_imm6_Slot_inst16b_get, - Field_imm7_Slot_inst16b_get, - Field_t2_Slot_inst16b_get, - Field_s2_Slot_inst16b_get, - Field_r2_Slot_inst16b_get, - Field_t4_Slot_inst16b_get, - Field_s4_Slot_inst16b_get, - Field_r4_Slot_inst16b_get, - Field_t8_Slot_inst16b_get, - Field_s8_Slot_inst16b_get, - Field_r8_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16b_get, - Field_s3to1_Slot_inst16b_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst16b_set_field_fns[] = { - Field_t_Slot_inst16b_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_set, - 0, - 0, - Field_r_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_set, - Field_st_Slot_inst16b_set, - 0, - Field_imm4_Slot_inst16b_set, - 0, - Field_i_Slot_inst16b_set, - Field_imm6lo_Slot_inst16b_set, - Field_imm6hi_Slot_inst16b_set, - Field_imm7lo_Slot_inst16b_set, - Field_imm7hi_Slot_inst16b_set, - Field_z_Slot_inst16b_set, - Field_imm6_Slot_inst16b_set, - Field_imm7_Slot_inst16b_set, - Field_t2_Slot_inst16b_set, - Field_s2_Slot_inst16b_set, - Field_r2_Slot_inst16b_set, - Field_t4_Slot_inst16b_set, - Field_s4_Slot_inst16b_set, - Field_r4_Slot_inst16b_set, - Field_t8_Slot_inst16b_set, - Field_s8_Slot_inst16b_set, - Field_r8_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16b_set, - Field_s3to1_Slot_inst16b_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_ae_slot1_get_field_fns[] = { - Field_t_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot1_get, - 0, - Field_ae_r20_Slot_ae_slot1_get, - Field_ae_r10_Slot_ae_slot1_get, - Field_ae_s20_Slot_ae_slot1_get, - 0, - 0, - Field_op0_s3_Slot_ae_slot1_get, - Field_ftsf12_Slot_ae_slot1_get, - Field_ftsf13_Slot_ae_slot1_get, - Field_ftsf14_Slot_ae_slot1_get, - Field_ftsf21ae_slot1_Slot_ae_slot1_get, - Field_ftsf22ae_slot1_Slot_ae_slot1_get, - Field_ftsf23ae_slot1_Slot_ae_slot1_get, - Field_ftsf24ae_slot1_Slot_ae_slot1_get, - Field_ftsf25ae_slot1_Slot_ae_slot1_get, - Field_ftsf26ae_slot1_Slot_ae_slot1_get, - Field_ftsf27ae_slot1_Slot_ae_slot1_get, - Field_ftsf28ae_slot1_Slot_ae_slot1_get, - Field_ftsf29ae_slot1_Slot_ae_slot1_get, - Field_ftsf30ae_slot1_Slot_ae_slot1_get, - Field_ftsf31ae_slot1_Slot_ae_slot1_get, - Field_ftsf32ae_slot1_Slot_ae_slot1_get, - Field_ftsf33ae_slot1_Slot_ae_slot1_get, - Field_ftsf34ae_slot1_Slot_ae_slot1_get, - Field_ftsf35ae_slot1_Slot_ae_slot1_get, - Field_ftsf36ae_slot1_Slot_ae_slot1_get, - Field_ftsf37ae_slot1_Slot_ae_slot1_get, - Field_ftsf38ae_slot1_Slot_ae_slot1_get, - Field_ftsf39ae_slot1_Slot_ae_slot1_get, - Field_ftsf40ae_slot1_Slot_ae_slot1_get, - Field_ftsf41ae_slot1_Slot_ae_slot1_get, - Field_ftsf42ae_slot1_Slot_ae_slot1_get, - Field_ftsf43ae_slot1_Slot_ae_slot1_get, - Field_ftsf44ae_slot1_Slot_ae_slot1_get, - Field_ftsf45ae_slot1_Slot_ae_slot1_get, - Field_ftsf46ae_slot1_Slot_ae_slot1_get, - Field_ftsf47ae_slot1_Slot_ae_slot1_get, - Field_ftsf48ae_slot1_Slot_ae_slot1_get, - Field_ftsf49ae_slot1_Slot_ae_slot1_get, - Field_ftsf50ae_slot1_Slot_ae_slot1_get, - Field_ftsf51ae_slot1_Slot_ae_slot1_get, - Field_ftsf52ae_slot1_Slot_ae_slot1_get, - Field_ftsf53ae_slot1_Slot_ae_slot1_get, - Field_ftsf54ae_slot1_Slot_ae_slot1_get, - Field_ftsf55ae_slot1_Slot_ae_slot1_get, - Field_ftsf56ae_slot1_Slot_ae_slot1_get, - Field_ftsf57ae_slot1_Slot_ae_slot1_get, - Field_ftsf58ae_slot1_Slot_ae_slot1_get, - Field_ftsf59ae_slot1_Slot_ae_slot1_get, - Field_ftsf60ae_slot1_Slot_ae_slot1_get, - Field_ftsf61ae_slot1_Slot_ae_slot1_get, - Field_ftsf63ae_slot1_Slot_ae_slot1_get, - Field_ftsf64ae_slot1_Slot_ae_slot1_get, - Field_ftsf66ae_slot1_Slot_ae_slot1_get, - Field_ftsf67ae_slot1_Slot_ae_slot1_get, - Field_ftsf69ae_slot1_Slot_ae_slot1_get, - Field_ftsf71ae_slot1_Slot_ae_slot1_get, - Field_ftsf72ae_slot1_Slot_ae_slot1_get, - Field_ftsf73ae_slot1_Slot_ae_slot1_get, - Field_ftsf75ae_slot1_Slot_ae_slot1_get, - Field_ftsf76ae_slot1_Slot_ae_slot1_get, - Field_ftsf77ae_slot1_Slot_ae_slot1_get, - Field_ftsf78ae_slot1_Slot_ae_slot1_get, - Field_ftsf79ae_slot1_Slot_ae_slot1_get, - Field_ftsf80ae_slot1_Slot_ae_slot1_get, - Field_ftsf81ae_slot1_Slot_ae_slot1_get, - Field_ftsf82ae_slot1_Slot_ae_slot1_get, - Field_ftsf84ae_slot1_Slot_ae_slot1_get, - Field_ftsf86ae_slot1_Slot_ae_slot1_get, - Field_ftsf87ae_slot1_Slot_ae_slot1_get, - Field_ftsf88ae_slot1_Slot_ae_slot1_get, - Field_ftsf89ae_slot1_Slot_ae_slot1_get, - Field_ftsf90ae_slot1_Slot_ae_slot1_get, - Field_ftsf91ae_slot1_Slot_ae_slot1_get, - Field_ftsf92ae_slot1_Slot_ae_slot1_get, - Field_ftsf94ae_slot1_Slot_ae_slot1_get, - Field_ftsf96ae_slot1_Slot_ae_slot1_get, - Field_ftsf97ae_slot1_Slot_ae_slot1_get, - Field_ftsf98ae_slot1_Slot_ae_slot1_get, - Field_ftsf99ae_slot1_Slot_ae_slot1_get, - Field_ftsf100ae_slot1_Slot_ae_slot1_get, - Field_ftsf101ae_slot1_Slot_ae_slot1_get, - Field_ftsf103ae_slot1_Slot_ae_slot1_get, - Field_ftsf104ae_slot1_Slot_ae_slot1_get, - Field_ftsf105ae_slot1_Slot_ae_slot1_get, - Field_ftsf106ae_slot1_Slot_ae_slot1_get, - Field_ftsf107ae_slot1_Slot_ae_slot1_get, - Field_ftsf108ae_slot1_Slot_ae_slot1_get, - Field_ftsf109ae_slot1_Slot_ae_slot1_get, - Field_ftsf110ae_slot1_Slot_ae_slot1_get, - Field_ftsf111ae_slot1_Slot_ae_slot1_get, - Field_ftsf112ae_slot1_Slot_ae_slot1_get, - Field_ftsf113ae_slot1_Slot_ae_slot1_get, - Field_ftsf114ae_slot1_Slot_ae_slot1_get, - Field_ftsf115ae_slot1_Slot_ae_slot1_get, - Field_ftsf116ae_slot1_Slot_ae_slot1_get, - Field_ftsf118ae_slot1_Slot_ae_slot1_get, - Field_ftsf119ae_slot1_Slot_ae_slot1_get, - Field_ftsf120ae_slot1_Slot_ae_slot1_get, - Field_ftsf122ae_slot1_Slot_ae_slot1_get, - Field_ftsf124ae_slot1_Slot_ae_slot1_get, - Field_ftsf125ae_slot1_Slot_ae_slot1_get, - Field_ftsf126ae_slot1_Slot_ae_slot1_get, - Field_ftsf127ae_slot1_Slot_ae_slot1_get, - Field_ftsf128ae_slot1_Slot_ae_slot1_get, - Field_ftsf129ae_slot1_Slot_ae_slot1_get, - Field_ftsf130ae_slot1_Slot_ae_slot1_get, - Field_ftsf131ae_slot1_Slot_ae_slot1_get, - Field_ftsf132ae_slot1_Slot_ae_slot1_get, - Field_ftsf133ae_slot1_Slot_ae_slot1_get, - Field_ftsf134ae_slot1_Slot_ae_slot1_get, - Field_ftsf135ae_slot1_Slot_ae_slot1_get, - Field_ftsf136ae_slot1_Slot_ae_slot1_get, - Field_ftsf137ae_slot1_Slot_ae_slot1_get, - Field_ftsf138ae_slot1_Slot_ae_slot1_get, - Field_ftsf139ae_slot1_Slot_ae_slot1_get, - Field_ftsf140ae_slot1_Slot_ae_slot1_get, - Field_ftsf141ae_slot1_Slot_ae_slot1_get, - Field_ftsf142ae_slot1_Slot_ae_slot1_get, - Field_ftsf143ae_slot1_Slot_ae_slot1_get, - Field_ftsf144ae_slot1_Slot_ae_slot1_get, - Field_ftsf145ae_slot1_Slot_ae_slot1_get, - Field_ftsf146ae_slot1_Slot_ae_slot1_get, - Field_ftsf147ae_slot1_Slot_ae_slot1_get, - Field_ftsf148ae_slot1_Slot_ae_slot1_get, - Field_ftsf149ae_slot1_Slot_ae_slot1_get, - Field_ftsf150ae_slot1_Slot_ae_slot1_get, - Field_ftsf151ae_slot1_Slot_ae_slot1_get, - Field_ftsf152ae_slot1_Slot_ae_slot1_get, - Field_ftsf153ae_slot1_Slot_ae_slot1_get, - Field_ftsf154ae_slot1_Slot_ae_slot1_get, - Field_ftsf155ae_slot1_Slot_ae_slot1_get, - Field_ftsf156ae_slot1_Slot_ae_slot1_get, - Field_ftsf157ae_slot1_Slot_ae_slot1_get, - Field_ftsf158ae_slot1_Slot_ae_slot1_get, - Field_ftsf159ae_slot1_Slot_ae_slot1_get, - Field_ftsf160ae_slot1_Slot_ae_slot1_get, - Field_ftsf161ae_slot1_Slot_ae_slot1_get, - Field_ftsf162ae_slot1_Slot_ae_slot1_get, - Field_ftsf163ae_slot1_Slot_ae_slot1_get, - Field_ftsf164ae_slot1_Slot_ae_slot1_get, - Field_ftsf165ae_slot1_Slot_ae_slot1_get, - Field_ftsf166ae_slot1_Slot_ae_slot1_get, - Field_ftsf167ae_slot1_Slot_ae_slot1_get, - Field_ftsf168ae_slot1_Slot_ae_slot1_get, - Field_ftsf169ae_slot1_Slot_ae_slot1_get, - Field_ftsf170ae_slot1_Slot_ae_slot1_get, - Field_ftsf171ae_slot1_Slot_ae_slot1_get, - Field_ftsf172ae_slot1_Slot_ae_slot1_get, - Field_ftsf173ae_slot1_Slot_ae_slot1_get, - Field_ftsf174ae_slot1_Slot_ae_slot1_get, - Field_ftsf175ae_slot1_Slot_ae_slot1_get, - Field_ftsf176ae_slot1_Slot_ae_slot1_get, - Field_ftsf177ae_slot1_Slot_ae_slot1_get, - Field_ftsf178ae_slot1_Slot_ae_slot1_get, - Field_ftsf179ae_slot1_Slot_ae_slot1_get, - Field_ftsf180ae_slot1_Slot_ae_slot1_get, - Field_ftsf181ae_slot1_Slot_ae_slot1_get, - Field_ftsf182ae_slot1_Slot_ae_slot1_get, - Field_ftsf183ae_slot1_Slot_ae_slot1_get, - Field_ftsf184ae_slot1_Slot_ae_slot1_get, - Field_ftsf185ae_slot1_Slot_ae_slot1_get, - Field_ftsf186ae_slot1_Slot_ae_slot1_get, - Field_ftsf187ae_slot1_Slot_ae_slot1_get, - Field_ftsf188ae_slot1_Slot_ae_slot1_get, - Field_ftsf189ae_slot1_Slot_ae_slot1_get, - Field_ftsf190ae_slot1_Slot_ae_slot1_get, - Field_ftsf191ae_slot1_Slot_ae_slot1_get, - Field_ftsf192ae_slot1_Slot_ae_slot1_get, - Field_ftsf193ae_slot1_Slot_ae_slot1_get, - Field_ftsf194ae_slot1_Slot_ae_slot1_get, - Field_ftsf195ae_slot1_Slot_ae_slot1_get, - Field_ftsf196ae_slot1_Slot_ae_slot1_get, - Field_ftsf197ae_slot1_Slot_ae_slot1_get, - Field_ftsf198ae_slot1_Slot_ae_slot1_get, - Field_ftsf199ae_slot1_Slot_ae_slot1_get, - Field_ftsf200ae_slot1_Slot_ae_slot1_get, - Field_ftsf201ae_slot1_Slot_ae_slot1_get, - Field_ftsf202ae_slot1_Slot_ae_slot1_get, - Field_ftsf203ae_slot1_Slot_ae_slot1_get, - Field_ftsf204ae_slot1_Slot_ae_slot1_get, - Field_ftsf205ae_slot1_Slot_ae_slot1_get, - Field_ftsf206ae_slot1_Slot_ae_slot1_get, - Field_ftsf207ae_slot1_Slot_ae_slot1_get, - Field_ftsf208_Slot_ae_slot1_get, - Field_ftsf209ae_slot1_Slot_ae_slot1_get, - Field_ftsf210ae_slot1_Slot_ae_slot1_get, - Field_ftsf211ae_slot1_Slot_ae_slot1_get, - Field_ftsf330ae_slot1_Slot_ae_slot1_get, - Field_ftsf332ae_slot1_Slot_ae_slot1_get, - Field_ftsf334ae_slot1_Slot_ae_slot1_get, - Field_ftsf336ae_slot1_Slot_ae_slot1_get, - Field_ftsf337ae_slot1_Slot_ae_slot1_get, - Field_ftsf338_Slot_ae_slot1_get, - Field_ftsf339ae_slot1_Slot_ae_slot1_get, - Field_ftsf340_Slot_ae_slot1_get, - Field_ftsf341ae_slot1_Slot_ae_slot1_get, - Field_ftsf342ae_slot1_Slot_ae_slot1_get, - Field_ftsf343ae_slot1_Slot_ae_slot1_get, - Field_ftsf344ae_slot1_Slot_ae_slot1_get, - Field_ftsf346ae_slot1_Slot_ae_slot1_get, - Field_ftsf347_Slot_ae_slot1_get, - Field_ftsf348ae_slot1_Slot_ae_slot1_get, - Field_ftsf349ae_slot1_Slot_ae_slot1_get, - Field_ftsf350ae_slot1_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_mul32x24fld_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_combined1b97e84f_fld54_Slot_ae_slot1_get, - Field_combined1b97e84f_fld17_Slot_ae_slot1_get, - Field_combined1b97e84f_fld76_Slot_ae_slot1_get, - Field_combined1b97e84f_fld73_Slot_ae_slot1_get, - Field_combined1b97e84f_fld62_Slot_ae_slot1_get, - Field_combined1b97e84f_fld24_Slot_ae_slot1_get, - Field_combined1b97e84f_fld70_Slot_ae_slot1_get, - Field_combined1b97e84f_fld58_Slot_ae_slot1_get, - Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_get, - Field_op0_s3_s3_Slot_ae_slot1_get, - Field_combined1b97e84f_fld49_Slot_ae_slot1_get, - Field_combined1b97e84f_fld51_Slot_ae_slot1_get, - Field_combined1b97e84f_fld23_Slot_ae_slot1_get, - Field_xt_fld0_Slot_ae_slot1_get, - Field_xt_fld1_Slot_ae_slot1_get, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_ae_slot1_set_field_fns[] = { - Field_t_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot1_set, - 0, - Field_ae_r20_Slot_ae_slot1_set, - Field_ae_r10_Slot_ae_slot1_set, - Field_ae_s20_Slot_ae_slot1_set, - 0, - 0, - Field_op0_s3_Slot_ae_slot1_set, - Field_ftsf12_Slot_ae_slot1_set, - Field_ftsf13_Slot_ae_slot1_set, - Field_ftsf14_Slot_ae_slot1_set, - Field_ftsf21ae_slot1_Slot_ae_slot1_set, - Field_ftsf22ae_slot1_Slot_ae_slot1_set, - Field_ftsf23ae_slot1_Slot_ae_slot1_set, - Field_ftsf24ae_slot1_Slot_ae_slot1_set, - Field_ftsf25ae_slot1_Slot_ae_slot1_set, - Field_ftsf26ae_slot1_Slot_ae_slot1_set, - Field_ftsf27ae_slot1_Slot_ae_slot1_set, - Field_ftsf28ae_slot1_Slot_ae_slot1_set, - Field_ftsf29ae_slot1_Slot_ae_slot1_set, - Field_ftsf30ae_slot1_Slot_ae_slot1_set, - Field_ftsf31ae_slot1_Slot_ae_slot1_set, - Field_ftsf32ae_slot1_Slot_ae_slot1_set, - Field_ftsf33ae_slot1_Slot_ae_slot1_set, - Field_ftsf34ae_slot1_Slot_ae_slot1_set, - Field_ftsf35ae_slot1_Slot_ae_slot1_set, - Field_ftsf36ae_slot1_Slot_ae_slot1_set, - Field_ftsf37ae_slot1_Slot_ae_slot1_set, - Field_ftsf38ae_slot1_Slot_ae_slot1_set, - Field_ftsf39ae_slot1_Slot_ae_slot1_set, - Field_ftsf40ae_slot1_Slot_ae_slot1_set, - Field_ftsf41ae_slot1_Slot_ae_slot1_set, - Field_ftsf42ae_slot1_Slot_ae_slot1_set, - Field_ftsf43ae_slot1_Slot_ae_slot1_set, - Field_ftsf44ae_slot1_Slot_ae_slot1_set, - Field_ftsf45ae_slot1_Slot_ae_slot1_set, - Field_ftsf46ae_slot1_Slot_ae_slot1_set, - Field_ftsf47ae_slot1_Slot_ae_slot1_set, - Field_ftsf48ae_slot1_Slot_ae_slot1_set, - Field_ftsf49ae_slot1_Slot_ae_slot1_set, - Field_ftsf50ae_slot1_Slot_ae_slot1_set, - Field_ftsf51ae_slot1_Slot_ae_slot1_set, - Field_ftsf52ae_slot1_Slot_ae_slot1_set, - Field_ftsf53ae_slot1_Slot_ae_slot1_set, - Field_ftsf54ae_slot1_Slot_ae_slot1_set, - Field_ftsf55ae_slot1_Slot_ae_slot1_set, - Field_ftsf56ae_slot1_Slot_ae_slot1_set, - Field_ftsf57ae_slot1_Slot_ae_slot1_set, - Field_ftsf58ae_slot1_Slot_ae_slot1_set, - Field_ftsf59ae_slot1_Slot_ae_slot1_set, - Field_ftsf60ae_slot1_Slot_ae_slot1_set, - Field_ftsf61ae_slot1_Slot_ae_slot1_set, - Field_ftsf63ae_slot1_Slot_ae_slot1_set, - Field_ftsf64ae_slot1_Slot_ae_slot1_set, - Field_ftsf66ae_slot1_Slot_ae_slot1_set, - Field_ftsf67ae_slot1_Slot_ae_slot1_set, - Field_ftsf69ae_slot1_Slot_ae_slot1_set, - Field_ftsf71ae_slot1_Slot_ae_slot1_set, - Field_ftsf72ae_slot1_Slot_ae_slot1_set, - Field_ftsf73ae_slot1_Slot_ae_slot1_set, - Field_ftsf75ae_slot1_Slot_ae_slot1_set, - Field_ftsf76ae_slot1_Slot_ae_slot1_set, - Field_ftsf77ae_slot1_Slot_ae_slot1_set, - Field_ftsf78ae_slot1_Slot_ae_slot1_set, - Field_ftsf79ae_slot1_Slot_ae_slot1_set, - Field_ftsf80ae_slot1_Slot_ae_slot1_set, - Field_ftsf81ae_slot1_Slot_ae_slot1_set, - Field_ftsf82ae_slot1_Slot_ae_slot1_set, - Field_ftsf84ae_slot1_Slot_ae_slot1_set, - Field_ftsf86ae_slot1_Slot_ae_slot1_set, - Field_ftsf87ae_slot1_Slot_ae_slot1_set, - Field_ftsf88ae_slot1_Slot_ae_slot1_set, - Field_ftsf89ae_slot1_Slot_ae_slot1_set, - Field_ftsf90ae_slot1_Slot_ae_slot1_set, - Field_ftsf91ae_slot1_Slot_ae_slot1_set, - Field_ftsf92ae_slot1_Slot_ae_slot1_set, - Field_ftsf94ae_slot1_Slot_ae_slot1_set, - Field_ftsf96ae_slot1_Slot_ae_slot1_set, - Field_ftsf97ae_slot1_Slot_ae_slot1_set, - Field_ftsf98ae_slot1_Slot_ae_slot1_set, - Field_ftsf99ae_slot1_Slot_ae_slot1_set, - Field_ftsf100ae_slot1_Slot_ae_slot1_set, - Field_ftsf101ae_slot1_Slot_ae_slot1_set, - Field_ftsf103ae_slot1_Slot_ae_slot1_set, - Field_ftsf104ae_slot1_Slot_ae_slot1_set, - Field_ftsf105ae_slot1_Slot_ae_slot1_set, - Field_ftsf106ae_slot1_Slot_ae_slot1_set, - Field_ftsf107ae_slot1_Slot_ae_slot1_set, - Field_ftsf108ae_slot1_Slot_ae_slot1_set, - Field_ftsf109ae_slot1_Slot_ae_slot1_set, - Field_ftsf110ae_slot1_Slot_ae_slot1_set, - Field_ftsf111ae_slot1_Slot_ae_slot1_set, - Field_ftsf112ae_slot1_Slot_ae_slot1_set, - Field_ftsf113ae_slot1_Slot_ae_slot1_set, - Field_ftsf114ae_slot1_Slot_ae_slot1_set, - Field_ftsf115ae_slot1_Slot_ae_slot1_set, - Field_ftsf116ae_slot1_Slot_ae_slot1_set, - Field_ftsf118ae_slot1_Slot_ae_slot1_set, - Field_ftsf119ae_slot1_Slot_ae_slot1_set, - Field_ftsf120ae_slot1_Slot_ae_slot1_set, - Field_ftsf122ae_slot1_Slot_ae_slot1_set, - Field_ftsf124ae_slot1_Slot_ae_slot1_set, - Field_ftsf125ae_slot1_Slot_ae_slot1_set, - Field_ftsf126ae_slot1_Slot_ae_slot1_set, - Field_ftsf127ae_slot1_Slot_ae_slot1_set, - Field_ftsf128ae_slot1_Slot_ae_slot1_set, - Field_ftsf129ae_slot1_Slot_ae_slot1_set, - Field_ftsf130ae_slot1_Slot_ae_slot1_set, - Field_ftsf131ae_slot1_Slot_ae_slot1_set, - Field_ftsf132ae_slot1_Slot_ae_slot1_set, - Field_ftsf133ae_slot1_Slot_ae_slot1_set, - Field_ftsf134ae_slot1_Slot_ae_slot1_set, - Field_ftsf135ae_slot1_Slot_ae_slot1_set, - Field_ftsf136ae_slot1_Slot_ae_slot1_set, - Field_ftsf137ae_slot1_Slot_ae_slot1_set, - Field_ftsf138ae_slot1_Slot_ae_slot1_set, - Field_ftsf139ae_slot1_Slot_ae_slot1_set, - Field_ftsf140ae_slot1_Slot_ae_slot1_set, - Field_ftsf141ae_slot1_Slot_ae_slot1_set, - Field_ftsf142ae_slot1_Slot_ae_slot1_set, - Field_ftsf143ae_slot1_Slot_ae_slot1_set, - Field_ftsf144ae_slot1_Slot_ae_slot1_set, - Field_ftsf145ae_slot1_Slot_ae_slot1_set, - Field_ftsf146ae_slot1_Slot_ae_slot1_set, - Field_ftsf147ae_slot1_Slot_ae_slot1_set, - Field_ftsf148ae_slot1_Slot_ae_slot1_set, - Field_ftsf149ae_slot1_Slot_ae_slot1_set, - Field_ftsf150ae_slot1_Slot_ae_slot1_set, - Field_ftsf151ae_slot1_Slot_ae_slot1_set, - Field_ftsf152ae_slot1_Slot_ae_slot1_set, - Field_ftsf153ae_slot1_Slot_ae_slot1_set, - Field_ftsf154ae_slot1_Slot_ae_slot1_set, - Field_ftsf155ae_slot1_Slot_ae_slot1_set, - Field_ftsf156ae_slot1_Slot_ae_slot1_set, - Field_ftsf157ae_slot1_Slot_ae_slot1_set, - Field_ftsf158ae_slot1_Slot_ae_slot1_set, - Field_ftsf159ae_slot1_Slot_ae_slot1_set, - Field_ftsf160ae_slot1_Slot_ae_slot1_set, - Field_ftsf161ae_slot1_Slot_ae_slot1_set, - Field_ftsf162ae_slot1_Slot_ae_slot1_set, - Field_ftsf163ae_slot1_Slot_ae_slot1_set, - Field_ftsf164ae_slot1_Slot_ae_slot1_set, - Field_ftsf165ae_slot1_Slot_ae_slot1_set, - Field_ftsf166ae_slot1_Slot_ae_slot1_set, - Field_ftsf167ae_slot1_Slot_ae_slot1_set, - Field_ftsf168ae_slot1_Slot_ae_slot1_set, - Field_ftsf169ae_slot1_Slot_ae_slot1_set, - Field_ftsf170ae_slot1_Slot_ae_slot1_set, - Field_ftsf171ae_slot1_Slot_ae_slot1_set, - Field_ftsf172ae_slot1_Slot_ae_slot1_set, - Field_ftsf173ae_slot1_Slot_ae_slot1_set, - Field_ftsf174ae_slot1_Slot_ae_slot1_set, - Field_ftsf175ae_slot1_Slot_ae_slot1_set, - Field_ftsf176ae_slot1_Slot_ae_slot1_set, - Field_ftsf177ae_slot1_Slot_ae_slot1_set, - Field_ftsf178ae_slot1_Slot_ae_slot1_set, - Field_ftsf179ae_slot1_Slot_ae_slot1_set, - Field_ftsf180ae_slot1_Slot_ae_slot1_set, - Field_ftsf181ae_slot1_Slot_ae_slot1_set, - Field_ftsf182ae_slot1_Slot_ae_slot1_set, - Field_ftsf183ae_slot1_Slot_ae_slot1_set, - Field_ftsf184ae_slot1_Slot_ae_slot1_set, - Field_ftsf185ae_slot1_Slot_ae_slot1_set, - Field_ftsf186ae_slot1_Slot_ae_slot1_set, - Field_ftsf187ae_slot1_Slot_ae_slot1_set, - Field_ftsf188ae_slot1_Slot_ae_slot1_set, - Field_ftsf189ae_slot1_Slot_ae_slot1_set, - Field_ftsf190ae_slot1_Slot_ae_slot1_set, - Field_ftsf191ae_slot1_Slot_ae_slot1_set, - Field_ftsf192ae_slot1_Slot_ae_slot1_set, - Field_ftsf193ae_slot1_Slot_ae_slot1_set, - Field_ftsf194ae_slot1_Slot_ae_slot1_set, - Field_ftsf195ae_slot1_Slot_ae_slot1_set, - Field_ftsf196ae_slot1_Slot_ae_slot1_set, - Field_ftsf197ae_slot1_Slot_ae_slot1_set, - Field_ftsf198ae_slot1_Slot_ae_slot1_set, - Field_ftsf199ae_slot1_Slot_ae_slot1_set, - Field_ftsf200ae_slot1_Slot_ae_slot1_set, - Field_ftsf201ae_slot1_Slot_ae_slot1_set, - Field_ftsf202ae_slot1_Slot_ae_slot1_set, - Field_ftsf203ae_slot1_Slot_ae_slot1_set, - Field_ftsf204ae_slot1_Slot_ae_slot1_set, - Field_ftsf205ae_slot1_Slot_ae_slot1_set, - Field_ftsf206ae_slot1_Slot_ae_slot1_set, - Field_ftsf207ae_slot1_Slot_ae_slot1_set, - Field_ftsf208_Slot_ae_slot1_set, - Field_ftsf209ae_slot1_Slot_ae_slot1_set, - Field_ftsf210ae_slot1_Slot_ae_slot1_set, - Field_ftsf211ae_slot1_Slot_ae_slot1_set, - Field_ftsf330ae_slot1_Slot_ae_slot1_set, - Field_ftsf332ae_slot1_Slot_ae_slot1_set, - Field_ftsf334ae_slot1_Slot_ae_slot1_set, - Field_ftsf336ae_slot1_Slot_ae_slot1_set, - Field_ftsf337ae_slot1_Slot_ae_slot1_set, - Field_ftsf338_Slot_ae_slot1_set, - Field_ftsf339ae_slot1_Slot_ae_slot1_set, - Field_ftsf340_Slot_ae_slot1_set, - Field_ftsf341ae_slot1_Slot_ae_slot1_set, - Field_ftsf342ae_slot1_Slot_ae_slot1_set, - Field_ftsf343ae_slot1_Slot_ae_slot1_set, - Field_ftsf344ae_slot1_Slot_ae_slot1_set, - Field_ftsf346ae_slot1_Slot_ae_slot1_set, - Field_ftsf347_Slot_ae_slot1_set, - Field_ftsf348ae_slot1_Slot_ae_slot1_set, - Field_ftsf349ae_slot1_Slot_ae_slot1_set, - Field_ftsf350ae_slot1_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_mul32x24fld_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_combined1b97e84f_fld54_Slot_ae_slot1_set, - Field_combined1b97e84f_fld17_Slot_ae_slot1_set, - Field_combined1b97e84f_fld76_Slot_ae_slot1_set, - Field_combined1b97e84f_fld73_Slot_ae_slot1_set, - Field_combined1b97e84f_fld62_Slot_ae_slot1_set, - Field_combined1b97e84f_fld24_Slot_ae_slot1_set, - Field_combined1b97e84f_fld70_Slot_ae_slot1_set, - Field_combined1b97e84f_fld58_Slot_ae_slot1_set, - Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_set, - Field_op0_s3_s3_Slot_ae_slot1_set, - Field_combined1b97e84f_fld49_Slot_ae_slot1_set, - Field_combined1b97e84f_fld51_Slot_ae_slot1_set, - Field_combined1b97e84f_fld23_Slot_ae_slot1_set, - Field_xt_fld0_Slot_ae_slot1_set, - Field_xt_fld1_Slot_ae_slot1_set, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_ae_slot0_get_field_fns[] = { - Field_t_Slot_ae_slot0_get, - 0, - Field_bbi_Slot_ae_slot0_get, - Field_imm12_Slot_ae_slot0_get, - Field_imm8_Slot_ae_slot0_get, - Field_s_Slot_ae_slot0_get, - Field_imm12b_Slot_ae_slot0_get, - Field_imm16_Slot_ae_slot0_get, - 0, - 0, - Field_offset_Slot_ae_slot0_get, - 0, - 0, - Field_op2_Slot_ae_slot0_get, - Field_r_Slot_ae_slot0_get, - 0, - 0, - Field_sae_Slot_ae_slot0_get, - Field_sal_Slot_ae_slot0_get, - Field_sargt_Slot_ae_slot0_get, - 0, - Field_sas_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_s4_Slot_ae_slot0_get, - 0, - 0, - Field_s8_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot0_get, - Field_ae_samt_s_t_Slot_ae_slot0_get, - Field_ae_r20_Slot_ae_slot0_get, - Field_ae_r10_Slot_ae_slot0_get, - Field_ae_s20_Slot_ae_slot0_get, - 0, - 0, - 0, - Field_ftsf12_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s4_Slot_ae_slot0_get, - Field_ftsf212ae_slot0_Slot_ae_slot0_get, - Field_ftsf213ae_slot0_Slot_ae_slot0_get, - Field_ftsf214ae_slot0_Slot_ae_slot0_get, - Field_ftsf215ae_slot0_Slot_ae_slot0_get, - Field_ftsf216ae_slot0_Slot_ae_slot0_get, - Field_ftsf217_Slot_ae_slot0_get, - Field_ftsf218ae_slot0_Slot_ae_slot0_get, - Field_ftsf219ae_slot0_Slot_ae_slot0_get, - Field_ftsf220ae_slot0_Slot_ae_slot0_get, - Field_ftsf221ae_slot0_Slot_ae_slot0_get, - Field_ftsf222ae_slot0_Slot_ae_slot0_get, - Field_ftsf223ae_slot0_Slot_ae_slot0_get, - Field_ftsf224ae_slot0_Slot_ae_slot0_get, - Field_ftsf225ae_slot0_Slot_ae_slot0_get, - Field_ftsf226ae_slot0_Slot_ae_slot0_get, - Field_ftsf227ae_slot0_Slot_ae_slot0_get, - Field_ftsf228ae_slot0_Slot_ae_slot0_get, - Field_ftsf229ae_slot0_Slot_ae_slot0_get, - Field_ftsf230ae_slot0_Slot_ae_slot0_get, - Field_ftsf231ae_slot0_Slot_ae_slot0_get, - Field_ftsf232ae_slot0_Slot_ae_slot0_get, - Field_ftsf233ae_slot0_Slot_ae_slot0_get, - Field_ftsf234ae_slot0_Slot_ae_slot0_get, - Field_ftsf235ae_slot0_Slot_ae_slot0_get, - Field_ftsf236ae_slot0_Slot_ae_slot0_get, - Field_ftsf237ae_slot0_Slot_ae_slot0_get, - Field_ftsf238ae_slot0_Slot_ae_slot0_get, - Field_ftsf239ae_slot0_Slot_ae_slot0_get, - Field_ftsf240ae_slot0_Slot_ae_slot0_get, - Field_ftsf241ae_slot0_Slot_ae_slot0_get, - Field_ftsf242ae_slot0_Slot_ae_slot0_get, - Field_ftsf243ae_slot0_Slot_ae_slot0_get, - Field_ftsf244ae_slot0_Slot_ae_slot0_get, - Field_ftsf245ae_slot0_Slot_ae_slot0_get, - Field_ftsf246ae_slot0_Slot_ae_slot0_get, - Field_ftsf247ae_slot0_Slot_ae_slot0_get, - Field_ftsf248ae_slot0_Slot_ae_slot0_get, - Field_ftsf249ae_slot0_Slot_ae_slot0_get, - Field_ftsf250ae_slot0_Slot_ae_slot0_get, - Field_ftsf251ae_slot0_Slot_ae_slot0_get, - Field_ftsf252ae_slot0_Slot_ae_slot0_get, - Field_ftsf253ae_slot0_Slot_ae_slot0_get, - Field_ftsf254ae_slot0_Slot_ae_slot0_get, - Field_ftsf255ae_slot0_Slot_ae_slot0_get, - Field_ftsf256ae_slot0_Slot_ae_slot0_get, - Field_ftsf257ae_slot0_Slot_ae_slot0_get, - Field_ftsf258ae_slot0_Slot_ae_slot0_get, - Field_ftsf259ae_slot0_Slot_ae_slot0_get, - Field_ftsf260ae_slot0_Slot_ae_slot0_get, - Field_ftsf261ae_slot0_Slot_ae_slot0_get, - Field_ftsf262ae_slot0_Slot_ae_slot0_get, - Field_ftsf263ae_slot0_Slot_ae_slot0_get, - Field_ftsf264ae_slot0_Slot_ae_slot0_get, - Field_ftsf265ae_slot0_Slot_ae_slot0_get, - Field_ftsf266ae_slot0_Slot_ae_slot0_get, - Field_ftsf267ae_slot0_Slot_ae_slot0_get, - Field_ftsf268ae_slot0_Slot_ae_slot0_get, - Field_ftsf269ae_slot0_Slot_ae_slot0_get, - Field_ftsf270ae_slot0_Slot_ae_slot0_get, - Field_ftsf271ae_slot0_Slot_ae_slot0_get, - Field_ftsf272ae_slot0_Slot_ae_slot0_get, - Field_ftsf273ae_slot0_Slot_ae_slot0_get, - Field_ftsf274ae_slot0_Slot_ae_slot0_get, - Field_ftsf275ae_slot0_Slot_ae_slot0_get, - Field_ftsf276ae_slot0_Slot_ae_slot0_get, - Field_ftsf277ae_slot0_Slot_ae_slot0_get, - Field_ftsf278ae_slot0_Slot_ae_slot0_get, - Field_ftsf279ae_slot0_Slot_ae_slot0_get, - Field_ftsf281ae_slot0_Slot_ae_slot0_get, - Field_ftsf282ae_slot0_Slot_ae_slot0_get, - Field_ftsf283ae_slot0_Slot_ae_slot0_get, - Field_ftsf284ae_slot0_Slot_ae_slot0_get, - Field_ftsf286ae_slot0_Slot_ae_slot0_get, - Field_ftsf288ae_slot0_Slot_ae_slot0_get, - Field_ftsf290ae_slot0_Slot_ae_slot0_get, - Field_ftsf292ae_slot0_Slot_ae_slot0_get, - Field_ftsf293_Slot_ae_slot0_get, - Field_ftsf294ae_slot0_Slot_ae_slot0_get, - Field_ftsf295ae_slot0_Slot_ae_slot0_get, - Field_ftsf296ae_slot0_Slot_ae_slot0_get, - Field_ftsf297ae_slot0_Slot_ae_slot0_get, - Field_ftsf298ae_slot0_Slot_ae_slot0_get, - Field_ftsf299ae_slot0_Slot_ae_slot0_get, - Field_ftsf300ae_slot0_Slot_ae_slot0_get, - Field_ftsf301ae_slot0_Slot_ae_slot0_get, - Field_ftsf302ae_slot0_Slot_ae_slot0_get, - Field_ftsf303ae_slot0_Slot_ae_slot0_get, - Field_ftsf304ae_slot0_Slot_ae_slot0_get, - Field_ftsf306ae_slot0_Slot_ae_slot0_get, - Field_ftsf308ae_slot0_Slot_ae_slot0_get, - Field_ftsf309ae_slot0_Slot_ae_slot0_get, - Field_ftsf310ae_slot0_Slot_ae_slot0_get, - Field_ftsf311ae_slot0_Slot_ae_slot0_get, - Field_ftsf312ae_slot0_Slot_ae_slot0_get, - Field_ftsf313ae_slot0_Slot_ae_slot0_get, - Field_ftsf314ae_slot0_Slot_ae_slot0_get, - Field_ftsf315ae_slot0_Slot_ae_slot0_get, - Field_ftsf316ae_slot0_Slot_ae_slot0_get, - Field_ftsf317ae_slot0_Slot_ae_slot0_get, - Field_ftsf318ae_slot0_Slot_ae_slot0_get, - Field_ftsf319_Slot_ae_slot0_get, - Field_ftsf320ae_slot0_Slot_ae_slot0_get, - Field_ftsf321_Slot_ae_slot0_get, - Field_ftsf322ae_slot0_Slot_ae_slot0_get, - Field_ftsf323ae_slot0_Slot_ae_slot0_get, - Field_ftsf324ae_slot0_Slot_ae_slot0_get, - Field_ftsf325ae_slot0_Slot_ae_slot0_get, - Field_ftsf326ae_slot0_Slot_ae_slot0_get, - Field_ftsf328ae_slot0_Slot_ae_slot0_get, - Field_ftsf329ae_slot0_Slot_ae_slot0_get, - Field_ftsf352ae_slot0_Slot_ae_slot0_get, - Field_ftsf353_Slot_ae_slot0_get, - Field_ftsf354ae_slot0_Slot_ae_slot0_get, - Field_ftsf356ae_slot0_Slot_ae_slot0_get, - Field_ftsf357_Slot_ae_slot0_get, - Field_ftsf358ae_slot0_Slot_ae_slot0_get, - Field_ftsf359ae_slot0_Slot_ae_slot0_get, - Field_ftsf360ae_slot0_Slot_ae_slot0_get, - Field_ftsf361ae_slot0_Slot_ae_slot0_get, - Field_ftsf362ae_slot0_Slot_ae_slot0_get, - Field_ftsf364ae_slot0_Slot_ae_slot0_get, - Field_ftsf365ae_slot0_Slot_ae_slot0_get, - Field_ftsf366ae_slot0_Slot_ae_slot0_get, - Field_ftsf368ae_slot0_Slot_ae_slot0_get, - Field_ftsf369ae_slot0_Slot_ae_slot0_get, - 0, - Field_combined1b97e84f_fld115_Slot_ae_slot0_get, - Field_combined1b97e84f_fld97_Slot_ae_slot0_get, - Field_combined1b97e84f_fld124_Slot_ae_slot0_get, - Field_combined1b97e84f_fld79_Slot_ae_slot0_get, - Field_combined1b97e84f_fld80_Slot_ae_slot0_get, - Field_combined1b97e84f_fld108_Slot_ae_slot0_get, - Field_combined1b97e84f_fld101_Slot_ae_slot0_get, - Field_combined1b97e84f_fld88_Slot_ae_slot0_get, - Field_combined1b97e84f_fld39_Slot_ae_slot0_get, - Field_op0_s4_s4_Slot_ae_slot0_get, - Field_combined1b97e84f_fld83_Slot_ae_slot0_get, - Field_combined1b97e84f_fld90_Slot_ae_slot0_get, - Field_combined1b97e84f_fld93_Slot_ae_slot0_get, - Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_get, - Field_combined4b12daa6_fld122_Slot_ae_slot0_get, - Field_combined4b12daa6_fld115_Slot_ae_slot0_get, - Field_combined4b12daa6_fld85_Slot_ae_slot0_get, - Field_combined4b12daa6_fld119_Slot_ae_slot0_get, - Field_combined4b12daa6_fld97_Slot_ae_slot0_get, - Field_combined4b12daa6_fld124_Slot_ae_slot0_get, - Field_combined4b12daa6_fld79_Slot_ae_slot0_get, - Field_combined4b12daa6_fld80_Slot_ae_slot0_get, - Field_combined4b12daa6_fld108_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_ae_slot0_get, - Field_s3to1_Slot_ae_slot0_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_ae_slot0_set_field_fns[] = { - Field_t_Slot_ae_slot0_set, - 0, - Field_bbi_Slot_ae_slot0_set, - Field_imm12_Slot_ae_slot0_set, - Field_imm8_Slot_ae_slot0_set, - Field_s_Slot_ae_slot0_set, - Field_imm12b_Slot_ae_slot0_set, - Field_imm16_Slot_ae_slot0_set, - 0, - 0, - Field_offset_Slot_ae_slot0_set, - 0, - 0, - Field_op2_Slot_ae_slot0_set, - Field_r_Slot_ae_slot0_set, - 0, - 0, - Field_sae_Slot_ae_slot0_set, - Field_sal_Slot_ae_slot0_set, - Field_sargt_Slot_ae_slot0_set, - 0, - Field_sas_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_s4_Slot_ae_slot0_set, - 0, - 0, - Field_s8_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot0_set, - Field_ae_samt_s_t_Slot_ae_slot0_set, - Field_ae_r20_Slot_ae_slot0_set, - Field_ae_r10_Slot_ae_slot0_set, - Field_ae_s20_Slot_ae_slot0_set, - 0, - 0, - 0, - Field_ftsf12_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s4_Slot_ae_slot0_set, - Field_ftsf212ae_slot0_Slot_ae_slot0_set, - Field_ftsf213ae_slot0_Slot_ae_slot0_set, - Field_ftsf214ae_slot0_Slot_ae_slot0_set, - Field_ftsf215ae_slot0_Slot_ae_slot0_set, - Field_ftsf216ae_slot0_Slot_ae_slot0_set, - Field_ftsf217_Slot_ae_slot0_set, - Field_ftsf218ae_slot0_Slot_ae_slot0_set, - Field_ftsf219ae_slot0_Slot_ae_slot0_set, - Field_ftsf220ae_slot0_Slot_ae_slot0_set, - Field_ftsf221ae_slot0_Slot_ae_slot0_set, - Field_ftsf222ae_slot0_Slot_ae_slot0_set, - Field_ftsf223ae_slot0_Slot_ae_slot0_set, - Field_ftsf224ae_slot0_Slot_ae_slot0_set, - Field_ftsf225ae_slot0_Slot_ae_slot0_set, - Field_ftsf226ae_slot0_Slot_ae_slot0_set, - Field_ftsf227ae_slot0_Slot_ae_slot0_set, - Field_ftsf228ae_slot0_Slot_ae_slot0_set, - Field_ftsf229ae_slot0_Slot_ae_slot0_set, - Field_ftsf230ae_slot0_Slot_ae_slot0_set, - Field_ftsf231ae_slot0_Slot_ae_slot0_set, - Field_ftsf232ae_slot0_Slot_ae_slot0_set, - Field_ftsf233ae_slot0_Slot_ae_slot0_set, - Field_ftsf234ae_slot0_Slot_ae_slot0_set, - Field_ftsf235ae_slot0_Slot_ae_slot0_set, - Field_ftsf236ae_slot0_Slot_ae_slot0_set, - Field_ftsf237ae_slot0_Slot_ae_slot0_set, - Field_ftsf238ae_slot0_Slot_ae_slot0_set, - Field_ftsf239ae_slot0_Slot_ae_slot0_set, - Field_ftsf240ae_slot0_Slot_ae_slot0_set, - Field_ftsf241ae_slot0_Slot_ae_slot0_set, - Field_ftsf242ae_slot0_Slot_ae_slot0_set, - Field_ftsf243ae_slot0_Slot_ae_slot0_set, - Field_ftsf244ae_slot0_Slot_ae_slot0_set, - Field_ftsf245ae_slot0_Slot_ae_slot0_set, - Field_ftsf246ae_slot0_Slot_ae_slot0_set, - Field_ftsf247ae_slot0_Slot_ae_slot0_set, - Field_ftsf248ae_slot0_Slot_ae_slot0_set, - Field_ftsf249ae_slot0_Slot_ae_slot0_set, - Field_ftsf250ae_slot0_Slot_ae_slot0_set, - Field_ftsf251ae_slot0_Slot_ae_slot0_set, - Field_ftsf252ae_slot0_Slot_ae_slot0_set, - Field_ftsf253ae_slot0_Slot_ae_slot0_set, - Field_ftsf254ae_slot0_Slot_ae_slot0_set, - Field_ftsf255ae_slot0_Slot_ae_slot0_set, - Field_ftsf256ae_slot0_Slot_ae_slot0_set, - Field_ftsf257ae_slot0_Slot_ae_slot0_set, - Field_ftsf258ae_slot0_Slot_ae_slot0_set, - Field_ftsf259ae_slot0_Slot_ae_slot0_set, - Field_ftsf260ae_slot0_Slot_ae_slot0_set, - Field_ftsf261ae_slot0_Slot_ae_slot0_set, - Field_ftsf262ae_slot0_Slot_ae_slot0_set, - Field_ftsf263ae_slot0_Slot_ae_slot0_set, - Field_ftsf264ae_slot0_Slot_ae_slot0_set, - Field_ftsf265ae_slot0_Slot_ae_slot0_set, - Field_ftsf266ae_slot0_Slot_ae_slot0_set, - Field_ftsf267ae_slot0_Slot_ae_slot0_set, - Field_ftsf268ae_slot0_Slot_ae_slot0_set, - Field_ftsf269ae_slot0_Slot_ae_slot0_set, - Field_ftsf270ae_slot0_Slot_ae_slot0_set, - Field_ftsf271ae_slot0_Slot_ae_slot0_set, - Field_ftsf272ae_slot0_Slot_ae_slot0_set, - Field_ftsf273ae_slot0_Slot_ae_slot0_set, - Field_ftsf274ae_slot0_Slot_ae_slot0_set, - Field_ftsf275ae_slot0_Slot_ae_slot0_set, - Field_ftsf276ae_slot0_Slot_ae_slot0_set, - Field_ftsf277ae_slot0_Slot_ae_slot0_set, - Field_ftsf278ae_slot0_Slot_ae_slot0_set, - Field_ftsf279ae_slot0_Slot_ae_slot0_set, - Field_ftsf281ae_slot0_Slot_ae_slot0_set, - Field_ftsf282ae_slot0_Slot_ae_slot0_set, - Field_ftsf283ae_slot0_Slot_ae_slot0_set, - Field_ftsf284ae_slot0_Slot_ae_slot0_set, - Field_ftsf286ae_slot0_Slot_ae_slot0_set, - Field_ftsf288ae_slot0_Slot_ae_slot0_set, - Field_ftsf290ae_slot0_Slot_ae_slot0_set, - Field_ftsf292ae_slot0_Slot_ae_slot0_set, - Field_ftsf293_Slot_ae_slot0_set, - Field_ftsf294ae_slot0_Slot_ae_slot0_set, - Field_ftsf295ae_slot0_Slot_ae_slot0_set, - Field_ftsf296ae_slot0_Slot_ae_slot0_set, - Field_ftsf297ae_slot0_Slot_ae_slot0_set, - Field_ftsf298ae_slot0_Slot_ae_slot0_set, - Field_ftsf299ae_slot0_Slot_ae_slot0_set, - Field_ftsf300ae_slot0_Slot_ae_slot0_set, - Field_ftsf301ae_slot0_Slot_ae_slot0_set, - Field_ftsf302ae_slot0_Slot_ae_slot0_set, - Field_ftsf303ae_slot0_Slot_ae_slot0_set, - Field_ftsf304ae_slot0_Slot_ae_slot0_set, - Field_ftsf306ae_slot0_Slot_ae_slot0_set, - Field_ftsf308ae_slot0_Slot_ae_slot0_set, - Field_ftsf309ae_slot0_Slot_ae_slot0_set, - Field_ftsf310ae_slot0_Slot_ae_slot0_set, - Field_ftsf311ae_slot0_Slot_ae_slot0_set, - Field_ftsf312ae_slot0_Slot_ae_slot0_set, - Field_ftsf313ae_slot0_Slot_ae_slot0_set, - Field_ftsf314ae_slot0_Slot_ae_slot0_set, - Field_ftsf315ae_slot0_Slot_ae_slot0_set, - Field_ftsf316ae_slot0_Slot_ae_slot0_set, - Field_ftsf317ae_slot0_Slot_ae_slot0_set, - Field_ftsf318ae_slot0_Slot_ae_slot0_set, - Field_ftsf319_Slot_ae_slot0_set, - Field_ftsf320ae_slot0_Slot_ae_slot0_set, - Field_ftsf321_Slot_ae_slot0_set, - Field_ftsf322ae_slot0_Slot_ae_slot0_set, - Field_ftsf323ae_slot0_Slot_ae_slot0_set, - Field_ftsf324ae_slot0_Slot_ae_slot0_set, - Field_ftsf325ae_slot0_Slot_ae_slot0_set, - Field_ftsf326ae_slot0_Slot_ae_slot0_set, - Field_ftsf328ae_slot0_Slot_ae_slot0_set, - Field_ftsf329ae_slot0_Slot_ae_slot0_set, - Field_ftsf352ae_slot0_Slot_ae_slot0_set, - Field_ftsf353_Slot_ae_slot0_set, - Field_ftsf354ae_slot0_Slot_ae_slot0_set, - Field_ftsf356ae_slot0_Slot_ae_slot0_set, - Field_ftsf357_Slot_ae_slot0_set, - Field_ftsf358ae_slot0_Slot_ae_slot0_set, - Field_ftsf359ae_slot0_Slot_ae_slot0_set, - Field_ftsf360ae_slot0_Slot_ae_slot0_set, - Field_ftsf361ae_slot0_Slot_ae_slot0_set, - Field_ftsf362ae_slot0_Slot_ae_slot0_set, - Field_ftsf364ae_slot0_Slot_ae_slot0_set, - Field_ftsf365ae_slot0_Slot_ae_slot0_set, - Field_ftsf366ae_slot0_Slot_ae_slot0_set, - Field_ftsf368ae_slot0_Slot_ae_slot0_set, - Field_ftsf369ae_slot0_Slot_ae_slot0_set, - 0, - Field_combined1b97e84f_fld115_Slot_ae_slot0_set, - Field_combined1b97e84f_fld97_Slot_ae_slot0_set, - Field_combined1b97e84f_fld124_Slot_ae_slot0_set, - Field_combined1b97e84f_fld79_Slot_ae_slot0_set, - Field_combined1b97e84f_fld80_Slot_ae_slot0_set, - Field_combined1b97e84f_fld108_Slot_ae_slot0_set, - Field_combined1b97e84f_fld101_Slot_ae_slot0_set, - Field_combined1b97e84f_fld88_Slot_ae_slot0_set, - Field_combined1b97e84f_fld39_Slot_ae_slot0_set, - Field_op0_s4_s4_Slot_ae_slot0_set, - Field_combined1b97e84f_fld83_Slot_ae_slot0_set, - Field_combined1b97e84f_fld90_Slot_ae_slot0_set, - Field_combined1b97e84f_fld93_Slot_ae_slot0_set, - Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_set, - Field_combined4b12daa6_fld122_Slot_ae_slot0_set, - Field_combined4b12daa6_fld115_Slot_ae_slot0_set, - Field_combined4b12daa6_fld85_Slot_ae_slot0_set, - Field_combined4b12daa6_fld119_Slot_ae_slot0_set, - Field_combined4b12daa6_fld97_Slot_ae_slot0_set, - Field_combined4b12daa6_fld124_Slot_ae_slot0_set, - Field_combined4b12daa6_fld79_Slot_ae_slot0_set, - Field_combined4b12daa6_fld80_Slot_ae_slot0_set, - Field_combined4b12daa6_fld108_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_ae_slot0_set, - Field_s3to1_Slot_ae_slot0_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_slot_internal slots[] = { - { "Inst", "x24", 0, - Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, - Slot_inst_get_field_fns, Slot_inst_set_field_fns, - Slot_inst_decode, "nop" }, - { "Inst16a", "x16a", 0, - Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, - Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, - Slot_inst16a_decode, "" }, - { "Inst16b", "x16b", 0, - Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, - Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, - Slot_inst16b_decode, "nop.n" }, - { "ae_slot1", "ae_format", 1, - Slot_ae_format_Format_ae_slot1_31_get, Slot_ae_format_Format_ae_slot1_31_set, - Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns, - Slot_ae_slot1_decode, "nop" }, - { "ae_slot0", "ae_format", 0, - Slot_ae_format_Format_ae_slot0_4_get, Slot_ae_format_Format_ae_slot0_4_set, - Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns, - Slot_ae_slot0_decode, "nop" } -}; - - -/* Instruction formats. */ - -static void -Format_x24_encode (xtensa_insnbuf insn) -{ - insn[0] = 0; - insn[1] = 0; -} - -static void -Format_x16a_encode (xtensa_insnbuf insn) -{ - insn[0] = 0x8; - insn[1] = 0; -} - -static void -Format_x16b_encode (xtensa_insnbuf insn) -{ - insn[0] = 0xc; - insn[1] = 0; -} - -static void -Format_ae_format_encode (xtensa_insnbuf insn) -{ - insn[0] = 0xf; - insn[1] = 0; -} - -static int Format_x24_slots[] = { 0 }; - -static int Format_x16a_slots[] = { 1 }; - -static int Format_x16b_slots[] = { 2 }; - -static int Format_ae_format_slots[] = { 4, 3 }; - -static xtensa_format_internal formats[] = { - { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, - { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, - { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, - { "ae_format", 8, Format_ae_format_encode, 2, Format_ae_format_slots } -}; - - -static int -format_decoder (const xtensa_insnbuf insn) -{ - if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0) - return 0; /* x24 */ - if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0) - return 1; /* x16a */ - if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0) - return 2; /* x16b */ - if ((insn[0] & 0xf) == 0xf && (insn[1] & 0xffc00000) == 0) - return 3; /* ae_format */ - return -1; -} - -static int length_table[256] = { - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8 -}; - -static int -length_decoder (const unsigned char *insn) -{ - int l = insn[0]; - return length_table[l]; -} - - -/* Top-level ISA structure. */ - -xtensa_isa_internal xtensa_modules = { - 0 /* little-endian */, - 8 /* insn_size */, 0, - 4, formats, format_decoder, length_decoder, - 5, slots, - 439 /* num_fields */, - 504, operands, - 703, iclasses, - 778, opcodes, 0, - 8, regfiles, - NUM_STATES, states, 0, - NUM_SYSREGS, sysregs, 0, - { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, - 9, interfaces, 0, - 4, funcUnits, 0 -}; diff --git a/overlays/xtensa_intel_bdw_adsp/gdb/gdb/regformats/reg-xtensa.dat b/overlays/xtensa_intel_bdw_adsp/gdb/gdb/regformats/reg-xtensa.dat deleted file mode 100644 index c327da9..0000000 --- a/overlays/xtensa_intel_bdw_adsp/gdb/gdb/regformats/reg-xtensa.dat +++ /dev/null @@ -1,66 +0,0 @@ -name:xtensa -expedite:pc,windowbase,windowstart -32:pc -32:ar0 -32:ar1 -32:ar2 -32:ar3 -32:ar4 -32:ar5 -32:ar6 -32:ar7 -32:ar8 -32:ar9 -32:ar10 -32:ar11 -32:ar12 -32:ar13 -32:ar14 -32:ar15 -32:ar16 -32:ar17 -32:ar18 -32:ar19 -32:ar20 -32:ar21 -32:ar22 -32:ar23 -32:ar24 -32:ar25 -32:ar26 -32:ar27 -32:ar28 -32:ar29 -32:ar30 -32:ar31 -32:lbeg -32:lend -32:lcount -32:sar -32:prefctl -32:windowbase -32:windowstart -32:configid0 -32:configid1 -32:ps -32:br -32:scompare1 -32:expstate -64:aep0 -64:aep1 -64:aep2 -64:aep3 -64:aep4 -64:aep5 -64:aep6 -64:aep7 -64:aeq0 -64:aeq1 -64:aeq2 -64:aeq3 -32:ae_ovf_sar -32:ae_bithead -32:ae_ts_fts_bu_bp -32:ae_sd_no -32:ae_cbegin0 -32:ae_cend0 diff --git a/overlays/xtensa_intel_bdw_adsp/gdb/gdb/xtensa-config.c b/overlays/xtensa_intel_bdw_adsp/gdb/gdb/xtensa-config.c deleted file mode 100644 index 1875e69..0000000 --- a/overlays/xtensa_intel_bdw_adsp/gdb/gdb/xtensa-config.c +++ /dev/null @@ -1,305 +0,0 @@ -/* Configuration for the Xtensa architecture for GDB, the GNU debugger. - - Customer ID=4313; Build=0x5483e; Copyright (c) 2003-2015 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#define XTENSA_CONFIG_VERSION 0x60 - -#include "defs.h" -#include "xtensa-config.h" -#include "xtensa-tdep.h" - - - -/* Masked registers. */ -xtensa_reg_mask_t xtensa_submask0[] = { { 43, 0, 1 } }; -const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 }; -xtensa_reg_mask_t xtensa_submask1[] = { { 43, 1, 1 } }; -const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 }; -xtensa_reg_mask_t xtensa_submask2[] = { { 43, 2, 1 } }; -const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 }; -xtensa_reg_mask_t xtensa_submask3[] = { { 43, 3, 1 } }; -const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 }; -xtensa_reg_mask_t xtensa_submask4[] = { { 43, 4, 1 } }; -const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 }; -xtensa_reg_mask_t xtensa_submask5[] = { { 43, 5, 1 } }; -const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 }; -xtensa_reg_mask_t xtensa_submask6[] = { { 43, 6, 1 } }; -const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 }; -xtensa_reg_mask_t xtensa_submask7[] = { { 43, 7, 1 } }; -const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 }; -xtensa_reg_mask_t xtensa_submask8[] = { { 43, 8, 1 } }; -const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 }; -xtensa_reg_mask_t xtensa_submask9[] = { { 43, 9, 1 } }; -const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 }; -xtensa_reg_mask_t xtensa_submask10[] = { { 43, 10, 1 } }; -const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 }; -xtensa_reg_mask_t xtensa_submask11[] = { { 43, 11, 1 } }; -const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 }; -xtensa_reg_mask_t xtensa_submask12[] = { { 43, 12, 1 } }; -const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 }; -xtensa_reg_mask_t xtensa_submask13[] = { { 43, 13, 1 } }; -const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 }; -xtensa_reg_mask_t xtensa_submask14[] = { { 43, 14, 1 } }; -const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 }; -xtensa_reg_mask_t xtensa_submask15[] = { { 43, 15, 1 } }; -const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 }; -xtensa_reg_mask_t xtensa_submask16[] = { { 42, 0, 4 } }; -const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 }; -xtensa_reg_mask_t xtensa_submask17[] = { { 42, 5, 1 } }; -const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 }; -xtensa_reg_mask_t xtensa_submask18[] = { { 42, 18, 1 } }; -const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 }; -xtensa_reg_mask_t xtensa_submask19[] = { { 42, 4, 1 } }; -const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 }; -xtensa_reg_mask_t xtensa_submask20[] = { { 42, 16, 2 } }; -const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 }; -xtensa_reg_mask_t xtensa_submask21[] = { { 42, 8, 4 } }; -const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 }; -xtensa_reg_mask_t xtensa_submask22[] = { { 102, 8, 4 } }; -const xtensa_mask_t xtensa_mask22 = { 1, xtensa_submask22 }; -xtensa_reg_mask_t xtensa_submask23[] = { { 58, 6, 1 } }; -const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 }; -xtensa_reg_mask_t xtensa_submask24[] = { { 58, 0, 6 } }; -const xtensa_mask_t xtensa_mask24 = { 1, xtensa_submask24 }; -xtensa_reg_mask_t xtensa_submask25[] = { { 60, 0, 4 } }; -const xtensa_mask_t xtensa_mask25 = { 1, xtensa_submask25 }; -xtensa_reg_mask_t xtensa_submask26[] = { { 60, 4, 4 } }; -const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 }; -xtensa_reg_mask_t xtensa_submask27[] = { { 60, 12, 4 } }; -const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 }; -xtensa_reg_mask_t xtensa_submask28[] = { { 60, 8, 4 } }; -const xtensa_mask_t xtensa_mask28 = { 1, xtensa_submask28 }; -xtensa_reg_mask_t xtensa_submask29[] = { { 61, 0, 27 } }; -const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 }; -xtensa_reg_mask_t xtensa_submask30[] = { { 61, 27, 1 } }; -const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 }; - - -/* Register map. */ -static xtensa_register_t rmap[] = -{ - /* idx ofs bi sz al targno flags cp typ group name */ - XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0) - XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) - XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) - XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) - XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) - XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) - XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) - XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) - XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) - XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) - XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) - XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) - XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) - XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) - XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) - XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) - XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) - XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) - XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) - XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) - XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) - XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) - XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) - XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) - XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) - XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) - XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) - XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) - XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) - XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) - XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) - XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) - XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) - XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) - XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) - XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) - XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) - XTREG( 37,148,13, 4, 4,0x0228,0x0006,-2, 2,0x1100,prefctl, 0,0,0,0,0,0) - XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) - XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) - XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) - XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) - XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) - XTREG( 43,172,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0) - XTREG( 44,176,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0) - XTREG( 45,180,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0) - XTREG( 46,184,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0, - "03:04:84:b2","03:04:84:a7",0,0,0,0) - XTREG( 47,192,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1, - "03:04:94:b2","03:04:94:a7",0,0,0,0) - XTREG( 48,200,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2, - "03:04:a4:b2","03:04:a4:a7",0,0,0,0) - XTREG( 49,208,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3, - "03:04:b4:b2","03:04:b4:a7",0,0,0,0) - XTREG( 50,216,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4, - "03:04:c4:b2","03:04:c4:a7",0,0,0,0) - XTREG( 51,224,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5, - "03:04:d4:b2","03:04:d4:a7",0,0,0,0) - XTREG( 52,232,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6, - "03:04:e4:b2","03:04:e4:a7",0,0,0,0) - XTREG( 53,240,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7, - "03:04:f4:b2","03:04:f4:a7",0,0,0,0) - XTREG( 54,248,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0, - "03:04:04:c3","03:04:04:c1",0,0,0,0) - XTREG( 55,256,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1, - "03:04:14:c3","03:04:44:c1",0,0,0,0) - XTREG( 56,264,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2, - "03:04:24:c3","03:04:84:c1",0,0,0,0) - XTREG( 57,272,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3, - "03:04:34:c3","03:04:c4:c1",0,0,0,0) - XTREG( 58,280, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0) - XTREG( 59,284,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0) - XTREG( 60,288,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0) - XTREG( 61,292,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no, 0,0,0,0,0,0) - XTREG( 62,296,32, 4, 4,0x03f6,0x0006, 1, 3,0x0110,ae_cbegin0, 0,0,0,0,0,0) - XTREG( 63,300,32, 4, 4,0x03f7,0x0006, 1, 3,0x0110,ae_cend0, 0,0,0,0,0,0) - XTREG( 64,304,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) - XTREG( 65,308, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) - XTREG( 66,312, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) - XTREG( 67,316,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) - XTREG( 68,320,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) - XTREG( 69,324,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) - XTREG( 70,328,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) - XTREG( 71,332,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) - XTREG( 72,336,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) - XTREG( 73,340,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) - XTREG( 74,344,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) - XTREG( 75,348,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) - XTREG( 76,352,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) - XTREG( 77,356,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) - XTREG( 78,360,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) - XTREG( 79,364,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0) - XTREG( 80,368,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0) - XTREG( 81,372,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) - XTREG( 82,376,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) - XTREG( 83,380,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) - XTREG( 84,384,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) - XTREG( 85,388,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) - XTREG( 86,392,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0) - XTREG( 87,396,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0) - XTREG( 88,400,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) - XTREG( 89,404,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) - XTREG( 90,408,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) - XTREG( 91,412,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) - XTREG( 92,416,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) - XTREG( 93,420,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0) - XTREG( 94,424,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0) - XTREG( 95,428, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0) - XTREG( 96,432,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) - XTREG( 97,436,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) - XTREG( 98,440,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) - XTREG( 99,444,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) - XTREG(100,448,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) - XTREG(101,452, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) - XTREG(102,456,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) - XTREG(103,460,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) - XTREG(104,464,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) - XTREG(105,468,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) - XTREG(106,472, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) - XTREG(107,476,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) - XTREG(108,480,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) - XTREG(109,484,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) - XTREG(110,488,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0) - XTREG(111,492,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) - XTREG(112,496,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) - XTREG(113,500,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0) - XTREG(114,504,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0) - XTREG(115,508,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0) - XTREG(116,512,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0) - XTREG(117,516,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0) - XTREG(118,520,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0) - XTREG(119,524,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0) - XTREG(120,528,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0) - XTREG(121,532,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0) - XTREG(122,536,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0) - XTREG(123,540,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0) - XTREG(124,544,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0) - XTREG(125,548,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0) - XTREG(126,552,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0) - XTREG(127,556,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0) - XTREG(128,560,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0) - XTREG(129,564, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0, - 0,0,&xtensa_mask0,0,0,0) - XTREG(130,565, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1, - 0,0,&xtensa_mask1,0,0,0) - XTREG(131,566, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2, - 0,0,&xtensa_mask2,0,0,0) - XTREG(132,567, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3, - 0,0,&xtensa_mask3,0,0,0) - XTREG(133,568, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4, - 0,0,&xtensa_mask4,0,0,0) - XTREG(134,569, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5, - 0,0,&xtensa_mask5,0,0,0) - XTREG(135,570, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6, - 0,0,&xtensa_mask6,0,0,0) - XTREG(136,571, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7, - 0,0,&xtensa_mask7,0,0,0) - XTREG(137,572, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8, - 0,0,&xtensa_mask8,0,0,0) - XTREG(138,573, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9, - 0,0,&xtensa_mask9,0,0,0) - XTREG(139,574, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10, - 0,0,&xtensa_mask10,0,0,0) - XTREG(140,575, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11, - 0,0,&xtensa_mask11,0,0,0) - XTREG(141,576, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12, - 0,0,&xtensa_mask12,0,0,0) - XTREG(142,577, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13, - 0,0,&xtensa_mask13,0,0,0) - XTREG(143,578, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14, - 0,0,&xtensa_mask14,0,0,0) - XTREG(144,579, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15, - 0,0,&xtensa_mask15,0,0,0) - XTREG(145,580, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel, - 0,0,&xtensa_mask16,0,0,0) - XTREG(146,584, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum, - 0,0,&xtensa_mask17,0,0,0) - XTREG(147,588, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe, - 0,0,&xtensa_mask18,0,0,0) - XTREG(148,592, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm, - 0,0,&xtensa_mask19,0,0,0) - XTREG(149,596, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc, - 0,0,&xtensa_mask20,0,0,0) - XTREG(150,600, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb, - 0,0,&xtensa_mask21,0,0,0) - XTREG(151,604, 4, 4, 4,0x2012,0x0006,-2, 6,0x1010,dbnum, - 0,0,&xtensa_mask22,0,0,0) - XTREG(152,608, 1, 4, 4,0x2014,0x0006, 1, 5,0x1010,ae_overflow, - 0,0,&xtensa_mask23,0,0,0) - XTREG(153,612, 6, 4, 4,0x2015,0x0006, 1, 5,0x1010,ae_sar, - 0,0,&xtensa_mask24,0,0,0) - XTREG(154,616, 4, 4, 4,0x2016,0x0006, 1, 5,0x1010,ae_bitptr, - 0,0,&xtensa_mask25,0,0,0) - XTREG(155,620, 4, 4, 4,0x2017,0x0006, 1, 5,0x1010,ae_bitsused, - 0,0,&xtensa_mask26,0,0,0) - XTREG(156,624, 4, 4, 4,0x2018,0x0006, 1, 5,0x1010,ae_tablesize, - 0,0,&xtensa_mask27,0,0,0) - XTREG(157,628, 4, 4, 4,0x2019,0x0006, 1, 5,0x1010,ae_first_ts, - 0,0,&xtensa_mask28,0,0,0) - XTREG(158,632,27, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_nextoffset, - 0,0,&xtensa_mask29,0,0,0) - XTREG_END -}; - -xtensa_gdbarch_tdep xtensa_tdep (rmap); diff --git a/overlays/xtensa_intel_bdw_adsp/gdb/gdbserver/xtensa-xtregs.cc b/overlays/xtensa_intel_bdw_adsp/gdb/gdbserver/xtensa-xtregs.cc deleted file mode 100644 index ec8c5de..0000000 --- a/overlays/xtensa_intel_bdw_adsp/gdb/gdbserver/xtensa-xtregs.cc +++ /dev/null @@ -1,62 +0,0 @@ -/* Customized table mapping between kernel xtregset and GDB register cache. - - Customer ID=4313; Build=0x5483e; Copyright (c) 2007-2010 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - - -typedef struct { - int gdb_regnum; - int gdb_offset; - int ptrace_cp_offset; - int ptrace_offset; - int size; - int coproc; - int dbnum; - char* name -;} xtensa_regtable_t; - -#define XTENSA_ELF_XTREG_SIZE 128 - -const xtensa_regtable_t xtensa_regmap_table[] = { - /* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */ - { 43, 172, 0, 0, 4, -1, 0x0204, "br" }, - { 44, 176, 4, 4, 4, -1, 0x020c, "scompare1" }, - { 46, 184, 24, 32, 8, 1, 0x0060, "aep0" }, - { 47, 192, 32, 40, 8, 1, 0x0061, "aep1" }, - { 48, 200, 40, 48, 8, 1, 0x0062, "aep2" }, - { 49, 208, 48, 56, 8, 1, 0x0063, "aep3" }, - { 50, 216, 56, 64, 8, 1, 0x0064, "aep4" }, - { 51, 224, 64, 72, 8, 1, 0x0065, "aep5" }, - { 52, 232, 72, 80, 8, 1, 0x0066, "aep6" }, - { 53, 240, 80, 88, 8, 1, 0x0067, "aep7" }, - { 54, 248, 88, 96, 8, 1, 0x0068, "aeq0" }, - { 55, 256, 96, 104, 8, 1, 0x0069, "aeq1" }, - { 56, 264, 104, 112, 8, 1, 0x006a, "aeq2" }, - { 57, 272, 112, 120, 8, 1, 0x006b, "aeq3" }, - { 58, 280, 0, 8, 4, 1, 0x03f0, "ae_ovf_sar" }, - { 59, 284, 4, 12, 4, 1, 0x03f1, "ae_bithead" }, - { 60, 288, 8, 16, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" }, - { 61, 292, 12, 20, 4, 1, 0x03f3, "ae_sd_no" }, - { 62, 296, 16, 24, 4, 1, 0x03f6, "ae_cbegin0" }, - { 63, 300, 20, 28, 4, 1, 0x03f7, "ae_cend0" }, - { 0 } -}; - diff --git a/overlays/xtensa_intel_bdw_adsp/gdb/include/xtensa-config.h b/overlays/xtensa_intel_bdw_adsp/gdb/include/xtensa-config.h deleted file mode 100644 index fe6442e..0000000 --- a/overlays/xtensa_intel_bdw_adsp/gdb/include/xtensa-config.h +++ /dev/null @@ -1,177 +0,0 @@ -/* Xtensa configuration settings. - Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 - Free Software Foundation, Inc. - Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef XTENSA_CONFIG_H -#define XTENSA_CONFIG_H - -/* The macros defined here match those with the same names in the Xtensa - compile-time HAL (Hardware Abstraction Layer). Please refer to the - Xtensa System Software Reference Manual for documentation of these - macros. */ - -#undef XCHAL_HAVE_BE -#define XCHAL_HAVE_BE 0 - -#undef XCHAL_HAVE_DENSITY -#define XCHAL_HAVE_DENSITY 1 - -#undef XCHAL_HAVE_CONST16 -#define XCHAL_HAVE_CONST16 0 - -#undef XCHAL_HAVE_ABS -#define XCHAL_HAVE_ABS 1 - -#undef XCHAL_HAVE_ADDX -#define XCHAL_HAVE_ADDX 1 - -#undef XCHAL_HAVE_L32R -#define XCHAL_HAVE_L32R 1 - -#undef XSHAL_USE_ABSOLUTE_LITERALS -#define XSHAL_USE_ABSOLUTE_LITERALS 0 - -#undef XSHAL_HAVE_TEXT_SECTION_LITERALS -#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ - -#undef XCHAL_HAVE_MAC16 -#define XCHAL_HAVE_MAC16 0 - -#undef XCHAL_HAVE_MUL16 -#define XCHAL_HAVE_MUL16 1 - -#undef XCHAL_HAVE_MUL32 -#define XCHAL_HAVE_MUL32 0 - -#undef XCHAL_HAVE_MUL32_HIGH -#define XCHAL_HAVE_MUL32_HIGH 0 - -#undef XCHAL_HAVE_DIV32 -#define XCHAL_HAVE_DIV32 0 - -#undef XCHAL_HAVE_NSA -#define XCHAL_HAVE_NSA 1 - -#undef XCHAL_HAVE_MINMAX -#define XCHAL_HAVE_MINMAX 1 - -#undef XCHAL_HAVE_SEXT -#define XCHAL_HAVE_SEXT 1 - -#undef XCHAL_HAVE_LOOPS -#define XCHAL_HAVE_LOOPS 1 - -#undef XCHAL_HAVE_THREADPTR -#define XCHAL_HAVE_THREADPTR 1 - -#undef XCHAL_HAVE_RELEASE_SYNC -#define XCHAL_HAVE_RELEASE_SYNC 1 - -#undef XCHAL_HAVE_S32C1I -#define XCHAL_HAVE_S32C1I 1 - -#undef XCHAL_HAVE_BOOLEANS -#define XCHAL_HAVE_BOOLEANS 1 - -#undef XCHAL_HAVE_FP -#define XCHAL_HAVE_FP 0 - -#undef XCHAL_HAVE_FP_DIV -#define XCHAL_HAVE_FP_DIV 0 - -#undef XCHAL_HAVE_FP_RECIP -#define XCHAL_HAVE_FP_RECIP 0 - -#undef XCHAL_HAVE_FP_SQRT -#define XCHAL_HAVE_FP_SQRT 0 - -#undef XCHAL_HAVE_FP_RSQRT -#define XCHAL_HAVE_FP_RSQRT 0 - -#undef XCHAL_HAVE_DFP_accel -#define XCHAL_HAVE_DFP_accel 0 -#undef XCHAL_HAVE_WINDOWED -#define XCHAL_HAVE_WINDOWED 1 - -#undef XCHAL_NUM_AREGS -#define XCHAL_NUM_AREGS 32 - -#undef XCHAL_HAVE_WIDE_BRANCHES -#define XCHAL_HAVE_WIDE_BRANCHES 0 - -#undef XCHAL_HAVE_PREDICTED_BRANCHES -#define XCHAL_HAVE_PREDICTED_BRANCHES 0 - - -#undef XCHAL_ICACHE_SIZE -#define XCHAL_ICACHE_SIZE 0 - -#undef XCHAL_DCACHE_SIZE -#define XCHAL_DCACHE_SIZE 0 - -#undef XCHAL_ICACHE_LINESIZE -#define XCHAL_ICACHE_LINESIZE 128 - -#undef XCHAL_DCACHE_LINESIZE -#define XCHAL_DCACHE_LINESIZE 128 - -#undef XCHAL_ICACHE_LINEWIDTH -#define XCHAL_ICACHE_LINEWIDTH 7 - -#undef XCHAL_DCACHE_LINEWIDTH -#define XCHAL_DCACHE_LINEWIDTH 7 - -#undef XCHAL_DCACHE_IS_WRITEBACK -#define XCHAL_DCACHE_IS_WRITEBACK 0 - - -#undef XCHAL_HAVE_MMU -#define XCHAL_HAVE_MMU 1 - -#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE -#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 - - -#undef XCHAL_HAVE_DEBUG -#define XCHAL_HAVE_DEBUG 1 - -#undef XCHAL_NUM_IBREAK -#define XCHAL_NUM_IBREAK 2 - -#undef XCHAL_NUM_DBREAK -#define XCHAL_NUM_DBREAK 2 - -#undef XCHAL_DEBUGLEVEL -#define XCHAL_DEBUGLEVEL 6 - - -#undef XCHAL_MAX_INSTRUCTION_SIZE -#define XCHAL_MAX_INSTRUCTION_SIZE 8 - -#undef XCHAL_INST_FETCH_WIDTH -#define XCHAL_INST_FETCH_WIDTH 4 - - -#undef XSHAL_ABI -#undef XTHAL_ABI_WINDOWED -#undef XTHAL_ABI_CALL0 -#define XSHAL_ABI XTHAL_ABI_WINDOWED -#define XTHAL_ABI_WINDOWED 0 -#define XTHAL_ABI_CALL0 1 - -#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_intel_byt_adsp/binutils/bfd/xtensa-modules.c b/overlays/xtensa_intel_byt_adsp/binutils/bfd/xtensa-modules.c deleted file mode 100644 index ee283c6..0000000 --- a/overlays/xtensa_intel_byt_adsp/binutils/bfd/xtensa-modules.c +++ /dev/null @@ -1,42978 +0,0 @@ -/* Xtensa configuration-specific ISA information. - - Copyright (c) 2003-2017 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#include "ansidecl.h" -#include -#include "xtensa-isa-internal.h" - - -/* Sysregs. */ - -static xtensa_sysreg_internal sysregs[] = { - { "LBEG", 0, 0 }, - { "LEND", 1, 0 }, - { "LCOUNT", 2, 0 }, - { "BR", 4, 0 }, - { "ACCLO", 16, 0 }, - { "ACCHI", 17, 0 }, - { "M0", 32, 0 }, - { "M1", 33, 0 }, - { "M2", 34, 0 }, - { "M3", 35, 0 }, - { "DDR", 104, 0 }, - { "CONFIGID0", 176, 0 }, - { "CONFIGID1", 208, 0 }, - { "INTERRUPT", 226, 0 }, - { "INTCLEAR", 227, 0 }, - { "CCOUNT", 234, 0 }, - { "PRID", 235, 0 }, - { "ICOUNT", 236, 0 }, - { "CCOMPARE0", 240, 0 }, - { "CCOMPARE1", 241, 0 }, - { "CCOMPARE2", 242, 0 }, - { "VECBASE", 231, 0 }, - { "EPC1", 177, 0 }, - { "EPC2", 178, 0 }, - { "EPC3", 179, 0 }, - { "EPC4", 180, 0 }, - { "EPC5", 181, 0 }, - { "EPC6", 182, 0 }, - { "EPC7", 183, 0 }, - { "EXCSAVE1", 209, 0 }, - { "EXCSAVE2", 210, 0 }, - { "EXCSAVE3", 211, 0 }, - { "EXCSAVE4", 212, 0 }, - { "EXCSAVE5", 213, 0 }, - { "EXCSAVE6", 214, 0 }, - { "EXCSAVE7", 215, 0 }, - { "EPS2", 194, 0 }, - { "EPS3", 195, 0 }, - { "EPS4", 196, 0 }, - { "EPS5", 197, 0 }, - { "EPS6", 198, 0 }, - { "EPS7", 199, 0 }, - { "EXCCAUSE", 232, 0 }, - { "DEPC", 192, 0 }, - { "EXCVADDR", 238, 0 }, - { "WINDOWBASE", 72, 0 }, - { "WINDOWSTART", 73, 0 }, - { "SAR", 3, 0 }, - { "PS", 230, 0 }, - { "INTENABLE", 228, 0 }, - { "DBREAKA0", 144, 0 }, - { "DBREAKC0", 160, 0 }, - { "DBREAKA1", 145, 0 }, - { "DBREAKC1", 161, 0 }, - { "IBREAKA0", 128, 0 }, - { "IBREAKA1", 129, 0 }, - { "IBREAKENABLE", 96, 0 }, - { "ICOUNTLEVEL", 237, 0 }, - { "DEBUGCAUSE", 233, 0 }, - { "PREFCTL", 40, 0 }, - { "CPENABLE", 224, 0 }, - { "SCOMPARE1", 12, 0 }, - { "ATOMCTL", 99, 0 }, - { "THREADPTR", 231, 1 }, - { "AE_OVF_SAR", 240, 1 }, - { "AE_BITHEAD", 241, 1 }, - { "AE_TS_FTS_BU_BP", 242, 1 }, - { "AE_SD_NO", 243, 1 }, - { "AE_CBEGIN0", 246, 1 }, - { "AE_CEND0", 247, 1 } -}; - -#define NUM_SYSREGS 70 -#define MAX_SPECIAL_REG 242 -#define MAX_USER_REG 247 - - -/* Processor states. */ - -static xtensa_state_internal states[] = { - { "LCOUNT", 32, 0 }, - { "PC", 32, 0 }, - { "ICOUNT", 32, 0 }, - { "DDR", 32, 0 }, - { "INTERRUPT", 22, 0 }, - { "CCOUNT", 32, 0 }, - { "XTSYNC", 1, 0 }, - { "VECBASE", 22, 0 }, - { "EPC1", 32, 0 }, - { "EPC2", 32, 0 }, - { "EPC3", 32, 0 }, - { "EPC4", 32, 0 }, - { "EPC5", 32, 0 }, - { "EPC6", 32, 0 }, - { "EPC7", 32, 0 }, - { "EXCSAVE1", 32, 0 }, - { "EXCSAVE2", 32, 0 }, - { "EXCSAVE3", 32, 0 }, - { "EXCSAVE4", 32, 0 }, - { "EXCSAVE5", 32, 0 }, - { "EXCSAVE6", 32, 0 }, - { "EXCSAVE7", 32, 0 }, - { "EPS2", 13, 0 }, - { "EPS3", 13, 0 }, - { "EPS4", 13, 0 }, - { "EPS5", 13, 0 }, - { "EPS6", 13, 0 }, - { "EPS7", 13, 0 }, - { "EXCCAUSE", 6, 0 }, - { "PSINTLEVEL", 4, 0 }, - { "PSUM", 1, 0 }, - { "PSWOE", 1, 0 }, - { "PSEXCM", 1, 0 }, - { "DEPC", 32, 0 }, - { "EXCVADDR", 32, 0 }, - { "WindowBase", 3, 0 }, - { "WindowStart", 8, 0 }, - { "PSCALLINC", 2, 0 }, - { "PSOWB", 4, 0 }, - { "LBEG", 32, 0 }, - { "LEND", 32, 0 }, - { "SAR", 6, 0 }, - { "THREADPTR", 32, 0 }, - { "ACC", 40, 0 }, - { "InOCDMode", 1, 0 }, - { "INTENABLE", 22, 0 }, - { "DBREAKA0", 32, 0 }, - { "DBREAKC0", 8, 0 }, - { "DBREAKA1", 32, 0 }, - { "DBREAKC1", 8, 0 }, - { "IBREAKA0", 32, 0 }, - { "IBREAKA1", 32, 0 }, - { "IBREAKENABLE", 2, 0 }, - { "ICOUNTLEVEL", 4, 0 }, - { "DEBUGCAUSE", 6, 0 }, - { "DBNUM", 4, 0 }, - { "CCOMPARE0", 32, 0 }, - { "CCOMPARE1", 32, 0 }, - { "CCOMPARE2", 32, 0 }, - { "PREFCTL", 8, 0 }, - { "CPENABLE", 2, 0 }, - { "SCOMPARE1", 32, 0 }, - { "ATOMCTL", 6, 0 }, - { "AE_OVERFLOW", 1, XTENSA_STATE_IS_SHARED_OR }, - { "AE_SAR", 6, 0 }, - { "AE_BITHEAD", 32, 0 }, - { "AE_BITPTR", 4, 0 }, - { "AE_BITSUSED", 4, 0 }, - { "AE_TABLESIZE", 4, 0 }, - { "AE_FIRST_TS", 4, 0 }, - { "AE_NEXTOFFSET", 27, 0 }, - { "AE_SEARCHDONE", 1, 0 }, - { "AE_CBEGIN0", 32, 0 }, - { "AE_CEND0", 32, 0 } -}; - -#define NUM_STATES 74 - -enum xtensa_state_id { - STATE_LCOUNT, - STATE_PC, - STATE_ICOUNT, - STATE_DDR, - STATE_INTERRUPT, - STATE_CCOUNT, - STATE_XTSYNC, - STATE_VECBASE, - STATE_EPC1, - STATE_EPC2, - STATE_EPC3, - STATE_EPC4, - STATE_EPC5, - STATE_EPC6, - STATE_EPC7, - STATE_EXCSAVE1, - STATE_EXCSAVE2, - STATE_EXCSAVE3, - STATE_EXCSAVE4, - STATE_EXCSAVE5, - STATE_EXCSAVE6, - STATE_EXCSAVE7, - STATE_EPS2, - STATE_EPS3, - STATE_EPS4, - STATE_EPS5, - STATE_EPS6, - STATE_EPS7, - STATE_EXCCAUSE, - STATE_PSINTLEVEL, - STATE_PSUM, - STATE_PSWOE, - STATE_PSEXCM, - STATE_DEPC, - STATE_EXCVADDR, - STATE_WindowBase, - STATE_WindowStart, - STATE_PSCALLINC, - STATE_PSOWB, - STATE_LBEG, - STATE_LEND, - STATE_SAR, - STATE_THREADPTR, - STATE_ACC, - STATE_InOCDMode, - STATE_INTENABLE, - STATE_DBREAKA0, - STATE_DBREAKC0, - STATE_DBREAKA1, - STATE_DBREAKC1, - STATE_IBREAKA0, - STATE_IBREAKA1, - STATE_IBREAKENABLE, - STATE_ICOUNTLEVEL, - STATE_DEBUGCAUSE, - STATE_DBNUM, - STATE_CCOMPARE0, - STATE_CCOMPARE1, - STATE_CCOMPARE2, - STATE_PREFCTL, - STATE_CPENABLE, - STATE_SCOMPARE1, - STATE_ATOMCTL, - STATE_AE_OVERFLOW, - STATE_AE_SAR, - STATE_AE_BITHEAD, - STATE_AE_BITPTR, - STATE_AE_BITSUSED, - STATE_AE_TABLESIZE, - STATE_AE_FIRST_TS, - STATE_AE_NEXTOFFSET, - STATE_AE_SEARCHDONE, - STATE_AE_CBEGIN0, - STATE_AE_CEND0 -}; - - -/* Field definitions. */ - -static unsigned -Field_t_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_s_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_r_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_op2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); - return tie_t; -} - -static void -Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); -} - -static unsigned -Field_op1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_op0_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_n_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_m_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_sr_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_st_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_w_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_r3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ae_r3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_ae_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_ae_r10_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_ae_r32_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ae_s3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_ae_s3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_ae_s_non_samt_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_ae_s_non_samt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf61ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf61ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 22) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_op0_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - return tie_t; -} - -static void -Field_op0_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf330ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_ftsf330ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ftsf81ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf81ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ae_r20_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_ftsf73ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf73ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf35ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf35ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf34ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf34ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf32ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf32ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf33ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf33ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf96ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf96ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ae_s20_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); -} - -static unsigned -Field_ftsf94ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_ftsf94ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf347_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf347_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); -} - -static unsigned -Field_ftsf24ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - return tie_t; -} - -static void -Field_ftsf24ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf23ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - return tie_t; -} - -static void -Field_ftsf23ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf125ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_ftsf125ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_ftsf350ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); - return tie_t; -} - -static void -Field_ftsf350ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78) | (tie_t << 3); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf80ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf80ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf88ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf88ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 23) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf340_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf340_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_ftsf87ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf87ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x60) | (tie_t << 5); - tie_t = (val << 22) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf342ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_ftsf342ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_ftsf86ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); - return tie_t; -} - -static void -Field_ftsf86ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78) | (tie_t << 3); - tie_t = (val << 21) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf84ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); - return tie_t; -} - -static void -Field_ftsf84ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78) | (tie_t << 3); - tie_t = (val << 21) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf76ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf76ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf75ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf75ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf60ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf60ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 21) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf64ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf64ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 20) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf63ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf63ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ae_r10_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf59ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf59ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 21) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf119ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf119ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 24) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 21) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf338_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf338_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_ftsf69ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf69ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 22) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf67ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf67ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x60) | (tie_t << 5); - tie_t = (val << 21) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf66ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf66ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 20) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf25ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf25ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf36ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf36ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf103ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf103ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf349ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 23) >> 26); - return tie_t; -} - -static void -Field_ftsf349ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x1f8) | (tie_t << 3); -} - -static unsigned -Field_ftsf99ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf99ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf27ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf27ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf28ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf28ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf21ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf21ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf22ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf22ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf29ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf29ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf97ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf97ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf100ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf100ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf101ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - return tie_t; -} - -static void -Field_ftsf101ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf348ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); - return tie_t; -} - -static void -Field_ftsf348ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); -} - -static unsigned -Field_ftsf26ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf26ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf30ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf30ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf31ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf31ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf98ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf98ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf92ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); - return tie_t; -} - -static void -Field_ftsf92ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6) | (tie_t << 1); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf208_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf208_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); -} - -static unsigned -Field_ftsf91ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf91ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf90ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf90ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf126ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); - return tie_t; -} - -static void -Field_ftsf126ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); -} - -static unsigned -Field_ftsf344ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf344ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 23) >> 30; - insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); -} - -static unsigned -Field_ftsf112ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf112ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf122ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); - return tie_t; -} - -static void -Field_ftsf122ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); - tie_t = (val << 24) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf346ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf346ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf116ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); - return tie_t; -} - -static void -Field_ftsf116ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); - tie_t = (val << 20) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf109ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf109ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf111ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf111ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf104ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf104ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf105ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf105ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf107ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf107ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf113ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf113ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf118ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); - return tie_t; -} - -static void -Field_ftsf118ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); - tie_t = (val << 20) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf120ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 6) | ((insn[0] << 25) >> 26); - return tie_t; -} - -static void -Field_ftsf120ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x7e) | (tie_t << 1); - tie_t = (val << 23) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf343ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf343ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf108ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf108ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf115ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf115ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf110ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf110ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf114ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf114ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf37ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - return tie_t; -} - -static void -Field_ftsf37ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf78ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf78ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf79ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf79ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf77ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf77ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf13_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_ftsf13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf12_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - return tie_t; -} - -static void -Field_ftsf12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf82ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf82ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 24) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf341ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf341ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ftsf124ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf124ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 28) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf339ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf339ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ftsf106ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf106ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ae_r32_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ae_mul32x24fld_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ae_mul32x24fld_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf160ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf160ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf154ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf154ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf175ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf175ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf158ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf158ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf155ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf155ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf167ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf167ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf157ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf157ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf153ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf153ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf163ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf163ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf156ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf156ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf152ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf152ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf161ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf161ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf133ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf133ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf191ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf191ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf142ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf142ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf159ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf159ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf141ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf141ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf130ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf130ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf143ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf143ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf140ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf140ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf211ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_ftsf211ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_ftsf332ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf332ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_ftsf135ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf135ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf138ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf138ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf176ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf176ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf170ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf170ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf184ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf184ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf174ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf174ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf171ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf171ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf182ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf182ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf173ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf173ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf169ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf169ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf181ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf181ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf172ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf172ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf168ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf168ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf180ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf180ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf139ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf139ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf151ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf151ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf137ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf137ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf136ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf136ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf145ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf145ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf134ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf134ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf144ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf144ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf178ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf178ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf188ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf188ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf183ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf183ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf186ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf186ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf179ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf179ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf187ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf187ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf177ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf177ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf185ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf185ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf45ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf45ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf44ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf44ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf48ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf48ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf47ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf47ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf49ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf49ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf50ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf50ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf52ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf52ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf51ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf51ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf38ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf38ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf54ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf54ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf40ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf40ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf39ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf39ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf46ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf46ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf42ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf42ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf43ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf43ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf41ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf41ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf55ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf55ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf53ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf53ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf58ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf58ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf56ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf56ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf72ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf72ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 26) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf71ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf71ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 26) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf57ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf57ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf89ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_ftsf89ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_ftsf334ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf334ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_ftsf195ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf195ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf207ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf207ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf336ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; -} - -static void -Field_ftsf336ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); -} - -static unsigned -Field_ftsf199ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf199ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf210ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} - -static void -Field_ftsf210ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf337ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf337ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_ftsf194ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf194ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf197ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf197ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf196ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf196ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf198ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf198ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf200ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf200ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf203ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf203ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf201ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf201ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf202ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf202ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf204ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf204ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf206ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf206ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf205ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf205ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf209ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf209ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf127ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf127ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf129ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf129ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf128ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf128ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf146ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf146ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf149ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf149ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf148ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf148ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf150ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf150ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf162ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf162ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf165ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf165ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf164ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf164ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf166ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf166ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf189ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf189ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf192ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf192ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf190ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf190ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf193ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf193ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_combined1b97e84f_fld49_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld49_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_combined1b97e84f_fld54_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld54_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_combined1b97e84f_fld51_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld51_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined1b97e84f_fld23_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld23_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_op0_s3_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - return tie_t; -} - -static void -Field_op0_s3_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_combined1b97e84f_fld17_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld17_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); -} - -static unsigned -Field_combined1b97e84f_fld76_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld76_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2) | (tie_t << 1); -} - -static unsigned -Field_combined1b97e84f_fld73_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld73_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); -} - -static unsigned -Field_combined1b97e84f_fld62_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld62_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld24_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld24_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_combined1b97e84f_fld70_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld70_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_combined1b97e84f_fld58_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld58_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); -} - -static unsigned -Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_op0_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); - return tie_t; -} - -static void -Field_op0_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); -} - -static unsigned -Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - return tie_t; -} - -static void -Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_ftsf293_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_ftsf293_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_ftsf321_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf321_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_ae_s20_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); -} - -static unsigned -Field_ftsf214ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_ftsf214ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf213ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); - return tie_t; -} - -static void -Field_ftsf213ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); -} - -static unsigned -Field_ftsf212ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_ftsf212ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_ftsf281ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_ftsf281ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); - tie_t = (val << 16) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf217_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf217_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_ae_r20_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_ftsf300ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - return tie_t; -} - -static void -Field_ftsf300ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf283ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); - return tie_t; -} - -static void -Field_ftsf283ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 17) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf352ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf352ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf282ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_ftsf282ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); - tie_t = (val << 16) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf288ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); - return tie_t; -} - -static void -Field_ftsf288ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x38) | (tie_t << 3); - tie_t = (val << 21) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf359ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf359ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf286ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); - return tie_t; -} - -static void -Field_ftsf286ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf356ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf356ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf284ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 5) | ((insn[0] << 26) >> 27); - return tie_t; -} - -static void -Field_ftsf284ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x3e) | (tie_t << 1); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf354ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf354ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf295ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_ftsf295ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf358ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf358ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf325ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf325ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf215ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); - return tie_t; -} - -static void -Field_ftsf215ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); -} - -static unsigned -Field_ftsf301ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19); - return tie_t; -} - -static void -Field_ftsf301ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 19) >> 19; - insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf353_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf353_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_ftsf309ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23); - return tie_t; -} - -static void -Field_ftsf309ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0xff800) | (tie_t << 11); -} - -static unsigned -Field_ftsf360ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 21) >> 27); - return tie_t; -} - -static void -Field_ftsf360ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x7c0) | (tie_t << 6); -} - -static unsigned -Field_ftsf294ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_ftsf294ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); - tie_t = (val << 21) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf292ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_ftsf292ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); - tie_t = (val << 21) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf319_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; -} - -static void -Field_ftsf319_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); -} - -static unsigned -Field_ftsf361ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf361ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_ftsf218ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf218ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf220ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf220ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf221ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf221ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf222ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf222ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf228ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf228ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf229ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf229ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf230ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf230ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf232ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf232ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf233ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf233ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf235ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf235ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf239ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf239ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf234ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf234ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf224ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf224ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf225ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf225ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf227ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf227ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf226ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf226ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf241ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf241ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf243ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf243ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf242ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf242ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf244ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf244ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf236ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf236ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf237ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf237ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf238ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf238ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf240ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf240ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf261ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf261ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf296ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf296ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf248ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf248ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf250ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf250ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf269ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf269ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf264ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf264ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf266ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf266ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf267ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf267ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf260ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf260ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf262ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf262ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf263ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf263ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf265ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf265ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf246ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf246ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf247ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf247ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf249ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf249ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf253ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf253ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf257ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf257ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf256ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf256ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf258ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf258ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf259ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf259ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf251ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf251ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf252ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf252ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf254ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf254ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf255ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf255ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf275ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf275ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf277ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf277ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf278ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf278ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf290ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_ftsf290ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_ftsf272ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf272ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf276ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf276ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf273ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf273ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf274ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf274ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf297ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf297ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf298ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf298ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf310ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf310ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf311ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf311ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf270ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf270ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf271ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf271ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ae_r32_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf329ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); - return tie_t; -} - -static void -Field_ftsf329ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); -} - -static unsigned -Field_ftsf362ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf362ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 27) >> 29; - insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); -} - -static unsigned -Field_combined4b12daa6_fld85_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld85_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_combined4b12daa6_fld122_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld122_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x200) | (tie_t << 9); -} - -static unsigned -Field_combined4b12daa6_fld119_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld119_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x400) | (tie_t << 10); -} - -static unsigned -Field_combined4b12daa6_fld97_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); - return tie_t; -} - -static void -Field_combined4b12daa6_fld97_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); -} - -static unsigned -Field_combined4b12daa6_fld124_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld124_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_combined4b12daa6_fld79_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld79_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_combined4b12daa6_fld80_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld80_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); -} - -static unsigned -Field_combined4b12daa6_fld108_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_combined4b12daa6_fld108_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_op0_s4_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); - return tie_t; -} - -static void -Field_op0_s4_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); -} - -static unsigned -Field_combined4b12daa6_fld115_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld115_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_ftsf245ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf245ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf268ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf268ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf313ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf313ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf312ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf312ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf231ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf231ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf223ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf223ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf219ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf219ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf216ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf216ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf302ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf302ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 17) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf364ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf364ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_ftsf322ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf322ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf279ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); - return tie_t; -} - -static void -Field_ftsf279ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); - tie_t = (val << 18) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf318ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; -} - -static void -Field_ftsf318ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); - tie_t = (val << 28) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf365ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf365ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_ftsf316ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf316ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf314ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf314ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf315ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf315ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf320ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf320ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf299ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); - return tie_t; -} - -static void -Field_ftsf299ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 22) >> 22; - insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); -} - -static unsigned -Field_ftsf308ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21); - return tie_t; -} - -static void -Field_ftsf308ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 21) >> 21; - insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf366ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf366ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_ftsf306ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_ftsf306ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); - tie_t = (val << 19) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf368ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf368ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); - tie_t = (val << 29) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_ftsf304ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); - return tie_t; -} - -static void -Field_ftsf304ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6) | (tie_t << 1); - tie_t = (val << 18) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf369ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf369ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_ftsf323ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf323ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf328ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf328ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf326ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); - return tie_t; -} - -static void -Field_ftsf326ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc) | (tie_t << 2); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf357_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf357_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); -} - -static unsigned -Field_ftsf303ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf303ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 17) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf324ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf324ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf317ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf317ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld101_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld101_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); -} - -static unsigned -Field_combined1b97e84f_fld88_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld88_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2) | (tie_t << 1); -} - -static unsigned -Field_combined1b97e84f_fld39_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld39_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); -} - -static unsigned -Field_combined1b97e84f_fld115_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld115_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined1b97e84f_fld97_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); - return tie_t; -} - -static void -Field_combined1b97e84f_fld97_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); -} - -static unsigned -Field_combined1b97e84f_fld124_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld124_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld79_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld79_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_combined1b97e84f_fld80_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld80_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); -} - -static unsigned -Field_combined1b97e84f_fld108_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_combined1b97e84f_fld108_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld83_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld83_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld93_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld93_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_combined1b97e84f_fld90_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld90_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); -} - -static unsigned -Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_bbi_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); - return tie_t; -} - -static void -Field_bbi_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); -} - -static unsigned -Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); - return tie_t; -} - -static void -Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); -} - -static unsigned -Field_imm12_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_imm12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); -} - -static unsigned -Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); - return tie_t; -} - -static void -Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); -} - -static unsigned -Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); - return tie_t; -} - -static void -Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); -} - -static unsigned -Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); - return tie_t; -} - -static void -Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); -} - -static unsigned -Field_offset_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); - return tie_t; -} - -static void -Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); -} - -static unsigned -Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - return tie_t; -} - -static void -Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sae_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27); - return tie_t; -} - -static void -Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12); -} - -static unsigned -Field_sal_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); - return tie_t; -} - -static void -Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); -} - -static unsigned -Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sas_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); - return tie_t; -} - -static void -Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); -} - -static unsigned -Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_mn_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_y_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_x_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_t2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t2_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_t2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_s2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_r2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} - -static unsigned -Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} - -static unsigned -Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} - -static unsigned -Field_t4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_s4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_r4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_t8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_s8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_r8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); - return tie_t; -} - -static void -Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 17) >> 17; - insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); -} - -static unsigned -Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_ae_samt_s_t_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); - return tie_t; -} - -static void -Field_ae_samt_s_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); -} - -static unsigned -Field_ae_samt_s_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ae_samt_s_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -} - -static unsigned -Field_ae_r20_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); -} - -static unsigned -Field_ae_r10_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_ae_s20_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); -} - -static unsigned -Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_ftsf12_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf13_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf13_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_ftsf14_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf14_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); -} - -static void -Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, - uint32 val ATTRIBUTE_UNUSED) -{ - /* Do nothing. */ -} - -static unsigned -Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 4; -} - -static unsigned -Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 8; -} - -static unsigned -Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 12; -} - -static unsigned -Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 1; -} - -static unsigned -Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 2; -} - -static unsigned -Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 3; -} - -static unsigned -Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -enum xtensa_field_id { - FIELD_t, - FIELD_bbi4, - FIELD_bbi, - FIELD_imm12, - FIELD_imm8, - FIELD_s, - FIELD_imm12b, - FIELD_imm16, - FIELD_m, - FIELD_n, - FIELD_offset, - FIELD_op0, - FIELD_op1, - FIELD_op2, - FIELD_r, - FIELD_sa4, - FIELD_sae4, - FIELD_sae, - FIELD_sal, - FIELD_sargt, - FIELD_sas4, - FIELD_sas, - FIELD_sr, - FIELD_st, - FIELD_thi3, - FIELD_imm4, - FIELD_mn, - FIELD_i, - FIELD_imm6lo, - FIELD_imm6hi, - FIELD_imm7lo, - FIELD_imm7hi, - FIELD_z, - FIELD_imm6, - FIELD_imm7, - FIELD_r3, - FIELD_rbit2, - FIELD_rhi, - FIELD_t3, - FIELD_tbit2, - FIELD_tlo, - FIELD_w, - FIELD_y, - FIELD_x, - FIELD_t2, - FIELD_s2, - FIELD_r2, - FIELD_t4, - FIELD_s4, - FIELD_r4, - FIELD_t8, - FIELD_s8, - FIELD_r8, - FIELD_xt_wbr15_imm, - FIELD_xt_wbr18_imm, - FIELD_ae_r3, - FIELD_ae_s_non_samt, - FIELD_ae_s3, - FIELD_ae_r32, - FIELD_ae_samt_s_t, - FIELD_ae_r20, - FIELD_ae_r10, - FIELD_ae_s20, - FIELD_ae_fld_ohba, - FIELD_ae_fld_ohba2, - FIELD_op0_s3, - FIELD_ftsf12, - FIELD_ftsf13, - FIELD_ftsf14, - FIELD_ftsf21ae_slot1, - FIELD_ftsf22ae_slot1, - FIELD_ftsf23ae_slot1, - FIELD_ftsf24ae_slot1, - FIELD_ftsf25ae_slot1, - FIELD_ftsf26ae_slot1, - FIELD_ftsf27ae_slot1, - FIELD_ftsf28ae_slot1, - FIELD_ftsf29ae_slot1, - FIELD_ftsf30ae_slot1, - FIELD_ftsf31ae_slot1, - FIELD_ftsf32ae_slot1, - FIELD_ftsf33ae_slot1, - FIELD_ftsf34ae_slot1, - FIELD_ftsf35ae_slot1, - FIELD_ftsf36ae_slot1, - FIELD_ftsf37ae_slot1, - FIELD_ftsf38ae_slot1, - FIELD_ftsf39ae_slot1, - FIELD_ftsf40ae_slot1, - FIELD_ftsf41ae_slot1, - FIELD_ftsf42ae_slot1, - FIELD_ftsf43ae_slot1, - FIELD_ftsf44ae_slot1, - FIELD_ftsf45ae_slot1, - FIELD_ftsf46ae_slot1, - FIELD_ftsf47ae_slot1, - FIELD_ftsf48ae_slot1, - FIELD_ftsf49ae_slot1, - FIELD_ftsf50ae_slot1, - FIELD_ftsf51ae_slot1, - FIELD_ftsf52ae_slot1, - FIELD_ftsf53ae_slot1, - FIELD_ftsf54ae_slot1, - FIELD_ftsf55ae_slot1, - FIELD_ftsf56ae_slot1, - FIELD_ftsf57ae_slot1, - FIELD_ftsf58ae_slot1, - FIELD_ftsf59ae_slot1, - FIELD_ftsf60ae_slot1, - FIELD_ftsf61ae_slot1, - FIELD_ftsf63ae_slot1, - FIELD_ftsf64ae_slot1, - FIELD_ftsf66ae_slot1, - FIELD_ftsf67ae_slot1, - FIELD_ftsf69ae_slot1, - FIELD_ftsf71ae_slot1, - FIELD_ftsf72ae_slot1, - FIELD_ftsf73ae_slot1, - FIELD_ftsf75ae_slot1, - FIELD_ftsf76ae_slot1, - FIELD_ftsf77ae_slot1, - FIELD_ftsf78ae_slot1, - FIELD_ftsf79ae_slot1, - FIELD_ftsf80ae_slot1, - FIELD_ftsf81ae_slot1, - FIELD_ftsf82ae_slot1, - FIELD_ftsf84ae_slot1, - FIELD_ftsf86ae_slot1, - FIELD_ftsf87ae_slot1, - FIELD_ftsf88ae_slot1, - FIELD_ftsf89ae_slot1, - FIELD_ftsf90ae_slot1, - FIELD_ftsf91ae_slot1, - FIELD_ftsf92ae_slot1, - FIELD_ftsf94ae_slot1, - FIELD_ftsf96ae_slot1, - FIELD_ftsf97ae_slot1, - FIELD_ftsf98ae_slot1, - FIELD_ftsf99ae_slot1, - FIELD_ftsf100ae_slot1, - FIELD_ftsf101ae_slot1, - FIELD_ftsf103ae_slot1, - FIELD_ftsf104ae_slot1, - FIELD_ftsf105ae_slot1, - FIELD_ftsf106ae_slot1, - FIELD_ftsf107ae_slot1, - FIELD_ftsf108ae_slot1, - FIELD_ftsf109ae_slot1, - FIELD_ftsf110ae_slot1, - FIELD_ftsf111ae_slot1, - FIELD_ftsf112ae_slot1, - FIELD_ftsf113ae_slot1, - FIELD_ftsf114ae_slot1, - FIELD_ftsf115ae_slot1, - FIELD_ftsf116ae_slot1, - FIELD_ftsf118ae_slot1, - FIELD_ftsf119ae_slot1, - FIELD_ftsf120ae_slot1, - FIELD_ftsf122ae_slot1, - FIELD_ftsf124ae_slot1, - FIELD_ftsf125ae_slot1, - FIELD_ftsf126ae_slot1, - FIELD_ftsf127ae_slot1, - FIELD_ftsf128ae_slot1, - FIELD_ftsf129ae_slot1, - FIELD_ftsf130ae_slot1, - FIELD_ftsf131ae_slot1, - FIELD_ftsf132ae_slot1, - FIELD_ftsf133ae_slot1, - FIELD_ftsf134ae_slot1, - FIELD_ftsf135ae_slot1, - FIELD_ftsf136ae_slot1, - FIELD_ftsf137ae_slot1, - FIELD_ftsf138ae_slot1, - FIELD_ftsf139ae_slot1, - FIELD_ftsf140ae_slot1, - FIELD_ftsf141ae_slot1, - FIELD_ftsf142ae_slot1, - FIELD_ftsf143ae_slot1, - FIELD_ftsf144ae_slot1, - FIELD_ftsf145ae_slot1, - FIELD_ftsf146ae_slot1, - FIELD_ftsf147ae_slot1, - FIELD_ftsf148ae_slot1, - FIELD_ftsf149ae_slot1, - FIELD_ftsf150ae_slot1, - FIELD_ftsf151ae_slot1, - FIELD_ftsf152ae_slot1, - FIELD_ftsf153ae_slot1, - FIELD_ftsf154ae_slot1, - FIELD_ftsf155ae_slot1, - FIELD_ftsf156ae_slot1, - FIELD_ftsf157ae_slot1, - FIELD_ftsf158ae_slot1, - FIELD_ftsf159ae_slot1, - FIELD_ftsf160ae_slot1, - FIELD_ftsf161ae_slot1, - FIELD_ftsf162ae_slot1, - FIELD_ftsf163ae_slot1, - FIELD_ftsf164ae_slot1, - FIELD_ftsf165ae_slot1, - FIELD_ftsf166ae_slot1, - FIELD_ftsf167ae_slot1, - FIELD_ftsf168ae_slot1, - FIELD_ftsf169ae_slot1, - FIELD_ftsf170ae_slot1, - FIELD_ftsf171ae_slot1, - FIELD_ftsf172ae_slot1, - FIELD_ftsf173ae_slot1, - FIELD_ftsf174ae_slot1, - FIELD_ftsf175ae_slot1, - FIELD_ftsf176ae_slot1, - FIELD_ftsf177ae_slot1, - FIELD_ftsf178ae_slot1, - FIELD_ftsf179ae_slot1, - FIELD_ftsf180ae_slot1, - FIELD_ftsf181ae_slot1, - FIELD_ftsf182ae_slot1, - FIELD_ftsf183ae_slot1, - FIELD_ftsf184ae_slot1, - FIELD_ftsf185ae_slot1, - FIELD_ftsf186ae_slot1, - FIELD_ftsf187ae_slot1, - FIELD_ftsf188ae_slot1, - FIELD_ftsf189ae_slot1, - FIELD_ftsf190ae_slot1, - FIELD_ftsf191ae_slot1, - FIELD_ftsf192ae_slot1, - FIELD_ftsf193ae_slot1, - FIELD_ftsf194ae_slot1, - FIELD_ftsf195ae_slot1, - FIELD_ftsf196ae_slot1, - FIELD_ftsf197ae_slot1, - FIELD_ftsf198ae_slot1, - FIELD_ftsf199ae_slot1, - FIELD_ftsf200ae_slot1, - FIELD_ftsf201ae_slot1, - FIELD_ftsf202ae_slot1, - FIELD_ftsf203ae_slot1, - FIELD_ftsf204ae_slot1, - FIELD_ftsf205ae_slot1, - FIELD_ftsf206ae_slot1, - FIELD_ftsf207ae_slot1, - FIELD_ftsf208, - FIELD_ftsf209ae_slot1, - FIELD_ftsf210ae_slot1, - FIELD_ftsf211ae_slot1, - FIELD_ftsf330ae_slot1, - FIELD_ftsf332ae_slot1, - FIELD_ftsf334ae_slot1, - FIELD_ftsf336ae_slot1, - FIELD_ftsf337ae_slot1, - FIELD_ftsf338, - FIELD_ftsf339ae_slot1, - FIELD_ftsf340, - FIELD_ftsf341ae_slot1, - FIELD_ftsf342ae_slot1, - FIELD_ftsf343ae_slot1, - FIELD_ftsf344ae_slot1, - FIELD_ftsf346ae_slot1, - FIELD_ftsf347, - FIELD_ftsf348ae_slot1, - FIELD_ftsf349ae_slot1, - FIELD_ftsf350ae_slot1, - FIELD_op0_s4, - FIELD_ftsf212ae_slot0, - FIELD_ftsf213ae_slot0, - FIELD_ftsf214ae_slot0, - FIELD_ftsf215ae_slot0, - FIELD_ftsf216ae_slot0, - FIELD_ftsf217, - FIELD_ftsf218ae_slot0, - FIELD_ftsf219ae_slot0, - FIELD_ftsf220ae_slot0, - FIELD_ftsf221ae_slot0, - FIELD_ftsf222ae_slot0, - FIELD_ftsf223ae_slot0, - FIELD_ftsf224ae_slot0, - FIELD_ftsf225ae_slot0, - FIELD_ftsf226ae_slot0, - FIELD_ftsf227ae_slot0, - FIELD_ftsf228ae_slot0, - FIELD_ftsf229ae_slot0, - FIELD_ftsf230ae_slot0, - FIELD_ftsf231ae_slot0, - FIELD_ftsf232ae_slot0, - FIELD_ftsf233ae_slot0, - FIELD_ftsf234ae_slot0, - FIELD_ftsf235ae_slot0, - FIELD_ftsf236ae_slot0, - FIELD_ftsf237ae_slot0, - FIELD_ftsf238ae_slot0, - FIELD_ftsf239ae_slot0, - FIELD_ftsf240ae_slot0, - FIELD_ftsf241ae_slot0, - FIELD_ftsf242ae_slot0, - FIELD_ftsf243ae_slot0, - FIELD_ftsf244ae_slot0, - FIELD_ftsf245ae_slot0, - FIELD_ftsf246ae_slot0, - FIELD_ftsf247ae_slot0, - FIELD_ftsf248ae_slot0, - FIELD_ftsf249ae_slot0, - FIELD_ftsf250ae_slot0, - FIELD_ftsf251ae_slot0, - FIELD_ftsf252ae_slot0, - FIELD_ftsf253ae_slot0, - FIELD_ftsf254ae_slot0, - FIELD_ftsf255ae_slot0, - FIELD_ftsf256ae_slot0, - FIELD_ftsf257ae_slot0, - FIELD_ftsf258ae_slot0, - FIELD_ftsf259ae_slot0, - FIELD_ftsf260ae_slot0, - FIELD_ftsf261ae_slot0, - FIELD_ftsf262ae_slot0, - FIELD_ftsf263ae_slot0, - FIELD_ftsf264ae_slot0, - FIELD_ftsf265ae_slot0, - FIELD_ftsf266ae_slot0, - FIELD_ftsf267ae_slot0, - FIELD_ftsf268ae_slot0, - FIELD_ftsf269ae_slot0, - FIELD_ftsf270ae_slot0, - FIELD_ftsf271ae_slot0, - FIELD_ftsf272ae_slot0, - FIELD_ftsf273ae_slot0, - FIELD_ftsf274ae_slot0, - FIELD_ftsf275ae_slot0, - FIELD_ftsf276ae_slot0, - FIELD_ftsf277ae_slot0, - FIELD_ftsf278ae_slot0, - FIELD_ftsf279ae_slot0, - FIELD_ftsf281ae_slot0, - FIELD_ftsf282ae_slot0, - FIELD_ftsf283ae_slot0, - FIELD_ftsf284ae_slot0, - FIELD_ftsf286ae_slot0, - FIELD_ftsf288ae_slot0, - FIELD_ftsf290ae_slot0, - FIELD_ftsf292ae_slot0, - FIELD_ftsf293, - FIELD_ftsf294ae_slot0, - FIELD_ftsf295ae_slot0, - FIELD_ftsf296ae_slot0, - FIELD_ftsf297ae_slot0, - FIELD_ftsf298ae_slot0, - FIELD_ftsf299ae_slot0, - FIELD_ftsf300ae_slot0, - FIELD_ftsf301ae_slot0, - FIELD_ftsf302ae_slot0, - FIELD_ftsf303ae_slot0, - FIELD_ftsf304ae_slot0, - FIELD_ftsf306ae_slot0, - FIELD_ftsf308ae_slot0, - FIELD_ftsf309ae_slot0, - FIELD_ftsf310ae_slot0, - FIELD_ftsf311ae_slot0, - FIELD_ftsf312ae_slot0, - FIELD_ftsf313ae_slot0, - FIELD_ftsf314ae_slot0, - FIELD_ftsf315ae_slot0, - FIELD_ftsf316ae_slot0, - FIELD_ftsf317ae_slot0, - FIELD_ftsf318ae_slot0, - FIELD_ftsf319, - FIELD_ftsf320ae_slot0, - FIELD_ftsf321, - FIELD_ftsf322ae_slot0, - FIELD_ftsf323ae_slot0, - FIELD_ftsf324ae_slot0, - FIELD_ftsf325ae_slot0, - FIELD_ftsf326ae_slot0, - FIELD_ftsf328ae_slot0, - FIELD_ftsf329ae_slot0, - FIELD_ftsf352ae_slot0, - FIELD_ftsf353, - FIELD_ftsf354ae_slot0, - FIELD_ftsf356ae_slot0, - FIELD_ftsf357, - FIELD_ftsf358ae_slot0, - FIELD_ftsf359ae_slot0, - FIELD_ftsf360ae_slot0, - FIELD_ftsf361ae_slot0, - FIELD_ftsf362ae_slot0, - FIELD_ftsf364ae_slot0, - FIELD_ftsf365ae_slot0, - FIELD_ftsf366ae_slot0, - FIELD_ftsf368ae_slot0, - FIELD_ftsf369ae_slot0, - FIELD_ae_mul32x24fld, - FIELD_combined1b97e84f_fld115, - FIELD_combined1b97e84f_fld97, - FIELD_combined1b97e84f_fld124, - FIELD_combined1b97e84f_fld79, - FIELD_combined1b97e84f_fld80, - FIELD_combined1b97e84f_fld108, - FIELD_combined1b97e84f_fld101, - FIELD_combined1b97e84f_fld88, - FIELD_combined1b97e84f_fld39, - FIELD_op0_s4_s4, - FIELD_combined1b97e84f_fld83, - FIELD_combined1b97e84f_fld90, - FIELD_combined1b97e84f_fld93, - FIELD_combined1b97e84f_fld138ae_slot0, - FIELD_combined1b97e84f_fld130ae_slot0, - FIELD_combined1b97e84f_fld137ae_slot0, - FIELD_combined1b97e84f_fld135ae_slot0, - FIELD_combined1b97e84f_fld136ae_slot0, - FIELD_combined1b97e84f_fld129ae_slot0, - FIELD_combined1b97e84f_fld127ae_slot0, - FIELD_combined1b97e84f_fld128ae_slot0, - FIELD_combined1b97e84f_fld132ae_slot0, - FIELD_combined1b97e84f_fld134ae_slot0, - FIELD_combined4b12daa6_fld122, - FIELD_combined4b12daa6_fld115, - FIELD_combined4b12daa6_fld85, - FIELD_combined4b12daa6_fld119, - FIELD_combined4b12daa6_fld97, - FIELD_combined4b12daa6_fld124, - FIELD_combined4b12daa6_fld79, - FIELD_combined4b12daa6_fld80, - FIELD_combined4b12daa6_fld108, - FIELD_combined1b97e84f_fld54, - FIELD_combined1b97e84f_fld17, - FIELD_combined1b97e84f_fld76, - FIELD_combined1b97e84f_fld73, - FIELD_combined1b97e84f_fld62, - FIELD_combined1b97e84f_fld24, - FIELD_combined1b97e84f_fld70, - FIELD_combined1b97e84f_fld58, - FIELD_combined1b97e84f_fld131ae_slot1, - FIELD_op0_s3_s3, - FIELD_combined1b97e84f_fld49, - FIELD_combined1b97e84f_fld51, - FIELD_combined1b97e84f_fld23, - FIELD__ar0, - FIELD__ar4, - FIELD__ar8, - FIELD__ar12, - FIELD__mr0, - FIELD__mr1, - FIELD__mr2, - FIELD__mr3, - FIELD__bt16, - FIELD__bs16, - FIELD__br16, - FIELD__brall -}; - - -/* Functional units. */ - -static xtensa_funcUnit_internal funcUnits[] = { - { "ae_add32", 1 }, - { "ae_shift32x4", 1 }, - { "ae_shift32x5", 1 }, - { "ae_subshift", 1 } -}; - -enum xtensa_funcUnit_id { - FUNCUNIT_ae_add32, - FUNCUNIT_ae_shift32x4, - FUNCUNIT_ae_shift32x5, - FUNCUNIT_ae_subshift -}; - - -/* Register files. */ - -enum xtensa_regfile_id { - REGFILE_AR, - REGFILE_MR, - REGFILE_BR, - REGFILE_AE_PR, - REGFILE_AE_QR, - REGFILE_BR2, - REGFILE_BR4, - REGFILE_BR8, - REGFILE_BR16 -}; - -static xtensa_regfile_internal regfiles[] = { - { "AR", "a", REGFILE_AR, 32, 32 }, - { "MR", "m", REGFILE_MR, 32, 4 }, - { "BR", "b", REGFILE_BR, 1, 16 }, - { "AE_PR", "aep", REGFILE_AE_PR, 48, 8 }, - { "AE_QR", "aeq", REGFILE_AE_QR, 56, 4 }, - { "BR2", "b", REGFILE_BR, 2, 8 }, - { "BR4", "b", REGFILE_BR, 4, 4 }, - { "BR8", "b", REGFILE_BR, 8, 2 }, - { "BR16", "b", REGFILE_BR, 16, 1 } -}; - - -/* Interfaces. */ - -static xtensa_interface_internal interfaces[] = { - -}; - - -/* Constant tables. */ - -/* constant table ai4c */ -static const unsigned CONST_TBL_ai4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0x9, - 0xa, - 0xb, - 0xc, - 0xd, - 0xe, - 0xf, - 0 -}; - -/* constant table b4c */ -static const unsigned CONST_TBL_b4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - -/* constant table b4cu */ -static const unsigned CONST_TBL_b4cu_0[] = { - 0x8000, - 0x10000, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - - -/* Instruction operands. */ - -static int -Operand_soffsetx4_decode (uint32 *valp) -{ - unsigned soffsetx4_0; - unsigned offset_0; - offset_0 = *valp & 0x3ffff; - soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); - *valp = soffsetx4_0; - return 0; -} - -static int -Operand_soffsetx4_encode (uint32 *valp) -{ - unsigned offset_0; - unsigned soffsetx4_0; - soffsetx4_0 = *valp; - offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; - *valp = offset_0; - return 0; -} - -static int -Operand_soffsetx4_ator (uint32 *valp, uint32 pc) -{ - *valp -= (pc & ~0x3); - return 0; -} - -static int -Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += (pc & ~0x3); - return 0; -} - -static int -Operand_uimm12x8_decode (uint32 *valp) -{ - unsigned uimm12x8_0; - unsigned imm12_0; - imm12_0 = *valp & 0xfff; - uimm12x8_0 = imm12_0 << 3; - *valp = uimm12x8_0; - return 0; -} - -static int -Operand_uimm12x8_encode (uint32 *valp) -{ - unsigned imm12_0; - unsigned uimm12x8_0; - uimm12x8_0 = *valp; - imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); - *valp = imm12_0; - return 0; -} - -static int -Operand_simm4_decode (uint32 *valp) -{ - unsigned simm4_0; - unsigned mn_0; - mn_0 = *valp & 0xf; - simm4_0 = ((int) mn_0 << 28) >> 28; - *valp = simm4_0; - return 0; -} - -static int -Operand_simm4_encode (uint32 *valp) -{ - unsigned mn_0; - unsigned simm4_0; - simm4_0 = *valp; - mn_0 = (simm4_0 & 0xf); - *valp = mn_0; - return 0; -} - -static int -Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_arr_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} - -static int -Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ars_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} - -static int -Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_art_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} - -static int -Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar0_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x1f) != 0; - return error; -} - -static int -Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar4_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x1f) != 0; - return error; -} - -static int -Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar8_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x1f) != 0; - return error; -} - -static int -Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar12_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x1f) != 0; - return error; -} - -static int -Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ars_entry_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x1f) != 0; - return error; -} - -static int -Operand_immrx4_decode (uint32 *valp) -{ - unsigned immrx4_0; - unsigned r_0; - r_0 = *valp & 0xf; - immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; - *valp = immrx4_0; - return 0; -} - -static int -Operand_immrx4_encode (uint32 *valp) -{ - unsigned r_0; - unsigned immrx4_0; - immrx4_0 = *valp; - r_0 = ((immrx4_0 >> 2) & 0xf); - *valp = r_0; - return 0; -} - -static int -Operand_lsi4x4_decode (uint32 *valp) -{ - unsigned lsi4x4_0; - unsigned r_0; - r_0 = *valp & 0xf; - lsi4x4_0 = r_0 << 2; - *valp = lsi4x4_0; - return 0; -} - -static int -Operand_lsi4x4_encode (uint32 *valp) -{ - unsigned r_0; - unsigned lsi4x4_0; - lsi4x4_0 = *valp; - r_0 = ((lsi4x4_0 >> 2) & 0xf); - *valp = r_0; - return 0; -} - -static int -Operand_simm7_decode (uint32 *valp) -{ - unsigned simm7_0; - unsigned imm7_0; - imm7_0 = *valp & 0x7f; - simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; - *valp = simm7_0; - return 0; -} - -static int -Operand_simm7_encode (uint32 *valp) -{ - unsigned imm7_0; - unsigned simm7_0; - simm7_0 = *valp; - imm7_0 = (simm7_0 & 0x7f); - *valp = imm7_0; - return 0; -} - -static int -Operand_uimm6_decode (uint32 *valp) -{ - unsigned uimm6_0; - unsigned imm6_0; - imm6_0 = *valp & 0x3f; - uimm6_0 = 0x4 + (((0) << 6) | imm6_0); - *valp = uimm6_0; - return 0; -} - -static int -Operand_uimm6_encode (uint32 *valp) -{ - unsigned imm6_0; - unsigned uimm6_0; - uimm6_0 = *valp; - imm6_0 = (uimm6_0 - 0x4) & 0x3f; - *valp = imm6_0; - return 0; -} - -static int -Operand_uimm6_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_uimm6_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ai4const_decode (uint32 *valp) -{ - unsigned ai4const_0; - unsigned t_0; - t_0 = *valp & 0xf; - ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; - *valp = ai4const_0; - return 0; -} - -static int -Operand_ai4const_encode (uint32 *valp) -{ - unsigned t_0; - unsigned ai4const_0; - ai4const_0 = *valp; - switch (ai4const_0) - { - case 0xffffffff: t_0 = 0; break; - case 0x1: t_0 = 0x1; break; - case 0x2: t_0 = 0x2; break; - case 0x3: t_0 = 0x3; break; - case 0x4: t_0 = 0x4; break; - case 0x5: t_0 = 0x5; break; - case 0x6: t_0 = 0x6; break; - case 0x7: t_0 = 0x7; break; - case 0x8: t_0 = 0x8; break; - case 0x9: t_0 = 0x9; break; - case 0xa: t_0 = 0xa; break; - case 0xb: t_0 = 0xb; break; - case 0xc: t_0 = 0xc; break; - case 0xd: t_0 = 0xd; break; - case 0xe: t_0 = 0xe; break; - default: t_0 = 0xf; break; - } - *valp = t_0; - return 0; -} - -static int -Operand_b4const_decode (uint32 *valp) -{ - unsigned b4const_0; - unsigned r_0; - r_0 = *valp & 0xf; - b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; - *valp = b4const_0; - return 0; -} - -static int -Operand_b4const_encode (uint32 *valp) -{ - unsigned r_0; - unsigned b4const_0; - b4const_0 = *valp; - switch (b4const_0) - { - case 0xffffffff: r_0 = 0; break; - case 0x1: r_0 = 0x1; break; - case 0x2: r_0 = 0x2; break; - case 0x3: r_0 = 0x3; break; - case 0x4: r_0 = 0x4; break; - case 0x5: r_0 = 0x5; break; - case 0x6: r_0 = 0x6; break; - case 0x7: r_0 = 0x7; break; - case 0x8: r_0 = 0x8; break; - case 0xa: r_0 = 0x9; break; - case 0xc: r_0 = 0xa; break; - case 0x10: r_0 = 0xb; break; - case 0x20: r_0 = 0xc; break; - case 0x40: r_0 = 0xd; break; - case 0x80: r_0 = 0xe; break; - default: r_0 = 0xf; break; - } - *valp = r_0; - return 0; -} - -static int -Operand_b4constu_decode (uint32 *valp) -{ - unsigned b4constu_0; - unsigned r_0; - r_0 = *valp & 0xf; - b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; - *valp = b4constu_0; - return 0; -} - -static int -Operand_b4constu_encode (uint32 *valp) -{ - unsigned r_0; - unsigned b4constu_0; - b4constu_0 = *valp; - switch (b4constu_0) - { - case 0x8000: r_0 = 0; break; - case 0x10000: r_0 = 0x1; break; - case 0x2: r_0 = 0x2; break; - case 0x3: r_0 = 0x3; break; - case 0x4: r_0 = 0x4; break; - case 0x5: r_0 = 0x5; break; - case 0x6: r_0 = 0x6; break; - case 0x7: r_0 = 0x7; break; - case 0x8: r_0 = 0x8; break; - case 0xa: r_0 = 0x9; break; - case 0xc: r_0 = 0xa; break; - case 0x10: r_0 = 0xb; break; - case 0x20: r_0 = 0xc; break; - case 0x40: r_0 = 0xd; break; - case 0x80: r_0 = 0xe; break; - default: r_0 = 0xf; break; - } - *valp = r_0; - return 0; -} - -static int -Operand_uimm8_decode (uint32 *valp) -{ - unsigned uimm8_0; - unsigned imm8_0; - imm8_0 = *valp & 0xff; - uimm8_0 = imm8_0; - *valp = uimm8_0; - return 0; -} - -static int -Operand_uimm8_encode (uint32 *valp) -{ - unsigned imm8_0; - unsigned uimm8_0; - uimm8_0 = *valp; - imm8_0 = (uimm8_0 & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_uimm8x2_decode (uint32 *valp) -{ - unsigned uimm8x2_0; - unsigned imm8_0; - imm8_0 = *valp & 0xff; - uimm8x2_0 = imm8_0 << 1; - *valp = uimm8x2_0; - return 0; -} - -static int -Operand_uimm8x2_encode (uint32 *valp) -{ - unsigned imm8_0; - unsigned uimm8x2_0; - uimm8x2_0 = *valp; - imm8_0 = ((uimm8x2_0 >> 1) & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_uimm8x4_decode (uint32 *valp) -{ - unsigned uimm8x4_0; - unsigned imm8_0; - imm8_0 = *valp & 0xff; - uimm8x4_0 = imm8_0 << 2; - *valp = uimm8x4_0; - return 0; -} - -static int -Operand_uimm8x4_encode (uint32 *valp) -{ - unsigned imm8_0; - unsigned uimm8x4_0; - uimm8x4_0 = *valp; - imm8_0 = ((uimm8x4_0 >> 2) & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_uimm4x16_decode (uint32 *valp) -{ - unsigned uimm4x16_0; - unsigned op2_0; - op2_0 = *valp & 0xf; - uimm4x16_0 = op2_0 << 4; - *valp = uimm4x16_0; - return 0; -} - -static int -Operand_uimm4x16_encode (uint32 *valp) -{ - unsigned op2_0; - unsigned uimm4x16_0; - uimm4x16_0 = *valp; - op2_0 = ((uimm4x16_0 >> 4) & 0xf); - *valp = op2_0; - return 0; -} - -static int -Operand_simm8_decode (uint32 *valp) -{ - unsigned simm8_0; - unsigned imm8_0; - imm8_0 = *valp & 0xff; - simm8_0 = ((int) imm8_0 << 24) >> 24; - *valp = simm8_0; - return 0; -} - -static int -Operand_simm8_encode (uint32 *valp) -{ - unsigned imm8_0; - unsigned simm8_0; - simm8_0 = *valp; - imm8_0 = (simm8_0 & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_simm8x256_decode (uint32 *valp) -{ - unsigned simm8x256_0; - unsigned imm8_0; - imm8_0 = *valp & 0xff; - simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; - *valp = simm8x256_0; - return 0; -} - -static int -Operand_simm8x256_encode (uint32 *valp) -{ - unsigned imm8_0; - unsigned simm8x256_0; - simm8x256_0 = *valp; - imm8_0 = ((simm8x256_0 >> 8) & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_simm12b_decode (uint32 *valp) -{ - unsigned simm12b_0; - unsigned imm12b_0; - imm12b_0 = *valp & 0xfff; - simm12b_0 = ((int) imm12b_0 << 20) >> 20; - *valp = simm12b_0; - return 0; -} - -static int -Operand_simm12b_encode (uint32 *valp) -{ - unsigned imm12b_0; - unsigned simm12b_0; - simm12b_0 = *valp; - imm12b_0 = (simm12b_0 & 0xfff); - *valp = imm12b_0; - return 0; -} - -static int -Operand_msalp32_decode (uint32 *valp) -{ - unsigned msalp32_0; - unsigned sal_0; - sal_0 = *valp & 0x1f; - msalp32_0 = 0x20 - sal_0; - *valp = msalp32_0; - return 0; -} - -static int -Operand_msalp32_encode (uint32 *valp) -{ - unsigned sal_0; - unsigned msalp32_0; - msalp32_0 = *valp; - sal_0 = (0x20 - msalp32_0) & 0x1f; - *valp = sal_0; - return 0; -} - -static int -Operand_op2p1_decode (uint32 *valp) -{ - unsigned op2p1_0; - unsigned op2_0; - op2_0 = *valp & 0xf; - op2p1_0 = op2_0 + 0x1; - *valp = op2p1_0; - return 0; -} - -static int -Operand_op2p1_encode (uint32 *valp) -{ - unsigned op2_0; - unsigned op2p1_0; - op2p1_0 = *valp; - op2_0 = (op2p1_0 - 0x1) & 0xf; - *valp = op2_0; - return 0; -} - -static int -Operand_label8_decode (uint32 *valp) -{ - unsigned label8_0; - unsigned imm8_0; - imm8_0 = *valp & 0xff; - label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); - *valp = label8_0; - return 0; -} - -static int -Operand_label8_encode (uint32 *valp) -{ - unsigned imm8_0; - unsigned label8_0; - label8_0 = *valp; - imm8_0 = (label8_0 - 0x4) & 0xff; - *valp = imm8_0; - return 0; -} - -static int -Operand_label8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ulabel8_decode (uint32 *valp) -{ - unsigned ulabel8_0; - unsigned imm8_0; - imm8_0 = *valp & 0xff; - ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); - *valp = ulabel8_0; - return 0; -} - -static int -Operand_ulabel8_encode (uint32 *valp) -{ - unsigned imm8_0; - unsigned ulabel8_0; - ulabel8_0 = *valp; - imm8_0 = (ulabel8_0 - 0x4) & 0xff; - *valp = imm8_0; - return 0; -} - -static int -Operand_ulabel8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_label12_decode (uint32 *valp) -{ - unsigned label12_0; - unsigned imm12_0; - imm12_0 = *valp & 0xfff; - label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); - *valp = label12_0; - return 0; -} - -static int -Operand_label12_encode (uint32 *valp) -{ - unsigned imm12_0; - unsigned label12_0; - label12_0 = *valp; - imm12_0 = (label12_0 - 0x4) & 0xfff; - *valp = imm12_0; - return 0; -} - -static int -Operand_label12_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label12_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_soffset_decode (uint32 *valp) -{ - unsigned soffset_0; - unsigned offset_0; - offset_0 = *valp & 0x3ffff; - soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); - *valp = soffset_0; - return 0; -} - -static int -Operand_soffset_encode (uint32 *valp) -{ - unsigned offset_0; - unsigned soffset_0; - soffset_0 = *valp; - offset_0 = (soffset_0 - 0x4) & 0x3ffff; - *valp = offset_0; - return 0; -} - -static int -Operand_soffset_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_soffset_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_uimm16x4_decode (uint32 *valp) -{ - unsigned uimm16x4_0; - unsigned imm16_0; - imm16_0 = *valp & 0xffff; - uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; - *valp = uimm16x4_0; - return 0; -} - -static int -Operand_uimm16x4_encode (uint32 *valp) -{ - unsigned imm16_0; - unsigned uimm16x4_0; - uimm16x4_0 = *valp; - imm16_0 = (uimm16x4_0 >> 2) & 0xffff; - *valp = imm16_0; - return 0; -} - -static int -Operand_uimm16x4_ator (uint32 *valp, uint32 pc) -{ - *valp -= ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_bbi_decode (uint32 *valp) -{ - unsigned bbi_0; - bbi_0 = *valp & 0x1f; - bbi_0 = (0 << 5) | bbi_0; - *valp = bbi_0; - return 0; -} - -static int -Operand_bbi_encode (uint32 *valp) -{ - unsigned bbi_0; - bbi_0 = *valp; - bbi_0 = (bbi_0 & 0x1f); - *valp = bbi_0; - return 0; -} - -static int -Operand_sae_decode (uint32 *valp) -{ - unsigned sae_0; - sae_0 = *valp & 0x1f; - sae_0 = (0 << 5) | sae_0; - *valp = sae_0; - return 0; -} - -static int -Operand_sae_encode (uint32 *valp) -{ - unsigned sae_0; - sae_0 = *valp; - sae_0 = (sae_0 & 0x1f); - *valp = sae_0; - return 0; -} - -static int -Operand_sas_decode (uint32 *valp) -{ - unsigned sas_0; - sas_0 = *valp & 0x1f; - sas_0 = (0 << 5) | sas_0; - *valp = sas_0; - return 0; -} - -static int -Operand_sas_encode (uint32 *valp) -{ - unsigned sas_0; - sas_0 = *valp; - sas_0 = (sas_0 & 0x1f); - *valp = sas_0; - return 0; -} - -static int -Operand_sargt_decode (uint32 *valp) -{ - unsigned sargt_0; - sargt_0 = *valp & 0x1f; - sargt_0 = (0 << 5) | sargt_0; - *valp = sargt_0; - return 0; -} - -static int -Operand_sargt_encode (uint32 *valp) -{ - unsigned sargt_0; - sargt_0 = *valp; - sargt_0 = (sargt_0 & 0x1f); - *valp = sargt_0; - return 0; -} - -static int -Operand_s_decode (uint32 *valp) -{ - unsigned s_0; - s_0 = *valp & 0xf; - s_0 = (0 << 4) | s_0; - *valp = s_0; - return 0; -} - -static int -Operand_s_encode (uint32 *valp) -{ - unsigned s_0; - s_0 = *valp; - s_0 = (s_0 & 0xf); - *valp = s_0; - return 0; -} - -static int -Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mx_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_my_decode (uint32 *valp) -{ - *valp += 2; - return 0; -} - -static int -Operand_my_encode (uint32 *valp) -{ - int error; - error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); - *valp = *valp & 1; - return error; -} - -static int -Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mw_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mr0_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mr1_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mr2_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mr3_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_immt_decode (uint32 *valp) -{ - unsigned immt_0; - unsigned t_0; - t_0 = *valp & 0xf; - immt_0 = t_0; - *valp = immt_0; - return 0; -} - -static int -Operand_immt_encode (uint32 *valp) -{ - unsigned t_0; - unsigned immt_0; - immt_0 = *valp; - t_0 = immt_0 & 0xf; - *valp = t_0; - return 0; -} - -static int -Operand_imms_decode (uint32 *valp) -{ - unsigned imms_0; - unsigned s_0; - s_0 = *valp & 0xf; - imms_0 = s_0; - *valp = imms_0; - return 0; -} - -static int -Operand_imms_encode (uint32 *valp) -{ - unsigned s_0; - unsigned imms_0; - imms_0 = *valp; - s_0 = imms_0 & 0xf; - *valp = s_0; - return 0; -} - -static int -Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_bt_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} - -static int -Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_bs_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} - -static int -Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_br_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} - -static int -Operand_bt2_decode (uint32 *valp) -{ - *valp = *valp << 1; - return 0; -} - -static int -Operand_bt2_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x7 << 1)) != 0; - *valp = *valp >> 1; - return error; -} - -static int -Operand_bs2_decode (uint32 *valp) -{ - *valp = *valp << 1; - return 0; -} - -static int -Operand_bs2_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x7 << 1)) != 0; - *valp = *valp >> 1; - return error; -} - -static int -Operand_br2_decode (uint32 *valp) -{ - *valp = *valp << 1; - return 0; -} - -static int -Operand_br2_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x7 << 1)) != 0; - *valp = *valp >> 1; - return error; -} - -static int -Operand_bt4_decode (uint32 *valp) -{ - *valp = *valp << 2; - return 0; -} - -static int -Operand_bt4_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x3 << 2)) != 0; - *valp = *valp >> 2; - return error; -} - -static int -Operand_bs4_decode (uint32 *valp) -{ - *valp = *valp << 2; - return 0; -} - -static int -Operand_bs4_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x3 << 2)) != 0; - *valp = *valp >> 2; - return error; -} - -static int -Operand_br4_decode (uint32 *valp) -{ - *valp = *valp << 2; - return 0; -} - -static int -Operand_br4_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x3 << 2)) != 0; - *valp = *valp >> 2; - return error; -} - -static int -Operand_bt8_decode (uint32 *valp) -{ - *valp = *valp << 3; - return 0; -} - -static int -Operand_bt8_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x1 << 3)) != 0; - *valp = *valp >> 3; - return error; -} - -static int -Operand_bs8_decode (uint32 *valp) -{ - *valp = *valp << 3; - return 0; -} - -static int -Operand_bs8_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x1 << 3)) != 0; - *valp = *valp >> 3; - return error; -} - -static int -Operand_br8_decode (uint32 *valp) -{ - *valp = *valp << 3; - return 0; -} - -static int -Operand_br8_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x1 << 3)) != 0; - *valp = *valp >> 3; - return error; -} - -static int -Operand_bt16_decode (uint32 *valp) -{ - *valp = *valp << 4; - return 0; -} - -static int -Operand_bt16_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0 << 4)) != 0; - *valp = *valp >> 4; - return error; -} - -static int -Operand_bs16_decode (uint32 *valp) -{ - *valp = *valp << 4; - return 0; -} - -static int -Operand_bs16_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0 << 4)) != 0; - *valp = *valp >> 4; - return error; -} - -static int -Operand_br16_decode (uint32 *valp) -{ - *valp = *valp << 4; - return 0; -} - -static int -Operand_br16_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0 << 4)) != 0; - *valp = *valp >> 4; - return error; -} - -static int -Operand_brall_decode (uint32 *valp) -{ - *valp = *valp << 4; - return 0; -} - -static int -Operand_brall_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0 << 4)) != 0; - *valp = *valp >> 4; - return error; -} - -static int -Operand_tp7_decode (uint32 *valp) -{ - unsigned tp7_0; - unsigned t_0; - t_0 = *valp & 0xf; - tp7_0 = t_0 + 0x7; - *valp = tp7_0; - return 0; -} - -static int -Operand_tp7_encode (uint32 *valp) -{ - unsigned t_0; - unsigned tp7_0; - tp7_0 = *valp; - t_0 = (tp7_0 - 0x7) & 0xf; - *valp = t_0; - return 0; -} - -static int -Operand_xt_wbr15_label_decode (uint32 *valp) -{ - unsigned xt_wbr15_label_0; - unsigned xt_wbr15_imm_0; - xt_wbr15_imm_0 = *valp & 0x7fff; - xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); - *valp = xt_wbr15_label_0; - return 0; -} - -static int -Operand_xt_wbr15_label_encode (uint32 *valp) -{ - unsigned xt_wbr15_imm_0; - unsigned xt_wbr15_label_0; - xt_wbr15_label_0 = *valp; - xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; - *valp = xt_wbr15_imm_0; - return 0; -} - -static int -Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_xt_wbr18_label_decode (uint32 *valp) -{ - unsigned xt_wbr18_label_0; - unsigned xt_wbr18_imm_0; - xt_wbr18_imm_0 = *valp & 0x3ffff; - xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); - *valp = xt_wbr18_label_0; - return 0; -} - -static int -Operand_xt_wbr18_label_encode (uint32 *valp) -{ - unsigned xt_wbr18_imm_0; - unsigned xt_wbr18_label_0; - xt_wbr18_label_0 = *valp; - xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; - *valp = xt_wbr18_imm_0; - return 0; -} - -static int -Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ae_samt32_decode (uint32 *valp) -{ - unsigned ae_samt32_0; - unsigned ftsf14_0; - ftsf14_0 = *valp & 0x1f; - ae_samt32_0 = (0 << 5) | ftsf14_0; - *valp = ae_samt32_0; - return 0; -} - -static int -Operand_ae_samt32_encode (uint32 *valp) -{ - unsigned ftsf14_0; - unsigned ae_samt32_0; - ae_samt32_0 = *valp; - ftsf14_0 = (ae_samt32_0 & 0x1f); - *valp = ftsf14_0; - return 0; -} - -static int -Operand_pr0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_pr0_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x7) != 0; - return error; -} - -static int -Operand_qr0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_qr0_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_mac_qr0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mac_qr0_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_ae_lsimm16_decode (uint32 *valp) -{ - unsigned ae_lsimm16_0; - unsigned t_0; - t_0 = *valp & 0xf; - ae_lsimm16_0 = (((int) t_0 << 28) >> 28) << 1; - *valp = ae_lsimm16_0; - return 0; -} - -static int -Operand_ae_lsimm16_encode (uint32 *valp) -{ - unsigned t_0; - unsigned ae_lsimm16_0; - ae_lsimm16_0 = *valp; - t_0 = ((ae_lsimm16_0 >> 1) & 0xf); - *valp = t_0; - return 0; -} - -static int -Operand_ae_lsimm32_decode (uint32 *valp) -{ - unsigned ae_lsimm32_0; - unsigned t_0; - t_0 = *valp & 0xf; - ae_lsimm32_0 = (((int) t_0 << 28) >> 28) << 2; - *valp = ae_lsimm32_0; - return 0; -} - -static int -Operand_ae_lsimm32_encode (uint32 *valp) -{ - unsigned t_0; - unsigned ae_lsimm32_0; - ae_lsimm32_0 = *valp; - t_0 = ((ae_lsimm32_0 >> 2) & 0xf); - *valp = t_0; - return 0; -} - -static int -Operand_ae_lsimm64_decode (uint32 *valp) -{ - unsigned ae_lsimm64_0; - unsigned t_0; - t_0 = *valp & 0xf; - ae_lsimm64_0 = (((int) t_0 << 28) >> 28) << 3; - *valp = ae_lsimm64_0; - return 0; -} - -static int -Operand_ae_lsimm64_encode (uint32 *valp) -{ - unsigned t_0; - unsigned ae_lsimm64_0; - ae_lsimm64_0 = *valp; - t_0 = ((ae_lsimm64_0 >> 3) & 0xf); - *valp = t_0; - return 0; -} - -static int -Operand_ae_samt64_decode (uint32 *valp) -{ - unsigned ae_samt64_0; - unsigned ae_samt_s_t_0; - ae_samt_s_t_0 = *valp & 0x3f; - ae_samt64_0 = (0 << 6) | ae_samt_s_t_0; - *valp = ae_samt64_0; - return 0; -} - -static int -Operand_ae_samt64_encode (uint32 *valp) -{ - unsigned ae_samt_s_t_0; - unsigned ae_samt64_0; - ae_samt64_0 = *valp; - ae_samt_s_t_0 = (ae_samt64_0 & 0x3f); - *valp = ae_samt_s_t_0; - return 0; -} - -static int -Operand_ae_ohba_decode (uint32 *valp) -{ - unsigned ae_ohba_0; - unsigned ae_fld_ohba_0; - ae_fld_ohba_0 = *valp & 0xf; - ae_ohba_0 = (0 << 5) | (((((ae_fld_ohba_0 & 0xf))) == 0) << 4) | ((ae_fld_ohba_0 & 0xf)); - *valp = ae_ohba_0; - return 0; -} - -static int -Operand_ae_ohba_encode (uint32 *valp) -{ - unsigned ae_fld_ohba_0; - unsigned ae_ohba_0; - ae_ohba_0 = *valp; - ae_fld_ohba_0 = (ae_ohba_0 & 0xf); - *valp = ae_fld_ohba_0; - return 0; -} - -static int -Operand_ae_ohba2_decode (uint32 *valp) -{ - unsigned ae_ohba2_0; - unsigned ae_fld_ohba2_0; - ae_fld_ohba2_0 = *valp & 0xf; - ae_ohba2_0 = (0 << 5) | (((((ae_fld_ohba2_0 & 0xf))) == 0) << 4) | ((ae_fld_ohba2_0 & 0xf)); - *valp = ae_ohba2_0; - return 0; -} - -static int -Operand_ae_ohba2_encode (uint32 *valp) -{ - unsigned ae_fld_ohba2_0; - unsigned ae_ohba2_0; - ae_ohba2_0 = *valp; - ae_fld_ohba2_0 = (ae_ohba2_0 & 0xf); - *valp = ae_fld_ohba2_0; - return 0; -} - -static int -Operand_pr_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_pr_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x7) != 0; - return error; -} - -static int -Operand_cvt_pr_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_cvt_pr_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x7) != 0; - return error; -} - -static int -Operand_qr0_rw_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_qr0_rw_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_mac_qr0_rw_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mac_qr0_rw_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_qr1_w_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_qr1_w_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_mac_qr1_w_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mac_qr1_w_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_ps_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ps_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x7) != 0; - return error; -} - -static int -Operand_alupppb_ps_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_alupppb_ps_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x7) != 0; - return error; -} - -static xtensa_operand_internal operands[] = { - { "soffsetx4", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_soffsetx4_encode, Operand_soffsetx4_decode, - Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, - { "uimm12x8", FIELD_imm12, -1, 0, - 0, - Operand_uimm12x8_encode, Operand_uimm12x8_decode, - 0, 0 }, - { "simm4", FIELD_mn, -1, 0, - 0, - Operand_simm4_encode, Operand_simm4_decode, - 0, 0 }, - { "arr", FIELD_r, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_arr_encode, Operand_arr_decode, - 0, 0 }, - { "ars", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_ars_encode, Operand_ars_decode, - 0, 0 }, - { "*ars_invisible", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ars_encode, Operand_ars_decode, - 0, 0 }, - { "art", FIELD_t, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_art_encode, Operand_art_decode, - 0, 0 }, - { "ar0", FIELD__ar0, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar0_encode, Operand_ar0_decode, - 0, 0 }, - { "ar4", FIELD__ar4, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar4_encode, Operand_ar4_decode, - 0, 0 }, - { "ar8", FIELD__ar8, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar8_encode, Operand_ar8_decode, - 0, 0 }, - { "ar12", FIELD__ar12, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar12_encode, Operand_ar12_decode, - 0, 0 }, - { "ars_entry", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_ars_entry_encode, Operand_ars_entry_decode, - 0, 0 }, - { "immrx4", FIELD_r, -1, 0, - 0, - Operand_immrx4_encode, Operand_immrx4_decode, - 0, 0 }, - { "lsi4x4", FIELD_r, -1, 0, - 0, - Operand_lsi4x4_encode, Operand_lsi4x4_decode, - 0, 0 }, - { "simm7", FIELD_imm7, -1, 0, - 0, - Operand_simm7_encode, Operand_simm7_decode, - 0, 0 }, - { "uimm6", FIELD_imm6, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_uimm6_encode, Operand_uimm6_decode, - Operand_uimm6_ator, Operand_uimm6_rtoa }, - { "ai4const", FIELD_t, -1, 0, - 0, - Operand_ai4const_encode, Operand_ai4const_decode, - 0, 0 }, - { "b4const", FIELD_r, -1, 0, - 0, - Operand_b4const_encode, Operand_b4const_decode, - 0, 0 }, - { "b4constu", FIELD_r, -1, 0, - 0, - Operand_b4constu_encode, Operand_b4constu_decode, - 0, 0 }, - { "uimm8", FIELD_imm8, -1, 0, - 0, - Operand_uimm8_encode, Operand_uimm8_decode, - 0, 0 }, - { "uimm8x2", FIELD_imm8, -1, 0, - 0, - Operand_uimm8x2_encode, Operand_uimm8x2_decode, - 0, 0 }, - { "uimm8x4", FIELD_imm8, -1, 0, - 0, - Operand_uimm8x4_encode, Operand_uimm8x4_decode, - 0, 0 }, - { "uimm4x16", FIELD_op2, -1, 0, - 0, - Operand_uimm4x16_encode, Operand_uimm4x16_decode, - 0, 0 }, - { "simm8", FIELD_imm8, -1, 0, - 0, - Operand_simm8_encode, Operand_simm8_decode, - 0, 0 }, - { "simm8x256", FIELD_imm8, -1, 0, - 0, - Operand_simm8x256_encode, Operand_simm8x256_decode, - 0, 0 }, - { "simm12b", FIELD_imm12b, -1, 0, - 0, - Operand_simm12b_encode, Operand_simm12b_decode, - 0, 0 }, - { "msalp32", FIELD_sal, -1, 0, - 0, - Operand_msalp32_encode, Operand_msalp32_decode, - 0, 0 }, - { "op2p1", FIELD_op2, -1, 0, - 0, - Operand_op2p1_encode, Operand_op2p1_decode, - 0, 0 }, - { "label8", FIELD_imm8, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_label8_encode, Operand_label8_decode, - Operand_label8_ator, Operand_label8_rtoa }, - { "ulabel8", FIELD_imm8, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_ulabel8_encode, Operand_ulabel8_decode, - Operand_ulabel8_ator, Operand_ulabel8_rtoa }, - { "label12", FIELD_imm12, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_label12_encode, Operand_label12_decode, - Operand_label12_ator, Operand_label12_rtoa }, - { "soffset", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_soffset_encode, Operand_soffset_decode, - Operand_soffset_ator, Operand_soffset_rtoa }, - { "uimm16x4", FIELD_imm16, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_uimm16x4_encode, Operand_uimm16x4_decode, - Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, - { "bbi", FIELD_bbi, -1, 0, - 0, - Operand_bbi_encode, Operand_bbi_decode, - 0, 0 }, - { "sae", FIELD_sae, -1, 0, - 0, - Operand_sae_encode, Operand_sae_decode, - 0, 0 }, - { "sas", FIELD_sas, -1, 0, - 0, - Operand_sas_encode, Operand_sas_decode, - 0, 0 }, - { "sargt", FIELD_sargt, -1, 0, - 0, - Operand_sargt_encode, Operand_sargt_decode, - 0, 0 }, - { "s", FIELD_s, -1, 0, - 0, - Operand_s_encode, Operand_s_decode, - 0, 0 }, - { "mx", FIELD_x, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, - Operand_mx_encode, Operand_mx_decode, - 0, 0 }, - { "my", FIELD_y, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, - Operand_my_encode, Operand_my_decode, - 0, 0 }, - { "mw", FIELD_w, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_mw_encode, Operand_mw_decode, - 0, 0 }, - { "mr0", FIELD__mr0, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr0_encode, Operand_mr0_decode, - 0, 0 }, - { "mr1", FIELD__mr1, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr1_encode, Operand_mr1_decode, - 0, 0 }, - { "mr2", FIELD__mr2, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr2_encode, Operand_mr2_decode, - 0, 0 }, - { "mr3", FIELD__mr3, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr3_encode, Operand_mr3_decode, - 0, 0 }, - { "immt", FIELD_t, -1, 0, - 0, - Operand_immt_encode, Operand_immt_decode, - 0, 0 }, - { "imms", FIELD_s, -1, 0, - 0, - Operand_imms_encode, Operand_imms_decode, - 0, 0 }, - { "bt", FIELD_t, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_bt_encode, Operand_bt_decode, - 0, 0 }, - { "bs", FIELD_s, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_bs_encode, Operand_bs_decode, - 0, 0 }, - { "br", FIELD_r, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_br_encode, Operand_br_decode, - 0, 0 }, - { "bt2", FIELD_t2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - Operand_bt2_encode, Operand_bt2_decode, - 0, 0 }, - { "bs2", FIELD_s2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - Operand_bs2_encode, Operand_bs2_decode, - 0, 0 }, - { "br2", FIELD_r2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - Operand_br2_encode, Operand_br2_decode, - 0, 0 }, - { "bt4", FIELD_t4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - Operand_bt4_encode, Operand_bt4_decode, - 0, 0 }, - { "bs4", FIELD_s4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - Operand_bs4_encode, Operand_bs4_decode, - 0, 0 }, - { "br4", FIELD_r4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - Operand_br4_encode, Operand_br4_decode, - 0, 0 }, - { "bt8", FIELD_t8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - Operand_bt8_encode, Operand_bt8_decode, - 0, 0 }, - { "bs8", FIELD_s8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - Operand_bs8_encode, Operand_bs8_decode, - 0, 0 }, - { "br8", FIELD_r8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - Operand_br8_encode, Operand_br8_decode, - 0, 0 }, - { "bt16", FIELD__bt16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - Operand_bt16_encode, Operand_bt16_decode, - 0, 0 }, - { "bs16", FIELD__bs16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - Operand_bs16_encode, Operand_bs16_decode, - 0, 0 }, - { "br16", FIELD__br16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - Operand_br16_encode, Operand_br16_decode, - 0, 0 }, - { "brall", FIELD__brall, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_brall_encode, Operand_brall_decode, - 0, 0 }, - { "tp7", FIELD_t, -1, 0, - 0, - Operand_tp7_encode, Operand_tp7_decode, - 0, 0 }, - { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, - Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, - { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, - Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, - { "ae_samt32", FIELD_ftsf14, -1, 0, - 0, - Operand_ae_samt32_encode, Operand_ae_samt32_decode, - 0, 0 }, - { "pr0", FIELD_ftsf12, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_pr0_encode, Operand_pr0_decode, - 0, 0 }, - { "qr0", FIELD_ftsf13, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_qr0_encode, Operand_qr0_decode, - 0, 0 }, - { "mac_qr0", FIELD_ftsf13, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_mac_qr0_encode, Operand_mac_qr0_decode, - 0, 0 }, - { "ae_lsimm16", FIELD_t, -1, 0, - 0, - Operand_ae_lsimm16_encode, Operand_ae_lsimm16_decode, - 0, 0 }, - { "ae_lsimm32", FIELD_t, -1, 0, - 0, - Operand_ae_lsimm32_encode, Operand_ae_lsimm32_decode, - 0, 0 }, - { "ae_lsimm64", FIELD_t, -1, 0, - 0, - Operand_ae_lsimm64_encode, Operand_ae_lsimm64_decode, - 0, 0 }, - { "ae_samt64", FIELD_ae_samt_s_t, -1, 0, - 0, - Operand_ae_samt64_encode, Operand_ae_samt64_decode, - 0, 0 }, - { "ae_ohba", FIELD_ae_fld_ohba, -1, 0, - 0, - Operand_ae_ohba_encode, Operand_ae_ohba_decode, - 0, 0 }, - { "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0, - 0, - Operand_ae_ohba2_encode, Operand_ae_ohba2_decode, - 0, 0 }, - { "pr", FIELD_ae_r20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_pr_encode, Operand_pr_decode, - 0, 0 }, - { "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_cvt_pr_encode, Operand_cvt_pr_decode, - 0, 0 }, - { "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_qr0_rw_encode, Operand_qr0_rw_decode, - 0, 0 }, - { "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_mac_qr0_rw_encode, Operand_mac_qr0_rw_decode, - 0, 0 }, - { "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_qr1_w_encode, Operand_qr1_w_decode, - 0, 0 }, - { "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_mac_qr1_w_encode, Operand_mac_qr1_w_decode, - 0, 0 }, - { "ps", FIELD_ae_s20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_ps_encode, Operand_ps_decode, - 0, 0 }, - { "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_alupppb_ps_encode, Operand_alupppb_ps_decode, - 0, 0 }, - { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, - { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, - { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, - { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, - { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, - { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, - { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, - { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, - { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, - { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, - { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, - { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, - { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, - { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, - { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, - { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, - { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, - { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, - { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, - { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, - { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, - { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, - { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 }, - { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 }, - { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 }, - { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 }, - { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 }, - { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 }, - { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 }, - { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 }, - { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 }, - { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, - { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, - { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, - { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, - { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, - { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, - { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, - { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, - { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r3", FIELD_ae_r3, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s_non_samt", FIELD_ae_s_non_samt, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s3", FIELD_ae_s3, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r32", FIELD_ae_r32, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_samt_s_t", FIELD_ae_samt_s_t, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf14", FIELD_ftsf14, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf21ae_slot1", FIELD_ftsf21ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf22ae_slot1", FIELD_ftsf22ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf23ae_slot1", FIELD_ftsf23ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf24ae_slot1", FIELD_ftsf24ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf25ae_slot1", FIELD_ftsf25ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf26ae_slot1", FIELD_ftsf26ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf27ae_slot1", FIELD_ftsf27ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf28ae_slot1", FIELD_ftsf28ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf29ae_slot1", FIELD_ftsf29ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf30ae_slot1", FIELD_ftsf30ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf31ae_slot1", FIELD_ftsf31ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf32ae_slot1", FIELD_ftsf32ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf33ae_slot1", FIELD_ftsf33ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf34ae_slot1", FIELD_ftsf34ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf35ae_slot1", FIELD_ftsf35ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf36ae_slot1", FIELD_ftsf36ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf37ae_slot1", FIELD_ftsf37ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf38ae_slot1", FIELD_ftsf38ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf39ae_slot1", FIELD_ftsf39ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf40ae_slot1", FIELD_ftsf40ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf41ae_slot1", FIELD_ftsf41ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf42ae_slot1", FIELD_ftsf42ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf43ae_slot1", FIELD_ftsf43ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf44ae_slot1", FIELD_ftsf44ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf45ae_slot1", FIELD_ftsf45ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf46ae_slot1", FIELD_ftsf46ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf47ae_slot1", FIELD_ftsf47ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf48ae_slot1", FIELD_ftsf48ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf49ae_slot1", FIELD_ftsf49ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf50ae_slot1", FIELD_ftsf50ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf51ae_slot1", FIELD_ftsf51ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf52ae_slot1", FIELD_ftsf52ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf53ae_slot1", FIELD_ftsf53ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf54ae_slot1", FIELD_ftsf54ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf55ae_slot1", FIELD_ftsf55ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf56ae_slot1", FIELD_ftsf56ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf57ae_slot1", FIELD_ftsf57ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf58ae_slot1", FIELD_ftsf58ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf59ae_slot1", FIELD_ftsf59ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf60ae_slot1", FIELD_ftsf60ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf61ae_slot1", FIELD_ftsf61ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf63ae_slot1", FIELD_ftsf63ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf64ae_slot1", FIELD_ftsf64ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf66ae_slot1", FIELD_ftsf66ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf67ae_slot1", FIELD_ftsf67ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf69ae_slot1", FIELD_ftsf69ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf71ae_slot1", FIELD_ftsf71ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf72ae_slot1", FIELD_ftsf72ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf73ae_slot1", FIELD_ftsf73ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf75ae_slot1", FIELD_ftsf75ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf76ae_slot1", FIELD_ftsf76ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf77ae_slot1", FIELD_ftsf77ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf78ae_slot1", FIELD_ftsf78ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf79ae_slot1", FIELD_ftsf79ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf80ae_slot1", FIELD_ftsf80ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf81ae_slot1", FIELD_ftsf81ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf82ae_slot1", FIELD_ftsf82ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf84ae_slot1", FIELD_ftsf84ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf86ae_slot1", FIELD_ftsf86ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf87ae_slot1", FIELD_ftsf87ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf88ae_slot1", FIELD_ftsf88ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf89ae_slot1", FIELD_ftsf89ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf90ae_slot1", FIELD_ftsf90ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf91ae_slot1", FIELD_ftsf91ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf92ae_slot1", FIELD_ftsf92ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf94ae_slot1", FIELD_ftsf94ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf96ae_slot1", FIELD_ftsf96ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf97ae_slot1", FIELD_ftsf97ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf98ae_slot1", FIELD_ftsf98ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf99ae_slot1", FIELD_ftsf99ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf100ae_slot1", FIELD_ftsf100ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf101ae_slot1", FIELD_ftsf101ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf103ae_slot1", FIELD_ftsf103ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf104ae_slot1", FIELD_ftsf104ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf105ae_slot1", FIELD_ftsf105ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf106ae_slot1", FIELD_ftsf106ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf107ae_slot1", FIELD_ftsf107ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf108ae_slot1", FIELD_ftsf108ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf109ae_slot1", FIELD_ftsf109ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf110ae_slot1", FIELD_ftsf110ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf111ae_slot1", FIELD_ftsf111ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf112ae_slot1", FIELD_ftsf112ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf113ae_slot1", FIELD_ftsf113ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf114ae_slot1", FIELD_ftsf114ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf115ae_slot1", FIELD_ftsf115ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf116ae_slot1", FIELD_ftsf116ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf118ae_slot1", FIELD_ftsf118ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf119ae_slot1", FIELD_ftsf119ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf120ae_slot1", FIELD_ftsf120ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf122ae_slot1", FIELD_ftsf122ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf124ae_slot1", FIELD_ftsf124ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf125ae_slot1", FIELD_ftsf125ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf126ae_slot1", FIELD_ftsf126ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf127ae_slot1", FIELD_ftsf127ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf128ae_slot1", FIELD_ftsf128ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf129ae_slot1", FIELD_ftsf129ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf130ae_slot1", FIELD_ftsf130ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf131ae_slot1", FIELD_ftsf131ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf132ae_slot1", FIELD_ftsf132ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf133ae_slot1", FIELD_ftsf133ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf134ae_slot1", FIELD_ftsf134ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf135ae_slot1", FIELD_ftsf135ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf136ae_slot1", FIELD_ftsf136ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf137ae_slot1", FIELD_ftsf137ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf138ae_slot1", FIELD_ftsf138ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf139ae_slot1", FIELD_ftsf139ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf140ae_slot1", FIELD_ftsf140ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf141ae_slot1", FIELD_ftsf141ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf142ae_slot1", FIELD_ftsf142ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf143ae_slot1", FIELD_ftsf143ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf144ae_slot1", FIELD_ftsf144ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf145ae_slot1", FIELD_ftsf145ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf146ae_slot1", FIELD_ftsf146ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf147ae_slot1", FIELD_ftsf147ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf148ae_slot1", FIELD_ftsf148ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf149ae_slot1", FIELD_ftsf149ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf150ae_slot1", FIELD_ftsf150ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf151ae_slot1", FIELD_ftsf151ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf152ae_slot1", FIELD_ftsf152ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf153ae_slot1", FIELD_ftsf153ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf154ae_slot1", FIELD_ftsf154ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf155ae_slot1", FIELD_ftsf155ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf156ae_slot1", FIELD_ftsf156ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf157ae_slot1", FIELD_ftsf157ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf158ae_slot1", FIELD_ftsf158ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf159ae_slot1", FIELD_ftsf159ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf160ae_slot1", FIELD_ftsf160ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf161ae_slot1", FIELD_ftsf161ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf162ae_slot1", FIELD_ftsf162ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf163ae_slot1", FIELD_ftsf163ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf164ae_slot1", FIELD_ftsf164ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf165ae_slot1", FIELD_ftsf165ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf166ae_slot1", FIELD_ftsf166ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf167ae_slot1", FIELD_ftsf167ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf168ae_slot1", FIELD_ftsf168ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf169ae_slot1", FIELD_ftsf169ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf170ae_slot1", FIELD_ftsf170ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf171ae_slot1", FIELD_ftsf171ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf172ae_slot1", FIELD_ftsf172ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf173ae_slot1", FIELD_ftsf173ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf174ae_slot1", FIELD_ftsf174ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf175ae_slot1", FIELD_ftsf175ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf176ae_slot1", FIELD_ftsf176ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf177ae_slot1", FIELD_ftsf177ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf178ae_slot1", FIELD_ftsf178ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf179ae_slot1", FIELD_ftsf179ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf180ae_slot1", FIELD_ftsf180ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf181ae_slot1", FIELD_ftsf181ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf182ae_slot1", FIELD_ftsf182ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf183ae_slot1", FIELD_ftsf183ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf184ae_slot1", FIELD_ftsf184ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf185ae_slot1", FIELD_ftsf185ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf186ae_slot1", FIELD_ftsf186ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf187ae_slot1", FIELD_ftsf187ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf188ae_slot1", FIELD_ftsf188ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf189ae_slot1", FIELD_ftsf189ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - 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{ "ftsf352ae_slot0", FIELD_ftsf352ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf353", FIELD_ftsf353, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf354ae_slot0", FIELD_ftsf354ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf356ae_slot0", FIELD_ftsf356ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf357", FIELD_ftsf357, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf358ae_slot0", FIELD_ftsf358ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf359ae_slot0", FIELD_ftsf359ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf360ae_slot0", FIELD_ftsf360ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf361ae_slot0", FIELD_ftsf361ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf362ae_slot0", FIELD_ftsf362ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf364ae_slot0", FIELD_ftsf364ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf365ae_slot0", FIELD_ftsf365ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf366ae_slot0", FIELD_ftsf366ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf368ae_slot0", FIELD_ftsf368ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf369ae_slot0", FIELD_ftsf369ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_mul32x24fld", FIELD_ae_mul32x24fld, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld115", FIELD_combined1b97e84f_fld115, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld97", FIELD_combined1b97e84f_fld97, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld124", FIELD_combined1b97e84f_fld124, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld79", FIELD_combined1b97e84f_fld79, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld80", FIELD_combined1b97e84f_fld80, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld108", FIELD_combined1b97e84f_fld108, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld101", FIELD_combined1b97e84f_fld101, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld88", FIELD_combined1b97e84f_fld88, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld39", FIELD_combined1b97e84f_fld39, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s4_s4", FIELD_op0_s4_s4, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld83", FIELD_combined1b97e84f_fld83, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld90", FIELD_combined1b97e84f_fld90, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld93", FIELD_combined1b97e84f_fld93, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld138ae_slot0", FIELD_combined1b97e84f_fld138ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld130ae_slot0", FIELD_combined1b97e84f_fld130ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld137ae_slot0", FIELD_combined1b97e84f_fld137ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld135ae_slot0", FIELD_combined1b97e84f_fld135ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld136ae_slot0", FIELD_combined1b97e84f_fld136ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld129ae_slot0", FIELD_combined1b97e84f_fld129ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld127ae_slot0", FIELD_combined1b97e84f_fld127ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld128ae_slot0", FIELD_combined1b97e84f_fld128ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld132ae_slot0", FIELD_combined1b97e84f_fld132ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld134ae_slot0", FIELD_combined1b97e84f_fld134ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld122", FIELD_combined4b12daa6_fld122, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld115", FIELD_combined4b12daa6_fld115, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld85", FIELD_combined4b12daa6_fld85, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld119", FIELD_combined4b12daa6_fld119, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld97", FIELD_combined4b12daa6_fld97, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld124", FIELD_combined4b12daa6_fld124, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld79", FIELD_combined4b12daa6_fld79, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld80", FIELD_combined4b12daa6_fld80, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld108", FIELD_combined4b12daa6_fld108, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld54", FIELD_combined1b97e84f_fld54, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld17", FIELD_combined1b97e84f_fld17, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld76", FIELD_combined1b97e84f_fld76, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld73", FIELD_combined1b97e84f_fld73, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld62", FIELD_combined1b97e84f_fld62, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld24", FIELD_combined1b97e84f_fld24, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld70", FIELD_combined1b97e84f_fld70, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld58", FIELD_combined1b97e84f_fld58, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld131ae_slot1", FIELD_combined1b97e84f_fld131ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s3_s3", FIELD_op0_s3_s3, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld49", FIELD_combined1b97e84f_fld49, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld51", FIELD_combined1b97e84f_fld51, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld23", FIELD_combined1b97e84f_fld23, -1, 0, 0, 0, 0, 0, 0 } -}; - -enum xtensa_operand_id { - OPERAND_soffsetx4, - OPERAND_uimm12x8, - OPERAND_simm4, - OPERAND_arr, - OPERAND_ars, - OPERAND__ars_invisible, - OPERAND_art, - OPERAND_ar0, - OPERAND_ar4, - OPERAND_ar8, - OPERAND_ar12, - OPERAND_ars_entry, - OPERAND_immrx4, - OPERAND_lsi4x4, - OPERAND_simm7, - OPERAND_uimm6, - OPERAND_ai4const, - OPERAND_b4const, - OPERAND_b4constu, - OPERAND_uimm8, - OPERAND_uimm8x2, - OPERAND_uimm8x4, - OPERAND_uimm4x16, - OPERAND_simm8, - OPERAND_simm8x256, - OPERAND_simm12b, - OPERAND_msalp32, - OPERAND_op2p1, - OPERAND_label8, - OPERAND_ulabel8, - OPERAND_label12, - OPERAND_soffset, - OPERAND_uimm16x4, - OPERAND_bbi, - OPERAND_sae, - OPERAND_sas, - OPERAND_sargt, - OPERAND_s, - OPERAND_mx, - OPERAND_my, - OPERAND_mw, - OPERAND_mr0, - OPERAND_mr1, - OPERAND_mr2, - OPERAND_mr3, - OPERAND_immt, - OPERAND_imms, - OPERAND_bt, - OPERAND_bs, - OPERAND_br, - OPERAND_bt2, - OPERAND_bs2, - OPERAND_br2, - OPERAND_bt4, - OPERAND_bs4, - OPERAND_br4, - OPERAND_bt8, - OPERAND_bs8, - OPERAND_br8, - OPERAND_bt16, - OPERAND_bs16, - OPERAND_br16, - OPERAND_brall, - OPERAND_tp7, - OPERAND_xt_wbr15_label, - OPERAND_xt_wbr18_label, - OPERAND_ae_samt32, - OPERAND_pr0, - OPERAND_qr0, - OPERAND_mac_qr0, - OPERAND_ae_lsimm16, - OPERAND_ae_lsimm32, - OPERAND_ae_lsimm64, - OPERAND_ae_samt64, - OPERAND_ae_ohba, - OPERAND_ae_ohba2, - OPERAND_pr, - OPERAND_cvt_pr, - OPERAND_qr0_rw, - OPERAND_mac_qr0_rw, - OPERAND_qr1_w, - OPERAND_mac_qr1_w, - OPERAND_ps, - OPERAND_alupppb_ps, - OPERAND_t, - OPERAND_bbi4, - OPERAND_imm12, - OPERAND_imm8, - OPERAND_imm12b, - OPERAND_imm16, - OPERAND_m, - OPERAND_n, - OPERAND_offset, - OPERAND_op0, - OPERAND_op1, - OPERAND_op2, - OPERAND_r, - OPERAND_sa4, - OPERAND_sae4, - OPERAND_sal, - OPERAND_sas4, - OPERAND_sr, - OPERAND_st, - OPERAND_thi3, - OPERAND_imm4, - OPERAND_mn, - OPERAND_i, - OPERAND_imm6lo, - OPERAND_imm6hi, - OPERAND_imm7lo, - OPERAND_imm7hi, - OPERAND_z, - OPERAND_imm6, - OPERAND_imm7, - OPERAND_r3, - OPERAND_rbit2, - OPERAND_rhi, - OPERAND_t3, - OPERAND_tbit2, - OPERAND_tlo, - OPERAND_w, - OPERAND_y, - OPERAND_x, - OPERAND_t2, - OPERAND_s2, - OPERAND_r2, - OPERAND_t4, - OPERAND_s4, - OPERAND_r4, - OPERAND_t8, - OPERAND_s8, - OPERAND_r8, - OPERAND_xt_wbr15_imm, - OPERAND_xt_wbr18_imm, - OPERAND_ae_r3, - OPERAND_ae_s_non_samt, - OPERAND_ae_s3, - OPERAND_ae_r32, - OPERAND_ae_samt_s_t, - OPERAND_ae_r20, - OPERAND_ae_r10, - OPERAND_ae_s20, - OPERAND_ae_fld_ohba, - OPERAND_ae_fld_ohba2, - OPERAND_op0_s3, - OPERAND_ftsf12, - OPERAND_ftsf13, - OPERAND_ftsf14, - OPERAND_ftsf21ae_slot1, - OPERAND_ftsf22ae_slot1, - OPERAND_ftsf23ae_slot1, - OPERAND_ftsf24ae_slot1, - OPERAND_ftsf25ae_slot1, - OPERAND_ftsf26ae_slot1, - OPERAND_ftsf27ae_slot1, - OPERAND_ftsf28ae_slot1, - OPERAND_ftsf29ae_slot1, - OPERAND_ftsf30ae_slot1, - OPERAND_ftsf31ae_slot1, - OPERAND_ftsf32ae_slot1, - OPERAND_ftsf33ae_slot1, - OPERAND_ftsf34ae_slot1, - OPERAND_ftsf35ae_slot1, - OPERAND_ftsf36ae_slot1, - OPERAND_ftsf37ae_slot1, - OPERAND_ftsf38ae_slot1, - OPERAND_ftsf39ae_slot1, - OPERAND_ftsf40ae_slot1, - OPERAND_ftsf41ae_slot1, - OPERAND_ftsf42ae_slot1, - OPERAND_ftsf43ae_slot1, - OPERAND_ftsf44ae_slot1, - OPERAND_ftsf45ae_slot1, - OPERAND_ftsf46ae_slot1, - OPERAND_ftsf47ae_slot1, - OPERAND_ftsf48ae_slot1, - OPERAND_ftsf49ae_slot1, - OPERAND_ftsf50ae_slot1, - OPERAND_ftsf51ae_slot1, - OPERAND_ftsf52ae_slot1, - OPERAND_ftsf53ae_slot1, - OPERAND_ftsf54ae_slot1, - OPERAND_ftsf55ae_slot1, - OPERAND_ftsf56ae_slot1, - OPERAND_ftsf57ae_slot1, - OPERAND_ftsf58ae_slot1, - OPERAND_ftsf59ae_slot1, - OPERAND_ftsf60ae_slot1, - OPERAND_ftsf61ae_slot1, - OPERAND_ftsf63ae_slot1, - OPERAND_ftsf64ae_slot1, - OPERAND_ftsf66ae_slot1, - OPERAND_ftsf67ae_slot1, - OPERAND_ftsf69ae_slot1, - OPERAND_ftsf71ae_slot1, - OPERAND_ftsf72ae_slot1, - OPERAND_ftsf73ae_slot1, - OPERAND_ftsf75ae_slot1, - OPERAND_ftsf76ae_slot1, - OPERAND_ftsf77ae_slot1, - OPERAND_ftsf78ae_slot1, - OPERAND_ftsf79ae_slot1, - OPERAND_ftsf80ae_slot1, - OPERAND_ftsf81ae_slot1, - OPERAND_ftsf82ae_slot1, - OPERAND_ftsf84ae_slot1, - OPERAND_ftsf86ae_slot1, - OPERAND_ftsf87ae_slot1, - OPERAND_ftsf88ae_slot1, - OPERAND_ftsf89ae_slot1, - OPERAND_ftsf90ae_slot1, - OPERAND_ftsf91ae_slot1, - OPERAND_ftsf92ae_slot1, - OPERAND_ftsf94ae_slot1, - OPERAND_ftsf96ae_slot1, - OPERAND_ftsf97ae_slot1, - OPERAND_ftsf98ae_slot1, - OPERAND_ftsf99ae_slot1, - OPERAND_ftsf100ae_slot1, - OPERAND_ftsf101ae_slot1, - OPERAND_ftsf103ae_slot1, - OPERAND_ftsf104ae_slot1, - OPERAND_ftsf105ae_slot1, - OPERAND_ftsf106ae_slot1, - OPERAND_ftsf107ae_slot1, - OPERAND_ftsf108ae_slot1, - OPERAND_ftsf109ae_slot1, - OPERAND_ftsf110ae_slot1, - OPERAND_ftsf111ae_slot1, - OPERAND_ftsf112ae_slot1, - OPERAND_ftsf113ae_slot1, - OPERAND_ftsf114ae_slot1, - OPERAND_ftsf115ae_slot1, - OPERAND_ftsf116ae_slot1, - OPERAND_ftsf118ae_slot1, - OPERAND_ftsf119ae_slot1, - OPERAND_ftsf120ae_slot1, - OPERAND_ftsf122ae_slot1, - OPERAND_ftsf124ae_slot1, - OPERAND_ftsf125ae_slot1, - OPERAND_ftsf126ae_slot1, - OPERAND_ftsf127ae_slot1, - OPERAND_ftsf128ae_slot1, - OPERAND_ftsf129ae_slot1, - OPERAND_ftsf130ae_slot1, - OPERAND_ftsf131ae_slot1, - OPERAND_ftsf132ae_slot1, - OPERAND_ftsf133ae_slot1, - OPERAND_ftsf134ae_slot1, - OPERAND_ftsf135ae_slot1, - OPERAND_ftsf136ae_slot1, - OPERAND_ftsf137ae_slot1, - OPERAND_ftsf138ae_slot1, - OPERAND_ftsf139ae_slot1, - OPERAND_ftsf140ae_slot1, - OPERAND_ftsf141ae_slot1, - OPERAND_ftsf142ae_slot1, - OPERAND_ftsf143ae_slot1, - OPERAND_ftsf144ae_slot1, - OPERAND_ftsf145ae_slot1, - OPERAND_ftsf146ae_slot1, - OPERAND_ftsf147ae_slot1, - OPERAND_ftsf148ae_slot1, - OPERAND_ftsf149ae_slot1, - OPERAND_ftsf150ae_slot1, - OPERAND_ftsf151ae_slot1, - OPERAND_ftsf152ae_slot1, - OPERAND_ftsf153ae_slot1, - OPERAND_ftsf154ae_slot1, - OPERAND_ftsf155ae_slot1, - OPERAND_ftsf156ae_slot1, - OPERAND_ftsf157ae_slot1, - OPERAND_ftsf158ae_slot1, - OPERAND_ftsf159ae_slot1, - OPERAND_ftsf160ae_slot1, - OPERAND_ftsf161ae_slot1, - OPERAND_ftsf162ae_slot1, - OPERAND_ftsf163ae_slot1, - OPERAND_ftsf164ae_slot1, - OPERAND_ftsf165ae_slot1, - OPERAND_ftsf166ae_slot1, - OPERAND_ftsf167ae_slot1, - OPERAND_ftsf168ae_slot1, - OPERAND_ftsf169ae_slot1, - OPERAND_ftsf170ae_slot1, - OPERAND_ftsf171ae_slot1, - OPERAND_ftsf172ae_slot1, - OPERAND_ftsf173ae_slot1, - OPERAND_ftsf174ae_slot1, - OPERAND_ftsf175ae_slot1, - OPERAND_ftsf176ae_slot1, - OPERAND_ftsf177ae_slot1, - OPERAND_ftsf178ae_slot1, - OPERAND_ftsf179ae_slot1, - OPERAND_ftsf180ae_slot1, - OPERAND_ftsf181ae_slot1, - OPERAND_ftsf182ae_slot1, - OPERAND_ftsf183ae_slot1, - OPERAND_ftsf184ae_slot1, - OPERAND_ftsf185ae_slot1, - OPERAND_ftsf186ae_slot1, - OPERAND_ftsf187ae_slot1, - OPERAND_ftsf188ae_slot1, - OPERAND_ftsf189ae_slot1, - OPERAND_ftsf190ae_slot1, - OPERAND_ftsf191ae_slot1, - OPERAND_ftsf192ae_slot1, - OPERAND_ftsf193ae_slot1, - OPERAND_ftsf194ae_slot1, - OPERAND_ftsf195ae_slot1, - OPERAND_ftsf196ae_slot1, - OPERAND_ftsf197ae_slot1, - OPERAND_ftsf198ae_slot1, - OPERAND_ftsf199ae_slot1, - OPERAND_ftsf200ae_slot1, - OPERAND_ftsf201ae_slot1, - OPERAND_ftsf202ae_slot1, - OPERAND_ftsf203ae_slot1, - OPERAND_ftsf204ae_slot1, - OPERAND_ftsf205ae_slot1, - OPERAND_ftsf206ae_slot1, - OPERAND_ftsf207ae_slot1, - OPERAND_ftsf208, - OPERAND_ftsf209ae_slot1, - OPERAND_ftsf210ae_slot1, - OPERAND_ftsf211ae_slot1, - OPERAND_ftsf330ae_slot1, - OPERAND_ftsf332ae_slot1, - OPERAND_ftsf334ae_slot1, - OPERAND_ftsf336ae_slot1, - OPERAND_ftsf337ae_slot1, - OPERAND_ftsf338, - OPERAND_ftsf339ae_slot1, - OPERAND_ftsf340, - OPERAND_ftsf341ae_slot1, - OPERAND_ftsf342ae_slot1, - OPERAND_ftsf343ae_slot1, - OPERAND_ftsf344ae_slot1, - OPERAND_ftsf346ae_slot1, - OPERAND_ftsf347, - OPERAND_ftsf348ae_slot1, - OPERAND_ftsf349ae_slot1, - OPERAND_ftsf350ae_slot1, - OPERAND_op0_s4, - OPERAND_ftsf212ae_slot0, - OPERAND_ftsf213ae_slot0, - OPERAND_ftsf214ae_slot0, - OPERAND_ftsf215ae_slot0, - OPERAND_ftsf216ae_slot0, - OPERAND_ftsf217, - OPERAND_ftsf218ae_slot0, - OPERAND_ftsf219ae_slot0, - OPERAND_ftsf220ae_slot0, - OPERAND_ftsf221ae_slot0, - OPERAND_ftsf222ae_slot0, - OPERAND_ftsf223ae_slot0, - OPERAND_ftsf224ae_slot0, - OPERAND_ftsf225ae_slot0, - OPERAND_ftsf226ae_slot0, - OPERAND_ftsf227ae_slot0, - OPERAND_ftsf228ae_slot0, - OPERAND_ftsf229ae_slot0, - OPERAND_ftsf230ae_slot0, - OPERAND_ftsf231ae_slot0, - OPERAND_ftsf232ae_slot0, - OPERAND_ftsf233ae_slot0, - OPERAND_ftsf234ae_slot0, - OPERAND_ftsf235ae_slot0, - OPERAND_ftsf236ae_slot0, - OPERAND_ftsf237ae_slot0, - OPERAND_ftsf238ae_slot0, - OPERAND_ftsf239ae_slot0, - OPERAND_ftsf240ae_slot0, - OPERAND_ftsf241ae_slot0, - OPERAND_ftsf242ae_slot0, - OPERAND_ftsf243ae_slot0, - OPERAND_ftsf244ae_slot0, - OPERAND_ftsf245ae_slot0, - OPERAND_ftsf246ae_slot0, - OPERAND_ftsf247ae_slot0, - OPERAND_ftsf248ae_slot0, - OPERAND_ftsf249ae_slot0, - OPERAND_ftsf250ae_slot0, - OPERAND_ftsf251ae_slot0, - OPERAND_ftsf252ae_slot0, - OPERAND_ftsf253ae_slot0, - OPERAND_ftsf254ae_slot0, - OPERAND_ftsf255ae_slot0, - OPERAND_ftsf256ae_slot0, - OPERAND_ftsf257ae_slot0, - OPERAND_ftsf258ae_slot0, - OPERAND_ftsf259ae_slot0, - OPERAND_ftsf260ae_slot0, - OPERAND_ftsf261ae_slot0, - OPERAND_ftsf262ae_slot0, - OPERAND_ftsf263ae_slot0, - OPERAND_ftsf264ae_slot0, - OPERAND_ftsf265ae_slot0, - OPERAND_ftsf266ae_slot0, - OPERAND_ftsf267ae_slot0, - OPERAND_ftsf268ae_slot0, - OPERAND_ftsf269ae_slot0, - OPERAND_ftsf270ae_slot0, - OPERAND_ftsf271ae_slot0, - OPERAND_ftsf272ae_slot0, - OPERAND_ftsf273ae_slot0, - OPERAND_ftsf274ae_slot0, - OPERAND_ftsf275ae_slot0, - OPERAND_ftsf276ae_slot0, - OPERAND_ftsf277ae_slot0, - OPERAND_ftsf278ae_slot0, - OPERAND_ftsf279ae_slot0, - OPERAND_ftsf281ae_slot0, - OPERAND_ftsf282ae_slot0, - OPERAND_ftsf283ae_slot0, - OPERAND_ftsf284ae_slot0, - OPERAND_ftsf286ae_slot0, - OPERAND_ftsf288ae_slot0, - OPERAND_ftsf290ae_slot0, - OPERAND_ftsf292ae_slot0, - OPERAND_ftsf293, - OPERAND_ftsf294ae_slot0, - OPERAND_ftsf295ae_slot0, - OPERAND_ftsf296ae_slot0, - OPERAND_ftsf297ae_slot0, - OPERAND_ftsf298ae_slot0, - OPERAND_ftsf299ae_slot0, - OPERAND_ftsf300ae_slot0, - OPERAND_ftsf301ae_slot0, - OPERAND_ftsf302ae_slot0, - OPERAND_ftsf303ae_slot0, - OPERAND_ftsf304ae_slot0, - OPERAND_ftsf306ae_slot0, - OPERAND_ftsf308ae_slot0, - OPERAND_ftsf309ae_slot0, - OPERAND_ftsf310ae_slot0, - OPERAND_ftsf311ae_slot0, - OPERAND_ftsf312ae_slot0, - OPERAND_ftsf313ae_slot0, - OPERAND_ftsf314ae_slot0, - OPERAND_ftsf315ae_slot0, - OPERAND_ftsf316ae_slot0, - OPERAND_ftsf317ae_slot0, - OPERAND_ftsf318ae_slot0, - OPERAND_ftsf319, - OPERAND_ftsf320ae_slot0, - OPERAND_ftsf321, - OPERAND_ftsf322ae_slot0, - OPERAND_ftsf323ae_slot0, - OPERAND_ftsf324ae_slot0, - OPERAND_ftsf325ae_slot0, - OPERAND_ftsf326ae_slot0, - OPERAND_ftsf328ae_slot0, - OPERAND_ftsf329ae_slot0, - OPERAND_ftsf352ae_slot0, - OPERAND_ftsf353, - OPERAND_ftsf354ae_slot0, - OPERAND_ftsf356ae_slot0, - OPERAND_ftsf357, - OPERAND_ftsf358ae_slot0, - OPERAND_ftsf359ae_slot0, - OPERAND_ftsf360ae_slot0, - OPERAND_ftsf361ae_slot0, - OPERAND_ftsf362ae_slot0, - OPERAND_ftsf364ae_slot0, - OPERAND_ftsf365ae_slot0, - OPERAND_ftsf366ae_slot0, - OPERAND_ftsf368ae_slot0, - OPERAND_ftsf369ae_slot0, - OPERAND_ae_mul32x24fld, - OPERAND_combined1b97e84f_fld115, - OPERAND_combined1b97e84f_fld97, - OPERAND_combined1b97e84f_fld124, - OPERAND_combined1b97e84f_fld79, - OPERAND_combined1b97e84f_fld80, - OPERAND_combined1b97e84f_fld108, - OPERAND_combined1b97e84f_fld101, - OPERAND_combined1b97e84f_fld88, - OPERAND_combined1b97e84f_fld39, - OPERAND_op0_s4_s4, - OPERAND_combined1b97e84f_fld83, - OPERAND_combined1b97e84f_fld90, - OPERAND_combined1b97e84f_fld93, - OPERAND_combined1b97e84f_fld138ae_slot0, - OPERAND_combined1b97e84f_fld130ae_slot0, - OPERAND_combined1b97e84f_fld137ae_slot0, - OPERAND_combined1b97e84f_fld135ae_slot0, - OPERAND_combined1b97e84f_fld136ae_slot0, - OPERAND_combined1b97e84f_fld129ae_slot0, - OPERAND_combined1b97e84f_fld127ae_slot0, - OPERAND_combined1b97e84f_fld128ae_slot0, - OPERAND_combined1b97e84f_fld132ae_slot0, - OPERAND_combined1b97e84f_fld134ae_slot0, - OPERAND_combined4b12daa6_fld122, - OPERAND_combined4b12daa6_fld115, - OPERAND_combined4b12daa6_fld85, - OPERAND_combined4b12daa6_fld119, - OPERAND_combined4b12daa6_fld97, - OPERAND_combined4b12daa6_fld124, - OPERAND_combined4b12daa6_fld79, - OPERAND_combined4b12daa6_fld80, - OPERAND_combined4b12daa6_fld108, - OPERAND_combined1b97e84f_fld54, - OPERAND_combined1b97e84f_fld17, - OPERAND_combined1b97e84f_fld76, - OPERAND_combined1b97e84f_fld73, - OPERAND_combined1b97e84f_fld62, - OPERAND_combined1b97e84f_fld24, - OPERAND_combined1b97e84f_fld70, - OPERAND_combined1b97e84f_fld58, - OPERAND_combined1b97e84f_fld131ae_slot1, - OPERAND_op0_s3_s3, - OPERAND_combined1b97e84f_fld49, - OPERAND_combined1b97e84f_fld51, - OPERAND_combined1b97e84f_fld23 -}; - - -/* Iclass table. */ - -static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { - { { STATE_PSEXCM }, 'o' }, - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { - { { OPERAND_ars_entry }, 's' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm12x8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { - { { STATE_WindowBase }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { - { { OPERAND_simm4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { - { { STATE_EPC1 }, 'i' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSOWB }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ai4const }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_simm7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_threadptr_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_threadptr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8x256 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4const }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_bbi }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4constu }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_label12 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sae }, 'i' }, - { { OPERAND_op2p1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { - { { OPERAND_soffset }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_uimm16x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ulabel8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ulabel8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_simm12b }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { - { { OPERAND_arr }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { - { { OPERAND_sas }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_msalp32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sargt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { - { { STATE_LEND }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { - { { STATE_LEND }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { - { { STATE_LEND }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { - { { STATE_LCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { - { { STATE_SAR }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { - { { STATE_SAR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_243_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'm' }, - { { STATE_PSCALLINC }, 'm' }, - { { STATE_PSOWB }, 'm' }, - { { STATE_PSUM }, 'm' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'i' }, - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_mul16_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_mul32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_mul32h_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { - { { OPERAND_mw }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_mx }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { - { { OPERAND_mw }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_mx }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { - { { OPERAND_mw }, 'o' }, - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPC1 }, 'i' }, - { { STATE_EPC2 }, 'i' }, - { { STATE_EPC3 }, 'i' }, - { { STATE_EPC4 }, 'i' }, - { { STATE_EPC5 }, 'i' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_EPC7 }, 'i' }, - { { STATE_EPS2 }, 'i' }, - { { STATE_EPS3 }, 'i' }, - { { STATE_EPS4 }, 'i' }, - { { STATE_EPS5 }, 'i' }, - { { STATE_EPS6 }, 'i' }, - { { STATE_EPS7 }, 'i' }, - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { - { { STATE_INTERRUPT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { - { { OPERAND_imms }, 'i' }, - { { OPERAND_immt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'i' }, - { { STATE_DBNUM }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'o' }, - { { STATE_DBNUM }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'm' }, - { { STATE_DBNUM }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { - { { STATE_ICOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { - { { STATE_DDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { - { { STATE_InOCDMode }, 'm' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_bs }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_bs4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_bs8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { - { { OPERAND_bs }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { - { { OPERAND_arr }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_brall }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_brall }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_brall }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { - { { STATE_CCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_stateArgs[] = { - { { STATE_PREFCTL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_stateArgs[] = { - { { STATE_PREFCTL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_stateArgs[] = { - { { STATE_PREFCTL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { - { { STATE_CPENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { - { { STATE_CPENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_tp7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_tp7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' }, - { { STATE_XTSYNC }, 'i' }, - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'i' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'o' }, - { { STATE_AE_SAR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = { - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = { - { { STATE_AE_BITHEAD }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_TABLESIZE }, 'i' }, - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = { - { { STATE_AE_BITPTR }, 'o' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_sd_no_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_sd_no_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_sd_no_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_sd_no_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_stateArgs[] = { - { { STATE_AE_SAR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_stateArgs[] = { - { { STATE_AE_BITPTR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_stateArgs[] = { - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_stateArgs[] = { - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_stateArgs[] = { - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_stateArgs[] = { - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_i_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_x_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zerop48_args[] = { - { { OPERAND_ps }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zerop48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp48_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp48_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp16_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp16_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zeroq56_args[] = { - { { OPERAND_qr1_w }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zeroq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtq56_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bs }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfq56_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bs }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_cvt_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_cvt_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_satq48s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_satq48s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncq32_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncq32_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = { - { { OPERAND_alupppb_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = { - { { OPERAND_alupppb_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltp24s_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lep24s_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lep24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqp24_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bt }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bt }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_slliq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_slliq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srliq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srliq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraiq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraiq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltq56s_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_leq56s_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_leq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqq56_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sha32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl32t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl32t_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16t_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16c_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16c_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldsht_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldsht_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lb_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ae_ohba2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbk_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_ohba2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_db_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_db_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_dbi_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_ohba }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_dbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel32t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel32t_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel16t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel16t_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sb_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sb_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbi_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_ae_ohba }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vles16c_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vles16c_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbf_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbf_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_ADDBRBA32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cbegin0_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cbegin0_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cbegin0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cbegin0_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cend0_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cend0_stateArgs[] = { - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cend0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cend0_stateArgs[] = { - { { STATE_AE_CEND0 }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ56_C_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ56_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_iclass_internal iclasses[] = { - { 0, 0 /* xt_iclass_excw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_rfe */, - 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfde */, - 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_syscall */, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call12_args, - 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call8_args, - 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call4_args, - 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx12_args, - 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx8_args, - 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx4_args, - 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_entry_args, - 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movsp_args, - 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rotw_args, - 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_retw_args, - 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfwou */, - 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_l32e_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32e_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowbase_args, - 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowbase_args, - 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowbase_args, - 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowstart_args, - 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowstart_args, - 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowstart_args, - 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_add_n_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addi_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bz6_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill_n */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_loadi4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_mov_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_movi_n_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nopn */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_retn_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_storei4_args, - 0, 0, 0, 0 }, - { 1, Iclass_rur_threadptr_args, - 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, - { 1, Iclass_wur_threadptr_args, - 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_addi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addmi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addsub_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bit_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8b_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8u_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bst8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bsz12_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_callx0_args, - 0, 0, 0, 0 }, - { 4, Iclass_xt_iclass_exti_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jump_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jumpx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16ui_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16si_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_l32r_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l8i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_loop_args, - 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_loopz_args, - 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_movz_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_neg_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nop */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_return_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_simcall */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s16i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s8i_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_sar_args, - 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_sari_args, - 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shifts_args, - 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_shiftst_args, - 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shiftt_args, - 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_slli_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srli_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_memw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_extw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_isync */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_sync */, - 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rsil_args, - 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lend_args, - 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lend_args, - 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lend_args, - 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lcount_args, - 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lcount_args, - 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lcount_args, - 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lbeg_args, - 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lbeg_args, - 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lbeg_args, - 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_sar_args, - 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_sar_args, - 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_sar_args, - 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_configid0_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_configid0_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_configid1_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_243_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ps_args, - 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ps_args, - 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ps_args, - 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc1_args, - 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc1_args, - 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc1_args, - 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave1_args, - 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave1_args, - 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave1_args, - 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc2_args, - 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc2_args, - 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc2_args, - 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave2_args, - 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave2_args, - 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave2_args, - 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc3_args, - 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc3_args, - 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc3_args, - 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave3_args, - 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave3_args, - 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave3_args, - 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc4_args, - 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc4_args, - 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc4_args, - 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave4_args, - 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave4_args, - 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave4_args, - 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc5_args, - 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc5_args, - 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc5_args, - 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave5_args, - 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave5_args, - 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave5_args, - 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc6_args, - 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc6_args, - 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc6_args, - 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave6_args, - 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave6_args, - 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave6_args, - 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc7_args, - 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc7_args, - 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc7_args, - 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave7_args, - 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave7_args, - 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave7_args, - 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps2_args, - 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps2_args, - 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps2_args, - 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps3_args, - 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps3_args, - 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps3_args, - 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps4_args, - 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps4_args, - 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps4_args, - 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps5_args, - 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps5_args, - 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps5_args, - 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps6_args, - 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps6_args, - 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps6_args, - 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps7_args, - 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps7_args, - 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps7_args, - 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excvaddr_args, - 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excvaddr_args, - 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excvaddr_args, - 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_depc_args, - 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_depc_args, - 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_depc_args, - 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_exccause_args, - 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_exccause_args, - 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_exccause_args, - 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_prid_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_vecbase_args, - 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_vecbase_args, - 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_vecbase_args, - 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, - { 3, Iclass_xt_mul16_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_mul32_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_mul32h_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_aa_args, - 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_ad_args, - 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_da_args, - 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_dd_args, - 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_aa_args, - 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_ad_args, - 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_da_args, - 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_dd_args, - 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, - { 4, Iclass_xt_iclass_mac16al_da_args, - 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, - { 4, Iclass_xt_iclass_mac16al_dd_args, - 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_l_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m3_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m3_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m3_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_acclo_args, - 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acclo_args, - 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acclo_args, - 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_acchi_args, - 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acchi_args, - 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acchi_args, - 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfi_args, - 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wait_args, - 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_interrupt_args, - 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intset_args, - 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intclear_args, - 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_intenable_args, - 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intenable_args, - 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_intenable_args, - 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_break_args, - 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_break_n_args, - 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka0_args, - 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka0_args, - 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka0_args, - 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc0_args, - 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc0_args, - 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc0_args, - 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka1_args, - 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka1_args, - 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka1_args, - 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc1_args, - 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc1_args, - 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc1_args, - 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka0_args, - 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka0_args, - 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka0_args, - 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka1_args, - 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka1_args, - 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka1_args, - 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreakenable_args, - 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreakenable_args, - 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreakenable_args, - 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_debugcause_args, - 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_debugcause_args, - 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_debugcause_args, - 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icount_args, - 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icount_args, - 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icount_args, - 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icountlevel_args, - 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icountlevel_args, - 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icountlevel_args, - 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ddr_args, - 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ddr_args, - 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ddr_args, - 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfdo_args, - 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfdd */, - 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_bbool1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbool4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbool8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbranch_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bmove_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_RSR_BR_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_WSR_BR_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_XSR_BR_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccount_args, - 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccount_args, - 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccount_args, - 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare0_args, - 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare0_args, - 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare0_args, - 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare1_args, - 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare1_args, - 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare1_args, - 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare2_args, - 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare2_args, - 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare2_args, - 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_icache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_icache_lock_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_icache_inv_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_licx_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_sicx_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_ind_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_inv_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dpf_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_lock_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_sdct_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_ldct_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_prefctl_args, - 1, Iclass_xt_iclass_rsr_prefctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_prefctl_args, - 1, Iclass_xt_iclass_wsr_prefctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_prefctl_args, - 1, Iclass_xt_iclass_xsr_prefctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_idtlb_args, - 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rdtlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wdtlb_args, - 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_iitlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_ritlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_witlb_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_cpenable_args, - 1, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_cpenable_args, - 1, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_cpenable_args, - 1, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_clamp_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_minmax_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_nsa_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_sx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32ai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32ri_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32c1i_args, - 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_scompare1_args, - 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_scompare1_args, - 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_scompare1_args, - 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_atomctl_args, - 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_atomctl_args, - 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_atomctl_args, - 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rer */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_wer */, - 0, 0, 0, 0 }, - { 1, Iclass_rur_ae_ovf_sar_args, - 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_ovf_sar_args, - 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_bithead_args, - 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_bithead_args, - 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_ts_fts_bu_bp_args, - 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_ts_fts_bu_bp_args, - 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_sd_no_args, - 3, Iclass_rur_ae_sd_no_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_sd_no_args, - 3, Iclass_wur_ae_sd_no_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_overflow_args, - 2, Iclass_ae_iclass_rur_ae_overflow_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_overflow_args, - 2, Iclass_ae_iclass_wur_ae_overflow_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_sar_args, - 2, Iclass_ae_iclass_rur_ae_sar_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_sar_args, - 2, Iclass_ae_iclass_wur_ae_sar_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_bitptr_args, - 2, Iclass_ae_iclass_rur_ae_bitptr_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_bitptr_args, - 2, Iclass_ae_iclass_wur_ae_bitptr_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_bitsused_args, - 2, Iclass_ae_iclass_rur_ae_bitsused_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_bitsused_args, - 2, Iclass_ae_iclass_wur_ae_bitsused_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_tablesize_args, - 2, Iclass_ae_iclass_rur_ae_tablesize_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_tablesize_args, - 2, Iclass_ae_iclass_wur_ae_tablesize_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_first_ts_args, - 2, Iclass_ae_iclass_rur_ae_first_ts_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_first_ts_args, - 2, Iclass_ae_iclass_wur_ae_first_ts_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_nextoffset_args, - 2, Iclass_ae_iclass_rur_ae_nextoffset_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_nextoffset_args, - 2, Iclass_ae_iclass_wur_ae_nextoffset_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_searchdone_args, - 2, Iclass_ae_iclass_rur_ae_searchdone_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_searchdone_args, - 2, Iclass_ae_iclass_wur_ae_searchdone_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_i_args, - 1, Iclass_ae_iclass_lp16f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_iu_args, - 1, Iclass_ae_iclass_lp16f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_x_args, - 1, Iclass_ae_iclass_lp16f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_xu_args, - 1, Iclass_ae_iclass_lp16f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_i_args, - 1, Iclass_ae_iclass_lp24_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_iu_args, - 1, Iclass_ae_iclass_lp24_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_x_args, - 1, Iclass_ae_iclass_lp24_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_xu_args, - 1, Iclass_ae_iclass_lp24_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_i_args, - 1, Iclass_ae_iclass_lp24f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_iu_args, - 1, Iclass_ae_iclass_lp24f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_x_args, - 1, Iclass_ae_iclass_lp24f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_xu_args, - 1, Iclass_ae_iclass_lp24f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_i_args, - 1, Iclass_ae_iclass_lp16x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_iu_args, - 1, Iclass_ae_iclass_lp16x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_x_args, - 1, Iclass_ae_iclass_lp16x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_xu_args, - 1, Iclass_ae_iclass_lp16x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_i_args, - 1, Iclass_ae_iclass_lp24x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_iu_args, - 1, Iclass_ae_iclass_lp24x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_x_args, - 1, Iclass_ae_iclass_lp24x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_xu_args, - 1, Iclass_ae_iclass_lp24x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_i_args, - 1, Iclass_ae_iclass_lp24x2_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_iu_args, - 1, Iclass_ae_iclass_lp24x2_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_x_args, - 1, Iclass_ae_iclass_lp24x2_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_xu_args, - 1, Iclass_ae_iclass_lp24x2_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_i_args, - 1, Iclass_ae_iclass_sp16x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_iu_args, - 1, Iclass_ae_iclass_sp16x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_x_args, - 1, Iclass_ae_iclass_sp16x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_xu_args, - 1, Iclass_ae_iclass_sp16x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_i_args, - 1, Iclass_ae_iclass_sp24x2s_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_iu_args, - 1, Iclass_ae_iclass_sp24x2s_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_x_args, - 1, Iclass_ae_iclass_sp24x2s_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_xu_args, - 1, Iclass_ae_iclass_sp24x2s_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_i_args, - 1, Iclass_ae_iclass_sp24x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_iu_args, - 1, Iclass_ae_iclass_sp24x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_x_args, - 1, Iclass_ae_iclass_sp24x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_xu_args, - 1, Iclass_ae_iclass_sp24x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_i_args, - 1, Iclass_ae_iclass_sp16f_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_iu_args, - 1, Iclass_ae_iclass_sp16f_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_x_args, - 1, Iclass_ae_iclass_sp16f_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_xu_args, - 1, Iclass_ae_iclass_sp16f_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_i_args, - 1, Iclass_ae_iclass_sp24s_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_iu_args, - 1, Iclass_ae_iclass_sp24s_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_x_args, - 1, Iclass_ae_iclass_sp24s_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_xu_args, - 1, Iclass_ae_iclass_sp24s_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_i_args, - 1, Iclass_ae_iclass_sp24f_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_iu_args, - 1, Iclass_ae_iclass_sp24f_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_x_args, - 1, Iclass_ae_iclass_sp24f_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_xu_args, - 1, Iclass_ae_iclass_sp24f_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_i_args, - 1, Iclass_ae_iclass_lq56_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_iu_args, - 1, Iclass_ae_iclass_lq56_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_x_args, - 1, Iclass_ae_iclass_lq56_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_xu_args, - 1, Iclass_ae_iclass_lq56_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_i_args, - 1, Iclass_ae_iclass_lq32f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_iu_args, - 1, Iclass_ae_iclass_lq32f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_x_args, - 1, Iclass_ae_iclass_lq32f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_xu_args, - 1, Iclass_ae_iclass_lq32f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_i_args, - 1, Iclass_ae_iclass_sq56s_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_iu_args, - 1, Iclass_ae_iclass_sq56s_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_x_args, - 1, Iclass_ae_iclass_sq56s_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_xu_args, - 1, Iclass_ae_iclass_sq56s_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_i_args, - 1, Iclass_ae_iclass_sq32f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_iu_args, - 1, Iclass_ae_iclass_sq32f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_x_args, - 1, Iclass_ae_iclass_sq32f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_xu_args, - 1, Iclass_ae_iclass_sq32f_xu_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_zerop48_args, - 1, Iclass_ae_iclass_zerop48_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movp48_args, - 1, Iclass_ae_iclass_movp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_ll_args, - 1, Iclass_ae_iclass_selp24_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_lh_args, - 1, Iclass_ae_iclass_selp24_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_hl_args, - 1, Iclass_ae_iclass_selp24_hl_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_hh_args, - 1, Iclass_ae_iclass_selp24_hh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movtp24x2_args, - 1, Iclass_ae_iclass_movtp24x2_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movfp24x2_args, - 1, Iclass_ae_iclass_movfp24x2_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movtp48_args, - 1, Iclass_ae_iclass_movtp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movfp48_args, - 1, Iclass_ae_iclass_movfp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movpa24x2_args, - 1, Iclass_ae_iclass_movpa24x2_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_truncp24a32x2_args, - 1, Iclass_ae_iclass_truncp24a32x2_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvta32p24_l_args, - 1, Iclass_ae_iclass_cvta32p24_l_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvta32p24_h_args, - 1, Iclass_ae_iclass_cvta32p24_h_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_ll_args, - 1, Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_lh_args, - 1, Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_hl_args, - 1, Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_hh_args, - 1, Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_truncp24q48x2_args, - 1, Iclass_ae_iclass_truncp24q48x2_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_truncp16_args, - 1, Iclass_ae_iclass_truncp16_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp24q48sym_args, - 2, Iclass_ae_iclass_roundsp24q48sym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp24q48asym_args, - 2, Iclass_ae_iclass_roundsp24q48asym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp16q48sym_args, - 2, Iclass_ae_iclass_roundsp16q48sym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp16q48asym_args, - 2, Iclass_ae_iclass_roundsp16q48asym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp16sym_args, - 2, Iclass_ae_iclass_roundsp16sym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp16asym_args, - 2, Iclass_ae_iclass_roundsp16asym_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_zeroq56_args, - 1, Iclass_ae_iclass_zeroq56_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movq56_args, - 1, Iclass_ae_iclass_movq56_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movtq56_args, - 1, Iclass_ae_iclass_movtq56_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movfq56_args, - 1, Iclass_ae_iclass_movfq56_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvtq48a32s_args, - 1, Iclass_ae_iclass_cvtq48a32s_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvtq48p24s_l_args, - 1, Iclass_ae_iclass_cvtq48p24s_l_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvtq48p24s_h_args, - 1, Iclass_ae_iclass_cvtq48p24s_h_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_satq48s_args, - 2, Iclass_ae_iclass_satq48s_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_truncq32_args, - 1, Iclass_ae_iclass_truncq32_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsq32sym_args, - 2, Iclass_ae_iclass_roundsq32sym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsq32asym_args, - 2, Iclass_ae_iclass_roundsq32asym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_trunca32q48_args, - 1, Iclass_ae_iclass_trunca32q48_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movap24s_l_args, - 1, Iclass_ae_iclass_movap24s_l_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movap24s_h_args, - 1, Iclass_ae_iclass_movap24s_h_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_trunca16p24s_l_args, - 1, Iclass_ae_iclass_trunca16p24s_l_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_trunca16p24s_h_args, - 1, Iclass_ae_iclass_trunca16p24s_h_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_addp24_args, - 1, Iclass_ae_iclass_addp24_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_subp24_args, - 1, Iclass_ae_iclass_subp24_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_negp24_args, - 1, Iclass_ae_iclass_negp24_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_absp24_args, - 1, Iclass_ae_iclass_absp24_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_maxp24s_args, - 1, Iclass_ae_iclass_maxp24s_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_minp24s_args, - 1, Iclass_ae_iclass_minp24s_stateArgs, 0, 0 }, - { 4, Iclass_ae_iclass_maxbp24s_args, - 1, Iclass_ae_iclass_maxbp24s_stateArgs, 0, 0 }, - { 4, Iclass_ae_iclass_minbp24s_args, - 1, Iclass_ae_iclass_minbp24s_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_addsp24s_args, - 2, Iclass_ae_iclass_addsp24s_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_subsp24s_args, - 2, Iclass_ae_iclass_subsp24s_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_negsp24s_args, - 2, Iclass_ae_iclass_negsp24s_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_abssp24s_args, - 2, Iclass_ae_iclass_abssp24s_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_andp48_args, - 1, Iclass_ae_iclass_andp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_nandp48_args, - 1, Iclass_ae_iclass_nandp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_orp48_args, - 1, Iclass_ae_iclass_orp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_xorp48_args, - 1, Iclass_ae_iclass_xorp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_ltp24s_args, - 1, Iclass_ae_iclass_ltp24s_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lep24s_args, - 1, Iclass_ae_iclass_lep24s_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_eqp24_args, - 1, Iclass_ae_iclass_eqp24_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_addq56_args, - 1, Iclass_ae_iclass_addq56_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_subq56_args, - 1, Iclass_ae_iclass_subq56_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_negq56_args, - 1, Iclass_ae_iclass_negq56_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_absq56_args, - 1, Iclass_ae_iclass_absq56_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_maxq56s_args, - 1, Iclass_ae_iclass_maxq56s_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_minq56s_args, - 1, Iclass_ae_iclass_minq56s_stateArgs, 0, 0 }, - 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1, Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16s_ll_args, - 1, Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16s_ll_args, - 1, Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16u_ll_args, - 1, Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16u_ll_args, - 1, Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzaafp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzaap24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzaafp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzaap24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzasfp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzasp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzasfp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzasp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzsafp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzsap24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzsafp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzsap24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzssfp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzssp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzssfp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzssp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulaafp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulaap24s_hh_ll_args, - 1, Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulaafp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulaap24s_hl_lh_args, - 1, Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulasfp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulasp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulasfp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulasp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulsafp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulsap24s_hh_ll_args, - 1, Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulsafp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulsap24s_hl_lh_args, - 1, Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulssfp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulssp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulssfp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulssp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_sha32_args, - 0, 0, 0, 0 }, - { 3, Iclass_ae_iclass_vldl32t_args, - 5, Iclass_ae_iclass_vldl32t_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_vldl16t_args, - 5, Iclass_ae_iclass_vldl16t_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_vldl16c_args, - 8, Iclass_ae_iclass_vldl16c_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_vldsht_args, - 6, Iclass_ae_iclass_vldsht_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_lb_args, - 3, Iclass_ae_iclass_lb_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_lbi_args, - 3, Iclass_ae_iclass_lbi_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lbk_args, - 3, Iclass_ae_iclass_lbk_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lbki_args, - 3, Iclass_ae_iclass_lbki_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_db_args, - 3, Iclass_ae_iclass_db_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_dbi_args, - 3, Iclass_ae_iclass_dbi_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_vlel32t_args, - 3, Iclass_ae_iclass_vlel32t_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_vlel16t_args, - 3, Iclass_ae_iclass_vlel16t_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_sb_args, - 4, Iclass_ae_iclass_sb_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sbi_args, - 3, Iclass_ae_iclass_sbi_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_vles16c_args, - 5, Iclass_ae_iclass_vles16c_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_sbf_args, - 3, Iclass_ae_iclass_sbf_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SLAASQ56S_args, - 2, Iclass_icls_AE_SLAASQ56S_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_ADDBRBA32_args, - 0, 0, 0, 0 }, - { 3, Iclass_icls_AE_MINABSSP24S_args, - 2, Iclass_icls_AE_MINABSSP24S_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_MAXABSSP24S_args, - 2, Iclass_icls_AE_MAXABSSP24S_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_MINABSSQ56S_args, - 2, Iclass_icls_AE_MINABSSQ56S_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_MAXABSSQ56S_args, - 2, Iclass_icls_AE_MAXABSSQ56S_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_cbegin0_args, - 2, Iclass_rur_ae_cbegin0_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_cbegin0_args, - 2, Iclass_wur_ae_cbegin0_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_cend0_args, - 2, Iclass_rur_ae_cend0_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_cend0_args, - 2, Iclass_wur_ae_cend0_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP24X2_C_args, - 3, Iclass_icls_AE_LP24X2_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP24X2S_C_args, - 3, Iclass_icls_AE_SP24X2S_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP24X2F_C_args, - 3, Iclass_icls_AE_LP24X2F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP24X2F_C_args, - 3, Iclass_icls_AE_SP24X2F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP16X2F_C_args, - 3, Iclass_icls_AE_LP16X2F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP16X2F_C_args, - 3, Iclass_icls_AE_SP16X2F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP24_C_args, - 3, Iclass_icls_AE_LP24_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP24S_L_C_args, - 3, Iclass_icls_AE_SP24S_L_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP24F_C_args, - 3, Iclass_icls_AE_LP24F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP24F_L_C_args, - 3, Iclass_icls_AE_SP24F_L_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP16F_C_args, - 3, Iclass_icls_AE_LP16F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP16F_L_C_args, - 3, Iclass_icls_AE_SP16F_L_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LQ56_C_args, - 3, Iclass_icls_AE_LQ56_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SQ56S_C_args, - 3, Iclass_icls_AE_SQ56S_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LQ32F_C_args, - 3, Iclass_icls_AE_LQ32F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SQ32F_C_args, - 3, Iclass_icls_AE_SQ32F_C_stateArgs, 0, 0 } -}; - -enum xtensa_iclass_id { - ICLASS_xt_iclass_excw, - ICLASS_xt_iclass_rfe, - ICLASS_xt_iclass_rfde, - ICLASS_xt_iclass_syscall, - ICLASS_xt_iclass_call12, - ICLASS_xt_iclass_call8, - ICLASS_xt_iclass_call4, - ICLASS_xt_iclass_callx12, - ICLASS_xt_iclass_callx8, - ICLASS_xt_iclass_callx4, - ICLASS_xt_iclass_entry, - ICLASS_xt_iclass_movsp, - ICLASS_xt_iclass_rotw, - ICLASS_xt_iclass_retw, - ICLASS_xt_iclass_rfwou, - ICLASS_xt_iclass_l32e, - ICLASS_xt_iclass_s32e, - ICLASS_xt_iclass_rsr_windowbase, - ICLASS_xt_iclass_wsr_windowbase, - ICLASS_xt_iclass_xsr_windowbase, - ICLASS_xt_iclass_rsr_windowstart, - ICLASS_xt_iclass_wsr_windowstart, - ICLASS_xt_iclass_xsr_windowstart, - ICLASS_xt_iclass_add_n, - ICLASS_xt_iclass_addi_n, - ICLASS_xt_iclass_bz6, - ICLASS_xt_iclass_ill_n, - ICLASS_xt_iclass_loadi4, - ICLASS_xt_iclass_mov_n, - ICLASS_xt_iclass_movi_n, - ICLASS_xt_iclass_nopn, - ICLASS_xt_iclass_retn, - ICLASS_xt_iclass_storei4, - ICLASS_rur_threadptr, - ICLASS_wur_threadptr, - ICLASS_xt_iclass_addi, - ICLASS_xt_iclass_addmi, - ICLASS_xt_iclass_addsub, - ICLASS_xt_iclass_bit, - ICLASS_xt_iclass_bsi8, - ICLASS_xt_iclass_bsi8b, - ICLASS_xt_iclass_bsi8u, - ICLASS_xt_iclass_bst8, - ICLASS_xt_iclass_bsz12, - ICLASS_xt_iclass_call0, - ICLASS_xt_iclass_callx0, - ICLASS_xt_iclass_exti, - ICLASS_xt_iclass_ill, - ICLASS_xt_iclass_jump, - ICLASS_xt_iclass_jumpx, - ICLASS_xt_iclass_l16ui, - ICLASS_xt_iclass_l16si, - ICLASS_xt_iclass_l32i, - ICLASS_xt_iclass_l32r, - ICLASS_xt_iclass_l8i, - ICLASS_xt_iclass_loop, - ICLASS_xt_iclass_loopz, - ICLASS_xt_iclass_movi, - ICLASS_xt_iclass_movz, - ICLASS_xt_iclass_neg, - ICLASS_xt_iclass_nop, - ICLASS_xt_iclass_return, - ICLASS_xt_iclass_simcall, - ICLASS_xt_iclass_s16i, - ICLASS_xt_iclass_s32i, - ICLASS_xt_iclass_s8i, - ICLASS_xt_iclass_sar, - ICLASS_xt_iclass_sari, - ICLASS_xt_iclass_shifts, - ICLASS_xt_iclass_shiftst, - ICLASS_xt_iclass_shiftt, - ICLASS_xt_iclass_slli, - ICLASS_xt_iclass_srai, - ICLASS_xt_iclass_srli, - ICLASS_xt_iclass_memw, - ICLASS_xt_iclass_extw, - ICLASS_xt_iclass_isync, - ICLASS_xt_iclass_sync, - ICLASS_xt_iclass_rsil, - ICLASS_xt_iclass_rsr_lend, - ICLASS_xt_iclass_wsr_lend, - ICLASS_xt_iclass_xsr_lend, - ICLASS_xt_iclass_rsr_lcount, - ICLASS_xt_iclass_wsr_lcount, - ICLASS_xt_iclass_xsr_lcount, - ICLASS_xt_iclass_rsr_lbeg, - ICLASS_xt_iclass_wsr_lbeg, - ICLASS_xt_iclass_xsr_lbeg, - ICLASS_xt_iclass_rsr_sar, - ICLASS_xt_iclass_wsr_sar, - ICLASS_xt_iclass_xsr_sar, - ICLASS_xt_iclass_rsr_litbase, - ICLASS_xt_iclass_wsr_litbase, - ICLASS_xt_iclass_xsr_litbase, - ICLASS_xt_iclass_rsr_configid0, - ICLASS_xt_iclass_wsr_configid0, - ICLASS_xt_iclass_rsr_configid1, - ICLASS_xt_iclass_rsr_243, - ICLASS_xt_iclass_rsr_ps, - ICLASS_xt_iclass_wsr_ps, - ICLASS_xt_iclass_xsr_ps, - ICLASS_xt_iclass_rsr_epc1, - ICLASS_xt_iclass_wsr_epc1, - ICLASS_xt_iclass_xsr_epc1, - ICLASS_xt_iclass_rsr_excsave1, - ICLASS_xt_iclass_wsr_excsave1, - ICLASS_xt_iclass_xsr_excsave1, - ICLASS_xt_iclass_rsr_epc2, - ICLASS_xt_iclass_wsr_epc2, - ICLASS_xt_iclass_xsr_epc2, - ICLASS_xt_iclass_rsr_excsave2, - ICLASS_xt_iclass_wsr_excsave2, - ICLASS_xt_iclass_xsr_excsave2, - ICLASS_xt_iclass_rsr_epc3, - ICLASS_xt_iclass_wsr_epc3, - ICLASS_xt_iclass_xsr_epc3, - ICLASS_xt_iclass_rsr_excsave3, - ICLASS_xt_iclass_wsr_excsave3, - ICLASS_xt_iclass_xsr_excsave3, - ICLASS_xt_iclass_rsr_epc4, - ICLASS_xt_iclass_wsr_epc4, - ICLASS_xt_iclass_xsr_epc4, - ICLASS_xt_iclass_rsr_excsave4, - ICLASS_xt_iclass_wsr_excsave4, - ICLASS_xt_iclass_xsr_excsave4, - ICLASS_xt_iclass_rsr_epc5, - ICLASS_xt_iclass_wsr_epc5, - ICLASS_xt_iclass_xsr_epc5, - ICLASS_xt_iclass_rsr_excsave5, - ICLASS_xt_iclass_wsr_excsave5, - ICLASS_xt_iclass_xsr_excsave5, - ICLASS_xt_iclass_rsr_epc6, - ICLASS_xt_iclass_wsr_epc6, - ICLASS_xt_iclass_xsr_epc6, - ICLASS_xt_iclass_rsr_excsave6, - ICLASS_xt_iclass_wsr_excsave6, - ICLASS_xt_iclass_xsr_excsave6, - ICLASS_xt_iclass_rsr_epc7, - ICLASS_xt_iclass_wsr_epc7, - ICLASS_xt_iclass_xsr_epc7, - ICLASS_xt_iclass_rsr_excsave7, - ICLASS_xt_iclass_wsr_excsave7, - ICLASS_xt_iclass_xsr_excsave7, - ICLASS_xt_iclass_rsr_eps2, - ICLASS_xt_iclass_wsr_eps2, - ICLASS_xt_iclass_xsr_eps2, - ICLASS_xt_iclass_rsr_eps3, - ICLASS_xt_iclass_wsr_eps3, - ICLASS_xt_iclass_xsr_eps3, - ICLASS_xt_iclass_rsr_eps4, - ICLASS_xt_iclass_wsr_eps4, - ICLASS_xt_iclass_xsr_eps4, - ICLASS_xt_iclass_rsr_eps5, - ICLASS_xt_iclass_wsr_eps5, - ICLASS_xt_iclass_xsr_eps5, - ICLASS_xt_iclass_rsr_eps6, - ICLASS_xt_iclass_wsr_eps6, - ICLASS_xt_iclass_xsr_eps6, - ICLASS_xt_iclass_rsr_eps7, - ICLASS_xt_iclass_wsr_eps7, - ICLASS_xt_iclass_xsr_eps7, - ICLASS_xt_iclass_rsr_excvaddr, - ICLASS_xt_iclass_wsr_excvaddr, - ICLASS_xt_iclass_xsr_excvaddr, - ICLASS_xt_iclass_rsr_depc, - ICLASS_xt_iclass_wsr_depc, - ICLASS_xt_iclass_xsr_depc, - ICLASS_xt_iclass_rsr_exccause, - ICLASS_xt_iclass_wsr_exccause, - ICLASS_xt_iclass_xsr_exccause, - ICLASS_xt_iclass_rsr_prid, - ICLASS_xt_iclass_rsr_vecbase, - ICLASS_xt_iclass_wsr_vecbase, - ICLASS_xt_iclass_xsr_vecbase, - ICLASS_xt_mul16, - ICLASS_xt_mul32, - ICLASS_xt_mul32h, - ICLASS_xt_iclass_mac16_aa, - ICLASS_xt_iclass_mac16_ad, - ICLASS_xt_iclass_mac16_da, - ICLASS_xt_iclass_mac16_dd, - ICLASS_xt_iclass_mac16a_aa, - ICLASS_xt_iclass_mac16a_ad, - ICLASS_xt_iclass_mac16a_da, - ICLASS_xt_iclass_mac16a_dd, - ICLASS_xt_iclass_mac16al_da, - ICLASS_xt_iclass_mac16al_dd, - ICLASS_xt_iclass_mac16_l, - ICLASS_xt_iclass_rsr_m0, - ICLASS_xt_iclass_wsr_m0, - ICLASS_xt_iclass_xsr_m0, - ICLASS_xt_iclass_rsr_m1, - ICLASS_xt_iclass_wsr_m1, - ICLASS_xt_iclass_xsr_m1, - ICLASS_xt_iclass_rsr_m2, - ICLASS_xt_iclass_wsr_m2, - ICLASS_xt_iclass_xsr_m2, - ICLASS_xt_iclass_rsr_m3, - ICLASS_xt_iclass_wsr_m3, - ICLASS_xt_iclass_xsr_m3, - ICLASS_xt_iclass_rsr_acclo, - ICLASS_xt_iclass_wsr_acclo, - ICLASS_xt_iclass_xsr_acclo, - ICLASS_xt_iclass_rsr_acchi, - ICLASS_xt_iclass_wsr_acchi, - ICLASS_xt_iclass_xsr_acchi, - ICLASS_xt_iclass_rfi, - ICLASS_xt_iclass_wait, - ICLASS_xt_iclass_rsr_interrupt, - ICLASS_xt_iclass_wsr_intset, - ICLASS_xt_iclass_wsr_intclear, - ICLASS_xt_iclass_rsr_intenable, - ICLASS_xt_iclass_wsr_intenable, - ICLASS_xt_iclass_xsr_intenable, - ICLASS_xt_iclass_break, - ICLASS_xt_iclass_break_n, - ICLASS_xt_iclass_rsr_dbreaka0, - ICLASS_xt_iclass_wsr_dbreaka0, - ICLASS_xt_iclass_xsr_dbreaka0, - ICLASS_xt_iclass_rsr_dbreakc0, - ICLASS_xt_iclass_wsr_dbreakc0, - ICLASS_xt_iclass_xsr_dbreakc0, - ICLASS_xt_iclass_rsr_dbreaka1, - ICLASS_xt_iclass_wsr_dbreaka1, - ICLASS_xt_iclass_xsr_dbreaka1, - ICLASS_xt_iclass_rsr_dbreakc1, - ICLASS_xt_iclass_wsr_dbreakc1, - ICLASS_xt_iclass_xsr_dbreakc1, - ICLASS_xt_iclass_rsr_ibreaka0, - ICLASS_xt_iclass_wsr_ibreaka0, - ICLASS_xt_iclass_xsr_ibreaka0, - ICLASS_xt_iclass_rsr_ibreaka1, - ICLASS_xt_iclass_wsr_ibreaka1, - ICLASS_xt_iclass_xsr_ibreaka1, - ICLASS_xt_iclass_rsr_ibreakenable, - ICLASS_xt_iclass_wsr_ibreakenable, - ICLASS_xt_iclass_xsr_ibreakenable, - ICLASS_xt_iclass_rsr_debugcause, - ICLASS_xt_iclass_wsr_debugcause, - ICLASS_xt_iclass_xsr_debugcause, - ICLASS_xt_iclass_rsr_icount, - ICLASS_xt_iclass_wsr_icount, - ICLASS_xt_iclass_xsr_icount, - ICLASS_xt_iclass_rsr_icountlevel, - ICLASS_xt_iclass_wsr_icountlevel, - ICLASS_xt_iclass_xsr_icountlevel, - ICLASS_xt_iclass_rsr_ddr, - ICLASS_xt_iclass_wsr_ddr, - ICLASS_xt_iclass_xsr_ddr, - ICLASS_xt_iclass_rfdo, - ICLASS_xt_iclass_rfdd, - ICLASS_xt_iclass_bbool1, - ICLASS_xt_iclass_bbool4, - ICLASS_xt_iclass_bbool8, - ICLASS_xt_iclass_bbranch, - ICLASS_xt_iclass_bmove, - ICLASS_xt_iclass_RSR_BR, - ICLASS_xt_iclass_WSR_BR, - ICLASS_xt_iclass_XSR_BR, - ICLASS_xt_iclass_rsr_ccount, - ICLASS_xt_iclass_wsr_ccount, - ICLASS_xt_iclass_xsr_ccount, - ICLASS_xt_iclass_rsr_ccompare0, - ICLASS_xt_iclass_wsr_ccompare0, - ICLASS_xt_iclass_xsr_ccompare0, - ICLASS_xt_iclass_rsr_ccompare1, - ICLASS_xt_iclass_wsr_ccompare1, - ICLASS_xt_iclass_xsr_ccompare1, - ICLASS_xt_iclass_rsr_ccompare2, - ICLASS_xt_iclass_wsr_ccompare2, - ICLASS_xt_iclass_xsr_ccompare2, - ICLASS_xt_iclass_icache, - ICLASS_xt_iclass_icache_lock, - ICLASS_xt_iclass_icache_inv, - ICLASS_xt_iclass_licx, - ICLASS_xt_iclass_sicx, - ICLASS_xt_iclass_dcache, - ICLASS_xt_iclass_dcache_ind, - ICLASS_xt_iclass_dcache_inv, - ICLASS_xt_iclass_dpf, - ICLASS_xt_iclass_dcache_lock, - ICLASS_xt_iclass_sdct, - ICLASS_xt_iclass_ldct, - ICLASS_xt_iclass_rsr_prefctl, - ICLASS_xt_iclass_wsr_prefctl, - ICLASS_xt_iclass_xsr_prefctl, - ICLASS_xt_iclass_idtlb, - ICLASS_xt_iclass_rdtlb, - ICLASS_xt_iclass_wdtlb, - ICLASS_xt_iclass_iitlb, - ICLASS_xt_iclass_ritlb, - ICLASS_xt_iclass_witlb, - ICLASS_xt_iclass_rsr_cpenable, - ICLASS_xt_iclass_wsr_cpenable, - ICLASS_xt_iclass_xsr_cpenable, - ICLASS_xt_iclass_clamp, - ICLASS_xt_iclass_minmax, - ICLASS_xt_iclass_nsa, - ICLASS_xt_iclass_sx, - ICLASS_xt_iclass_l32ai, - ICLASS_xt_iclass_s32ri, - ICLASS_xt_iclass_s32c1i, - ICLASS_xt_iclass_rsr_scompare1, - ICLASS_xt_iclass_wsr_scompare1, - ICLASS_xt_iclass_xsr_scompare1, - ICLASS_xt_iclass_rsr_atomctl, - ICLASS_xt_iclass_wsr_atomctl, - ICLASS_xt_iclass_xsr_atomctl, - ICLASS_xt_iclass_rer, - ICLASS_xt_iclass_wer, - ICLASS_rur_ae_ovf_sar, - ICLASS_wur_ae_ovf_sar, - ICLASS_rur_ae_bithead, - ICLASS_wur_ae_bithead, - ICLASS_rur_ae_ts_fts_bu_bp, - ICLASS_wur_ae_ts_fts_bu_bp, - ICLASS_rur_ae_sd_no, - ICLASS_wur_ae_sd_no, - ICLASS_ae_iclass_rur_ae_overflow, - ICLASS_ae_iclass_wur_ae_overflow, - ICLASS_ae_iclass_rur_ae_sar, - ICLASS_ae_iclass_wur_ae_sar, - ICLASS_ae_iclass_rur_ae_bitptr, - ICLASS_ae_iclass_wur_ae_bitptr, - ICLASS_ae_iclass_rur_ae_bitsused, - ICLASS_ae_iclass_wur_ae_bitsused, - ICLASS_ae_iclass_rur_ae_tablesize, - ICLASS_ae_iclass_wur_ae_tablesize, - ICLASS_ae_iclass_rur_ae_first_ts, - ICLASS_ae_iclass_wur_ae_first_ts, - ICLASS_ae_iclass_rur_ae_nextoffset, - ICLASS_ae_iclass_wur_ae_nextoffset, - ICLASS_ae_iclass_rur_ae_searchdone, - ICLASS_ae_iclass_wur_ae_searchdone, - ICLASS_ae_iclass_lp16f_i, - ICLASS_ae_iclass_lp16f_iu, - ICLASS_ae_iclass_lp16f_x, - ICLASS_ae_iclass_lp16f_xu, - ICLASS_ae_iclass_lp24_i, - ICLASS_ae_iclass_lp24_iu, - ICLASS_ae_iclass_lp24_x, - ICLASS_ae_iclass_lp24_xu, - ICLASS_ae_iclass_lp24f_i, - ICLASS_ae_iclass_lp24f_iu, - ICLASS_ae_iclass_lp24f_x, - ICLASS_ae_iclass_lp24f_xu, - ICLASS_ae_iclass_lp16x2f_i, - ICLASS_ae_iclass_lp16x2f_iu, - ICLASS_ae_iclass_lp16x2f_x, - ICLASS_ae_iclass_lp16x2f_xu, - ICLASS_ae_iclass_lp24x2f_i, - ICLASS_ae_iclass_lp24x2f_iu, - ICLASS_ae_iclass_lp24x2f_x, - ICLASS_ae_iclass_lp24x2f_xu, - ICLASS_ae_iclass_lp24x2_i, - ICLASS_ae_iclass_lp24x2_iu, - ICLASS_ae_iclass_lp24x2_x, - ICLASS_ae_iclass_lp24x2_xu, - ICLASS_ae_iclass_sp16x2f_i, - ICLASS_ae_iclass_sp16x2f_iu, - ICLASS_ae_iclass_sp16x2f_x, - ICLASS_ae_iclass_sp16x2f_xu, - ICLASS_ae_iclass_sp24x2s_i, - ICLASS_ae_iclass_sp24x2s_iu, - ICLASS_ae_iclass_sp24x2s_x, - ICLASS_ae_iclass_sp24x2s_xu, - ICLASS_ae_iclass_sp24x2f_i, - ICLASS_ae_iclass_sp24x2f_iu, - ICLASS_ae_iclass_sp24x2f_x, - ICLASS_ae_iclass_sp24x2f_xu, - ICLASS_ae_iclass_sp16f_l_i, - ICLASS_ae_iclass_sp16f_l_iu, - ICLASS_ae_iclass_sp16f_l_x, - ICLASS_ae_iclass_sp16f_l_xu, - ICLASS_ae_iclass_sp24s_l_i, - ICLASS_ae_iclass_sp24s_l_iu, - ICLASS_ae_iclass_sp24s_l_x, - ICLASS_ae_iclass_sp24s_l_xu, - ICLASS_ae_iclass_sp24f_l_i, - ICLASS_ae_iclass_sp24f_l_iu, - ICLASS_ae_iclass_sp24f_l_x, - ICLASS_ae_iclass_sp24f_l_xu, - ICLASS_ae_iclass_lq56_i, - ICLASS_ae_iclass_lq56_iu, - ICLASS_ae_iclass_lq56_x, - ICLASS_ae_iclass_lq56_xu, - ICLASS_ae_iclass_lq32f_i, - ICLASS_ae_iclass_lq32f_iu, - ICLASS_ae_iclass_lq32f_x, - ICLASS_ae_iclass_lq32f_xu, - ICLASS_ae_iclass_sq56s_i, - ICLASS_ae_iclass_sq56s_iu, - ICLASS_ae_iclass_sq56s_x, - ICLASS_ae_iclass_sq56s_xu, - ICLASS_ae_iclass_sq32f_i, - ICLASS_ae_iclass_sq32f_iu, - ICLASS_ae_iclass_sq32f_x, - ICLASS_ae_iclass_sq32f_xu, - ICLASS_ae_iclass_zerop48, - ICLASS_ae_iclass_movp48, - ICLASS_ae_iclass_selp24_ll, - ICLASS_ae_iclass_selp24_lh, - ICLASS_ae_iclass_selp24_hl, - ICLASS_ae_iclass_selp24_hh, - ICLASS_ae_iclass_movtp24x2, - ICLASS_ae_iclass_movfp24x2, - ICLASS_ae_iclass_movtp48, - ICLASS_ae_iclass_movfp48, - ICLASS_ae_iclass_movpa24x2, - ICLASS_ae_iclass_truncp24a32x2, - ICLASS_ae_iclass_cvta32p24_l, - ICLASS_ae_iclass_cvta32p24_h, - ICLASS_ae_iclass_cvtp24a16x2_ll, - ICLASS_ae_iclass_cvtp24a16x2_lh, - ICLASS_ae_iclass_cvtp24a16x2_hl, - ICLASS_ae_iclass_cvtp24a16x2_hh, - ICLASS_ae_iclass_truncp24q48x2, - ICLASS_ae_iclass_truncp16, - ICLASS_ae_iclass_roundsp24q48sym, - ICLASS_ae_iclass_roundsp24q48asym, - ICLASS_ae_iclass_roundsp16q48sym, - ICLASS_ae_iclass_roundsp16q48asym, - ICLASS_ae_iclass_roundsp16sym, - ICLASS_ae_iclass_roundsp16asym, - ICLASS_ae_iclass_zeroq56, - ICLASS_ae_iclass_movq56, - ICLASS_ae_iclass_movtq56, - ICLASS_ae_iclass_movfq56, - ICLASS_ae_iclass_cvtq48a32s, - ICLASS_ae_iclass_cvtq48p24s_l, - ICLASS_ae_iclass_cvtq48p24s_h, - ICLASS_ae_iclass_satq48s, - ICLASS_ae_iclass_truncq32, - ICLASS_ae_iclass_roundsq32sym, - ICLASS_ae_iclass_roundsq32asym, - ICLASS_ae_iclass_trunca32q48, - ICLASS_ae_iclass_movap24s_l, - ICLASS_ae_iclass_movap24s_h, - ICLASS_ae_iclass_trunca16p24s_l, - ICLASS_ae_iclass_trunca16p24s_h, - ICLASS_ae_iclass_addp24, - ICLASS_ae_iclass_subp24, - ICLASS_ae_iclass_negp24, - ICLASS_ae_iclass_absp24, - ICLASS_ae_iclass_maxp24s, - ICLASS_ae_iclass_minp24s, - ICLASS_ae_iclass_maxbp24s, - ICLASS_ae_iclass_minbp24s, - ICLASS_ae_iclass_addsp24s, - ICLASS_ae_iclass_subsp24s, - ICLASS_ae_iclass_negsp24s, - ICLASS_ae_iclass_abssp24s, - ICLASS_ae_iclass_andp48, - ICLASS_ae_iclass_nandp48, - ICLASS_ae_iclass_orp48, - ICLASS_ae_iclass_xorp48, - ICLASS_ae_iclass_ltp24s, - ICLASS_ae_iclass_lep24s, - ICLASS_ae_iclass_eqp24, - ICLASS_ae_iclass_addq56, - ICLASS_ae_iclass_subq56, - ICLASS_ae_iclass_negq56, - ICLASS_ae_iclass_absq56, - ICLASS_ae_iclass_maxq56s, - ICLASS_ae_iclass_minq56s, - ICLASS_ae_iclass_maxbq56s, - ICLASS_ae_iclass_minbq56s, - ICLASS_ae_iclass_addsq56s, - ICLASS_ae_iclass_subsq56s, - ICLASS_ae_iclass_negsq56s, - ICLASS_ae_iclass_abssq56s, - ICLASS_ae_iclass_andq56, - ICLASS_ae_iclass_nandq56, - ICLASS_ae_iclass_orq56, - ICLASS_ae_iclass_xorq56, - ICLASS_ae_iclass_sllip24, - ICLASS_ae_iclass_srlip24, - ICLASS_ae_iclass_sraip24, - ICLASS_ae_iclass_sllsp24, - ICLASS_ae_iclass_srlsp24, - ICLASS_ae_iclass_srasp24, - ICLASS_ae_iclass_sllisp24s, - ICLASS_ae_iclass_sllssp24s, - ICLASS_ae_iclass_slliq56, - ICLASS_ae_iclass_srliq56, - ICLASS_ae_iclass_sraiq56, - ICLASS_ae_iclass_sllsq56, - ICLASS_ae_iclass_srlsq56, - ICLASS_ae_iclass_srasq56, - ICLASS_ae_iclass_sllaq56, - ICLASS_ae_iclass_srlaq56, - ICLASS_ae_iclass_sraaq56, - ICLASS_ae_iclass_sllisq56s, - ICLASS_ae_iclass_sllssq56s, - ICLASS_ae_iclass_sllasq56s, - ICLASS_ae_iclass_ltq56s, - ICLASS_ae_iclass_leq56s, - ICLASS_ae_iclass_eqq56, - ICLASS_ae_iclass_nsaq56s, - ICLASS_ae_iclass_mulsrfq32sp24s_h, - ICLASS_ae_iclass_mulsrfq32sp24s_l, - ICLASS_ae_iclass_mularfq32sp24s_h, - ICLASS_ae_iclass_mularfq32sp24s_l, - ICLASS_ae_iclass_mulrfq32sp24s_h, - ICLASS_ae_iclass_mulrfq32sp24s_l, - ICLASS_ae_iclass_mulsfq32sp24s_h, - ICLASS_ae_iclass_mulsfq32sp24s_l, - ICLASS_ae_iclass_mulafq32sp24s_h, - ICLASS_ae_iclass_mulafq32sp24s_l, - ICLASS_ae_iclass_mulfq32sp24s_h, - ICLASS_ae_iclass_mulfq32sp24s_l, - ICLASS_ae_iclass_mulfs32p16s_ll, - ICLASS_ae_iclass_mulfp24s_ll, - ICLASS_ae_iclass_mulp24s_ll, - ICLASS_ae_iclass_mulfs32p16s_lh, - ICLASS_ae_iclass_mulfp24s_lh, - ICLASS_ae_iclass_mulp24s_lh, - ICLASS_ae_iclass_mulfs32p16s_hl, - ICLASS_ae_iclass_mulfp24s_hl, - ICLASS_ae_iclass_mulp24s_hl, - ICLASS_ae_iclass_mulfs32p16s_hh, - ICLASS_ae_iclass_mulfp24s_hh, - ICLASS_ae_iclass_mulp24s_hh, - ICLASS_ae_iclass_mulafs32p16s_ll, - ICLASS_ae_iclass_mulafp24s_ll, - ICLASS_ae_iclass_mulap24s_ll, - ICLASS_ae_iclass_mulafs32p16s_lh, - ICLASS_ae_iclass_mulafp24s_lh, - ICLASS_ae_iclass_mulap24s_lh, - ICLASS_ae_iclass_mulafs32p16s_hl, - ICLASS_ae_iclass_mulafp24s_hl, - ICLASS_ae_iclass_mulap24s_hl, - ICLASS_ae_iclass_mulafs32p16s_hh, - ICLASS_ae_iclass_mulafp24s_hh, - ICLASS_ae_iclass_mulap24s_hh, - ICLASS_ae_iclass_mulsfs32p16s_ll, - ICLASS_ae_iclass_mulsfp24s_ll, - ICLASS_ae_iclass_mulsp24s_ll, - ICLASS_ae_iclass_mulsfs32p16s_lh, - ICLASS_ae_iclass_mulsfp24s_lh, - ICLASS_ae_iclass_mulsp24s_lh, - ICLASS_ae_iclass_mulsfs32p16s_hl, - ICLASS_ae_iclass_mulsfp24s_hl, - ICLASS_ae_iclass_mulsp24s_hl, - ICLASS_ae_iclass_mulsfs32p16s_hh, - ICLASS_ae_iclass_mulsfp24s_hh, - ICLASS_ae_iclass_mulsp24s_hh, - ICLASS_ae_iclass_mulafs56p24s_ll, - ICLASS_ae_iclass_mulas56p24s_ll, - ICLASS_ae_iclass_mulafs56p24s_lh, - ICLASS_ae_iclass_mulas56p24s_lh, - ICLASS_ae_iclass_mulafs56p24s_hl, - ICLASS_ae_iclass_mulas56p24s_hl, - ICLASS_ae_iclass_mulafs56p24s_hh, - ICLASS_ae_iclass_mulas56p24s_hh, - ICLASS_ae_iclass_mulsfs56p24s_ll, - ICLASS_ae_iclass_mulss56p24s_ll, - ICLASS_ae_iclass_mulsfs56p24s_lh, - ICLASS_ae_iclass_mulss56p24s_lh, - ICLASS_ae_iclass_mulsfs56p24s_hl, - ICLASS_ae_iclass_mulss56p24s_hl, - ICLASS_ae_iclass_mulsfs56p24s_hh, - ICLASS_ae_iclass_mulss56p24s_hh, - ICLASS_ae_iclass_mulfq32sp16s_l, - ICLASS_ae_iclass_mulfq32sp16s_h, - ICLASS_ae_iclass_mulfq32sp16u_l, - ICLASS_ae_iclass_mulfq32sp16u_h, - ICLASS_ae_iclass_mulq32sp16s_l, - ICLASS_ae_iclass_mulq32sp16s_h, - ICLASS_ae_iclass_mulq32sp16u_l, - ICLASS_ae_iclass_mulq32sp16u_h, - ICLASS_ae_iclass_mulafq32sp16s_l, - ICLASS_ae_iclass_mulafq32sp16s_h, - ICLASS_ae_iclass_mulafq32sp16u_l, - ICLASS_ae_iclass_mulafq32sp16u_h, - ICLASS_ae_iclass_mulaq32sp16s_l, - ICLASS_ae_iclass_mulaq32sp16s_h, - ICLASS_ae_iclass_mulaq32sp16u_l, - ICLASS_ae_iclass_mulaq32sp16u_h, - ICLASS_ae_iclass_mulsfq32sp16s_l, - ICLASS_ae_iclass_mulsfq32sp16s_h, - ICLASS_ae_iclass_mulsfq32sp16u_l, - ICLASS_ae_iclass_mulsfq32sp16u_h, - ICLASS_ae_iclass_mulsq32sp16s_l, - ICLASS_ae_iclass_mulsq32sp16s_h, - ICLASS_ae_iclass_mulsq32sp16u_l, - ICLASS_ae_iclass_mulsq32sp16u_h, - ICLASS_ae_iclass_mulzaaq32sp16s_ll, - ICLASS_ae_iclass_mulzaafq32sp16s_ll, - ICLASS_ae_iclass_mulzaaq32sp16u_ll, - ICLASS_ae_iclass_mulzaafq32sp16u_ll, - ICLASS_ae_iclass_mulzaaq32sp16s_hh, - ICLASS_ae_iclass_mulzaafq32sp16s_hh, - ICLASS_ae_iclass_mulzaaq32sp16u_hh, - ICLASS_ae_iclass_mulzaafq32sp16u_hh, - ICLASS_ae_iclass_mulzaaq32sp16s_lh, - ICLASS_ae_iclass_mulzaafq32sp16s_lh, - ICLASS_ae_iclass_mulzaaq32sp16u_lh, - ICLASS_ae_iclass_mulzaafq32sp16u_lh, - ICLASS_ae_iclass_mulzasq32sp16s_ll, - ICLASS_ae_iclass_mulzasfq32sp16s_ll, - ICLASS_ae_iclass_mulzasq32sp16u_ll, - ICLASS_ae_iclass_mulzasfq32sp16u_ll, - ICLASS_ae_iclass_mulzasq32sp16s_hh, - ICLASS_ae_iclass_mulzasfq32sp16s_hh, - ICLASS_ae_iclass_mulzasq32sp16u_hh, - ICLASS_ae_iclass_mulzasfq32sp16u_hh, - ICLASS_ae_iclass_mulzasq32sp16s_lh, - ICLASS_ae_iclass_mulzasfq32sp16s_lh, - ICLASS_ae_iclass_mulzasq32sp16u_lh, - ICLASS_ae_iclass_mulzasfq32sp16u_lh, - ICLASS_ae_iclass_mulzsaq32sp16s_ll, - ICLASS_ae_iclass_mulzsafq32sp16s_ll, - ICLASS_ae_iclass_mulzsaq32sp16u_ll, - ICLASS_ae_iclass_mulzsafq32sp16u_ll, - ICLASS_ae_iclass_mulzsaq32sp16s_hh, - ICLASS_ae_iclass_mulzsafq32sp16s_hh, - ICLASS_ae_iclass_mulzsaq32sp16u_hh, - ICLASS_ae_iclass_mulzsafq32sp16u_hh, - ICLASS_ae_iclass_mulzsaq32sp16s_lh, - ICLASS_ae_iclass_mulzsafq32sp16s_lh, - ICLASS_ae_iclass_mulzsaq32sp16u_lh, - ICLASS_ae_iclass_mulzsafq32sp16u_lh, - ICLASS_ae_iclass_mulzssq32sp16s_ll, - ICLASS_ae_iclass_mulzssfq32sp16s_ll, - ICLASS_ae_iclass_mulzssq32sp16u_ll, - ICLASS_ae_iclass_mulzssfq32sp16u_ll, - ICLASS_ae_iclass_mulzssq32sp16s_hh, - ICLASS_ae_iclass_mulzssfq32sp16s_hh, - ICLASS_ae_iclass_mulzssq32sp16u_hh, - ICLASS_ae_iclass_mulzssfq32sp16u_hh, - ICLASS_ae_iclass_mulzssq32sp16s_lh, - ICLASS_ae_iclass_mulzssfq32sp16s_lh, - ICLASS_ae_iclass_mulzssq32sp16u_lh, - ICLASS_ae_iclass_mulzssfq32sp16u_lh, - ICLASS_ae_iclass_mulzaafp24s_hh_ll, - ICLASS_ae_iclass_mulzaap24s_hh_ll, - ICLASS_ae_iclass_mulzaafp24s_hl_lh, - ICLASS_ae_iclass_mulzaap24s_hl_lh, - ICLASS_ae_iclass_mulzasfp24s_hh_ll, - ICLASS_ae_iclass_mulzasp24s_hh_ll, - ICLASS_ae_iclass_mulzasfp24s_hl_lh, - ICLASS_ae_iclass_mulzasp24s_hl_lh, - ICLASS_ae_iclass_mulzsafp24s_hh_ll, - ICLASS_ae_iclass_mulzsap24s_hh_ll, - ICLASS_ae_iclass_mulzsafp24s_hl_lh, - ICLASS_ae_iclass_mulzsap24s_hl_lh, - ICLASS_ae_iclass_mulzssfp24s_hh_ll, - ICLASS_ae_iclass_mulzssp24s_hh_ll, - ICLASS_ae_iclass_mulzssfp24s_hl_lh, - ICLASS_ae_iclass_mulzssp24s_hl_lh, - ICLASS_ae_iclass_mulaafp24s_hh_ll, - ICLASS_ae_iclass_mulaap24s_hh_ll, - ICLASS_ae_iclass_mulaafp24s_hl_lh, - ICLASS_ae_iclass_mulaap24s_hl_lh, - ICLASS_ae_iclass_mulasfp24s_hh_ll, - ICLASS_ae_iclass_mulasp24s_hh_ll, - ICLASS_ae_iclass_mulasfp24s_hl_lh, - ICLASS_ae_iclass_mulasp24s_hl_lh, - ICLASS_ae_iclass_mulsafp24s_hh_ll, - ICLASS_ae_iclass_mulsap24s_hh_ll, - ICLASS_ae_iclass_mulsafp24s_hl_lh, - ICLASS_ae_iclass_mulsap24s_hl_lh, - ICLASS_ae_iclass_mulssfp24s_hh_ll, - ICLASS_ae_iclass_mulssp24s_hh_ll, - ICLASS_ae_iclass_mulssfp24s_hl_lh, - ICLASS_ae_iclass_mulssp24s_hl_lh, - ICLASS_ae_iclass_sha32, - ICLASS_ae_iclass_vldl32t, - ICLASS_ae_iclass_vldl16t, - ICLASS_ae_iclass_vldl16c, - ICLASS_ae_iclass_vldsht, - ICLASS_ae_iclass_lb, - ICLASS_ae_iclass_lbi, - ICLASS_ae_iclass_lbk, - ICLASS_ae_iclass_lbki, - ICLASS_ae_iclass_db, - ICLASS_ae_iclass_dbi, - ICLASS_ae_iclass_vlel32t, - ICLASS_ae_iclass_vlel16t, - ICLASS_ae_iclass_sb, - ICLASS_ae_iclass_sbi, - ICLASS_ae_iclass_vles16c, - ICLASS_ae_iclass_sbf, - ICLASS_icls_AE_SLAASQ56S, - ICLASS_icls_AE_ADDBRBA32, - ICLASS_icls_AE_MINABSSP24S, - ICLASS_icls_AE_MAXABSSP24S, - ICLASS_icls_AE_MINABSSQ56S, - ICLASS_icls_AE_MAXABSSQ56S, - ICLASS_rur_ae_cbegin0, - ICLASS_wur_ae_cbegin0, - ICLASS_rur_ae_cend0, - ICLASS_wur_ae_cend0, - ICLASS_icls_AE_LP24X2_C, - ICLASS_icls_AE_SP24X2S_C, - ICLASS_icls_AE_LP24X2F_C, - ICLASS_icls_AE_SP24X2F_C, - ICLASS_icls_AE_LP16X2F_C, - ICLASS_icls_AE_SP16X2F_C, - ICLASS_icls_AE_LP24_C, - ICLASS_icls_AE_SP24S_L_C, - ICLASS_icls_AE_LP24F_C, - ICLASS_icls_AE_SP24F_L_C, - ICLASS_icls_AE_LP16F_C, - ICLASS_icls_AE_SP16F_L_C, - ICLASS_icls_AE_LQ56_C, - ICLASS_icls_AE_SQ56S_C, - ICLASS_icls_AE_LQ32F_C, - ICLASS_icls_AE_SQ32F_C -}; - - -/* Opcode encodings. */ - -static void -Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2080; -} - -static void -Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000; -} - -static void -Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3200; -} - -static void -Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5000; -} - -static void -Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35; -} - -static void -Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x25; -} - -static void -Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15; -} - -static void -Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf0; -} - -static void -Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0; -} - -static void -Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd0; -} - -static void -Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36; -} - -static void -Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1000; -} - -static void -Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x408000; -} - -static void -Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90; -} - -static void -Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf01d; -} - -static void -Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3400; -} - -static void -Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3500; -} - -static void -Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90000; -} - -static void -Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x490000; -} - -static void -Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34800; -} - -static void -Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134800; -} - -static void -Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614800; -} - -static void -Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34900; -} - -static void -Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134900; -} - -static void -Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614900; -} - -static void -Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa; -} - -static void -Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb; -} - -static void -Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8c; -} - -static void -Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcc; -} - -static void -Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf06d; -} - -static void -Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8; -} - -static void -Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd; -} - -static void -Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc; -} - -static void -Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf03d; -} - -static void -Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00d; -} - -static void -Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9; -} - -static void -Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30e70; -} - -static void -Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3e700; -} - -static void -Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc002; -} - -static void -Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200040; -} - -static void -Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd002; -} - -static void -Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200080; -} - -static void -Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800000; -} - -static void -Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b2000; -} - -static void -Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc00000; -} - -static void -Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ca000; -} - -static void -Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900000; -} - -static void -Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b4000; -} - -static void -Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00000; -} - -static void -Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b8000; -} - -static void -Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb00000; -} - -static void -Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b3000; -} - -static void -Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd00000; -} - -static void -Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cc000; -} - -static void -Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00000; -} - -static void -Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cb000; -} - -static void -Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00000; -} - -static void -Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cd000; -} - -static void -Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b5000; -} - -static void -Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e0000; -} - -static void -Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300000; -} - -static void -Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ce000; -} - -static void -Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x26; -} - -static void -Opcode_beqi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300000; -} - -static void -Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x66; -} - -static void -Opcode_bnei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300003; -} - -static void -Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe6; -} - -static void -Opcode_bgei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300001; -} - -static void -Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa6; -} - -static void -Opcode_blti_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300004; -} - -static void -Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6007; -} - -static void -Opcode_bbci_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe007; -} - -static void -Opcode_bbsi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200020; -} - -static void -Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf6; -} - -static void -Opcode_bgeui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300002; -} - -static void -Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb6; -} - -static void -Opcode_bltui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300008; -} - -static void -Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1007; -} - -static void -Opcode_beq_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000a0; -} - -static void -Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9007; -} - -static void -Opcode_bne_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400000; -} - -static void -Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa007; -} - -static void -Opcode_bge_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000c0; -} - -static void -Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2007; -} - -static void -Opcode_blt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000d0; -} - -static void -Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb007; -} - -static void -Opcode_bgeu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000b0; -} - -static void -Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3007; -} - -static void -Opcode_bltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000e0; -} - -static void -Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8007; -} - -static void -Opcode_bany_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200060; -} - -static void -Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7; -} - -static void -Opcode_bnone_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400010; -} - -static void -Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4007; -} - -static void -Opcode_ball_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200050; -} - -static void -Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc007; -} - -static void -Opcode_bnall_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000f0; -} - -static void -Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5007; -} - -static void -Opcode_bbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200070; -} - -static void -Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd007; -} - -static void -Opcode_bbs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200090; -} - -static void -Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16; -} - -static void -Opcode_beqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180000; -} - -static void -Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x56; -} - -static void -Opcode_bnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x190000; -} - -static void -Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd6; -} - -static void -Opcode_bgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x160000; -} - -static void -Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x96; -} - -static void -Opcode_bltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x170000; -} - -static void -Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5; -} - -static void -Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc0; -} - -static void -Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000; -} - -static void -Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x140000; -} - -static void -Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0; -} - -static void -Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6; -} - -static void -Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0; -} - -static void -Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee031; -} - -static void -Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1002; -} - -static void -Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400040; -} - -static void -Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9002; -} - -static void -Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400020; -} - -static void -Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2002; -} - -static void -Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400080; -} - -static void -Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1; -} - -static void -Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500000; -} - -static void -Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2; -} - -static void -Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400030; -} - -static void -Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8076; -} - -static void -Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9076; -} - -static void -Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa076; -} - -static void -Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa002; -} - -static void -Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a0000; -} - -static void -Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x830000; -} - -static void -Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1be000; -} - -static void -Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x930000; -} - -static void -Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c8000; -} - -static void -Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa30000; -} - -static void -Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c4000; -} - -static void -Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb30000; -} - -static void -Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c2000; -} - -static void -Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600000; -} - -static void -Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1d00; -} - -static void -Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600100; -} - -static void -Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1c00; -} - -static void -Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20f0; -} - -static void -Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16105; -} - -static void -Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee0b1; -} - -static void -Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80; -} - -static void -Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5100; -} - -static void -Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5002; -} - -static void -Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400050; -} - -static void -Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6002; -} - -static void -Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400060; -} - -static void -Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4002; -} - -static void -Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400070; -} - -static void -Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400000; -} - -static void -Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee071; -} - -static void -Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x401000; -} - -static void -Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee038; -} - -static void -Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x402000; -} - -static void -Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee034; -} - -static void -Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x403000; -} - -static void -Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee032; -} - -static void -Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x404000; -} - -static void -Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef0a0; -} - -static void -Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa10000; -} - -static void -Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5003; -} - -static void -Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x810000; -} - -static void -Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c7000; -} - -static void -Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x910000; -} - -static void -Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1f00; -} - -static void -Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb10000; -} - -static void -Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1e00; -} - -static void -Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10000; -} - -static void -Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c0000; -} - -static void -Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x210000; -} - -static void -Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b0000; -} - -static void -Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x410000; -} - -static void -Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c9000; -} - -static void -Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20c0; -} - -static void -Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20d0; -} - -static void -Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000; -} - -static void -Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2010; -} - -static void -Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2020; -} - -static void -Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2030; -} - -static void -Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000; -} - -static void -Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30100; -} - -static void -Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130100; -} - -static void -Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610100; -} - -static void -Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30200; -} - -static void -Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130200; -} - -static void -Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610200; -} - -static void -Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000; -} - -static void -Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130000; -} - -static void -Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610000; -} - -static void -Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30300; -} - -static void -Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130300; -} - -static void -Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610300; -} - -static void -Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30500; -} - -static void -Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130500; -} - -static void -Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610500; -} - -static void -Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b000; -} - -static void -Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b000; -} - -static void -Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d000; -} - -static void -Opcode_rsr_243_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f300; -} - -static void -Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e600; -} - -static void -Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e600; -} - -static void -Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e600; -} - -static void -Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b100; -} - -static void -Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b100; -} - -static void -Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b100; -} - -static void -Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d100; -} - -static void -Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d100; -} - -static void -Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d100; -} - -static void -Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b200; -} - -static void -Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b200; -} - -static void -Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b200; -} - -static void -Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d200; -} - -static void -Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d200; -} - -static void -Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d200; -} - -static void -Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b300; -} - -static void -Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b300; -} - -static void -Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b300; -} - -static void -Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d300; -} - -static void -Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d300; -} - -static void -Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d300; -} - -static void -Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b400; -} - -static void -Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b400; -} - -static void -Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b400; -} - -static void -Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d400; -} - -static void -Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d400; -} - -static void -Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d400; -} - -static void -Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b500; -} - -static void -Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b500; -} - -static void -Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b500; -} - -static void -Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d500; -} - -static void -Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d500; -} - -static void -Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d500; -} - -static void -Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b600; -} - -static void -Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b600; -} - -static void -Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b600; -} - -static void -Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d600; -} - -static void -Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d600; -} - -static void -Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d600; -} - -static void -Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b700; -} - -static void -Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b700; -} - -static void -Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b700; -} - -static void -Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d700; -} - -static void -Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d700; -} - -static void -Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d700; -} - -static void -Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c200; -} - -static void -Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c200; -} - -static void -Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c200; -} - -static void -Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c300; -} - -static void -Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c300; -} - -static void -Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c300; -} - -static void -Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c400; -} - -static void -Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c400; -} - -static void -Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c400; -} - -static void -Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c500; -} - -static void -Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c500; -} - -static void -Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c500; -} - -static void -Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c600; -} - -static void -Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c600; -} - -static void -Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c600; -} - -static void -Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c700; -} - -static void -Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c700; -} - -static void -Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c700; -} - -static void -Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ee00; -} - -static void -Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ee00; -} - -static void -Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ee00; -} - -static void -Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c000; -} - -static void -Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c000; -} - -static void -Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c000; -} - -static void -Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e800; -} - -static void -Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e800; -} - -static void -Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e800; -} - -static void -Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3eb00; -} - -static void -Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e700; -} - -static void -Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e700; -} - -static void -Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e700; -} - -static void -Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc10000; -} - -static void -Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd10000; -} - -static void -Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x820000; -} - -static void -Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa20000; -} - -static void -Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb20000; -} - -static void -Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x740004; -} - -static void -Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x750004; -} - -static void -Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x760004; -} - -static void -Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x770004; -} - -static void -Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700004; -} - -static void -Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x710004; -} - -static void -Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x720004; -} - -static void -Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x730004; -} - -static void -Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x340004; -} - -static void -Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x350004; -} - -static void -Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x360004; -} - -static void -Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x370004; -} - -static void -Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x640004; -} - -static void -Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x650004; -} - -static void -Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x660004; -} - -static void -Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x670004; -} - -static void -Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x240004; -} - -static void -Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x250004; -} - -static void -Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x260004; -} - -static void -Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x270004; -} - -static void -Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x780004; -} - -static void -Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x790004; -} - -static void -Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7a0004; -} - -static void -Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7b0004; -} - -static void -Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7c0004; -} - -static void -Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7d0004; -} - -static void -Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7e0004; -} - -static void -Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7f0004; -} - -static void -Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x380004; -} - -static void -Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x390004; -} - -static void -Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a0004; -} - -static void -Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b0004; -} - -static void -Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c0004; -} - -static void -Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d0004; -} - -static void -Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e0004; -} - -static void -Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f0004; -} - -static void -Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x680004; -} - -static void -Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x690004; -} - -static void -Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6a0004; -} - -static void -Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6b0004; -} - -static void -Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6c0004; -} - -static void -Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6d0004; -} - -static void -Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6e0004; -} - -static void -Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6f0004; -} - -static void -Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280004; -} - -static void -Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x290004; -} - -static void -Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2a0004; -} - -static void -Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2b0004; -} - -static void -Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2c0004; -} - -static void -Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2d0004; -} - -static void -Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2e0004; -} - -static void -Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2f0004; -} - -static void -Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x580004; -} - -static void -Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x480004; -} - -static void -Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x590004; -} - -static void -Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x490004; -} - -static void -Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5a0004; -} - -static void -Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4a0004; -} - -static void -Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5b0004; -} - -static void -Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4b0004; -} - -static void -Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180004; -} - -static void -Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80004; -} - -static void -Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x190004; -} - -static void -Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90004; -} - -static void -Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a0004; -} - -static void -Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0004; -} - -static void -Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b0004; -} - -static void -Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb0004; -} - -static void -Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900004; -} - -static void -Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800004; -} - -static void -Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32000; -} - -static void -Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132000; -} - -static void -Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612000; -} - -static void -Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32100; -} - -static void -Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132100; -} - -static void -Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612100; -} - -static void -Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32200; -} - -static void -Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132200; -} - -static void -Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612200; -} - -static void -Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32300; -} - -static void -Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132300; -} - -static void -Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612300; -} - -static void -Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31000; -} - -static void -Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131000; -} - -static void -Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x611000; -} - -static void -Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31100; -} - -static void -Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131100; -} - -static void -Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x611100; -} - -static void -Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3010; -} - -static void -Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7000; -} - -static void -Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e200; -} - -static void -Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e200; -} - -static void -Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e300; -} - -static void -Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e400; -} - -static void -Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e400; -} - -static void -Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e400; -} - -static void -Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000; -} - -static void -Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf02d; -} - -static void -Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39000; -} - -static void -Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139000; -} - -static void -Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619000; -} - -static void -Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a000; -} - -static void -Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a000; -} - -static void -Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a000; -} - -static void -Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39100; -} - -static void -Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139100; -} - -static void -Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619100; -} - -static void -Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a100; -} - -static void -Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a100; -} - -static void -Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a100; -} - -static void -Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38000; -} - -static void -Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138000; -} - -static void -Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618000; -} - -static void -Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38100; -} - -static void -Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138100; -} - -static void -Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618100; -} - -static void -Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36000; -} - -static void -Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136000; -} - -static void -Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616000; -} - -static void -Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e900; -} - -static void -Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e900; -} - -static void -Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e900; -} - -static void -Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ec00; -} - -static void -Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ec00; -} - -static void -Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ec00; -} - -static void -Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ed00; -} - -static void -Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ed00; -} - -static void -Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ed00; -} - -static void -Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36800; -} - -static void -Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136800; -} - -static void -Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616800; -} - -static void -Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e000; -} - -static void -Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e010; -} - -static void -Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20000; -} - -static void -Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b6000; -} - -static void -Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x120000; -} - -static void -Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b7000; -} - -static void -Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x220000; -} - -static void -Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c3000; -} - -static void -Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x320000; -} - -static void -Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c5000; -} - -static void -Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x420000; -} - -static void -Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cf000; -} - -static void -Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8000; -} - -static void -Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2480; -} - -static void -Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9000; -} - -static void -Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2800; -} - -static void -Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa000; -} - -static void -Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef060; -} - -static void -Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb000; -} - -static void -Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef020; -} - -static void -Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x76; -} - -static void -Opcode_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300005; -} - -static void -Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1076; -} - -static void -Opcode_bt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300006; -} - -static void -Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc30000; -} - -static void -Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bf000; -} - -static void -Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd30000; -} - -static void -Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d0000; -} - -static void -Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30400; -} - -static void -Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130400; -} - -static void -Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610400; -} - -static void -Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ea00; -} - -static void -Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ea00; -} - -static void -Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ea00; -} - -static void -Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f000; -} - -static void -Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f000; -} - -static void -Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f000; -} - -static void -Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f100; -} - -static void -Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f100; -} - -static void -Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f100; -} - -static void -Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f200; -} - -static void -Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f200; -} - -static void -Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f200; -} - -static void -Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70c2; -} - -static void -Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70e2; -} - -static void -Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70d2; -} - -static void -Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x270d2; -} - -static void -Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x370d2; -} - -static void -Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70f2; -} - -static void -Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf10000; -} - -static void -Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf12000; -} - -static void -Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf11000; -} - -static void -Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf13000; -} - -static void -Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7042; -} - -static void -Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7052; -} - -static void -Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x47082; -} - -static void -Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x57082; -} - -static void -Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7062; -} - -static void -Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7072; -} - -static void -Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7002; -} - -static void -Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7012; -} - -static void -Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7022; -} - -static void -Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7032; -} - -static void -Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7082; -} - -static void -Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x27082; -} - -static void -Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x37082; -} - -static void -Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf19000; -} - -static void -Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf18000; -} - -static void -Opcode_rsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32800; -} - -static void -Opcode_wsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132800; -} - -static void -Opcode_xsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612800; -} - -static void -Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50c000; -} - -static void -Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50d000; -} - -static void -Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50b000; -} - -static void -Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50f000; -} - -static void -Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50e000; -} - -static void -Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x504000; -} - -static void -Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x505000; -} - -static void -Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x503000; -} - -static void -Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x507000; -} - -static void -Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x506000; -} - -static void -Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e000; -} - -static void -Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e000; -} - -static void -Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e000; -} - -static void -Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x330000; -} - -static void -Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b9000; -} - -static void -Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x430000; -} - -static void -Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bb000; -} - -static void -Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x530000; -} - -static void -Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ba000; -} - -static void -Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x630000; -} - -static void -Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bd000; -} - -static void -Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x730000; -} - -static void -Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bc000; -} - -static void -Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40e000; -} - -static void -Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40f000; -} - -static void -Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x230000; -} - -static void -Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c6000; -} - -static void -Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb002; -} - -static void -Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf002; -} - -static void -Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe002; -} - -static void -Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30c00; -} - -static void -Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130c00; -} - -static void -Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610c00; -} - -static void -Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36300; -} - -static void -Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136300; -} - -static void -Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616300; -} - -static void -Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x406000; -} - -static void -Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x407000; -} - -static void -Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f00; -} - -static void -Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f000; -} - -static void -Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f10; -} - -static void -Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f100; -} - -static void -Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f20; -} - -static void -Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f200; -} - -static void -Opcode_rur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f30; -} - -static void -Opcode_wur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f300; -} - -static void -Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90804; -} - -static void -Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca0004; -} - -static void -Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90904; -} - -static void -Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca1004; -} - -static void -Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90a04; -} - -static void -Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca2004; -} - -static void -Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90b04; -} - -static void -Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca3004; -} - -static void -Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90c04; -} - -static void -Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca4004; -} - -static void -Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90d04; -} - -static void -Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca5004; -} - -static void -Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90e04; -} - -static void -Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca6004; -} - -static void -Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90f04; -} - -static void -Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca7004; -} - -static void -Opcode_ae_lp16f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d1080; -} - -static void -Opcode_ae_lp16f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa50004; -} - -static void -Opcode_ae_lp16f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d2080; -} - -static void -Opcode_ae_lp16f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa90004; -} - -static void -Opcode_ae_lp16f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d3000; -} - -static void -Opcode_ae_lp16f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xac0004; -} - -static void -Opcode_ae_lp16f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d3080; -} - -static void -Opcode_ae_lp16f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaf0004; -} - -static void -Opcode_ae_lp24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d6080; -} - -static void -Opcode_ae_lp24_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa58004; -} - -static void -Opcode_ae_lp24_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d7000; -} - -static void -Opcode_ae_lp24_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa98004; -} - -static void -Opcode_ae_lp24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d7080; -} - -static void -Opcode_ae_lp24_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xac8004; -} - -static void -Opcode_ae_lp24_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d8080; -} - -static void -Opcode_ae_lp24_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaf8004; -} - -static void -Opcode_ae_lp24f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d9000; -} - -static void -Opcode_ae_lp24f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa60004; -} - -static void -Opcode_ae_lp24f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1da000; -} - -static void -Opcode_ae_lp24f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaa0004; -} - -static void -Opcode_ae_lp24f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dc000; -} - -static void -Opcode_ae_lp24f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xad0004; -} - -static void -Opcode_ae_lp24f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d9080; -} - -static void -Opcode_ae_lp24f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb00004; -} - -static void -Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d4080; -} - -static void -Opcode_ae_lp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa68004; -} - -static void -Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d5000; -} - -static void -Opcode_ae_lp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaa8004; -} - -static void -Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d6000; -} - -static void -Opcode_ae_lp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xad8004; -} - -static void -Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d5080; -} - -static void -Opcode_ae_lp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb08004; -} - -static void -Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dd000; -} - -static void -Opcode_ae_lp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa70004; -} - -static void -Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1de000; -} - -static void -Opcode_ae_lp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xab0004; -} - -static void -Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dd080; -} - -static void -Opcode_ae_lp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xae0004; -} - -static void -Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1de080; -} - -static void -Opcode_ae_lp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb10004; -} - -static void -Opcode_ae_lp24x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1da080; -} - -static void -Opcode_ae_lp24x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa78004; -} - -static void -Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1db000; -} - -static void -Opcode_ae_lp24x2_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xab8004; -} - -static void -Opcode_ae_lp24x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1db080; -} - -static void -Opcode_ae_lp24x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xae8004; -} - -static void -Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dc080; -} - -static void -Opcode_ae_lp24x2_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb18004; -} - -static void -Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e8000; -} - -static void -Opcode_ae_sp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb20004; -} - -static void -Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f0000; -} - -static void -Opcode_ae_sp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb50004; -} - -static void -Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e1080; -} - -static void -Opcode_ae_sp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb80004; -} - -static void -Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e2080; -} - -static void -Opcode_ae_sp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbb0004; -} - -static void -Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ec000; -} - -static void -Opcode_ae_sp24x2s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb28004; -} - -static void -Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e9080; -} - -static void -Opcode_ae_sp24x2s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb58004; -} - -static void -Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ea080; -} - -static void -Opcode_ae_sp24x2s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb88004; -} - -static void -Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1eb000; -} - -static void -Opcode_ae_sp24x2s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbb8004; -} - -static void -Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e7080; -} - -static void -Opcode_ae_sp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb30004; -} - -static void -Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e8080; -} - -static void -Opcode_ae_sp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb60004; -} - -static void -Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e9000; -} - -static void -Opcode_ae_sp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb90004; -} - -static void -Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ea000; -} - -static void -Opcode_ae_sp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbc0004; -} - -static void -Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1df080; -} - -static void -Opcode_ae_sp16f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb38004; -} - -static void -Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e1000; -} - -static void -Opcode_ae_sp16f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb68004; -} - -static void -Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e2000; -} - -static void -Opcode_ae_sp16f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb98004; -} - -static void -Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e4000; -} - -static void -Opcode_ae_sp16f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbc8004; -} - -static void -Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e6000; -} - -static void -Opcode_ae_sp24s_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb40004; -} - -static void -Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e5080; -} - -static void -Opcode_ae_sp24s_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb70004; -} - -static void -Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e6080; -} - -static void -Opcode_ae_sp24s_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xba0004; -} - -static void -Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e7000; -} - -static void -Opcode_ae_sp24s_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbd0004; -} - -static void -Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e3000; -} - -static void -Opcode_ae_sp24f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb48004; -} - -static void -Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e3080; -} - -static void -Opcode_ae_sp24f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb78004; -} - -static void -Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e4080; -} - -static void -Opcode_ae_sp24f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xba8004; -} - -static void -Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e5000; -} - -static void -Opcode_ae_sp24f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbd8004; -} - -static void -Opcode_ae_lq56_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed030; -} - -static void -Opcode_ae_lq56_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc10004; -} - -static void -Opcode_ae_lq56_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee010; -} - -static void -Opcode_ae_lq56_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc12004; -} - -static void -Opcode_ae_lq56_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee020; -} - -static void -Opcode_ae_lq56_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc20004; -} - -static void -Opcode_ae_lq56_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef000; -} - -static void -Opcode_ae_lq56_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc22004; -} - -static void -Opcode_ae_lq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed000; -} - -static void -Opcode_ae_lq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc11004; -} - -static void -Opcode_ae_lq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee000; -} - -static void -Opcode_ae_lq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc13004; -} - -static void -Opcode_ae_lq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed010; -} - -static void -Opcode_ae_lq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc21004; -} - -static void -Opcode_ae_lq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed020; -} - -static void -Opcode_ae_lq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc23004; -} - -static void -Opcode_ae_sq56s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f0080; -} - -static void -Opcode_ae_sq56s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc30004; -} - -static void -Opcode_ae_sq56s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f00c0; -} - -static void -Opcode_ae_sq56s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc38004; -} - -static void -Opcode_ae_sq56s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3000; -} - -static void -Opcode_ae_sq56s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc40004; -} - -static void -Opcode_ae_sq56s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3040; -} - -static void -Opcode_ae_sq56s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc48004; -} - -static void -Opcode_ae_sq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ec080; -} - -static void -Opcode_ae_sq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc34004; -} - -static void -Opcode_ae_sq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ec0c0; -} - -static void -Opcode_ae_sq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc3c004; -} - -static void -Opcode_ae_sq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f4000; -} - -static void -Opcode_ae_sq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc44004; -} - -static void -Opcode_ae_sq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f8000; -} - -static void -Opcode_ae_sq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc4c004; -} - -static void -Opcode_ae_zerop48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16b88; -} - -static void -Opcode_ae_movp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16808; -} - -static void -Opcode_ae_movp48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2400; -} - -static void -Opcode_ae_movp48_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90004; -} - -static void -Opcode_ae_selp24_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10780; -} - -static void -Opcode_ae_selp24_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2e00; -} - -static void -Opcode_ae_selp24_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10708; -} - -static void -Opcode_ae_selp24_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fa600; -} - -static void -Opcode_ae_selp24_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10688; -} - -static void -Opcode_ae_selp24_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fa200; -} - -static void -Opcode_ae_selp24_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10700; -} - -static void -Opcode_ae_selp24_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fa000; -} - -static void -Opcode_ae_movtp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c200; -} - -static void -Opcode_ae_movfp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c004; -} - -static void -Opcode_ae_movtp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10480; -} - -static void -Opcode_ae_movfp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10400; -} - -static void -Opcode_ae_movpa24x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1df000; -} - -static void -Opcode_ae_movpa24x2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc00004; -} - -static void -Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1eb080; -} - -static void -Opcode_ae_truncp24a32x2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc08004; -} - -static void -Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3081; -} - -static void -Opcode_ae_cvta32p24_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcb0004; -} - -static void -Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3080; -} - -static void -Opcode_ae_cvta32p24_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcb8004; -} - -static void -Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d8000; -} - -static void -Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbe0004; -} - -static void -Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d4000; -} - -static void -Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbe8004; -} - -static void -Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d2000; -} - -static void -Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbf0004; -} - -static void -Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d1000; -} - -static void -Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbf8004; -} - -static void -Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x51000; -} - -static void -Opcode_ae_truncp16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16b08; -} - -static void -Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e48; -} - -static void -Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e28; -} - -static void -Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e18; -} - -static void -Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e08; -} - -static void -Opcode_ae_roundsp16sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16908; -} - -static void -Opcode_ae_roundsp16asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16888; -} - -static void -Opcode_ae_zeroq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16085; -} - -static void -Opcode_ae_movq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16007; -} - -static void -Opcode_ae_movq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2500; -} - -static void -Opcode_ae_movq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90414; -} - -static void -Opcode_ae_movtq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f6000; -} - -static void -Opcode_ae_movtq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe50014; -} - -static void -Opcode_ae_movfq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5000; -} - -static void -Opcode_ae_movfq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe60014; -} - -static void -Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee030; -} - -static void -Opcode_ae_cvtq48a32s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe72034; -} - -static void -Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16006; -} - -static void -Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16005; -} - -static void -Opcode_ae_satq48s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50139; -} - -static void -Opcode_ae_truncq32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16047; -} - -static void -Opcode_ae_roundsq32sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16027; -} - -static void -Opcode_ae_roundsq32asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16017; -} - -static void -Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3086; -} - -static void -Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe70014; -} - -static void -Opcode_ae_movap24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3084; -} - -static void -Opcode_ae_movap24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc70004; -} - -static void -Opcode_ae_movap24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3082; -} - -static void -Opcode_ae_movap24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc78004; -} - -static void -Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3083; -} - -static void -Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc80004; -} - -static void -Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3088; -} - -static void -Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc88004; -} - -static void -Opcode_ae_addp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10500; -} - -static void -Opcode_ae_subp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10788; -} - -static void -Opcode_ae_negp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c600; -} - -static void -Opcode_ae_absp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c480; -} - -static void -Opcode_ae_maxp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10580; -} - -static void -Opcode_ae_minp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10588; -} - -static void -Opcode_ae_maxbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10000; -} - -static void -Opcode_ae_minbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10200; -} - -static void -Opcode_ae_addsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10600; -} - -static void -Opcode_ae_subsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c400; -} - -static void -Opcode_ae_negsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c488; -} - -static void -Opcode_ae_abssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c500; -} - -static void -Opcode_ae_andp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10508; -} - -static void -Opcode_ae_nandp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10608; -} - -static void -Opcode_ae_orp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10680; -} - -static void -Opcode_ae_xorp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c408; -} - -static void -Opcode_ae_ltp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c002; -} - -static void -Opcode_ae_lep24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c001; -} - -static void -Opcode_ae_eqp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c000; -} - -static void -Opcode_ae_addq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x52000; -} - -static void -Opcode_ae_subq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50035; -} - -static void -Opcode_ae_negq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5003c; -} - -static void -Opcode_ae_absq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50039; -} - -static void -Opcode_ae_maxq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50032; -} - -static void -Opcode_ae_minq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50034; -} - -static void -Opcode_ae_maxbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50000; -} - -static void -Opcode_ae_minbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50010; -} - -static void -Opcode_ae_addsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50030; -} - -static void -Opcode_ae_subsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50036; -} - -static void -Opcode_ae_negsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500b9; -} - -static void -Opcode_ae_abssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5003a; -} - -static void -Opcode_ae_andq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50031; -} - -static void -Opcode_ae_nandq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50038; -} - -static void -Opcode_ae_orq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50033; -} - -static void -Opcode_ae_xorq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50037; -} - -static void -Opcode_ae_sllip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x14000; -} - -static void -Opcode_ae_srlip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15000; -} - -static void -Opcode_ae_sraip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x14800; -} - -static void -Opcode_ae_sllsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16a08; -} - -static void -Opcode_ae_srlsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16a88; -} - -static void -Opcode_ae_srasp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16988; -} - -static void -Opcode_ae_sllisp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x18000; -} - -static void -Opcode_ae_sllssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16c08; -} - -static void -Opcode_ae_slliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1000; -} - -static void -Opcode_ae_slliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50004; -} - -static void -Opcode_ae_srliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1800; -} - -static void -Opcode_ae_srliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50404; -} - -static void -Opcode_ae_sraiq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1400; -} - -static void -Opcode_ae_sraiq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50804; -} - -static void -Opcode_ae_sllsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2600; -} - -static void -Opcode_ae_sllsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90014; -} - -static void -Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2504; -} - -static void -Opcode_ae_srlsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90114; -} - -static void -Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2502; -} - -static void -Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90214; -} - -static void -Opcode_ae_sllaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5001; -} - -static void -Opcode_ae_sllaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe10014; -} - -static void -Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5008; -} - -static void -Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe20014; -} - -static void -Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5004; -} - -static void -Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30014; -} - -static void -Opcode_ae_sllisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2000; -} - -static void -Opcode_ae_sllisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50c04; -} - -static void -Opcode_ae_sllssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2501; -} - -static void -Opcode_ae_sllssq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90314; -} - -static void -Opcode_ae_sllasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5002; -} - -static void -Opcode_ae_sllasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe40014; -} - -static void -Opcode_ae_ltq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50800; -} - -static void -Opcode_ae_leq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50040; -} - -static void -Opcode_ae_eqq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50020; -} - -static void -Opcode_ae_nsaq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3085; -} - -static void -Opcode_ae_nsaq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe74014; -} - -static void -Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19004; -} - -static void -Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19005; -} - -static void -Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19002; -} - -static void -Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19003; -} - -static void -Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19000; -} - -static void -Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19001; -} - -static void -Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1900a; -} - -static void -Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1900b; -} - -static void -Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19008; -} - -static void -Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19009; -} - -static void -Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19006; -} - -static void -Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19007; -} - -static void -Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60101; -} - -static void -Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008b; -} - -static void -Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60180; -} - -static void -Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008f; -} - -static void -Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008c; -} - -static void -Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60108; -} - -static void -Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008e; -} - -static void -Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008a; -} - -static void -Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60104; -} - -static void -Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008d; -} - -static void -Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60089; -} - -static void -Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60102; -} - -static void -Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60006; -} - -static void -Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64000; -} - -static void -Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000f; -} - -static void -Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60005; -} - -static void -Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60100; -} - -static void -Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000e; -} - -static void -Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60003; -} - -static void -Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60080; -} - -static void -Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000d; -} - -static void -Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x68000; -} - -static void -Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60008; -} - -static void -Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000b; -} - -static void -Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60181; -} - -static void -Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010b; -} - -static void -Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60189; -} - -static void -Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010f; -} - -static void -Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010c; -} - -static void -Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60187; -} - -static void -Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010e; -} - -static void -Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010a; -} - -static void -Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60186; -} - -static void -Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010d; -} - -static void -Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60109; -} - -static void -Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60185; -} - -static void -Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000c; -} - -static void -Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60088; -} - -static void -Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000a; -} - -static void -Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60084; -} - -static void -Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60009; -} - -static void -Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60082; -} - -static void -Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60007; -} - -static void -Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60081; -} - -static void -Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60183; -} - -static void -Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018d; -} - -static void -Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60188; -} - -static void -Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018b; -} - -static void -Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60184; -} - -static void -Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018c; -} - -static void -Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60182; -} - -static void -Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018a; -} - -static void -Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15807; -} - -static void -Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15806; -} - -static void -Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580a; -} - -static void -Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15809; -} - -static void -Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580b; -} - -static void -Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580c; -} - -static void -Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580e; -} - -static void -Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580d; -} - -static void -Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15800; -} - -static void -Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16000; -} - -static void -Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15802; -} - -static void -Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15801; -} - -static void -Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15808; -} - -static void -Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15804; -} - -static void -Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15805; -} - -static void -Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15803; -} - -static void -Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16001; -} - -static void -Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580f; -} - -static void -Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16004; -} - -static void -Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16002; -} - -static void -Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16800; -} - -static void -Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16008; -} - -static void -Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16003; -} - -static void -Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x17000; -} - -static void -Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20007; -} - -static void -Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20002; -} - -static void -Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000c; -} - -static void -Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20003; -} - -static void -Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20005; -} - -static void -Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20000; -} - -static void -Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20009; -} - -static void -Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20004; -} - -static void -Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20006; -} - -static void -Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20001; -} - -static void -Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000a; -} - -static void -Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20008; -} - -static void -Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30008; -} - -static void -Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000e; -} - -static void -Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30006; -} - -static void -Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30001; -} - -static void -Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30002; -} - -static void -Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000b; -} - -static void -Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30003; -} - -static void -Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000f; -} - -static void -Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30004; -} - -static void -Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000d; -} - -static void -Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30005; -} - -static void -Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000; -} - -static void -Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000; -} - -static void -Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000a; -} - -static void -Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40004; -} - -static void -Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000d; -} - -static void -Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000e; -} - -static void -Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30007; -} - -static void -Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40001; -} - -static void -Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000c; -} - -static void -Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000f; -} - -static void -Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30009; -} - -static void -Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40002; -} - -static void -Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000b; -} - -static void -Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000b; -} - -static void -Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40005; -} - -static void -Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000f; -} - -static void -Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40009; -} - -static void -Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000a; -} - -static void -Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40008; -} - -static void -Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000d; -} - -static void -Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40006; -} - -static void -Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000c; -} - -static void -Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40003; -} - -static void -Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000e; -} - -static void -Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40007; -} - -static void -Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64004; -} - -static void -Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64080; -} - -static void -Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64008; -} - -static void -Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64100; -} - -static void -Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64003; -} - -static void -Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64006; -} - -static void -Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64005; -} - -static void -Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64007; -} - -static void -Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64009; -} - -static void -Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400c; -} - -static void -Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400a; -} - -static void -Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400b; -} - -static void -Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400d; -} - -static void -Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400f; -} - -static void -Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400e; -} - -static void -Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64081; -} - -static void -Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60000; -} - -static void -Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60002; -} - -static void -Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60001; -} - -static void -Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60004; -} - -static void -Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60083; -} - -static void -Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60086; -} - -static void -Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60085; -} - -static void -Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60087; -} - -static void -Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60103; -} - -static void -Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60106; -} - -static void -Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60105; -} - -static void -Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60107; -} - -static void -Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018e; -} - -static void -Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64001; -} - -static void -Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018f; -} - -static void -Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64002; -} - -static void -Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00014; -} - -static void -Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00004; -} - -static void -Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa10004; -} - -static void -Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe7e014; -} - -static void -Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca8004; -} - -static void -Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc60004; -} - -static void -Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00024; -} - -static void -Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa20004; -} - -static void -Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00004; -} - -static void -Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf01004; -} - -static void -Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf02004; -} - -static void -Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa30004; -} - -static void -Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa40004; -} - -static void -Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf11004; -} - -static void -Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00004; -} - -static void -Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe7c014; -} - -static void -Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe7d014; -} - -static void -Opcode_ae_slaasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f6008; -} - -static void -Opcode_ae_addbrba32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f7000; -} - -static void -Opcode_ae_minabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c508; -} - -static void -Opcode_ae_maxabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c580; -} - -static void -Opcode_ae_minabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x52004; -} - -static void -Opcode_ae_maxabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x52008; -} - -static void -Opcode_rur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f60; -} - -static void -Opcode_wur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f600; -} - -static void -Opcode_rur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f70; -} - -static void -Opcode_wur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f700; -} - -static void -Opcode_ae_lp24x2_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fe080; -} - -static void -Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900000; -} - -static void -Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ff000; -} - -static void -Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800000; -} - -static void -Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f4080; -} - -static void -Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0; -} - -static void -Opcode_ae_lp24_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fc080; -} - -static void -Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700000; -} - -static void -Opcode_ae_lp24f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fe000; -} - -static void -Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600000; -} - -static void -Opcode_ae_lp16f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fc000; -} - -static void -Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ff080; -} - -static void -Opcode_ae_lq56_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00000; -} - -static void -Opcode_ae_sq56s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f8080; -} - -static void -Opcode_ae_lq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef010; -} - -static void -Opcode_ae_sq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f8040; -} - -xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { - Opcode_excw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { - Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { - Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { - Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { - Opcode_call12_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { - Opcode_call8_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { - Opcode_call4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { - Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { - Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { - Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { - Opcode_entry_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { - Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { - Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { - Opcode_retw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { - 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { - Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { - Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { - Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { - Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { - Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { - Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { - Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { - Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { - Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { - Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { - 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { - 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { - 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { - 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { - 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { - 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { - 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { - 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { - 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { - 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { - 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { - Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { - Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { - Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { - Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { - Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { - Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { - Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { - Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { - Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { - Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { - Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { - Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { - Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { - Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { - Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { - Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { - Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { - Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { - Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { - Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { - Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { - Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { - Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { - Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { - Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { - Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { - Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { - Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { - Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { - Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { - Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { - Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { - Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { - Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { - Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { - Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { - Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { - Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { - Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { - Opcode_call0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { - Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { - Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { - Opcode_ill_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { - Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { - Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { - Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { - Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { - Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { - Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { - Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { - Opcode_loop_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { - Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { - Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { - Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { - Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { - Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { - Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { - Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { - Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { - Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { - Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { - Opcode_ret_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { - Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { - Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { - Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { - Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { - Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { - Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { - Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { - Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { - Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { - Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { - Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { - Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { - Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { - Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { - Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { - Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { - Opcode_memw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { - Opcode_extw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { - Opcode_isync_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { - Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { - Opcode_esync_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { - Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { - Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { - Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { - Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { - Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { - Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { - Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { - Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { - Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { - Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { - Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { - Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { - Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { - Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { - Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { - Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { - Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { - Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { - Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { - Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_243_encode_fns[] = { - Opcode_rsr_243_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { - Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { - Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { - Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { - Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { - Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { - Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { - Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { - Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { - Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { - Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { - Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { - Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { - Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { - Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { - Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { - Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { - Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { - Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { - Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { - Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { - Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { - Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { - Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { - Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { - Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { - Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { - Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { - Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { - Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { - Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { - Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { - Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { - Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { - Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { - Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { - Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { - Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { - Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { - Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { - Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { - Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { - Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { - Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { - Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { - Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { - Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { - Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { - Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { - Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { - Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { - Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { - Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { - Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { - Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { - Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { - Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { - Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { - Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { - Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { - Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { - Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { - Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { - Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { - Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { - Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { - Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { - Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { - Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { - Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { - Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { - Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { - Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { - Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { - Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { - Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { - Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { - Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { - Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { - Opcode_mull_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = { - Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = { - Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { - Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { - Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { - Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { - Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { - Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { - Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { - Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { - Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { - Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { - Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { - Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { - Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { - Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { - Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { - Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { - Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { - Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { - Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { - Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { - Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { - Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { - Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { - Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { - Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { - Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { - Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { - Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { - Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { - Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { - Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { - Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { - Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { - Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { - Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { - Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { - Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { - Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { - Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { - Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { - Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { - Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { - Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { - Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { - Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { - Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { - Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { - Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { - Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { - Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { - Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { - Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { - Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { - Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { - Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { - Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { - Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { - Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { - Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { - Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { - Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { - Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { - Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { - Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { - Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { - Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { - Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { - Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { - Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { - Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { - Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { - Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { - Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { - Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { - Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { - Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { - Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { - Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { - Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { - Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { - Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { - Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { - Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { - Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { - Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { - Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { - Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { - Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { - Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { - Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { - Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { - Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { - Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { - Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { - Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { - Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { - Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { - Opcode_break_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { - 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { - Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { - Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { - Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { - Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { - Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { - Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { - Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { - Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { - Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { - Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { - Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { - Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { - Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { - Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { - Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { - Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { - Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { - Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { - Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { - Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { - Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { - Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { - Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { - Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { - Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { - Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { - Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { - Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { - Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { - Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { - Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { - Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { - Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { - Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { - Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { - Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { - Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { - Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { - Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { - Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { - Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { - Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { - Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { - Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { - Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { - Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { - Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { - Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { - Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { - Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { - Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { - Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { - Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { - Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { - Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { - Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { - Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { - Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { - Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { - Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { - Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { - Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { - Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { - Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { - Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { - Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { - Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { - Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { - Opcode_iii_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { - Opcode_lict_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { - Opcode_licw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { - Opcode_sict_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { - Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { - Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { - Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { - Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { - Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { - Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { - Opcode_dii_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { - Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { - Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { - Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { - Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { - Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { - Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { - Opcode_diu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { - Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { - Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_prefctl_encode_fns[] = { - Opcode_rsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_prefctl_encode_fns[] = { - Opcode_wsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_prefctl_encode_fns[] = { - Opcode_xsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { - Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { - Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { - Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { - Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { - Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { - Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { - Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { - Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { - Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { - Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { - Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { - Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { - Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { - Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { - Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { - Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { - Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { - Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { - Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { - Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { - Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { - Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { - Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { - Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { - Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { - Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { - Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { - Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { - Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { - Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { - Opcode_rer_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { - Opcode_wer_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { - Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { - Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { - Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { - Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { - Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { - Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = { - Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = { - Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { - Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { - Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { - Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { - Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { - Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { - Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { - Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { - Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { - Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { - Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { - Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { - Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { - Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { - Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { - Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { - Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = { - Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = { - Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = { - Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = { - Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = { - Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = { - Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = { - Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = { - Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = { - Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = { - Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = { - Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = { - Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = { - Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = { - Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = { - Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = { - Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = { - Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = { - Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = { - Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = { - Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = { - Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = { - Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = { - Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = { - Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = { - Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = { - Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = { - Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = { - Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = { - Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = { - Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = { - Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = { - Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = { - Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = { - Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = { - Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = { - Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = { - Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = { - Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = { - Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = { - Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = { - Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = { - Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = { - Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = { - Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = { - Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = { - Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = { - Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = { - Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = { - Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = { - Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = { - Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = { - Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = { - Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = { - Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = { - Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = { - Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = { - Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = { - Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = { - Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = { - Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = { - Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = { - Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = { - Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = { - Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = { - 0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = { - Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, Opcode_ae_selp24_ll_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, Opcode_ae_selp24_lh_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, Opcode_ae_selp24_hl_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, Opcode_ae_selp24_hh_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = { - Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { - Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = { - Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = { - Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { - Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { - Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { - Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { - Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = { - Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = { - Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = { - Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = { - Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = { - 0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { - Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = { - Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = { - Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { - Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { - Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = { - Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = { - Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = { - Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = { - Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { - Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { - Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = { - Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { - Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { - Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = { - Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = { - Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = { - Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = { - Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { - Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { - Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { - Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { - Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { - Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { - Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { - Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { - Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { - Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { - Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { - Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { - Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { - Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { - Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { - Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { - Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { - Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_slaasq56s_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_addbrba32_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_minabssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minabssp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxabssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxabssp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minabssq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minabssq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxabssq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxabssq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_cbegin0_encode_fns[] = { - Opcode_rur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_cbegin0_encode_fns[] = { - Opcode_wur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_cend0_encode_fns[] = { - Opcode_rur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_cend0_encode_fns[] = { - Opcode_wur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24x2_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp16f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lq56_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sq56s_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lq32f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sq32f_c_Slot_ae_slot0_encode -}; - - -/* Opcode table. */ - -static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 4 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 4 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 3 }, - { FUNCUNIT_ae_shift32x5, 4 }, - { FUNCUNIT_ae_add32, 4 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 3 }, - { FUNCUNIT_ae_shift32x5, 4 }, - { FUNCUNIT_ae_add32, 4 } -}; - -static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 3 }, - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 3 }, - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 4 } -}; - -static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 4 } -}; - -static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 3 }, - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 3 }, - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 3 }, - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 3 }, - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_opcode_internal opcodes[] = { - { "excw", ICLASS_xt_iclass_excw, - 0, - Opcode_excw_encode_fns, 0, 0 }, - { "rfe", ICLASS_xt_iclass_rfe, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfe_encode_fns, 0, 0 }, - { "rfde", ICLASS_xt_iclass_rfde, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfde_encode_fns, 0, 0 }, - { "syscall", ICLASS_xt_iclass_syscall, - 0, - Opcode_syscall_encode_fns, 0, 0 }, - { "call12", ICLASS_xt_iclass_call12, - XTENSA_OPCODE_IS_CALL, - Opcode_call12_encode_fns, 0, 0 }, - { "call8", ICLASS_xt_iclass_call8, - XTENSA_OPCODE_IS_CALL, - Opcode_call8_encode_fns, 0, 0 }, - { "call4", ICLASS_xt_iclass_call4, - XTENSA_OPCODE_IS_CALL, - Opcode_call4_encode_fns, 0, 0 }, - { "callx12", ICLASS_xt_iclass_callx12, - XTENSA_OPCODE_IS_CALL, - Opcode_callx12_encode_fns, 0, 0 }, - { "callx8", ICLASS_xt_iclass_callx8, - XTENSA_OPCODE_IS_CALL, - Opcode_callx8_encode_fns, 0, 0 }, - { "callx4", ICLASS_xt_iclass_callx4, - XTENSA_OPCODE_IS_CALL, - Opcode_callx4_encode_fns, 0, 0 }, - { "entry", ICLASS_xt_iclass_entry, - 0, - Opcode_entry_encode_fns, 0, 0 }, - { "movsp", ICLASS_xt_iclass_movsp, - 0, - Opcode_movsp_encode_fns, 0, 0 }, - { "rotw", ICLASS_xt_iclass_rotw, - 0, - Opcode_rotw_encode_fns, 0, 0 }, - { "retw", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_encode_fns, 0, 0 }, - { "retw.n", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_n_encode_fns, 0, 0 }, - { "rfwo", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwo_encode_fns, 0, 0 }, - { "rfwu", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwu_encode_fns, 0, 0 }, - { "l32e", ICLASS_xt_iclass_l32e, - 0, - Opcode_l32e_encode_fns, 0, 0 }, - { "s32e", ICLASS_xt_iclass_s32e, - 0, - Opcode_s32e_encode_fns, 0, 0 }, - { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, - 0, - Opcode_rsr_windowbase_encode_fns, 0, 0 }, - { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, - 0, - Opcode_wsr_windowbase_encode_fns, 0, 0 }, - { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, - 0, - Opcode_xsr_windowbase_encode_fns, 0, 0 }, - { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, - 0, - Opcode_rsr_windowstart_encode_fns, 0, 0 }, - { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, - 0, - Opcode_wsr_windowstart_encode_fns, 0, 0 }, - { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, - 0, - Opcode_xsr_windowstart_encode_fns, 0, 0 }, - { "add.n", ICLASS_xt_iclass_add_n, - 0, - Opcode_add_n_encode_fns, 0, 0 }, - { "addi.n", ICLASS_xt_iclass_addi_n, - 0, - Opcode_addi_n_encode_fns, 0, 0 }, - { "beqz.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_n_encode_fns, 0, 0 }, - { "bnez.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_n_encode_fns, 0, 0 }, - { "ill.n", ICLASS_xt_iclass_ill_n, - 0, - Opcode_ill_n_encode_fns, 0, 0 }, - { "l32i.n", ICLASS_xt_iclass_loadi4, - 0, - Opcode_l32i_n_encode_fns, 0, 0 }, - { "mov.n", ICLASS_xt_iclass_mov_n, - 0, - Opcode_mov_n_encode_fns, 0, 0 }, - { "movi.n", ICLASS_xt_iclass_movi_n, - 0, - Opcode_movi_n_encode_fns, 0, 0 }, - { "nop.n", ICLASS_xt_iclass_nopn, - 0, - Opcode_nop_n_encode_fns, 0, 0 }, - { "ret.n", ICLASS_xt_iclass_retn, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_n_encode_fns, 0, 0 }, - { "s32i.n", ICLASS_xt_iclass_storei4, - 0, - Opcode_s32i_n_encode_fns, 0, 0 }, - { "rur.threadptr", ICLASS_rur_threadptr, - 0, - Opcode_rur_threadptr_encode_fns, 0, 0 }, - { "wur.threadptr", ICLASS_wur_threadptr, - 0, - Opcode_wur_threadptr_encode_fns, 0, 0 }, - { "addi", ICLASS_xt_iclass_addi, - 0, - Opcode_addi_encode_fns, 0, 0 }, - { "addmi", ICLASS_xt_iclass_addmi, - 0, - Opcode_addmi_encode_fns, 0, 0 }, - { "add", ICLASS_xt_iclass_addsub, - 0, - Opcode_add_encode_fns, 0, 0 }, - { "sub", ICLASS_xt_iclass_addsub, - 0, - Opcode_sub_encode_fns, 0, 0 }, - { "addx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx2_encode_fns, 0, 0 }, - { "addx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx4_encode_fns, 0, 0 }, - { "addx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx8_encode_fns, 0, 0 }, - { "subx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx2_encode_fns, 0, 0 }, - { "subx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx4_encode_fns, 0, 0 }, - { "subx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx8_encode_fns, 0, 0 }, - { "and", ICLASS_xt_iclass_bit, - 0, - Opcode_and_encode_fns, 0, 0 }, - { "or", ICLASS_xt_iclass_bit, - 0, - Opcode_or_encode_fns, 0, 0 }, - { "xor", ICLASS_xt_iclass_bit, - 0, - Opcode_xor_encode_fns, 0, 0 }, - { "beqi", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqi_encode_fns, 0, 0 }, - { "bnei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnei_encode_fns, 0, 0 }, - { "bgei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgei_encode_fns, 0, 0 }, - { "blti", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blti_encode_fns, 0, 0 }, - { "bbci", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbci_encode_fns, 0, 0 }, - { "bbsi", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbsi_encode_fns, 0, 0 }, - { "bgeui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeui_encode_fns, 0, 0 }, - { "bltui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltui_encode_fns, 0, 0 }, - { "beq", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beq_encode_fns, 0, 0 }, - { "bne", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bne_encode_fns, 0, 0 }, - { "bge", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bge_encode_fns, 0, 0 }, - { "blt", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blt_encode_fns, 0, 0 }, - { "bgeu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeu_encode_fns, 0, 0 }, - { "bltu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltu_encode_fns, 0, 0 }, - { "bany", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bany_encode_fns, 0, 0 }, - { "bnone", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnone_encode_fns, 0, 0 }, - { "ball", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_ball_encode_fns, 0, 0 }, - { "bnall", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnall_encode_fns, 0, 0 }, - { "bbc", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbc_encode_fns, 0, 0 }, - { "bbs", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbs_encode_fns, 0, 0 }, - { "beqz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_encode_fns, 0, 0 }, - { "bnez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_encode_fns, 0, 0 }, - { "bgez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgez_encode_fns, 0, 0 }, - { "bltz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltz_encode_fns, 0, 0 }, - { "call0", ICLASS_xt_iclass_call0, - XTENSA_OPCODE_IS_CALL, - Opcode_call0_encode_fns, 0, 0 }, - { "callx0", ICLASS_xt_iclass_callx0, - XTENSA_OPCODE_IS_CALL, - Opcode_callx0_encode_fns, 0, 0 }, - { "extui", ICLASS_xt_iclass_exti, - 0, - Opcode_extui_encode_fns, 0, 0 }, - { "ill", ICLASS_xt_iclass_ill, - 0, - Opcode_ill_encode_fns, 0, 0 }, - { "j", ICLASS_xt_iclass_jump, - XTENSA_OPCODE_IS_JUMP, - Opcode_j_encode_fns, 0, 0 }, - { "jx", ICLASS_xt_iclass_jumpx, - XTENSA_OPCODE_IS_JUMP, - Opcode_jx_encode_fns, 0, 0 }, - { "l16ui", ICLASS_xt_iclass_l16ui, - 0, - Opcode_l16ui_encode_fns, 0, 0 }, - { "l16si", ICLASS_xt_iclass_l16si, - 0, - Opcode_l16si_encode_fns, 0, 0 }, - { "l32i", ICLASS_xt_iclass_l32i, - 0, - Opcode_l32i_encode_fns, 0, 0 }, - { "l32r", ICLASS_xt_iclass_l32r, - 0, - Opcode_l32r_encode_fns, 0, 0 }, - { "l8ui", ICLASS_xt_iclass_l8i, - 0, - Opcode_l8ui_encode_fns, 0, 0 }, - { "loop", ICLASS_xt_iclass_loop, - XTENSA_OPCODE_IS_LOOP, - Opcode_loop_encode_fns, 0, 0 }, - { "loopnez", ICLASS_xt_iclass_loopz, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopnez_encode_fns, 0, 0 }, - { "loopgtz", ICLASS_xt_iclass_loopz, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopgtz_encode_fns, 0, 0 }, - { "movi", ICLASS_xt_iclass_movi, - 0, - Opcode_movi_encode_fns, 0, 0 }, - { "moveqz", ICLASS_xt_iclass_movz, - 0, - Opcode_moveqz_encode_fns, 0, 0 }, - { "movnez", ICLASS_xt_iclass_movz, - 0, - Opcode_movnez_encode_fns, 0, 0 }, - { "movltz", ICLASS_xt_iclass_movz, - 0, - Opcode_movltz_encode_fns, 0, 0 }, - { "movgez", ICLASS_xt_iclass_movz, - 0, - Opcode_movgez_encode_fns, 0, 0 }, - { "neg", ICLASS_xt_iclass_neg, - 0, - Opcode_neg_encode_fns, 0, 0 }, - { "abs", ICLASS_xt_iclass_neg, - 0, - Opcode_abs_encode_fns, 0, 0 }, - { "nop", ICLASS_xt_iclass_nop, - 0, - Opcode_nop_encode_fns, 0, 0 }, - { "ret", ICLASS_xt_iclass_return, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_encode_fns, 0, 0 }, - { "simcall", ICLASS_xt_iclass_simcall, - 0, - Opcode_simcall_encode_fns, 0, 0 }, - { "s16i", ICLASS_xt_iclass_s16i, - 0, - Opcode_s16i_encode_fns, 0, 0 }, - { "s32i", ICLASS_xt_iclass_s32i, - 0, - Opcode_s32i_encode_fns, 0, 0 }, - { "s8i", ICLASS_xt_iclass_s8i, - 0, - Opcode_s8i_encode_fns, 0, 0 }, - { "ssr", ICLASS_xt_iclass_sar, - 0, - Opcode_ssr_encode_fns, 0, 0 }, - { "ssl", ICLASS_xt_iclass_sar, - 0, - Opcode_ssl_encode_fns, 0, 0 }, - { "ssa8l", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8l_encode_fns, 0, 0 }, - { "ssa8b", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8b_encode_fns, 0, 0 }, - { "ssai", ICLASS_xt_iclass_sari, - 0, - Opcode_ssai_encode_fns, 0, 0 }, - { "sll", ICLASS_xt_iclass_shifts, - 0, - Opcode_sll_encode_fns, 0, 0 }, - { "src", ICLASS_xt_iclass_shiftst, - 0, - Opcode_src_encode_fns, 0, 0 }, - { "srl", ICLASS_xt_iclass_shiftt, - 0, - Opcode_srl_encode_fns, 0, 0 }, - { "sra", ICLASS_xt_iclass_shiftt, - 0, - Opcode_sra_encode_fns, 0, 0 }, - { "slli", ICLASS_xt_iclass_slli, - 0, - Opcode_slli_encode_fns, 0, 0 }, - { "srai", ICLASS_xt_iclass_srai, - 0, - Opcode_srai_encode_fns, 0, 0 }, - { "srli", ICLASS_xt_iclass_srli, - 0, - Opcode_srli_encode_fns, 0, 0 }, - { "memw", ICLASS_xt_iclass_memw, - 0, - Opcode_memw_encode_fns, 0, 0 }, - { "extw", ICLASS_xt_iclass_extw, - 0, - Opcode_extw_encode_fns, 0, 0 }, - { "isync", ICLASS_xt_iclass_isync, - 0, - Opcode_isync_encode_fns, 0, 0 }, - { "rsync", ICLASS_xt_iclass_sync, - 0, - Opcode_rsync_encode_fns, 0, 0 }, - { "esync", ICLASS_xt_iclass_sync, - 0, - Opcode_esync_encode_fns, 0, 0 }, - { "dsync", ICLASS_xt_iclass_sync, - 0, - Opcode_dsync_encode_fns, 0, 0 }, - { "rsil", ICLASS_xt_iclass_rsil, - 0, - Opcode_rsil_encode_fns, 0, 0 }, - { "rsr.lend", ICLASS_xt_iclass_rsr_lend, - 0, - Opcode_rsr_lend_encode_fns, 0, 0 }, - { "wsr.lend", ICLASS_xt_iclass_wsr_lend, - 0, - Opcode_wsr_lend_encode_fns, 0, 0 }, - { "xsr.lend", ICLASS_xt_iclass_xsr_lend, - 0, - Opcode_xsr_lend_encode_fns, 0, 0 }, - { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, - 0, - Opcode_rsr_lcount_encode_fns, 0, 0 }, - { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, - 0, - Opcode_wsr_lcount_encode_fns, 0, 0 }, - { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, - 0, - Opcode_xsr_lcount_encode_fns, 0, 0 }, - { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, - 0, - Opcode_rsr_lbeg_encode_fns, 0, 0 }, - { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, - 0, - Opcode_wsr_lbeg_encode_fns, 0, 0 }, - { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, - 0, - Opcode_xsr_lbeg_encode_fns, 0, 0 }, - { "rsr.sar", ICLASS_xt_iclass_rsr_sar, - 0, - Opcode_rsr_sar_encode_fns, 0, 0 }, - { "wsr.sar", ICLASS_xt_iclass_wsr_sar, - 0, - Opcode_wsr_sar_encode_fns, 0, 0 }, - { "xsr.sar", ICLASS_xt_iclass_xsr_sar, - 0, - Opcode_xsr_sar_encode_fns, 0, 0 }, - { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, - 0, - Opcode_rsr_litbase_encode_fns, 0, 0 }, - { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, - 0, - Opcode_wsr_litbase_encode_fns, 0, 0 }, - { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, - 0, - Opcode_xsr_litbase_encode_fns, 0, 0 }, - { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, - 0, - Opcode_rsr_configid0_encode_fns, 0, 0 }, - { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, - 0, - Opcode_wsr_configid0_encode_fns, 0, 0 }, - { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, - 0, - Opcode_rsr_configid1_encode_fns, 0, 0 }, - { "rsr.243", ICLASS_xt_iclass_rsr_243, - 0, - Opcode_rsr_243_encode_fns, 0, 0 }, - { "rsr.ps", ICLASS_xt_iclass_rsr_ps, - 0, - Opcode_rsr_ps_encode_fns, 0, 0 }, - { "wsr.ps", ICLASS_xt_iclass_wsr_ps, - 0, - Opcode_wsr_ps_encode_fns, 0, 0 }, - { "xsr.ps", ICLASS_xt_iclass_xsr_ps, - 0, - Opcode_xsr_ps_encode_fns, 0, 0 }, - { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, - 0, - Opcode_rsr_epc1_encode_fns, 0, 0 }, - { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, - 0, - Opcode_wsr_epc1_encode_fns, 0, 0 }, - { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, - 0, - Opcode_xsr_epc1_encode_fns, 0, 0 }, - { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, - 0, - Opcode_rsr_excsave1_encode_fns, 0, 0 }, - { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, - 0, - Opcode_wsr_excsave1_encode_fns, 0, 0 }, - { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, - 0, - Opcode_xsr_excsave1_encode_fns, 0, 0 }, - { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, - 0, - Opcode_rsr_epc2_encode_fns, 0, 0 }, - { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, - 0, - Opcode_wsr_epc2_encode_fns, 0, 0 }, - { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, - 0, - Opcode_xsr_epc2_encode_fns, 0, 0 }, - { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, - 0, - Opcode_rsr_excsave2_encode_fns, 0, 0 }, - { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, - 0, - Opcode_wsr_excsave2_encode_fns, 0, 0 }, - { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, - 0, - Opcode_xsr_excsave2_encode_fns, 0, 0 }, - { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, - 0, - Opcode_rsr_epc3_encode_fns, 0, 0 }, - { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, - 0, - Opcode_wsr_epc3_encode_fns, 0, 0 }, - { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, - 0, - Opcode_xsr_epc3_encode_fns, 0, 0 }, - { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, - 0, - Opcode_rsr_excsave3_encode_fns, 0, 0 }, - { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, - 0, - Opcode_wsr_excsave3_encode_fns, 0, 0 }, - { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, - 0, - Opcode_xsr_excsave3_encode_fns, 0, 0 }, - { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, - 0, - Opcode_rsr_epc4_encode_fns, 0, 0 }, - { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, - 0, - Opcode_wsr_epc4_encode_fns, 0, 0 }, - { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, - 0, - Opcode_xsr_epc4_encode_fns, 0, 0 }, - { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, - 0, - Opcode_rsr_excsave4_encode_fns, 0, 0 }, - { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, - 0, - Opcode_wsr_excsave4_encode_fns, 0, 0 }, - { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, - 0, - Opcode_xsr_excsave4_encode_fns, 0, 0 }, - { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, - 0, - Opcode_rsr_epc5_encode_fns, 0, 0 }, - { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, - 0, - Opcode_wsr_epc5_encode_fns, 0, 0 }, - { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, - 0, - Opcode_xsr_epc5_encode_fns, 0, 0 }, - { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, - 0, - Opcode_rsr_excsave5_encode_fns, 0, 0 }, - { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, - 0, - Opcode_wsr_excsave5_encode_fns, 0, 0 }, - { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, - 0, - Opcode_xsr_excsave5_encode_fns, 0, 0 }, - { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, - 0, - Opcode_rsr_epc6_encode_fns, 0, 0 }, - { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, - 0, - Opcode_wsr_epc6_encode_fns, 0, 0 }, - { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, - 0, - Opcode_xsr_epc6_encode_fns, 0, 0 }, - { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, - 0, - Opcode_rsr_excsave6_encode_fns, 0, 0 }, - { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, - 0, - Opcode_wsr_excsave6_encode_fns, 0, 0 }, - { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, - 0, - Opcode_xsr_excsave6_encode_fns, 0, 0 }, - { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, - 0, - Opcode_rsr_epc7_encode_fns, 0, 0 }, - { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, - 0, - Opcode_wsr_epc7_encode_fns, 0, 0 }, - { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, - 0, - Opcode_xsr_epc7_encode_fns, 0, 0 }, - { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, - 0, - Opcode_rsr_excsave7_encode_fns, 0, 0 }, - { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, - 0, - Opcode_wsr_excsave7_encode_fns, 0, 0 }, - { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, - 0, - Opcode_xsr_excsave7_encode_fns, 0, 0 }, - { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, - 0, - Opcode_rsr_eps2_encode_fns, 0, 0 }, - { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, - 0, - Opcode_wsr_eps2_encode_fns, 0, 0 }, - { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, - 0, - Opcode_xsr_eps2_encode_fns, 0, 0 }, - { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, - 0, - Opcode_rsr_eps3_encode_fns, 0, 0 }, - { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, - 0, - Opcode_wsr_eps3_encode_fns, 0, 0 }, - { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, - 0, - Opcode_xsr_eps3_encode_fns, 0, 0 }, - { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, - 0, - Opcode_rsr_eps4_encode_fns, 0, 0 }, - { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, - 0, - Opcode_wsr_eps4_encode_fns, 0, 0 }, - { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, - 0, - Opcode_xsr_eps4_encode_fns, 0, 0 }, - { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, - 0, - Opcode_rsr_eps5_encode_fns, 0, 0 }, - { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, - 0, - Opcode_wsr_eps5_encode_fns, 0, 0 }, - { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, - 0, - Opcode_xsr_eps5_encode_fns, 0, 0 }, - { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, - 0, - Opcode_rsr_eps6_encode_fns, 0, 0 }, - { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, - 0, - Opcode_wsr_eps6_encode_fns, 0, 0 }, - { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, - 0, - Opcode_xsr_eps6_encode_fns, 0, 0 }, - { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, - 0, - Opcode_rsr_eps7_encode_fns, 0, 0 }, - { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, - 0, - Opcode_wsr_eps7_encode_fns, 0, 0 }, - { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, - 0, - Opcode_xsr_eps7_encode_fns, 0, 0 }, - { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, - 0, - Opcode_rsr_excvaddr_encode_fns, 0, 0 }, - { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, - 0, - Opcode_wsr_excvaddr_encode_fns, 0, 0 }, - { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, - 0, - Opcode_xsr_excvaddr_encode_fns, 0, 0 }, - { "rsr.depc", ICLASS_xt_iclass_rsr_depc, - 0, - Opcode_rsr_depc_encode_fns, 0, 0 }, - { "wsr.depc", ICLASS_xt_iclass_wsr_depc, - 0, - Opcode_wsr_depc_encode_fns, 0, 0 }, - { "xsr.depc", ICLASS_xt_iclass_xsr_depc, - 0, - Opcode_xsr_depc_encode_fns, 0, 0 }, - { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, - 0, - Opcode_rsr_exccause_encode_fns, 0, 0 }, - { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, - 0, - Opcode_wsr_exccause_encode_fns, 0, 0 }, - { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, - 0, - Opcode_xsr_exccause_encode_fns, 0, 0 }, - { "rsr.prid", ICLASS_xt_iclass_rsr_prid, - 0, - Opcode_rsr_prid_encode_fns, 0, 0 }, - { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, - 0, - Opcode_rsr_vecbase_encode_fns, 0, 0 }, - { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, - 0, - Opcode_wsr_vecbase_encode_fns, 0, 0 }, - { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, - 0, - Opcode_xsr_vecbase_encode_fns, 0, 0 }, - { "mul16u", ICLASS_xt_mul16, - 0, - Opcode_mul16u_encode_fns, 0, 0 }, - { "mul16s", ICLASS_xt_mul16, - 0, - Opcode_mul16s_encode_fns, 0, 0 }, - { "mull", ICLASS_xt_mul32, - 0, - Opcode_mull_encode_fns, 0, 0 }, - { "muluh", ICLASS_xt_mul32h, - 0, - Opcode_muluh_encode_fns, 0, 0 }, - { "mulsh", ICLASS_xt_mul32h, - 0, - Opcode_mulsh_encode_fns, 0, 0 }, - { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_ll_encode_fns, 0, 0 }, - { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_hl_encode_fns, 0, 0 }, - { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_lh_encode_fns, 0, 0 }, - { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_hh_encode_fns, 0, 0 }, - { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_ll_encode_fns, 0, 0 }, - { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_hl_encode_fns, 0, 0 }, - { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_lh_encode_fns, 0, 0 }, - { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_hh_encode_fns, 0, 0 }, - { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_ll_encode_fns, 0, 0 }, - { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_hl_encode_fns, 0, 0 }, - { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_lh_encode_fns, 0, 0 }, - { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_hh_encode_fns, 0, 0 }, - { "mul.da.ll", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_ll_encode_fns, 0, 0 }, - { "mul.da.hl", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_hl_encode_fns, 0, 0 }, - { "mul.da.lh", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_lh_encode_fns, 0, 0 }, - { "mul.da.hh", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_hh_encode_fns, 0, 0 }, - { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_ll_encode_fns, 0, 0 }, - { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_hl_encode_fns, 0, 0 }, - { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_lh_encode_fns, 0, 0 }, - { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_hh_encode_fns, 0, 0 }, - { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_ll_encode_fns, 0, 0 }, - { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_hl_encode_fns, 0, 0 }, - { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_lh_encode_fns, 0, 0 }, - { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_hh_encode_fns, 0, 0 }, - { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_ll_encode_fns, 0, 0 }, - { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_hl_encode_fns, 0, 0 }, - { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_lh_encode_fns, 0, 0 }, - { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_hh_encode_fns, 0, 0 }, - { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_ll_encode_fns, 0, 0 }, - { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_hl_encode_fns, 0, 0 }, - { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_lh_encode_fns, 0, 0 }, - { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_hh_encode_fns, 0, 0 }, - { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_ll_encode_fns, 0, 0 }, - { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_hl_encode_fns, 0, 0 }, - { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_lh_encode_fns, 0, 0 }, - { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_hh_encode_fns, 0, 0 }, - { "mula.da.ll", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_ll_encode_fns, 0, 0 }, - { "mula.da.hl", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_hl_encode_fns, 0, 0 }, - { "mula.da.lh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_lh_encode_fns, 0, 0 }, - { "mula.da.hh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_hh_encode_fns, 0, 0 }, - { "muls.da.ll", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_ll_encode_fns, 0, 0 }, - { "muls.da.hl", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_hl_encode_fns, 0, 0 }, - { "muls.da.lh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_lh_encode_fns, 0, 0 }, - { "muls.da.hh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_hh_encode_fns, 0, 0 }, - { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_ll_encode_fns, 0, 0 }, - { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_hl_encode_fns, 0, 0 }, - { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_lh_encode_fns, 0, 0 }, - { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_hh_encode_fns, 0, 0 }, - { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_ll_encode_fns, 0, 0 }, - { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_hl_encode_fns, 0, 0 }, - { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_lh_encode_fns, 0, 0 }, - { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_hh_encode_fns, 0, 0 }, - { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, - { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, - { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, - { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, - { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, - { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, - { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, - { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, - { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, - { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, - { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, - { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, - { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, - { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, - { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, - { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, - { "lddec", ICLASS_xt_iclass_mac16_l, - 0, - Opcode_lddec_encode_fns, 0, 0 }, - { "ldinc", ICLASS_xt_iclass_mac16_l, - 0, - Opcode_ldinc_encode_fns, 0, 0 }, - { "rsr.m0", ICLASS_xt_iclass_rsr_m0, - 0, - Opcode_rsr_m0_encode_fns, 0, 0 }, - { "wsr.m0", ICLASS_xt_iclass_wsr_m0, - 0, - Opcode_wsr_m0_encode_fns, 0, 0 }, - { "xsr.m0", ICLASS_xt_iclass_xsr_m0, - 0, - Opcode_xsr_m0_encode_fns, 0, 0 }, - { "rsr.m1", ICLASS_xt_iclass_rsr_m1, - 0, - Opcode_rsr_m1_encode_fns, 0, 0 }, - { "wsr.m1", ICLASS_xt_iclass_wsr_m1, - 0, - Opcode_wsr_m1_encode_fns, 0, 0 }, - { "xsr.m1", ICLASS_xt_iclass_xsr_m1, - 0, - Opcode_xsr_m1_encode_fns, 0, 0 }, - { "rsr.m2", ICLASS_xt_iclass_rsr_m2, - 0, - Opcode_rsr_m2_encode_fns, 0, 0 }, - { "wsr.m2", ICLASS_xt_iclass_wsr_m2, - 0, - Opcode_wsr_m2_encode_fns, 0, 0 }, - { "xsr.m2", ICLASS_xt_iclass_xsr_m2, - 0, - Opcode_xsr_m2_encode_fns, 0, 0 }, - { "rsr.m3", ICLASS_xt_iclass_rsr_m3, - 0, - Opcode_rsr_m3_encode_fns, 0, 0 }, - { "wsr.m3", ICLASS_xt_iclass_wsr_m3, - 0, - Opcode_wsr_m3_encode_fns, 0, 0 }, - { "xsr.m3", ICLASS_xt_iclass_xsr_m3, - 0, - Opcode_xsr_m3_encode_fns, 0, 0 }, - { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo, - 0, - Opcode_rsr_acclo_encode_fns, 0, 0 }, - { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo, - 0, - Opcode_wsr_acclo_encode_fns, 0, 0 }, - { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo, - 0, - Opcode_xsr_acclo_encode_fns, 0, 0 }, - { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi, - 0, - Opcode_rsr_acchi_encode_fns, 0, 0 }, - { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi, - 0, - Opcode_wsr_acchi_encode_fns, 0, 0 }, - { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi, - 0, - Opcode_xsr_acchi_encode_fns, 0, 0 }, - { "rfi", ICLASS_xt_iclass_rfi, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfi_encode_fns, 0, 0 }, - { "waiti", ICLASS_xt_iclass_wait, - 0, - Opcode_waiti_encode_fns, 0, 0 }, - { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, - 0, - Opcode_rsr_interrupt_encode_fns, 0, 0 }, - { "wsr.intset", ICLASS_xt_iclass_wsr_intset, - 0, - Opcode_wsr_intset_encode_fns, 0, 0 }, - { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, - 0, - Opcode_wsr_intclear_encode_fns, 0, 0 }, - { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, - 0, - Opcode_rsr_intenable_encode_fns, 0, 0 }, - { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, - 0, - Opcode_wsr_intenable_encode_fns, 0, 0 }, - { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, - 0, - Opcode_xsr_intenable_encode_fns, 0, 0 }, - { "break", ICLASS_xt_iclass_break, - 0, - Opcode_break_encode_fns, 0, 0 }, - { "break.n", ICLASS_xt_iclass_break_n, - 0, - Opcode_break_n_encode_fns, 0, 0 }, - { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, - 0, - Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, - { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, - 0, - Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, - { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, - 0, - Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, - { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, - 0, - Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, - { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, - 0, - Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, - { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, - 0, - Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, - { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, - 0, - Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, - { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, - 0, - Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, - { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, - 0, - Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, - { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, - 0, - Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, - { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, - 0, - Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, - { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, - 0, - Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, - { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, - 0, - Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, - { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, - 0, - Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, - { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, - 0, - Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, - { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, - 0, - Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, - { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, - 0, - Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, - { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, - 0, - Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, - { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, - 0, - Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, - { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, - 0, - Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, - { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, - 0, - Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, - { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, - 0, - Opcode_rsr_debugcause_encode_fns, 0, 0 }, - { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, - 0, - Opcode_wsr_debugcause_encode_fns, 0, 0 }, - { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, - 0, - Opcode_xsr_debugcause_encode_fns, 0, 0 }, - { "rsr.icount", ICLASS_xt_iclass_rsr_icount, - 0, - Opcode_rsr_icount_encode_fns, 0, 0 }, - { "wsr.icount", ICLASS_xt_iclass_wsr_icount, - 0, - Opcode_wsr_icount_encode_fns, 0, 0 }, - { "xsr.icount", ICLASS_xt_iclass_xsr_icount, - 0, - Opcode_xsr_icount_encode_fns, 0, 0 }, - { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, - 0, - Opcode_rsr_icountlevel_encode_fns, 0, 0 }, - { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, - 0, - Opcode_wsr_icountlevel_encode_fns, 0, 0 }, - { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, - 0, - Opcode_xsr_icountlevel_encode_fns, 0, 0 }, - { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, - 0, - Opcode_rsr_ddr_encode_fns, 0, 0 }, - { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, - 0, - Opcode_wsr_ddr_encode_fns, 0, 0 }, - { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, - 0, - Opcode_xsr_ddr_encode_fns, 0, 0 }, - { "rfdo", ICLASS_xt_iclass_rfdo, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdo_encode_fns, 0, 0 }, - { "rfdd", ICLASS_xt_iclass_rfdd, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdd_encode_fns, 0, 0 }, - { "andb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_andb_encode_fns, 0, 0 }, - { "andbc", ICLASS_xt_iclass_bbool1, - 0, - Opcode_andbc_encode_fns, 0, 0 }, - { "orb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_orb_encode_fns, 0, 0 }, - { "orbc", ICLASS_xt_iclass_bbool1, - 0, - Opcode_orbc_encode_fns, 0, 0 }, - { "xorb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_xorb_encode_fns, 0, 0 }, - { "any4", ICLASS_xt_iclass_bbool4, - 0, - Opcode_any4_encode_fns, 0, 0 }, - { "all4", ICLASS_xt_iclass_bbool4, - 0, - Opcode_all4_encode_fns, 0, 0 }, - { "any8", ICLASS_xt_iclass_bbool8, - 0, - Opcode_any8_encode_fns, 0, 0 }, - { "all8", ICLASS_xt_iclass_bbool8, - 0, - Opcode_all8_encode_fns, 0, 0 }, - { "bf", ICLASS_xt_iclass_bbranch, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bf_encode_fns, 0, 0 }, - { "bt", ICLASS_xt_iclass_bbranch, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bt_encode_fns, 0, 0 }, - { "movf", ICLASS_xt_iclass_bmove, - 0, - Opcode_movf_encode_fns, 0, 0 }, - { "movt", ICLASS_xt_iclass_bmove, - 0, - Opcode_movt_encode_fns, 0, 0 }, - { "rsr.br", ICLASS_xt_iclass_RSR_BR, - 0, - Opcode_rsr_br_encode_fns, 0, 0 }, - { "wsr.br", ICLASS_xt_iclass_WSR_BR, - 0, - Opcode_wsr_br_encode_fns, 0, 0 }, - { "xsr.br", ICLASS_xt_iclass_XSR_BR, - 0, - Opcode_xsr_br_encode_fns, 0, 0 }, - { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, - 0, - Opcode_rsr_ccount_encode_fns, 0, 0 }, - { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, - 0, - Opcode_wsr_ccount_encode_fns, 0, 0 }, - { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, - 0, - Opcode_xsr_ccount_encode_fns, 0, 0 }, - { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, - 0, - Opcode_rsr_ccompare0_encode_fns, 0, 0 }, - { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, - 0, - Opcode_wsr_ccompare0_encode_fns, 0, 0 }, - { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, - 0, - Opcode_xsr_ccompare0_encode_fns, 0, 0 }, - { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, - 0, - Opcode_rsr_ccompare1_encode_fns, 0, 0 }, - { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, - 0, - Opcode_wsr_ccompare1_encode_fns, 0, 0 }, - { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, - 0, - Opcode_xsr_ccompare1_encode_fns, 0, 0 }, - { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, - 0, - Opcode_rsr_ccompare2_encode_fns, 0, 0 }, - { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, - 0, - Opcode_wsr_ccompare2_encode_fns, 0, 0 }, - { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, - 0, - Opcode_xsr_ccompare2_encode_fns, 0, 0 }, - { "ipf", ICLASS_xt_iclass_icache, - 0, - Opcode_ipf_encode_fns, 0, 0 }, - { "ihi", ICLASS_xt_iclass_icache, - 0, - Opcode_ihi_encode_fns, 0, 0 }, - { "ipfl", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_ipfl_encode_fns, 0, 0 }, - { "ihu", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_ihu_encode_fns, 0, 0 }, - { "iiu", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_iiu_encode_fns, 0, 0 }, - { "iii", ICLASS_xt_iclass_icache_inv, - 0, - Opcode_iii_encode_fns, 0, 0 }, - { "lict", ICLASS_xt_iclass_licx, - 0, - Opcode_lict_encode_fns, 0, 0 }, - { "licw", ICLASS_xt_iclass_licx, - 0, - Opcode_licw_encode_fns, 0, 0 }, - { "sict", ICLASS_xt_iclass_sicx, - 0, - Opcode_sict_encode_fns, 0, 0 }, - { "sicw", ICLASS_xt_iclass_sicx, - 0, - Opcode_sicw_encode_fns, 0, 0 }, - { "dhwb", ICLASS_xt_iclass_dcache, - 0, - Opcode_dhwb_encode_fns, 0, 0 }, - { "dhwbi", ICLASS_xt_iclass_dcache, - 0, - Opcode_dhwbi_encode_fns, 0, 0 }, - { "diwb", ICLASS_xt_iclass_dcache_ind, - 0, - Opcode_diwb_encode_fns, 0, 0 }, - { "diwbi", ICLASS_xt_iclass_dcache_ind, - 0, - Opcode_diwbi_encode_fns, 0, 0 }, - { "dhi", ICLASS_xt_iclass_dcache_inv, - 0, - Opcode_dhi_encode_fns, 0, 0 }, - { "dii", ICLASS_xt_iclass_dcache_inv, - 0, - Opcode_dii_encode_fns, 0, 0 }, - { "dpfr", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfr_encode_fns, 0, 0 }, - { "dpfw", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfw_encode_fns, 0, 0 }, - { "dpfro", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfro_encode_fns, 0, 0 }, - { "dpfwo", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfwo_encode_fns, 0, 0 }, - { "dpfl", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_dpfl_encode_fns, 0, 0 }, - { "dhu", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_dhu_encode_fns, 0, 0 }, - { "diu", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_diu_encode_fns, 0, 0 }, - { "sdct", ICLASS_xt_iclass_sdct, - 0, - Opcode_sdct_encode_fns, 0, 0 }, - { "ldct", ICLASS_xt_iclass_ldct, - 0, - Opcode_ldct_encode_fns, 0, 0 }, - { "rsr.prefctl", ICLASS_xt_iclass_rsr_prefctl, - 0, - Opcode_rsr_prefctl_encode_fns, 0, 0 }, - { "wsr.prefctl", ICLASS_xt_iclass_wsr_prefctl, - 0, - Opcode_wsr_prefctl_encode_fns, 0, 0 }, - { "xsr.prefctl", ICLASS_xt_iclass_xsr_prefctl, - 0, - Opcode_xsr_prefctl_encode_fns, 0, 0 }, - { "idtlb", ICLASS_xt_iclass_idtlb, - 0, - Opcode_idtlb_encode_fns, 0, 0 }, - { "pdtlb", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_pdtlb_encode_fns, 0, 0 }, - { "rdtlb0", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb0_encode_fns, 0, 0 }, - { "rdtlb1", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb1_encode_fns, 0, 0 }, - { "wdtlb", ICLASS_xt_iclass_wdtlb, - 0, - Opcode_wdtlb_encode_fns, 0, 0 }, - { "iitlb", ICLASS_xt_iclass_iitlb, - 0, - Opcode_iitlb_encode_fns, 0, 0 }, - { "pitlb", ICLASS_xt_iclass_ritlb, - 0, - Opcode_pitlb_encode_fns, 0, 0 }, - { "ritlb0", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb0_encode_fns, 0, 0 }, - { "ritlb1", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb1_encode_fns, 0, 0 }, - { "witlb", ICLASS_xt_iclass_witlb, - 0, - Opcode_witlb_encode_fns, 0, 0 }, - { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, - 0, - Opcode_rsr_cpenable_encode_fns, 0, 0 }, - { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, - 0, - Opcode_wsr_cpenable_encode_fns, 0, 0 }, - { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, - 0, - Opcode_xsr_cpenable_encode_fns, 0, 0 }, - { "clamps", ICLASS_xt_iclass_clamp, - 0, - Opcode_clamps_encode_fns, 0, 0 }, - { "min", ICLASS_xt_iclass_minmax, - 0, - Opcode_min_encode_fns, 0, 0 }, - { "max", ICLASS_xt_iclass_minmax, - 0, - Opcode_max_encode_fns, 0, 0 }, - { "minu", ICLASS_xt_iclass_minmax, - 0, - Opcode_minu_encode_fns, 0, 0 }, - { "maxu", ICLASS_xt_iclass_minmax, - 0, - Opcode_maxu_encode_fns, 0, 0 }, - { "nsa", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsa_encode_fns, 0, 0 }, - { "nsau", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsau_encode_fns, 0, 0 }, - { "sext", ICLASS_xt_iclass_sx, - 0, - Opcode_sext_encode_fns, 0, 0 }, - { "l32ai", ICLASS_xt_iclass_l32ai, - 0, - Opcode_l32ai_encode_fns, 0, 0 }, - { "s32ri", ICLASS_xt_iclass_s32ri, - 0, - Opcode_s32ri_encode_fns, 0, 0 }, - { "s32c1i", ICLASS_xt_iclass_s32c1i, - 0, - Opcode_s32c1i_encode_fns, 0, 0 }, - { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, - 0, - Opcode_rsr_scompare1_encode_fns, 0, 0 }, - { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, - 0, - Opcode_wsr_scompare1_encode_fns, 0, 0 }, - { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, - 0, - Opcode_xsr_scompare1_encode_fns, 0, 0 }, - { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, - 0, - Opcode_rsr_atomctl_encode_fns, 0, 0 }, - { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, - 0, - Opcode_wsr_atomctl_encode_fns, 0, 0 }, - { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, - 0, - Opcode_xsr_atomctl_encode_fns, 0, 0 }, - { "rer", ICLASS_xt_iclass_rer, - 0, - Opcode_rer_encode_fns, 0, 0 }, - { "wer", ICLASS_xt_iclass_wer, - 0, - Opcode_wer_encode_fns, 0, 0 }, - { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar, - 0, - Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 }, - { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar, - 0, - Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 }, - { "rur.ae_bithead", ICLASS_rur_ae_bithead, - 0, - Opcode_rur_ae_bithead_encode_fns, 0, 0 }, - { "wur.ae_bithead", ICLASS_wur_ae_bithead, - 0, - Opcode_wur_ae_bithead_encode_fns, 0, 0 }, - { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp, - 0, - Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, - { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp, - 0, - Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, - { "rur.ae_sd_no", ICLASS_rur_ae_sd_no, - 0, - Opcode_rur_ae_sd_no_encode_fns, 0, 0 }, - { "wur.ae_sd_no", ICLASS_wur_ae_sd_no, - 0, - Opcode_wur_ae_sd_no_encode_fns, 0, 0 }, - { "rur.ae_overflow", ICLASS_ae_iclass_rur_ae_overflow, - 0, - Opcode_rur_ae_overflow_encode_fns, 0, 0 }, - { "wur.ae_overflow", ICLASS_ae_iclass_wur_ae_overflow, - 0, - Opcode_wur_ae_overflow_encode_fns, 0, 0 }, - { "rur.ae_sar", ICLASS_ae_iclass_rur_ae_sar, - 0, - Opcode_rur_ae_sar_encode_fns, 0, 0 }, - { "wur.ae_sar", ICLASS_ae_iclass_wur_ae_sar, - 0, - Opcode_wur_ae_sar_encode_fns, 0, 0 }, - { "rur.ae_bitptr", ICLASS_ae_iclass_rur_ae_bitptr, - 0, - Opcode_rur_ae_bitptr_encode_fns, 0, 0 }, - { "wur.ae_bitptr", ICLASS_ae_iclass_wur_ae_bitptr, - 0, - Opcode_wur_ae_bitptr_encode_fns, 0, 0 }, - { "rur.ae_bitsused", ICLASS_ae_iclass_rur_ae_bitsused, - 0, - Opcode_rur_ae_bitsused_encode_fns, 0, 0 }, - { "wur.ae_bitsused", ICLASS_ae_iclass_wur_ae_bitsused, - 0, - Opcode_wur_ae_bitsused_encode_fns, 0, 0 }, - { "rur.ae_tablesize", ICLASS_ae_iclass_rur_ae_tablesize, - 0, - Opcode_rur_ae_tablesize_encode_fns, 0, 0 }, - { "wur.ae_tablesize", ICLASS_ae_iclass_wur_ae_tablesize, - 0, - Opcode_wur_ae_tablesize_encode_fns, 0, 0 }, - { "rur.ae_first_ts", ICLASS_ae_iclass_rur_ae_first_ts, - 0, - Opcode_rur_ae_first_ts_encode_fns, 0, 0 }, - { "wur.ae_first_ts", ICLASS_ae_iclass_wur_ae_first_ts, - 0, - Opcode_wur_ae_first_ts_encode_fns, 0, 0 }, - { "rur.ae_nextoffset", ICLASS_ae_iclass_rur_ae_nextoffset, - 0, - Opcode_rur_ae_nextoffset_encode_fns, 0, 0 }, - { "wur.ae_nextoffset", ICLASS_ae_iclass_wur_ae_nextoffset, - 0, - Opcode_wur_ae_nextoffset_encode_fns, 0, 0 }, - { "rur.ae_searchdone", ICLASS_ae_iclass_rur_ae_searchdone, - 0, - Opcode_rur_ae_searchdone_encode_fns, 0, 0 }, - { "wur.ae_searchdone", ICLASS_ae_iclass_wur_ae_searchdone, - 0, - Opcode_wur_ae_searchdone_encode_fns, 0, 0 }, - { "ae_lp16f.i", ICLASS_ae_iclass_lp16f_i, - 0, - Opcode_ae_lp16f_i_encode_fns, 0, 0 }, - { "ae_lp16f.iu", ICLASS_ae_iclass_lp16f_iu, - 0, - Opcode_ae_lp16f_iu_encode_fns, 0, 0 }, - { "ae_lp16f.x", ICLASS_ae_iclass_lp16f_x, - 0, - Opcode_ae_lp16f_x_encode_fns, 0, 0 }, - { "ae_lp16f.xu", ICLASS_ae_iclass_lp16f_xu, - 0, - Opcode_ae_lp16f_xu_encode_fns, 0, 0 }, - { "ae_lp24.i", ICLASS_ae_iclass_lp24_i, - 0, - Opcode_ae_lp24_i_encode_fns, 0, 0 }, - { "ae_lp24.iu", ICLASS_ae_iclass_lp24_iu, - 0, - Opcode_ae_lp24_iu_encode_fns, 0, 0 }, - { "ae_lp24.x", ICLASS_ae_iclass_lp24_x, - 0, - Opcode_ae_lp24_x_encode_fns, 0, 0 }, - { "ae_lp24.xu", ICLASS_ae_iclass_lp24_xu, - 0, - Opcode_ae_lp24_xu_encode_fns, 0, 0 }, - { "ae_lp24f.i", ICLASS_ae_iclass_lp24f_i, - 0, - Opcode_ae_lp24f_i_encode_fns, 0, 0 }, - { "ae_lp24f.iu", ICLASS_ae_iclass_lp24f_iu, - 0, - Opcode_ae_lp24f_iu_encode_fns, 0, 0 }, - { "ae_lp24f.x", ICLASS_ae_iclass_lp24f_x, - 0, - Opcode_ae_lp24f_x_encode_fns, 0, 0 }, - { "ae_lp24f.xu", ICLASS_ae_iclass_lp24f_xu, - 0, - Opcode_ae_lp24f_xu_encode_fns, 0, 0 }, - { "ae_lp16x2f.i", ICLASS_ae_iclass_lp16x2f_i, - 0, - Opcode_ae_lp16x2f_i_encode_fns, 0, 0 }, - { "ae_lp16x2f.iu", ICLASS_ae_iclass_lp16x2f_iu, - 0, - Opcode_ae_lp16x2f_iu_encode_fns, 0, 0 }, - { "ae_lp16x2f.x", ICLASS_ae_iclass_lp16x2f_x, - 0, - Opcode_ae_lp16x2f_x_encode_fns, 0, 0 }, - { "ae_lp16x2f.xu", ICLASS_ae_iclass_lp16x2f_xu, - 0, - Opcode_ae_lp16x2f_xu_encode_fns, 0, 0 }, - { "ae_lp24x2f.i", ICLASS_ae_iclass_lp24x2f_i, - 0, - Opcode_ae_lp24x2f_i_encode_fns, 0, 0 }, - { "ae_lp24x2f.iu", ICLASS_ae_iclass_lp24x2f_iu, - 0, - Opcode_ae_lp24x2f_iu_encode_fns, 0, 0 }, - { "ae_lp24x2f.x", ICLASS_ae_iclass_lp24x2f_x, - 0, - Opcode_ae_lp24x2f_x_encode_fns, 0, 0 }, - { "ae_lp24x2f.xu", ICLASS_ae_iclass_lp24x2f_xu, - 0, - Opcode_ae_lp24x2f_xu_encode_fns, 0, 0 }, - { "ae_lp24x2.i", ICLASS_ae_iclass_lp24x2_i, - 0, - Opcode_ae_lp24x2_i_encode_fns, 0, 0 }, - { "ae_lp24x2.iu", ICLASS_ae_iclass_lp24x2_iu, - 0, - Opcode_ae_lp24x2_iu_encode_fns, 0, 0 }, - { "ae_lp24x2.x", ICLASS_ae_iclass_lp24x2_x, - 0, - Opcode_ae_lp24x2_x_encode_fns, 0, 0 }, - { "ae_lp24x2.xu", ICLASS_ae_iclass_lp24x2_xu, - 0, - Opcode_ae_lp24x2_xu_encode_fns, 0, 0 }, - { "ae_sp16x2f.i", ICLASS_ae_iclass_sp16x2f_i, - 0, - Opcode_ae_sp16x2f_i_encode_fns, 0, 0 }, - { "ae_sp16x2f.iu", ICLASS_ae_iclass_sp16x2f_iu, - 0, - Opcode_ae_sp16x2f_iu_encode_fns, 0, 0 }, - { "ae_sp16x2f.x", ICLASS_ae_iclass_sp16x2f_x, - 0, - Opcode_ae_sp16x2f_x_encode_fns, 0, 0 }, - { "ae_sp16x2f.xu", ICLASS_ae_iclass_sp16x2f_xu, - 0, - Opcode_ae_sp16x2f_xu_encode_fns, 0, 0 }, - { "ae_sp24x2s.i", ICLASS_ae_iclass_sp24x2s_i, - 0, - Opcode_ae_sp24x2s_i_encode_fns, 0, 0 }, - { "ae_sp24x2s.iu", ICLASS_ae_iclass_sp24x2s_iu, - 0, - Opcode_ae_sp24x2s_iu_encode_fns, 0, 0 }, - { "ae_sp24x2s.x", ICLASS_ae_iclass_sp24x2s_x, - 0, - Opcode_ae_sp24x2s_x_encode_fns, 0, 0 }, - { "ae_sp24x2s.xu", ICLASS_ae_iclass_sp24x2s_xu, - 0, - Opcode_ae_sp24x2s_xu_encode_fns, 0, 0 }, - { "ae_sp24x2f.i", ICLASS_ae_iclass_sp24x2f_i, - 0, - Opcode_ae_sp24x2f_i_encode_fns, 0, 0 }, - { "ae_sp24x2f.iu", ICLASS_ae_iclass_sp24x2f_iu, - 0, - Opcode_ae_sp24x2f_iu_encode_fns, 0, 0 }, - { "ae_sp24x2f.x", ICLASS_ae_iclass_sp24x2f_x, - 0, - Opcode_ae_sp24x2f_x_encode_fns, 0, 0 }, - { "ae_sp24x2f.xu", ICLASS_ae_iclass_sp24x2f_xu, - 0, - Opcode_ae_sp24x2f_xu_encode_fns, 0, 0 }, - { "ae_sp16f.l.i", ICLASS_ae_iclass_sp16f_l_i, - 0, - Opcode_ae_sp16f_l_i_encode_fns, 0, 0 }, - { "ae_sp16f.l.iu", ICLASS_ae_iclass_sp16f_l_iu, - 0, - Opcode_ae_sp16f_l_iu_encode_fns, 0, 0 }, - { "ae_sp16f.l.x", ICLASS_ae_iclass_sp16f_l_x, - 0, - Opcode_ae_sp16f_l_x_encode_fns, 0, 0 }, - { "ae_sp16f.l.xu", ICLASS_ae_iclass_sp16f_l_xu, - 0, - Opcode_ae_sp16f_l_xu_encode_fns, 0, 0 }, - { "ae_sp24s.l.i", ICLASS_ae_iclass_sp24s_l_i, - 0, - Opcode_ae_sp24s_l_i_encode_fns, 0, 0 }, - { "ae_sp24s.l.iu", ICLASS_ae_iclass_sp24s_l_iu, - 0, - Opcode_ae_sp24s_l_iu_encode_fns, 0, 0 }, - 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{ "ae_mulzasq32sp16s.lh", ICLASS_ae_iclass_mulzasq32sp16s_lh, - 0, - Opcode_ae_mulzasq32sp16s_lh_encode_fns, 0, 0 }, - { "ae_mulzasfq32sp16s.lh", ICLASS_ae_iclass_mulzasfq32sp16s_lh, - 0, - Opcode_ae_mulzasfq32sp16s_lh_encode_fns, 0, 0 }, - { "ae_mulzasq32sp16u.lh", ICLASS_ae_iclass_mulzasq32sp16u_lh, - 0, - Opcode_ae_mulzasq32sp16u_lh_encode_fns, 0, 0 }, - { "ae_mulzasfq32sp16u.lh", ICLASS_ae_iclass_mulzasfq32sp16u_lh, - 0, - Opcode_ae_mulzasfq32sp16u_lh_encode_fns, 0, 0 }, - { "ae_mulzsaq32sp16s.ll", ICLASS_ae_iclass_mulzsaq32sp16s_ll, - 0, - Opcode_ae_mulzsaq32sp16s_ll_encode_fns, 0, 0 }, - { "ae_mulzsafq32sp16s.ll", ICLASS_ae_iclass_mulzsafq32sp16s_ll, - 0, - Opcode_ae_mulzsafq32sp16s_ll_encode_fns, 0, 0 }, - { "ae_mulzsaq32sp16u.ll", ICLASS_ae_iclass_mulzsaq32sp16u_ll, - 0, - Opcode_ae_mulzsaq32sp16u_ll_encode_fns, 0, 0 }, - { "ae_mulzsafq32sp16u.ll", ICLASS_ae_iclass_mulzsafq32sp16u_ll, - 0, - Opcode_ae_mulzsafq32sp16u_ll_encode_fns, 0, 0 }, - { "ae_mulzsaq32sp16s.hh", ICLASS_ae_iclass_mulzsaq32sp16s_hh, - 0, - Opcode_ae_mulzsaq32sp16s_hh_encode_fns, 0, 0 }, - { "ae_mulzsafq32sp16s.hh", ICLASS_ae_iclass_mulzsafq32sp16s_hh, - 0, - Opcode_ae_mulzsafq32sp16s_hh_encode_fns, 0, 0 }, - { "ae_mulzsaq32sp16u.hh", ICLASS_ae_iclass_mulzsaq32sp16u_hh, - 0, - Opcode_ae_mulzsaq32sp16u_hh_encode_fns, 0, 0 }, - { "ae_mulzsafq32sp16u.hh", ICLASS_ae_iclass_mulzsafq32sp16u_hh, - 0, - Opcode_ae_mulzsafq32sp16u_hh_encode_fns, 0, 0 }, - { "ae_mulzsaq32sp16s.lh", ICLASS_ae_iclass_mulzsaq32sp16s_lh, - 0, - Opcode_ae_mulzsaq32sp16s_lh_encode_fns, 0, 0 }, - { "ae_mulzsafq32sp16s.lh", ICLASS_ae_iclass_mulzsafq32sp16s_lh, - 0, - Opcode_ae_mulzsafq32sp16s_lh_encode_fns, 0, 0 }, - { "ae_mulzsaq32sp16u.lh", ICLASS_ae_iclass_mulzsaq32sp16u_lh, - 0, - Opcode_ae_mulzsaq32sp16u_lh_encode_fns, 0, 0 }, - { "ae_mulzsafq32sp16u.lh", ICLASS_ae_iclass_mulzsafq32sp16u_lh, - 0, - Opcode_ae_mulzsafq32sp16u_lh_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16s.ll", ICLASS_ae_iclass_mulzssq32sp16s_ll, - 0, - Opcode_ae_mulzssq32sp16s_ll_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16s.ll", ICLASS_ae_iclass_mulzssfq32sp16s_ll, - 0, - Opcode_ae_mulzssfq32sp16s_ll_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16u.ll", ICLASS_ae_iclass_mulzssq32sp16u_ll, - 0, - Opcode_ae_mulzssq32sp16u_ll_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16u.ll", ICLASS_ae_iclass_mulzssfq32sp16u_ll, - 0, - Opcode_ae_mulzssfq32sp16u_ll_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16s.hh", ICLASS_ae_iclass_mulzssq32sp16s_hh, - 0, - Opcode_ae_mulzssq32sp16s_hh_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16s.hh", ICLASS_ae_iclass_mulzssfq32sp16s_hh, - 0, - Opcode_ae_mulzssfq32sp16s_hh_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16u.hh", ICLASS_ae_iclass_mulzssq32sp16u_hh, - 0, - Opcode_ae_mulzssq32sp16u_hh_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16u.hh", ICLASS_ae_iclass_mulzssfq32sp16u_hh, - 0, - Opcode_ae_mulzssfq32sp16u_hh_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16s.lh", ICLASS_ae_iclass_mulzssq32sp16s_lh, - 0, - Opcode_ae_mulzssq32sp16s_lh_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16s.lh", ICLASS_ae_iclass_mulzssfq32sp16s_lh, - 0, - Opcode_ae_mulzssfq32sp16s_lh_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16u.lh", ICLASS_ae_iclass_mulzssq32sp16u_lh, - 0, - Opcode_ae_mulzssq32sp16u_lh_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16u.lh", ICLASS_ae_iclass_mulzssfq32sp16u_lh, - 0, - Opcode_ae_mulzssfq32sp16u_lh_encode_fns, 0, 0 }, - { "ae_mulzaafp24s.hh.ll", ICLASS_ae_iclass_mulzaafp24s_hh_ll, - 0, - Opcode_ae_mulzaafp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzaap24s.hh.ll", ICLASS_ae_iclass_mulzaap24s_hh_ll, - 0, - Opcode_ae_mulzaap24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzaafp24s.hl.lh", ICLASS_ae_iclass_mulzaafp24s_hl_lh, - 0, - Opcode_ae_mulzaafp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzaap24s.hl.lh", ICLASS_ae_iclass_mulzaap24s_hl_lh, - 0, - Opcode_ae_mulzaap24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzasfp24s.hh.ll", ICLASS_ae_iclass_mulzasfp24s_hh_ll, - 0, - Opcode_ae_mulzasfp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzasp24s.hh.ll", ICLASS_ae_iclass_mulzasp24s_hh_ll, - 0, - Opcode_ae_mulzasp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzasfp24s.hl.lh", ICLASS_ae_iclass_mulzasfp24s_hl_lh, - 0, - Opcode_ae_mulzasfp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzasp24s.hl.lh", ICLASS_ae_iclass_mulzasp24s_hl_lh, - 0, - Opcode_ae_mulzasp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzsafp24s.hh.ll", ICLASS_ae_iclass_mulzsafp24s_hh_ll, - 0, - Opcode_ae_mulzsafp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzsap24s.hh.ll", ICLASS_ae_iclass_mulzsap24s_hh_ll, - 0, - Opcode_ae_mulzsap24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzsafp24s.hl.lh", ICLASS_ae_iclass_mulzsafp24s_hl_lh, - 0, - Opcode_ae_mulzsafp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzsap24s.hl.lh", ICLASS_ae_iclass_mulzsap24s_hl_lh, - 0, - Opcode_ae_mulzsap24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzssfp24s.hh.ll", ICLASS_ae_iclass_mulzssfp24s_hh_ll, - 0, - Opcode_ae_mulzssfp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzssp24s.hh.ll", ICLASS_ae_iclass_mulzssp24s_hh_ll, - 0, - Opcode_ae_mulzssp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzssfp24s.hl.lh", ICLASS_ae_iclass_mulzssfp24s_hl_lh, - 0, - Opcode_ae_mulzssfp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzssp24s.hl.lh", ICLASS_ae_iclass_mulzssp24s_hl_lh, - 0, - Opcode_ae_mulzssp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulaafp24s.hh.ll", ICLASS_ae_iclass_mulaafp24s_hh_ll, - 0, - Opcode_ae_mulaafp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulaap24s.hh.ll", ICLASS_ae_iclass_mulaap24s_hh_ll, - 0, - Opcode_ae_mulaap24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulaafp24s.hl.lh", ICLASS_ae_iclass_mulaafp24s_hl_lh, - 0, - Opcode_ae_mulaafp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulaap24s.hl.lh", ICLASS_ae_iclass_mulaap24s_hl_lh, - 0, - Opcode_ae_mulaap24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulasfp24s.hh.ll", ICLASS_ae_iclass_mulasfp24s_hh_ll, - 0, - Opcode_ae_mulasfp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulasp24s.hh.ll", ICLASS_ae_iclass_mulasp24s_hh_ll, - 0, - Opcode_ae_mulasp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulasfp24s.hl.lh", ICLASS_ae_iclass_mulasfp24s_hl_lh, - 0, - Opcode_ae_mulasfp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulasp24s.hl.lh", ICLASS_ae_iclass_mulasp24s_hl_lh, - 0, - Opcode_ae_mulasp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulsafp24s.hh.ll", ICLASS_ae_iclass_mulsafp24s_hh_ll, - 0, - Opcode_ae_mulsafp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulsap24s.hh.ll", ICLASS_ae_iclass_mulsap24s_hh_ll, - 0, - Opcode_ae_mulsap24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulsafp24s.hl.lh", ICLASS_ae_iclass_mulsafp24s_hl_lh, - 0, - Opcode_ae_mulsafp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulsap24s.hl.lh", ICLASS_ae_iclass_mulsap24s_hl_lh, - 0, - Opcode_ae_mulsap24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulssfp24s.hh.ll", ICLASS_ae_iclass_mulssfp24s_hh_ll, - 0, - Opcode_ae_mulssfp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulssp24s.hh.ll", ICLASS_ae_iclass_mulssp24s_hh_ll, - 0, - Opcode_ae_mulssp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulssfp24s.hl.lh", ICLASS_ae_iclass_mulssfp24s_hl_lh, - 0, - Opcode_ae_mulssfp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulssp24s.hl.lh", ICLASS_ae_iclass_mulssp24s_hl_lh, - 0, - Opcode_ae_mulssp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_sha32", ICLASS_ae_iclass_sha32, - 0, - Opcode_ae_sha32_encode_fns, 0, 0 }, - { "ae_vldl32t", ICLASS_ae_iclass_vldl32t, - 0, - Opcode_ae_vldl32t_encode_fns, 1, Opcode_ae_vldl32t_funcUnit_uses }, - { "ae_vldl16t", ICLASS_ae_iclass_vldl16t, - 0, - Opcode_ae_vldl16t_encode_fns, 1, Opcode_ae_vldl16t_funcUnit_uses }, - { "ae_vldl16c", ICLASS_ae_iclass_vldl16c, - 0, - Opcode_ae_vldl16c_encode_fns, 3, Opcode_ae_vldl16c_funcUnit_uses }, - { "ae_vldsht", ICLASS_ae_iclass_vldsht, - 0, - Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses }, - { "ae_lb", ICLASS_ae_iclass_lb, - 0, - Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses }, - { "ae_lbi", ICLASS_ae_iclass_lbi, - 0, - Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses }, - { "ae_lbk", ICLASS_ae_iclass_lbk, - 0, - Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses }, - { "ae_lbki", ICLASS_ae_iclass_lbki, - 0, - Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses }, - { "ae_db", ICLASS_ae_iclass_db, - 0, - Opcode_ae_db_encode_fns, 2, Opcode_ae_db_funcUnit_uses }, - { "ae_dbi", ICLASS_ae_iclass_dbi, - 0, - Opcode_ae_dbi_encode_fns, 2, Opcode_ae_dbi_funcUnit_uses }, - { "ae_vlel32t", ICLASS_ae_iclass_vlel32t, - 0, - Opcode_ae_vlel32t_encode_fns, 1, Opcode_ae_vlel32t_funcUnit_uses }, - { "ae_vlel16t", ICLASS_ae_iclass_vlel16t, - 0, - Opcode_ae_vlel16t_encode_fns, 1, Opcode_ae_vlel16t_funcUnit_uses }, - { "ae_sb", ICLASS_ae_iclass_sb, - 0, - Opcode_ae_sb_encode_fns, 2, Opcode_ae_sb_funcUnit_uses }, - { "ae_sbi", ICLASS_ae_iclass_sbi, - 0, - Opcode_ae_sbi_encode_fns, 2, Opcode_ae_sbi_funcUnit_uses }, - { "ae_vles16c", ICLASS_ae_iclass_vles16c, - 0, - Opcode_ae_vles16c_encode_fns, 2, Opcode_ae_vles16c_funcUnit_uses }, - { "ae_sbf", ICLASS_ae_iclass_sbf, - 0, - Opcode_ae_sbf_encode_fns, 2, Opcode_ae_sbf_funcUnit_uses }, - { "ae_slaasq56s", ICLASS_icls_AE_SLAASQ56S, - 0, - Opcode_ae_slaasq56s_encode_fns, 0, 0 }, - { "ae_addbrba32", ICLASS_icls_AE_ADDBRBA32, - 0, - Opcode_ae_addbrba32_encode_fns, 0, 0 }, - { "ae_minabssp24s", ICLASS_icls_AE_MINABSSP24S, - 0, - Opcode_ae_minabssp24s_encode_fns, 0, 0 }, - { "ae_maxabssp24s", ICLASS_icls_AE_MAXABSSP24S, - 0, - Opcode_ae_maxabssp24s_encode_fns, 0, 0 }, - { "ae_minabssq56s", ICLASS_icls_AE_MINABSSQ56S, - 0, - Opcode_ae_minabssq56s_encode_fns, 0, 0 }, - { "ae_maxabssq56s", ICLASS_icls_AE_MAXABSSQ56S, - 0, - Opcode_ae_maxabssq56s_encode_fns, 0, 0 }, - { "rur.ae_cbegin0", ICLASS_rur_ae_cbegin0, - 0, - Opcode_rur_ae_cbegin0_encode_fns, 0, 0 }, - { "wur.ae_cbegin0", ICLASS_wur_ae_cbegin0, - 0, - Opcode_wur_ae_cbegin0_encode_fns, 0, 0 }, - { "rur.ae_cend0", ICLASS_rur_ae_cend0, - 0, - Opcode_rur_ae_cend0_encode_fns, 0, 0 }, - { "wur.ae_cend0", ICLASS_wur_ae_cend0, - 0, - Opcode_wur_ae_cend0_encode_fns, 0, 0 }, - { "ae_lp24x2.c", ICLASS_icls_AE_LP24X2_C, - 0, - Opcode_ae_lp24x2_c_encode_fns, 0, 0 }, - { "ae_sp24x2s.c", ICLASS_icls_AE_SP24X2S_C, - 0, - Opcode_ae_sp24x2s_c_encode_fns, 0, 0 }, - { "ae_lp24x2f.c", ICLASS_icls_AE_LP24X2F_C, - 0, - Opcode_ae_lp24x2f_c_encode_fns, 0, 0 }, - { "ae_sp24x2f.c", ICLASS_icls_AE_SP24X2F_C, - 0, - Opcode_ae_sp24x2f_c_encode_fns, 0, 0 }, - { "ae_lp16x2f.c", ICLASS_icls_AE_LP16X2F_C, - 0, - Opcode_ae_lp16x2f_c_encode_fns, 0, 0 }, - { "ae_sp16x2f.c", ICLASS_icls_AE_SP16X2F_C, - 0, - Opcode_ae_sp16x2f_c_encode_fns, 0, 0 }, - { "ae_lp24.c", ICLASS_icls_AE_LP24_C, - 0, - Opcode_ae_lp24_c_encode_fns, 0, 0 }, - { "ae_sp24s.l.c", ICLASS_icls_AE_SP24S_L_C, - 0, - Opcode_ae_sp24s_l_c_encode_fns, 0, 0 }, - { "ae_lp24f.c", ICLASS_icls_AE_LP24F_C, - 0, - Opcode_ae_lp24f_c_encode_fns, 0, 0 }, - { "ae_sp24f.l.c", ICLASS_icls_AE_SP24F_L_C, - 0, - Opcode_ae_sp24f_l_c_encode_fns, 0, 0 }, - { "ae_lp16f.c", ICLASS_icls_AE_LP16F_C, - 0, - Opcode_ae_lp16f_c_encode_fns, 0, 0 }, - { "ae_sp16f.l.c", ICLASS_icls_AE_SP16F_L_C, - 0, - Opcode_ae_sp16f_l_c_encode_fns, 0, 0 }, - { "ae_lq56.c", ICLASS_icls_AE_LQ56_C, - 0, - Opcode_ae_lq56_c_encode_fns, 0, 0 }, - { "ae_sq56s.c", ICLASS_icls_AE_SQ56S_C, - 0, - Opcode_ae_sq56s_c_encode_fns, 0, 0 }, - { "ae_lq32f.c", ICLASS_icls_AE_LQ32F_C, - 0, - Opcode_ae_lq32f_c_encode_fns, 0, 0 }, - { "ae_sq32f.c", ICLASS_icls_AE_SQ32F_C, - 0, - Opcode_ae_sq32f_c_encode_fns, 0, 0 } -}; - -enum xtensa_opcode_id { - OPCODE_EXCW, - OPCODE_RFE, - OPCODE_RFDE, - OPCODE_SYSCALL, - OPCODE_CALL12, - OPCODE_CALL8, - OPCODE_CALL4, - OPCODE_CALLX12, - OPCODE_CALLX8, - OPCODE_CALLX4, - OPCODE_ENTRY, - OPCODE_MOVSP, - OPCODE_ROTW, - OPCODE_RETW, - OPCODE_RETW_N, - OPCODE_RFWO, - OPCODE_RFWU, - OPCODE_L32E, - OPCODE_S32E, - OPCODE_RSR_WINDOWBASE, - OPCODE_WSR_WINDOWBASE, - OPCODE_XSR_WINDOWBASE, - OPCODE_RSR_WINDOWSTART, - OPCODE_WSR_WINDOWSTART, - OPCODE_XSR_WINDOWSTART, - OPCODE_ADD_N, - OPCODE_ADDI_N, - OPCODE_BEQZ_N, - OPCODE_BNEZ_N, - OPCODE_ILL_N, - OPCODE_L32I_N, - OPCODE_MOV_N, - OPCODE_MOVI_N, - OPCODE_NOP_N, - OPCODE_RET_N, - OPCODE_S32I_N, - OPCODE_RUR_THREADPTR, - OPCODE_WUR_THREADPTR, - OPCODE_ADDI, - OPCODE_ADDMI, - OPCODE_ADD, - OPCODE_SUB, - OPCODE_ADDX2, - OPCODE_ADDX4, - OPCODE_ADDX8, - OPCODE_SUBX2, - OPCODE_SUBX4, - OPCODE_SUBX8, - OPCODE_AND, - OPCODE_OR, - OPCODE_XOR, - OPCODE_BEQI, - OPCODE_BNEI, - OPCODE_BGEI, - OPCODE_BLTI, - OPCODE_BBCI, - OPCODE_BBSI, - OPCODE_BGEUI, - OPCODE_BLTUI, - OPCODE_BEQ, - OPCODE_BNE, - OPCODE_BGE, - OPCODE_BLT, - OPCODE_BGEU, - OPCODE_BLTU, - OPCODE_BANY, - OPCODE_BNONE, - OPCODE_BALL, - OPCODE_BNALL, - OPCODE_BBC, - OPCODE_BBS, - OPCODE_BEQZ, - OPCODE_BNEZ, - OPCODE_BGEZ, - OPCODE_BLTZ, - OPCODE_CALL0, - OPCODE_CALLX0, - OPCODE_EXTUI, - OPCODE_ILL, - OPCODE_J, - OPCODE_JX, - OPCODE_L16UI, - OPCODE_L16SI, - OPCODE_L32I, - OPCODE_L32R, - OPCODE_L8UI, - OPCODE_LOOP, - OPCODE_LOOPNEZ, - OPCODE_LOOPGTZ, - OPCODE_MOVI, - OPCODE_MOVEQZ, - OPCODE_MOVNEZ, - OPCODE_MOVLTZ, - OPCODE_MOVGEZ, - OPCODE_NEG, - OPCODE_ABS, - OPCODE_NOP, - OPCODE_RET, - OPCODE_SIMCALL, - OPCODE_S16I, - OPCODE_S32I, - OPCODE_S8I, - OPCODE_SSR, - OPCODE_SSL, - OPCODE_SSA8L, - OPCODE_SSA8B, - OPCODE_SSAI, - OPCODE_SLL, - OPCODE_SRC, - OPCODE_SRL, - OPCODE_SRA, - OPCODE_SLLI, - OPCODE_SRAI, - OPCODE_SRLI, - OPCODE_MEMW, - OPCODE_EXTW, - OPCODE_ISYNC, - OPCODE_RSYNC, - OPCODE_ESYNC, - OPCODE_DSYNC, - OPCODE_RSIL, - OPCODE_RSR_LEND, - OPCODE_WSR_LEND, - OPCODE_XSR_LEND, - OPCODE_RSR_LCOUNT, - OPCODE_WSR_LCOUNT, - OPCODE_XSR_LCOUNT, - OPCODE_RSR_LBEG, - OPCODE_WSR_LBEG, - OPCODE_XSR_LBEG, - OPCODE_RSR_SAR, - OPCODE_WSR_SAR, - OPCODE_XSR_SAR, - OPCODE_RSR_LITBASE, - OPCODE_WSR_LITBASE, - OPCODE_XSR_LITBASE, - OPCODE_RSR_CONFIGID0, - OPCODE_WSR_CONFIGID0, - OPCODE_RSR_CONFIGID1, - OPCODE_RSR_243, - OPCODE_RSR_PS, - OPCODE_WSR_PS, - OPCODE_XSR_PS, - OPCODE_RSR_EPC1, - OPCODE_WSR_EPC1, - OPCODE_XSR_EPC1, - OPCODE_RSR_EXCSAVE1, - OPCODE_WSR_EXCSAVE1, - OPCODE_XSR_EXCSAVE1, - OPCODE_RSR_EPC2, - OPCODE_WSR_EPC2, - OPCODE_XSR_EPC2, - OPCODE_RSR_EXCSAVE2, - OPCODE_WSR_EXCSAVE2, - OPCODE_XSR_EXCSAVE2, - OPCODE_RSR_EPC3, - OPCODE_WSR_EPC3, - OPCODE_XSR_EPC3, - OPCODE_RSR_EXCSAVE3, - OPCODE_WSR_EXCSAVE3, - OPCODE_XSR_EXCSAVE3, - OPCODE_RSR_EPC4, - OPCODE_WSR_EPC4, - OPCODE_XSR_EPC4, - OPCODE_RSR_EXCSAVE4, - OPCODE_WSR_EXCSAVE4, - OPCODE_XSR_EXCSAVE4, - OPCODE_RSR_EPC5, - OPCODE_WSR_EPC5, - OPCODE_XSR_EPC5, - OPCODE_RSR_EXCSAVE5, - OPCODE_WSR_EXCSAVE5, - OPCODE_XSR_EXCSAVE5, - OPCODE_RSR_EPC6, - OPCODE_WSR_EPC6, - OPCODE_XSR_EPC6, - OPCODE_RSR_EXCSAVE6, - OPCODE_WSR_EXCSAVE6, - OPCODE_XSR_EXCSAVE6, - OPCODE_RSR_EPC7, - OPCODE_WSR_EPC7, - OPCODE_XSR_EPC7, - OPCODE_RSR_EXCSAVE7, - OPCODE_WSR_EXCSAVE7, - OPCODE_XSR_EXCSAVE7, - OPCODE_RSR_EPS2, - OPCODE_WSR_EPS2, - OPCODE_XSR_EPS2, - OPCODE_RSR_EPS3, - OPCODE_WSR_EPS3, - OPCODE_XSR_EPS3, - OPCODE_RSR_EPS4, - OPCODE_WSR_EPS4, - OPCODE_XSR_EPS4, - OPCODE_RSR_EPS5, - OPCODE_WSR_EPS5, - OPCODE_XSR_EPS5, - OPCODE_RSR_EPS6, - OPCODE_WSR_EPS6, - OPCODE_XSR_EPS6, - OPCODE_RSR_EPS7, - OPCODE_WSR_EPS7, - OPCODE_XSR_EPS7, - OPCODE_RSR_EXCVADDR, - OPCODE_WSR_EXCVADDR, - OPCODE_XSR_EXCVADDR, - OPCODE_RSR_DEPC, - OPCODE_WSR_DEPC, - OPCODE_XSR_DEPC, - OPCODE_RSR_EXCCAUSE, - OPCODE_WSR_EXCCAUSE, - OPCODE_XSR_EXCCAUSE, - OPCODE_RSR_PRID, - OPCODE_RSR_VECBASE, - OPCODE_WSR_VECBASE, - OPCODE_XSR_VECBASE, - OPCODE_MUL16U, - OPCODE_MUL16S, - OPCODE_MULL, - OPCODE_MULUH, - OPCODE_MULSH, - OPCODE_MUL_AA_LL, - OPCODE_MUL_AA_HL, - OPCODE_MUL_AA_LH, - OPCODE_MUL_AA_HH, - OPCODE_UMUL_AA_LL, - OPCODE_UMUL_AA_HL, - OPCODE_UMUL_AA_LH, - OPCODE_UMUL_AA_HH, - OPCODE_MUL_AD_LL, - OPCODE_MUL_AD_HL, - OPCODE_MUL_AD_LH, - OPCODE_MUL_AD_HH, - OPCODE_MUL_DA_LL, - OPCODE_MUL_DA_HL, - OPCODE_MUL_DA_LH, - OPCODE_MUL_DA_HH, - OPCODE_MUL_DD_LL, - OPCODE_MUL_DD_HL, - OPCODE_MUL_DD_LH, - OPCODE_MUL_DD_HH, - OPCODE_MULA_AA_LL, - OPCODE_MULA_AA_HL, - OPCODE_MULA_AA_LH, - OPCODE_MULA_AA_HH, - OPCODE_MULS_AA_LL, - OPCODE_MULS_AA_HL, - OPCODE_MULS_AA_LH, - OPCODE_MULS_AA_HH, - OPCODE_MULA_AD_LL, - OPCODE_MULA_AD_HL, - OPCODE_MULA_AD_LH, - OPCODE_MULA_AD_HH, - OPCODE_MULS_AD_LL, - OPCODE_MULS_AD_HL, - OPCODE_MULS_AD_LH, - OPCODE_MULS_AD_HH, - OPCODE_MULA_DA_LL, - OPCODE_MULA_DA_HL, - OPCODE_MULA_DA_LH, - OPCODE_MULA_DA_HH, - OPCODE_MULS_DA_LL, - OPCODE_MULS_DA_HL, - OPCODE_MULS_DA_LH, - OPCODE_MULS_DA_HH, - OPCODE_MULA_DD_LL, - OPCODE_MULA_DD_HL, - OPCODE_MULA_DD_LH, - OPCODE_MULA_DD_HH, - OPCODE_MULS_DD_LL, - OPCODE_MULS_DD_HL, - OPCODE_MULS_DD_LH, - OPCODE_MULS_DD_HH, - OPCODE_MULA_DA_LL_LDDEC, - OPCODE_MULA_DA_LL_LDINC, - OPCODE_MULA_DA_HL_LDDEC, - OPCODE_MULA_DA_HL_LDINC, - OPCODE_MULA_DA_LH_LDDEC, - OPCODE_MULA_DA_LH_LDINC, - OPCODE_MULA_DA_HH_LDDEC, - OPCODE_MULA_DA_HH_LDINC, - OPCODE_MULA_DD_LL_LDDEC, - OPCODE_MULA_DD_LL_LDINC, - OPCODE_MULA_DD_HL_LDDEC, - OPCODE_MULA_DD_HL_LDINC, - OPCODE_MULA_DD_LH_LDDEC, - OPCODE_MULA_DD_LH_LDINC, - OPCODE_MULA_DD_HH_LDDEC, - OPCODE_MULA_DD_HH_LDINC, - OPCODE_LDDEC, - OPCODE_LDINC, - OPCODE_RSR_M0, - OPCODE_WSR_M0, - OPCODE_XSR_M0, - OPCODE_RSR_M1, - OPCODE_WSR_M1, - OPCODE_XSR_M1, - OPCODE_RSR_M2, - OPCODE_WSR_M2, - OPCODE_XSR_M2, - OPCODE_RSR_M3, - OPCODE_WSR_M3, - OPCODE_XSR_M3, - OPCODE_RSR_ACCLO, - OPCODE_WSR_ACCLO, - OPCODE_XSR_ACCLO, - OPCODE_RSR_ACCHI, - OPCODE_WSR_ACCHI, - OPCODE_XSR_ACCHI, - OPCODE_RFI, - OPCODE_WAITI, - OPCODE_RSR_INTERRUPT, - OPCODE_WSR_INTSET, - OPCODE_WSR_INTCLEAR, - OPCODE_RSR_INTENABLE, - OPCODE_WSR_INTENABLE, - OPCODE_XSR_INTENABLE, - OPCODE_BREAK, - OPCODE_BREAK_N, - OPCODE_RSR_DBREAKA0, - OPCODE_WSR_DBREAKA0, - OPCODE_XSR_DBREAKA0, - OPCODE_RSR_DBREAKC0, - OPCODE_WSR_DBREAKC0, - OPCODE_XSR_DBREAKC0, - OPCODE_RSR_DBREAKA1, - OPCODE_WSR_DBREAKA1, - OPCODE_XSR_DBREAKA1, - OPCODE_RSR_DBREAKC1, - OPCODE_WSR_DBREAKC1, - OPCODE_XSR_DBREAKC1, - OPCODE_RSR_IBREAKA0, - OPCODE_WSR_IBREAKA0, - OPCODE_XSR_IBREAKA0, - OPCODE_RSR_IBREAKA1, - OPCODE_WSR_IBREAKA1, - OPCODE_XSR_IBREAKA1, - OPCODE_RSR_IBREAKENABLE, - OPCODE_WSR_IBREAKENABLE, - OPCODE_XSR_IBREAKENABLE, - OPCODE_RSR_DEBUGCAUSE, - OPCODE_WSR_DEBUGCAUSE, - OPCODE_XSR_DEBUGCAUSE, - OPCODE_RSR_ICOUNT, - OPCODE_WSR_ICOUNT, - OPCODE_XSR_ICOUNT, - OPCODE_RSR_ICOUNTLEVEL, - OPCODE_WSR_ICOUNTLEVEL, - OPCODE_XSR_ICOUNTLEVEL, - OPCODE_RSR_DDR, - OPCODE_WSR_DDR, - OPCODE_XSR_DDR, - OPCODE_RFDO, - OPCODE_RFDD, - OPCODE_ANDB, - OPCODE_ANDBC, - OPCODE_ORB, - OPCODE_ORBC, - OPCODE_XORB, - OPCODE_ANY4, - OPCODE_ALL4, - OPCODE_ANY8, - OPCODE_ALL8, - OPCODE_BF, - OPCODE_BT, - OPCODE_MOVF, - OPCODE_MOVT, - OPCODE_RSR_BR, - OPCODE_WSR_BR, - OPCODE_XSR_BR, - OPCODE_RSR_CCOUNT, - OPCODE_WSR_CCOUNT, - OPCODE_XSR_CCOUNT, - OPCODE_RSR_CCOMPARE0, - OPCODE_WSR_CCOMPARE0, - OPCODE_XSR_CCOMPARE0, - OPCODE_RSR_CCOMPARE1, - OPCODE_WSR_CCOMPARE1, - OPCODE_XSR_CCOMPARE1, - OPCODE_RSR_CCOMPARE2, - OPCODE_WSR_CCOMPARE2, - OPCODE_XSR_CCOMPARE2, - OPCODE_IPF, - OPCODE_IHI, - OPCODE_IPFL, - OPCODE_IHU, - OPCODE_IIU, - OPCODE_III, - OPCODE_LICT, - OPCODE_LICW, - OPCODE_SICT, - OPCODE_SICW, - OPCODE_DHWB, - OPCODE_DHWBI, - OPCODE_DIWB, - OPCODE_DIWBI, - OPCODE_DHI, - OPCODE_DII, - OPCODE_DPFR, - OPCODE_DPFW, - OPCODE_DPFRO, - OPCODE_DPFWO, - OPCODE_DPFL, - OPCODE_DHU, - OPCODE_DIU, - OPCODE_SDCT, - OPCODE_LDCT, - OPCODE_RSR_PREFCTL, - OPCODE_WSR_PREFCTL, - OPCODE_XSR_PREFCTL, - OPCODE_IDTLB, - OPCODE_PDTLB, - OPCODE_RDTLB0, - OPCODE_RDTLB1, - OPCODE_WDTLB, - OPCODE_IITLB, - OPCODE_PITLB, - OPCODE_RITLB0, - OPCODE_RITLB1, - OPCODE_WITLB, - OPCODE_RSR_CPENABLE, - OPCODE_WSR_CPENABLE, - OPCODE_XSR_CPENABLE, - OPCODE_CLAMPS, - OPCODE_MIN, - OPCODE_MAX, - OPCODE_MINU, - OPCODE_MAXU, - OPCODE_NSA, - OPCODE_NSAU, - OPCODE_SEXT, - OPCODE_L32AI, - OPCODE_S32RI, - OPCODE_S32C1I, - OPCODE_RSR_SCOMPARE1, - OPCODE_WSR_SCOMPARE1, - OPCODE_XSR_SCOMPARE1, - OPCODE_RSR_ATOMCTL, - OPCODE_WSR_ATOMCTL, - OPCODE_XSR_ATOMCTL, - OPCODE_RER, - OPCODE_WER, - OPCODE_RUR_AE_OVF_SAR, - OPCODE_WUR_AE_OVF_SAR, - OPCODE_RUR_AE_BITHEAD, - OPCODE_WUR_AE_BITHEAD, - OPCODE_RUR_AE_TS_FTS_BU_BP, - OPCODE_WUR_AE_TS_FTS_BU_BP, - OPCODE_RUR_AE_SD_NO, - OPCODE_WUR_AE_SD_NO, - OPCODE_RUR_AE_OVERFLOW, - OPCODE_WUR_AE_OVERFLOW, - OPCODE_RUR_AE_SAR, - OPCODE_WUR_AE_SAR, - OPCODE_RUR_AE_BITPTR, - OPCODE_WUR_AE_BITPTR, - OPCODE_RUR_AE_BITSUSED, - OPCODE_WUR_AE_BITSUSED, - OPCODE_RUR_AE_TABLESIZE, - OPCODE_WUR_AE_TABLESIZE, - OPCODE_RUR_AE_FIRST_TS, - OPCODE_WUR_AE_FIRST_TS, - OPCODE_RUR_AE_NEXTOFFSET, - OPCODE_WUR_AE_NEXTOFFSET, - OPCODE_RUR_AE_SEARCHDONE, - OPCODE_WUR_AE_SEARCHDONE, - OPCODE_AE_LP16F_I, - OPCODE_AE_LP16F_IU, - OPCODE_AE_LP16F_X, - OPCODE_AE_LP16F_XU, - OPCODE_AE_LP24_I, - OPCODE_AE_LP24_IU, - OPCODE_AE_LP24_X, - OPCODE_AE_LP24_XU, - OPCODE_AE_LP24F_I, - OPCODE_AE_LP24F_IU, - OPCODE_AE_LP24F_X, - OPCODE_AE_LP24F_XU, - OPCODE_AE_LP16X2F_I, - OPCODE_AE_LP16X2F_IU, - OPCODE_AE_LP16X2F_X, - OPCODE_AE_LP16X2F_XU, - OPCODE_AE_LP24X2F_I, - OPCODE_AE_LP24X2F_IU, - OPCODE_AE_LP24X2F_X, - OPCODE_AE_LP24X2F_XU, - OPCODE_AE_LP24X2_I, - OPCODE_AE_LP24X2_IU, - OPCODE_AE_LP24X2_X, - OPCODE_AE_LP24X2_XU, - OPCODE_AE_SP16X2F_I, - OPCODE_AE_SP16X2F_IU, - OPCODE_AE_SP16X2F_X, - OPCODE_AE_SP16X2F_XU, - OPCODE_AE_SP24X2S_I, - OPCODE_AE_SP24X2S_IU, - OPCODE_AE_SP24X2S_X, - OPCODE_AE_SP24X2S_XU, - OPCODE_AE_SP24X2F_I, - OPCODE_AE_SP24X2F_IU, - OPCODE_AE_SP24X2F_X, - OPCODE_AE_SP24X2F_XU, - OPCODE_AE_SP16F_L_I, - OPCODE_AE_SP16F_L_IU, - OPCODE_AE_SP16F_L_X, - OPCODE_AE_SP16F_L_XU, - OPCODE_AE_SP24S_L_I, - OPCODE_AE_SP24S_L_IU, - OPCODE_AE_SP24S_L_X, - OPCODE_AE_SP24S_L_XU, - OPCODE_AE_SP24F_L_I, - OPCODE_AE_SP24F_L_IU, - OPCODE_AE_SP24F_L_X, - OPCODE_AE_SP24F_L_XU, - OPCODE_AE_LQ56_I, - OPCODE_AE_LQ56_IU, - OPCODE_AE_LQ56_X, - OPCODE_AE_LQ56_XU, - OPCODE_AE_LQ32F_I, - OPCODE_AE_LQ32F_IU, - OPCODE_AE_LQ32F_X, - OPCODE_AE_LQ32F_XU, - OPCODE_AE_SQ56S_I, - OPCODE_AE_SQ56S_IU, - OPCODE_AE_SQ56S_X, - OPCODE_AE_SQ56S_XU, - OPCODE_AE_SQ32F_I, - OPCODE_AE_SQ32F_IU, - OPCODE_AE_SQ32F_X, - OPCODE_AE_SQ32F_XU, - OPCODE_AE_ZEROP48, - OPCODE_AE_MOVP48, - OPCODE_AE_SELP24_LL, - OPCODE_AE_SELP24_LH, - OPCODE_AE_SELP24_HL, - OPCODE_AE_SELP24_HH, - OPCODE_AE_MOVTP24X2, - OPCODE_AE_MOVFP24X2, - OPCODE_AE_MOVTP48, - OPCODE_AE_MOVFP48, - OPCODE_AE_MOVPA24X2, - OPCODE_AE_TRUNCP24A32X2, - OPCODE_AE_CVTA32P24_L, - OPCODE_AE_CVTA32P24_H, - OPCODE_AE_CVTP24A16X2_LL, - OPCODE_AE_CVTP24A16X2_LH, - OPCODE_AE_CVTP24A16X2_HL, - OPCODE_AE_CVTP24A16X2_HH, - OPCODE_AE_TRUNCP24Q48X2, - OPCODE_AE_TRUNCP16, - OPCODE_AE_ROUNDSP24Q48SYM, - OPCODE_AE_ROUNDSP24Q48ASYM, - OPCODE_AE_ROUNDSP16Q48SYM, - OPCODE_AE_ROUNDSP16Q48ASYM, - OPCODE_AE_ROUNDSP16SYM, - OPCODE_AE_ROUNDSP16ASYM, - OPCODE_AE_ZEROQ56, - OPCODE_AE_MOVQ56, - OPCODE_AE_MOVTQ56, - OPCODE_AE_MOVFQ56, - OPCODE_AE_CVTQ48A32S, - OPCODE_AE_CVTQ48P24S_L, - OPCODE_AE_CVTQ48P24S_H, - OPCODE_AE_SATQ48S, - OPCODE_AE_TRUNCQ32, - OPCODE_AE_ROUNDSQ32SYM, - OPCODE_AE_ROUNDSQ32ASYM, - OPCODE_AE_TRUNCA32Q48, - OPCODE_AE_MOVAP24S_L, - OPCODE_AE_MOVAP24S_H, - OPCODE_AE_TRUNCA16P24S_L, - OPCODE_AE_TRUNCA16P24S_H, - OPCODE_AE_ADDP24, - OPCODE_AE_SUBP24, - OPCODE_AE_NEGP24, - OPCODE_AE_ABSP24, - OPCODE_AE_MAXP24S, - OPCODE_AE_MINP24S, - OPCODE_AE_MAXBP24S, - OPCODE_AE_MINBP24S, - OPCODE_AE_ADDSP24S, - OPCODE_AE_SUBSP24S, - OPCODE_AE_NEGSP24S, - OPCODE_AE_ABSSP24S, - OPCODE_AE_ANDP48, - OPCODE_AE_NANDP48, - OPCODE_AE_ORP48, - OPCODE_AE_XORP48, - OPCODE_AE_LTP24S, - OPCODE_AE_LEP24S, - OPCODE_AE_EQP24, - OPCODE_AE_ADDQ56, - OPCODE_AE_SUBQ56, - OPCODE_AE_NEGQ56, - OPCODE_AE_ABSQ56, - OPCODE_AE_MAXQ56S, - OPCODE_AE_MINQ56S, - OPCODE_AE_MAXBQ56S, - OPCODE_AE_MINBQ56S, - OPCODE_AE_ADDSQ56S, - OPCODE_AE_SUBSQ56S, - OPCODE_AE_NEGSQ56S, - OPCODE_AE_ABSSQ56S, - OPCODE_AE_ANDQ56, - OPCODE_AE_NANDQ56, - OPCODE_AE_ORQ56, - OPCODE_AE_XORQ56, - OPCODE_AE_SLLIP24, - OPCODE_AE_SRLIP24, - OPCODE_AE_SRAIP24, - OPCODE_AE_SLLSP24, - OPCODE_AE_SRLSP24, - OPCODE_AE_SRASP24, - OPCODE_AE_SLLISP24S, - OPCODE_AE_SLLSSP24S, - OPCODE_AE_SLLIQ56, - OPCODE_AE_SRLIQ56, - OPCODE_AE_SRAIQ56, - OPCODE_AE_SLLSQ56, - OPCODE_AE_SRLSQ56, - OPCODE_AE_SRASQ56, - OPCODE_AE_SLLAQ56, - OPCODE_AE_SRLAQ56, - OPCODE_AE_SRAAQ56, - OPCODE_AE_SLLISQ56S, - OPCODE_AE_SLLSSQ56S, - OPCODE_AE_SLLASQ56S, - OPCODE_AE_LTQ56S, - OPCODE_AE_LEQ56S, - OPCODE_AE_EQQ56, - OPCODE_AE_NSAQ56S, - OPCODE_AE_MULSRFQ32SP24S_H, - OPCODE_AE_MULSRFQ32SP24S_L, - OPCODE_AE_MULARFQ32SP24S_H, - OPCODE_AE_MULARFQ32SP24S_L, - OPCODE_AE_MULRFQ32SP24S_H, - OPCODE_AE_MULRFQ32SP24S_L, - OPCODE_AE_MULSFQ32SP24S_H, - OPCODE_AE_MULSFQ32SP24S_L, - OPCODE_AE_MULAFQ32SP24S_H, - OPCODE_AE_MULAFQ32SP24S_L, - OPCODE_AE_MULFQ32SP24S_H, - OPCODE_AE_MULFQ32SP24S_L, - OPCODE_AE_MULFS32P16S_LL, - OPCODE_AE_MULFP24S_LL, - OPCODE_AE_MULP24S_LL, - OPCODE_AE_MULFS32P16S_LH, - OPCODE_AE_MULFP24S_LH, - OPCODE_AE_MULP24S_LH, - OPCODE_AE_MULFS32P16S_HL, - OPCODE_AE_MULFP24S_HL, - OPCODE_AE_MULP24S_HL, - OPCODE_AE_MULFS32P16S_HH, - OPCODE_AE_MULFP24S_HH, - OPCODE_AE_MULP24S_HH, - OPCODE_AE_MULAFS32P16S_LL, - OPCODE_AE_MULAFP24S_LL, - OPCODE_AE_MULAP24S_LL, - OPCODE_AE_MULAFS32P16S_LH, - OPCODE_AE_MULAFP24S_LH, - OPCODE_AE_MULAP24S_LH, - OPCODE_AE_MULAFS32P16S_HL, - OPCODE_AE_MULAFP24S_HL, - OPCODE_AE_MULAP24S_HL, - OPCODE_AE_MULAFS32P16S_HH, - OPCODE_AE_MULAFP24S_HH, - OPCODE_AE_MULAP24S_HH, - OPCODE_AE_MULSFS32P16S_LL, - OPCODE_AE_MULSFP24S_LL, - OPCODE_AE_MULSP24S_LL, - OPCODE_AE_MULSFS32P16S_LH, - OPCODE_AE_MULSFP24S_LH, - OPCODE_AE_MULSP24S_LH, - OPCODE_AE_MULSFS32P16S_HL, - OPCODE_AE_MULSFP24S_HL, - OPCODE_AE_MULSP24S_HL, - OPCODE_AE_MULSFS32P16S_HH, - OPCODE_AE_MULSFP24S_HH, - OPCODE_AE_MULSP24S_HH, - OPCODE_AE_MULAFS56P24S_LL, - OPCODE_AE_MULAS56P24S_LL, - OPCODE_AE_MULAFS56P24S_LH, - OPCODE_AE_MULAS56P24S_LH, - OPCODE_AE_MULAFS56P24S_HL, - OPCODE_AE_MULAS56P24S_HL, - OPCODE_AE_MULAFS56P24S_HH, - OPCODE_AE_MULAS56P24S_HH, - OPCODE_AE_MULSFS56P24S_LL, - OPCODE_AE_MULSS56P24S_LL, - OPCODE_AE_MULSFS56P24S_LH, - OPCODE_AE_MULSS56P24S_LH, - OPCODE_AE_MULSFS56P24S_HL, - OPCODE_AE_MULSS56P24S_HL, - OPCODE_AE_MULSFS56P24S_HH, - OPCODE_AE_MULSS56P24S_HH, - OPCODE_AE_MULFQ32SP16S_L, - OPCODE_AE_MULFQ32SP16S_H, - OPCODE_AE_MULFQ32SP16U_L, - OPCODE_AE_MULFQ32SP16U_H, - OPCODE_AE_MULQ32SP16S_L, - OPCODE_AE_MULQ32SP16S_H, - OPCODE_AE_MULQ32SP16U_L, - OPCODE_AE_MULQ32SP16U_H, - OPCODE_AE_MULAFQ32SP16S_L, - OPCODE_AE_MULAFQ32SP16S_H, - OPCODE_AE_MULAFQ32SP16U_L, - OPCODE_AE_MULAFQ32SP16U_H, - OPCODE_AE_MULAQ32SP16S_L, - OPCODE_AE_MULAQ32SP16S_H, - OPCODE_AE_MULAQ32SP16U_L, - OPCODE_AE_MULAQ32SP16U_H, - OPCODE_AE_MULSFQ32SP16S_L, - OPCODE_AE_MULSFQ32SP16S_H, - OPCODE_AE_MULSFQ32SP16U_L, - OPCODE_AE_MULSFQ32SP16U_H, - OPCODE_AE_MULSQ32SP16S_L, - OPCODE_AE_MULSQ32SP16S_H, - OPCODE_AE_MULSQ32SP16U_L, - OPCODE_AE_MULSQ32SP16U_H, - OPCODE_AE_MULZAAQ32SP16S_LL, - OPCODE_AE_MULZAAFQ32SP16S_LL, - OPCODE_AE_MULZAAQ32SP16U_LL, - OPCODE_AE_MULZAAFQ32SP16U_LL, - OPCODE_AE_MULZAAQ32SP16S_HH, - OPCODE_AE_MULZAAFQ32SP16S_HH, - OPCODE_AE_MULZAAQ32SP16U_HH, - OPCODE_AE_MULZAAFQ32SP16U_HH, - OPCODE_AE_MULZAAQ32SP16S_LH, - OPCODE_AE_MULZAAFQ32SP16S_LH, - OPCODE_AE_MULZAAQ32SP16U_LH, - OPCODE_AE_MULZAAFQ32SP16U_LH, - OPCODE_AE_MULZASQ32SP16S_LL, - OPCODE_AE_MULZASFQ32SP16S_LL, - OPCODE_AE_MULZASQ32SP16U_LL, - OPCODE_AE_MULZASFQ32SP16U_LL, - OPCODE_AE_MULZASQ32SP16S_HH, - OPCODE_AE_MULZASFQ32SP16S_HH, - OPCODE_AE_MULZASQ32SP16U_HH, - OPCODE_AE_MULZASFQ32SP16U_HH, - OPCODE_AE_MULZASQ32SP16S_LH, - OPCODE_AE_MULZASFQ32SP16S_LH, - OPCODE_AE_MULZASQ32SP16U_LH, - OPCODE_AE_MULZASFQ32SP16U_LH, - OPCODE_AE_MULZSAQ32SP16S_LL, - OPCODE_AE_MULZSAFQ32SP16S_LL, - OPCODE_AE_MULZSAQ32SP16U_LL, - OPCODE_AE_MULZSAFQ32SP16U_LL, - OPCODE_AE_MULZSAQ32SP16S_HH, - OPCODE_AE_MULZSAFQ32SP16S_HH, - OPCODE_AE_MULZSAQ32SP16U_HH, - OPCODE_AE_MULZSAFQ32SP16U_HH, - OPCODE_AE_MULZSAQ32SP16S_LH, - OPCODE_AE_MULZSAFQ32SP16S_LH, - OPCODE_AE_MULZSAQ32SP16U_LH, - OPCODE_AE_MULZSAFQ32SP16U_LH, - OPCODE_AE_MULZSSQ32SP16S_LL, - OPCODE_AE_MULZSSFQ32SP16S_LL, - OPCODE_AE_MULZSSQ32SP16U_LL, - OPCODE_AE_MULZSSFQ32SP16U_LL, - OPCODE_AE_MULZSSQ32SP16S_HH, - OPCODE_AE_MULZSSFQ32SP16S_HH, - OPCODE_AE_MULZSSQ32SP16U_HH, - OPCODE_AE_MULZSSFQ32SP16U_HH, - OPCODE_AE_MULZSSQ32SP16S_LH, - OPCODE_AE_MULZSSFQ32SP16S_LH, - OPCODE_AE_MULZSSQ32SP16U_LH, - OPCODE_AE_MULZSSFQ32SP16U_LH, - OPCODE_AE_MULZAAFP24S_HH_LL, - OPCODE_AE_MULZAAP24S_HH_LL, - OPCODE_AE_MULZAAFP24S_HL_LH, - OPCODE_AE_MULZAAP24S_HL_LH, - OPCODE_AE_MULZASFP24S_HH_LL, - OPCODE_AE_MULZASP24S_HH_LL, - OPCODE_AE_MULZASFP24S_HL_LH, - OPCODE_AE_MULZASP24S_HL_LH, - OPCODE_AE_MULZSAFP24S_HH_LL, - OPCODE_AE_MULZSAP24S_HH_LL, - OPCODE_AE_MULZSAFP24S_HL_LH, - OPCODE_AE_MULZSAP24S_HL_LH, - OPCODE_AE_MULZSSFP24S_HH_LL, - OPCODE_AE_MULZSSP24S_HH_LL, - OPCODE_AE_MULZSSFP24S_HL_LH, - OPCODE_AE_MULZSSP24S_HL_LH, - OPCODE_AE_MULAAFP24S_HH_LL, - OPCODE_AE_MULAAP24S_HH_LL, - OPCODE_AE_MULAAFP24S_HL_LH, - OPCODE_AE_MULAAP24S_HL_LH, - OPCODE_AE_MULASFP24S_HH_LL, - OPCODE_AE_MULASP24S_HH_LL, - OPCODE_AE_MULASFP24S_HL_LH, - OPCODE_AE_MULASP24S_HL_LH, - OPCODE_AE_MULSAFP24S_HH_LL, - OPCODE_AE_MULSAP24S_HH_LL, - OPCODE_AE_MULSAFP24S_HL_LH, - OPCODE_AE_MULSAP24S_HL_LH, - OPCODE_AE_MULSSFP24S_HH_LL, - OPCODE_AE_MULSSP24S_HH_LL, - OPCODE_AE_MULSSFP24S_HL_LH, - OPCODE_AE_MULSSP24S_HL_LH, - OPCODE_AE_SHA32, - OPCODE_AE_VLDL32T, - OPCODE_AE_VLDL16T, - OPCODE_AE_VLDL16C, - OPCODE_AE_VLDSHT, - OPCODE_AE_LB, - OPCODE_AE_LBI, - OPCODE_AE_LBK, - OPCODE_AE_LBKI, - OPCODE_AE_DB, - OPCODE_AE_DBI, - OPCODE_AE_VLEL32T, - OPCODE_AE_VLEL16T, - OPCODE_AE_SB, - OPCODE_AE_SBI, - OPCODE_AE_VLES16C, - OPCODE_AE_SBF, - OPCODE_AE_SLAASQ56S, - OPCODE_AE_ADDBRBA32, - OPCODE_AE_MINABSSP24S, - OPCODE_AE_MAXABSSP24S, - OPCODE_AE_MINABSSQ56S, - OPCODE_AE_MAXABSSQ56S, - OPCODE_RUR_AE_CBEGIN0, - OPCODE_WUR_AE_CBEGIN0, - OPCODE_RUR_AE_CEND0, - OPCODE_WUR_AE_CEND0, - OPCODE_AE_LP24X2_C, - OPCODE_AE_SP24X2S_C, - OPCODE_AE_LP24X2F_C, - OPCODE_AE_SP24X2F_C, - OPCODE_AE_LP16X2F_C, - OPCODE_AE_SP16X2F_C, - OPCODE_AE_LP24_C, - OPCODE_AE_SP24S_L_C, - OPCODE_AE_LP24F_C, - OPCODE_AE_SP24F_L_C, - OPCODE_AE_LP16F_C, - OPCODE_AE_SP16F_L_C, - OPCODE_AE_LQ56_C, - OPCODE_AE_SQ56S_C, - OPCODE_AE_LQ32F_C, - OPCODE_AE_SQ32F_C -}; - - -/* Slot-specific opcode decode functions. */ - -static int -Slot_inst_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst_get (insn) == 0) - { - if (Field_op1_Slot_inst_get (insn) == 0) - { - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_r_Slot_inst_get (insn) == 0) - { - if (Field_m_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_n_Slot_inst_get (insn) == 0) - return OPCODE_ILL; - if (Field_m_Slot_inst_get (insn) == 2) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_RET; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_RETW; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_JX; - } - if (Field_m_Slot_inst_get (insn) == 3) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_CALLX0; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_CALLX4; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_CALLX8; - if (Field_n_Slot_inst_get (insn) == 3) - return OPCODE_CALLX12; - } - } - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_MOVSP; - if (Field_r_Slot_inst_get (insn) == 2) - { - if (Field_s_Slot_inst_get (insn) == 0) - { - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_ISYNC; - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RSYNC; - if (Field_t_Slot_inst_get (insn) == 2) - return OPCODE_ESYNC; - if (Field_t_Slot_inst_get (insn) == 3) - return OPCODE_DSYNC; - if (Field_t_Slot_inst_get (insn) == 8) - return OPCODE_EXCW; - if (Field_t_Slot_inst_get (insn) == 12) - return OPCODE_MEMW; - if (Field_t_Slot_inst_get (insn) == 13) - return OPCODE_EXTW; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_NOP; - } - } - if (Field_r_Slot_inst_get (insn) == 3) - { - if (Field_t_Slot_inst_get (insn) == 0) - { - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_RFE; - if (Field_s_Slot_inst_get (insn) == 2) - return OPCODE_RFDE; - if (Field_s_Slot_inst_get (insn) == 4) - return OPCODE_RFWO; - if (Field_s_Slot_inst_get (insn) == 5) - return OPCODE_RFWU; - } - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFI; - } - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_BREAK; - if (Field_r_Slot_inst_get (insn) == 5) - { - if (Field_s_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SYSCALL; - if (Field_s_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SIMCALL; - } - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_RSIL; - if (Field_r_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_WAITI; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_ANY4; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_ALL4; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_ANY8; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_ALL8; - } - if (Field_op2_Slot_inst_get (insn) == 1) - return OPCODE_AND; - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_OR; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_XOR; - if (Field_op2_Slot_inst_get (insn) == 4) - { - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSR; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSL; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8L; - if (Field_r_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8B; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_thi3_Slot_inst_get (insn) == 0) - return OPCODE_SSAI; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_RER; - if (Field_r_Slot_inst_get (insn) == 7) - return OPCODE_WER; - if (Field_r_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_ROTW; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_NSA; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_NSAU; - } - if (Field_op2_Slot_inst_get (insn) == 5) - { - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_RITLB0; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IITLB; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_PITLB; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_WITLB; - if (Field_r_Slot_inst_get (insn) == 7) - return OPCODE_RITLB1; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_RDTLB0; - if (Field_r_Slot_inst_get (insn) == 12 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IDTLB; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_PDTLB; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_WDTLB; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_RDTLB1; - } - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_NEG; - if (Field_s_Slot_inst_get (insn) == 1) - return OPCODE_ABS; - } - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_ADD; - if (Field_op2_Slot_inst_get (insn) == 9) - return OPCODE_ADDX2; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_ADDX4; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_ADDX8; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_SUB; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_SUBX2; - if (Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_SUBX4; - if (Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_SUBX8; - } - if (Field_op1_Slot_inst_get (insn) == 1) - { - if ((Field_op2_Slot_inst_get (insn) == 0 || - Field_op2_Slot_inst_get (insn) == 1)) - return OPCODE_SLLI; - if ((Field_op2_Slot_inst_get (insn) == 2 || - Field_op2_Slot_inst_get (insn) == 3)) - return OPCODE_SRAI; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_SRLI; - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_XSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_XSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_XSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_XSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_XSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_XSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_XSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_XSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_XSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 32) - return OPCODE_XSR_M0; - if (Field_sr_Slot_inst_get (insn) == 33) - return OPCODE_XSR_M1; - if (Field_sr_Slot_inst_get (insn) == 34) - return OPCODE_XSR_M2; - if (Field_sr_Slot_inst_get (insn) == 35) - return OPCODE_XSR_M3; - if (Field_sr_Slot_inst_get (insn) == 40) - return OPCODE_XSR_PREFCTL; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_XSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_XSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_XSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_XSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_XSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_XSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_XSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_XSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_XSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_XSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_XSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_XSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_XSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_XSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_XSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_XSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_XSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_XSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_XSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_XSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_XSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_XSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_XSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_XSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_XSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_XSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_XSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_XSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_XSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_XSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_XSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_XSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_XSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_XSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_XSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_XSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_XSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_XSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_XSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_XSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_XSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_XSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_XSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_XSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_XSR_CCOMPARE2; - } - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_SRC; - if (Field_op2_Slot_inst_get (insn) == 9 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRL; - if (Field_op2_Slot_inst_get (insn) == 10 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SLL; - if (Field_op2_Slot_inst_get (insn) == 11 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRA; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_MUL16U; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_MUL16S; - if (Field_op2_Slot_inst_get (insn) == 15) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_LICT; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_SICT; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_LICW; - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_SICW; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_LDCT; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_SDCT; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_RFDO; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFDD; - } - } - if (Field_op1_Slot_inst_get (insn) == 2) - { - if (Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_ANDB; - if (Field_op2_Slot_inst_get (insn) == 1) - return OPCODE_ANDBC; - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_ORB; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_ORBC; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_XORB; - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_MULL; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_MULUH; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_MULSH; - } - if (Field_op1_Slot_inst_get (insn) == 3) - { - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_RSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_RSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_RSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_RSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_RSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_RSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_RSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_RSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_RSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 32) - return OPCODE_RSR_M0; - if (Field_sr_Slot_inst_get (insn) == 33) - return OPCODE_RSR_M1; - if (Field_sr_Slot_inst_get (insn) == 34) - return OPCODE_RSR_M2; - if (Field_sr_Slot_inst_get (insn) == 35) - return OPCODE_RSR_M3; - if (Field_sr_Slot_inst_get (insn) == 40) - return OPCODE_RSR_PREFCTL; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_RSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_RSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_RSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_RSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_RSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_RSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_RSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_RSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_RSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_RSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_RSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 176) - return OPCODE_RSR_CONFIGID0; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_RSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_RSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_RSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_RSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_RSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_RSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_RSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_RSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_RSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_RSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_RSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_RSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_RSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_RSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 208) - return OPCODE_RSR_CONFIGID1; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_RSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_RSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_RSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_RSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_RSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_RSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_RSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_RSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 226) - return OPCODE_RSR_INTERRUPT; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_RSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_RSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_RSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_RSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_RSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_RSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 235) - return OPCODE_RSR_PRID; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_RSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_RSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_RSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_RSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_RSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_RSR_CCOMPARE2; - if (Field_sr_Slot_inst_get (insn) == 243) - return OPCODE_RSR_243; - } - if (Field_op2_Slot_inst_get (insn) == 1) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_WSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_WSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_WSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_WSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_WSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_WSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_WSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_WSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_WSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 32) - return OPCODE_WSR_M0; - if (Field_sr_Slot_inst_get (insn) == 33) - return OPCODE_WSR_M1; - if (Field_sr_Slot_inst_get (insn) == 34) - return OPCODE_WSR_M2; - if (Field_sr_Slot_inst_get (insn) == 35) - return OPCODE_WSR_M3; - if (Field_sr_Slot_inst_get (insn) == 40) - return OPCODE_WSR_PREFCTL; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_WSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_WSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_WSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_WSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_WSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_WSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_WSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_WSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_WSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_WSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_WSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 176) - return OPCODE_WSR_CONFIGID0; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_WSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_WSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_WSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_WSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_WSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_WSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_WSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_WSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_WSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_WSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_WSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_WSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_WSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_WSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_WSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_WSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_WSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_WSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_WSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_WSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_WSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_WSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 226) - return OPCODE_WSR_INTSET; - if (Field_sr_Slot_inst_get (insn) == 227) - return OPCODE_WSR_INTCLEAR; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_WSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_WSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_WSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_WSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_WSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_WSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_WSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_WSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_WSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_WSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_WSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_WSR_CCOMPARE2; - } - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_SEXT; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_CLAMPS; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_MIN; - if (Field_op2_Slot_inst_get (insn) == 5) - return OPCODE_MAX; - if (Field_op2_Slot_inst_get (insn) == 6) - return OPCODE_MINU; - if (Field_op2_Slot_inst_get (insn) == 7) - return OPCODE_MAXU; - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_MOVEQZ; - if (Field_op2_Slot_inst_get (insn) == 9) - return OPCODE_MOVNEZ; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_MOVLTZ; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_MOVGEZ; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_MOVF; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_MOVT; - if (Field_op2_Slot_inst_get (insn) == 14) - { - if (Field_st_Slot_inst_get (insn) == 231) - return OPCODE_RUR_THREADPTR; - if (Field_st_Slot_inst_get (insn) == 240) - return OPCODE_RUR_AE_OVF_SAR; - if (Field_st_Slot_inst_get (insn) == 241) - return OPCODE_RUR_AE_BITHEAD; - if (Field_st_Slot_inst_get (insn) == 242) - return OPCODE_RUR_AE_TS_FTS_BU_BP; - if (Field_st_Slot_inst_get (insn) == 243) - return OPCODE_RUR_AE_SD_NO; - if (Field_st_Slot_inst_get (insn) == 246) - return OPCODE_RUR_AE_CBEGIN0; - if (Field_st_Slot_inst_get (insn) == 247) - return OPCODE_RUR_AE_CEND0; - } - if (Field_op2_Slot_inst_get (insn) == 15) - { - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_WUR_THREADPTR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_WUR_AE_OVF_SAR; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_WUR_AE_BITHEAD; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_WUR_AE_TS_FTS_BU_BP; - if (Field_sr_Slot_inst_get (insn) == 243) - return OPCODE_WUR_AE_SD_NO; - if (Field_sr_Slot_inst_get (insn) == 246) - return OPCODE_WUR_AE_CBEGIN0; - if (Field_sr_Slot_inst_get (insn) == 247) - return OPCODE_WUR_AE_CEND0; - } - } - if ((Field_op1_Slot_inst_get (insn) == 4 || - Field_op1_Slot_inst_get (insn) == 5)) - return OPCODE_EXTUI; - if (Field_op1_Slot_inst_get (insn) == 9) - { - if (Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_L32E; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_S32E; - } - } - if (Field_op0_Slot_inst_get (insn) == 1) - return OPCODE_L32R; - if (Field_op0_Slot_inst_get (insn) == 2) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_L8UI; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_L16UI; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_L32I; - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_S8I; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_S16I; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_S32I; - if (Field_r_Slot_inst_get (insn) == 7) - { - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_DPFR; - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_DPFW; - if (Field_t_Slot_inst_get (insn) == 2) - return OPCODE_DPFRO; - if (Field_t_Slot_inst_get (insn) == 3) - return OPCODE_DPFWO; - if (Field_t_Slot_inst_get (insn) == 4) - return OPCODE_DHWB; - if (Field_t_Slot_inst_get (insn) == 5) - return OPCODE_DHWBI; - if (Field_t_Slot_inst_get (insn) == 6) - return OPCODE_DHI; - if (Field_t_Slot_inst_get (insn) == 7) - return OPCODE_DII; - if (Field_t_Slot_inst_get (insn) == 8) - { - if (Field_op1_Slot_inst_get (insn) == 0) - return OPCODE_DPFL; - if (Field_op1_Slot_inst_get (insn) == 2) - return OPCODE_DHU; - if (Field_op1_Slot_inst_get (insn) == 3) - return OPCODE_DIU; - if (Field_op1_Slot_inst_get (insn) == 4) - return OPCODE_DIWB; - if (Field_op1_Slot_inst_get (insn) == 5) - return OPCODE_DIWBI; - } - if (Field_t_Slot_inst_get (insn) == 12) - return OPCODE_IPF; - if (Field_t_Slot_inst_get (insn) == 13) - { - if (Field_op1_Slot_inst_get (insn) == 0) - return OPCODE_IPFL; - if (Field_op1_Slot_inst_get (insn) == 2) - return OPCODE_IHU; - if (Field_op1_Slot_inst_get (insn) == 3) - return OPCODE_IIU; - } - if (Field_t_Slot_inst_get (insn) == 14) - return OPCODE_IHI; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_III; - } - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_L16SI; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_MOVI; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_L32AI; - if (Field_r_Slot_inst_get (insn) == 12) - return OPCODE_ADDI; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_ADDMI; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_S32C1I; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_S32RI; - } - if (Field_op0_Slot_inst_get (insn) == 4) - { - if (Field_ae_r10_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_I; - if (Field_ae_r10_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_X; - if (Field_ae_r10_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_I; - if (Field_ae_r10_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_X; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_IU; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_XU; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_CVTQ48A32S; - if (Field_ae_r10_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_IU; - if (Field_ae_r10_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_ae_s3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVP48; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVPA24X2; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_CVTA32P24_L; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_LL; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_HL; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVAP24S_L; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCA16P24S_L; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP16X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24X2_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCP24A32X2; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_CVTA32P24_H; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_LH; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_HH; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVAP24S_H; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCA16P24S_H; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_I; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_X; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_TRUNCA32Q48; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_I; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_X; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_NSAQ56S; - if (Field_ae_r32_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_IU; - if (Field_ae_r32_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_XU; - if (Field_ae_r32_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_IU; - if (Field_ae_r32_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_XU; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRLIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRAIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLISQ56S; - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SHA32; - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLDL32T; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SLLAQ56; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLDL16T; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SRLAQ56; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LBK; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SRAAQ56; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLEL32T; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SLLASQ56S; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLEL16T; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_MOVTQ56; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_MOVFQ56; - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LL_LDINC; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HL_LDINC; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LH_LDINC; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HH_LDINC; - } - if (Field_op2_Slot_inst_get (insn) == 1) - { - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LL_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HL_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LH_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HH_LDDEC; - } - if (Field_op2_Slot_inst_get (insn) == 2) - { - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_LL; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_HL; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_LH; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_HH; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LL; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HL; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LH; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HH; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_LL; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_HL; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_LH; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_HH; - } - if (Field_op2_Slot_inst_get (insn) == 3) - { - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_LL; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_HL; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_LH; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_HH; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_LL; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_HL; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_LH; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_HH; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_LL; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_HL; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_LH; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_HH; - } - if (Field_op2_Slot_inst_get (insn) == 4) - { - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LL_LDINC; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HL_LDINC; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LH_LDINC; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HH_LDINC; - } - if (Field_op2_Slot_inst_get (insn) == 5) - { - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LL_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HL_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LH_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HH_LDDEC; - } - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_LL; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_HL; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_LH; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_HH; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LL; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HL; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LH; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HH; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_LL; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_HL; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_LH; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_HH; - } - if (Field_op2_Slot_inst_get (insn) == 7) - { - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_LL; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_HL; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_LH; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_HH; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_LL; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_HL; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_LH; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_HH; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_LL; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_HL; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_LH; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_HH; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_LL; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_HL; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_LH; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_HH; - } - if (Field_op2_Slot_inst_get (insn) == 8) - { - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_rhi_Slot_inst_get (insn) == 0) - return OPCODE_LDINC; - } - if (Field_op2_Slot_inst_get (insn) == 9) - { - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_rhi_Slot_inst_get (insn) == 0) - return OPCODE_LDDEC; - } - if (Field_r_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_OVERFLOW; - if (Field_r_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_SBI; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_SAR; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_DB; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_SB; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_BITPTR; - if (Field_r_Slot_inst_get (insn) == 3 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_BITSUSED; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_TABLESIZE; - if (Field_r_Slot_inst_get (insn) == 5 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_FIRST_TS; - if (Field_r_Slot_inst_get (insn) == 6 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_NEXTOFFSET; - if (Field_r_Slot_inst_get (insn) == 7 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_SEARCHDONE; - if (Field_r_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_VLDSHT; - if (Field_r_Slot_inst_get (insn) == 12 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_VLES16C; - if (Field_r_Slot_inst_get (insn) == 13 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SBF; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_VLDL16C; - if (Field_s_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLSQ56; - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LB; - if (Field_s_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRLSQ56; - if (Field_s_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRASQ56; - if (Field_s_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLSSQ56S; - if (Field_s_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVQ56; - if (Field_s_Slot_inst_get (insn) == 8 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_OVERFLOW; - if (Field_s_Slot_inst_get (insn) == 9 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_SAR; - if (Field_s_Slot_inst_get (insn) == 10 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_BITPTR; - if (Field_s_Slot_inst_get (insn) == 11 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_BITSUSED; - if (Field_s_Slot_inst_get (insn) == 12 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_TABLESIZE; - if (Field_s_Slot_inst_get (insn) == 13 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_FIRST_TS; - if (Field_s_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_NEXTOFFSET; - if (Field_s_Slot_inst_get (insn) == 15 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_SEARCHDONE; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_LBKI; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_r_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_DBI; - if (Field_t_Slot_inst_get (insn) == 2 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_LBI; - } - if (Field_op0_Slot_inst_get (insn) == 5) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_CALL0; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_CALL4; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_CALL8; - if (Field_n_Slot_inst_get (insn) == 3) - return OPCODE_CALL12; - } - if (Field_op0_Slot_inst_get (insn) == 6) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_J; - if (Field_n_Slot_inst_get (insn) == 1) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_BEQZ; - if (Field_m_Slot_inst_get (insn) == 1) - return OPCODE_BNEZ; - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTZ; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEZ; - } - if (Field_n_Slot_inst_get (insn) == 2) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_BEQI; - if (Field_m_Slot_inst_get (insn) == 1) - return OPCODE_BNEI; - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTI; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEI; - } - if (Field_n_Slot_inst_get (insn) == 3) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_ENTRY; - if (Field_m_Slot_inst_get (insn) == 1) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_BF; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_BT; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_LOOP; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_LOOPNEZ; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_LOOPGTZ; - } - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTUI; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEUI; - } - } - if (Field_op0_Slot_inst_get (insn) == 7) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_BNONE; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_BEQ; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_BLT; - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_BLTU; - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_BALL; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_BBC; - if ((Field_r_Slot_inst_get (insn) == 6 || - Field_r_Slot_inst_get (insn) == 7)) - return OPCODE_BBCI; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_BANY; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_BNE; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_BGE; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_BGEU; - if (Field_r_Slot_inst_get (insn) == 12) - return OPCODE_BNALL; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_BBS; - if ((Field_r_Slot_inst_get (insn) == 14 || - Field_r_Slot_inst_get (insn) == 15)) - return OPCODE_BBSI; - } - return 0; -} - -static int -Slot_inst16b_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst16b_get (insn) == 12) - { - if (Field_i_Slot_inst16b_get (insn) == 0) - return OPCODE_MOVI_N; - if (Field_i_Slot_inst16b_get (insn) == 1) - { - if (Field_z_Slot_inst16b_get (insn) == 0) - return OPCODE_BEQZ_N; - if (Field_z_Slot_inst16b_get (insn) == 1) - return OPCODE_BNEZ_N; - } - } - if (Field_op0_Slot_inst16b_get (insn) == 13) - { - if (Field_r_Slot_inst16b_get (insn) == 0) - return OPCODE_MOV_N; - if (Field_r_Slot_inst16b_get (insn) == 15) - { - if (Field_t_Slot_inst16b_get (insn) == 0) - return OPCODE_RET_N; - if (Field_t_Slot_inst16b_get (insn) == 1) - return OPCODE_RETW_N; - if (Field_t_Slot_inst16b_get (insn) == 2) - return OPCODE_BREAK_N; - if (Field_t_Slot_inst16b_get (insn) == 3 && - Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_NOP_N; - if (Field_t_Slot_inst16b_get (insn) == 6 && - Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_ILL_N; - } - } - return 0; -} - -static int -Slot_inst16a_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst16a_get (insn) == 8) - return OPCODE_L32I_N; - if (Field_op0_Slot_inst16a_get (insn) == 9) - return OPCODE_S32I_N; - if (Field_op0_Slot_inst16a_get (insn) == 10) - return OPCODE_ADD_N; - if (Field_op0_Slot_inst16a_get (insn) == 11) - return OPCODE_ADDI_N; - return 0; -} - -static int -Slot_ae_slot0_decode (const xtensa_insnbuf insn) -{ - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_ADDBRBA32; - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 2 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_C; - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 2 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_C; - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 2 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_C; - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf353_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_C; - if (Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_C; - if (Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_C; - if (Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_get (insn) == 2 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_C; - if (Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_C; - if (Field_combined1b97e84f_fld93_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld90_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_C; - if (Field_combined4b12daa6_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld85_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld122_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld119_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld97_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SELP24_LH; - if (Field_combined4b12daa6_fld122_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld85_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld119_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld97_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SELP24_HH; - if (Field_combined4b12daa6_fld122_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld85_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld119_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld97_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SELP24_HL; - if (Field_combined4b12daa6_fld85_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld122_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld119_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld97_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld115_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SELP24_LL; - if (Field_ftsf212ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_J; - if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_EXTUI; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BGEZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BLTZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 8 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BEQZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 9 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BNEZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVI; - if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 88 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRAI; - if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 96 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SLLI; - if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 123 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVTQ56; - if (Field_ftsf216ae_slot0_Slot_ae_slot0_get (insn) == 418 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_HH; - if (Field_ftsf217_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4 && - Field_ae_r20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_L32I; - if (Field_ftsf218ae_slot0_Slot_ae_slot0_get (insn) == 419 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_I; - if (Field_ftsf219ae_slot0_Slot_ae_slot0_get (insn) == 420 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_HL; - if (Field_ftsf220ae_slot0_Slot_ae_slot0_get (insn) == 421 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_IU; - if (Field_ftsf221ae_slot0_Slot_ae_slot0_get (insn) == 422 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_X; - if (Field_ftsf222ae_slot0_Slot_ae_slot0_get (insn) == 423 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_XU; - if (Field_ftsf223ae_slot0_Slot_ae_slot0_get (insn) == 424 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_LH; - if (Field_ftsf224ae_slot0_Slot_ae_slot0_get (insn) == 425 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_I; - if (Field_ftsf225ae_slot0_Slot_ae_slot0_get (insn) == 426 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_IU; - if (Field_ftsf226ae_slot0_Slot_ae_slot0_get (insn) == 427 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_XU; - if (Field_ftsf227ae_slot0_Slot_ae_slot0_get (insn) == 428 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_X; - if (Field_ftsf228ae_slot0_Slot_ae_slot0_get (insn) == 429 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_I; - if (Field_ftsf229ae_slot0_Slot_ae_slot0_get (insn) == 430 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_IU; - if (Field_ftsf230ae_slot0_Slot_ae_slot0_get (insn) == 431 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_X; - if (Field_ftsf231ae_slot0_Slot_ae_slot0_get (insn) == 432 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_LL; - if (Field_ftsf232ae_slot0_Slot_ae_slot0_get (insn) == 433 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_XU; - if (Field_ftsf233ae_slot0_Slot_ae_slot0_get (insn) == 434 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_I; - if (Field_ftsf234ae_slot0_Slot_ae_slot0_get (insn) == 435 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_XU; - if (Field_ftsf235ae_slot0_Slot_ae_slot0_get (insn) == 436 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_IU; - if (Field_ftsf236ae_slot0_Slot_ae_slot0_get (insn) == 437 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_I; - if (Field_ftsf237ae_slot0_Slot_ae_slot0_get (insn) == 438 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_IU; - if (Field_ftsf238ae_slot0_Slot_ae_slot0_get (insn) == 439 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_X; - if (Field_ftsf239ae_slot0_Slot_ae_slot0_get (insn) == 440 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_X; - if (Field_ftsf240ae_slot0_Slot_ae_slot0_get (insn) == 441 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_XU; - if (Field_ftsf241ae_slot0_Slot_ae_slot0_get (insn) == 442 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_I; - if (Field_ftsf242ae_slot0_Slot_ae_slot0_get (insn) == 443 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_X; - if (Field_ftsf243ae_slot0_Slot_ae_slot0_get (insn) == 444 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_IU; - if (Field_ftsf244ae_slot0_Slot_ae_slot0_get (insn) == 445 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_XU; - if (Field_ftsf245ae_slot0_Slot_ae_slot0_get (insn) == 446 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVPA24X2; - if (Field_ftsf246ae_slot0_Slot_ae_slot0_get (insn) == 447 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_I; - if (Field_ftsf247ae_slot0_Slot_ae_slot0_get (insn) == 450 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_IU; - if (Field_ftsf248ae_slot0_Slot_ae_slot0_get (insn) == 451 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_X; - if (Field_ftsf249ae_slot0_Slot_ae_slot0_get (insn) == 452 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_X; - if (Field_ftsf250ae_slot0_Slot_ae_slot0_get (insn) == 453 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_XU; - if (Field_ftsf251ae_slot0_Slot_ae_slot0_get (insn) == 454 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_I; - if (Field_ftsf252ae_slot0_Slot_ae_slot0_get (insn) == 455 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_IU; - if (Field_ftsf253ae_slot0_Slot_ae_slot0_get (insn) == 456 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_XU; - if (Field_ftsf254ae_slot0_Slot_ae_slot0_get (insn) == 457 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_X; - if (Field_ftsf255ae_slot0_Slot_ae_slot0_get (insn) == 458 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_XU; - if (Field_ftsf256ae_slot0_Slot_ae_slot0_get (insn) == 459 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_IU; - if (Field_ftsf257ae_slot0_Slot_ae_slot0_get (insn) == 460 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_I; - if (Field_ftsf258ae_slot0_Slot_ae_slot0_get (insn) == 461 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_X; - if (Field_ftsf259ae_slot0_Slot_ae_slot0_get (insn) == 462 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_XU; - if (Field_ftsf260ae_slot0_Slot_ae_slot0_get (insn) == 463 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_I; - if (Field_ftsf261ae_slot0_Slot_ae_slot0_get (insn) == 464 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_I; - if (Field_ftsf262ae_slot0_Slot_ae_slot0_get (insn) == 465 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_IU; - if (Field_ftsf263ae_slot0_Slot_ae_slot0_get (insn) == 466 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_X; - if (Field_ftsf264ae_slot0_Slot_ae_slot0_get (insn) == 467 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_IU; - if (Field_ftsf265ae_slot0_Slot_ae_slot0_get (insn) == 468 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_XU; - if (Field_ftsf266ae_slot0_Slot_ae_slot0_get (insn) == 469 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_X; - if (Field_ftsf267ae_slot0_Slot_ae_slot0_get (insn) == 470 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_XU; - if (Field_ftsf268ae_slot0_Slot_ae_slot0_get (insn) == 471 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_TRUNCP24A32X2; - if (Field_ftsf269ae_slot0_Slot_ae_slot0_get (insn) == 472 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_I; - if (Field_ftsf270ae_slot0_Slot_ae_slot0_get (insn) == 946 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_I; - if (Field_ftsf271ae_slot0_Slot_ae_slot0_get (insn) == 947 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_IU; - if (Field_ftsf272ae_slot0_Slot_ae_slot0_get (insn) == 948 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_I; - if (Field_ftsf273ae_slot0_Slot_ae_slot0_get (insn) == 949 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_X; - if (Field_ftsf274ae_slot0_Slot_ae_slot0_get (insn) == 950 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_XU; - if (Field_ftsf275ae_slot0_Slot_ae_slot0_get (insn) == 951 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_I; - if (Field_ftsf276ae_slot0_Slot_ae_slot0_get (insn) == 952 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_IU; - if (Field_ftsf277ae_slot0_Slot_ae_slot0_get (insn) == 953 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_IU; - if (Field_ftsf278ae_slot0_Slot_ae_slot0_get (insn) == 954 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_X; - if (Field_ftsf279ae_slot0_Slot_ae_slot0_get (insn) == 15280 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTQ48A32S; - if (Field_ftsf281ae_slot0_Slot_ae_slot0_get (insn) == 60977 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_JX; - if (Field_ftsf282ae_slot0_Slot_ae_slot0_get (insn) == 61041 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SSR; - if (Field_ftsf283ae_slot0_Slot_ae_slot0_get (insn) == 30577 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf352ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_NOP; - if (Field_ftsf284ae_slot0_Slot_ae_slot0_get (insn) == 7641 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf354ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSA8B; - if (Field_ftsf286ae_slot0_Slot_ae_slot0_get (insn) == 3821 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf356ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSA8L; - if (Field_ftsf288ae_slot0_Slot_ae_slot0_get (insn) == 1911 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf359ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSL; - if (Field_ftsf290ae_slot0_Slot_ae_slot0_get (insn) == 478 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s8_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_LQ56_XU; - if (Field_ftsf292ae_slot0_Slot_ae_slot0_get (insn) == 1913 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ALL8; - if (Field_ftsf293_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBCI; - if (Field_ftsf293_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBSI; - if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 1915 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ANY8; - if (Field_ftsf295ae_slot0_Slot_ae_slot0_get (insn) == 959 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf358ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSAI; - if (Field_ftsf296ae_slot0_Slot_ae_slot0_get (insn) == 480 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_IU; - if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 962 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_I; - if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 963 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_IU; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 964 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLIQ56; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 965 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SRAIQ56; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 966 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SRLIQ56; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 968 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLISQ56S; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3868 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ABS; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3869 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_NEG; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3870 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRA; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3871 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRL; - if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7752 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf321_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVP48; - if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7753 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf353_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ANY4; - if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 31016 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf321_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVQ56; - if (Field_ftsf303ae_slot0_Slot_ae_slot0_get (insn) == 31017 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf321_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SLLSSQ56S; - if (Field_ftsf304ae_slot0_Slot_ae_slot0_get (insn) == 15509 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf369ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRASQ56; - if (Field_ftsf306ae_slot0_Slot_ae_slot0_get (insn) == 7755 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf368ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRLSQ56; - if (Field_ftsf308ae_slot0_Slot_ae_slot0_get (insn) == 1939 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf366ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SLLSQ56; - if (Field_ftsf309ae_slot0_Slot_ae_slot0_get (insn) == 485 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ALL4; - if (Field_ftsf310ae_slot0_Slot_ae_slot0_get (insn) == 972 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_X; - if (Field_ftsf311ae_slot0_Slot_ae_slot0_get (insn) == 973 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_XU; - if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 7792 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTA32P24_H; - if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 7793 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTA32P24_L; - if (Field_ftsf314ae_slot0_Slot_ae_slot0_get (insn) == 7794 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVAP24S_H; - if (Field_ftsf315ae_slot0_Slot_ae_slot0_get (insn) == 7795 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_TRUNCA16P24S_L; - if (Field_ftsf316ae_slot0_Slot_ae_slot0_get (insn) == 7796 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVAP24S_L; - if (Field_ftsf317ae_slot0_Slot_ae_slot0_get (insn) == 7797 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf353_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_NSAQ56S; - if (Field_ftsf318ae_slot0_Slot_ae_slot0_get (insn) == 3899 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf365ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_TRUNCA32Q48; - if (Field_ftsf319_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_ftsf361ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BT; - if (Field_ftsf320ae_slot0_Slot_ae_slot0_get (insn) == 975 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_TRUNCA16P24S_H; - if (Field_ftsf321_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_ae_s20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BLTUI; - if (Field_ftsf321_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld101_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld88_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld39_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLAASQ56S; - if (Field_ftsf322ae_slot0_Slot_ae_slot0_get (insn) == 3920 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVFQ56; - if (Field_ftsf323ae_slot0_Slot_ae_slot0_get (insn) == 3921 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLAQ56; - if (Field_ftsf324ae_slot0_Slot_ae_slot0_get (insn) == 3922 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLASQ56S; - if (Field_ftsf325ae_slot0_Slot_ae_slot0_get (insn) == 3923 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SLL; - if (Field_ftsf326ae_slot0_Slot_ae_slot0_get (insn) == 981 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf357_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRAAQ56; - if (Field_ftsf328ae_slot0_Slot_ae_slot0_get (insn) == 491 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRLAQ56; - if (Field_ftsf329ae_slot0_Slot_ae_slot0_get (insn) == 31 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SQ32F_XU; - if (Field_ftsf353_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_C; - if (Field_imm8_Slot_ae_slot0_get (insn) == 178 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADD; - if (Field_imm8_Slot_ae_slot0_get (insn) == 179 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX8; - if (Field_imm8_Slot_ae_slot0_get (insn) == 180 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX2; - if (Field_imm8_Slot_ae_slot0_get (insn) == 181 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AND; - if (Field_imm8_Slot_ae_slot0_get (insn) == 182 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ANDB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 183 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ANDBC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 184 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX4; - if (Field_imm8_Slot_ae_slot0_get (insn) == 185 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_CLAMPS; - if (Field_imm8_Slot_ae_slot0_get (insn) == 186 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MAX; - if (Field_imm8_Slot_ae_slot0_get (insn) == 187 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MIN; - if (Field_imm8_Slot_ae_slot0_get (insn) == 188 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MAXU; - if (Field_imm8_Slot_ae_slot0_get (insn) == 189 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MINU; - if (Field_imm8_Slot_ae_slot0_get (insn) == 190 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVEQZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 191 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVF; - if (Field_imm8_Slot_ae_slot0_get (insn) == 194 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVGEZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 195 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ORB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 196 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVLTZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 197 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ORBC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 198 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SEXT; - if (Field_imm8_Slot_ae_slot0_get (insn) == 199 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 200 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVNEZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 201 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRLI; - if (Field_imm8_Slot_ae_slot0_get (insn) == 202 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 203 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX4; - if (Field_imm8_Slot_ae_slot0_get (insn) == 204 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX2; - if (Field_imm8_Slot_ae_slot0_get (insn) == 205 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX8; - if (Field_imm8_Slot_ae_slot0_get (insn) == 206 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_XOR; - if (Field_imm8_Slot_ae_slot0_get (insn) == 207 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_XORB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 208 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVT; - if (Field_imm8_Slot_ae_slot0_get (insn) == 224 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_OR; - if (Field_imm8_Slot_ae_slot0_get (insn) == 244 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_r32_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SQ32F_X; - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5) - return OPCODE_L32R; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP16X2F_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 6 && - Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP24F_L_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 7 && - Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP24S_L_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 8 && - Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP24X2F_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 9 && - Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP24X2S_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 10 && - Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_LQ56_C; - if (Field_r_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_BNE; - if (Field_r_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_BNONE; - if (Field_r_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L16SI; - if (Field_r_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L8UI; - if (Field_r_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_ADDI; - if (Field_r_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L16UI; - if (Field_r_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BALL; - if (Field_r_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S16I; - if (Field_r_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BANY; - if (Field_r_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S32I; - if (Field_r_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBC; - if (Field_r_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S8I; - if (Field_r_Slot_ae_slot0_get (insn) == 8 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_ADDMI; - if (Field_r_Slot_ae_slot0_get (insn) == 9 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBS; - if (Field_r_Slot_ae_slot0_get (insn) == 10 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BEQ; - if (Field_r_Slot_ae_slot0_get (insn) == 11 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BGEU; - if (Field_r_Slot_ae_slot0_get (insn) == 12 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BGE; - if (Field_r_Slot_ae_slot0_get (insn) == 13 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BLT; - if (Field_r_Slot_ae_slot0_get (insn) == 14 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BLTU; - if (Field_r_Slot_ae_slot0_get (insn) == 15 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BNALL; - if (Field_t_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BEQI; - if (Field_t_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BGEI; - if (Field_t_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BGEUI; - if (Field_t_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BNEI; - if (Field_t_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BLTI; - if (Field_t_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_r_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BF; - return 0; -} - -static int -Slot_ae_slot1_decode (const xtensa_insnbuf insn) -{ - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 288 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULRFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 289 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULRFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 290 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULARFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 291 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULARFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 292 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSRFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 293 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSRFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 294 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 295 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 296 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 297 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 298 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 299 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP24S_L; - if (Field_combined1b97e84f_fld17_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld76_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf208_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld73_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld62_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld24_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld70_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld58_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5 && - Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MINABSSQ56S; - if (Field_combined1b97e84f_fld49_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf338_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld54_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r32_Slot_ae_slot1_get (insn) == 2 && - Field_combined1b97e84f_fld51_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld23_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MINABSSP24S; - if (Field_combined1b97e84f_fld49_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf338_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld54_Slot_ae_slot1_get (insn) == 0 && - Field_ae_r32_Slot_ae_slot1_get (insn) == 2 && - Field_combined1b97e84f_fld51_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld23_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MAXABSSP24S; - if (Field_combined1b97e84f_fld54_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld17_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld76_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf208_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld73_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld62_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld24_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld70_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld58_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MAXABSSQ56S; - if (Field_ftsf100ae_slot1_Slot_ae_slot1_get (insn) == 115 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_NEGSP24S; - if (Field_ftsf101ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf348ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ABSSP24S; - if (Field_ftsf103ae_slot1_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf349ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_NEGP24; - if (Field_ftsf104ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MAXBQ56S; - if (Field_ftsf105ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MINBQ56S; - if (Field_ftsf106ae_slot1_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ae_r32_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_EQQ56; - if (Field_ftsf107ae_slot1_Slot_ae_slot1_get (insn) == 48 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ADDSQ56S; - if (Field_ftsf108ae_slot1_Slot_ae_slot1_get (insn) == 49 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ANDQ56; - if (Field_ftsf109ae_slot1_Slot_ae_slot1_get (insn) == 50 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MAXQ56S; - if (Field_ftsf110ae_slot1_Slot_ae_slot1_get (insn) == 51 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ORQ56; - if (Field_ftsf111ae_slot1_Slot_ae_slot1_get (insn) == 52 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MINQ56S; - if (Field_ftsf112ae_slot1_Slot_ae_slot1_get (insn) == 53 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_SUBQ56; - if (Field_ftsf113ae_slot1_Slot_ae_slot1_get (insn) == 54 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_SUBSQ56S; - if (Field_ftsf114ae_slot1_Slot_ae_slot1_get (insn) == 55 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_XORQ56; - if (Field_ftsf115ae_slot1_Slot_ae_slot1_get (insn) == 56 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_NANDQ56; - if (Field_ftsf116ae_slot1_Slot_ae_slot1_get (insn) == 57 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ABSQ56; - if (Field_ftsf118ae_slot1_Slot_ae_slot1_get (insn) == 185 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_NEGSQ56S; - if (Field_ftsf119ae_slot1_Slot_ae_slot1_get (insn) == 185 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf338_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_SATQ48S; - if (Field_ftsf12_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf341ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LTQ56S; - if (Field_ftsf120ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf343ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ABSSQ56S; - if (Field_ftsf122ae_slot1_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf346ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_NEGQ56; - if (Field_ftsf124ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf339ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LEQ56S; - if (Field_ftsf125ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf350ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_TRUNCP24Q48X2; - if (Field_ftsf126ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ADDQ56; - if (Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAFP24S_HH_LL; - if (Field_ftsf128ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAFP24S_HL_LH; - if (Field_ftsf129ae_slot1_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAP24S_HH_LL; - if (Field_ftsf13_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf12_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_SLLISP24S; - if (Field_ftsf130ae_slot1_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_HL; - if (Field_ftsf131ae_slot1_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAP24S_HL_LH; - if (Field_ftsf132ae_slot1_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_LH; - if (Field_ftsf133ae_slot1_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_LL; - if (Field_ftsf134ae_slot1_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_HH; - if (Field_ftsf135ae_slot1_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_HH; - if (Field_ftsf136ae_slot1_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_HL; - if (Field_ftsf137ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_LH; - if (Field_ftsf138ae_slot1_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_HH; - if (Field_ftsf139ae_slot1_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_LL; - if (Field_ftsf140ae_slot1_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_HL; - if (Field_ftsf141ae_slot1_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_LH; - if (Field_ftsf142ae_slot1_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_LL; - if (Field_ftsf143ae_slot1_Slot_ae_slot1_get (insn) == 16 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_HL; - if (Field_ftsf144ae_slot1_Slot_ae_slot1_get (insn) == 17 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_HH; - if (Field_ftsf145ae_slot1_Slot_ae_slot1_get (insn) == 18 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_HL; - if (Field_ftsf146ae_slot1_Slot_ae_slot1_get (insn) == 19 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASFP24S_HH_LL; - if (Field_ftsf147ae_slot1_Slot_ae_slot1_get (insn) == 20 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_LH; - if (Field_ftsf148ae_slot1_Slot_ae_slot1_get (insn) == 21 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASFP24S_HL_LH; - if (Field_ftsf149ae_slot1_Slot_ae_slot1_get (insn) == 22 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASP24S_HH_LL; - if (Field_ftsf150ae_slot1_Slot_ae_slot1_get (insn) == 23 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASP24S_HL_LH; - if (Field_ftsf151ae_slot1_Slot_ae_slot1_get (insn) == 24 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_LL; - if (Field_ftsf152ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_HH; - if (Field_ftsf153ae_slot1_Slot_ae_slot1_get (insn) == 26 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_HL; - if (Field_ftsf154ae_slot1_Slot_ae_slot1_get (insn) == 27 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_LL; - if (Field_ftsf155ae_slot1_Slot_ae_slot1_get (insn) == 28 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_LH; - if (Field_ftsf156ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_HH; - if (Field_ftsf157ae_slot1_Slot_ae_slot1_get (insn) == 30 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_HL; - if (Field_ftsf158ae_slot1_Slot_ae_slot1_get (insn) == 31 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_LH; - if (Field_ftsf159ae_slot1_Slot_ae_slot1_get (insn) == 32 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_LH; - if (Field_ftsf160ae_slot1_Slot_ae_slot1_get (insn) == 33 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_LL; - if (Field_ftsf161ae_slot1_Slot_ae_slot1_get (insn) == 34 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_HH; - if (Field_ftsf162ae_slot1_Slot_ae_slot1_get (insn) == 35 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAFP24S_HH_LL; - if (Field_ftsf163ae_slot1_Slot_ae_slot1_get (insn) == 36 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_HL; - if (Field_ftsf164ae_slot1_Slot_ae_slot1_get (insn) == 37 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAFP24S_HL_LH; - if (Field_ftsf165ae_slot1_Slot_ae_slot1_get (insn) == 38 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAP24S_HH_LL; - if (Field_ftsf166ae_slot1_Slot_ae_slot1_get (insn) == 39 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAP24S_HL_LH; - if (Field_ftsf167ae_slot1_Slot_ae_slot1_get (insn) == 40 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_LH; - if (Field_ftsf168ae_slot1_Slot_ae_slot1_get (insn) == 41 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_HH; - if (Field_ftsf169ae_slot1_Slot_ae_slot1_get (insn) == 42 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_HL; - if (Field_ftsf170ae_slot1_Slot_ae_slot1_get (insn) == 43 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_LL; - if (Field_ftsf171ae_slot1_Slot_ae_slot1_get (insn) == 44 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_LH; - if (Field_ftsf172ae_slot1_Slot_ae_slot1_get (insn) == 45 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_HH; - if (Field_ftsf173ae_slot1_Slot_ae_slot1_get (insn) == 46 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_HL; - if (Field_ftsf174ae_slot1_Slot_ae_slot1_get (insn) == 47 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_LH; - if (Field_ftsf175ae_slot1_Slot_ae_slot1_get (insn) == 48 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_LL; - if (Field_ftsf176ae_slot1_Slot_ae_slot1_get (insn) == 49 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_LL; - if (Field_ftsf177ae_slot1_Slot_ae_slot1_get (insn) == 50 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_HH; - if (Field_ftsf178ae_slot1_Slot_ae_slot1_get (insn) == 51 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_LL; - if (Field_ftsf179ae_slot1_Slot_ae_slot1_get (insn) == 52 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_HL; - if (Field_ftsf180ae_slot1_Slot_ae_slot1_get (insn) == 53 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_HH; - if (Field_ftsf181ae_slot1_Slot_ae_slot1_get (insn) == 54 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_HL; - if (Field_ftsf182ae_slot1_Slot_ae_slot1_get (insn) == 55 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_LH; - if (Field_ftsf183ae_slot1_Slot_ae_slot1_get (insn) == 56 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_LH; - if (Field_ftsf184ae_slot1_Slot_ae_slot1_get (insn) == 57 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_LL; - if (Field_ftsf185ae_slot1_Slot_ae_slot1_get (insn) == 58 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_HH; - if (Field_ftsf186ae_slot1_Slot_ae_slot1_get (insn) == 59 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_LH; - if (Field_ftsf187ae_slot1_Slot_ae_slot1_get (insn) == 60 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_HL; - if (Field_ftsf188ae_slot1_Slot_ae_slot1_get (insn) == 61 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_LL; - if (Field_ftsf189ae_slot1_Slot_ae_slot1_get (insn) == 62 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSFP24S_HH_LL; - if (Field_ftsf190ae_slot1_Slot_ae_slot1_get (insn) == 63 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSFP24S_HL_LH; - if (Field_ftsf191ae_slot1_Slot_ae_slot1_get (insn) == 64 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_LL; - if (Field_ftsf192ae_slot1_Slot_ae_slot1_get (insn) == 65 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSP24S_HH_LL; - if (Field_ftsf193ae_slot1_Slot_ae_slot1_get (insn) == 66 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSP24S_HL_LH; - if (Field_ftsf194ae_slot1_Slot_ae_slot1_get (insn) == 67 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASFP24S_HH_LL; - if (Field_ftsf195ae_slot1_Slot_ae_slot1_get (insn) == 68 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZAAFP24S_HH_LL; - if (Field_ftsf196ae_slot1_Slot_ae_slot1_get (insn) == 69 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASFP24S_HL_LH; - if (Field_ftsf197ae_slot1_Slot_ae_slot1_get (insn) == 70 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASP24S_HH_LL; - if (Field_ftsf198ae_slot1_Slot_ae_slot1_get (insn) == 71 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASP24S_HL_LH; - if (Field_ftsf199ae_slot1_Slot_ae_slot1_get (insn) == 72 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZAAFP24S_HL_LH; - if (Field_ftsf200ae_slot1_Slot_ae_slot1_get (insn) == 73 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAFP24S_HH_LL; - if (Field_ftsf201ae_slot1_Slot_ae_slot1_get (insn) == 74 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAFP24S_HL_LH; - if (Field_ftsf202ae_slot1_Slot_ae_slot1_get (insn) == 75 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAP24S_HL_LH; - if (Field_ftsf203ae_slot1_Slot_ae_slot1_get (insn) == 76 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAP24S_HH_LL; - if (Field_ftsf204ae_slot1_Slot_ae_slot1_get (insn) == 77 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSFP24S_HH_LL; - if (Field_ftsf205ae_slot1_Slot_ae_slot1_get (insn) == 78 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSFP24S_HL_LH; - if (Field_ftsf206ae_slot1_Slot_ae_slot1_get (insn) == 79 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSP24S_HH_LL; - if (Field_ftsf207ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZAAP24S_HH_LL; - if (Field_ftsf209ae_slot1_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZSSP24S_HL_LH; - if (Field_ftsf210ae_slot1_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf337ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZAAP24S_HL_LH; - if (Field_ftsf211ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf332ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULAFS32P16S_HH; - if (Field_ftsf21ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MAXBP24S; - if (Field_ftsf22ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MINBP24S; - if (Field_ftsf23ae_slot1_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVFP48; - if (Field_ftsf24ae_slot1_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVTP48; - if (Field_ftsf25ae_slot1_Slot_ae_slot1_get (insn) == 20 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ADDP24; - if (Field_ftsf26ae_slot1_Slot_ae_slot1_get (insn) == 21 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ANDP48; - if (Field_ftsf27ae_slot1_Slot_ae_slot1_get (insn) == 22 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MAXP24S; - if (Field_ftsf28ae_slot1_Slot_ae_slot1_get (insn) == 23 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MINP24S; - if (Field_ftsf29ae_slot1_Slot_ae_slot1_get (insn) == 24 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ADDSP24S; - if (Field_ftsf30ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_NANDP48; - if (Field_ftsf31ae_slot1_Slot_ae_slot1_get (insn) == 26 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ORP48; - if (Field_ftsf32ae_slot1_Slot_ae_slot1_get (insn) == 27 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_HL; - if (Field_ftsf33ae_slot1_Slot_ae_slot1_get (insn) == 28 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_HH; - if (Field_ftsf34ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_LH; - if (Field_ftsf35ae_slot1_Slot_ae_slot1_get (insn) == 30 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_LL; - if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 31 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SUBP24; - if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SLLIP24; - if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRAIP24; - if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRLIP24; - if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 176 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16S_L; - if (Field_ftsf39ae_slot1_Slot_ae_slot1_get (insn) == 177 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16U_H; - if (Field_ftsf40ae_slot1_Slot_ae_slot1_get (insn) == 178 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16U_L; - if (Field_ftsf41ae_slot1_Slot_ae_slot1_get (insn) == 179 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16U_H; - if (Field_ftsf42ae_slot1_Slot_ae_slot1_get (insn) == 180 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16S_H; - if (Field_ftsf43ae_slot1_Slot_ae_slot1_get (insn) == 181 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16U_L; - if (Field_ftsf44ae_slot1_Slot_ae_slot1_get (insn) == 182 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16S_H; - if (Field_ftsf45ae_slot1_Slot_ae_slot1_get (insn) == 183 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16S_L; - if (Field_ftsf46ae_slot1_Slot_ae_slot1_get (insn) == 184 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16S_L; - if (Field_ftsf47ae_slot1_Slot_ae_slot1_get (insn) == 185 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16U_H; - if (Field_ftsf48ae_slot1_Slot_ae_slot1_get (insn) == 186 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16U_L; - if (Field_ftsf49ae_slot1_Slot_ae_slot1_get (insn) == 187 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16S_L; - if (Field_ftsf50ae_slot1_Slot_ae_slot1_get (insn) == 188 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16S_H; - if (Field_ftsf51ae_slot1_Slot_ae_slot1_get (insn) == 189 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16U_H; - if (Field_ftsf52ae_slot1_Slot_ae_slot1_get (insn) == 190 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16U_L; - if (Field_ftsf53ae_slot1_Slot_ae_slot1_get (insn) == 191 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16S_H; - if (Field_ftsf54ae_slot1_Slot_ae_slot1_get (insn) == 192 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16S_H; - if (Field_ftsf55ae_slot1_Slot_ae_slot1_get (insn) == 193 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16S_L; - if (Field_ftsf56ae_slot1_Slot_ae_slot1_get (insn) == 194 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16U_H; - if (Field_ftsf57ae_slot1_Slot_ae_slot1_get (insn) == 195 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSQ32SP16U_L; - if (Field_ftsf58ae_slot1_Slot_ae_slot1_get (insn) == 196 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16U_L; - if (Field_ftsf59ae_slot1_Slot_ae_slot1_get (insn) == 773 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_CVTQ48P24S_H; - if (Field_ftsf60ae_slot1_Slot_ae_slot1_get (insn) == 789 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ZEROQ56; - if (Field_ftsf61ae_slot1_Slot_ae_slot1_get (insn) == 405 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf330ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_NOP; - if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 198 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r10_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_CVTQ48P24S_L; - if (Field_ftsf64ae_slot1_Slot_ae_slot1_get (insn) == 1543 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVQ56; - if (Field_ftsf66ae_slot1_Slot_ae_slot1_get (insn) == 1559 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSQ32ASYM; - if (Field_ftsf67ae_slot1_Slot_ae_slot1_get (insn) == 791 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSQ32SYM; - if (Field_ftsf69ae_slot1_Slot_ae_slot1_get (insn) == 407 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf340_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_TRUNCQ32; - if (Field_ftsf71ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULSQ32SP16S_H; - if (Field_ftsf72ae_slot1_Slot_ae_slot1_get (insn) == 26 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULSQ32SP16S_L; - if (Field_ftsf73ae_slot1_Slot_ae_slot1_get (insn) == 417 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVP48; - if (Field_ftsf75ae_slot1_Slot_ae_slot1_get (insn) == 419 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16ASYM; - if (Field_ftsf76ae_slot1_Slot_ae_slot1_get (insn) == 421 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16SYM; - if (Field_ftsf77ae_slot1_Slot_ae_slot1_get (insn) == 423 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRASP24; - if (Field_ftsf78ae_slot1_Slot_ae_slot1_get (insn) == 425 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SLLSP24; - if (Field_ftsf79ae_slot1_Slot_ae_slot1_get (insn) == 427 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRLSP24; - if (Field_ftsf80ae_slot1_Slot_ae_slot1_get (insn) == 429 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_TRUNCP16; - if (Field_ftsf81ae_slot1_Slot_ae_slot1_get (insn) == 431 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ZEROP48; - if (Field_ftsf82ae_slot1_Slot_ae_slot1_get (insn) == 109 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r10_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_SLLSSP24S; - if (Field_ftsf84ae_slot1_Slot_ae_slot1_get (insn) == 881 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16Q48ASYM; - if (Field_ftsf86ae_slot1_Slot_ae_slot1_get (insn) == 883 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16Q48SYM; - if (Field_ftsf87ae_slot1_Slot_ae_slot1_get (insn) == 443 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSP24Q48ASYM; - if (Field_ftsf88ae_slot1_Slot_ae_slot1_get (insn) == 223 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf340_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSP24Q48SYM; - if (Field_ftsf89ae_slot1_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf334ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULSQ32SP16U_H; - if (Field_ftsf90ae_slot1_Slot_ae_slot1_get (insn) == 96 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_EQP24; - if (Field_ftsf91ae_slot1_Slot_ae_slot1_get (insn) == 97 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_LEP24S; - if (Field_ftsf92ae_slot1_Slot_ae_slot1_get (insn) == 49 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf208_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LTP24S; - if (Field_ftsf94ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf347_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MOVFP24X2; - if (Field_ftsf96ae_slot1_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MOVTP24X2; - if (Field_ftsf97ae_slot1_Slot_ae_slot1_get (insn) == 112 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SUBSP24S; - if (Field_ftsf98ae_slot1_Slot_ae_slot1_get (insn) == 113 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_XORP48; - if (Field_ftsf99ae_slot1_Slot_ae_slot1_get (insn) == 114 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ABSP24; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_LL; - return 0; -} - - -/* Instruction slots. */ - -static void -Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffffff); -} - -static void -Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); -} - -static void -Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static void -Slot_ae_format_Format_ae_slot1_31_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[0] & 0x80000000) >> 31); - slotbuf[0] = (slotbuf[0] & ~0x7ffffe) | ((insn[1] & 0x3fffff) << 1); -} - -static void -Slot_ae_format_Format_ae_slot1_31_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0x80000000) | ((slotbuf[0] & 0x1) << 31); - insn[1] = (insn[1] & ~0x3fffff) | ((slotbuf[0] & 0x7ffffe) >> 1); -} - -static void -Slot_ae_format_Format_ae_slot0_4_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[0] & 0x7ffffff0) >> 4); -} - -static void -Slot_ae_format_Format_ae_slot0_4_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0x7ffffff0) | ((slotbuf[0] & 0x7ffffff) << 4); -} - -static xtensa_get_field_fn -Slot_inst_get_field_fns[] = { - Field_t_Slot_inst_get, - Field_bbi4_Slot_inst_get, - Field_bbi_Slot_inst_get, - Field_imm12_Slot_inst_get, - Field_imm8_Slot_inst_get, - Field_s_Slot_inst_get, - Field_imm12b_Slot_inst_get, - Field_imm16_Slot_inst_get, - Field_m_Slot_inst_get, - Field_n_Slot_inst_get, - Field_offset_Slot_inst_get, - Field_op0_Slot_inst_get, - Field_op1_Slot_inst_get, - Field_op2_Slot_inst_get, - Field_r_Slot_inst_get, - Field_sa4_Slot_inst_get, - Field_sae4_Slot_inst_get, - Field_sae_Slot_inst_get, - Field_sal_Slot_inst_get, - Field_sargt_Slot_inst_get, - Field_sas4_Slot_inst_get, - Field_sas_Slot_inst_get, - Field_sr_Slot_inst_get, - Field_st_Slot_inst_get, - Field_thi3_Slot_inst_get, - Field_imm4_Slot_inst_get, - Field_mn_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r3_Slot_inst_get, - Field_rbit2_Slot_inst_get, - Field_rhi_Slot_inst_get, - Field_t3_Slot_inst_get, - Field_tbit2_Slot_inst_get, - Field_tlo_Slot_inst_get, - Field_w_Slot_inst_get, - Field_y_Slot_inst_get, - Field_x_Slot_inst_get, - Field_t2_Slot_inst_get, - Field_s2_Slot_inst_get, - Field_r2_Slot_inst_get, - Field_t4_Slot_inst_get, - Field_s4_Slot_inst_get, - Field_r4_Slot_inst_get, - Field_t8_Slot_inst_get, - Field_s8_Slot_inst_get, - Field_r8_Slot_inst_get, - Field_xt_wbr15_imm_Slot_inst_get, - Field_xt_wbr18_imm_Slot_inst_get, - Field_ae_r3_Slot_inst_get, - Field_ae_s_non_samt_Slot_inst_get, - Field_ae_s3_Slot_inst_get, - Field_ae_r32_Slot_inst_get, - Field_ae_samt_s_t_Slot_inst_get, - Field_ae_r20_Slot_inst_get, - Field_ae_r10_Slot_inst_get, - Field_ae_s20_Slot_inst_get, - Field_ae_fld_ohba_Slot_inst_get, - Field_ae_fld_ohba2_Slot_inst_get, - 0, - Field_ftsf12_Slot_inst_get, - Field_ftsf13_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst_set_field_fns[] = { - Field_t_Slot_inst_set, - Field_bbi4_Slot_inst_set, - Field_bbi_Slot_inst_set, - Field_imm12_Slot_inst_set, - Field_imm8_Slot_inst_set, - Field_s_Slot_inst_set, - Field_imm12b_Slot_inst_set, - Field_imm16_Slot_inst_set, - Field_m_Slot_inst_set, - Field_n_Slot_inst_set, - Field_offset_Slot_inst_set, - Field_op0_Slot_inst_set, - Field_op1_Slot_inst_set, - Field_op2_Slot_inst_set, - Field_r_Slot_inst_set, - Field_sa4_Slot_inst_set, - Field_sae4_Slot_inst_set, - Field_sae_Slot_inst_set, - Field_sal_Slot_inst_set, - Field_sargt_Slot_inst_set, - Field_sas4_Slot_inst_set, - Field_sas_Slot_inst_set, - Field_sr_Slot_inst_set, - Field_st_Slot_inst_set, - Field_thi3_Slot_inst_set, - Field_imm4_Slot_inst_set, - Field_mn_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r3_Slot_inst_set, - Field_rbit2_Slot_inst_set, - Field_rhi_Slot_inst_set, - Field_t3_Slot_inst_set, - Field_tbit2_Slot_inst_set, - Field_tlo_Slot_inst_set, - Field_w_Slot_inst_set, - Field_y_Slot_inst_set, - Field_x_Slot_inst_set, - Field_t2_Slot_inst_set, - Field_s2_Slot_inst_set, - Field_r2_Slot_inst_set, - Field_t4_Slot_inst_set, - Field_s4_Slot_inst_set, - Field_r4_Slot_inst_set, - Field_t8_Slot_inst_set, - Field_s8_Slot_inst_set, - Field_r8_Slot_inst_set, - Field_xt_wbr15_imm_Slot_inst_set, - Field_xt_wbr18_imm_Slot_inst_set, - Field_ae_r3_Slot_inst_set, - Field_ae_s_non_samt_Slot_inst_set, - Field_ae_s3_Slot_inst_set, - Field_ae_r32_Slot_inst_set, - Field_ae_samt_s_t_Slot_inst_set, - Field_ae_r20_Slot_inst_set, - Field_ae_r10_Slot_inst_set, - Field_ae_s20_Slot_inst_set, - Field_ae_fld_ohba_Slot_inst_set, - Field_ae_fld_ohba2_Slot_inst_set, - 0, - Field_ftsf12_Slot_inst_set, - Field_ftsf13_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16a_get_field_fns[] = { - Field_t_Slot_inst16a_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_get, - 0, - 0, - Field_r_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_get, - Field_st_Slot_inst16a_get, - 0, - Field_imm4_Slot_inst16a_get, - 0, - Field_i_Slot_inst16a_get, - Field_imm6lo_Slot_inst16a_get, - Field_imm6hi_Slot_inst16a_get, - Field_imm7lo_Slot_inst16a_get, - Field_imm7hi_Slot_inst16a_get, - Field_z_Slot_inst16a_get, - Field_imm6_Slot_inst16a_get, - Field_imm7_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst16a_get, - Field_s2_Slot_inst16a_get, - Field_r2_Slot_inst16a_get, - Field_t4_Slot_inst16a_get, - Field_s4_Slot_inst16a_get, - Field_r4_Slot_inst16a_get, - Field_t8_Slot_inst16a_get, - Field_s8_Slot_inst16a_get, - Field_r8_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst16a_set_field_fns[] = { - Field_t_Slot_inst16a_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_set, - 0, - 0, - Field_r_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_set, - Field_st_Slot_inst16a_set, - 0, - Field_imm4_Slot_inst16a_set, - 0, - Field_i_Slot_inst16a_set, - Field_imm6lo_Slot_inst16a_set, - Field_imm6hi_Slot_inst16a_set, - Field_imm7lo_Slot_inst16a_set, - Field_imm7hi_Slot_inst16a_set, - Field_z_Slot_inst16a_set, - Field_imm6_Slot_inst16a_set, - Field_imm7_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst16a_set, - Field_s2_Slot_inst16a_set, - Field_r2_Slot_inst16a_set, - Field_t4_Slot_inst16a_set, - Field_s4_Slot_inst16a_set, - Field_r4_Slot_inst16a_set, - Field_t8_Slot_inst16a_set, - Field_s8_Slot_inst16a_set, - Field_r8_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16b_get_field_fns[] = { - Field_t_Slot_inst16b_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_get, - 0, - 0, - Field_r_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_get, - Field_st_Slot_inst16b_get, - 0, - Field_imm4_Slot_inst16b_get, - 0, - Field_i_Slot_inst16b_get, - Field_imm6lo_Slot_inst16b_get, - Field_imm6hi_Slot_inst16b_get, - Field_imm7lo_Slot_inst16b_get, - Field_imm7hi_Slot_inst16b_get, - Field_z_Slot_inst16b_get, - Field_imm6_Slot_inst16b_get, - Field_imm7_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst16b_get, - Field_s2_Slot_inst16b_get, - Field_r2_Slot_inst16b_get, - Field_t4_Slot_inst16b_get, - Field_s4_Slot_inst16b_get, - Field_r4_Slot_inst16b_get, - Field_t8_Slot_inst16b_get, - Field_s8_Slot_inst16b_get, - Field_r8_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst16b_set_field_fns[] = { - Field_t_Slot_inst16b_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_set, - 0, - 0, - Field_r_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_set, - Field_st_Slot_inst16b_set, - 0, - Field_imm4_Slot_inst16b_set, - 0, - Field_i_Slot_inst16b_set, - Field_imm6lo_Slot_inst16b_set, - Field_imm6hi_Slot_inst16b_set, - Field_imm7lo_Slot_inst16b_set, - Field_imm7hi_Slot_inst16b_set, - Field_z_Slot_inst16b_set, - Field_imm6_Slot_inst16b_set, - Field_imm7_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst16b_set, - Field_s2_Slot_inst16b_set, - Field_r2_Slot_inst16b_set, - Field_t4_Slot_inst16b_set, - Field_s4_Slot_inst16b_set, - Field_r4_Slot_inst16b_set, - Field_t8_Slot_inst16b_set, - Field_s8_Slot_inst16b_set, - Field_r8_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_ae_slot1_get_field_fns[] = { - Field_t_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot1_get, - 0, - Field_ae_r20_Slot_ae_slot1_get, - Field_ae_r10_Slot_ae_slot1_get, - Field_ae_s20_Slot_ae_slot1_get, - 0, - 0, - Field_op0_s3_Slot_ae_slot1_get, - Field_ftsf12_Slot_ae_slot1_get, - Field_ftsf13_Slot_ae_slot1_get, - Field_ftsf14_Slot_ae_slot1_get, - Field_ftsf21ae_slot1_Slot_ae_slot1_get, - Field_ftsf22ae_slot1_Slot_ae_slot1_get, - Field_ftsf23ae_slot1_Slot_ae_slot1_get, - Field_ftsf24ae_slot1_Slot_ae_slot1_get, - Field_ftsf25ae_slot1_Slot_ae_slot1_get, - Field_ftsf26ae_slot1_Slot_ae_slot1_get, - Field_ftsf27ae_slot1_Slot_ae_slot1_get, - Field_ftsf28ae_slot1_Slot_ae_slot1_get, - Field_ftsf29ae_slot1_Slot_ae_slot1_get, - Field_ftsf30ae_slot1_Slot_ae_slot1_get, - Field_ftsf31ae_slot1_Slot_ae_slot1_get, - Field_ftsf32ae_slot1_Slot_ae_slot1_get, - Field_ftsf33ae_slot1_Slot_ae_slot1_get, - Field_ftsf34ae_slot1_Slot_ae_slot1_get, - Field_ftsf35ae_slot1_Slot_ae_slot1_get, - Field_ftsf36ae_slot1_Slot_ae_slot1_get, - Field_ftsf37ae_slot1_Slot_ae_slot1_get, - Field_ftsf38ae_slot1_Slot_ae_slot1_get, - Field_ftsf39ae_slot1_Slot_ae_slot1_get, - Field_ftsf40ae_slot1_Slot_ae_slot1_get, - Field_ftsf41ae_slot1_Slot_ae_slot1_get, - Field_ftsf42ae_slot1_Slot_ae_slot1_get, - Field_ftsf43ae_slot1_Slot_ae_slot1_get, - Field_ftsf44ae_slot1_Slot_ae_slot1_get, - Field_ftsf45ae_slot1_Slot_ae_slot1_get, - Field_ftsf46ae_slot1_Slot_ae_slot1_get, - Field_ftsf47ae_slot1_Slot_ae_slot1_get, - Field_ftsf48ae_slot1_Slot_ae_slot1_get, - Field_ftsf49ae_slot1_Slot_ae_slot1_get, - Field_ftsf50ae_slot1_Slot_ae_slot1_get, - Field_ftsf51ae_slot1_Slot_ae_slot1_get, - Field_ftsf52ae_slot1_Slot_ae_slot1_get, - Field_ftsf53ae_slot1_Slot_ae_slot1_get, - Field_ftsf54ae_slot1_Slot_ae_slot1_get, - Field_ftsf55ae_slot1_Slot_ae_slot1_get, - Field_ftsf56ae_slot1_Slot_ae_slot1_get, - Field_ftsf57ae_slot1_Slot_ae_slot1_get, - Field_ftsf58ae_slot1_Slot_ae_slot1_get, - Field_ftsf59ae_slot1_Slot_ae_slot1_get, - Field_ftsf60ae_slot1_Slot_ae_slot1_get, - Field_ftsf61ae_slot1_Slot_ae_slot1_get, - Field_ftsf63ae_slot1_Slot_ae_slot1_get, - Field_ftsf64ae_slot1_Slot_ae_slot1_get, - Field_ftsf66ae_slot1_Slot_ae_slot1_get, - Field_ftsf67ae_slot1_Slot_ae_slot1_get, - Field_ftsf69ae_slot1_Slot_ae_slot1_get, - Field_ftsf71ae_slot1_Slot_ae_slot1_get, - Field_ftsf72ae_slot1_Slot_ae_slot1_get, - Field_ftsf73ae_slot1_Slot_ae_slot1_get, - Field_ftsf75ae_slot1_Slot_ae_slot1_get, - Field_ftsf76ae_slot1_Slot_ae_slot1_get, - Field_ftsf77ae_slot1_Slot_ae_slot1_get, - Field_ftsf78ae_slot1_Slot_ae_slot1_get, - Field_ftsf79ae_slot1_Slot_ae_slot1_get, - Field_ftsf80ae_slot1_Slot_ae_slot1_get, - Field_ftsf81ae_slot1_Slot_ae_slot1_get, - Field_ftsf82ae_slot1_Slot_ae_slot1_get, - Field_ftsf84ae_slot1_Slot_ae_slot1_get, - Field_ftsf86ae_slot1_Slot_ae_slot1_get, - Field_ftsf87ae_slot1_Slot_ae_slot1_get, - Field_ftsf88ae_slot1_Slot_ae_slot1_get, - Field_ftsf89ae_slot1_Slot_ae_slot1_get, - Field_ftsf90ae_slot1_Slot_ae_slot1_get, - Field_ftsf91ae_slot1_Slot_ae_slot1_get, - Field_ftsf92ae_slot1_Slot_ae_slot1_get, - Field_ftsf94ae_slot1_Slot_ae_slot1_get, - Field_ftsf96ae_slot1_Slot_ae_slot1_get, - Field_ftsf97ae_slot1_Slot_ae_slot1_get, - Field_ftsf98ae_slot1_Slot_ae_slot1_get, - Field_ftsf99ae_slot1_Slot_ae_slot1_get, - Field_ftsf100ae_slot1_Slot_ae_slot1_get, - Field_ftsf101ae_slot1_Slot_ae_slot1_get, - Field_ftsf103ae_slot1_Slot_ae_slot1_get, - Field_ftsf104ae_slot1_Slot_ae_slot1_get, - Field_ftsf105ae_slot1_Slot_ae_slot1_get, - Field_ftsf106ae_slot1_Slot_ae_slot1_get, - Field_ftsf107ae_slot1_Slot_ae_slot1_get, - Field_ftsf108ae_slot1_Slot_ae_slot1_get, - Field_ftsf109ae_slot1_Slot_ae_slot1_get, - Field_ftsf110ae_slot1_Slot_ae_slot1_get, - Field_ftsf111ae_slot1_Slot_ae_slot1_get, - Field_ftsf112ae_slot1_Slot_ae_slot1_get, - Field_ftsf113ae_slot1_Slot_ae_slot1_get, - Field_ftsf114ae_slot1_Slot_ae_slot1_get, - Field_ftsf115ae_slot1_Slot_ae_slot1_get, - Field_ftsf116ae_slot1_Slot_ae_slot1_get, - Field_ftsf118ae_slot1_Slot_ae_slot1_get, - Field_ftsf119ae_slot1_Slot_ae_slot1_get, - Field_ftsf120ae_slot1_Slot_ae_slot1_get, - Field_ftsf122ae_slot1_Slot_ae_slot1_get, - Field_ftsf124ae_slot1_Slot_ae_slot1_get, - Field_ftsf125ae_slot1_Slot_ae_slot1_get, - Field_ftsf126ae_slot1_Slot_ae_slot1_get, - Field_ftsf127ae_slot1_Slot_ae_slot1_get, - Field_ftsf128ae_slot1_Slot_ae_slot1_get, - Field_ftsf129ae_slot1_Slot_ae_slot1_get, - Field_ftsf130ae_slot1_Slot_ae_slot1_get, - Field_ftsf131ae_slot1_Slot_ae_slot1_get, - Field_ftsf132ae_slot1_Slot_ae_slot1_get, - Field_ftsf133ae_slot1_Slot_ae_slot1_get, - Field_ftsf134ae_slot1_Slot_ae_slot1_get, - Field_ftsf135ae_slot1_Slot_ae_slot1_get, - Field_ftsf136ae_slot1_Slot_ae_slot1_get, - Field_ftsf137ae_slot1_Slot_ae_slot1_get, - Field_ftsf138ae_slot1_Slot_ae_slot1_get, - Field_ftsf139ae_slot1_Slot_ae_slot1_get, - Field_ftsf140ae_slot1_Slot_ae_slot1_get, - Field_ftsf141ae_slot1_Slot_ae_slot1_get, - Field_ftsf142ae_slot1_Slot_ae_slot1_get, - Field_ftsf143ae_slot1_Slot_ae_slot1_get, - Field_ftsf144ae_slot1_Slot_ae_slot1_get, - Field_ftsf145ae_slot1_Slot_ae_slot1_get, - Field_ftsf146ae_slot1_Slot_ae_slot1_get, - Field_ftsf147ae_slot1_Slot_ae_slot1_get, - Field_ftsf148ae_slot1_Slot_ae_slot1_get, - Field_ftsf149ae_slot1_Slot_ae_slot1_get, - Field_ftsf150ae_slot1_Slot_ae_slot1_get, - Field_ftsf151ae_slot1_Slot_ae_slot1_get, - Field_ftsf152ae_slot1_Slot_ae_slot1_get, - Field_ftsf153ae_slot1_Slot_ae_slot1_get, - Field_ftsf154ae_slot1_Slot_ae_slot1_get, - Field_ftsf155ae_slot1_Slot_ae_slot1_get, - Field_ftsf156ae_slot1_Slot_ae_slot1_get, - Field_ftsf157ae_slot1_Slot_ae_slot1_get, - Field_ftsf158ae_slot1_Slot_ae_slot1_get, - Field_ftsf159ae_slot1_Slot_ae_slot1_get, - Field_ftsf160ae_slot1_Slot_ae_slot1_get, - Field_ftsf161ae_slot1_Slot_ae_slot1_get, - Field_ftsf162ae_slot1_Slot_ae_slot1_get, - Field_ftsf163ae_slot1_Slot_ae_slot1_get, - Field_ftsf164ae_slot1_Slot_ae_slot1_get, - Field_ftsf165ae_slot1_Slot_ae_slot1_get, - Field_ftsf166ae_slot1_Slot_ae_slot1_get, - Field_ftsf167ae_slot1_Slot_ae_slot1_get, - Field_ftsf168ae_slot1_Slot_ae_slot1_get, - Field_ftsf169ae_slot1_Slot_ae_slot1_get, - Field_ftsf170ae_slot1_Slot_ae_slot1_get, - Field_ftsf171ae_slot1_Slot_ae_slot1_get, - Field_ftsf172ae_slot1_Slot_ae_slot1_get, - Field_ftsf173ae_slot1_Slot_ae_slot1_get, - Field_ftsf174ae_slot1_Slot_ae_slot1_get, - Field_ftsf175ae_slot1_Slot_ae_slot1_get, - Field_ftsf176ae_slot1_Slot_ae_slot1_get, - Field_ftsf177ae_slot1_Slot_ae_slot1_get, - Field_ftsf178ae_slot1_Slot_ae_slot1_get, - Field_ftsf179ae_slot1_Slot_ae_slot1_get, - Field_ftsf180ae_slot1_Slot_ae_slot1_get, - Field_ftsf181ae_slot1_Slot_ae_slot1_get, - Field_ftsf182ae_slot1_Slot_ae_slot1_get, - Field_ftsf183ae_slot1_Slot_ae_slot1_get, - Field_ftsf184ae_slot1_Slot_ae_slot1_get, - Field_ftsf185ae_slot1_Slot_ae_slot1_get, - Field_ftsf186ae_slot1_Slot_ae_slot1_get, - Field_ftsf187ae_slot1_Slot_ae_slot1_get, - Field_ftsf188ae_slot1_Slot_ae_slot1_get, - Field_ftsf189ae_slot1_Slot_ae_slot1_get, - Field_ftsf190ae_slot1_Slot_ae_slot1_get, - Field_ftsf191ae_slot1_Slot_ae_slot1_get, - Field_ftsf192ae_slot1_Slot_ae_slot1_get, - Field_ftsf193ae_slot1_Slot_ae_slot1_get, - Field_ftsf194ae_slot1_Slot_ae_slot1_get, - Field_ftsf195ae_slot1_Slot_ae_slot1_get, - Field_ftsf196ae_slot1_Slot_ae_slot1_get, - Field_ftsf197ae_slot1_Slot_ae_slot1_get, - Field_ftsf198ae_slot1_Slot_ae_slot1_get, - Field_ftsf199ae_slot1_Slot_ae_slot1_get, - Field_ftsf200ae_slot1_Slot_ae_slot1_get, - Field_ftsf201ae_slot1_Slot_ae_slot1_get, - Field_ftsf202ae_slot1_Slot_ae_slot1_get, - Field_ftsf203ae_slot1_Slot_ae_slot1_get, - Field_ftsf204ae_slot1_Slot_ae_slot1_get, - Field_ftsf205ae_slot1_Slot_ae_slot1_get, - Field_ftsf206ae_slot1_Slot_ae_slot1_get, - Field_ftsf207ae_slot1_Slot_ae_slot1_get, - Field_ftsf208_Slot_ae_slot1_get, - Field_ftsf209ae_slot1_Slot_ae_slot1_get, - Field_ftsf210ae_slot1_Slot_ae_slot1_get, - Field_ftsf211ae_slot1_Slot_ae_slot1_get, - Field_ftsf330ae_slot1_Slot_ae_slot1_get, - Field_ftsf332ae_slot1_Slot_ae_slot1_get, - Field_ftsf334ae_slot1_Slot_ae_slot1_get, - Field_ftsf336ae_slot1_Slot_ae_slot1_get, - Field_ftsf337ae_slot1_Slot_ae_slot1_get, - Field_ftsf338_Slot_ae_slot1_get, - Field_ftsf339ae_slot1_Slot_ae_slot1_get, - Field_ftsf340_Slot_ae_slot1_get, - Field_ftsf341ae_slot1_Slot_ae_slot1_get, - Field_ftsf342ae_slot1_Slot_ae_slot1_get, - Field_ftsf343ae_slot1_Slot_ae_slot1_get, - Field_ftsf344ae_slot1_Slot_ae_slot1_get, - Field_ftsf346ae_slot1_Slot_ae_slot1_get, - Field_ftsf347_Slot_ae_slot1_get, - Field_ftsf348ae_slot1_Slot_ae_slot1_get, - Field_ftsf349ae_slot1_Slot_ae_slot1_get, - Field_ftsf350ae_slot1_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_mul32x24fld_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_combined1b97e84f_fld54_Slot_ae_slot1_get, - Field_combined1b97e84f_fld17_Slot_ae_slot1_get, - Field_combined1b97e84f_fld76_Slot_ae_slot1_get, - Field_combined1b97e84f_fld73_Slot_ae_slot1_get, - Field_combined1b97e84f_fld62_Slot_ae_slot1_get, - Field_combined1b97e84f_fld24_Slot_ae_slot1_get, - Field_combined1b97e84f_fld70_Slot_ae_slot1_get, - Field_combined1b97e84f_fld58_Slot_ae_slot1_get, - Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_get, - Field_op0_s3_s3_Slot_ae_slot1_get, - Field_combined1b97e84f_fld49_Slot_ae_slot1_get, - Field_combined1b97e84f_fld51_Slot_ae_slot1_get, - Field_combined1b97e84f_fld23_Slot_ae_slot1_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_ae_slot1_set_field_fns[] = { - Field_t_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot1_set, - 0, - Field_ae_r20_Slot_ae_slot1_set, - Field_ae_r10_Slot_ae_slot1_set, - Field_ae_s20_Slot_ae_slot1_set, - 0, - 0, - Field_op0_s3_Slot_ae_slot1_set, - Field_ftsf12_Slot_ae_slot1_set, - Field_ftsf13_Slot_ae_slot1_set, - Field_ftsf14_Slot_ae_slot1_set, - Field_ftsf21ae_slot1_Slot_ae_slot1_set, - Field_ftsf22ae_slot1_Slot_ae_slot1_set, - Field_ftsf23ae_slot1_Slot_ae_slot1_set, - Field_ftsf24ae_slot1_Slot_ae_slot1_set, - Field_ftsf25ae_slot1_Slot_ae_slot1_set, - Field_ftsf26ae_slot1_Slot_ae_slot1_set, - Field_ftsf27ae_slot1_Slot_ae_slot1_set, - Field_ftsf28ae_slot1_Slot_ae_slot1_set, - Field_ftsf29ae_slot1_Slot_ae_slot1_set, - Field_ftsf30ae_slot1_Slot_ae_slot1_set, - Field_ftsf31ae_slot1_Slot_ae_slot1_set, - Field_ftsf32ae_slot1_Slot_ae_slot1_set, - Field_ftsf33ae_slot1_Slot_ae_slot1_set, - Field_ftsf34ae_slot1_Slot_ae_slot1_set, - Field_ftsf35ae_slot1_Slot_ae_slot1_set, - Field_ftsf36ae_slot1_Slot_ae_slot1_set, - Field_ftsf37ae_slot1_Slot_ae_slot1_set, - Field_ftsf38ae_slot1_Slot_ae_slot1_set, - Field_ftsf39ae_slot1_Slot_ae_slot1_set, - Field_ftsf40ae_slot1_Slot_ae_slot1_set, - Field_ftsf41ae_slot1_Slot_ae_slot1_set, - Field_ftsf42ae_slot1_Slot_ae_slot1_set, - Field_ftsf43ae_slot1_Slot_ae_slot1_set, - Field_ftsf44ae_slot1_Slot_ae_slot1_set, - Field_ftsf45ae_slot1_Slot_ae_slot1_set, - Field_ftsf46ae_slot1_Slot_ae_slot1_set, - Field_ftsf47ae_slot1_Slot_ae_slot1_set, - Field_ftsf48ae_slot1_Slot_ae_slot1_set, - Field_ftsf49ae_slot1_Slot_ae_slot1_set, - Field_ftsf50ae_slot1_Slot_ae_slot1_set, - Field_ftsf51ae_slot1_Slot_ae_slot1_set, - Field_ftsf52ae_slot1_Slot_ae_slot1_set, - Field_ftsf53ae_slot1_Slot_ae_slot1_set, - Field_ftsf54ae_slot1_Slot_ae_slot1_set, - Field_ftsf55ae_slot1_Slot_ae_slot1_set, - Field_ftsf56ae_slot1_Slot_ae_slot1_set, - Field_ftsf57ae_slot1_Slot_ae_slot1_set, - Field_ftsf58ae_slot1_Slot_ae_slot1_set, - Field_ftsf59ae_slot1_Slot_ae_slot1_set, - Field_ftsf60ae_slot1_Slot_ae_slot1_set, - Field_ftsf61ae_slot1_Slot_ae_slot1_set, - Field_ftsf63ae_slot1_Slot_ae_slot1_set, - Field_ftsf64ae_slot1_Slot_ae_slot1_set, - Field_ftsf66ae_slot1_Slot_ae_slot1_set, - Field_ftsf67ae_slot1_Slot_ae_slot1_set, - Field_ftsf69ae_slot1_Slot_ae_slot1_set, - Field_ftsf71ae_slot1_Slot_ae_slot1_set, - Field_ftsf72ae_slot1_Slot_ae_slot1_set, - Field_ftsf73ae_slot1_Slot_ae_slot1_set, - Field_ftsf75ae_slot1_Slot_ae_slot1_set, - Field_ftsf76ae_slot1_Slot_ae_slot1_set, - Field_ftsf77ae_slot1_Slot_ae_slot1_set, - Field_ftsf78ae_slot1_Slot_ae_slot1_set, - Field_ftsf79ae_slot1_Slot_ae_slot1_set, - Field_ftsf80ae_slot1_Slot_ae_slot1_set, - Field_ftsf81ae_slot1_Slot_ae_slot1_set, - Field_ftsf82ae_slot1_Slot_ae_slot1_set, - Field_ftsf84ae_slot1_Slot_ae_slot1_set, - Field_ftsf86ae_slot1_Slot_ae_slot1_set, - Field_ftsf87ae_slot1_Slot_ae_slot1_set, - Field_ftsf88ae_slot1_Slot_ae_slot1_set, - Field_ftsf89ae_slot1_Slot_ae_slot1_set, - Field_ftsf90ae_slot1_Slot_ae_slot1_set, - Field_ftsf91ae_slot1_Slot_ae_slot1_set, - Field_ftsf92ae_slot1_Slot_ae_slot1_set, - Field_ftsf94ae_slot1_Slot_ae_slot1_set, - Field_ftsf96ae_slot1_Slot_ae_slot1_set, - Field_ftsf97ae_slot1_Slot_ae_slot1_set, - Field_ftsf98ae_slot1_Slot_ae_slot1_set, - Field_ftsf99ae_slot1_Slot_ae_slot1_set, - Field_ftsf100ae_slot1_Slot_ae_slot1_set, - Field_ftsf101ae_slot1_Slot_ae_slot1_set, - Field_ftsf103ae_slot1_Slot_ae_slot1_set, - Field_ftsf104ae_slot1_Slot_ae_slot1_set, - Field_ftsf105ae_slot1_Slot_ae_slot1_set, - Field_ftsf106ae_slot1_Slot_ae_slot1_set, - Field_ftsf107ae_slot1_Slot_ae_slot1_set, - Field_ftsf108ae_slot1_Slot_ae_slot1_set, - Field_ftsf109ae_slot1_Slot_ae_slot1_set, - Field_ftsf110ae_slot1_Slot_ae_slot1_set, - Field_ftsf111ae_slot1_Slot_ae_slot1_set, - Field_ftsf112ae_slot1_Slot_ae_slot1_set, - Field_ftsf113ae_slot1_Slot_ae_slot1_set, - Field_ftsf114ae_slot1_Slot_ae_slot1_set, - Field_ftsf115ae_slot1_Slot_ae_slot1_set, - Field_ftsf116ae_slot1_Slot_ae_slot1_set, - Field_ftsf118ae_slot1_Slot_ae_slot1_set, - Field_ftsf119ae_slot1_Slot_ae_slot1_set, - Field_ftsf120ae_slot1_Slot_ae_slot1_set, - Field_ftsf122ae_slot1_Slot_ae_slot1_set, - Field_ftsf124ae_slot1_Slot_ae_slot1_set, - Field_ftsf125ae_slot1_Slot_ae_slot1_set, - Field_ftsf126ae_slot1_Slot_ae_slot1_set, - Field_ftsf127ae_slot1_Slot_ae_slot1_set, - Field_ftsf128ae_slot1_Slot_ae_slot1_set, - Field_ftsf129ae_slot1_Slot_ae_slot1_set, - Field_ftsf130ae_slot1_Slot_ae_slot1_set, - Field_ftsf131ae_slot1_Slot_ae_slot1_set, - Field_ftsf132ae_slot1_Slot_ae_slot1_set, - Field_ftsf133ae_slot1_Slot_ae_slot1_set, - Field_ftsf134ae_slot1_Slot_ae_slot1_set, - Field_ftsf135ae_slot1_Slot_ae_slot1_set, - Field_ftsf136ae_slot1_Slot_ae_slot1_set, - Field_ftsf137ae_slot1_Slot_ae_slot1_set, - Field_ftsf138ae_slot1_Slot_ae_slot1_set, - Field_ftsf139ae_slot1_Slot_ae_slot1_set, - Field_ftsf140ae_slot1_Slot_ae_slot1_set, - Field_ftsf141ae_slot1_Slot_ae_slot1_set, - Field_ftsf142ae_slot1_Slot_ae_slot1_set, - Field_ftsf143ae_slot1_Slot_ae_slot1_set, - Field_ftsf144ae_slot1_Slot_ae_slot1_set, - Field_ftsf145ae_slot1_Slot_ae_slot1_set, - Field_ftsf146ae_slot1_Slot_ae_slot1_set, - Field_ftsf147ae_slot1_Slot_ae_slot1_set, - Field_ftsf148ae_slot1_Slot_ae_slot1_set, - Field_ftsf149ae_slot1_Slot_ae_slot1_set, - Field_ftsf150ae_slot1_Slot_ae_slot1_set, - Field_ftsf151ae_slot1_Slot_ae_slot1_set, - Field_ftsf152ae_slot1_Slot_ae_slot1_set, - Field_ftsf153ae_slot1_Slot_ae_slot1_set, - Field_ftsf154ae_slot1_Slot_ae_slot1_set, - Field_ftsf155ae_slot1_Slot_ae_slot1_set, - Field_ftsf156ae_slot1_Slot_ae_slot1_set, - Field_ftsf157ae_slot1_Slot_ae_slot1_set, - Field_ftsf158ae_slot1_Slot_ae_slot1_set, - Field_ftsf159ae_slot1_Slot_ae_slot1_set, - Field_ftsf160ae_slot1_Slot_ae_slot1_set, - Field_ftsf161ae_slot1_Slot_ae_slot1_set, - Field_ftsf162ae_slot1_Slot_ae_slot1_set, - Field_ftsf163ae_slot1_Slot_ae_slot1_set, - Field_ftsf164ae_slot1_Slot_ae_slot1_set, - Field_ftsf165ae_slot1_Slot_ae_slot1_set, - Field_ftsf166ae_slot1_Slot_ae_slot1_set, - Field_ftsf167ae_slot1_Slot_ae_slot1_set, - Field_ftsf168ae_slot1_Slot_ae_slot1_set, - Field_ftsf169ae_slot1_Slot_ae_slot1_set, - Field_ftsf170ae_slot1_Slot_ae_slot1_set, - Field_ftsf171ae_slot1_Slot_ae_slot1_set, - Field_ftsf172ae_slot1_Slot_ae_slot1_set, - Field_ftsf173ae_slot1_Slot_ae_slot1_set, - Field_ftsf174ae_slot1_Slot_ae_slot1_set, - Field_ftsf175ae_slot1_Slot_ae_slot1_set, - Field_ftsf176ae_slot1_Slot_ae_slot1_set, - Field_ftsf177ae_slot1_Slot_ae_slot1_set, - Field_ftsf178ae_slot1_Slot_ae_slot1_set, - Field_ftsf179ae_slot1_Slot_ae_slot1_set, - Field_ftsf180ae_slot1_Slot_ae_slot1_set, - Field_ftsf181ae_slot1_Slot_ae_slot1_set, - Field_ftsf182ae_slot1_Slot_ae_slot1_set, - Field_ftsf183ae_slot1_Slot_ae_slot1_set, - Field_ftsf184ae_slot1_Slot_ae_slot1_set, - Field_ftsf185ae_slot1_Slot_ae_slot1_set, - Field_ftsf186ae_slot1_Slot_ae_slot1_set, - Field_ftsf187ae_slot1_Slot_ae_slot1_set, - Field_ftsf188ae_slot1_Slot_ae_slot1_set, - Field_ftsf189ae_slot1_Slot_ae_slot1_set, - Field_ftsf190ae_slot1_Slot_ae_slot1_set, - Field_ftsf191ae_slot1_Slot_ae_slot1_set, - Field_ftsf192ae_slot1_Slot_ae_slot1_set, - Field_ftsf193ae_slot1_Slot_ae_slot1_set, - Field_ftsf194ae_slot1_Slot_ae_slot1_set, - Field_ftsf195ae_slot1_Slot_ae_slot1_set, - Field_ftsf196ae_slot1_Slot_ae_slot1_set, - Field_ftsf197ae_slot1_Slot_ae_slot1_set, - Field_ftsf198ae_slot1_Slot_ae_slot1_set, - Field_ftsf199ae_slot1_Slot_ae_slot1_set, - Field_ftsf200ae_slot1_Slot_ae_slot1_set, - Field_ftsf201ae_slot1_Slot_ae_slot1_set, - Field_ftsf202ae_slot1_Slot_ae_slot1_set, - Field_ftsf203ae_slot1_Slot_ae_slot1_set, - Field_ftsf204ae_slot1_Slot_ae_slot1_set, - Field_ftsf205ae_slot1_Slot_ae_slot1_set, - Field_ftsf206ae_slot1_Slot_ae_slot1_set, - Field_ftsf207ae_slot1_Slot_ae_slot1_set, - Field_ftsf208_Slot_ae_slot1_set, - Field_ftsf209ae_slot1_Slot_ae_slot1_set, - Field_ftsf210ae_slot1_Slot_ae_slot1_set, - Field_ftsf211ae_slot1_Slot_ae_slot1_set, - Field_ftsf330ae_slot1_Slot_ae_slot1_set, - Field_ftsf332ae_slot1_Slot_ae_slot1_set, - Field_ftsf334ae_slot1_Slot_ae_slot1_set, - Field_ftsf336ae_slot1_Slot_ae_slot1_set, - Field_ftsf337ae_slot1_Slot_ae_slot1_set, - Field_ftsf338_Slot_ae_slot1_set, - Field_ftsf339ae_slot1_Slot_ae_slot1_set, - Field_ftsf340_Slot_ae_slot1_set, - Field_ftsf341ae_slot1_Slot_ae_slot1_set, - Field_ftsf342ae_slot1_Slot_ae_slot1_set, - Field_ftsf343ae_slot1_Slot_ae_slot1_set, - Field_ftsf344ae_slot1_Slot_ae_slot1_set, - Field_ftsf346ae_slot1_Slot_ae_slot1_set, - Field_ftsf347_Slot_ae_slot1_set, - Field_ftsf348ae_slot1_Slot_ae_slot1_set, - Field_ftsf349ae_slot1_Slot_ae_slot1_set, - Field_ftsf350ae_slot1_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_mul32x24fld_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_combined1b97e84f_fld54_Slot_ae_slot1_set, - Field_combined1b97e84f_fld17_Slot_ae_slot1_set, - Field_combined1b97e84f_fld76_Slot_ae_slot1_set, - Field_combined1b97e84f_fld73_Slot_ae_slot1_set, - Field_combined1b97e84f_fld62_Slot_ae_slot1_set, - Field_combined1b97e84f_fld24_Slot_ae_slot1_set, - Field_combined1b97e84f_fld70_Slot_ae_slot1_set, - Field_combined1b97e84f_fld58_Slot_ae_slot1_set, - Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_set, - Field_op0_s3_s3_Slot_ae_slot1_set, - Field_combined1b97e84f_fld49_Slot_ae_slot1_set, - Field_combined1b97e84f_fld51_Slot_ae_slot1_set, - Field_combined1b97e84f_fld23_Slot_ae_slot1_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_ae_slot0_get_field_fns[] = { - Field_t_Slot_ae_slot0_get, - 0, - Field_bbi_Slot_ae_slot0_get, - Field_imm12_Slot_ae_slot0_get, - Field_imm8_Slot_ae_slot0_get, - Field_s_Slot_ae_slot0_get, - Field_imm12b_Slot_ae_slot0_get, - Field_imm16_Slot_ae_slot0_get, - 0, - 0, - Field_offset_Slot_ae_slot0_get, - 0, - 0, - Field_op2_Slot_ae_slot0_get, - Field_r_Slot_ae_slot0_get, - 0, - 0, - Field_sae_Slot_ae_slot0_get, - Field_sal_Slot_ae_slot0_get, - Field_sargt_Slot_ae_slot0_get, - 0, - Field_sas_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_s4_Slot_ae_slot0_get, - 0, - 0, - Field_s8_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot0_get, - Field_ae_samt_s_t_Slot_ae_slot0_get, - Field_ae_r20_Slot_ae_slot0_get, - Field_ae_r10_Slot_ae_slot0_get, - Field_ae_s20_Slot_ae_slot0_get, - 0, - 0, - 0, - Field_ftsf12_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s4_Slot_ae_slot0_get, - Field_ftsf212ae_slot0_Slot_ae_slot0_get, - Field_ftsf213ae_slot0_Slot_ae_slot0_get, - Field_ftsf214ae_slot0_Slot_ae_slot0_get, - Field_ftsf215ae_slot0_Slot_ae_slot0_get, - Field_ftsf216ae_slot0_Slot_ae_slot0_get, - Field_ftsf217_Slot_ae_slot0_get, - Field_ftsf218ae_slot0_Slot_ae_slot0_get, - Field_ftsf219ae_slot0_Slot_ae_slot0_get, - Field_ftsf220ae_slot0_Slot_ae_slot0_get, - Field_ftsf221ae_slot0_Slot_ae_slot0_get, - Field_ftsf222ae_slot0_Slot_ae_slot0_get, - Field_ftsf223ae_slot0_Slot_ae_slot0_get, - Field_ftsf224ae_slot0_Slot_ae_slot0_get, - Field_ftsf225ae_slot0_Slot_ae_slot0_get, - Field_ftsf226ae_slot0_Slot_ae_slot0_get, - Field_ftsf227ae_slot0_Slot_ae_slot0_get, - Field_ftsf228ae_slot0_Slot_ae_slot0_get, - Field_ftsf229ae_slot0_Slot_ae_slot0_get, - Field_ftsf230ae_slot0_Slot_ae_slot0_get, - Field_ftsf231ae_slot0_Slot_ae_slot0_get, - Field_ftsf232ae_slot0_Slot_ae_slot0_get, - Field_ftsf233ae_slot0_Slot_ae_slot0_get, - Field_ftsf234ae_slot0_Slot_ae_slot0_get, - Field_ftsf235ae_slot0_Slot_ae_slot0_get, - Field_ftsf236ae_slot0_Slot_ae_slot0_get, - Field_ftsf237ae_slot0_Slot_ae_slot0_get, - Field_ftsf238ae_slot0_Slot_ae_slot0_get, - Field_ftsf239ae_slot0_Slot_ae_slot0_get, - Field_ftsf240ae_slot0_Slot_ae_slot0_get, - Field_ftsf241ae_slot0_Slot_ae_slot0_get, - Field_ftsf242ae_slot0_Slot_ae_slot0_get, - Field_ftsf243ae_slot0_Slot_ae_slot0_get, - Field_ftsf244ae_slot0_Slot_ae_slot0_get, - Field_ftsf245ae_slot0_Slot_ae_slot0_get, - Field_ftsf246ae_slot0_Slot_ae_slot0_get, - Field_ftsf247ae_slot0_Slot_ae_slot0_get, - Field_ftsf248ae_slot0_Slot_ae_slot0_get, - Field_ftsf249ae_slot0_Slot_ae_slot0_get, - Field_ftsf250ae_slot0_Slot_ae_slot0_get, - Field_ftsf251ae_slot0_Slot_ae_slot0_get, - Field_ftsf252ae_slot0_Slot_ae_slot0_get, - Field_ftsf253ae_slot0_Slot_ae_slot0_get, - Field_ftsf254ae_slot0_Slot_ae_slot0_get, - Field_ftsf255ae_slot0_Slot_ae_slot0_get, - Field_ftsf256ae_slot0_Slot_ae_slot0_get, - Field_ftsf257ae_slot0_Slot_ae_slot0_get, - Field_ftsf258ae_slot0_Slot_ae_slot0_get, - Field_ftsf259ae_slot0_Slot_ae_slot0_get, - Field_ftsf260ae_slot0_Slot_ae_slot0_get, - Field_ftsf261ae_slot0_Slot_ae_slot0_get, - Field_ftsf262ae_slot0_Slot_ae_slot0_get, - Field_ftsf263ae_slot0_Slot_ae_slot0_get, - Field_ftsf264ae_slot0_Slot_ae_slot0_get, - Field_ftsf265ae_slot0_Slot_ae_slot0_get, - Field_ftsf266ae_slot0_Slot_ae_slot0_get, - Field_ftsf267ae_slot0_Slot_ae_slot0_get, - Field_ftsf268ae_slot0_Slot_ae_slot0_get, - Field_ftsf269ae_slot0_Slot_ae_slot0_get, - Field_ftsf270ae_slot0_Slot_ae_slot0_get, - Field_ftsf271ae_slot0_Slot_ae_slot0_get, - Field_ftsf272ae_slot0_Slot_ae_slot0_get, - Field_ftsf273ae_slot0_Slot_ae_slot0_get, - Field_ftsf274ae_slot0_Slot_ae_slot0_get, - Field_ftsf275ae_slot0_Slot_ae_slot0_get, - Field_ftsf276ae_slot0_Slot_ae_slot0_get, - Field_ftsf277ae_slot0_Slot_ae_slot0_get, - Field_ftsf278ae_slot0_Slot_ae_slot0_get, - Field_ftsf279ae_slot0_Slot_ae_slot0_get, - Field_ftsf281ae_slot0_Slot_ae_slot0_get, - Field_ftsf282ae_slot0_Slot_ae_slot0_get, - Field_ftsf283ae_slot0_Slot_ae_slot0_get, - Field_ftsf284ae_slot0_Slot_ae_slot0_get, - Field_ftsf286ae_slot0_Slot_ae_slot0_get, - Field_ftsf288ae_slot0_Slot_ae_slot0_get, - Field_ftsf290ae_slot0_Slot_ae_slot0_get, - Field_ftsf292ae_slot0_Slot_ae_slot0_get, - Field_ftsf293_Slot_ae_slot0_get, - Field_ftsf294ae_slot0_Slot_ae_slot0_get, - Field_ftsf295ae_slot0_Slot_ae_slot0_get, - Field_ftsf296ae_slot0_Slot_ae_slot0_get, - Field_ftsf297ae_slot0_Slot_ae_slot0_get, - Field_ftsf298ae_slot0_Slot_ae_slot0_get, - Field_ftsf299ae_slot0_Slot_ae_slot0_get, - Field_ftsf300ae_slot0_Slot_ae_slot0_get, - Field_ftsf301ae_slot0_Slot_ae_slot0_get, - Field_ftsf302ae_slot0_Slot_ae_slot0_get, - Field_ftsf303ae_slot0_Slot_ae_slot0_get, - Field_ftsf304ae_slot0_Slot_ae_slot0_get, - Field_ftsf306ae_slot0_Slot_ae_slot0_get, - Field_ftsf308ae_slot0_Slot_ae_slot0_get, - Field_ftsf309ae_slot0_Slot_ae_slot0_get, - Field_ftsf310ae_slot0_Slot_ae_slot0_get, - Field_ftsf311ae_slot0_Slot_ae_slot0_get, - Field_ftsf312ae_slot0_Slot_ae_slot0_get, - Field_ftsf313ae_slot0_Slot_ae_slot0_get, - Field_ftsf314ae_slot0_Slot_ae_slot0_get, - Field_ftsf315ae_slot0_Slot_ae_slot0_get, - Field_ftsf316ae_slot0_Slot_ae_slot0_get, - Field_ftsf317ae_slot0_Slot_ae_slot0_get, - Field_ftsf318ae_slot0_Slot_ae_slot0_get, - Field_ftsf319_Slot_ae_slot0_get, - Field_ftsf320ae_slot0_Slot_ae_slot0_get, - Field_ftsf321_Slot_ae_slot0_get, - Field_ftsf322ae_slot0_Slot_ae_slot0_get, - Field_ftsf323ae_slot0_Slot_ae_slot0_get, - Field_ftsf324ae_slot0_Slot_ae_slot0_get, - Field_ftsf325ae_slot0_Slot_ae_slot0_get, - Field_ftsf326ae_slot0_Slot_ae_slot0_get, - Field_ftsf328ae_slot0_Slot_ae_slot0_get, - Field_ftsf329ae_slot0_Slot_ae_slot0_get, - Field_ftsf352ae_slot0_Slot_ae_slot0_get, - Field_ftsf353_Slot_ae_slot0_get, - Field_ftsf354ae_slot0_Slot_ae_slot0_get, - Field_ftsf356ae_slot0_Slot_ae_slot0_get, - Field_ftsf357_Slot_ae_slot0_get, - Field_ftsf358ae_slot0_Slot_ae_slot0_get, - Field_ftsf359ae_slot0_Slot_ae_slot0_get, - Field_ftsf360ae_slot0_Slot_ae_slot0_get, - Field_ftsf361ae_slot0_Slot_ae_slot0_get, - Field_ftsf362ae_slot0_Slot_ae_slot0_get, - Field_ftsf364ae_slot0_Slot_ae_slot0_get, - Field_ftsf365ae_slot0_Slot_ae_slot0_get, - Field_ftsf366ae_slot0_Slot_ae_slot0_get, - Field_ftsf368ae_slot0_Slot_ae_slot0_get, - Field_ftsf369ae_slot0_Slot_ae_slot0_get, - 0, - Field_combined1b97e84f_fld115_Slot_ae_slot0_get, - Field_combined1b97e84f_fld97_Slot_ae_slot0_get, - Field_combined1b97e84f_fld124_Slot_ae_slot0_get, - Field_combined1b97e84f_fld79_Slot_ae_slot0_get, - Field_combined1b97e84f_fld80_Slot_ae_slot0_get, - Field_combined1b97e84f_fld108_Slot_ae_slot0_get, - Field_combined1b97e84f_fld101_Slot_ae_slot0_get, - Field_combined1b97e84f_fld88_Slot_ae_slot0_get, - Field_combined1b97e84f_fld39_Slot_ae_slot0_get, - Field_op0_s4_s4_Slot_ae_slot0_get, - Field_combined1b97e84f_fld83_Slot_ae_slot0_get, - Field_combined1b97e84f_fld90_Slot_ae_slot0_get, - Field_combined1b97e84f_fld93_Slot_ae_slot0_get, - Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_get, - Field_combined4b12daa6_fld122_Slot_ae_slot0_get, - Field_combined4b12daa6_fld115_Slot_ae_slot0_get, - Field_combined4b12daa6_fld85_Slot_ae_slot0_get, - Field_combined4b12daa6_fld119_Slot_ae_slot0_get, - Field_combined4b12daa6_fld97_Slot_ae_slot0_get, - Field_combined4b12daa6_fld124_Slot_ae_slot0_get, - Field_combined4b12daa6_fld79_Slot_ae_slot0_get, - Field_combined4b12daa6_fld80_Slot_ae_slot0_get, - Field_combined4b12daa6_fld108_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_ae_slot0_set_field_fns[] = { - Field_t_Slot_ae_slot0_set, - 0, - Field_bbi_Slot_ae_slot0_set, - Field_imm12_Slot_ae_slot0_set, - Field_imm8_Slot_ae_slot0_set, - Field_s_Slot_ae_slot0_set, - Field_imm12b_Slot_ae_slot0_set, - Field_imm16_Slot_ae_slot0_set, - 0, - 0, - Field_offset_Slot_ae_slot0_set, - 0, - 0, - Field_op2_Slot_ae_slot0_set, - Field_r_Slot_ae_slot0_set, - 0, - 0, - Field_sae_Slot_ae_slot0_set, - Field_sal_Slot_ae_slot0_set, - Field_sargt_Slot_ae_slot0_set, - 0, - Field_sas_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_s4_Slot_ae_slot0_set, - 0, - 0, - Field_s8_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot0_set, - Field_ae_samt_s_t_Slot_ae_slot0_set, - Field_ae_r20_Slot_ae_slot0_set, - Field_ae_r10_Slot_ae_slot0_set, - Field_ae_s20_Slot_ae_slot0_set, - 0, - 0, - 0, - Field_ftsf12_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s4_Slot_ae_slot0_set, - Field_ftsf212ae_slot0_Slot_ae_slot0_set, - Field_ftsf213ae_slot0_Slot_ae_slot0_set, - Field_ftsf214ae_slot0_Slot_ae_slot0_set, - Field_ftsf215ae_slot0_Slot_ae_slot0_set, - Field_ftsf216ae_slot0_Slot_ae_slot0_set, - Field_ftsf217_Slot_ae_slot0_set, - Field_ftsf218ae_slot0_Slot_ae_slot0_set, - Field_ftsf219ae_slot0_Slot_ae_slot0_set, - Field_ftsf220ae_slot0_Slot_ae_slot0_set, - Field_ftsf221ae_slot0_Slot_ae_slot0_set, - Field_ftsf222ae_slot0_Slot_ae_slot0_set, - Field_ftsf223ae_slot0_Slot_ae_slot0_set, - Field_ftsf224ae_slot0_Slot_ae_slot0_set, - Field_ftsf225ae_slot0_Slot_ae_slot0_set, - Field_ftsf226ae_slot0_Slot_ae_slot0_set, - Field_ftsf227ae_slot0_Slot_ae_slot0_set, - Field_ftsf228ae_slot0_Slot_ae_slot0_set, - Field_ftsf229ae_slot0_Slot_ae_slot0_set, - Field_ftsf230ae_slot0_Slot_ae_slot0_set, - Field_ftsf231ae_slot0_Slot_ae_slot0_set, - Field_ftsf232ae_slot0_Slot_ae_slot0_set, - Field_ftsf233ae_slot0_Slot_ae_slot0_set, - Field_ftsf234ae_slot0_Slot_ae_slot0_set, - Field_ftsf235ae_slot0_Slot_ae_slot0_set, - Field_ftsf236ae_slot0_Slot_ae_slot0_set, - Field_ftsf237ae_slot0_Slot_ae_slot0_set, - Field_ftsf238ae_slot0_Slot_ae_slot0_set, - Field_ftsf239ae_slot0_Slot_ae_slot0_set, - Field_ftsf240ae_slot0_Slot_ae_slot0_set, - Field_ftsf241ae_slot0_Slot_ae_slot0_set, - Field_ftsf242ae_slot0_Slot_ae_slot0_set, - Field_ftsf243ae_slot0_Slot_ae_slot0_set, - Field_ftsf244ae_slot0_Slot_ae_slot0_set, - Field_ftsf245ae_slot0_Slot_ae_slot0_set, - Field_ftsf246ae_slot0_Slot_ae_slot0_set, - Field_ftsf247ae_slot0_Slot_ae_slot0_set, - Field_ftsf248ae_slot0_Slot_ae_slot0_set, - Field_ftsf249ae_slot0_Slot_ae_slot0_set, - Field_ftsf250ae_slot0_Slot_ae_slot0_set, - Field_ftsf251ae_slot0_Slot_ae_slot0_set, - Field_ftsf252ae_slot0_Slot_ae_slot0_set, - Field_ftsf253ae_slot0_Slot_ae_slot0_set, - Field_ftsf254ae_slot0_Slot_ae_slot0_set, - Field_ftsf255ae_slot0_Slot_ae_slot0_set, - Field_ftsf256ae_slot0_Slot_ae_slot0_set, - Field_ftsf257ae_slot0_Slot_ae_slot0_set, - Field_ftsf258ae_slot0_Slot_ae_slot0_set, - Field_ftsf259ae_slot0_Slot_ae_slot0_set, - Field_ftsf260ae_slot0_Slot_ae_slot0_set, - Field_ftsf261ae_slot0_Slot_ae_slot0_set, - Field_ftsf262ae_slot0_Slot_ae_slot0_set, - Field_ftsf263ae_slot0_Slot_ae_slot0_set, - Field_ftsf264ae_slot0_Slot_ae_slot0_set, - Field_ftsf265ae_slot0_Slot_ae_slot0_set, - Field_ftsf266ae_slot0_Slot_ae_slot0_set, - Field_ftsf267ae_slot0_Slot_ae_slot0_set, - Field_ftsf268ae_slot0_Slot_ae_slot0_set, - Field_ftsf269ae_slot0_Slot_ae_slot0_set, - Field_ftsf270ae_slot0_Slot_ae_slot0_set, - Field_ftsf271ae_slot0_Slot_ae_slot0_set, - Field_ftsf272ae_slot0_Slot_ae_slot0_set, - Field_ftsf273ae_slot0_Slot_ae_slot0_set, - Field_ftsf274ae_slot0_Slot_ae_slot0_set, - Field_ftsf275ae_slot0_Slot_ae_slot0_set, - Field_ftsf276ae_slot0_Slot_ae_slot0_set, - Field_ftsf277ae_slot0_Slot_ae_slot0_set, - Field_ftsf278ae_slot0_Slot_ae_slot0_set, - Field_ftsf279ae_slot0_Slot_ae_slot0_set, - Field_ftsf281ae_slot0_Slot_ae_slot0_set, - Field_ftsf282ae_slot0_Slot_ae_slot0_set, - Field_ftsf283ae_slot0_Slot_ae_slot0_set, - Field_ftsf284ae_slot0_Slot_ae_slot0_set, - Field_ftsf286ae_slot0_Slot_ae_slot0_set, - Field_ftsf288ae_slot0_Slot_ae_slot0_set, - Field_ftsf290ae_slot0_Slot_ae_slot0_set, - Field_ftsf292ae_slot0_Slot_ae_slot0_set, - Field_ftsf293_Slot_ae_slot0_set, - Field_ftsf294ae_slot0_Slot_ae_slot0_set, - Field_ftsf295ae_slot0_Slot_ae_slot0_set, - Field_ftsf296ae_slot0_Slot_ae_slot0_set, - Field_ftsf297ae_slot0_Slot_ae_slot0_set, - Field_ftsf298ae_slot0_Slot_ae_slot0_set, - Field_ftsf299ae_slot0_Slot_ae_slot0_set, - Field_ftsf300ae_slot0_Slot_ae_slot0_set, - Field_ftsf301ae_slot0_Slot_ae_slot0_set, - Field_ftsf302ae_slot0_Slot_ae_slot0_set, - Field_ftsf303ae_slot0_Slot_ae_slot0_set, - Field_ftsf304ae_slot0_Slot_ae_slot0_set, - Field_ftsf306ae_slot0_Slot_ae_slot0_set, - Field_ftsf308ae_slot0_Slot_ae_slot0_set, - Field_ftsf309ae_slot0_Slot_ae_slot0_set, - Field_ftsf310ae_slot0_Slot_ae_slot0_set, - Field_ftsf311ae_slot0_Slot_ae_slot0_set, - Field_ftsf312ae_slot0_Slot_ae_slot0_set, - Field_ftsf313ae_slot0_Slot_ae_slot0_set, - Field_ftsf314ae_slot0_Slot_ae_slot0_set, - Field_ftsf315ae_slot0_Slot_ae_slot0_set, - Field_ftsf316ae_slot0_Slot_ae_slot0_set, - Field_ftsf317ae_slot0_Slot_ae_slot0_set, - Field_ftsf318ae_slot0_Slot_ae_slot0_set, - Field_ftsf319_Slot_ae_slot0_set, - Field_ftsf320ae_slot0_Slot_ae_slot0_set, - Field_ftsf321_Slot_ae_slot0_set, - Field_ftsf322ae_slot0_Slot_ae_slot0_set, - Field_ftsf323ae_slot0_Slot_ae_slot0_set, - Field_ftsf324ae_slot0_Slot_ae_slot0_set, - Field_ftsf325ae_slot0_Slot_ae_slot0_set, - Field_ftsf326ae_slot0_Slot_ae_slot0_set, - Field_ftsf328ae_slot0_Slot_ae_slot0_set, - Field_ftsf329ae_slot0_Slot_ae_slot0_set, - Field_ftsf352ae_slot0_Slot_ae_slot0_set, - Field_ftsf353_Slot_ae_slot0_set, - Field_ftsf354ae_slot0_Slot_ae_slot0_set, - Field_ftsf356ae_slot0_Slot_ae_slot0_set, - Field_ftsf357_Slot_ae_slot0_set, - Field_ftsf358ae_slot0_Slot_ae_slot0_set, - Field_ftsf359ae_slot0_Slot_ae_slot0_set, - Field_ftsf360ae_slot0_Slot_ae_slot0_set, - Field_ftsf361ae_slot0_Slot_ae_slot0_set, - Field_ftsf362ae_slot0_Slot_ae_slot0_set, - Field_ftsf364ae_slot0_Slot_ae_slot0_set, - Field_ftsf365ae_slot0_Slot_ae_slot0_set, - Field_ftsf366ae_slot0_Slot_ae_slot0_set, - Field_ftsf368ae_slot0_Slot_ae_slot0_set, - Field_ftsf369ae_slot0_Slot_ae_slot0_set, - 0, - Field_combined1b97e84f_fld115_Slot_ae_slot0_set, - Field_combined1b97e84f_fld97_Slot_ae_slot0_set, - Field_combined1b97e84f_fld124_Slot_ae_slot0_set, - Field_combined1b97e84f_fld79_Slot_ae_slot0_set, - Field_combined1b97e84f_fld80_Slot_ae_slot0_set, - Field_combined1b97e84f_fld108_Slot_ae_slot0_set, - Field_combined1b97e84f_fld101_Slot_ae_slot0_set, - Field_combined1b97e84f_fld88_Slot_ae_slot0_set, - Field_combined1b97e84f_fld39_Slot_ae_slot0_set, - Field_op0_s4_s4_Slot_ae_slot0_set, - Field_combined1b97e84f_fld83_Slot_ae_slot0_set, - Field_combined1b97e84f_fld90_Slot_ae_slot0_set, - Field_combined1b97e84f_fld93_Slot_ae_slot0_set, - Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_set, - Field_combined4b12daa6_fld122_Slot_ae_slot0_set, - Field_combined4b12daa6_fld115_Slot_ae_slot0_set, - Field_combined4b12daa6_fld85_Slot_ae_slot0_set, - Field_combined4b12daa6_fld119_Slot_ae_slot0_set, - Field_combined4b12daa6_fld97_Slot_ae_slot0_set, - Field_combined4b12daa6_fld124_Slot_ae_slot0_set, - Field_combined4b12daa6_fld79_Slot_ae_slot0_set, - Field_combined4b12daa6_fld80_Slot_ae_slot0_set, - Field_combined4b12daa6_fld108_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_slot_internal slots[] = { - { "Inst", "x24", 0, - Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, - Slot_inst_get_field_fns, Slot_inst_set_field_fns, - Slot_inst_decode, "nop" }, - { "Inst16a", "x16a", 0, - Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, - Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, - Slot_inst16a_decode, "" }, - { "Inst16b", "x16b", 0, - Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, - Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, - Slot_inst16b_decode, "nop.n" }, - { "ae_slot1", "ae_format", 1, - Slot_ae_format_Format_ae_slot1_31_get, Slot_ae_format_Format_ae_slot1_31_set, - Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns, - Slot_ae_slot1_decode, "nop" }, - { "ae_slot0", "ae_format", 0, - Slot_ae_format_Format_ae_slot0_4_get, Slot_ae_format_Format_ae_slot0_4_set, - Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns, - Slot_ae_slot0_decode, "nop" } -}; - - -/* Instruction formats. */ - -static void -Format_x24_encode (xtensa_insnbuf insn) -{ - insn[0] = 0; - insn[1] = 0; -} - -static void -Format_x16a_encode (xtensa_insnbuf insn) -{ - insn[0] = 0x8; - insn[1] = 0; -} - -static void -Format_x16b_encode (xtensa_insnbuf insn) -{ - insn[0] = 0xc; - insn[1] = 0; -} - -static void -Format_ae_format_encode (xtensa_insnbuf insn) -{ - insn[0] = 0xf; - insn[1] = 0; -} - -static int Format_x24_slots[] = { 0 }; - -static int Format_x16a_slots[] = { 1 }; - -static int Format_x16b_slots[] = { 2 }; - -static int Format_ae_format_slots[] = { 4, 3 }; - -static xtensa_format_internal formats[] = { - { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, - { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, - { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, - { "ae_format", 8, Format_ae_format_encode, 2, Format_ae_format_slots } -}; - - -static int -format_decoder (const xtensa_insnbuf insn) -{ - if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0) - return 0; /* x24 */ - if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0) - return 1; /* x16a */ - if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0) - return 2; /* x16b */ - if ((insn[0] & 0xf) == 0xf && (insn[1] & 0xffc00000) == 0) - return 3; /* ae_format */ - return -1; -} - -static int length_table[16] = { - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8 -}; - -static int -length_decoder (const unsigned char *insn) -{ - int op0 = insn[0] & 0xf; - return length_table[op0]; -} - - -/* Top-level ISA structure. */ - -xtensa_isa_internal xtensa_modules = { - 0 /* little-endian */, - 8 /* insn_size */, 0, - 4, formats, format_decoder, length_decoder, - 5, slots, - 448 /* num_fields */, - 515, operands, - 710, iclasses, - 842, opcodes, 0, - 9, regfiles, - NUM_STATES, states, 0, - NUM_SYSREGS, sysregs, 0, - { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, - 0, interfaces, 0, - 4, funcUnits, 0 -}; diff --git a/overlays/xtensa_intel_byt_adsp/binutils/include/xtensa-config.h b/overlays/xtensa_intel_byt_adsp/binutils/include/xtensa-config.h deleted file mode 100644 index f60dc1f..0000000 --- a/overlays/xtensa_intel_byt_adsp/binutils/include/xtensa-config.h +++ /dev/null @@ -1,174 +0,0 @@ -/* Xtensa configuration settings. - Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 - Free Software Foundation, Inc. - Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef XTENSA_CONFIG_H -#define XTENSA_CONFIG_H - -/* The macros defined here match those with the same names in the Xtensa - compile-time HAL (Hardware Abstraction Layer). Please refer to the - Xtensa System Software Reference Manual for documentation of these - macros. */ - -#undef XCHAL_HAVE_BE -#define XCHAL_HAVE_BE 0 - -#undef XCHAL_HAVE_DENSITY -#define XCHAL_HAVE_DENSITY 1 - -#undef XCHAL_HAVE_CONST16 -#define XCHAL_HAVE_CONST16 0 - -#undef XCHAL_HAVE_ABS -#define XCHAL_HAVE_ABS 1 - -#undef XCHAL_HAVE_ADDX -#define XCHAL_HAVE_ADDX 1 - -#undef XCHAL_HAVE_L32R -#define XCHAL_HAVE_L32R 1 - -#undef XSHAL_USE_ABSOLUTE_LITERALS -#define XSHAL_USE_ABSOLUTE_LITERALS 0 - -#undef XSHAL_HAVE_TEXT_SECTION_LITERALS -#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ - -#undef XCHAL_HAVE_MAC16 -#define XCHAL_HAVE_MAC16 1 - -#undef XCHAL_HAVE_MUL16 -#define XCHAL_HAVE_MUL16 1 - -#undef XCHAL_HAVE_MUL32 -#define XCHAL_HAVE_MUL32 1 - -#undef XCHAL_HAVE_MUL32_HIGH -#define XCHAL_HAVE_MUL32_HIGH 1 - -#undef XCHAL_HAVE_DIV32 -#define XCHAL_HAVE_DIV32 0 - -#undef XCHAL_HAVE_NSA -#define XCHAL_HAVE_NSA 1 - -#undef XCHAL_HAVE_MINMAX -#define XCHAL_HAVE_MINMAX 1 - -#undef XCHAL_HAVE_SEXT -#define XCHAL_HAVE_SEXT 1 - -#undef XCHAL_HAVE_LOOPS -#define XCHAL_HAVE_LOOPS 1 - -#undef XCHAL_HAVE_THREADPTR -#define XCHAL_HAVE_THREADPTR 1 - -#undef XCHAL_HAVE_RELEASE_SYNC -#define XCHAL_HAVE_RELEASE_SYNC 1 - -#undef XCHAL_HAVE_S32C1I -#define XCHAL_HAVE_S32C1I 1 - -#undef XCHAL_HAVE_BOOLEANS -#define XCHAL_HAVE_BOOLEANS 1 - -#undef XCHAL_HAVE_FP -#define XCHAL_HAVE_FP 0 - -#undef XCHAL_HAVE_FP_DIV -#define XCHAL_HAVE_FP_DIV 0 - -#undef XCHAL_HAVE_FP_RECIP -#define XCHAL_HAVE_FP_RECIP 0 - -#undef XCHAL_HAVE_FP_SQRT -#define XCHAL_HAVE_FP_SQRT 0 - -#undef XCHAL_HAVE_FP_RSQRT -#define XCHAL_HAVE_FP_RSQRT 0 - -#undef XCHAL_HAVE_DFP_accel -#define XCHAL_HAVE_DFP_accel 0 -#undef XCHAL_HAVE_WINDOWED -#define XCHAL_HAVE_WINDOWED 1 - -#undef XCHAL_NUM_AREGS -#define XCHAL_NUM_AREGS 32 - -#undef XCHAL_HAVE_WIDE_BRANCHES -#define XCHAL_HAVE_WIDE_BRANCHES 0 - -#undef XCHAL_HAVE_PREDICTED_BRANCHES -#define XCHAL_HAVE_PREDICTED_BRANCHES 0 - - -#undef XCHAL_ICACHE_SIZE -#define XCHAL_ICACHE_SIZE 49152 - -#undef XCHAL_DCACHE_SIZE -#define XCHAL_DCACHE_SIZE 98304 - -#undef XCHAL_ICACHE_LINESIZE -#define XCHAL_ICACHE_LINESIZE 128 - -#undef XCHAL_DCACHE_LINESIZE -#define XCHAL_DCACHE_LINESIZE 128 - -#undef XCHAL_ICACHE_LINEWIDTH -#define XCHAL_ICACHE_LINEWIDTH 7 - -#undef XCHAL_DCACHE_LINEWIDTH -#define XCHAL_DCACHE_LINEWIDTH 7 - -#undef XCHAL_DCACHE_IS_WRITEBACK -#define XCHAL_DCACHE_IS_WRITEBACK 1 - - -#undef XCHAL_HAVE_MMU -#define XCHAL_HAVE_MMU 0 - - -#undef XCHAL_HAVE_DEBUG -#define XCHAL_HAVE_DEBUG 1 - -#undef XCHAL_NUM_IBREAK -#define XCHAL_NUM_IBREAK 2 - -#undef XCHAL_NUM_DBREAK -#define XCHAL_NUM_DBREAK 2 - -#undef XCHAL_DEBUGLEVEL -#define XCHAL_DEBUGLEVEL 6 - - -#undef XCHAL_MAX_INSTRUCTION_SIZE -#define XCHAL_MAX_INSTRUCTION_SIZE 8 - -#undef XCHAL_INST_FETCH_WIDTH -#define XCHAL_INST_FETCH_WIDTH 8 - - -#undef XSHAL_ABI -#undef XTHAL_ABI_WINDOWED -#undef XTHAL_ABI_CALL0 -#define XSHAL_ABI XTHAL_ABI_WINDOWED -#define XTHAL_ABI_WINDOWED 0 -#define XTHAL_ABI_CALL0 1 - -#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_intel_byt_adsp/gcc/include/xtensa-config.h b/overlays/xtensa_intel_byt_adsp/gcc/include/xtensa-config.h deleted file mode 100644 index f60dc1f..0000000 --- a/overlays/xtensa_intel_byt_adsp/gcc/include/xtensa-config.h +++ /dev/null @@ -1,174 +0,0 @@ -/* Xtensa configuration settings. - Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 - Free Software Foundation, Inc. - Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef XTENSA_CONFIG_H -#define XTENSA_CONFIG_H - -/* The macros defined here match those with the same names in the Xtensa - compile-time HAL (Hardware Abstraction Layer). Please refer to the - Xtensa System Software Reference Manual for documentation of these - macros. */ - -#undef XCHAL_HAVE_BE -#define XCHAL_HAVE_BE 0 - -#undef XCHAL_HAVE_DENSITY -#define XCHAL_HAVE_DENSITY 1 - -#undef XCHAL_HAVE_CONST16 -#define XCHAL_HAVE_CONST16 0 - -#undef XCHAL_HAVE_ABS -#define XCHAL_HAVE_ABS 1 - -#undef XCHAL_HAVE_ADDX -#define XCHAL_HAVE_ADDX 1 - -#undef XCHAL_HAVE_L32R -#define XCHAL_HAVE_L32R 1 - -#undef XSHAL_USE_ABSOLUTE_LITERALS -#define XSHAL_USE_ABSOLUTE_LITERALS 0 - -#undef XSHAL_HAVE_TEXT_SECTION_LITERALS -#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ - -#undef XCHAL_HAVE_MAC16 -#define XCHAL_HAVE_MAC16 1 - -#undef XCHAL_HAVE_MUL16 -#define XCHAL_HAVE_MUL16 1 - -#undef XCHAL_HAVE_MUL32 -#define XCHAL_HAVE_MUL32 1 - -#undef XCHAL_HAVE_MUL32_HIGH -#define XCHAL_HAVE_MUL32_HIGH 1 - -#undef XCHAL_HAVE_DIV32 -#define XCHAL_HAVE_DIV32 0 - -#undef XCHAL_HAVE_NSA -#define XCHAL_HAVE_NSA 1 - -#undef XCHAL_HAVE_MINMAX -#define XCHAL_HAVE_MINMAX 1 - -#undef XCHAL_HAVE_SEXT -#define XCHAL_HAVE_SEXT 1 - -#undef XCHAL_HAVE_LOOPS -#define XCHAL_HAVE_LOOPS 1 - -#undef XCHAL_HAVE_THREADPTR -#define XCHAL_HAVE_THREADPTR 1 - -#undef XCHAL_HAVE_RELEASE_SYNC -#define XCHAL_HAVE_RELEASE_SYNC 1 - -#undef XCHAL_HAVE_S32C1I -#define XCHAL_HAVE_S32C1I 1 - -#undef XCHAL_HAVE_BOOLEANS -#define XCHAL_HAVE_BOOLEANS 1 - -#undef XCHAL_HAVE_FP -#define XCHAL_HAVE_FP 0 - -#undef XCHAL_HAVE_FP_DIV -#define XCHAL_HAVE_FP_DIV 0 - -#undef XCHAL_HAVE_FP_RECIP -#define XCHAL_HAVE_FP_RECIP 0 - -#undef XCHAL_HAVE_FP_SQRT -#define XCHAL_HAVE_FP_SQRT 0 - -#undef XCHAL_HAVE_FP_RSQRT -#define XCHAL_HAVE_FP_RSQRT 0 - -#undef XCHAL_HAVE_DFP_accel -#define XCHAL_HAVE_DFP_accel 0 -#undef XCHAL_HAVE_WINDOWED -#define XCHAL_HAVE_WINDOWED 1 - -#undef XCHAL_NUM_AREGS -#define XCHAL_NUM_AREGS 32 - -#undef XCHAL_HAVE_WIDE_BRANCHES -#define XCHAL_HAVE_WIDE_BRANCHES 0 - -#undef XCHAL_HAVE_PREDICTED_BRANCHES -#define XCHAL_HAVE_PREDICTED_BRANCHES 0 - - -#undef XCHAL_ICACHE_SIZE -#define XCHAL_ICACHE_SIZE 49152 - -#undef XCHAL_DCACHE_SIZE -#define XCHAL_DCACHE_SIZE 98304 - -#undef XCHAL_ICACHE_LINESIZE -#define XCHAL_ICACHE_LINESIZE 128 - -#undef XCHAL_DCACHE_LINESIZE -#define XCHAL_DCACHE_LINESIZE 128 - -#undef XCHAL_ICACHE_LINEWIDTH -#define XCHAL_ICACHE_LINEWIDTH 7 - -#undef XCHAL_DCACHE_LINEWIDTH -#define XCHAL_DCACHE_LINEWIDTH 7 - -#undef XCHAL_DCACHE_IS_WRITEBACK -#define XCHAL_DCACHE_IS_WRITEBACK 1 - - -#undef XCHAL_HAVE_MMU -#define XCHAL_HAVE_MMU 0 - - -#undef XCHAL_HAVE_DEBUG -#define XCHAL_HAVE_DEBUG 1 - -#undef XCHAL_NUM_IBREAK -#define XCHAL_NUM_IBREAK 2 - -#undef XCHAL_NUM_DBREAK -#define XCHAL_NUM_DBREAK 2 - -#undef XCHAL_DEBUGLEVEL -#define XCHAL_DEBUGLEVEL 6 - - -#undef XCHAL_MAX_INSTRUCTION_SIZE -#define XCHAL_MAX_INSTRUCTION_SIZE 8 - -#undef XCHAL_INST_FETCH_WIDTH -#define XCHAL_INST_FETCH_WIDTH 8 - - -#undef XSHAL_ABI -#undef XTHAL_ABI_WINDOWED -#undef XTHAL_ABI_CALL0 -#define XSHAL_ABI XTHAL_ABI_WINDOWED -#define XTHAL_ABI_WINDOWED 0 -#define XTHAL_ABI_CALL0 1 - -#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_intel_byt_adsp/gdb/bfd/xtensa-modules.c b/overlays/xtensa_intel_byt_adsp/gdb/bfd/xtensa-modules.c deleted file mode 100644 index ee283c6..0000000 --- a/overlays/xtensa_intel_byt_adsp/gdb/bfd/xtensa-modules.c +++ /dev/null @@ -1,42978 +0,0 @@ -/* Xtensa configuration-specific ISA information. - - Copyright (c) 2003-2017 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#include "ansidecl.h" -#include -#include "xtensa-isa-internal.h" - - -/* Sysregs. */ - -static xtensa_sysreg_internal sysregs[] = { - { "LBEG", 0, 0 }, - { "LEND", 1, 0 }, - { "LCOUNT", 2, 0 }, - { "BR", 4, 0 }, - { "ACCLO", 16, 0 }, - { "ACCHI", 17, 0 }, - { "M0", 32, 0 }, - { "M1", 33, 0 }, - { "M2", 34, 0 }, - { "M3", 35, 0 }, - { "DDR", 104, 0 }, - { "CONFIGID0", 176, 0 }, - { "CONFIGID1", 208, 0 }, - { "INTERRUPT", 226, 0 }, - { "INTCLEAR", 227, 0 }, - { "CCOUNT", 234, 0 }, - { "PRID", 235, 0 }, - { "ICOUNT", 236, 0 }, - { "CCOMPARE0", 240, 0 }, - { "CCOMPARE1", 241, 0 }, - { "CCOMPARE2", 242, 0 }, - { "VECBASE", 231, 0 }, - { "EPC1", 177, 0 }, - { "EPC2", 178, 0 }, - { "EPC3", 179, 0 }, - { "EPC4", 180, 0 }, - { "EPC5", 181, 0 }, - { "EPC6", 182, 0 }, - { "EPC7", 183, 0 }, - { "EXCSAVE1", 209, 0 }, - { "EXCSAVE2", 210, 0 }, - { "EXCSAVE3", 211, 0 }, - { "EXCSAVE4", 212, 0 }, - { "EXCSAVE5", 213, 0 }, - { "EXCSAVE6", 214, 0 }, - { "EXCSAVE7", 215, 0 }, - { "EPS2", 194, 0 }, - { "EPS3", 195, 0 }, - { "EPS4", 196, 0 }, - { "EPS5", 197, 0 }, - { "EPS6", 198, 0 }, - { "EPS7", 199, 0 }, - { "EXCCAUSE", 232, 0 }, - { "DEPC", 192, 0 }, - { "EXCVADDR", 238, 0 }, - { "WINDOWBASE", 72, 0 }, - { "WINDOWSTART", 73, 0 }, - { "SAR", 3, 0 }, - { "PS", 230, 0 }, - { "INTENABLE", 228, 0 }, - { "DBREAKA0", 144, 0 }, - { "DBREAKC0", 160, 0 }, - { "DBREAKA1", 145, 0 }, - { "DBREAKC1", 161, 0 }, - { "IBREAKA0", 128, 0 }, - { "IBREAKA1", 129, 0 }, - { "IBREAKENABLE", 96, 0 }, - { "ICOUNTLEVEL", 237, 0 }, - { "DEBUGCAUSE", 233, 0 }, - { "PREFCTL", 40, 0 }, - { "CPENABLE", 224, 0 }, - { "SCOMPARE1", 12, 0 }, - { "ATOMCTL", 99, 0 }, - { "THREADPTR", 231, 1 }, - { "AE_OVF_SAR", 240, 1 }, - { "AE_BITHEAD", 241, 1 }, - { "AE_TS_FTS_BU_BP", 242, 1 }, - { "AE_SD_NO", 243, 1 }, - { "AE_CBEGIN0", 246, 1 }, - { "AE_CEND0", 247, 1 } -}; - -#define NUM_SYSREGS 70 -#define MAX_SPECIAL_REG 242 -#define MAX_USER_REG 247 - - -/* Processor states. */ - -static xtensa_state_internal states[] = { - { "LCOUNT", 32, 0 }, - { "PC", 32, 0 }, - { "ICOUNT", 32, 0 }, - { "DDR", 32, 0 }, - { "INTERRUPT", 22, 0 }, - { "CCOUNT", 32, 0 }, - { "XTSYNC", 1, 0 }, - { "VECBASE", 22, 0 }, - { "EPC1", 32, 0 }, - { "EPC2", 32, 0 }, - { "EPC3", 32, 0 }, - { "EPC4", 32, 0 }, - { "EPC5", 32, 0 }, - { "EPC6", 32, 0 }, - { "EPC7", 32, 0 }, - { "EXCSAVE1", 32, 0 }, - { "EXCSAVE2", 32, 0 }, - { "EXCSAVE3", 32, 0 }, - { "EXCSAVE4", 32, 0 }, - { "EXCSAVE5", 32, 0 }, - { "EXCSAVE6", 32, 0 }, - { "EXCSAVE7", 32, 0 }, - { "EPS2", 13, 0 }, - { "EPS3", 13, 0 }, - { "EPS4", 13, 0 }, - { "EPS5", 13, 0 }, - { "EPS6", 13, 0 }, - { "EPS7", 13, 0 }, - { "EXCCAUSE", 6, 0 }, - { "PSINTLEVEL", 4, 0 }, - { "PSUM", 1, 0 }, - { "PSWOE", 1, 0 }, - { "PSEXCM", 1, 0 }, - { "DEPC", 32, 0 }, - { "EXCVADDR", 32, 0 }, - { "WindowBase", 3, 0 }, - { "WindowStart", 8, 0 }, - { "PSCALLINC", 2, 0 }, - { "PSOWB", 4, 0 }, - { "LBEG", 32, 0 }, - { "LEND", 32, 0 }, - { "SAR", 6, 0 }, - { "THREADPTR", 32, 0 }, - { "ACC", 40, 0 }, - { "InOCDMode", 1, 0 }, - { "INTENABLE", 22, 0 }, - { "DBREAKA0", 32, 0 }, - { "DBREAKC0", 8, 0 }, - { "DBREAKA1", 32, 0 }, - { "DBREAKC1", 8, 0 }, - { "IBREAKA0", 32, 0 }, - { "IBREAKA1", 32, 0 }, - { "IBREAKENABLE", 2, 0 }, - { "ICOUNTLEVEL", 4, 0 }, - { "DEBUGCAUSE", 6, 0 }, - { "DBNUM", 4, 0 }, - { "CCOMPARE0", 32, 0 }, - { "CCOMPARE1", 32, 0 }, - { "CCOMPARE2", 32, 0 }, - { "PREFCTL", 8, 0 }, - { "CPENABLE", 2, 0 }, - { "SCOMPARE1", 32, 0 }, - { "ATOMCTL", 6, 0 }, - { "AE_OVERFLOW", 1, XTENSA_STATE_IS_SHARED_OR }, - { "AE_SAR", 6, 0 }, - { "AE_BITHEAD", 32, 0 }, - { "AE_BITPTR", 4, 0 }, - { "AE_BITSUSED", 4, 0 }, - { "AE_TABLESIZE", 4, 0 }, - { "AE_FIRST_TS", 4, 0 }, - { "AE_NEXTOFFSET", 27, 0 }, - { "AE_SEARCHDONE", 1, 0 }, - { "AE_CBEGIN0", 32, 0 }, - { "AE_CEND0", 32, 0 } -}; - -#define NUM_STATES 74 - -enum xtensa_state_id { - STATE_LCOUNT, - STATE_PC, - STATE_ICOUNT, - STATE_DDR, - STATE_INTERRUPT, - STATE_CCOUNT, - STATE_XTSYNC, - STATE_VECBASE, - STATE_EPC1, - STATE_EPC2, - STATE_EPC3, - STATE_EPC4, - STATE_EPC5, - STATE_EPC6, - STATE_EPC7, - STATE_EXCSAVE1, - STATE_EXCSAVE2, - STATE_EXCSAVE3, - STATE_EXCSAVE4, - STATE_EXCSAVE5, - STATE_EXCSAVE6, - STATE_EXCSAVE7, - STATE_EPS2, - STATE_EPS3, - STATE_EPS4, - STATE_EPS5, - STATE_EPS6, - STATE_EPS7, - STATE_EXCCAUSE, - STATE_PSINTLEVEL, - STATE_PSUM, - STATE_PSWOE, - STATE_PSEXCM, - STATE_DEPC, - STATE_EXCVADDR, - STATE_WindowBase, - STATE_WindowStart, - STATE_PSCALLINC, - STATE_PSOWB, - STATE_LBEG, - STATE_LEND, - STATE_SAR, - STATE_THREADPTR, - STATE_ACC, - STATE_InOCDMode, - STATE_INTENABLE, - STATE_DBREAKA0, - STATE_DBREAKC0, - STATE_DBREAKA1, - STATE_DBREAKC1, - STATE_IBREAKA0, - STATE_IBREAKA1, - STATE_IBREAKENABLE, - STATE_ICOUNTLEVEL, - STATE_DEBUGCAUSE, - STATE_DBNUM, - STATE_CCOMPARE0, - STATE_CCOMPARE1, - STATE_CCOMPARE2, - STATE_PREFCTL, - STATE_CPENABLE, - STATE_SCOMPARE1, - STATE_ATOMCTL, - STATE_AE_OVERFLOW, - STATE_AE_SAR, - STATE_AE_BITHEAD, - STATE_AE_BITPTR, - STATE_AE_BITSUSED, - STATE_AE_TABLESIZE, - STATE_AE_FIRST_TS, - STATE_AE_NEXTOFFSET, - STATE_AE_SEARCHDONE, - STATE_AE_CBEGIN0, - STATE_AE_CEND0 -}; - - -/* Field definitions. */ - -static unsigned -Field_t_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_s_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_r_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_op2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); - return tie_t; -} - -static void -Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); -} - -static unsigned -Field_op1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_op0_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_n_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_m_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_sr_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_st_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_w_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_r3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ae_r3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_ae_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_ae_r10_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_ae_r32_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ae_s3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_ae_s3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_ae_s_non_samt_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_ae_s_non_samt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf61ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf61ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 22) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_op0_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - return tie_t; -} - -static void -Field_op0_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf330ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_ftsf330ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ftsf81ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf81ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ae_r20_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_ftsf73ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf73ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf35ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf35ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf34ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf34ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf32ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf32ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf33ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf33ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf96ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf96ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ae_s20_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); -} - -static unsigned -Field_ftsf94ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_ftsf94ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf347_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf347_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); -} - -static unsigned -Field_ftsf24ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - return tie_t; -} - -static void -Field_ftsf24ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf23ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - return tie_t; -} - -static void -Field_ftsf23ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf125ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_ftsf125ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_ftsf350ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); - return tie_t; -} - -static void -Field_ftsf350ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78) | (tie_t << 3); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf80ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf80ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf88ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf88ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 23) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf340_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf340_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_ftsf87ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf87ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x60) | (tie_t << 5); - tie_t = (val << 22) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf342ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_ftsf342ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_ftsf86ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); - return tie_t; -} - -static void -Field_ftsf86ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78) | (tie_t << 3); - tie_t = (val << 21) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf84ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); - return tie_t; -} - -static void -Field_ftsf84ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78) | (tie_t << 3); - tie_t = (val << 21) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf76ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf76ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf75ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf75ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf60ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf60ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 21) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf64ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf64ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 20) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf63ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf63ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ae_r10_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf59ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf59ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 21) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf119ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf119ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 24) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 21) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf338_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf338_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_ftsf69ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf69ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 22) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf67ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf67ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x60) | (tie_t << 5); - tie_t = (val << 21) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf66ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf66ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 20) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf25ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf25ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf36ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf36ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf103ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf103ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf349ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 23) >> 26); - return tie_t; -} - -static void -Field_ftsf349ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x1f8) | (tie_t << 3); -} - -static unsigned -Field_ftsf99ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf99ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf27ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf27ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf28ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf28ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf21ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf21ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf22ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf22ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf29ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf29ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf97ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf97ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf100ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf100ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf101ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - return tie_t; -} - -static void -Field_ftsf101ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf348ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); - return tie_t; -} - -static void -Field_ftsf348ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); -} - -static unsigned -Field_ftsf26ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf26ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf30ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf30ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf31ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf31ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf98ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf98ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf92ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); - return tie_t; -} - -static void -Field_ftsf92ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6) | (tie_t << 1); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf208_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf208_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); -} - -static unsigned -Field_ftsf91ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf91ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf90ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf90ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf126ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); - return tie_t; -} - -static void -Field_ftsf126ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); -} - -static unsigned -Field_ftsf344ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf344ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 23) >> 30; - insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); -} - -static unsigned -Field_ftsf112ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf112ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf122ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); - return tie_t; -} - -static void -Field_ftsf122ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); - tie_t = (val << 24) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf346ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf346ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf116ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); - return tie_t; -} - -static void -Field_ftsf116ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); - tie_t = (val << 20) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf109ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf109ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf111ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf111ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf104ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf104ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf105ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf105ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf107ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf107ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf113ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf113ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf118ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); - return tie_t; -} - -static void -Field_ftsf118ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); - tie_t = (val << 20) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf120ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 6) | ((insn[0] << 25) >> 26); - return tie_t; -} - -static void -Field_ftsf120ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x7e) | (tie_t << 1); - tie_t = (val << 23) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf343ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf343ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf108ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf108ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf115ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf115ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf110ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf110ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf114ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf114ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf37ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - return tie_t; -} - -static void -Field_ftsf37ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf78ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf78ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf79ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf79ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf77ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf77ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf13_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_ftsf13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf12_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - return tie_t; -} - -static void -Field_ftsf12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf82ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf82ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 24) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf341ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf341ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ftsf124ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf124ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 28) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf339ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf339ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ftsf106ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf106ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ae_r32_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ae_mul32x24fld_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ae_mul32x24fld_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf160ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf160ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf154ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf154ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf175ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf175ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf158ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf158ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf155ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf155ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf167ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf167ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf157ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf157ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf153ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf153ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf163ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf163ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf156ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf156ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf152ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf152ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf161ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf161ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf133ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf133ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf191ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf191ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf142ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf142ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf159ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf159ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf141ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf141ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf130ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf130ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf143ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf143ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf140ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf140ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf211ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_ftsf211ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_ftsf332ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf332ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_ftsf135ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf135ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf138ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf138ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf176ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf176ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf170ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf170ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf184ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf184ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf174ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf174ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf171ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf171ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf182ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf182ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf173ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf173ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf169ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf169ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf181ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf181ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf172ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf172ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf168ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf168ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf180ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf180ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf139ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf139ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf151ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf151ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf137ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf137ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf136ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf136ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf145ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf145ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf134ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf134ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf144ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf144ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf178ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf178ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf188ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf188ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf183ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf183ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf186ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf186ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf179ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf179ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf187ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf187ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf177ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf177ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf185ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf185ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf45ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf45ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf44ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf44ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf48ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf48ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf47ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf47ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf49ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf49ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf50ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf50ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf52ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf52ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf51ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf51ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf38ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf38ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf54ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf54ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf40ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf40ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf39ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf39ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf46ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf46ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf42ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf42ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf43ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf43ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf41ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf41ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf55ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf55ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf53ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf53ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf58ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf58ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf56ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf56ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf72ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf72ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 26) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf71ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf71ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 26) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf57ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf57ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf89ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_ftsf89ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_ftsf334ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf334ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_ftsf195ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf195ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf207ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf207ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf336ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; -} - -static void -Field_ftsf336ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); -} - -static unsigned -Field_ftsf199ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf199ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf210ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} - -static void -Field_ftsf210ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf337ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf337ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_ftsf194ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf194ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf197ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf197ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf196ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf196ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf198ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf198ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf200ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf200ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf203ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf203ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf201ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf201ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf202ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf202ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf204ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf204ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf206ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf206ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf205ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf205ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf209ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf209ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf127ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf127ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf129ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf129ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf128ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf128ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf146ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf146ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf149ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf149ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf148ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf148ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf150ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf150ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf162ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf162ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf165ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf165ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf164ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf164ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf166ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf166ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf189ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf189ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf192ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf192ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf190ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf190ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf193ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf193ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_combined1b97e84f_fld49_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld49_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_combined1b97e84f_fld54_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld54_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_combined1b97e84f_fld51_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld51_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined1b97e84f_fld23_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld23_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_op0_s3_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - return tie_t; -} - -static void -Field_op0_s3_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_combined1b97e84f_fld17_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld17_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); -} - -static unsigned -Field_combined1b97e84f_fld76_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld76_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2) | (tie_t << 1); -} - -static unsigned -Field_combined1b97e84f_fld73_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld73_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); -} - -static unsigned -Field_combined1b97e84f_fld62_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld62_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld24_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld24_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_combined1b97e84f_fld70_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld70_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_combined1b97e84f_fld58_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld58_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); -} - -static unsigned -Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_op0_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); - return tie_t; -} - -static void -Field_op0_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); -} - -static unsigned -Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - return tie_t; -} - -static void -Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_ftsf293_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_ftsf293_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_ftsf321_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf321_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_ae_s20_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); -} - -static unsigned -Field_ftsf214ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_ftsf214ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf213ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); - return tie_t; -} - -static void -Field_ftsf213ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); -} - -static unsigned -Field_ftsf212ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_ftsf212ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_ftsf281ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_ftsf281ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); - tie_t = (val << 16) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf217_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf217_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_ae_r20_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_ftsf300ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - return tie_t; -} - -static void -Field_ftsf300ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf283ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); - return tie_t; -} - -static void -Field_ftsf283ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 17) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf352ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf352ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf282ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_ftsf282ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); - tie_t = (val << 16) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf288ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); - return tie_t; -} - -static void -Field_ftsf288ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x38) | (tie_t << 3); - tie_t = (val << 21) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf359ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf359ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf286ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); - return tie_t; -} - -static void -Field_ftsf286ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf356ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf356ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf284ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 5) | ((insn[0] << 26) >> 27); - return tie_t; -} - -static void -Field_ftsf284ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x3e) | (tie_t << 1); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf354ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf354ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf295ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_ftsf295ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf358ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf358ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf325ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf325ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf215ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); - return tie_t; -} - -static void -Field_ftsf215ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); -} - -static unsigned -Field_ftsf301ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19); - return tie_t; -} - -static void -Field_ftsf301ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 19) >> 19; - insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf353_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf353_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_ftsf309ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23); - return tie_t; -} - -static void -Field_ftsf309ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0xff800) | (tie_t << 11); -} - -static unsigned -Field_ftsf360ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 21) >> 27); - return tie_t; -} - -static void -Field_ftsf360ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x7c0) | (tie_t << 6); -} - -static unsigned -Field_ftsf294ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_ftsf294ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); - tie_t = (val << 21) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf292ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_ftsf292ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); - tie_t = (val << 21) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf319_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; -} - -static void -Field_ftsf319_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); -} - -static unsigned -Field_ftsf361ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf361ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_ftsf218ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf218ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf220ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf220ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf221ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf221ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf222ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf222ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf228ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf228ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf229ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf229ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf230ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf230ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf232ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf232ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf233ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf233ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf235ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf235ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf239ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf239ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf234ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf234ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf224ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf224ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf225ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf225ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf227ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf227ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf226ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf226ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf241ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf241ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf243ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf243ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf242ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf242ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf244ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf244ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf236ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf236ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf237ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf237ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf238ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf238ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf240ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf240ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf261ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf261ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf296ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf296ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf248ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf248ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf250ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf250ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf269ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf269ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf264ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf264ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf266ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf266ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf267ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf267ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf260ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf260ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf262ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf262ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf263ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf263ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf265ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf265ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf246ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf246ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf247ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf247ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf249ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf249ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf253ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf253ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf257ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf257ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf256ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf256ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf258ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf258ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf259ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf259ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf251ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf251ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf252ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf252ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf254ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf254ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf255ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf255ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf275ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf275ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf277ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf277ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf278ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf278ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf290ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_ftsf290ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_ftsf272ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf272ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf276ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf276ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf273ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf273ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf274ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf274ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf297ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf297ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf298ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf298ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf310ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf310ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf311ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf311ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf270ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf270ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf271ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf271ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ae_r32_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf329ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); - return tie_t; -} - -static void -Field_ftsf329ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); -} - -static unsigned -Field_ftsf362ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf362ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 27) >> 29; - insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); -} - -static unsigned -Field_combined4b12daa6_fld85_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld85_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_combined4b12daa6_fld122_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld122_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x200) | (tie_t << 9); -} - -static unsigned -Field_combined4b12daa6_fld119_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld119_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x400) | (tie_t << 10); -} - -static unsigned -Field_combined4b12daa6_fld97_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); - return tie_t; -} - -static void -Field_combined4b12daa6_fld97_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); -} - -static unsigned -Field_combined4b12daa6_fld124_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld124_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_combined4b12daa6_fld79_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld79_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_combined4b12daa6_fld80_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld80_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); -} - -static unsigned -Field_combined4b12daa6_fld108_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_combined4b12daa6_fld108_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_op0_s4_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); - return tie_t; -} - -static void -Field_op0_s4_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); -} - -static unsigned -Field_combined4b12daa6_fld115_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_combined4b12daa6_fld115_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_ftsf245ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf245ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf268ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf268ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf313ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf313ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf312ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf312ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf231ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf231ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf223ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf223ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf219ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf219ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf216ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf216ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf302ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf302ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 17) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf364ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf364ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_ftsf322ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf322ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf279ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); - return tie_t; -} - -static void -Field_ftsf279ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); - tie_t = (val << 18) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf318ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; -} - -static void -Field_ftsf318ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); - tie_t = (val << 28) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf365ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf365ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_ftsf316ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf316ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf314ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf314ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf315ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf315ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf320ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf320ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf299ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); - return tie_t; -} - -static void -Field_ftsf299ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 22) >> 22; - insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); -} - -static unsigned -Field_ftsf308ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21); - return tie_t; -} - -static void -Field_ftsf308ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 21) >> 21; - insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf366ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf366ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_ftsf306ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_ftsf306ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); - tie_t = (val << 19) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf368ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf368ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); - tie_t = (val << 29) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_ftsf304ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); - return tie_t; -} - -static void -Field_ftsf304ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6) | (tie_t << 1); - tie_t = (val << 18) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf369ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf369ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_ftsf323ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf323ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf328ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf328ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf326ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); - return tie_t; -} - -static void -Field_ftsf326ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc) | (tie_t << 2); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf357_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf357_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); -} - -static unsigned -Field_ftsf303ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf303ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 17) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf324ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf324ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf317ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf317ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld101_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld101_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); -} - -static unsigned -Field_combined1b97e84f_fld88_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld88_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2) | (tie_t << 1); -} - -static unsigned -Field_combined1b97e84f_fld39_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld39_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); -} - -static unsigned -Field_combined1b97e84f_fld115_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld115_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined1b97e84f_fld97_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); - return tie_t; -} - -static void -Field_combined1b97e84f_fld97_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); -} - -static unsigned -Field_combined1b97e84f_fld124_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld124_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld79_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld79_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_combined1b97e84f_fld80_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld80_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); -} - -static unsigned -Field_combined1b97e84f_fld108_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_combined1b97e84f_fld108_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld83_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld83_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_combined1b97e84f_fld93_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld93_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_combined1b97e84f_fld90_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_combined1b97e84f_fld90_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); -} - -static unsigned -Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_bbi_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); - return tie_t; -} - -static void -Field_bbi_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); -} - -static unsigned -Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); - return tie_t; -} - -static void -Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); -} - -static unsigned -Field_imm12_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_imm12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); -} - -static unsigned -Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); - return tie_t; -} - -static void -Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); -} - -static unsigned -Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); - return tie_t; -} - -static void -Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); -} - -static unsigned -Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); - return tie_t; -} - -static void -Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); -} - -static unsigned -Field_offset_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); - return tie_t; -} - -static void -Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); -} - -static unsigned -Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - return tie_t; -} - -static void -Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sae_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27); - return tie_t; -} - -static void -Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12); -} - -static unsigned -Field_sal_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); - return tie_t; -} - -static void -Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); -} - -static unsigned -Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sas_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); - return tie_t; -} - -static void -Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); -} - -static unsigned -Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_mn_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_y_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_x_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_t2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t2_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_t2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_s2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_r2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} - -static unsigned -Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} - -static unsigned -Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} - -static unsigned -Field_t4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_s4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_r4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_t8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_s8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_r8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); - return tie_t; -} - -static void -Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 17) >> 17; - insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); -} - -static unsigned -Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_ae_samt_s_t_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); - return tie_t; -} - -static void -Field_ae_samt_s_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); -} - -static unsigned -Field_ae_samt_s_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ae_samt_s_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -} - -static unsigned -Field_ae_r20_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); -} - -static unsigned -Field_ae_r10_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_ae_s20_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); -} - -static unsigned -Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_ftsf12_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf13_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf13_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_ftsf14_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf14_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); -} - -static void -Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, - uint32 val ATTRIBUTE_UNUSED) -{ - /* Do nothing. */ -} - -static unsigned -Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 4; -} - -static unsigned -Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 8; -} - -static unsigned -Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 12; -} - -static unsigned -Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 1; -} - -static unsigned -Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 2; -} - -static unsigned -Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 3; -} - -static unsigned -Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -enum xtensa_field_id { - FIELD_t, - FIELD_bbi4, - FIELD_bbi, - FIELD_imm12, - FIELD_imm8, - FIELD_s, - FIELD_imm12b, - FIELD_imm16, - FIELD_m, - FIELD_n, - FIELD_offset, - FIELD_op0, - FIELD_op1, - FIELD_op2, - FIELD_r, - FIELD_sa4, - FIELD_sae4, - FIELD_sae, - FIELD_sal, - FIELD_sargt, - FIELD_sas4, - FIELD_sas, - FIELD_sr, - FIELD_st, - FIELD_thi3, - FIELD_imm4, - FIELD_mn, - FIELD_i, - FIELD_imm6lo, - FIELD_imm6hi, - FIELD_imm7lo, - FIELD_imm7hi, - FIELD_z, - FIELD_imm6, - FIELD_imm7, - FIELD_r3, - FIELD_rbit2, - FIELD_rhi, - FIELD_t3, - FIELD_tbit2, - FIELD_tlo, - FIELD_w, - FIELD_y, - FIELD_x, - FIELD_t2, - FIELD_s2, - FIELD_r2, - FIELD_t4, - FIELD_s4, - FIELD_r4, - FIELD_t8, - FIELD_s8, - FIELD_r8, - FIELD_xt_wbr15_imm, - FIELD_xt_wbr18_imm, - FIELD_ae_r3, - FIELD_ae_s_non_samt, - FIELD_ae_s3, - FIELD_ae_r32, - FIELD_ae_samt_s_t, - FIELD_ae_r20, - FIELD_ae_r10, - FIELD_ae_s20, - FIELD_ae_fld_ohba, - FIELD_ae_fld_ohba2, - FIELD_op0_s3, - FIELD_ftsf12, - FIELD_ftsf13, - FIELD_ftsf14, - FIELD_ftsf21ae_slot1, - FIELD_ftsf22ae_slot1, - FIELD_ftsf23ae_slot1, - FIELD_ftsf24ae_slot1, - FIELD_ftsf25ae_slot1, - FIELD_ftsf26ae_slot1, - FIELD_ftsf27ae_slot1, - FIELD_ftsf28ae_slot1, - FIELD_ftsf29ae_slot1, - FIELD_ftsf30ae_slot1, - FIELD_ftsf31ae_slot1, - FIELD_ftsf32ae_slot1, - FIELD_ftsf33ae_slot1, - FIELD_ftsf34ae_slot1, - FIELD_ftsf35ae_slot1, - FIELD_ftsf36ae_slot1, - FIELD_ftsf37ae_slot1, - FIELD_ftsf38ae_slot1, - FIELD_ftsf39ae_slot1, - FIELD_ftsf40ae_slot1, - FIELD_ftsf41ae_slot1, - FIELD_ftsf42ae_slot1, - FIELD_ftsf43ae_slot1, - FIELD_ftsf44ae_slot1, - FIELD_ftsf45ae_slot1, - FIELD_ftsf46ae_slot1, - FIELD_ftsf47ae_slot1, - FIELD_ftsf48ae_slot1, - FIELD_ftsf49ae_slot1, - FIELD_ftsf50ae_slot1, - FIELD_ftsf51ae_slot1, - FIELD_ftsf52ae_slot1, - FIELD_ftsf53ae_slot1, - FIELD_ftsf54ae_slot1, - FIELD_ftsf55ae_slot1, - FIELD_ftsf56ae_slot1, - FIELD_ftsf57ae_slot1, - FIELD_ftsf58ae_slot1, - FIELD_ftsf59ae_slot1, - FIELD_ftsf60ae_slot1, - FIELD_ftsf61ae_slot1, - FIELD_ftsf63ae_slot1, - FIELD_ftsf64ae_slot1, - FIELD_ftsf66ae_slot1, - FIELD_ftsf67ae_slot1, - FIELD_ftsf69ae_slot1, - FIELD_ftsf71ae_slot1, - FIELD_ftsf72ae_slot1, - FIELD_ftsf73ae_slot1, - FIELD_ftsf75ae_slot1, - FIELD_ftsf76ae_slot1, - FIELD_ftsf77ae_slot1, - FIELD_ftsf78ae_slot1, - FIELD_ftsf79ae_slot1, - FIELD_ftsf80ae_slot1, - FIELD_ftsf81ae_slot1, - FIELD_ftsf82ae_slot1, - FIELD_ftsf84ae_slot1, - FIELD_ftsf86ae_slot1, - FIELD_ftsf87ae_slot1, - FIELD_ftsf88ae_slot1, - FIELD_ftsf89ae_slot1, - FIELD_ftsf90ae_slot1, - FIELD_ftsf91ae_slot1, - FIELD_ftsf92ae_slot1, - FIELD_ftsf94ae_slot1, - FIELD_ftsf96ae_slot1, - FIELD_ftsf97ae_slot1, - FIELD_ftsf98ae_slot1, - FIELD_ftsf99ae_slot1, - FIELD_ftsf100ae_slot1, - FIELD_ftsf101ae_slot1, - FIELD_ftsf103ae_slot1, - FIELD_ftsf104ae_slot1, - FIELD_ftsf105ae_slot1, - FIELD_ftsf106ae_slot1, - FIELD_ftsf107ae_slot1, - FIELD_ftsf108ae_slot1, - FIELD_ftsf109ae_slot1, - FIELD_ftsf110ae_slot1, - FIELD_ftsf111ae_slot1, - FIELD_ftsf112ae_slot1, - FIELD_ftsf113ae_slot1, - FIELD_ftsf114ae_slot1, - FIELD_ftsf115ae_slot1, - FIELD_ftsf116ae_slot1, - FIELD_ftsf118ae_slot1, - FIELD_ftsf119ae_slot1, - FIELD_ftsf120ae_slot1, - FIELD_ftsf122ae_slot1, - FIELD_ftsf124ae_slot1, - FIELD_ftsf125ae_slot1, - FIELD_ftsf126ae_slot1, - FIELD_ftsf127ae_slot1, - FIELD_ftsf128ae_slot1, - FIELD_ftsf129ae_slot1, - FIELD_ftsf130ae_slot1, - FIELD_ftsf131ae_slot1, - FIELD_ftsf132ae_slot1, - FIELD_ftsf133ae_slot1, - FIELD_ftsf134ae_slot1, - FIELD_ftsf135ae_slot1, - FIELD_ftsf136ae_slot1, - FIELD_ftsf137ae_slot1, - FIELD_ftsf138ae_slot1, - FIELD_ftsf139ae_slot1, - FIELD_ftsf140ae_slot1, - FIELD_ftsf141ae_slot1, - FIELD_ftsf142ae_slot1, - FIELD_ftsf143ae_slot1, - FIELD_ftsf144ae_slot1, - FIELD_ftsf145ae_slot1, - FIELD_ftsf146ae_slot1, - FIELD_ftsf147ae_slot1, - FIELD_ftsf148ae_slot1, - FIELD_ftsf149ae_slot1, - FIELD_ftsf150ae_slot1, - FIELD_ftsf151ae_slot1, - FIELD_ftsf152ae_slot1, - FIELD_ftsf153ae_slot1, - FIELD_ftsf154ae_slot1, - FIELD_ftsf155ae_slot1, - FIELD_ftsf156ae_slot1, - FIELD_ftsf157ae_slot1, - FIELD_ftsf158ae_slot1, - FIELD_ftsf159ae_slot1, - FIELD_ftsf160ae_slot1, - FIELD_ftsf161ae_slot1, - FIELD_ftsf162ae_slot1, - FIELD_ftsf163ae_slot1, - FIELD_ftsf164ae_slot1, - FIELD_ftsf165ae_slot1, - FIELD_ftsf166ae_slot1, - FIELD_ftsf167ae_slot1, - FIELD_ftsf168ae_slot1, - FIELD_ftsf169ae_slot1, - FIELD_ftsf170ae_slot1, - FIELD_ftsf171ae_slot1, - FIELD_ftsf172ae_slot1, - FIELD_ftsf173ae_slot1, - FIELD_ftsf174ae_slot1, - FIELD_ftsf175ae_slot1, - FIELD_ftsf176ae_slot1, - FIELD_ftsf177ae_slot1, - FIELD_ftsf178ae_slot1, - FIELD_ftsf179ae_slot1, - FIELD_ftsf180ae_slot1, - FIELD_ftsf181ae_slot1, - FIELD_ftsf182ae_slot1, - FIELD_ftsf183ae_slot1, - FIELD_ftsf184ae_slot1, - FIELD_ftsf185ae_slot1, - FIELD_ftsf186ae_slot1, - FIELD_ftsf187ae_slot1, - FIELD_ftsf188ae_slot1, - FIELD_ftsf189ae_slot1, - FIELD_ftsf190ae_slot1, - FIELD_ftsf191ae_slot1, - FIELD_ftsf192ae_slot1, - FIELD_ftsf193ae_slot1, - FIELD_ftsf194ae_slot1, - FIELD_ftsf195ae_slot1, - FIELD_ftsf196ae_slot1, - FIELD_ftsf197ae_slot1, - FIELD_ftsf198ae_slot1, - FIELD_ftsf199ae_slot1, - FIELD_ftsf200ae_slot1, - FIELD_ftsf201ae_slot1, - FIELD_ftsf202ae_slot1, - FIELD_ftsf203ae_slot1, - FIELD_ftsf204ae_slot1, - FIELD_ftsf205ae_slot1, - FIELD_ftsf206ae_slot1, - FIELD_ftsf207ae_slot1, - FIELD_ftsf208, - FIELD_ftsf209ae_slot1, - FIELD_ftsf210ae_slot1, - FIELD_ftsf211ae_slot1, - FIELD_ftsf330ae_slot1, - FIELD_ftsf332ae_slot1, - FIELD_ftsf334ae_slot1, - FIELD_ftsf336ae_slot1, - FIELD_ftsf337ae_slot1, - FIELD_ftsf338, - FIELD_ftsf339ae_slot1, - FIELD_ftsf340, - FIELD_ftsf341ae_slot1, - FIELD_ftsf342ae_slot1, - FIELD_ftsf343ae_slot1, - FIELD_ftsf344ae_slot1, - FIELD_ftsf346ae_slot1, - FIELD_ftsf347, - FIELD_ftsf348ae_slot1, - FIELD_ftsf349ae_slot1, - FIELD_ftsf350ae_slot1, - FIELD_op0_s4, - FIELD_ftsf212ae_slot0, - FIELD_ftsf213ae_slot0, - FIELD_ftsf214ae_slot0, - FIELD_ftsf215ae_slot0, - FIELD_ftsf216ae_slot0, - FIELD_ftsf217, - FIELD_ftsf218ae_slot0, - FIELD_ftsf219ae_slot0, - FIELD_ftsf220ae_slot0, - FIELD_ftsf221ae_slot0, - FIELD_ftsf222ae_slot0, - FIELD_ftsf223ae_slot0, - FIELD_ftsf224ae_slot0, - FIELD_ftsf225ae_slot0, - FIELD_ftsf226ae_slot0, - FIELD_ftsf227ae_slot0, - FIELD_ftsf228ae_slot0, - FIELD_ftsf229ae_slot0, - FIELD_ftsf230ae_slot0, - FIELD_ftsf231ae_slot0, - FIELD_ftsf232ae_slot0, - FIELD_ftsf233ae_slot0, - FIELD_ftsf234ae_slot0, - FIELD_ftsf235ae_slot0, - FIELD_ftsf236ae_slot0, - FIELD_ftsf237ae_slot0, - FIELD_ftsf238ae_slot0, - FIELD_ftsf239ae_slot0, - FIELD_ftsf240ae_slot0, - FIELD_ftsf241ae_slot0, - FIELD_ftsf242ae_slot0, - FIELD_ftsf243ae_slot0, - FIELD_ftsf244ae_slot0, - FIELD_ftsf245ae_slot0, - FIELD_ftsf246ae_slot0, - FIELD_ftsf247ae_slot0, - FIELD_ftsf248ae_slot0, - FIELD_ftsf249ae_slot0, - FIELD_ftsf250ae_slot0, - FIELD_ftsf251ae_slot0, - FIELD_ftsf252ae_slot0, - FIELD_ftsf253ae_slot0, - FIELD_ftsf254ae_slot0, - FIELD_ftsf255ae_slot0, - FIELD_ftsf256ae_slot0, - FIELD_ftsf257ae_slot0, - FIELD_ftsf258ae_slot0, - FIELD_ftsf259ae_slot0, - FIELD_ftsf260ae_slot0, - FIELD_ftsf261ae_slot0, - FIELD_ftsf262ae_slot0, - FIELD_ftsf263ae_slot0, - FIELD_ftsf264ae_slot0, - FIELD_ftsf265ae_slot0, - FIELD_ftsf266ae_slot0, - FIELD_ftsf267ae_slot0, - FIELD_ftsf268ae_slot0, - FIELD_ftsf269ae_slot0, - FIELD_ftsf270ae_slot0, - FIELD_ftsf271ae_slot0, - FIELD_ftsf272ae_slot0, - FIELD_ftsf273ae_slot0, - FIELD_ftsf274ae_slot0, - FIELD_ftsf275ae_slot0, - FIELD_ftsf276ae_slot0, - FIELD_ftsf277ae_slot0, - FIELD_ftsf278ae_slot0, - FIELD_ftsf279ae_slot0, - FIELD_ftsf281ae_slot0, - FIELD_ftsf282ae_slot0, - FIELD_ftsf283ae_slot0, - FIELD_ftsf284ae_slot0, - FIELD_ftsf286ae_slot0, - FIELD_ftsf288ae_slot0, - FIELD_ftsf290ae_slot0, - FIELD_ftsf292ae_slot0, - FIELD_ftsf293, - FIELD_ftsf294ae_slot0, - FIELD_ftsf295ae_slot0, - FIELD_ftsf296ae_slot0, - FIELD_ftsf297ae_slot0, - FIELD_ftsf298ae_slot0, - FIELD_ftsf299ae_slot0, - FIELD_ftsf300ae_slot0, - FIELD_ftsf301ae_slot0, - FIELD_ftsf302ae_slot0, - FIELD_ftsf303ae_slot0, - FIELD_ftsf304ae_slot0, - FIELD_ftsf306ae_slot0, - FIELD_ftsf308ae_slot0, - FIELD_ftsf309ae_slot0, - FIELD_ftsf310ae_slot0, - FIELD_ftsf311ae_slot0, - FIELD_ftsf312ae_slot0, - FIELD_ftsf313ae_slot0, - FIELD_ftsf314ae_slot0, - FIELD_ftsf315ae_slot0, - FIELD_ftsf316ae_slot0, - FIELD_ftsf317ae_slot0, - FIELD_ftsf318ae_slot0, - FIELD_ftsf319, - FIELD_ftsf320ae_slot0, - FIELD_ftsf321, - FIELD_ftsf322ae_slot0, - FIELD_ftsf323ae_slot0, - FIELD_ftsf324ae_slot0, - FIELD_ftsf325ae_slot0, - FIELD_ftsf326ae_slot0, - FIELD_ftsf328ae_slot0, - FIELD_ftsf329ae_slot0, - FIELD_ftsf352ae_slot0, - FIELD_ftsf353, - FIELD_ftsf354ae_slot0, - FIELD_ftsf356ae_slot0, - FIELD_ftsf357, - FIELD_ftsf358ae_slot0, - FIELD_ftsf359ae_slot0, - FIELD_ftsf360ae_slot0, - FIELD_ftsf361ae_slot0, - FIELD_ftsf362ae_slot0, - FIELD_ftsf364ae_slot0, - FIELD_ftsf365ae_slot0, - FIELD_ftsf366ae_slot0, - FIELD_ftsf368ae_slot0, - FIELD_ftsf369ae_slot0, - FIELD_ae_mul32x24fld, - FIELD_combined1b97e84f_fld115, - FIELD_combined1b97e84f_fld97, - FIELD_combined1b97e84f_fld124, - FIELD_combined1b97e84f_fld79, - FIELD_combined1b97e84f_fld80, - FIELD_combined1b97e84f_fld108, - FIELD_combined1b97e84f_fld101, - FIELD_combined1b97e84f_fld88, - FIELD_combined1b97e84f_fld39, - FIELD_op0_s4_s4, - FIELD_combined1b97e84f_fld83, - FIELD_combined1b97e84f_fld90, - FIELD_combined1b97e84f_fld93, - FIELD_combined1b97e84f_fld138ae_slot0, - FIELD_combined1b97e84f_fld130ae_slot0, - FIELD_combined1b97e84f_fld137ae_slot0, - FIELD_combined1b97e84f_fld135ae_slot0, - FIELD_combined1b97e84f_fld136ae_slot0, - FIELD_combined1b97e84f_fld129ae_slot0, - FIELD_combined1b97e84f_fld127ae_slot0, - FIELD_combined1b97e84f_fld128ae_slot0, - FIELD_combined1b97e84f_fld132ae_slot0, - FIELD_combined1b97e84f_fld134ae_slot0, - FIELD_combined4b12daa6_fld122, - FIELD_combined4b12daa6_fld115, - FIELD_combined4b12daa6_fld85, - FIELD_combined4b12daa6_fld119, - FIELD_combined4b12daa6_fld97, - FIELD_combined4b12daa6_fld124, - FIELD_combined4b12daa6_fld79, - FIELD_combined4b12daa6_fld80, - FIELD_combined4b12daa6_fld108, - FIELD_combined1b97e84f_fld54, - FIELD_combined1b97e84f_fld17, - FIELD_combined1b97e84f_fld76, - FIELD_combined1b97e84f_fld73, - FIELD_combined1b97e84f_fld62, - FIELD_combined1b97e84f_fld24, - FIELD_combined1b97e84f_fld70, - FIELD_combined1b97e84f_fld58, - FIELD_combined1b97e84f_fld131ae_slot1, - FIELD_op0_s3_s3, - FIELD_combined1b97e84f_fld49, - FIELD_combined1b97e84f_fld51, - FIELD_combined1b97e84f_fld23, - FIELD__ar0, - FIELD__ar4, - FIELD__ar8, - FIELD__ar12, - FIELD__mr0, - FIELD__mr1, - FIELD__mr2, - FIELD__mr3, - FIELD__bt16, - FIELD__bs16, - FIELD__br16, - FIELD__brall -}; - - -/* Functional units. */ - -static xtensa_funcUnit_internal funcUnits[] = { - { "ae_add32", 1 }, - { "ae_shift32x4", 1 }, - { "ae_shift32x5", 1 }, - { "ae_subshift", 1 } -}; - -enum xtensa_funcUnit_id { - FUNCUNIT_ae_add32, - FUNCUNIT_ae_shift32x4, - FUNCUNIT_ae_shift32x5, - FUNCUNIT_ae_subshift -}; - - -/* Register files. */ - -enum xtensa_regfile_id { - REGFILE_AR, - REGFILE_MR, - REGFILE_BR, - REGFILE_AE_PR, - REGFILE_AE_QR, - REGFILE_BR2, - REGFILE_BR4, - REGFILE_BR8, - REGFILE_BR16 -}; - -static xtensa_regfile_internal regfiles[] = { - { "AR", "a", REGFILE_AR, 32, 32 }, - { "MR", "m", REGFILE_MR, 32, 4 }, - { "BR", "b", REGFILE_BR, 1, 16 }, - { "AE_PR", "aep", REGFILE_AE_PR, 48, 8 }, - { "AE_QR", "aeq", REGFILE_AE_QR, 56, 4 }, - { "BR2", "b", REGFILE_BR, 2, 8 }, - { "BR4", "b", REGFILE_BR, 4, 4 }, - { "BR8", "b", REGFILE_BR, 8, 2 }, - { "BR16", "b", REGFILE_BR, 16, 1 } -}; - - -/* Interfaces. */ - -static xtensa_interface_internal interfaces[] = { - -}; - - -/* Constant tables. */ - -/* constant table ai4c */ -static const unsigned CONST_TBL_ai4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0x9, - 0xa, - 0xb, - 0xc, - 0xd, - 0xe, - 0xf, - 0 -}; - -/* constant table b4c */ -static const unsigned CONST_TBL_b4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - -/* constant table b4cu */ -static const unsigned CONST_TBL_b4cu_0[] = { - 0x8000, - 0x10000, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - - -/* Instruction operands. */ - -static int -Operand_soffsetx4_decode (uint32 *valp) -{ - unsigned soffsetx4_0; - unsigned offset_0; - offset_0 = *valp & 0x3ffff; - soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); - *valp = soffsetx4_0; - return 0; -} - -static int -Operand_soffsetx4_encode (uint32 *valp) -{ - unsigned offset_0; - unsigned soffsetx4_0; - soffsetx4_0 = *valp; - offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; - *valp = offset_0; - return 0; -} - -static int -Operand_soffsetx4_ator (uint32 *valp, uint32 pc) -{ - *valp -= (pc & ~0x3); - return 0; -} - -static int -Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += (pc & ~0x3); - return 0; -} - -static int -Operand_uimm12x8_decode (uint32 *valp) -{ - unsigned uimm12x8_0; - unsigned imm12_0; - imm12_0 = *valp & 0xfff; - uimm12x8_0 = imm12_0 << 3; - *valp = uimm12x8_0; - return 0; -} - -static int -Operand_uimm12x8_encode (uint32 *valp) -{ - unsigned imm12_0; - unsigned uimm12x8_0; - uimm12x8_0 = *valp; - imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); - *valp = imm12_0; - return 0; -} - -static int -Operand_simm4_decode (uint32 *valp) -{ - unsigned simm4_0; - unsigned mn_0; - mn_0 = *valp & 0xf; - simm4_0 = ((int) mn_0 << 28) >> 28; - *valp = simm4_0; - return 0; -} - -static int -Operand_simm4_encode (uint32 *valp) -{ - unsigned mn_0; - unsigned simm4_0; - simm4_0 = *valp; - mn_0 = (simm4_0 & 0xf); - *valp = mn_0; - return 0; -} - -static int -Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_arr_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} - -static int -Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ars_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} - -static int -Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_art_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} - -static int -Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar0_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x1f) != 0; - return error; -} - -static int -Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar4_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x1f) != 0; - return error; -} - -static int -Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar8_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x1f) != 0; - return error; -} - -static int -Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar12_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x1f) != 0; - return error; -} - -static int -Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ars_entry_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x1f) != 0; - return error; -} - -static int -Operand_immrx4_decode (uint32 *valp) -{ - unsigned immrx4_0; - unsigned r_0; - r_0 = *valp & 0xf; - immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; - *valp = immrx4_0; - return 0; -} - -static int -Operand_immrx4_encode (uint32 *valp) -{ - unsigned r_0; - unsigned immrx4_0; - immrx4_0 = *valp; - r_0 = ((immrx4_0 >> 2) & 0xf); - *valp = r_0; - return 0; -} - -static int -Operand_lsi4x4_decode (uint32 *valp) -{ - unsigned lsi4x4_0; - unsigned r_0; - r_0 = *valp & 0xf; - lsi4x4_0 = r_0 << 2; - *valp = lsi4x4_0; - return 0; -} - -static int -Operand_lsi4x4_encode (uint32 *valp) -{ - unsigned r_0; - unsigned lsi4x4_0; - lsi4x4_0 = *valp; - r_0 = ((lsi4x4_0 >> 2) & 0xf); - *valp = r_0; - return 0; -} - -static int -Operand_simm7_decode (uint32 *valp) -{ - unsigned simm7_0; - unsigned imm7_0; - imm7_0 = *valp & 0x7f; - simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; - *valp = simm7_0; - return 0; -} - -static int -Operand_simm7_encode (uint32 *valp) -{ - unsigned imm7_0; - unsigned simm7_0; - simm7_0 = *valp; - imm7_0 = (simm7_0 & 0x7f); - *valp = imm7_0; - return 0; -} - -static int -Operand_uimm6_decode (uint32 *valp) -{ - unsigned uimm6_0; - unsigned imm6_0; - imm6_0 = *valp & 0x3f; - uimm6_0 = 0x4 + (((0) << 6) | imm6_0); - *valp = uimm6_0; - return 0; -} - -static int -Operand_uimm6_encode (uint32 *valp) -{ - unsigned imm6_0; - unsigned uimm6_0; - uimm6_0 = *valp; - imm6_0 = (uimm6_0 - 0x4) & 0x3f; - *valp = imm6_0; - return 0; -} - -static int -Operand_uimm6_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_uimm6_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ai4const_decode (uint32 *valp) -{ - unsigned ai4const_0; - unsigned t_0; - t_0 = *valp & 0xf; - ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; - *valp = ai4const_0; - return 0; -} - -static int -Operand_ai4const_encode (uint32 *valp) -{ - unsigned t_0; - unsigned ai4const_0; - ai4const_0 = *valp; - switch (ai4const_0) - { - case 0xffffffff: t_0 = 0; break; - case 0x1: t_0 = 0x1; break; - case 0x2: t_0 = 0x2; break; - case 0x3: t_0 = 0x3; break; - case 0x4: t_0 = 0x4; break; - case 0x5: t_0 = 0x5; break; - case 0x6: t_0 = 0x6; break; - case 0x7: t_0 = 0x7; break; - case 0x8: t_0 = 0x8; break; - case 0x9: t_0 = 0x9; break; - case 0xa: t_0 = 0xa; break; - case 0xb: t_0 = 0xb; break; - case 0xc: t_0 = 0xc; break; - case 0xd: t_0 = 0xd; break; - case 0xe: t_0 = 0xe; break; - default: t_0 = 0xf; break; - } - *valp = t_0; - return 0; -} - -static int -Operand_b4const_decode (uint32 *valp) -{ - unsigned b4const_0; - unsigned r_0; - r_0 = *valp & 0xf; - b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; - *valp = b4const_0; - return 0; -} - -static int -Operand_b4const_encode (uint32 *valp) -{ - unsigned r_0; - unsigned b4const_0; - b4const_0 = *valp; - switch (b4const_0) - { - case 0xffffffff: r_0 = 0; break; - case 0x1: r_0 = 0x1; break; - case 0x2: r_0 = 0x2; break; - case 0x3: r_0 = 0x3; break; - case 0x4: r_0 = 0x4; break; - case 0x5: r_0 = 0x5; break; - case 0x6: r_0 = 0x6; break; - case 0x7: r_0 = 0x7; break; - case 0x8: r_0 = 0x8; break; - case 0xa: r_0 = 0x9; break; - case 0xc: r_0 = 0xa; break; - case 0x10: r_0 = 0xb; break; - case 0x20: r_0 = 0xc; break; - case 0x40: r_0 = 0xd; break; - case 0x80: r_0 = 0xe; break; - default: r_0 = 0xf; break; - } - *valp = r_0; - return 0; -} - -static int -Operand_b4constu_decode (uint32 *valp) -{ - unsigned b4constu_0; - unsigned r_0; - r_0 = *valp & 0xf; - b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; - *valp = b4constu_0; - return 0; -} - -static int -Operand_b4constu_encode (uint32 *valp) -{ - unsigned r_0; - unsigned b4constu_0; - b4constu_0 = *valp; - switch (b4constu_0) - { - case 0x8000: r_0 = 0; break; - case 0x10000: r_0 = 0x1; break; - case 0x2: r_0 = 0x2; break; - case 0x3: r_0 = 0x3; break; - case 0x4: r_0 = 0x4; break; - case 0x5: r_0 = 0x5; break; - case 0x6: r_0 = 0x6; break; - case 0x7: r_0 = 0x7; break; - case 0x8: r_0 = 0x8; break; - case 0xa: r_0 = 0x9; break; - case 0xc: r_0 = 0xa; break; - case 0x10: r_0 = 0xb; break; - case 0x20: r_0 = 0xc; break; - case 0x40: r_0 = 0xd; break; - case 0x80: r_0 = 0xe; break; - default: r_0 = 0xf; break; - } - *valp = r_0; - return 0; -} - -static int -Operand_uimm8_decode (uint32 *valp) -{ - unsigned uimm8_0; - unsigned imm8_0; - imm8_0 = *valp & 0xff; - uimm8_0 = imm8_0; - *valp = uimm8_0; - return 0; -} - -static int -Operand_uimm8_encode (uint32 *valp) -{ - unsigned imm8_0; - unsigned uimm8_0; - uimm8_0 = *valp; - imm8_0 = (uimm8_0 & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_uimm8x2_decode (uint32 *valp) -{ - unsigned uimm8x2_0; - unsigned imm8_0; - imm8_0 = *valp & 0xff; - uimm8x2_0 = imm8_0 << 1; - *valp = uimm8x2_0; - return 0; -} - -static int -Operand_uimm8x2_encode (uint32 *valp) -{ - unsigned imm8_0; - unsigned uimm8x2_0; - uimm8x2_0 = *valp; - imm8_0 = ((uimm8x2_0 >> 1) & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_uimm8x4_decode (uint32 *valp) -{ - unsigned uimm8x4_0; - unsigned imm8_0; - imm8_0 = *valp & 0xff; - uimm8x4_0 = imm8_0 << 2; - *valp = uimm8x4_0; - return 0; -} - -static int -Operand_uimm8x4_encode (uint32 *valp) -{ - unsigned imm8_0; - unsigned uimm8x4_0; - uimm8x4_0 = *valp; - imm8_0 = ((uimm8x4_0 >> 2) & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_uimm4x16_decode (uint32 *valp) -{ - unsigned uimm4x16_0; - unsigned op2_0; - op2_0 = *valp & 0xf; - uimm4x16_0 = op2_0 << 4; - *valp = uimm4x16_0; - return 0; -} - -static int -Operand_uimm4x16_encode (uint32 *valp) -{ - unsigned op2_0; - unsigned uimm4x16_0; - uimm4x16_0 = *valp; - op2_0 = ((uimm4x16_0 >> 4) & 0xf); - *valp = op2_0; - return 0; -} - -static int -Operand_simm8_decode (uint32 *valp) -{ - unsigned simm8_0; - unsigned imm8_0; - imm8_0 = *valp & 0xff; - simm8_0 = ((int) imm8_0 << 24) >> 24; - *valp = simm8_0; - return 0; -} - -static int -Operand_simm8_encode (uint32 *valp) -{ - unsigned imm8_0; - unsigned simm8_0; - simm8_0 = *valp; - imm8_0 = (simm8_0 & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_simm8x256_decode (uint32 *valp) -{ - unsigned simm8x256_0; - unsigned imm8_0; - imm8_0 = *valp & 0xff; - simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; - *valp = simm8x256_0; - return 0; -} - -static int -Operand_simm8x256_encode (uint32 *valp) -{ - unsigned imm8_0; - unsigned simm8x256_0; - simm8x256_0 = *valp; - imm8_0 = ((simm8x256_0 >> 8) & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_simm12b_decode (uint32 *valp) -{ - unsigned simm12b_0; - unsigned imm12b_0; - imm12b_0 = *valp & 0xfff; - simm12b_0 = ((int) imm12b_0 << 20) >> 20; - *valp = simm12b_0; - return 0; -} - -static int -Operand_simm12b_encode (uint32 *valp) -{ - unsigned imm12b_0; - unsigned simm12b_0; - simm12b_0 = *valp; - imm12b_0 = (simm12b_0 & 0xfff); - *valp = imm12b_0; - return 0; -} - -static int -Operand_msalp32_decode (uint32 *valp) -{ - unsigned msalp32_0; - unsigned sal_0; - sal_0 = *valp & 0x1f; - msalp32_0 = 0x20 - sal_0; - *valp = msalp32_0; - return 0; -} - -static int -Operand_msalp32_encode (uint32 *valp) -{ - unsigned sal_0; - unsigned msalp32_0; - msalp32_0 = *valp; - sal_0 = (0x20 - msalp32_0) & 0x1f; - *valp = sal_0; - return 0; -} - -static int -Operand_op2p1_decode (uint32 *valp) -{ - unsigned op2p1_0; - unsigned op2_0; - op2_0 = *valp & 0xf; - op2p1_0 = op2_0 + 0x1; - *valp = op2p1_0; - return 0; -} - -static int -Operand_op2p1_encode (uint32 *valp) -{ - unsigned op2_0; - unsigned op2p1_0; - op2p1_0 = *valp; - op2_0 = (op2p1_0 - 0x1) & 0xf; - *valp = op2_0; - return 0; -} - -static int -Operand_label8_decode (uint32 *valp) -{ - unsigned label8_0; - unsigned imm8_0; - imm8_0 = *valp & 0xff; - label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); - *valp = label8_0; - return 0; -} - -static int -Operand_label8_encode (uint32 *valp) -{ - unsigned imm8_0; - unsigned label8_0; - label8_0 = *valp; - imm8_0 = (label8_0 - 0x4) & 0xff; - *valp = imm8_0; - return 0; -} - -static int -Operand_label8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ulabel8_decode (uint32 *valp) -{ - unsigned ulabel8_0; - unsigned imm8_0; - imm8_0 = *valp & 0xff; - ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); - *valp = ulabel8_0; - return 0; -} - -static int -Operand_ulabel8_encode (uint32 *valp) -{ - unsigned imm8_0; - unsigned ulabel8_0; - ulabel8_0 = *valp; - imm8_0 = (ulabel8_0 - 0x4) & 0xff; - *valp = imm8_0; - return 0; -} - -static int -Operand_ulabel8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_label12_decode (uint32 *valp) -{ - unsigned label12_0; - unsigned imm12_0; - imm12_0 = *valp & 0xfff; - label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); - *valp = label12_0; - return 0; -} - -static int -Operand_label12_encode (uint32 *valp) -{ - unsigned imm12_0; - unsigned label12_0; - label12_0 = *valp; - imm12_0 = (label12_0 - 0x4) & 0xfff; - *valp = imm12_0; - return 0; -} - -static int -Operand_label12_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label12_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_soffset_decode (uint32 *valp) -{ - unsigned soffset_0; - unsigned offset_0; - offset_0 = *valp & 0x3ffff; - soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); - *valp = soffset_0; - return 0; -} - -static int -Operand_soffset_encode (uint32 *valp) -{ - unsigned offset_0; - unsigned soffset_0; - soffset_0 = *valp; - offset_0 = (soffset_0 - 0x4) & 0x3ffff; - *valp = offset_0; - return 0; -} - -static int -Operand_soffset_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_soffset_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_uimm16x4_decode (uint32 *valp) -{ - unsigned uimm16x4_0; - unsigned imm16_0; - imm16_0 = *valp & 0xffff; - uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; - *valp = uimm16x4_0; - return 0; -} - -static int -Operand_uimm16x4_encode (uint32 *valp) -{ - unsigned imm16_0; - unsigned uimm16x4_0; - uimm16x4_0 = *valp; - imm16_0 = (uimm16x4_0 >> 2) & 0xffff; - *valp = imm16_0; - return 0; -} - -static int -Operand_uimm16x4_ator (uint32 *valp, uint32 pc) -{ - *valp -= ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_bbi_decode (uint32 *valp) -{ - unsigned bbi_0; - bbi_0 = *valp & 0x1f; - bbi_0 = (0 << 5) | bbi_0; - *valp = bbi_0; - return 0; -} - -static int -Operand_bbi_encode (uint32 *valp) -{ - unsigned bbi_0; - bbi_0 = *valp; - bbi_0 = (bbi_0 & 0x1f); - *valp = bbi_0; - return 0; -} - -static int -Operand_sae_decode (uint32 *valp) -{ - unsigned sae_0; - sae_0 = *valp & 0x1f; - sae_0 = (0 << 5) | sae_0; - *valp = sae_0; - return 0; -} - -static int -Operand_sae_encode (uint32 *valp) -{ - unsigned sae_0; - sae_0 = *valp; - sae_0 = (sae_0 & 0x1f); - *valp = sae_0; - return 0; -} - -static int -Operand_sas_decode (uint32 *valp) -{ - unsigned sas_0; - sas_0 = *valp & 0x1f; - sas_0 = (0 << 5) | sas_0; - *valp = sas_0; - return 0; -} - -static int -Operand_sas_encode (uint32 *valp) -{ - unsigned sas_0; - sas_0 = *valp; - sas_0 = (sas_0 & 0x1f); - *valp = sas_0; - return 0; -} - -static int -Operand_sargt_decode (uint32 *valp) -{ - unsigned sargt_0; - sargt_0 = *valp & 0x1f; - sargt_0 = (0 << 5) | sargt_0; - *valp = sargt_0; - return 0; -} - -static int -Operand_sargt_encode (uint32 *valp) -{ - unsigned sargt_0; - sargt_0 = *valp; - sargt_0 = (sargt_0 & 0x1f); - *valp = sargt_0; - return 0; -} - -static int -Operand_s_decode (uint32 *valp) -{ - unsigned s_0; - s_0 = *valp & 0xf; - s_0 = (0 << 4) | s_0; - *valp = s_0; - return 0; -} - -static int -Operand_s_encode (uint32 *valp) -{ - unsigned s_0; - s_0 = *valp; - s_0 = (s_0 & 0xf); - *valp = s_0; - return 0; -} - -static int -Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mx_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_my_decode (uint32 *valp) -{ - *valp += 2; - return 0; -} - -static int -Operand_my_encode (uint32 *valp) -{ - int error; - error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); - *valp = *valp & 1; - return error; -} - -static int -Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mw_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mr0_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mr1_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mr2_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mr3_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_immt_decode (uint32 *valp) -{ - unsigned immt_0; - unsigned t_0; - t_0 = *valp & 0xf; - immt_0 = t_0; - *valp = immt_0; - return 0; -} - -static int -Operand_immt_encode (uint32 *valp) -{ - unsigned t_0; - unsigned immt_0; - immt_0 = *valp; - t_0 = immt_0 & 0xf; - *valp = t_0; - return 0; -} - -static int -Operand_imms_decode (uint32 *valp) -{ - unsigned imms_0; - unsigned s_0; - s_0 = *valp & 0xf; - imms_0 = s_0; - *valp = imms_0; - return 0; -} - -static int -Operand_imms_encode (uint32 *valp) -{ - unsigned s_0; - unsigned imms_0; - imms_0 = *valp; - s_0 = imms_0 & 0xf; - *valp = s_0; - return 0; -} - -static int -Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_bt_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} - -static int -Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_bs_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} - -static int -Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_br_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} - -static int -Operand_bt2_decode (uint32 *valp) -{ - *valp = *valp << 1; - return 0; -} - -static int -Operand_bt2_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x7 << 1)) != 0; - *valp = *valp >> 1; - return error; -} - -static int -Operand_bs2_decode (uint32 *valp) -{ - *valp = *valp << 1; - return 0; -} - -static int -Operand_bs2_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x7 << 1)) != 0; - *valp = *valp >> 1; - return error; -} - -static int -Operand_br2_decode (uint32 *valp) -{ - *valp = *valp << 1; - return 0; -} - -static int -Operand_br2_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x7 << 1)) != 0; - *valp = *valp >> 1; - return error; -} - -static int -Operand_bt4_decode (uint32 *valp) -{ - *valp = *valp << 2; - return 0; -} - -static int -Operand_bt4_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x3 << 2)) != 0; - *valp = *valp >> 2; - return error; -} - -static int -Operand_bs4_decode (uint32 *valp) -{ - *valp = *valp << 2; - return 0; -} - -static int -Operand_bs4_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x3 << 2)) != 0; - *valp = *valp >> 2; - return error; -} - -static int -Operand_br4_decode (uint32 *valp) -{ - *valp = *valp << 2; - return 0; -} - -static int -Operand_br4_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x3 << 2)) != 0; - *valp = *valp >> 2; - return error; -} - -static int -Operand_bt8_decode (uint32 *valp) -{ - *valp = *valp << 3; - return 0; -} - -static int -Operand_bt8_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x1 << 3)) != 0; - *valp = *valp >> 3; - return error; -} - -static int -Operand_bs8_decode (uint32 *valp) -{ - *valp = *valp << 3; - return 0; -} - -static int -Operand_bs8_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x1 << 3)) != 0; - *valp = *valp >> 3; - return error; -} - -static int -Operand_br8_decode (uint32 *valp) -{ - *valp = *valp << 3; - return 0; -} - -static int -Operand_br8_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x1 << 3)) != 0; - *valp = *valp >> 3; - return error; -} - -static int -Operand_bt16_decode (uint32 *valp) -{ - *valp = *valp << 4; - return 0; -} - -static int -Operand_bt16_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0 << 4)) != 0; - *valp = *valp >> 4; - return error; -} - -static int -Operand_bs16_decode (uint32 *valp) -{ - *valp = *valp << 4; - return 0; -} - -static int -Operand_bs16_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0 << 4)) != 0; - *valp = *valp >> 4; - return error; -} - -static int -Operand_br16_decode (uint32 *valp) -{ - *valp = *valp << 4; - return 0; -} - -static int -Operand_br16_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0 << 4)) != 0; - *valp = *valp >> 4; - return error; -} - -static int -Operand_brall_decode (uint32 *valp) -{ - *valp = *valp << 4; - return 0; -} - -static int -Operand_brall_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0 << 4)) != 0; - *valp = *valp >> 4; - return error; -} - -static int -Operand_tp7_decode (uint32 *valp) -{ - unsigned tp7_0; - unsigned t_0; - t_0 = *valp & 0xf; - tp7_0 = t_0 + 0x7; - *valp = tp7_0; - return 0; -} - -static int -Operand_tp7_encode (uint32 *valp) -{ - unsigned t_0; - unsigned tp7_0; - tp7_0 = *valp; - t_0 = (tp7_0 - 0x7) & 0xf; - *valp = t_0; - return 0; -} - -static int -Operand_xt_wbr15_label_decode (uint32 *valp) -{ - unsigned xt_wbr15_label_0; - unsigned xt_wbr15_imm_0; - xt_wbr15_imm_0 = *valp & 0x7fff; - xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); - *valp = xt_wbr15_label_0; - return 0; -} - -static int -Operand_xt_wbr15_label_encode (uint32 *valp) -{ - unsigned xt_wbr15_imm_0; - unsigned xt_wbr15_label_0; - xt_wbr15_label_0 = *valp; - xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; - *valp = xt_wbr15_imm_0; - return 0; -} - -static int -Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_xt_wbr18_label_decode (uint32 *valp) -{ - unsigned xt_wbr18_label_0; - unsigned xt_wbr18_imm_0; - xt_wbr18_imm_0 = *valp & 0x3ffff; - xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); - *valp = xt_wbr18_label_0; - return 0; -} - -static int -Operand_xt_wbr18_label_encode (uint32 *valp) -{ - unsigned xt_wbr18_imm_0; - unsigned xt_wbr18_label_0; - xt_wbr18_label_0 = *valp; - xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; - *valp = xt_wbr18_imm_0; - return 0; -} - -static int -Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ae_samt32_decode (uint32 *valp) -{ - unsigned ae_samt32_0; - unsigned ftsf14_0; - ftsf14_0 = *valp & 0x1f; - ae_samt32_0 = (0 << 5) | ftsf14_0; - *valp = ae_samt32_0; - return 0; -} - -static int -Operand_ae_samt32_encode (uint32 *valp) -{ - unsigned ftsf14_0; - unsigned ae_samt32_0; - ae_samt32_0 = *valp; - ftsf14_0 = (ae_samt32_0 & 0x1f); - *valp = ftsf14_0; - return 0; -} - -static int -Operand_pr0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_pr0_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x7) != 0; - return error; -} - -static int -Operand_qr0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_qr0_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_mac_qr0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mac_qr0_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_ae_lsimm16_decode (uint32 *valp) -{ - unsigned ae_lsimm16_0; - unsigned t_0; - t_0 = *valp & 0xf; - ae_lsimm16_0 = (((int) t_0 << 28) >> 28) << 1; - *valp = ae_lsimm16_0; - return 0; -} - -static int -Operand_ae_lsimm16_encode (uint32 *valp) -{ - unsigned t_0; - unsigned ae_lsimm16_0; - ae_lsimm16_0 = *valp; - t_0 = ((ae_lsimm16_0 >> 1) & 0xf); - *valp = t_0; - return 0; -} - -static int -Operand_ae_lsimm32_decode (uint32 *valp) -{ - unsigned ae_lsimm32_0; - unsigned t_0; - t_0 = *valp & 0xf; - ae_lsimm32_0 = (((int) t_0 << 28) >> 28) << 2; - *valp = ae_lsimm32_0; - return 0; -} - -static int -Operand_ae_lsimm32_encode (uint32 *valp) -{ - unsigned t_0; - unsigned ae_lsimm32_0; - ae_lsimm32_0 = *valp; - t_0 = ((ae_lsimm32_0 >> 2) & 0xf); - *valp = t_0; - return 0; -} - -static int -Operand_ae_lsimm64_decode (uint32 *valp) -{ - unsigned ae_lsimm64_0; - unsigned t_0; - t_0 = *valp & 0xf; - ae_lsimm64_0 = (((int) t_0 << 28) >> 28) << 3; - *valp = ae_lsimm64_0; - return 0; -} - -static int -Operand_ae_lsimm64_encode (uint32 *valp) -{ - unsigned t_0; - unsigned ae_lsimm64_0; - ae_lsimm64_0 = *valp; - t_0 = ((ae_lsimm64_0 >> 3) & 0xf); - *valp = t_0; - return 0; -} - -static int -Operand_ae_samt64_decode (uint32 *valp) -{ - unsigned ae_samt64_0; - unsigned ae_samt_s_t_0; - ae_samt_s_t_0 = *valp & 0x3f; - ae_samt64_0 = (0 << 6) | ae_samt_s_t_0; - *valp = ae_samt64_0; - return 0; -} - -static int -Operand_ae_samt64_encode (uint32 *valp) -{ - unsigned ae_samt_s_t_0; - unsigned ae_samt64_0; - ae_samt64_0 = *valp; - ae_samt_s_t_0 = (ae_samt64_0 & 0x3f); - *valp = ae_samt_s_t_0; - return 0; -} - -static int -Operand_ae_ohba_decode (uint32 *valp) -{ - unsigned ae_ohba_0; - unsigned ae_fld_ohba_0; - ae_fld_ohba_0 = *valp & 0xf; - ae_ohba_0 = (0 << 5) | (((((ae_fld_ohba_0 & 0xf))) == 0) << 4) | ((ae_fld_ohba_0 & 0xf)); - *valp = ae_ohba_0; - return 0; -} - -static int -Operand_ae_ohba_encode (uint32 *valp) -{ - unsigned ae_fld_ohba_0; - unsigned ae_ohba_0; - ae_ohba_0 = *valp; - ae_fld_ohba_0 = (ae_ohba_0 & 0xf); - *valp = ae_fld_ohba_0; - return 0; -} - -static int -Operand_ae_ohba2_decode (uint32 *valp) -{ - unsigned ae_ohba2_0; - unsigned ae_fld_ohba2_0; - ae_fld_ohba2_0 = *valp & 0xf; - ae_ohba2_0 = (0 << 5) | (((((ae_fld_ohba2_0 & 0xf))) == 0) << 4) | ((ae_fld_ohba2_0 & 0xf)); - *valp = ae_ohba2_0; - return 0; -} - -static int -Operand_ae_ohba2_encode (uint32 *valp) -{ - unsigned ae_fld_ohba2_0; - unsigned ae_ohba2_0; - ae_ohba2_0 = *valp; - ae_fld_ohba2_0 = (ae_ohba2_0 & 0xf); - *valp = ae_fld_ohba2_0; - return 0; -} - -static int -Operand_pr_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_pr_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x7) != 0; - return error; -} - -static int -Operand_cvt_pr_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_cvt_pr_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x7) != 0; - return error; -} - -static int -Operand_qr0_rw_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_qr0_rw_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_mac_qr0_rw_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mac_qr0_rw_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_qr1_w_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_qr1_w_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_mac_qr1_w_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mac_qr1_w_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_ps_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ps_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x7) != 0; - return error; -} - -static int -Operand_alupppb_ps_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_alupppb_ps_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x7) != 0; - return error; -} - -static xtensa_operand_internal operands[] = { - { "soffsetx4", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_soffsetx4_encode, Operand_soffsetx4_decode, - Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, - { "uimm12x8", FIELD_imm12, -1, 0, - 0, - Operand_uimm12x8_encode, Operand_uimm12x8_decode, - 0, 0 }, - { "simm4", FIELD_mn, -1, 0, - 0, - Operand_simm4_encode, Operand_simm4_decode, - 0, 0 }, - { "arr", FIELD_r, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_arr_encode, Operand_arr_decode, - 0, 0 }, - { "ars", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_ars_encode, Operand_ars_decode, - 0, 0 }, - { "*ars_invisible", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ars_encode, Operand_ars_decode, - 0, 0 }, - { "art", FIELD_t, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_art_encode, Operand_art_decode, - 0, 0 }, - { "ar0", FIELD__ar0, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar0_encode, Operand_ar0_decode, - 0, 0 }, - { "ar4", FIELD__ar4, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar4_encode, Operand_ar4_decode, - 0, 0 }, - { "ar8", FIELD__ar8, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar8_encode, Operand_ar8_decode, - 0, 0 }, - { "ar12", FIELD__ar12, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar12_encode, Operand_ar12_decode, - 0, 0 }, - { "ars_entry", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_ars_entry_encode, Operand_ars_entry_decode, - 0, 0 }, - { "immrx4", FIELD_r, -1, 0, - 0, - Operand_immrx4_encode, Operand_immrx4_decode, - 0, 0 }, - { "lsi4x4", FIELD_r, -1, 0, - 0, - Operand_lsi4x4_encode, Operand_lsi4x4_decode, - 0, 0 }, - { "simm7", FIELD_imm7, -1, 0, - 0, - Operand_simm7_encode, Operand_simm7_decode, - 0, 0 }, - { "uimm6", FIELD_imm6, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_uimm6_encode, Operand_uimm6_decode, - Operand_uimm6_ator, Operand_uimm6_rtoa }, - { "ai4const", FIELD_t, -1, 0, - 0, - Operand_ai4const_encode, Operand_ai4const_decode, - 0, 0 }, - { "b4const", FIELD_r, -1, 0, - 0, - Operand_b4const_encode, Operand_b4const_decode, - 0, 0 }, - { "b4constu", FIELD_r, -1, 0, - 0, - Operand_b4constu_encode, Operand_b4constu_decode, - 0, 0 }, - { "uimm8", FIELD_imm8, -1, 0, - 0, - Operand_uimm8_encode, Operand_uimm8_decode, - 0, 0 }, - { "uimm8x2", FIELD_imm8, -1, 0, - 0, - Operand_uimm8x2_encode, Operand_uimm8x2_decode, - 0, 0 }, - { "uimm8x4", FIELD_imm8, -1, 0, - 0, - Operand_uimm8x4_encode, Operand_uimm8x4_decode, - 0, 0 }, - { "uimm4x16", FIELD_op2, -1, 0, - 0, - Operand_uimm4x16_encode, Operand_uimm4x16_decode, - 0, 0 }, - { "simm8", FIELD_imm8, -1, 0, - 0, - Operand_simm8_encode, Operand_simm8_decode, - 0, 0 }, - { "simm8x256", FIELD_imm8, -1, 0, - 0, - Operand_simm8x256_encode, Operand_simm8x256_decode, - 0, 0 }, - { "simm12b", FIELD_imm12b, -1, 0, - 0, - Operand_simm12b_encode, Operand_simm12b_decode, - 0, 0 }, - { "msalp32", FIELD_sal, -1, 0, - 0, - Operand_msalp32_encode, Operand_msalp32_decode, - 0, 0 }, - { "op2p1", FIELD_op2, -1, 0, - 0, - Operand_op2p1_encode, Operand_op2p1_decode, - 0, 0 }, - { "label8", FIELD_imm8, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_label8_encode, Operand_label8_decode, - Operand_label8_ator, Operand_label8_rtoa }, - { "ulabel8", FIELD_imm8, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_ulabel8_encode, Operand_ulabel8_decode, - Operand_ulabel8_ator, Operand_ulabel8_rtoa }, - { "label12", FIELD_imm12, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_label12_encode, Operand_label12_decode, - Operand_label12_ator, Operand_label12_rtoa }, - { "soffset", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_soffset_encode, Operand_soffset_decode, - Operand_soffset_ator, Operand_soffset_rtoa }, - { "uimm16x4", FIELD_imm16, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_uimm16x4_encode, Operand_uimm16x4_decode, - Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, - { "bbi", FIELD_bbi, -1, 0, - 0, - Operand_bbi_encode, Operand_bbi_decode, - 0, 0 }, - { "sae", FIELD_sae, -1, 0, - 0, - Operand_sae_encode, Operand_sae_decode, - 0, 0 }, - { "sas", FIELD_sas, -1, 0, - 0, - Operand_sas_encode, Operand_sas_decode, - 0, 0 }, - { "sargt", FIELD_sargt, -1, 0, - 0, - Operand_sargt_encode, Operand_sargt_decode, - 0, 0 }, - { "s", FIELD_s, -1, 0, - 0, - Operand_s_encode, Operand_s_decode, - 0, 0 }, - { "mx", FIELD_x, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, - Operand_mx_encode, Operand_mx_decode, - 0, 0 }, - { "my", FIELD_y, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, - Operand_my_encode, Operand_my_decode, - 0, 0 }, - { "mw", FIELD_w, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_mw_encode, Operand_mw_decode, - 0, 0 }, - { "mr0", FIELD__mr0, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr0_encode, Operand_mr0_decode, - 0, 0 }, - { "mr1", FIELD__mr1, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr1_encode, Operand_mr1_decode, - 0, 0 }, - { "mr2", FIELD__mr2, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr2_encode, Operand_mr2_decode, - 0, 0 }, - { "mr3", FIELD__mr3, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr3_encode, Operand_mr3_decode, - 0, 0 }, - { "immt", FIELD_t, -1, 0, - 0, - Operand_immt_encode, Operand_immt_decode, - 0, 0 }, - { "imms", FIELD_s, -1, 0, - 0, - Operand_imms_encode, Operand_imms_decode, - 0, 0 }, - { "bt", FIELD_t, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_bt_encode, Operand_bt_decode, - 0, 0 }, - { "bs", FIELD_s, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_bs_encode, Operand_bs_decode, - 0, 0 }, - { "br", FIELD_r, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_br_encode, Operand_br_decode, - 0, 0 }, - { "bt2", FIELD_t2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - Operand_bt2_encode, Operand_bt2_decode, - 0, 0 }, - { "bs2", FIELD_s2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - Operand_bs2_encode, Operand_bs2_decode, - 0, 0 }, - { "br2", FIELD_r2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - Operand_br2_encode, Operand_br2_decode, - 0, 0 }, - { "bt4", FIELD_t4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - Operand_bt4_encode, Operand_bt4_decode, - 0, 0 }, - { "bs4", FIELD_s4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - Operand_bs4_encode, Operand_bs4_decode, - 0, 0 }, - { "br4", FIELD_r4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - Operand_br4_encode, Operand_br4_decode, - 0, 0 }, - { "bt8", FIELD_t8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - Operand_bt8_encode, Operand_bt8_decode, - 0, 0 }, - { "bs8", FIELD_s8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - Operand_bs8_encode, Operand_bs8_decode, - 0, 0 }, - { "br8", FIELD_r8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - Operand_br8_encode, Operand_br8_decode, - 0, 0 }, - { "bt16", FIELD__bt16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - Operand_bt16_encode, Operand_bt16_decode, - 0, 0 }, - { "bs16", FIELD__bs16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - Operand_bs16_encode, Operand_bs16_decode, - 0, 0 }, - { "br16", FIELD__br16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - Operand_br16_encode, Operand_br16_decode, - 0, 0 }, - { "brall", FIELD__brall, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_brall_encode, Operand_brall_decode, - 0, 0 }, - { "tp7", FIELD_t, -1, 0, - 0, - Operand_tp7_encode, Operand_tp7_decode, - 0, 0 }, - { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, - Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, - { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, - Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, - { "ae_samt32", FIELD_ftsf14, -1, 0, - 0, - Operand_ae_samt32_encode, Operand_ae_samt32_decode, - 0, 0 }, - { "pr0", FIELD_ftsf12, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_pr0_encode, Operand_pr0_decode, - 0, 0 }, - { "qr0", FIELD_ftsf13, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_qr0_encode, Operand_qr0_decode, - 0, 0 }, - { "mac_qr0", FIELD_ftsf13, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_mac_qr0_encode, Operand_mac_qr0_decode, - 0, 0 }, - { "ae_lsimm16", FIELD_t, -1, 0, - 0, - Operand_ae_lsimm16_encode, Operand_ae_lsimm16_decode, - 0, 0 }, - { "ae_lsimm32", FIELD_t, -1, 0, - 0, - Operand_ae_lsimm32_encode, Operand_ae_lsimm32_decode, - 0, 0 }, - { "ae_lsimm64", FIELD_t, -1, 0, - 0, - Operand_ae_lsimm64_encode, Operand_ae_lsimm64_decode, - 0, 0 }, - { "ae_samt64", FIELD_ae_samt_s_t, -1, 0, - 0, - Operand_ae_samt64_encode, Operand_ae_samt64_decode, - 0, 0 }, - { "ae_ohba", FIELD_ae_fld_ohba, -1, 0, - 0, - Operand_ae_ohba_encode, Operand_ae_ohba_decode, - 0, 0 }, - { "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0, - 0, - Operand_ae_ohba2_encode, Operand_ae_ohba2_decode, - 0, 0 }, - { "pr", FIELD_ae_r20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_pr_encode, Operand_pr_decode, - 0, 0 }, - { "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_cvt_pr_encode, Operand_cvt_pr_decode, - 0, 0 }, - { "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_qr0_rw_encode, Operand_qr0_rw_decode, - 0, 0 }, - { "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_mac_qr0_rw_encode, Operand_mac_qr0_rw_decode, - 0, 0 }, - { "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_qr1_w_encode, Operand_qr1_w_decode, - 0, 0 }, - { "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_mac_qr1_w_encode, Operand_mac_qr1_w_decode, - 0, 0 }, - { "ps", FIELD_ae_s20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_ps_encode, Operand_ps_decode, - 0, 0 }, - { "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_alupppb_ps_encode, Operand_alupppb_ps_decode, - 0, 0 }, - { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, - { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, - { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, - { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, - { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, - { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, - { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, - { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, - { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, - { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, - { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, - { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, - { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, - { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, - { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, - { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, - { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, - { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, - { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, - { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, - { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, - { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, - { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 }, - { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 }, - { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 }, - { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 }, - { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 }, - { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 }, - { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 }, - { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 }, - { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 }, - { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, - { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, - { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, - { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, - { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, - { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, - { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, - { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, - { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r3", FIELD_ae_r3, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s_non_samt", FIELD_ae_s_non_samt, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s3", FIELD_ae_s3, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r32", FIELD_ae_r32, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_samt_s_t", FIELD_ae_samt_s_t, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf14", FIELD_ftsf14, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf21ae_slot1", FIELD_ftsf21ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf22ae_slot1", FIELD_ftsf22ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf23ae_slot1", FIELD_ftsf23ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf24ae_slot1", FIELD_ftsf24ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf25ae_slot1", FIELD_ftsf25ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf26ae_slot1", FIELD_ftsf26ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf27ae_slot1", FIELD_ftsf27ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf28ae_slot1", FIELD_ftsf28ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf29ae_slot1", FIELD_ftsf29ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf30ae_slot1", FIELD_ftsf30ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf31ae_slot1", FIELD_ftsf31ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf32ae_slot1", FIELD_ftsf32ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf33ae_slot1", FIELD_ftsf33ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf34ae_slot1", FIELD_ftsf34ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf35ae_slot1", FIELD_ftsf35ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf36ae_slot1", FIELD_ftsf36ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf37ae_slot1", FIELD_ftsf37ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf38ae_slot1", FIELD_ftsf38ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf39ae_slot1", FIELD_ftsf39ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf40ae_slot1", FIELD_ftsf40ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf41ae_slot1", FIELD_ftsf41ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf42ae_slot1", FIELD_ftsf42ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf43ae_slot1", FIELD_ftsf43ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf44ae_slot1", FIELD_ftsf44ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf45ae_slot1", FIELD_ftsf45ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf46ae_slot1", FIELD_ftsf46ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf47ae_slot1", FIELD_ftsf47ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf48ae_slot1", FIELD_ftsf48ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf49ae_slot1", FIELD_ftsf49ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf50ae_slot1", FIELD_ftsf50ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf51ae_slot1", FIELD_ftsf51ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf52ae_slot1", FIELD_ftsf52ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf53ae_slot1", FIELD_ftsf53ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf54ae_slot1", FIELD_ftsf54ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf55ae_slot1", FIELD_ftsf55ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf56ae_slot1", FIELD_ftsf56ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf57ae_slot1", FIELD_ftsf57ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf58ae_slot1", FIELD_ftsf58ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf59ae_slot1", FIELD_ftsf59ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf60ae_slot1", FIELD_ftsf60ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf61ae_slot1", FIELD_ftsf61ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf63ae_slot1", FIELD_ftsf63ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf64ae_slot1", FIELD_ftsf64ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf66ae_slot1", FIELD_ftsf66ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf67ae_slot1", FIELD_ftsf67ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf69ae_slot1", FIELD_ftsf69ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf71ae_slot1", FIELD_ftsf71ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf72ae_slot1", FIELD_ftsf72ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf73ae_slot1", FIELD_ftsf73ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf75ae_slot1", FIELD_ftsf75ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf76ae_slot1", FIELD_ftsf76ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf77ae_slot1", FIELD_ftsf77ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf78ae_slot1", FIELD_ftsf78ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf79ae_slot1", FIELD_ftsf79ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf80ae_slot1", FIELD_ftsf80ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf81ae_slot1", FIELD_ftsf81ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf82ae_slot1", FIELD_ftsf82ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf84ae_slot1", FIELD_ftsf84ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf86ae_slot1", FIELD_ftsf86ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf87ae_slot1", FIELD_ftsf87ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf88ae_slot1", FIELD_ftsf88ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf89ae_slot1", FIELD_ftsf89ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf90ae_slot1", FIELD_ftsf90ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf91ae_slot1", FIELD_ftsf91ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf92ae_slot1", FIELD_ftsf92ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf94ae_slot1", FIELD_ftsf94ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf96ae_slot1", FIELD_ftsf96ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf97ae_slot1", FIELD_ftsf97ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf98ae_slot1", FIELD_ftsf98ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf99ae_slot1", FIELD_ftsf99ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf100ae_slot1", FIELD_ftsf100ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf101ae_slot1", FIELD_ftsf101ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf103ae_slot1", FIELD_ftsf103ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf104ae_slot1", FIELD_ftsf104ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf105ae_slot1", FIELD_ftsf105ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf106ae_slot1", FIELD_ftsf106ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf107ae_slot1", FIELD_ftsf107ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf108ae_slot1", FIELD_ftsf108ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf109ae_slot1", FIELD_ftsf109ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf110ae_slot1", FIELD_ftsf110ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf111ae_slot1", FIELD_ftsf111ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf112ae_slot1", FIELD_ftsf112ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf113ae_slot1", FIELD_ftsf113ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf114ae_slot1", FIELD_ftsf114ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf115ae_slot1", FIELD_ftsf115ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf116ae_slot1", FIELD_ftsf116ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf118ae_slot1", FIELD_ftsf118ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf119ae_slot1", FIELD_ftsf119ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf120ae_slot1", FIELD_ftsf120ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf122ae_slot1", FIELD_ftsf122ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf124ae_slot1", FIELD_ftsf124ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf125ae_slot1", FIELD_ftsf125ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf126ae_slot1", FIELD_ftsf126ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf127ae_slot1", FIELD_ftsf127ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf128ae_slot1", FIELD_ftsf128ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf129ae_slot1", FIELD_ftsf129ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf130ae_slot1", FIELD_ftsf130ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf131ae_slot1", FIELD_ftsf131ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf132ae_slot1", FIELD_ftsf132ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf133ae_slot1", FIELD_ftsf133ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf134ae_slot1", FIELD_ftsf134ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf135ae_slot1", FIELD_ftsf135ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf136ae_slot1", FIELD_ftsf136ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf137ae_slot1", FIELD_ftsf137ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf138ae_slot1", FIELD_ftsf138ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf139ae_slot1", FIELD_ftsf139ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf140ae_slot1", FIELD_ftsf140ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf141ae_slot1", FIELD_ftsf141ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf142ae_slot1", FIELD_ftsf142ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf143ae_slot1", FIELD_ftsf143ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf144ae_slot1", FIELD_ftsf144ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf145ae_slot1", FIELD_ftsf145ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf146ae_slot1", FIELD_ftsf146ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf147ae_slot1", FIELD_ftsf147ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf148ae_slot1", FIELD_ftsf148ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf149ae_slot1", FIELD_ftsf149ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf150ae_slot1", FIELD_ftsf150ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf151ae_slot1", FIELD_ftsf151ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf152ae_slot1", FIELD_ftsf152ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf153ae_slot1", FIELD_ftsf153ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf154ae_slot1", FIELD_ftsf154ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf155ae_slot1", FIELD_ftsf155ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf156ae_slot1", FIELD_ftsf156ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf157ae_slot1", FIELD_ftsf157ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf158ae_slot1", FIELD_ftsf158ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf159ae_slot1", FIELD_ftsf159ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - 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{ "ftsf297ae_slot0", FIELD_ftsf297ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf298ae_slot0", FIELD_ftsf298ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf299ae_slot0", FIELD_ftsf299ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf300ae_slot0", FIELD_ftsf300ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf301ae_slot0", FIELD_ftsf301ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf302ae_slot0", FIELD_ftsf302ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf303ae_slot0", FIELD_ftsf303ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf304ae_slot0", FIELD_ftsf304ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf306ae_slot0", FIELD_ftsf306ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf308ae_slot0", FIELD_ftsf308ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf309ae_slot0", FIELD_ftsf309ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf310ae_slot0", FIELD_ftsf310ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf311ae_slot0", FIELD_ftsf311ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf312ae_slot0", FIELD_ftsf312ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf313ae_slot0", FIELD_ftsf313ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf314ae_slot0", FIELD_ftsf314ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf315ae_slot0", FIELD_ftsf315ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf316ae_slot0", FIELD_ftsf316ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf317ae_slot0", FIELD_ftsf317ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf318ae_slot0", FIELD_ftsf318ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf319", FIELD_ftsf319, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf320ae_slot0", FIELD_ftsf320ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf321", FIELD_ftsf321, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf322ae_slot0", FIELD_ftsf322ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf323ae_slot0", FIELD_ftsf323ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf324ae_slot0", FIELD_ftsf324ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf325ae_slot0", FIELD_ftsf325ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf326ae_slot0", FIELD_ftsf326ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf328ae_slot0", FIELD_ftsf328ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf329ae_slot0", FIELD_ftsf329ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf352ae_slot0", FIELD_ftsf352ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf353", FIELD_ftsf353, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf354ae_slot0", FIELD_ftsf354ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf356ae_slot0", FIELD_ftsf356ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf357", FIELD_ftsf357, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf358ae_slot0", FIELD_ftsf358ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf359ae_slot0", FIELD_ftsf359ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf360ae_slot0", FIELD_ftsf360ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf361ae_slot0", FIELD_ftsf361ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf362ae_slot0", FIELD_ftsf362ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf364ae_slot0", FIELD_ftsf364ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf365ae_slot0", FIELD_ftsf365ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf366ae_slot0", FIELD_ftsf366ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf368ae_slot0", FIELD_ftsf368ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf369ae_slot0", FIELD_ftsf369ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_mul32x24fld", FIELD_ae_mul32x24fld, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld115", FIELD_combined1b97e84f_fld115, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld97", FIELD_combined1b97e84f_fld97, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld124", FIELD_combined1b97e84f_fld124, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld79", FIELD_combined1b97e84f_fld79, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld80", FIELD_combined1b97e84f_fld80, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld108", FIELD_combined1b97e84f_fld108, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld101", FIELD_combined1b97e84f_fld101, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld88", FIELD_combined1b97e84f_fld88, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld39", FIELD_combined1b97e84f_fld39, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s4_s4", FIELD_op0_s4_s4, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld83", FIELD_combined1b97e84f_fld83, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld90", FIELD_combined1b97e84f_fld90, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld93", FIELD_combined1b97e84f_fld93, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld138ae_slot0", FIELD_combined1b97e84f_fld138ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld130ae_slot0", FIELD_combined1b97e84f_fld130ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld137ae_slot0", FIELD_combined1b97e84f_fld137ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld135ae_slot0", FIELD_combined1b97e84f_fld135ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld136ae_slot0", FIELD_combined1b97e84f_fld136ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld129ae_slot0", FIELD_combined1b97e84f_fld129ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld127ae_slot0", FIELD_combined1b97e84f_fld127ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld128ae_slot0", FIELD_combined1b97e84f_fld128ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld132ae_slot0", FIELD_combined1b97e84f_fld132ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld134ae_slot0", FIELD_combined1b97e84f_fld134ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld122", FIELD_combined4b12daa6_fld122, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld115", FIELD_combined4b12daa6_fld115, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld85", FIELD_combined4b12daa6_fld85, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld119", FIELD_combined4b12daa6_fld119, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld97", FIELD_combined4b12daa6_fld97, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld124", FIELD_combined4b12daa6_fld124, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld79", FIELD_combined4b12daa6_fld79, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld80", FIELD_combined4b12daa6_fld80, -1, 0, 0, 0, 0, 0, 0 }, - { "combined4b12daa6_fld108", FIELD_combined4b12daa6_fld108, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld54", FIELD_combined1b97e84f_fld54, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld17", FIELD_combined1b97e84f_fld17, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld76", FIELD_combined1b97e84f_fld76, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld73", FIELD_combined1b97e84f_fld73, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld62", FIELD_combined1b97e84f_fld62, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld24", FIELD_combined1b97e84f_fld24, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld70", FIELD_combined1b97e84f_fld70, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld58", FIELD_combined1b97e84f_fld58, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld131ae_slot1", FIELD_combined1b97e84f_fld131ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s3_s3", FIELD_op0_s3_s3, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld49", FIELD_combined1b97e84f_fld49, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld51", FIELD_combined1b97e84f_fld51, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1b97e84f_fld23", FIELD_combined1b97e84f_fld23, -1, 0, 0, 0, 0, 0, 0 } -}; - -enum xtensa_operand_id { - OPERAND_soffsetx4, - OPERAND_uimm12x8, - OPERAND_simm4, - OPERAND_arr, - OPERAND_ars, - OPERAND__ars_invisible, - OPERAND_art, - OPERAND_ar0, - OPERAND_ar4, - OPERAND_ar8, - OPERAND_ar12, - OPERAND_ars_entry, - OPERAND_immrx4, - OPERAND_lsi4x4, - OPERAND_simm7, - OPERAND_uimm6, - OPERAND_ai4const, - OPERAND_b4const, - OPERAND_b4constu, - OPERAND_uimm8, - OPERAND_uimm8x2, - OPERAND_uimm8x4, - OPERAND_uimm4x16, - OPERAND_simm8, - OPERAND_simm8x256, - OPERAND_simm12b, - OPERAND_msalp32, - OPERAND_op2p1, - OPERAND_label8, - OPERAND_ulabel8, - OPERAND_label12, - OPERAND_soffset, - OPERAND_uimm16x4, - OPERAND_bbi, - OPERAND_sae, - OPERAND_sas, - OPERAND_sargt, - OPERAND_s, - OPERAND_mx, - OPERAND_my, - OPERAND_mw, - OPERAND_mr0, - OPERAND_mr1, - OPERAND_mr2, - OPERAND_mr3, - OPERAND_immt, - OPERAND_imms, - OPERAND_bt, - OPERAND_bs, - OPERAND_br, - OPERAND_bt2, - OPERAND_bs2, - OPERAND_br2, - OPERAND_bt4, - OPERAND_bs4, - OPERAND_br4, - OPERAND_bt8, - OPERAND_bs8, - OPERAND_br8, - OPERAND_bt16, - OPERAND_bs16, - OPERAND_br16, - OPERAND_brall, - OPERAND_tp7, - OPERAND_xt_wbr15_label, - OPERAND_xt_wbr18_label, - OPERAND_ae_samt32, - OPERAND_pr0, - OPERAND_qr0, - OPERAND_mac_qr0, - OPERAND_ae_lsimm16, - OPERAND_ae_lsimm32, - OPERAND_ae_lsimm64, - OPERAND_ae_samt64, - OPERAND_ae_ohba, - OPERAND_ae_ohba2, - OPERAND_pr, - OPERAND_cvt_pr, - OPERAND_qr0_rw, - OPERAND_mac_qr0_rw, - OPERAND_qr1_w, - OPERAND_mac_qr1_w, - OPERAND_ps, - OPERAND_alupppb_ps, - OPERAND_t, - OPERAND_bbi4, - OPERAND_imm12, - OPERAND_imm8, - OPERAND_imm12b, - OPERAND_imm16, - OPERAND_m, - OPERAND_n, - OPERAND_offset, - OPERAND_op0, - OPERAND_op1, - OPERAND_op2, - OPERAND_r, - OPERAND_sa4, - OPERAND_sae4, - OPERAND_sal, - OPERAND_sas4, - OPERAND_sr, - OPERAND_st, - OPERAND_thi3, - OPERAND_imm4, - OPERAND_mn, - OPERAND_i, - OPERAND_imm6lo, - OPERAND_imm6hi, - OPERAND_imm7lo, - OPERAND_imm7hi, - OPERAND_z, - OPERAND_imm6, - OPERAND_imm7, - OPERAND_r3, - OPERAND_rbit2, - OPERAND_rhi, - OPERAND_t3, - OPERAND_tbit2, - OPERAND_tlo, - OPERAND_w, - OPERAND_y, - OPERAND_x, - OPERAND_t2, - OPERAND_s2, - OPERAND_r2, - OPERAND_t4, - OPERAND_s4, - OPERAND_r4, - OPERAND_t8, - OPERAND_s8, - OPERAND_r8, - OPERAND_xt_wbr15_imm, - OPERAND_xt_wbr18_imm, - OPERAND_ae_r3, - OPERAND_ae_s_non_samt, - OPERAND_ae_s3, - OPERAND_ae_r32, - OPERAND_ae_samt_s_t, - OPERAND_ae_r20, - OPERAND_ae_r10, - OPERAND_ae_s20, - OPERAND_ae_fld_ohba, - OPERAND_ae_fld_ohba2, - OPERAND_op0_s3, - OPERAND_ftsf12, - OPERAND_ftsf13, - OPERAND_ftsf14, - OPERAND_ftsf21ae_slot1, - OPERAND_ftsf22ae_slot1, - OPERAND_ftsf23ae_slot1, - OPERAND_ftsf24ae_slot1, - OPERAND_ftsf25ae_slot1, - OPERAND_ftsf26ae_slot1, - OPERAND_ftsf27ae_slot1, - OPERAND_ftsf28ae_slot1, - OPERAND_ftsf29ae_slot1, - OPERAND_ftsf30ae_slot1, - OPERAND_ftsf31ae_slot1, - OPERAND_ftsf32ae_slot1, - OPERAND_ftsf33ae_slot1, - OPERAND_ftsf34ae_slot1, - OPERAND_ftsf35ae_slot1, - OPERAND_ftsf36ae_slot1, - OPERAND_ftsf37ae_slot1, - OPERAND_ftsf38ae_slot1, - OPERAND_ftsf39ae_slot1, - OPERAND_ftsf40ae_slot1, - OPERAND_ftsf41ae_slot1, - OPERAND_ftsf42ae_slot1, - OPERAND_ftsf43ae_slot1, - OPERAND_ftsf44ae_slot1, - OPERAND_ftsf45ae_slot1, - OPERAND_ftsf46ae_slot1, - OPERAND_ftsf47ae_slot1, - OPERAND_ftsf48ae_slot1, - OPERAND_ftsf49ae_slot1, - OPERAND_ftsf50ae_slot1, - OPERAND_ftsf51ae_slot1, - OPERAND_ftsf52ae_slot1, - OPERAND_ftsf53ae_slot1, - OPERAND_ftsf54ae_slot1, - OPERAND_ftsf55ae_slot1, - OPERAND_ftsf56ae_slot1, - OPERAND_ftsf57ae_slot1, - OPERAND_ftsf58ae_slot1, - OPERAND_ftsf59ae_slot1, - OPERAND_ftsf60ae_slot1, - OPERAND_ftsf61ae_slot1, - OPERAND_ftsf63ae_slot1, - OPERAND_ftsf64ae_slot1, - OPERAND_ftsf66ae_slot1, - OPERAND_ftsf67ae_slot1, - OPERAND_ftsf69ae_slot1, - OPERAND_ftsf71ae_slot1, - OPERAND_ftsf72ae_slot1, - OPERAND_ftsf73ae_slot1, - OPERAND_ftsf75ae_slot1, - OPERAND_ftsf76ae_slot1, - OPERAND_ftsf77ae_slot1, - OPERAND_ftsf78ae_slot1, - OPERAND_ftsf79ae_slot1, - OPERAND_ftsf80ae_slot1, - OPERAND_ftsf81ae_slot1, - OPERAND_ftsf82ae_slot1, - OPERAND_ftsf84ae_slot1, - OPERAND_ftsf86ae_slot1, - OPERAND_ftsf87ae_slot1, - OPERAND_ftsf88ae_slot1, - OPERAND_ftsf89ae_slot1, - OPERAND_ftsf90ae_slot1, - OPERAND_ftsf91ae_slot1, - OPERAND_ftsf92ae_slot1, - OPERAND_ftsf94ae_slot1, - OPERAND_ftsf96ae_slot1, - OPERAND_ftsf97ae_slot1, - OPERAND_ftsf98ae_slot1, - OPERAND_ftsf99ae_slot1, - OPERAND_ftsf100ae_slot1, - OPERAND_ftsf101ae_slot1, - OPERAND_ftsf103ae_slot1, - OPERAND_ftsf104ae_slot1, - OPERAND_ftsf105ae_slot1, - OPERAND_ftsf106ae_slot1, - OPERAND_ftsf107ae_slot1, - OPERAND_ftsf108ae_slot1, - OPERAND_ftsf109ae_slot1, - OPERAND_ftsf110ae_slot1, - OPERAND_ftsf111ae_slot1, - OPERAND_ftsf112ae_slot1, - OPERAND_ftsf113ae_slot1, - OPERAND_ftsf114ae_slot1, - OPERAND_ftsf115ae_slot1, - OPERAND_ftsf116ae_slot1, - OPERAND_ftsf118ae_slot1, - OPERAND_ftsf119ae_slot1, - OPERAND_ftsf120ae_slot1, - OPERAND_ftsf122ae_slot1, - OPERAND_ftsf124ae_slot1, - OPERAND_ftsf125ae_slot1, - OPERAND_ftsf126ae_slot1, - OPERAND_ftsf127ae_slot1, - OPERAND_ftsf128ae_slot1, - OPERAND_ftsf129ae_slot1, - OPERAND_ftsf130ae_slot1, - OPERAND_ftsf131ae_slot1, - OPERAND_ftsf132ae_slot1, - OPERAND_ftsf133ae_slot1, - OPERAND_ftsf134ae_slot1, - OPERAND_ftsf135ae_slot1, - OPERAND_ftsf136ae_slot1, - OPERAND_ftsf137ae_slot1, - OPERAND_ftsf138ae_slot1, - OPERAND_ftsf139ae_slot1, - OPERAND_ftsf140ae_slot1, - OPERAND_ftsf141ae_slot1, - OPERAND_ftsf142ae_slot1, - OPERAND_ftsf143ae_slot1, - OPERAND_ftsf144ae_slot1, - OPERAND_ftsf145ae_slot1, - OPERAND_ftsf146ae_slot1, - OPERAND_ftsf147ae_slot1, - OPERAND_ftsf148ae_slot1, - OPERAND_ftsf149ae_slot1, - OPERAND_ftsf150ae_slot1, - OPERAND_ftsf151ae_slot1, - OPERAND_ftsf152ae_slot1, - OPERAND_ftsf153ae_slot1, - OPERAND_ftsf154ae_slot1, - OPERAND_ftsf155ae_slot1, - OPERAND_ftsf156ae_slot1, - OPERAND_ftsf157ae_slot1, - OPERAND_ftsf158ae_slot1, - OPERAND_ftsf159ae_slot1, - OPERAND_ftsf160ae_slot1, - OPERAND_ftsf161ae_slot1, - OPERAND_ftsf162ae_slot1, - OPERAND_ftsf163ae_slot1, - OPERAND_ftsf164ae_slot1, - OPERAND_ftsf165ae_slot1, - OPERAND_ftsf166ae_slot1, - OPERAND_ftsf167ae_slot1, - OPERAND_ftsf168ae_slot1, - OPERAND_ftsf169ae_slot1, - OPERAND_ftsf170ae_slot1, - OPERAND_ftsf171ae_slot1, - OPERAND_ftsf172ae_slot1, - OPERAND_ftsf173ae_slot1, - OPERAND_ftsf174ae_slot1, - OPERAND_ftsf175ae_slot1, - OPERAND_ftsf176ae_slot1, - OPERAND_ftsf177ae_slot1, - OPERAND_ftsf178ae_slot1, - OPERAND_ftsf179ae_slot1, - OPERAND_ftsf180ae_slot1, - OPERAND_ftsf181ae_slot1, - OPERAND_ftsf182ae_slot1, - OPERAND_ftsf183ae_slot1, - OPERAND_ftsf184ae_slot1, - OPERAND_ftsf185ae_slot1, - OPERAND_ftsf186ae_slot1, - OPERAND_ftsf187ae_slot1, - OPERAND_ftsf188ae_slot1, - OPERAND_ftsf189ae_slot1, - OPERAND_ftsf190ae_slot1, - OPERAND_ftsf191ae_slot1, - OPERAND_ftsf192ae_slot1, - OPERAND_ftsf193ae_slot1, - OPERAND_ftsf194ae_slot1, - OPERAND_ftsf195ae_slot1, - OPERAND_ftsf196ae_slot1, - OPERAND_ftsf197ae_slot1, - OPERAND_ftsf198ae_slot1, - OPERAND_ftsf199ae_slot1, - OPERAND_ftsf200ae_slot1, - OPERAND_ftsf201ae_slot1, - OPERAND_ftsf202ae_slot1, - OPERAND_ftsf203ae_slot1, - OPERAND_ftsf204ae_slot1, - OPERAND_ftsf205ae_slot1, - OPERAND_ftsf206ae_slot1, - OPERAND_ftsf207ae_slot1, - OPERAND_ftsf208, - OPERAND_ftsf209ae_slot1, - OPERAND_ftsf210ae_slot1, - OPERAND_ftsf211ae_slot1, - OPERAND_ftsf330ae_slot1, - OPERAND_ftsf332ae_slot1, - OPERAND_ftsf334ae_slot1, - OPERAND_ftsf336ae_slot1, - OPERAND_ftsf337ae_slot1, - OPERAND_ftsf338, - OPERAND_ftsf339ae_slot1, - OPERAND_ftsf340, - OPERAND_ftsf341ae_slot1, - OPERAND_ftsf342ae_slot1, - OPERAND_ftsf343ae_slot1, - OPERAND_ftsf344ae_slot1, - OPERAND_ftsf346ae_slot1, - OPERAND_ftsf347, - OPERAND_ftsf348ae_slot1, - OPERAND_ftsf349ae_slot1, - OPERAND_ftsf350ae_slot1, - OPERAND_op0_s4, - OPERAND_ftsf212ae_slot0, - OPERAND_ftsf213ae_slot0, - OPERAND_ftsf214ae_slot0, - OPERAND_ftsf215ae_slot0, - OPERAND_ftsf216ae_slot0, - OPERAND_ftsf217, - OPERAND_ftsf218ae_slot0, - OPERAND_ftsf219ae_slot0, - OPERAND_ftsf220ae_slot0, - OPERAND_ftsf221ae_slot0, - OPERAND_ftsf222ae_slot0, - OPERAND_ftsf223ae_slot0, - OPERAND_ftsf224ae_slot0, - OPERAND_ftsf225ae_slot0, - OPERAND_ftsf226ae_slot0, - OPERAND_ftsf227ae_slot0, - OPERAND_ftsf228ae_slot0, - OPERAND_ftsf229ae_slot0, - OPERAND_ftsf230ae_slot0, - OPERAND_ftsf231ae_slot0, - OPERAND_ftsf232ae_slot0, - OPERAND_ftsf233ae_slot0, - OPERAND_ftsf234ae_slot0, - OPERAND_ftsf235ae_slot0, - OPERAND_ftsf236ae_slot0, - OPERAND_ftsf237ae_slot0, - OPERAND_ftsf238ae_slot0, - OPERAND_ftsf239ae_slot0, - OPERAND_ftsf240ae_slot0, - OPERAND_ftsf241ae_slot0, - OPERAND_ftsf242ae_slot0, - OPERAND_ftsf243ae_slot0, - OPERAND_ftsf244ae_slot0, - OPERAND_ftsf245ae_slot0, - OPERAND_ftsf246ae_slot0, - OPERAND_ftsf247ae_slot0, - OPERAND_ftsf248ae_slot0, - OPERAND_ftsf249ae_slot0, - OPERAND_ftsf250ae_slot0, - OPERAND_ftsf251ae_slot0, - OPERAND_ftsf252ae_slot0, - OPERAND_ftsf253ae_slot0, - OPERAND_ftsf254ae_slot0, - OPERAND_ftsf255ae_slot0, - OPERAND_ftsf256ae_slot0, - OPERAND_ftsf257ae_slot0, - OPERAND_ftsf258ae_slot0, - OPERAND_ftsf259ae_slot0, - OPERAND_ftsf260ae_slot0, - OPERAND_ftsf261ae_slot0, - OPERAND_ftsf262ae_slot0, - OPERAND_ftsf263ae_slot0, - OPERAND_ftsf264ae_slot0, - OPERAND_ftsf265ae_slot0, - OPERAND_ftsf266ae_slot0, - OPERAND_ftsf267ae_slot0, - OPERAND_ftsf268ae_slot0, - OPERAND_ftsf269ae_slot0, - OPERAND_ftsf270ae_slot0, - OPERAND_ftsf271ae_slot0, - OPERAND_ftsf272ae_slot0, - OPERAND_ftsf273ae_slot0, - OPERAND_ftsf274ae_slot0, - OPERAND_ftsf275ae_slot0, - OPERAND_ftsf276ae_slot0, - OPERAND_ftsf277ae_slot0, - OPERAND_ftsf278ae_slot0, - OPERAND_ftsf279ae_slot0, - OPERAND_ftsf281ae_slot0, - OPERAND_ftsf282ae_slot0, - OPERAND_ftsf283ae_slot0, - OPERAND_ftsf284ae_slot0, - OPERAND_ftsf286ae_slot0, - OPERAND_ftsf288ae_slot0, - OPERAND_ftsf290ae_slot0, - OPERAND_ftsf292ae_slot0, - OPERAND_ftsf293, - OPERAND_ftsf294ae_slot0, - OPERAND_ftsf295ae_slot0, - OPERAND_ftsf296ae_slot0, - OPERAND_ftsf297ae_slot0, - OPERAND_ftsf298ae_slot0, - OPERAND_ftsf299ae_slot0, - OPERAND_ftsf300ae_slot0, - OPERAND_ftsf301ae_slot0, - OPERAND_ftsf302ae_slot0, - OPERAND_ftsf303ae_slot0, - OPERAND_ftsf304ae_slot0, - OPERAND_ftsf306ae_slot0, - OPERAND_ftsf308ae_slot0, - OPERAND_ftsf309ae_slot0, - OPERAND_ftsf310ae_slot0, - OPERAND_ftsf311ae_slot0, - OPERAND_ftsf312ae_slot0, - OPERAND_ftsf313ae_slot0, - OPERAND_ftsf314ae_slot0, - OPERAND_ftsf315ae_slot0, - OPERAND_ftsf316ae_slot0, - OPERAND_ftsf317ae_slot0, - OPERAND_ftsf318ae_slot0, - OPERAND_ftsf319, - OPERAND_ftsf320ae_slot0, - OPERAND_ftsf321, - OPERAND_ftsf322ae_slot0, - OPERAND_ftsf323ae_slot0, - OPERAND_ftsf324ae_slot0, - OPERAND_ftsf325ae_slot0, - OPERAND_ftsf326ae_slot0, - OPERAND_ftsf328ae_slot0, - OPERAND_ftsf329ae_slot0, - OPERAND_ftsf352ae_slot0, - OPERAND_ftsf353, - OPERAND_ftsf354ae_slot0, - OPERAND_ftsf356ae_slot0, - OPERAND_ftsf357, - OPERAND_ftsf358ae_slot0, - OPERAND_ftsf359ae_slot0, - OPERAND_ftsf360ae_slot0, - OPERAND_ftsf361ae_slot0, - OPERAND_ftsf362ae_slot0, - OPERAND_ftsf364ae_slot0, - OPERAND_ftsf365ae_slot0, - OPERAND_ftsf366ae_slot0, - OPERAND_ftsf368ae_slot0, - OPERAND_ftsf369ae_slot0, - OPERAND_ae_mul32x24fld, - OPERAND_combined1b97e84f_fld115, - OPERAND_combined1b97e84f_fld97, - OPERAND_combined1b97e84f_fld124, - OPERAND_combined1b97e84f_fld79, - OPERAND_combined1b97e84f_fld80, - OPERAND_combined1b97e84f_fld108, - OPERAND_combined1b97e84f_fld101, - OPERAND_combined1b97e84f_fld88, - OPERAND_combined1b97e84f_fld39, - OPERAND_op0_s4_s4, - OPERAND_combined1b97e84f_fld83, - OPERAND_combined1b97e84f_fld90, - OPERAND_combined1b97e84f_fld93, - OPERAND_combined1b97e84f_fld138ae_slot0, - OPERAND_combined1b97e84f_fld130ae_slot0, - OPERAND_combined1b97e84f_fld137ae_slot0, - OPERAND_combined1b97e84f_fld135ae_slot0, - OPERAND_combined1b97e84f_fld136ae_slot0, - OPERAND_combined1b97e84f_fld129ae_slot0, - OPERAND_combined1b97e84f_fld127ae_slot0, - OPERAND_combined1b97e84f_fld128ae_slot0, - OPERAND_combined1b97e84f_fld132ae_slot0, - OPERAND_combined1b97e84f_fld134ae_slot0, - OPERAND_combined4b12daa6_fld122, - OPERAND_combined4b12daa6_fld115, - OPERAND_combined4b12daa6_fld85, - OPERAND_combined4b12daa6_fld119, - OPERAND_combined4b12daa6_fld97, - OPERAND_combined4b12daa6_fld124, - OPERAND_combined4b12daa6_fld79, - OPERAND_combined4b12daa6_fld80, - OPERAND_combined4b12daa6_fld108, - OPERAND_combined1b97e84f_fld54, - OPERAND_combined1b97e84f_fld17, - OPERAND_combined1b97e84f_fld76, - OPERAND_combined1b97e84f_fld73, - OPERAND_combined1b97e84f_fld62, - OPERAND_combined1b97e84f_fld24, - OPERAND_combined1b97e84f_fld70, - OPERAND_combined1b97e84f_fld58, - OPERAND_combined1b97e84f_fld131ae_slot1, - OPERAND_op0_s3_s3, - OPERAND_combined1b97e84f_fld49, - OPERAND_combined1b97e84f_fld51, - OPERAND_combined1b97e84f_fld23 -}; - - -/* Iclass table. */ - -static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { - { { STATE_PSEXCM }, 'o' }, - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { - { { OPERAND_ars_entry }, 's' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm12x8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { - { { STATE_WindowBase }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { - { { OPERAND_simm4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { - { { STATE_EPC1 }, 'i' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSOWB }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ai4const }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_simm7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_threadptr_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_threadptr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8x256 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4const }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_bbi }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4constu }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_label12 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sae }, 'i' }, - { { OPERAND_op2p1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { - { { OPERAND_soffset }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_uimm16x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ulabel8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ulabel8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_simm12b }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { - { { OPERAND_arr }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { - { { OPERAND_sas }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_msalp32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sargt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { - { { STATE_LEND }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { - { { STATE_LEND }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { - { { STATE_LEND }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { - { { STATE_LCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { - { { STATE_SAR }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { - { { STATE_SAR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_243_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'm' }, - { { STATE_PSCALLINC }, 'm' }, - { { STATE_PSOWB }, 'm' }, - { { STATE_PSUM }, 'm' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'i' }, - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_mul16_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_mul32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_mul32h_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { - { { OPERAND_mw }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_mx }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { - { { OPERAND_mw }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_mx }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { - { { OPERAND_mw }, 'o' }, - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPC1 }, 'i' }, - { { STATE_EPC2 }, 'i' }, - { { STATE_EPC3 }, 'i' }, - { { STATE_EPC4 }, 'i' }, - { { STATE_EPC5 }, 'i' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_EPC7 }, 'i' }, - { { STATE_EPS2 }, 'i' }, - { { STATE_EPS3 }, 'i' }, - { { STATE_EPS4 }, 'i' }, - { { STATE_EPS5 }, 'i' }, - { { STATE_EPS6 }, 'i' }, - { { STATE_EPS7 }, 'i' }, - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { - { { STATE_INTERRUPT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { - { { OPERAND_imms }, 'i' }, - { { OPERAND_immt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'i' }, - { { STATE_DBNUM }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'o' }, - { { STATE_DBNUM }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'm' }, - { { STATE_DBNUM }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { - { { STATE_ICOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { - { { STATE_DDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { - { { STATE_InOCDMode }, 'm' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_bs }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_bs4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_bs8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { - { { OPERAND_bs }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { - { { OPERAND_arr }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_brall }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_brall }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_brall }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { - { { STATE_CCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_stateArgs[] = { - { { STATE_PREFCTL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_stateArgs[] = { - { { STATE_PREFCTL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_stateArgs[] = { - { { STATE_PREFCTL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { - { { STATE_CPENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { - { { STATE_CPENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_tp7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_tp7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' }, - { { STATE_XTSYNC }, 'i' }, - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'i' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'o' }, - { { STATE_AE_SAR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = { - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = { - { { STATE_AE_BITHEAD }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_TABLESIZE }, 'i' }, - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = { - { { STATE_AE_BITPTR }, 'o' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_sd_no_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_sd_no_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_sd_no_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_sd_no_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_stateArgs[] = { - { { STATE_AE_SAR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_stateArgs[] = { - { { STATE_AE_BITPTR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_stateArgs[] = { - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_stateArgs[] = { - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_stateArgs[] = { - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_stateArgs[] = { - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_i_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_x_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zerop48_args[] = { - { { OPERAND_ps }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zerop48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp48_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp48_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp16_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp16_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zeroq56_args[] = { - { { OPERAND_qr1_w }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zeroq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtq56_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bs }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfq56_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bs }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_cvt_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_cvt_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_satq48s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_satq48s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncq32_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncq32_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = { - { { OPERAND_alupppb_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = { - { { OPERAND_alupppb_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltp24s_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lep24s_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lep24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqp24_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bt }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bt }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_slliq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_slliq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srliq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srliq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraiq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraiq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltq56s_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_leq56s_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_leq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqq56_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sha32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl32t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl32t_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16t_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16c_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16c_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldsht_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldsht_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lb_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ae_ohba2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbk_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_ohba2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_db_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_db_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_dbi_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_ohba }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_dbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel32t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel32t_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel16t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel16t_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sb_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sb_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbi_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_ae_ohba }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vles16c_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vles16c_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbf_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbf_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_ADDBRBA32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cbegin0_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cbegin0_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cbegin0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cbegin0_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cend0_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cend0_stateArgs[] = { - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cend0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cend0_stateArgs[] = { - { { STATE_AE_CEND0 }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ56_C_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ56_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_iclass_internal iclasses[] = { - { 0, 0 /* xt_iclass_excw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_rfe */, - 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfde */, - 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_syscall */, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call12_args, - 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call8_args, - 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call4_args, - 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx12_args, - 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx8_args, - 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx4_args, - 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_entry_args, - 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movsp_args, - 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rotw_args, - 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_retw_args, - 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfwou */, - 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_l32e_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32e_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowbase_args, - 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowbase_args, - 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowbase_args, - 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowstart_args, - 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowstart_args, - 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowstart_args, - 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_add_n_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addi_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bz6_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill_n */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_loadi4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_mov_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_movi_n_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nopn */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_retn_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_storei4_args, - 0, 0, 0, 0 }, - { 1, Iclass_rur_threadptr_args, - 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, - { 1, Iclass_wur_threadptr_args, - 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_addi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addmi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addsub_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bit_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8b_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8u_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bst8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bsz12_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_callx0_args, - 0, 0, 0, 0 }, - { 4, Iclass_xt_iclass_exti_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jump_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jumpx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16ui_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16si_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_l32r_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l8i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_loop_args, - 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_loopz_args, - 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_movz_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_neg_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nop */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_return_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_simcall */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s16i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s8i_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_sar_args, - 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_sari_args, - 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shifts_args, - 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_shiftst_args, - 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shiftt_args, - 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_slli_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srli_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_memw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_extw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_isync */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_sync */, - 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rsil_args, - 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lend_args, - 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lend_args, - 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lend_args, - 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lcount_args, - 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lcount_args, - 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lcount_args, - 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lbeg_args, - 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lbeg_args, - 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lbeg_args, - 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_sar_args, - 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_sar_args, - 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_sar_args, - 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_configid0_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_configid0_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_configid1_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_243_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ps_args, - 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ps_args, - 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ps_args, - 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc1_args, - 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc1_args, - 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc1_args, - 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave1_args, - 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave1_args, - 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave1_args, - 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc2_args, - 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc2_args, - 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc2_args, - 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave2_args, - 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave2_args, - 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave2_args, - 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc3_args, - 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc3_args, - 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc3_args, - 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave3_args, - 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave3_args, - 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave3_args, - 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc4_args, - 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc4_args, - 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc4_args, - 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave4_args, - 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave4_args, - 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave4_args, - 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc5_args, - 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc5_args, - 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc5_args, - 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave5_args, - 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave5_args, - 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave5_args, - 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc6_args, - 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc6_args, - 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc6_args, - 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave6_args, - 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave6_args, - 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave6_args, - 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc7_args, - 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc7_args, - 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc7_args, - 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave7_args, - 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave7_args, - 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave7_args, - 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps2_args, - 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps2_args, - 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps2_args, - 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps3_args, - 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps3_args, - 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps3_args, - 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps4_args, - 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps4_args, - 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps4_args, - 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps5_args, - 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps5_args, - 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps5_args, - 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps6_args, - 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps6_args, - 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps6_args, - 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps7_args, - 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps7_args, - 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps7_args, - 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excvaddr_args, - 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excvaddr_args, - 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excvaddr_args, - 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_depc_args, - 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_depc_args, - 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_depc_args, - 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_exccause_args, - 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_exccause_args, - 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_exccause_args, - 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_prid_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_vecbase_args, - 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_vecbase_args, - 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_vecbase_args, - 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, - { 3, Iclass_xt_mul16_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_mul32_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_mul32h_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_aa_args, - 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_ad_args, - 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_da_args, - 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_dd_args, - 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_aa_args, - 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_ad_args, - 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_da_args, - 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_dd_args, - 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, - { 4, Iclass_xt_iclass_mac16al_da_args, - 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, - { 4, Iclass_xt_iclass_mac16al_dd_args, - 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_l_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m3_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m3_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m3_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_acclo_args, - 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acclo_args, - 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acclo_args, - 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_acchi_args, - 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acchi_args, - 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acchi_args, - 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfi_args, - 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wait_args, - 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_interrupt_args, - 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intset_args, - 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intclear_args, - 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_intenable_args, - 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intenable_args, - 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_intenable_args, - 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_break_args, - 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_break_n_args, - 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka0_args, - 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka0_args, - 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka0_args, - 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc0_args, - 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc0_args, - 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc0_args, - 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka1_args, - 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka1_args, - 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka1_args, - 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc1_args, - 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc1_args, - 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc1_args, - 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka0_args, - 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka0_args, - 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka0_args, - 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka1_args, - 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka1_args, - 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka1_args, - 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreakenable_args, - 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreakenable_args, - 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreakenable_args, - 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_debugcause_args, - 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_debugcause_args, - 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_debugcause_args, - 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icount_args, - 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icount_args, - 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icount_args, - 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icountlevel_args, - 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icountlevel_args, - 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icountlevel_args, - 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ddr_args, - 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ddr_args, - 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ddr_args, - 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfdo_args, - 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfdd */, - 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_bbool1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbool4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbool8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbranch_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bmove_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_RSR_BR_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_WSR_BR_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_XSR_BR_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccount_args, - 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccount_args, - 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccount_args, - 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare0_args, - 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare0_args, - 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare0_args, - 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare1_args, - 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare1_args, - 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare1_args, - 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare2_args, - 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare2_args, - 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare2_args, - 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_icache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_icache_lock_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_icache_inv_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_licx_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_sicx_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_ind_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_inv_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dpf_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_lock_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_sdct_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_ldct_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_prefctl_args, - 1, Iclass_xt_iclass_rsr_prefctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_prefctl_args, - 1, Iclass_xt_iclass_wsr_prefctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_prefctl_args, - 1, Iclass_xt_iclass_xsr_prefctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_idtlb_args, - 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rdtlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wdtlb_args, - 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_iitlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_ritlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_witlb_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_cpenable_args, - 1, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_cpenable_args, - 1, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_cpenable_args, - 1, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_clamp_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_minmax_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_nsa_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_sx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32ai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32ri_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32c1i_args, - 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_scompare1_args, - 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_scompare1_args, - 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_scompare1_args, - 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_atomctl_args, - 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_atomctl_args, - 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_atomctl_args, - 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rer */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_wer */, - 0, 0, 0, 0 }, - { 1, Iclass_rur_ae_ovf_sar_args, - 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_ovf_sar_args, - 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_bithead_args, - 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_bithead_args, - 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_ts_fts_bu_bp_args, - 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_ts_fts_bu_bp_args, - 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_sd_no_args, - 3, Iclass_rur_ae_sd_no_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_sd_no_args, - 3, Iclass_wur_ae_sd_no_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_overflow_args, - 2, Iclass_ae_iclass_rur_ae_overflow_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_overflow_args, - 2, Iclass_ae_iclass_wur_ae_overflow_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_sar_args, - 2, Iclass_ae_iclass_rur_ae_sar_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_sar_args, - 2, Iclass_ae_iclass_wur_ae_sar_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_bitptr_args, - 2, Iclass_ae_iclass_rur_ae_bitptr_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_bitptr_args, - 2, Iclass_ae_iclass_wur_ae_bitptr_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_bitsused_args, - 2, Iclass_ae_iclass_rur_ae_bitsused_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_bitsused_args, - 2, Iclass_ae_iclass_wur_ae_bitsused_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_tablesize_args, - 2, Iclass_ae_iclass_rur_ae_tablesize_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_tablesize_args, - 2, Iclass_ae_iclass_wur_ae_tablesize_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_first_ts_args, - 2, Iclass_ae_iclass_rur_ae_first_ts_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_first_ts_args, - 2, Iclass_ae_iclass_wur_ae_first_ts_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_nextoffset_args, - 2, Iclass_ae_iclass_rur_ae_nextoffset_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_nextoffset_args, - 2, Iclass_ae_iclass_wur_ae_nextoffset_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_searchdone_args, - 2, Iclass_ae_iclass_rur_ae_searchdone_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_searchdone_args, - 2, Iclass_ae_iclass_wur_ae_searchdone_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_i_args, - 1, Iclass_ae_iclass_lp16f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_iu_args, - 1, Iclass_ae_iclass_lp16f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_x_args, - 1, Iclass_ae_iclass_lp16f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_xu_args, - 1, Iclass_ae_iclass_lp16f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_i_args, - 1, Iclass_ae_iclass_lp24_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_iu_args, - 1, Iclass_ae_iclass_lp24_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_x_args, - 1, Iclass_ae_iclass_lp24_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_xu_args, - 1, Iclass_ae_iclass_lp24_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_i_args, - 1, Iclass_ae_iclass_lp24f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_iu_args, - 1, Iclass_ae_iclass_lp24f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_x_args, - 1, Iclass_ae_iclass_lp24f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_xu_args, - 1, Iclass_ae_iclass_lp24f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_i_args, - 1, Iclass_ae_iclass_lp16x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_iu_args, - 1, Iclass_ae_iclass_lp16x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_x_args, - 1, Iclass_ae_iclass_lp16x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_xu_args, - 1, Iclass_ae_iclass_lp16x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_i_args, - 1, Iclass_ae_iclass_lp24x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_iu_args, - 1, Iclass_ae_iclass_lp24x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_x_args, - 1, Iclass_ae_iclass_lp24x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_xu_args, - 1, Iclass_ae_iclass_lp24x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_i_args, - 1, Iclass_ae_iclass_lp24x2_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_iu_args, - 1, Iclass_ae_iclass_lp24x2_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_x_args, - 1, Iclass_ae_iclass_lp24x2_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_xu_args, - 1, Iclass_ae_iclass_lp24x2_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_i_args, - 1, Iclass_ae_iclass_sp16x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_iu_args, - 1, Iclass_ae_iclass_sp16x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_x_args, - 1, Iclass_ae_iclass_sp16x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_xu_args, - 1, Iclass_ae_iclass_sp16x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_i_args, - 1, Iclass_ae_iclass_sp24x2s_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_iu_args, - 1, Iclass_ae_iclass_sp24x2s_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_x_args, - 1, Iclass_ae_iclass_sp24x2s_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_xu_args, - 1, Iclass_ae_iclass_sp24x2s_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_i_args, - 1, Iclass_ae_iclass_sp24x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_iu_args, - 1, Iclass_ae_iclass_sp24x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_x_args, - 1, Iclass_ae_iclass_sp24x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_xu_args, - 1, Iclass_ae_iclass_sp24x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_i_args, - 1, Iclass_ae_iclass_sp16f_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_iu_args, - 1, Iclass_ae_iclass_sp16f_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_x_args, - 1, Iclass_ae_iclass_sp16f_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_xu_args, - 1, Iclass_ae_iclass_sp16f_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_i_args, - 1, Iclass_ae_iclass_sp24s_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_iu_args, - 1, Iclass_ae_iclass_sp24s_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_x_args, - 1, Iclass_ae_iclass_sp24s_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_xu_args, - 1, Iclass_ae_iclass_sp24s_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_i_args, - 1, Iclass_ae_iclass_sp24f_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_iu_args, - 1, Iclass_ae_iclass_sp24f_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_x_args, - 1, Iclass_ae_iclass_sp24f_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_xu_args, - 1, Iclass_ae_iclass_sp24f_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_i_args, - 1, Iclass_ae_iclass_lq56_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_iu_args, - 1, Iclass_ae_iclass_lq56_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_x_args, - 1, Iclass_ae_iclass_lq56_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_xu_args, - 1, Iclass_ae_iclass_lq56_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_i_args, - 1, Iclass_ae_iclass_lq32f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_iu_args, - 1, Iclass_ae_iclass_lq32f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_x_args, - 1, Iclass_ae_iclass_lq32f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_xu_args, - 1, Iclass_ae_iclass_lq32f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_i_args, - 1, Iclass_ae_iclass_sq56s_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_iu_args, - 1, Iclass_ae_iclass_sq56s_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_x_args, - 1, Iclass_ae_iclass_sq56s_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_xu_args, - 1, Iclass_ae_iclass_sq56s_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_i_args, - 1, Iclass_ae_iclass_sq32f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_iu_args, - 1, Iclass_ae_iclass_sq32f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_x_args, - 1, Iclass_ae_iclass_sq32f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_xu_args, - 1, Iclass_ae_iclass_sq32f_xu_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_zerop48_args, - 1, Iclass_ae_iclass_zerop48_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movp48_args, - 1, Iclass_ae_iclass_movp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_ll_args, - 1, Iclass_ae_iclass_selp24_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_lh_args, - 1, Iclass_ae_iclass_selp24_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_hl_args, - 1, Iclass_ae_iclass_selp24_hl_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_hh_args, - 1, Iclass_ae_iclass_selp24_hh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movtp24x2_args, - 1, Iclass_ae_iclass_movtp24x2_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movfp24x2_args, - 1, Iclass_ae_iclass_movfp24x2_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movtp48_args, - 1, Iclass_ae_iclass_movtp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movfp48_args, - 1, Iclass_ae_iclass_movfp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movpa24x2_args, - 1, Iclass_ae_iclass_movpa24x2_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_truncp24a32x2_args, - 1, Iclass_ae_iclass_truncp24a32x2_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvta32p24_l_args, - 1, Iclass_ae_iclass_cvta32p24_l_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvta32p24_h_args, - 1, Iclass_ae_iclass_cvta32p24_h_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_ll_args, - 1, Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_lh_args, - 1, Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_hl_args, - 1, Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_hh_args, - 1, Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_truncp24q48x2_args, - 1, Iclass_ae_iclass_truncp24q48x2_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_truncp16_args, - 1, Iclass_ae_iclass_truncp16_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp24q48sym_args, - 2, Iclass_ae_iclass_roundsp24q48sym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp24q48asym_args, - 2, Iclass_ae_iclass_roundsp24q48asym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp16q48sym_args, - 2, Iclass_ae_iclass_roundsp16q48sym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp16q48asym_args, - 2, Iclass_ae_iclass_roundsp16q48asym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp16sym_args, - 2, Iclass_ae_iclass_roundsp16sym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp16asym_args, - 2, Iclass_ae_iclass_roundsp16asym_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_zeroq56_args, - 1, Iclass_ae_iclass_zeroq56_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movq56_args, - 1, Iclass_ae_iclass_movq56_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movtq56_args, - 1, Iclass_ae_iclass_movtq56_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movfq56_args, - 1, Iclass_ae_iclass_movfq56_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvtq48a32s_args, - 1, Iclass_ae_iclass_cvtq48a32s_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvtq48p24s_l_args, - 1, Iclass_ae_iclass_cvtq48p24s_l_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvtq48p24s_h_args, - 1, Iclass_ae_iclass_cvtq48p24s_h_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_satq48s_args, - 2, Iclass_ae_iclass_satq48s_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_truncq32_args, - 1, Iclass_ae_iclass_truncq32_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsq32sym_args, - 2, Iclass_ae_iclass_roundsq32sym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsq32asym_args, - 2, Iclass_ae_iclass_roundsq32asym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_trunca32q48_args, - 1, Iclass_ae_iclass_trunca32q48_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movap24s_l_args, - 1, Iclass_ae_iclass_movap24s_l_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movap24s_h_args, - 1, Iclass_ae_iclass_movap24s_h_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_trunca16p24s_l_args, - 1, Iclass_ae_iclass_trunca16p24s_l_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_trunca16p24s_h_args, - 1, Iclass_ae_iclass_trunca16p24s_h_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_addp24_args, - 1, Iclass_ae_iclass_addp24_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_subp24_args, - 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1, Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasfq32sp16u_ll_args, - 1, Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasfq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasfq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasfq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasfq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16s_ll_args, - 1, Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16s_ll_args, - 1, Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16u_ll_args, - 1, Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16u_ll_args, - 1, Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16s_ll_args, - 1, Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16s_ll_args, - 1, Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16u_ll_args, - 1, Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16u_ll_args, - 1, Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzaafp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzaap24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzaafp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzaap24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzasfp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzasp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzasfp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzasp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzsafp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzsap24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzsafp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzsap24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzssfp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzssp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzssfp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzssp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulaafp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulaap24s_hh_ll_args, - 1, Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulaafp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulaap24s_hl_lh_args, - 1, Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulasfp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulasp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulasfp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulasp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulsafp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulsap24s_hh_ll_args, - 1, Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulsafp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulsap24s_hl_lh_args, - 1, Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulssfp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulssp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulssfp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulssp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_sha32_args, - 0, 0, 0, 0 }, - { 3, Iclass_ae_iclass_vldl32t_args, - 5, Iclass_ae_iclass_vldl32t_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_vldl16t_args, - 5, Iclass_ae_iclass_vldl16t_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_vldl16c_args, - 8, Iclass_ae_iclass_vldl16c_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_vldsht_args, - 6, Iclass_ae_iclass_vldsht_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_lb_args, - 3, Iclass_ae_iclass_lb_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_lbi_args, - 3, Iclass_ae_iclass_lbi_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lbk_args, - 3, Iclass_ae_iclass_lbk_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lbki_args, - 3, Iclass_ae_iclass_lbki_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_db_args, - 3, Iclass_ae_iclass_db_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_dbi_args, - 3, Iclass_ae_iclass_dbi_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_vlel32t_args, - 3, Iclass_ae_iclass_vlel32t_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_vlel16t_args, - 3, Iclass_ae_iclass_vlel16t_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_sb_args, - 4, Iclass_ae_iclass_sb_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sbi_args, - 3, Iclass_ae_iclass_sbi_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_vles16c_args, - 5, Iclass_ae_iclass_vles16c_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_sbf_args, - 3, Iclass_ae_iclass_sbf_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SLAASQ56S_args, - 2, Iclass_icls_AE_SLAASQ56S_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_ADDBRBA32_args, - 0, 0, 0, 0 }, - { 3, Iclass_icls_AE_MINABSSP24S_args, - 2, Iclass_icls_AE_MINABSSP24S_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_MAXABSSP24S_args, - 2, Iclass_icls_AE_MAXABSSP24S_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_MINABSSQ56S_args, - 2, Iclass_icls_AE_MINABSSQ56S_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_MAXABSSQ56S_args, - 2, Iclass_icls_AE_MAXABSSQ56S_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_cbegin0_args, - 2, Iclass_rur_ae_cbegin0_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_cbegin0_args, - 2, Iclass_wur_ae_cbegin0_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_cend0_args, - 2, Iclass_rur_ae_cend0_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_cend0_args, - 2, Iclass_wur_ae_cend0_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP24X2_C_args, - 3, Iclass_icls_AE_LP24X2_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP24X2S_C_args, - 3, Iclass_icls_AE_SP24X2S_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP24X2F_C_args, - 3, Iclass_icls_AE_LP24X2F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP24X2F_C_args, - 3, Iclass_icls_AE_SP24X2F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP16X2F_C_args, - 3, Iclass_icls_AE_LP16X2F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP16X2F_C_args, - 3, Iclass_icls_AE_SP16X2F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP24_C_args, - 3, Iclass_icls_AE_LP24_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP24S_L_C_args, - 3, Iclass_icls_AE_SP24S_L_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP24F_C_args, - 3, Iclass_icls_AE_LP24F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP24F_L_C_args, - 3, Iclass_icls_AE_SP24F_L_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP16F_C_args, - 3, Iclass_icls_AE_LP16F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP16F_L_C_args, - 3, Iclass_icls_AE_SP16F_L_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LQ56_C_args, - 3, Iclass_icls_AE_LQ56_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SQ56S_C_args, - 3, Iclass_icls_AE_SQ56S_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LQ32F_C_args, - 3, Iclass_icls_AE_LQ32F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SQ32F_C_args, - 3, Iclass_icls_AE_SQ32F_C_stateArgs, 0, 0 } -}; - -enum xtensa_iclass_id { - ICLASS_xt_iclass_excw, - ICLASS_xt_iclass_rfe, - ICLASS_xt_iclass_rfde, - ICLASS_xt_iclass_syscall, - ICLASS_xt_iclass_call12, - ICLASS_xt_iclass_call8, - ICLASS_xt_iclass_call4, - ICLASS_xt_iclass_callx12, - ICLASS_xt_iclass_callx8, - ICLASS_xt_iclass_callx4, - ICLASS_xt_iclass_entry, - ICLASS_xt_iclass_movsp, - ICLASS_xt_iclass_rotw, - ICLASS_xt_iclass_retw, - ICLASS_xt_iclass_rfwou, - ICLASS_xt_iclass_l32e, - ICLASS_xt_iclass_s32e, - ICLASS_xt_iclass_rsr_windowbase, - ICLASS_xt_iclass_wsr_windowbase, - ICLASS_xt_iclass_xsr_windowbase, - ICLASS_xt_iclass_rsr_windowstart, - ICLASS_xt_iclass_wsr_windowstart, - ICLASS_xt_iclass_xsr_windowstart, - ICLASS_xt_iclass_add_n, - ICLASS_xt_iclass_addi_n, - ICLASS_xt_iclass_bz6, - ICLASS_xt_iclass_ill_n, - ICLASS_xt_iclass_loadi4, - ICLASS_xt_iclass_mov_n, - ICLASS_xt_iclass_movi_n, - ICLASS_xt_iclass_nopn, - ICLASS_xt_iclass_retn, - ICLASS_xt_iclass_storei4, - ICLASS_rur_threadptr, - ICLASS_wur_threadptr, - ICLASS_xt_iclass_addi, - ICLASS_xt_iclass_addmi, - ICLASS_xt_iclass_addsub, - ICLASS_xt_iclass_bit, - ICLASS_xt_iclass_bsi8, - ICLASS_xt_iclass_bsi8b, - ICLASS_xt_iclass_bsi8u, - ICLASS_xt_iclass_bst8, - ICLASS_xt_iclass_bsz12, - ICLASS_xt_iclass_call0, - ICLASS_xt_iclass_callx0, - ICLASS_xt_iclass_exti, - ICLASS_xt_iclass_ill, - ICLASS_xt_iclass_jump, - ICLASS_xt_iclass_jumpx, - ICLASS_xt_iclass_l16ui, - ICLASS_xt_iclass_l16si, - ICLASS_xt_iclass_l32i, - ICLASS_xt_iclass_l32r, - ICLASS_xt_iclass_l8i, - ICLASS_xt_iclass_loop, - ICLASS_xt_iclass_loopz, - ICLASS_xt_iclass_movi, - ICLASS_xt_iclass_movz, - ICLASS_xt_iclass_neg, - ICLASS_xt_iclass_nop, - ICLASS_xt_iclass_return, - ICLASS_xt_iclass_simcall, - ICLASS_xt_iclass_s16i, - ICLASS_xt_iclass_s32i, - ICLASS_xt_iclass_s8i, - ICLASS_xt_iclass_sar, - ICLASS_xt_iclass_sari, - ICLASS_xt_iclass_shifts, - ICLASS_xt_iclass_shiftst, - ICLASS_xt_iclass_shiftt, - ICLASS_xt_iclass_slli, - ICLASS_xt_iclass_srai, - ICLASS_xt_iclass_srli, - ICLASS_xt_iclass_memw, - ICLASS_xt_iclass_extw, - ICLASS_xt_iclass_isync, - ICLASS_xt_iclass_sync, - ICLASS_xt_iclass_rsil, - ICLASS_xt_iclass_rsr_lend, - ICLASS_xt_iclass_wsr_lend, - ICLASS_xt_iclass_xsr_lend, - ICLASS_xt_iclass_rsr_lcount, - ICLASS_xt_iclass_wsr_lcount, - ICLASS_xt_iclass_xsr_lcount, - ICLASS_xt_iclass_rsr_lbeg, - ICLASS_xt_iclass_wsr_lbeg, - ICLASS_xt_iclass_xsr_lbeg, - ICLASS_xt_iclass_rsr_sar, - ICLASS_xt_iclass_wsr_sar, - ICLASS_xt_iclass_xsr_sar, - ICLASS_xt_iclass_rsr_litbase, - ICLASS_xt_iclass_wsr_litbase, - ICLASS_xt_iclass_xsr_litbase, - ICLASS_xt_iclass_rsr_configid0, - ICLASS_xt_iclass_wsr_configid0, - ICLASS_xt_iclass_rsr_configid1, - ICLASS_xt_iclass_rsr_243, - ICLASS_xt_iclass_rsr_ps, - ICLASS_xt_iclass_wsr_ps, - ICLASS_xt_iclass_xsr_ps, - ICLASS_xt_iclass_rsr_epc1, - ICLASS_xt_iclass_wsr_epc1, - ICLASS_xt_iclass_xsr_epc1, - ICLASS_xt_iclass_rsr_excsave1, - ICLASS_xt_iclass_wsr_excsave1, - ICLASS_xt_iclass_xsr_excsave1, - ICLASS_xt_iclass_rsr_epc2, - ICLASS_xt_iclass_wsr_epc2, - ICLASS_xt_iclass_xsr_epc2, - ICLASS_xt_iclass_rsr_excsave2, - ICLASS_xt_iclass_wsr_excsave2, - ICLASS_xt_iclass_xsr_excsave2, - ICLASS_xt_iclass_rsr_epc3, - ICLASS_xt_iclass_wsr_epc3, - ICLASS_xt_iclass_xsr_epc3, - ICLASS_xt_iclass_rsr_excsave3, - ICLASS_xt_iclass_wsr_excsave3, - ICLASS_xt_iclass_xsr_excsave3, - ICLASS_xt_iclass_rsr_epc4, - ICLASS_xt_iclass_wsr_epc4, - ICLASS_xt_iclass_xsr_epc4, - ICLASS_xt_iclass_rsr_excsave4, - ICLASS_xt_iclass_wsr_excsave4, - ICLASS_xt_iclass_xsr_excsave4, - ICLASS_xt_iclass_rsr_epc5, - ICLASS_xt_iclass_wsr_epc5, - ICLASS_xt_iclass_xsr_epc5, - ICLASS_xt_iclass_rsr_excsave5, - ICLASS_xt_iclass_wsr_excsave5, - ICLASS_xt_iclass_xsr_excsave5, - ICLASS_xt_iclass_rsr_epc6, - ICLASS_xt_iclass_wsr_epc6, - ICLASS_xt_iclass_xsr_epc6, - ICLASS_xt_iclass_rsr_excsave6, - ICLASS_xt_iclass_wsr_excsave6, - ICLASS_xt_iclass_xsr_excsave6, - ICLASS_xt_iclass_rsr_epc7, - ICLASS_xt_iclass_wsr_epc7, - ICLASS_xt_iclass_xsr_epc7, - ICLASS_xt_iclass_rsr_excsave7, - ICLASS_xt_iclass_wsr_excsave7, - ICLASS_xt_iclass_xsr_excsave7, - ICLASS_xt_iclass_rsr_eps2, - ICLASS_xt_iclass_wsr_eps2, - ICLASS_xt_iclass_xsr_eps2, - ICLASS_xt_iclass_rsr_eps3, - ICLASS_xt_iclass_wsr_eps3, - ICLASS_xt_iclass_xsr_eps3, - ICLASS_xt_iclass_rsr_eps4, - ICLASS_xt_iclass_wsr_eps4, - ICLASS_xt_iclass_xsr_eps4, - ICLASS_xt_iclass_rsr_eps5, - ICLASS_xt_iclass_wsr_eps5, - ICLASS_xt_iclass_xsr_eps5, - ICLASS_xt_iclass_rsr_eps6, - ICLASS_xt_iclass_wsr_eps6, - ICLASS_xt_iclass_xsr_eps6, - ICLASS_xt_iclass_rsr_eps7, - ICLASS_xt_iclass_wsr_eps7, - ICLASS_xt_iclass_xsr_eps7, - ICLASS_xt_iclass_rsr_excvaddr, - ICLASS_xt_iclass_wsr_excvaddr, - ICLASS_xt_iclass_xsr_excvaddr, - ICLASS_xt_iclass_rsr_depc, - ICLASS_xt_iclass_wsr_depc, - ICLASS_xt_iclass_xsr_depc, - ICLASS_xt_iclass_rsr_exccause, - ICLASS_xt_iclass_wsr_exccause, - ICLASS_xt_iclass_xsr_exccause, - ICLASS_xt_iclass_rsr_prid, - ICLASS_xt_iclass_rsr_vecbase, - ICLASS_xt_iclass_wsr_vecbase, - ICLASS_xt_iclass_xsr_vecbase, - ICLASS_xt_mul16, - ICLASS_xt_mul32, - ICLASS_xt_mul32h, - ICLASS_xt_iclass_mac16_aa, - ICLASS_xt_iclass_mac16_ad, - ICLASS_xt_iclass_mac16_da, - ICLASS_xt_iclass_mac16_dd, - ICLASS_xt_iclass_mac16a_aa, - ICLASS_xt_iclass_mac16a_ad, - ICLASS_xt_iclass_mac16a_da, - ICLASS_xt_iclass_mac16a_dd, - ICLASS_xt_iclass_mac16al_da, - ICLASS_xt_iclass_mac16al_dd, - ICLASS_xt_iclass_mac16_l, - ICLASS_xt_iclass_rsr_m0, - ICLASS_xt_iclass_wsr_m0, - ICLASS_xt_iclass_xsr_m0, - ICLASS_xt_iclass_rsr_m1, - ICLASS_xt_iclass_wsr_m1, - ICLASS_xt_iclass_xsr_m1, - ICLASS_xt_iclass_rsr_m2, - ICLASS_xt_iclass_wsr_m2, - ICLASS_xt_iclass_xsr_m2, - ICLASS_xt_iclass_rsr_m3, - ICLASS_xt_iclass_wsr_m3, - ICLASS_xt_iclass_xsr_m3, - ICLASS_xt_iclass_rsr_acclo, - ICLASS_xt_iclass_wsr_acclo, - ICLASS_xt_iclass_xsr_acclo, - ICLASS_xt_iclass_rsr_acchi, - ICLASS_xt_iclass_wsr_acchi, - ICLASS_xt_iclass_xsr_acchi, - ICLASS_xt_iclass_rfi, - ICLASS_xt_iclass_wait, - ICLASS_xt_iclass_rsr_interrupt, - ICLASS_xt_iclass_wsr_intset, - ICLASS_xt_iclass_wsr_intclear, - ICLASS_xt_iclass_rsr_intenable, - ICLASS_xt_iclass_wsr_intenable, - ICLASS_xt_iclass_xsr_intenable, - ICLASS_xt_iclass_break, - ICLASS_xt_iclass_break_n, - ICLASS_xt_iclass_rsr_dbreaka0, - ICLASS_xt_iclass_wsr_dbreaka0, - ICLASS_xt_iclass_xsr_dbreaka0, - ICLASS_xt_iclass_rsr_dbreakc0, - ICLASS_xt_iclass_wsr_dbreakc0, - ICLASS_xt_iclass_xsr_dbreakc0, - ICLASS_xt_iclass_rsr_dbreaka1, - ICLASS_xt_iclass_wsr_dbreaka1, - ICLASS_xt_iclass_xsr_dbreaka1, - ICLASS_xt_iclass_rsr_dbreakc1, - ICLASS_xt_iclass_wsr_dbreakc1, - ICLASS_xt_iclass_xsr_dbreakc1, - ICLASS_xt_iclass_rsr_ibreaka0, - ICLASS_xt_iclass_wsr_ibreaka0, - ICLASS_xt_iclass_xsr_ibreaka0, - ICLASS_xt_iclass_rsr_ibreaka1, - ICLASS_xt_iclass_wsr_ibreaka1, - ICLASS_xt_iclass_xsr_ibreaka1, - ICLASS_xt_iclass_rsr_ibreakenable, - ICLASS_xt_iclass_wsr_ibreakenable, - ICLASS_xt_iclass_xsr_ibreakenable, - ICLASS_xt_iclass_rsr_debugcause, - ICLASS_xt_iclass_wsr_debugcause, - ICLASS_xt_iclass_xsr_debugcause, - ICLASS_xt_iclass_rsr_icount, - ICLASS_xt_iclass_wsr_icount, - ICLASS_xt_iclass_xsr_icount, - ICLASS_xt_iclass_rsr_icountlevel, - ICLASS_xt_iclass_wsr_icountlevel, - ICLASS_xt_iclass_xsr_icountlevel, - ICLASS_xt_iclass_rsr_ddr, - ICLASS_xt_iclass_wsr_ddr, - ICLASS_xt_iclass_xsr_ddr, - ICLASS_xt_iclass_rfdo, - ICLASS_xt_iclass_rfdd, - ICLASS_xt_iclass_bbool1, - ICLASS_xt_iclass_bbool4, - ICLASS_xt_iclass_bbool8, - ICLASS_xt_iclass_bbranch, - ICLASS_xt_iclass_bmove, - ICLASS_xt_iclass_RSR_BR, - ICLASS_xt_iclass_WSR_BR, - ICLASS_xt_iclass_XSR_BR, - ICLASS_xt_iclass_rsr_ccount, - ICLASS_xt_iclass_wsr_ccount, - ICLASS_xt_iclass_xsr_ccount, - ICLASS_xt_iclass_rsr_ccompare0, - ICLASS_xt_iclass_wsr_ccompare0, - ICLASS_xt_iclass_xsr_ccompare0, - ICLASS_xt_iclass_rsr_ccompare1, - ICLASS_xt_iclass_wsr_ccompare1, - ICLASS_xt_iclass_xsr_ccompare1, - ICLASS_xt_iclass_rsr_ccompare2, - ICLASS_xt_iclass_wsr_ccompare2, - ICLASS_xt_iclass_xsr_ccompare2, - ICLASS_xt_iclass_icache, - ICLASS_xt_iclass_icache_lock, - ICLASS_xt_iclass_icache_inv, - ICLASS_xt_iclass_licx, - ICLASS_xt_iclass_sicx, - ICLASS_xt_iclass_dcache, - ICLASS_xt_iclass_dcache_ind, - ICLASS_xt_iclass_dcache_inv, - ICLASS_xt_iclass_dpf, - ICLASS_xt_iclass_dcache_lock, - ICLASS_xt_iclass_sdct, - ICLASS_xt_iclass_ldct, - ICLASS_xt_iclass_rsr_prefctl, - ICLASS_xt_iclass_wsr_prefctl, - ICLASS_xt_iclass_xsr_prefctl, - ICLASS_xt_iclass_idtlb, - ICLASS_xt_iclass_rdtlb, - ICLASS_xt_iclass_wdtlb, - ICLASS_xt_iclass_iitlb, - ICLASS_xt_iclass_ritlb, - ICLASS_xt_iclass_witlb, - ICLASS_xt_iclass_rsr_cpenable, - ICLASS_xt_iclass_wsr_cpenable, - ICLASS_xt_iclass_xsr_cpenable, - ICLASS_xt_iclass_clamp, - ICLASS_xt_iclass_minmax, - ICLASS_xt_iclass_nsa, - ICLASS_xt_iclass_sx, - ICLASS_xt_iclass_l32ai, - ICLASS_xt_iclass_s32ri, - ICLASS_xt_iclass_s32c1i, - ICLASS_xt_iclass_rsr_scompare1, - ICLASS_xt_iclass_wsr_scompare1, - ICLASS_xt_iclass_xsr_scompare1, - ICLASS_xt_iclass_rsr_atomctl, - ICLASS_xt_iclass_wsr_atomctl, - ICLASS_xt_iclass_xsr_atomctl, - ICLASS_xt_iclass_rer, - ICLASS_xt_iclass_wer, - ICLASS_rur_ae_ovf_sar, - ICLASS_wur_ae_ovf_sar, - ICLASS_rur_ae_bithead, - ICLASS_wur_ae_bithead, - ICLASS_rur_ae_ts_fts_bu_bp, - ICLASS_wur_ae_ts_fts_bu_bp, - ICLASS_rur_ae_sd_no, - ICLASS_wur_ae_sd_no, - ICLASS_ae_iclass_rur_ae_overflow, - ICLASS_ae_iclass_wur_ae_overflow, - ICLASS_ae_iclass_rur_ae_sar, - ICLASS_ae_iclass_wur_ae_sar, - ICLASS_ae_iclass_rur_ae_bitptr, - ICLASS_ae_iclass_wur_ae_bitptr, - ICLASS_ae_iclass_rur_ae_bitsused, - ICLASS_ae_iclass_wur_ae_bitsused, - ICLASS_ae_iclass_rur_ae_tablesize, - ICLASS_ae_iclass_wur_ae_tablesize, - ICLASS_ae_iclass_rur_ae_first_ts, - ICLASS_ae_iclass_wur_ae_first_ts, - ICLASS_ae_iclass_rur_ae_nextoffset, - ICLASS_ae_iclass_wur_ae_nextoffset, - ICLASS_ae_iclass_rur_ae_searchdone, - ICLASS_ae_iclass_wur_ae_searchdone, - ICLASS_ae_iclass_lp16f_i, - ICLASS_ae_iclass_lp16f_iu, - ICLASS_ae_iclass_lp16f_x, - ICLASS_ae_iclass_lp16f_xu, - ICLASS_ae_iclass_lp24_i, - ICLASS_ae_iclass_lp24_iu, - ICLASS_ae_iclass_lp24_x, - ICLASS_ae_iclass_lp24_xu, - ICLASS_ae_iclass_lp24f_i, - ICLASS_ae_iclass_lp24f_iu, - ICLASS_ae_iclass_lp24f_x, - ICLASS_ae_iclass_lp24f_xu, - ICLASS_ae_iclass_lp16x2f_i, - ICLASS_ae_iclass_lp16x2f_iu, - ICLASS_ae_iclass_lp16x2f_x, - ICLASS_ae_iclass_lp16x2f_xu, - ICLASS_ae_iclass_lp24x2f_i, - ICLASS_ae_iclass_lp24x2f_iu, - ICLASS_ae_iclass_lp24x2f_x, - ICLASS_ae_iclass_lp24x2f_xu, - ICLASS_ae_iclass_lp24x2_i, - ICLASS_ae_iclass_lp24x2_iu, - ICLASS_ae_iclass_lp24x2_x, - ICLASS_ae_iclass_lp24x2_xu, - ICLASS_ae_iclass_sp16x2f_i, - ICLASS_ae_iclass_sp16x2f_iu, - ICLASS_ae_iclass_sp16x2f_x, - ICLASS_ae_iclass_sp16x2f_xu, - ICLASS_ae_iclass_sp24x2s_i, - ICLASS_ae_iclass_sp24x2s_iu, - ICLASS_ae_iclass_sp24x2s_x, - ICLASS_ae_iclass_sp24x2s_xu, - ICLASS_ae_iclass_sp24x2f_i, - ICLASS_ae_iclass_sp24x2f_iu, - ICLASS_ae_iclass_sp24x2f_x, - ICLASS_ae_iclass_sp24x2f_xu, - ICLASS_ae_iclass_sp16f_l_i, - ICLASS_ae_iclass_sp16f_l_iu, - ICLASS_ae_iclass_sp16f_l_x, - ICLASS_ae_iclass_sp16f_l_xu, - ICLASS_ae_iclass_sp24s_l_i, - ICLASS_ae_iclass_sp24s_l_iu, - ICLASS_ae_iclass_sp24s_l_x, - ICLASS_ae_iclass_sp24s_l_xu, - ICLASS_ae_iclass_sp24f_l_i, - ICLASS_ae_iclass_sp24f_l_iu, - ICLASS_ae_iclass_sp24f_l_x, - ICLASS_ae_iclass_sp24f_l_xu, - ICLASS_ae_iclass_lq56_i, - ICLASS_ae_iclass_lq56_iu, - ICLASS_ae_iclass_lq56_x, - ICLASS_ae_iclass_lq56_xu, - ICLASS_ae_iclass_lq32f_i, - ICLASS_ae_iclass_lq32f_iu, - ICLASS_ae_iclass_lq32f_x, - ICLASS_ae_iclass_lq32f_xu, - ICLASS_ae_iclass_sq56s_i, - ICLASS_ae_iclass_sq56s_iu, - ICLASS_ae_iclass_sq56s_x, - ICLASS_ae_iclass_sq56s_xu, - ICLASS_ae_iclass_sq32f_i, - ICLASS_ae_iclass_sq32f_iu, - ICLASS_ae_iclass_sq32f_x, - ICLASS_ae_iclass_sq32f_xu, - ICLASS_ae_iclass_zerop48, - ICLASS_ae_iclass_movp48, - ICLASS_ae_iclass_selp24_ll, - ICLASS_ae_iclass_selp24_lh, - ICLASS_ae_iclass_selp24_hl, - ICLASS_ae_iclass_selp24_hh, - ICLASS_ae_iclass_movtp24x2, - ICLASS_ae_iclass_movfp24x2, - ICLASS_ae_iclass_movtp48, - ICLASS_ae_iclass_movfp48, - ICLASS_ae_iclass_movpa24x2, - ICLASS_ae_iclass_truncp24a32x2, - ICLASS_ae_iclass_cvta32p24_l, - ICLASS_ae_iclass_cvta32p24_h, - ICLASS_ae_iclass_cvtp24a16x2_ll, - ICLASS_ae_iclass_cvtp24a16x2_lh, - ICLASS_ae_iclass_cvtp24a16x2_hl, - ICLASS_ae_iclass_cvtp24a16x2_hh, - ICLASS_ae_iclass_truncp24q48x2, - ICLASS_ae_iclass_truncp16, - ICLASS_ae_iclass_roundsp24q48sym, - ICLASS_ae_iclass_roundsp24q48asym, - ICLASS_ae_iclass_roundsp16q48sym, - ICLASS_ae_iclass_roundsp16q48asym, - ICLASS_ae_iclass_roundsp16sym, - ICLASS_ae_iclass_roundsp16asym, - ICLASS_ae_iclass_zeroq56, - ICLASS_ae_iclass_movq56, - ICLASS_ae_iclass_movtq56, - ICLASS_ae_iclass_movfq56, - ICLASS_ae_iclass_cvtq48a32s, - ICLASS_ae_iclass_cvtq48p24s_l, - ICLASS_ae_iclass_cvtq48p24s_h, - ICLASS_ae_iclass_satq48s, - ICLASS_ae_iclass_truncq32, - ICLASS_ae_iclass_roundsq32sym, - ICLASS_ae_iclass_roundsq32asym, - ICLASS_ae_iclass_trunca32q48, - ICLASS_ae_iclass_movap24s_l, - ICLASS_ae_iclass_movap24s_h, - ICLASS_ae_iclass_trunca16p24s_l, - ICLASS_ae_iclass_trunca16p24s_h, - ICLASS_ae_iclass_addp24, - ICLASS_ae_iclass_subp24, - ICLASS_ae_iclass_negp24, - ICLASS_ae_iclass_absp24, - ICLASS_ae_iclass_maxp24s, - ICLASS_ae_iclass_minp24s, - ICLASS_ae_iclass_maxbp24s, - ICLASS_ae_iclass_minbp24s, - ICLASS_ae_iclass_addsp24s, - ICLASS_ae_iclass_subsp24s, - ICLASS_ae_iclass_negsp24s, - ICLASS_ae_iclass_abssp24s, - ICLASS_ae_iclass_andp48, - ICLASS_ae_iclass_nandp48, - ICLASS_ae_iclass_orp48, - ICLASS_ae_iclass_xorp48, - ICLASS_ae_iclass_ltp24s, - ICLASS_ae_iclass_lep24s, - ICLASS_ae_iclass_eqp24, - ICLASS_ae_iclass_addq56, - ICLASS_ae_iclass_subq56, - ICLASS_ae_iclass_negq56, - ICLASS_ae_iclass_absq56, - ICLASS_ae_iclass_maxq56s, - ICLASS_ae_iclass_minq56s, - ICLASS_ae_iclass_maxbq56s, - ICLASS_ae_iclass_minbq56s, - ICLASS_ae_iclass_addsq56s, - ICLASS_ae_iclass_subsq56s, - ICLASS_ae_iclass_negsq56s, - ICLASS_ae_iclass_abssq56s, - ICLASS_ae_iclass_andq56, - ICLASS_ae_iclass_nandq56, - ICLASS_ae_iclass_orq56, - ICLASS_ae_iclass_xorq56, - ICLASS_ae_iclass_sllip24, - ICLASS_ae_iclass_srlip24, - ICLASS_ae_iclass_sraip24, - ICLASS_ae_iclass_sllsp24, - ICLASS_ae_iclass_srlsp24, - ICLASS_ae_iclass_srasp24, - ICLASS_ae_iclass_sllisp24s, - ICLASS_ae_iclass_sllssp24s, - ICLASS_ae_iclass_slliq56, - ICLASS_ae_iclass_srliq56, - ICLASS_ae_iclass_sraiq56, - ICLASS_ae_iclass_sllsq56, - ICLASS_ae_iclass_srlsq56, - ICLASS_ae_iclass_srasq56, - ICLASS_ae_iclass_sllaq56, - ICLASS_ae_iclass_srlaq56, - ICLASS_ae_iclass_sraaq56, - ICLASS_ae_iclass_sllisq56s, - ICLASS_ae_iclass_sllssq56s, - ICLASS_ae_iclass_sllasq56s, - ICLASS_ae_iclass_ltq56s, - ICLASS_ae_iclass_leq56s, - ICLASS_ae_iclass_eqq56, - ICLASS_ae_iclass_nsaq56s, - ICLASS_ae_iclass_mulsrfq32sp24s_h, - ICLASS_ae_iclass_mulsrfq32sp24s_l, - ICLASS_ae_iclass_mularfq32sp24s_h, - ICLASS_ae_iclass_mularfq32sp24s_l, - ICLASS_ae_iclass_mulrfq32sp24s_h, - ICLASS_ae_iclass_mulrfq32sp24s_l, - ICLASS_ae_iclass_mulsfq32sp24s_h, - ICLASS_ae_iclass_mulsfq32sp24s_l, - ICLASS_ae_iclass_mulafq32sp24s_h, - ICLASS_ae_iclass_mulafq32sp24s_l, - ICLASS_ae_iclass_mulfq32sp24s_h, - ICLASS_ae_iclass_mulfq32sp24s_l, - ICLASS_ae_iclass_mulfs32p16s_ll, - ICLASS_ae_iclass_mulfp24s_ll, - ICLASS_ae_iclass_mulp24s_ll, - ICLASS_ae_iclass_mulfs32p16s_lh, - ICLASS_ae_iclass_mulfp24s_lh, - ICLASS_ae_iclass_mulp24s_lh, - ICLASS_ae_iclass_mulfs32p16s_hl, - ICLASS_ae_iclass_mulfp24s_hl, - ICLASS_ae_iclass_mulp24s_hl, - ICLASS_ae_iclass_mulfs32p16s_hh, - ICLASS_ae_iclass_mulfp24s_hh, - ICLASS_ae_iclass_mulp24s_hh, - ICLASS_ae_iclass_mulafs32p16s_ll, - ICLASS_ae_iclass_mulafp24s_ll, - ICLASS_ae_iclass_mulap24s_ll, - ICLASS_ae_iclass_mulafs32p16s_lh, - ICLASS_ae_iclass_mulafp24s_lh, - ICLASS_ae_iclass_mulap24s_lh, - ICLASS_ae_iclass_mulafs32p16s_hl, - ICLASS_ae_iclass_mulafp24s_hl, - ICLASS_ae_iclass_mulap24s_hl, - ICLASS_ae_iclass_mulafs32p16s_hh, - ICLASS_ae_iclass_mulafp24s_hh, - ICLASS_ae_iclass_mulap24s_hh, - ICLASS_ae_iclass_mulsfs32p16s_ll, - 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slotbuf[0] = 0x2080; -} - -static void -Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000; -} - -static void -Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3200; -} - -static void -Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5000; -} - -static void -Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35; -} - -static void -Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x25; -} - -static void -Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15; -} - -static void -Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf0; -} - -static void -Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0; -} - -static void -Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd0; -} - -static void -Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36; -} - -static void -Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1000; -} - -static void -Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x408000; -} - -static void -Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90; -} - -static void -Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf01d; -} - -static void -Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3400; -} - -static void -Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3500; -} - -static void -Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90000; -} - -static void -Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x490000; -} - -static void -Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34800; -} - -static void -Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134800; -} - -static void -Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614800; -} - -static void -Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34900; -} - -static void -Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134900; -} - -static void -Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614900; -} - -static void -Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa; -} - -static void -Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb; -} - -static void -Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8c; -} - -static void -Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcc; -} - -static void -Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf06d; -} - -static void -Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8; -} - -static void -Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd; -} - -static void -Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc; -} - -static void -Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf03d; -} - -static void -Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00d; -} - -static void -Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9; -} - -static void -Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30e70; -} - -static void -Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3e700; -} - -static void -Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc002; -} - -static void -Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200040; -} - -static void -Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd002; -} - -static void -Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200080; -} - -static void -Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800000; -} - -static void -Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b2000; -} - -static void -Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc00000; -} - -static void -Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ca000; -} - -static void -Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900000; -} - -static void -Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b4000; -} - -static void -Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00000; -} - -static void -Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b8000; -} - -static void -Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb00000; -} - -static void -Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b3000; -} - -static void -Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd00000; -} - -static void -Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cc000; -} - -static void -Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00000; -} - -static void -Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cb000; -} - -static void -Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00000; -} - -static void -Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cd000; -} - -static void -Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b5000; -} - -static void -Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e0000; -} - -static void -Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300000; -} - -static void -Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ce000; -} - -static void -Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x26; -} - -static void -Opcode_beqi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300000; -} - -static void -Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x66; -} - -static void -Opcode_bnei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300003; -} - -static void -Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe6; -} - -static void -Opcode_bgei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300001; -} - -static void -Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa6; -} - -static void -Opcode_blti_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300004; -} - -static void -Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6007; -} - -static void -Opcode_bbci_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe007; -} - -static void -Opcode_bbsi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200020; -} - -static void -Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf6; -} - -static void -Opcode_bgeui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300002; -} - -static void -Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb6; -} - -static void -Opcode_bltui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300008; -} - -static void -Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1007; -} - -static void -Opcode_beq_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000a0; -} - -static void -Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9007; -} - -static void -Opcode_bne_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400000; -} - -static void -Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa007; -} - -static void -Opcode_bge_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000c0; -} - -static void -Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2007; -} - -static void -Opcode_blt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000d0; -} - -static void -Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb007; -} - -static void -Opcode_bgeu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000b0; -} - -static void -Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3007; -} - -static void -Opcode_bltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000e0; -} - -static void -Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8007; -} - -static void -Opcode_bany_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200060; -} - -static void -Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7; -} - -static void -Opcode_bnone_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400010; -} - -static void -Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4007; -} - -static void -Opcode_ball_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200050; -} - -static void -Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc007; -} - -static void -Opcode_bnall_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000f0; -} - -static void -Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5007; -} - -static void -Opcode_bbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200070; -} - -static void -Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd007; -} - -static void -Opcode_bbs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200090; -} - -static void -Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16; -} - -static void -Opcode_beqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180000; -} - -static void -Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x56; -} - -static void -Opcode_bnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x190000; -} - -static void -Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd6; -} - -static void -Opcode_bgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x160000; -} - -static void -Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x96; -} - -static void -Opcode_bltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x170000; -} - -static void -Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5; -} - -static void -Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc0; -} - -static void -Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000; -} - -static void -Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x140000; -} - -static void -Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0; -} - -static void -Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6; -} - -static void -Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0; -} - -static void -Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee031; -} - -static void -Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1002; -} - -static void -Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400040; -} - -static void -Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9002; -} - -static void -Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400020; -} - -static void -Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2002; -} - -static void -Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400080; -} - -static void -Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1; -} - -static void -Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500000; -} - -static void -Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2; -} - -static void -Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400030; -} - -static void -Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8076; -} - -static void -Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9076; -} - -static void -Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa076; -} - -static void -Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa002; -} - -static void -Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a0000; -} - -static void -Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x830000; -} - -static void -Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1be000; -} - -static void -Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x930000; -} - -static void -Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c8000; -} - -static void -Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa30000; -} - -static void -Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c4000; -} - -static void -Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb30000; -} - -static void -Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c2000; -} - -static void -Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600000; -} - -static void -Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1d00; -} - -static void -Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600100; -} - -static void -Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1c00; -} - -static void -Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20f0; -} - -static void -Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16105; -} - -static void -Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee0b1; -} - -static void -Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80; -} - -static void -Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5100; -} - -static void -Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5002; -} - -static void -Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400050; -} - -static void -Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6002; -} - -static void -Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400060; -} - -static void -Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4002; -} - -static void -Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400070; -} - -static void -Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400000; -} - -static void -Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee071; -} - -static void -Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x401000; -} - -static void -Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee038; -} - -static void -Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x402000; -} - -static void -Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee034; -} - -static void -Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x403000; -} - -static void -Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee032; -} - -static void -Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x404000; -} - -static void -Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef0a0; -} - -static void -Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa10000; -} - -static void -Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5003; -} - -static void -Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x810000; -} - -static void -Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c7000; -} - -static void -Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x910000; -} - -static void -Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1f00; -} - -static void -Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb10000; -} - -static void -Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1e00; -} - -static void -Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10000; -} - -static void -Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c0000; -} - -static void -Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x210000; -} - -static void -Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b0000; -} - -static void -Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x410000; -} - -static void -Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c9000; -} - -static void -Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20c0; -} - -static void -Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20d0; -} - -static void -Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000; -} - -static void -Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2010; -} - -static void -Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2020; -} - -static void -Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2030; -} - -static void -Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000; -} - -static void -Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30100; -} - -static void -Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130100; -} - -static void -Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610100; -} - -static void -Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30200; -} - -static void -Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130200; -} - -static void -Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610200; -} - -static void -Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000; -} - -static void -Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130000; -} - -static void -Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610000; -} - -static void -Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30300; -} - -static void -Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130300; -} - -static void -Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610300; -} - -static void -Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30500; -} - -static void -Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130500; -} - -static void -Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610500; -} - -static void -Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b000; -} - -static void -Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b000; -} - -static void -Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d000; -} - -static void -Opcode_rsr_243_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f300; -} - -static void -Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e600; -} - -static void -Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e600; -} - -static void -Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e600; -} - -static void -Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b100; -} - -static void -Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b100; -} - -static void -Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b100; -} - -static void -Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d100; -} - -static void -Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d100; -} - -static void -Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d100; -} - -static void -Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b200; -} - -static void -Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b200; -} - -static void -Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b200; -} - -static void -Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d200; -} - -static void -Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d200; -} - -static void -Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d200; -} - -static void -Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b300; -} - -static void -Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b300; -} - -static void -Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b300; -} - -static void -Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d300; -} - -static void -Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d300; -} - -static void -Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d300; -} - -static void -Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b400; -} - -static void -Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b400; -} - -static void -Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b400; -} - -static void -Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d400; -} - -static void -Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d400; -} - -static void -Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d400; -} - -static void -Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b500; -} - -static void -Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b500; -} - -static void -Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b500; -} - -static void -Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d500; -} - -static void -Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d500; -} - -static void -Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d500; -} - -static void -Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b600; -} - -static void -Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b600; -} - -static void -Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b600; -} - -static void -Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d600; -} - -static void -Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d600; -} - -static void -Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d600; -} - -static void -Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b700; -} - -static void -Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b700; -} - -static void -Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b700; -} - -static void -Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d700; -} - -static void -Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d700; -} - -static void -Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d700; -} - -static void -Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c200; -} - -static void -Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c200; -} - -static void -Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c200; -} - -static void -Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c300; -} - -static void -Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c300; -} - -static void -Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c300; -} - -static void -Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c400; -} - -static void -Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c400; -} - -static void -Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c400; -} - -static void -Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c500; -} - -static void -Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c500; -} - -static void -Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c500; -} - -static void -Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c600; -} - -static void -Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c600; -} - -static void -Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c600; -} - -static void -Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c700; -} - -static void -Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c700; -} - -static void -Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c700; -} - -static void -Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ee00; -} - -static void -Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ee00; -} - -static void -Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ee00; -} - -static void -Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c000; -} - -static void -Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c000; -} - -static void -Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c000; -} - -static void -Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e800; -} - -static void -Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e800; -} - -static void -Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e800; -} - -static void -Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3eb00; -} - -static void -Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e700; -} - -static void -Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e700; -} - -static void -Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e700; -} - -static void -Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc10000; -} - -static void -Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd10000; -} - -static void -Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x820000; -} - -static void -Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa20000; -} - -static void -Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb20000; -} - -static void -Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x740004; -} - -static void -Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x750004; -} - -static void -Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x760004; -} - -static void -Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x770004; -} - -static void -Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700004; -} - -static void -Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x710004; -} - -static void -Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x720004; -} - -static void -Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x730004; -} - -static void -Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x340004; -} - -static void -Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x350004; -} - -static void -Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x360004; -} - -static void -Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x370004; -} - -static void -Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x640004; -} - -static void -Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x650004; -} - -static void -Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x660004; -} - -static void -Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x670004; -} - -static void -Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x240004; -} - -static void -Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x250004; -} - -static void -Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x260004; -} - -static void -Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x270004; -} - -static void -Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x780004; -} - -static void -Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x790004; -} - -static void -Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7a0004; -} - -static void -Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7b0004; -} - -static void -Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7c0004; -} - -static void -Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7d0004; -} - -static void -Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7e0004; -} - -static void -Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7f0004; -} - -static void -Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x380004; -} - -static void -Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x390004; -} - -static void -Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a0004; -} - -static void -Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b0004; -} - -static void -Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c0004; -} - -static void -Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d0004; -} - -static void -Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e0004; -} - -static void -Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f0004; -} - -static void -Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x680004; -} - -static void -Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x690004; -} - -static void -Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6a0004; -} - -static void -Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6b0004; -} - -static void -Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6c0004; -} - -static void -Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6d0004; -} - -static void -Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6e0004; -} - -static void -Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6f0004; -} - -static void -Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280004; -} - -static void -Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x290004; -} - -static void -Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2a0004; -} - -static void -Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2b0004; -} - -static void -Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2c0004; -} - -static void -Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2d0004; -} - -static void -Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2e0004; -} - -static void -Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2f0004; -} - -static void -Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x580004; -} - -static void -Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x480004; -} - -static void -Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x590004; -} - -static void -Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x490004; -} - -static void -Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5a0004; -} - -static void -Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4a0004; -} - -static void -Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5b0004; -} - -static void -Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4b0004; -} - -static void -Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180004; -} - -static void -Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80004; -} - -static void -Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x190004; -} - -static void -Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90004; -} - -static void -Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a0004; -} - -static void -Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0004; -} - -static void -Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b0004; -} - -static void -Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb0004; -} - -static void -Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900004; -} - -static void -Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800004; -} - -static void -Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32000; -} - -static void -Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132000; -} - -static void -Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612000; -} - -static void -Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32100; -} - -static void -Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132100; -} - -static void -Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612100; -} - -static void -Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32200; -} - -static void -Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132200; -} - -static void -Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612200; -} - -static void -Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32300; -} - -static void -Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132300; -} - -static void -Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612300; -} - -static void -Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31000; -} - -static void -Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131000; -} - -static void -Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x611000; -} - -static void -Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31100; -} - -static void -Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131100; -} - -static void -Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x611100; -} - -static void -Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3010; -} - -static void -Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7000; -} - -static void -Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e200; -} - -static void -Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e200; -} - -static void -Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e300; -} - -static void -Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e400; -} - -static void -Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e400; -} - -static void -Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e400; -} - -static void -Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000; -} - -static void -Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf02d; -} - -static void -Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39000; -} - -static void -Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139000; -} - -static void -Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619000; -} - -static void -Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a000; -} - -static void -Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a000; -} - -static void -Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a000; -} - -static void -Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39100; -} - -static void -Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139100; -} - -static void -Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619100; -} - -static void -Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a100; -} - -static void -Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a100; -} - -static void -Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a100; -} - -static void -Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38000; -} - -static void -Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138000; -} - -static void -Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618000; -} - -static void -Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38100; -} - -static void -Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138100; -} - -static void -Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618100; -} - -static void -Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36000; -} - -static void -Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136000; -} - -static void -Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616000; -} - -static void -Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e900; -} - -static void -Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e900; -} - -static void -Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e900; -} - -static void -Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ec00; -} - -static void -Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ec00; -} - -static void -Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ec00; -} - -static void -Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ed00; -} - -static void -Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ed00; -} - -static void -Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ed00; -} - -static void -Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36800; -} - -static void -Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136800; -} - -static void -Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616800; -} - -static void -Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e000; -} - -static void -Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e010; -} - -static void -Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20000; -} - -static void -Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b6000; -} - -static void -Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x120000; -} - -static void -Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b7000; -} - -static void -Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x220000; -} - -static void -Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c3000; -} - -static void -Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x320000; -} - -static void -Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c5000; -} - -static void -Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x420000; -} - -static void -Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cf000; -} - -static void -Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8000; -} - -static void -Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2480; -} - -static void -Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9000; -} - -static void -Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2800; -} - -static void -Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa000; -} - -static void -Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef060; -} - -static void -Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb000; -} - -static void -Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef020; -} - -static void -Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x76; -} - -static void -Opcode_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300005; -} - -static void -Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1076; -} - -static void -Opcode_bt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300006; -} - -static void -Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc30000; -} - -static void -Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bf000; -} - -static void -Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd30000; -} - -static void -Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d0000; -} - -static void -Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30400; -} - -static void -Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130400; -} - -static void -Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610400; -} - -static void -Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ea00; -} - -static void -Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ea00; -} - -static void -Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ea00; -} - -static void -Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f000; -} - -static void -Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f000; -} - -static void -Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f000; -} - -static void -Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f100; -} - -static void -Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f100; -} - -static void -Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f100; -} - -static void -Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f200; -} - -static void -Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f200; -} - -static void -Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f200; -} - -static void -Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70c2; -} - -static void -Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70e2; -} - -static void -Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70d2; -} - -static void -Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x270d2; -} - -static void -Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x370d2; -} - -static void -Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70f2; -} - -static void -Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf10000; -} - -static void -Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf12000; -} - -static void -Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf11000; -} - -static void -Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf13000; -} - -static void -Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7042; -} - -static void -Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7052; -} - -static void -Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x47082; -} - -static void -Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x57082; -} - -static void -Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7062; -} - -static void -Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7072; -} - -static void -Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7002; -} - -static void -Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7012; -} - -static void -Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7022; -} - -static void -Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7032; -} - -static void -Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7082; -} - -static void -Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x27082; -} - -static void -Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x37082; -} - -static void -Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf19000; -} - -static void -Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf18000; -} - -static void -Opcode_rsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32800; -} - -static void -Opcode_wsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132800; -} - -static void -Opcode_xsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612800; -} - -static void -Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50c000; -} - -static void -Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50d000; -} - -static void -Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50b000; -} - -static void -Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50f000; -} - -static void -Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50e000; -} - -static void -Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x504000; -} - -static void -Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x505000; -} - -static void -Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x503000; -} - -static void -Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x507000; -} - -static void -Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x506000; -} - -static void -Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e000; -} - -static void -Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e000; -} - -static void -Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e000; -} - -static void -Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x330000; -} - -static void -Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b9000; -} - -static void -Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x430000; -} - -static void -Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bb000; -} - -static void -Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x530000; -} - -static void -Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ba000; -} - -static void -Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x630000; -} - -static void -Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bd000; -} - -static void -Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x730000; -} - -static void -Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bc000; -} - -static void -Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40e000; -} - -static void -Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40f000; -} - -static void -Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x230000; -} - -static void -Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c6000; -} - -static void -Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb002; -} - -static void -Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf002; -} - -static void -Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe002; -} - -static void -Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30c00; -} - -static void -Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130c00; -} - -static void -Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610c00; -} - -static void -Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36300; -} - -static void -Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136300; -} - -static void -Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616300; -} - -static void -Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x406000; -} - -static void -Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x407000; -} - -static void -Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f00; -} - -static void -Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f000; -} - -static void -Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f10; -} - -static void -Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f100; -} - -static void -Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f20; -} - -static void -Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f200; -} - -static void -Opcode_rur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f30; -} - -static void -Opcode_wur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f300; -} - -static void -Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90804; -} - -static void -Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca0004; -} - -static void -Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90904; -} - -static void -Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca1004; -} - -static void -Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90a04; -} - -static void -Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca2004; -} - -static void -Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90b04; -} - -static void -Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca3004; -} - -static void -Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90c04; -} - -static void -Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca4004; -} - -static void -Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90d04; -} - -static void -Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca5004; -} - -static void -Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90e04; -} - -static void -Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca6004; -} - -static void -Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90f04; -} - -static void -Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca7004; -} - -static void -Opcode_ae_lp16f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d1080; -} - -static void -Opcode_ae_lp16f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa50004; -} - -static void -Opcode_ae_lp16f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d2080; -} - -static void -Opcode_ae_lp16f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa90004; -} - -static void -Opcode_ae_lp16f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d3000; -} - -static void -Opcode_ae_lp16f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xac0004; -} - -static void -Opcode_ae_lp16f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d3080; -} - -static void -Opcode_ae_lp16f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaf0004; -} - -static void -Opcode_ae_lp24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d6080; -} - -static void -Opcode_ae_lp24_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa58004; -} - -static void -Opcode_ae_lp24_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d7000; -} - -static void -Opcode_ae_lp24_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa98004; -} - -static void -Opcode_ae_lp24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d7080; -} - -static void -Opcode_ae_lp24_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xac8004; -} - -static void -Opcode_ae_lp24_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d8080; -} - -static void -Opcode_ae_lp24_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaf8004; -} - -static void -Opcode_ae_lp24f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d9000; -} - -static void -Opcode_ae_lp24f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa60004; -} - -static void -Opcode_ae_lp24f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1da000; -} - -static void -Opcode_ae_lp24f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaa0004; -} - -static void -Opcode_ae_lp24f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dc000; -} - -static void -Opcode_ae_lp24f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xad0004; -} - -static void -Opcode_ae_lp24f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d9080; -} - -static void -Opcode_ae_lp24f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb00004; -} - -static void -Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d4080; -} - -static void -Opcode_ae_lp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa68004; -} - -static void -Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d5000; -} - -static void -Opcode_ae_lp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaa8004; -} - -static void -Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d6000; -} - -static void -Opcode_ae_lp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xad8004; -} - -static void -Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d5080; -} - -static void -Opcode_ae_lp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb08004; -} - -static void -Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dd000; -} - -static void -Opcode_ae_lp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa70004; -} - -static void -Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1de000; -} - -static void -Opcode_ae_lp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xab0004; -} - -static void -Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dd080; -} - -static void -Opcode_ae_lp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xae0004; -} - -static void -Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1de080; -} - -static void -Opcode_ae_lp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb10004; -} - -static void -Opcode_ae_lp24x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1da080; -} - -static void -Opcode_ae_lp24x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa78004; -} - -static void -Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1db000; -} - -static void -Opcode_ae_lp24x2_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xab8004; -} - -static void -Opcode_ae_lp24x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1db080; -} - -static void -Opcode_ae_lp24x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xae8004; -} - -static void -Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dc080; -} - -static void -Opcode_ae_lp24x2_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb18004; -} - -static void -Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e8000; -} - -static void -Opcode_ae_sp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb20004; -} - -static void -Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f0000; -} - -static void -Opcode_ae_sp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb50004; -} - -static void -Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e1080; -} - -static void -Opcode_ae_sp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb80004; -} - -static void -Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e2080; -} - -static void -Opcode_ae_sp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbb0004; -} - -static void -Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ec000; -} - -static void -Opcode_ae_sp24x2s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb28004; -} - -static void -Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e9080; -} - -static void -Opcode_ae_sp24x2s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb58004; -} - -static void -Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ea080; -} - -static void -Opcode_ae_sp24x2s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb88004; -} - -static void -Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1eb000; -} - -static void -Opcode_ae_sp24x2s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbb8004; -} - -static void -Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e7080; -} - -static void -Opcode_ae_sp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb30004; -} - -static void -Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e8080; -} - -static void -Opcode_ae_sp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb60004; -} - -static void -Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e9000; -} - -static void -Opcode_ae_sp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb90004; -} - -static void -Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ea000; -} - -static void -Opcode_ae_sp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbc0004; -} - -static void -Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1df080; -} - -static void -Opcode_ae_sp16f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb38004; -} - -static void -Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e1000; -} - -static void -Opcode_ae_sp16f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb68004; -} - -static void -Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e2000; -} - -static void -Opcode_ae_sp16f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb98004; -} - -static void -Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e4000; -} - -static void -Opcode_ae_sp16f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbc8004; -} - -static void -Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e6000; -} - -static void -Opcode_ae_sp24s_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb40004; -} - -static void -Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e5080; -} - -static void -Opcode_ae_sp24s_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb70004; -} - -static void -Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e6080; -} - -static void -Opcode_ae_sp24s_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xba0004; -} - -static void -Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e7000; -} - -static void -Opcode_ae_sp24s_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbd0004; -} - -static void -Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e3000; -} - -static void -Opcode_ae_sp24f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb48004; -} - -static void -Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e3080; -} - -static void -Opcode_ae_sp24f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb78004; -} - -static void -Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e4080; -} - -static void -Opcode_ae_sp24f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xba8004; -} - -static void -Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e5000; -} - -static void -Opcode_ae_sp24f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbd8004; -} - -static void -Opcode_ae_lq56_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed030; -} - -static void -Opcode_ae_lq56_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc10004; -} - -static void -Opcode_ae_lq56_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee010; -} - -static void -Opcode_ae_lq56_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc12004; -} - -static void -Opcode_ae_lq56_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee020; -} - -static void -Opcode_ae_lq56_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc20004; -} - -static void -Opcode_ae_lq56_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef000; -} - -static void -Opcode_ae_lq56_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc22004; -} - -static void -Opcode_ae_lq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed000; -} - -static void -Opcode_ae_lq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc11004; -} - -static void -Opcode_ae_lq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee000; -} - -static void -Opcode_ae_lq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc13004; -} - -static void -Opcode_ae_lq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed010; -} - -static void -Opcode_ae_lq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc21004; -} - -static void -Opcode_ae_lq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed020; -} - -static void -Opcode_ae_lq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc23004; -} - -static void -Opcode_ae_sq56s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f0080; -} - -static void -Opcode_ae_sq56s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc30004; -} - -static void -Opcode_ae_sq56s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f00c0; -} - -static void -Opcode_ae_sq56s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc38004; -} - -static void -Opcode_ae_sq56s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3000; -} - -static void -Opcode_ae_sq56s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc40004; -} - -static void -Opcode_ae_sq56s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3040; -} - -static void -Opcode_ae_sq56s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc48004; -} - -static void -Opcode_ae_sq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ec080; -} - -static void -Opcode_ae_sq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc34004; -} - -static void -Opcode_ae_sq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ec0c0; -} - -static void -Opcode_ae_sq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc3c004; -} - -static void -Opcode_ae_sq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f4000; -} - -static void -Opcode_ae_sq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc44004; -} - -static void -Opcode_ae_sq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f8000; -} - -static void -Opcode_ae_sq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc4c004; -} - -static void -Opcode_ae_zerop48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16b88; -} - -static void -Opcode_ae_movp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16808; -} - -static void -Opcode_ae_movp48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2400; -} - -static void -Opcode_ae_movp48_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90004; -} - -static void -Opcode_ae_selp24_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10780; -} - -static void -Opcode_ae_selp24_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2e00; -} - -static void -Opcode_ae_selp24_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10708; -} - -static void -Opcode_ae_selp24_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fa600; -} - -static void -Opcode_ae_selp24_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10688; -} - -static void -Opcode_ae_selp24_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fa200; -} - -static void -Opcode_ae_selp24_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10700; -} - -static void -Opcode_ae_selp24_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fa000; -} - -static void -Opcode_ae_movtp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c200; -} - -static void -Opcode_ae_movfp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c004; -} - -static void -Opcode_ae_movtp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10480; -} - -static void -Opcode_ae_movfp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10400; -} - -static void -Opcode_ae_movpa24x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1df000; -} - -static void -Opcode_ae_movpa24x2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc00004; -} - -static void -Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1eb080; -} - -static void -Opcode_ae_truncp24a32x2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc08004; -} - -static void -Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3081; -} - -static void -Opcode_ae_cvta32p24_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcb0004; -} - -static void -Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3080; -} - -static void -Opcode_ae_cvta32p24_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcb8004; -} - -static void -Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d8000; -} - -static void -Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbe0004; -} - -static void -Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d4000; -} - -static void -Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbe8004; -} - -static void -Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d2000; -} - -static void -Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbf0004; -} - -static void -Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d1000; -} - -static void -Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbf8004; -} - -static void -Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x51000; -} - -static void -Opcode_ae_truncp16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16b08; -} - -static void -Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e48; -} - -static void -Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e28; -} - -static void -Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e18; -} - -static void -Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e08; -} - -static void -Opcode_ae_roundsp16sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16908; -} - -static void -Opcode_ae_roundsp16asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16888; -} - -static void -Opcode_ae_zeroq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16085; -} - -static void -Opcode_ae_movq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16007; -} - -static void -Opcode_ae_movq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2500; -} - -static void -Opcode_ae_movq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90414; -} - -static void -Opcode_ae_movtq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f6000; -} - -static void -Opcode_ae_movtq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe50014; -} - -static void -Opcode_ae_movfq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5000; -} - -static void -Opcode_ae_movfq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe60014; -} - -static void -Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee030; -} - -static void -Opcode_ae_cvtq48a32s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe72034; -} - -static void -Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16006; -} - -static void -Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16005; -} - -static void -Opcode_ae_satq48s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50139; -} - -static void -Opcode_ae_truncq32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16047; -} - -static void -Opcode_ae_roundsq32sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16027; -} - -static void -Opcode_ae_roundsq32asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16017; -} - -static void -Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3086; -} - -static void -Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe70014; -} - -static void -Opcode_ae_movap24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3084; -} - -static void -Opcode_ae_movap24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc70004; -} - -static void -Opcode_ae_movap24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3082; -} - -static void -Opcode_ae_movap24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc78004; -} - -static void -Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3083; -} - -static void -Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc80004; -} - -static void -Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3088; -} - -static void -Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc88004; -} - -static void -Opcode_ae_addp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10500; -} - -static void -Opcode_ae_subp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10788; -} - -static void -Opcode_ae_negp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c600; -} - -static void -Opcode_ae_absp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c480; -} - -static void -Opcode_ae_maxp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10580; -} - -static void -Opcode_ae_minp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10588; -} - -static void -Opcode_ae_maxbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10000; -} - -static void -Opcode_ae_minbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10200; -} - -static void -Opcode_ae_addsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10600; -} - -static void -Opcode_ae_subsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c400; -} - -static void -Opcode_ae_negsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c488; -} - -static void -Opcode_ae_abssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c500; -} - -static void -Opcode_ae_andp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10508; -} - -static void -Opcode_ae_nandp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10608; -} - -static void -Opcode_ae_orp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10680; -} - -static void -Opcode_ae_xorp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c408; -} - -static void -Opcode_ae_ltp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c002; -} - -static void -Opcode_ae_lep24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c001; -} - -static void -Opcode_ae_eqp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c000; -} - -static void -Opcode_ae_addq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x52000; -} - -static void -Opcode_ae_subq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50035; -} - -static void -Opcode_ae_negq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5003c; -} - -static void -Opcode_ae_absq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50039; -} - -static void -Opcode_ae_maxq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50032; -} - -static void -Opcode_ae_minq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50034; -} - -static void -Opcode_ae_maxbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50000; -} - -static void -Opcode_ae_minbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50010; -} - -static void -Opcode_ae_addsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50030; -} - -static void -Opcode_ae_subsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50036; -} - -static void -Opcode_ae_negsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500b9; -} - -static void -Opcode_ae_abssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5003a; -} - -static void -Opcode_ae_andq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50031; -} - -static void -Opcode_ae_nandq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50038; -} - -static void -Opcode_ae_orq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50033; -} - -static void -Opcode_ae_xorq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50037; -} - -static void -Opcode_ae_sllip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x14000; -} - -static void -Opcode_ae_srlip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15000; -} - -static void -Opcode_ae_sraip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x14800; -} - -static void -Opcode_ae_sllsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16a08; -} - -static void -Opcode_ae_srlsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16a88; -} - -static void -Opcode_ae_srasp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16988; -} - -static void -Opcode_ae_sllisp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x18000; -} - -static void -Opcode_ae_sllssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16c08; -} - -static void -Opcode_ae_slliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1000; -} - -static void -Opcode_ae_slliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50004; -} - -static void -Opcode_ae_srliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1800; -} - -static void -Opcode_ae_srliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50404; -} - -static void -Opcode_ae_sraiq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1400; -} - -static void -Opcode_ae_sraiq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50804; -} - -static void -Opcode_ae_sllsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2600; -} - -static void -Opcode_ae_sllsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90014; -} - -static void -Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2504; -} - -static void -Opcode_ae_srlsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90114; -} - -static void -Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2502; -} - -static void -Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90214; -} - -static void -Opcode_ae_sllaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5001; -} - -static void -Opcode_ae_sllaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe10014; -} - -static void -Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5008; -} - -static void -Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe20014; -} - -static void -Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5004; -} - -static void -Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30014; -} - -static void -Opcode_ae_sllisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2000; -} - -static void -Opcode_ae_sllisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50c04; -} - -static void -Opcode_ae_sllssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2501; -} - -static void -Opcode_ae_sllssq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90314; -} - -static void -Opcode_ae_sllasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5002; -} - -static void -Opcode_ae_sllasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe40014; -} - -static void -Opcode_ae_ltq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50800; -} - -static void -Opcode_ae_leq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50040; -} - -static void -Opcode_ae_eqq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50020; -} - -static void -Opcode_ae_nsaq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3085; -} - -static void -Opcode_ae_nsaq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe74014; -} - -static void -Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19004; -} - -static void -Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19005; -} - -static void -Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19002; -} - -static void -Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19003; -} - -static void -Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19000; -} - -static void -Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19001; -} - -static void -Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1900a; -} - -static void -Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1900b; -} - -static void -Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19008; -} - -static void -Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19009; -} - -static void -Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19006; -} - -static void -Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19007; -} - -static void -Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60101; -} - -static void -Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008b; -} - -static void -Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60180; -} - -static void -Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008f; -} - -static void -Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008c; -} - -static void -Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60108; -} - -static void -Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008e; -} - -static void -Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008a; -} - -static void -Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60104; -} - -static void -Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008d; -} - -static void -Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60089; -} - -static void -Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60102; -} - -static void -Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60006; -} - -static void -Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64000; -} - -static void -Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000f; -} - -static void -Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60005; -} - -static void -Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60100; -} - -static void -Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000e; -} - -static void -Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60003; -} - -static void -Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60080; -} - -static void -Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000d; -} - -static void -Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x68000; -} - -static void -Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60008; -} - -static void -Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000b; -} - -static void -Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60181; -} - -static void -Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010b; -} - -static void -Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60189; -} - -static void -Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010f; -} - -static void -Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010c; -} - -static void -Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60187; -} - -static void -Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010e; -} - -static void -Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010a; -} - -static void -Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60186; -} - -static void -Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010d; -} - -static void -Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60109; -} - -static void -Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60185; -} - -static void -Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000c; -} - -static void -Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60088; -} - -static void -Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000a; -} - -static void -Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60084; -} - -static void -Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60009; -} - -static void -Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60082; -} - -static void -Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60007; -} - -static void -Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60081; -} - -static void -Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60183; -} - -static void -Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018d; -} - -static void -Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60188; -} - -static void -Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018b; -} - -static void -Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60184; -} - -static void -Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018c; -} - -static void -Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60182; -} - -static void -Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018a; -} - -static void -Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15807; -} - -static void -Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15806; -} - -static void -Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580a; -} - -static void -Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15809; -} - -static void -Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580b; -} - -static void -Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580c; -} - -static void -Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580e; -} - -static void -Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580d; -} - -static void -Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15800; -} - -static void -Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16000; -} - -static void -Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15802; -} - -static void -Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15801; -} - -static void -Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15808; -} - -static void -Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15804; -} - -static void -Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15805; -} - -static void -Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15803; -} - -static void -Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16001; -} - -static void -Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580f; -} - -static void -Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16004; -} - -static void -Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16002; -} - -static void -Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16800; -} - -static void -Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16008; -} - -static void -Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16003; -} - -static void -Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x17000; -} - -static void -Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20007; -} - -static void -Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20002; -} - -static void -Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000c; -} - -static void -Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20003; -} - -static void -Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20005; -} - -static void -Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20000; -} - -static void -Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20009; -} - -static void -Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20004; -} - -static void -Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20006; -} - -static void -Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20001; -} - -static void -Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000a; -} - -static void -Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20008; -} - -static void -Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30008; -} - -static void -Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000e; -} - -static void -Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30006; -} - -static void -Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30001; -} - -static void -Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30002; -} - -static void -Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000b; -} - -static void -Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30003; -} - -static void -Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000f; -} - -static void -Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30004; -} - -static void -Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000d; -} - -static void -Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30005; -} - -static void -Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000; -} - -static void -Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000; -} - -static void -Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000a; -} - -static void -Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40004; -} - -static void -Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000d; -} - -static void -Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000e; -} - -static void -Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30007; -} - -static void -Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40001; -} - -static void -Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000c; -} - -static void -Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000f; -} - -static void -Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30009; -} - -static void -Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40002; -} - -static void -Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000b; -} - -static void -Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000b; -} - -static void -Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40005; -} - -static void -Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000f; -} - -static void -Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40009; -} - -static void -Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000a; -} - -static void -Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40008; -} - -static void -Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000d; -} - -static void -Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40006; -} - -static void -Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000c; -} - -static void -Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40003; -} - -static void -Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000e; -} - -static void -Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40007; -} - -static void -Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64004; -} - -static void -Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64080; -} - -static void -Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64008; -} - -static void -Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64100; -} - -static void -Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64003; -} - -static void -Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64006; -} - -static void -Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64005; -} - -static void -Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64007; -} - -static void -Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64009; -} - -static void -Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400c; -} - -static void -Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400a; -} - -static void -Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400b; -} - -static void -Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400d; -} - -static void -Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400f; -} - -static void -Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400e; -} - -static void -Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64081; -} - -static void -Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60000; -} - -static void -Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60002; -} - -static void -Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60001; -} - -static void -Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60004; -} - -static void -Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60083; -} - -static void -Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60086; -} - -static void -Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60085; -} - -static void -Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60087; -} - -static void -Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60103; -} - -static void -Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60106; -} - -static void -Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60105; -} - -static void -Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60107; -} - -static void -Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018e; -} - -static void -Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64001; -} - -static void -Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018f; -} - -static void -Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64002; -} - -static void -Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00014; -} - -static void -Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00004; -} - -static void -Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa10004; -} - -static void -Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe7e014; -} - -static void -Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca8004; -} - -static void -Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc60004; -} - -static void -Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00024; -} - -static void -Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa20004; -} - -static void -Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00004; -} - -static void -Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf01004; -} - -static void -Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf02004; -} - -static void -Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa30004; -} - -static void -Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa40004; -} - -static void -Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf11004; -} - -static void -Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00004; -} - -static void -Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe7c014; -} - -static void -Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe7d014; -} - -static void -Opcode_ae_slaasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f6008; -} - -static void -Opcode_ae_addbrba32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f7000; -} - -static void -Opcode_ae_minabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c508; -} - -static void -Opcode_ae_maxabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c580; -} - -static void -Opcode_ae_minabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x52004; -} - -static void -Opcode_ae_maxabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x52008; -} - -static void -Opcode_rur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f60; -} - -static void -Opcode_wur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f600; -} - -static void -Opcode_rur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f70; -} - -static void -Opcode_wur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f700; -} - -static void -Opcode_ae_lp24x2_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fe080; -} - -static void -Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900000; -} - -static void -Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ff000; -} - -static void -Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800000; -} - -static void -Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f4080; -} - -static void -Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0; -} - -static void -Opcode_ae_lp24_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fc080; -} - -static void -Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700000; -} - -static void -Opcode_ae_lp24f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fe000; -} - -static void -Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600000; -} - -static void -Opcode_ae_lp16f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1fc000; -} - -static void -Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ff080; -} - -static void -Opcode_ae_lq56_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00000; -} - -static void -Opcode_ae_sq56s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f8080; -} - -static void -Opcode_ae_lq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef010; -} - -static void -Opcode_ae_sq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f8040; -} - -xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { - Opcode_excw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { - Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { - Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { - Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { - Opcode_call12_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { - Opcode_call8_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { - Opcode_call4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { - Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { - Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { - Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { - Opcode_entry_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { - Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { - Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { - Opcode_retw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { - 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { - Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { - Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { - Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { - Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { - Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { - Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { - Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { - Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { - Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { - Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { - 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { - 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { - 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { - 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { - 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { - 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { - 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { - 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { - 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { - 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { - 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { - Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { - Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { - Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { - Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { - Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { - Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { - Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { - Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { - Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { - Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { - Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { - Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { - Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { - Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { - Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { - Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { - Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { - Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { - Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { - Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { - Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { - Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { - Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { - Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { - Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { - Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { - Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { - Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { - Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { - Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { - Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { - Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { - Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { - Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { - Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { - Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { - Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { - Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { - Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { - Opcode_call0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { - Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { - Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { - Opcode_ill_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { - Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { - Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { - Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { - Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { - Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { - Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { - Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { - Opcode_loop_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { - Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { - Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { - Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { - Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { - Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { - Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { - Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { - Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { - Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { - Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { - Opcode_ret_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { - Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { - Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { - Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { - Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { - Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { - Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { - Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { - Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { - Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { - Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { - Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { - Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { - Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { - Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { - Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { - Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { - Opcode_memw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { - Opcode_extw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { - Opcode_isync_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { - Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { - Opcode_esync_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { - Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { - Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { - Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { - Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { - Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { - Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { - Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { - Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { - Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { - Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { - Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { - Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { - Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { - Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { - Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { - Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { - Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { - Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { - Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { - Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_243_encode_fns[] = { - Opcode_rsr_243_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { - Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { - Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { - Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { - Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { - Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { - Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { - Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { - Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { - Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { - Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { - Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { - Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { - Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { - Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { - Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { - Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { - Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { - Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { - Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { - Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { - Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { - Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { - Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { - Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { - Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { - Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { - Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { - Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { - Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { - Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { - Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { - Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { - Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { - Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { - Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { - Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { - Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { - Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { - Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { - Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { - Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { - Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { - Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { - Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { - Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { - Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { - Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { - Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { - Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { - Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { - Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { - Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { - Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { - Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { - Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { - Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { - Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { - Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { - Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { - Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { - Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { - Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { - Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { - Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { - Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { - Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { - Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { - Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { - Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { - Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { - Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { - Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { - Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { - Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { - Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { - Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { - Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { - Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { - Opcode_mull_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = { - Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = { - Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { - Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { - Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { - Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { - Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { - Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { - Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { - Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { - Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { - Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { - Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { - Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { - Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { - Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { - Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { - Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { - Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { - Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { - Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { - Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { - Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { - Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { - Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { - Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { - Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { - Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { - Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { - Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { - Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { - Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { - Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { - Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { - Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { - Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { - Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { - Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { - Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { - Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { - Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { - Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { - Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { - Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { - Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { - Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { - Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { - Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { - Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { - Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { - Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { - Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { - Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { - Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { - Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { - Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { - Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { - Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { - Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { - Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { - Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { - Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { - Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { - Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { - Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { - Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { - Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { - Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { - Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { - Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { - Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { - Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { - Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { - Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { - Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { - Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { - Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { - Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { - Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { - Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { - Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { - Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { - Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { - Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { - Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { - Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { - Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { - Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { - Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { - Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { - Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { - Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { - Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { - Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { - Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { - Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { - Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { - Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { - Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { - Opcode_break_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { - 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { - Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { - Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { - Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { - Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { - Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { - Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { - Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { - Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { - Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { - Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { - Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { - Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { - Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { - Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { - Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { - Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { - Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { - Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { - Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { - Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { - Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { - Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { - Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { - Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { - Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { - Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { - Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { - Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { - Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { - Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { - Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { - Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { - Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { - Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { - Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { - Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { - Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { - Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { - Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { - Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { - Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { - Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { - Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { - Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { - Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { - Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { - Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { - Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { - Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { - Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { - Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { - Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { - Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { - Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { - Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { - Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { - Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { - Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { - Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { - Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { - Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { - Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { - Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { - Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { - Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { - Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { - Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { - Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { - Opcode_iii_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { - Opcode_lict_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { - Opcode_licw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { - Opcode_sict_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { - Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { - Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { - Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { - Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { - Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { - Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { - Opcode_dii_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { - Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { - Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { - Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { - Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { - Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { - Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { - Opcode_diu_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { - Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { - Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_prefctl_encode_fns[] = { - Opcode_rsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_prefctl_encode_fns[] = { - Opcode_wsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_prefctl_encode_fns[] = { - Opcode_xsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { - Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { - Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { - Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { - Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { - Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { - Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { - Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { - Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { - Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { - Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { - Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { - Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { - Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { - Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { - Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { - Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { - Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { - Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { - Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { - Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { - Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { - Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { - Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { - Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { - Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { - Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { - Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { - Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { - Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { - Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { - Opcode_rer_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { - Opcode_wer_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { - Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { - Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { - Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { - Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { - Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { - Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = { - Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = { - Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { - Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { - Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { - Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { - Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { - Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { - Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { - Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { - Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { - Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { - Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { - Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { - Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { - Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { - Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { - Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { - Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = { - Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = { - Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = { - Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = { - Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = { - Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = { - Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = { - Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = { - Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = { - Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = { - Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = { - Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = { - Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = { - Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = { - Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = { - Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = { - Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = { - Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = { - Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = { - Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = { - Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = { - Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = { - Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = { - Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = { - Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = { - Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = { - Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = { - Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = { - Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = { - Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = { - Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = { - Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = { - Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = { - Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = { - Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = { - Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = { - Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = { - Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = { - Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = { - Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = { - Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = { - Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = { - Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = { - Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = { - Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = { - Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = { - Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = { - Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = { - Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = { - Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = { - Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = { - Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = { - Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = { - Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = { - Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = { - Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = { - Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = { - Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = { - Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = { - Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = { - Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = { - Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = { - Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = { - Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = { - Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = { - 0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = { - Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, Opcode_ae_selp24_ll_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, Opcode_ae_selp24_lh_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, Opcode_ae_selp24_hl_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, Opcode_ae_selp24_hh_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = { - Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { - Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = { - Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = { - Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { - Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { - Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { - Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { - Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = { - Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = { - Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = { - Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = { - Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = { - 0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { - Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = { - Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = { - Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { - Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { - Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = { - Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = { - Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = { - Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = { - Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { - Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { - Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = { - Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { - Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { - Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = { - Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = { - Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = { - Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = { - Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { - Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { - Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { - Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { - Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { - Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { - Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { - Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { - Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { - Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { - Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { - Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { - Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { - Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { - Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { - Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { - Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { - Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_slaasq56s_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_addbrba32_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_minabssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minabssp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxabssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxabssp24s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_minabssq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minabssq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_maxabssq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxabssq56s_Slot_ae_slot1_encode, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_cbegin0_encode_fns[] = { - Opcode_rur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_cbegin0_encode_fns[] = { - Opcode_wur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_rur_ae_cend0_encode_fns[] = { - Opcode_rur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_wur_ae_cend0_encode_fns[] = { - Opcode_wur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0 -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24x2_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp24f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lp16f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp16f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq56_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lq56_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq56s_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sq56s_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_lq32f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lq32f_c_Slot_ae_slot0_encode -}; - -xtensa_opcode_encode_fn Opcode_ae_sq32f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sq32f_c_Slot_ae_slot0_encode -}; - - -/* Opcode table. */ - -static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 4 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 4 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 3 }, - { FUNCUNIT_ae_shift32x5, 4 }, - { FUNCUNIT_ae_add32, 4 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 3 }, - { FUNCUNIT_ae_shift32x5, 4 }, - { FUNCUNIT_ae_add32, 4 } -}; - -static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 3 }, - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 3 }, - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 4 } -}; - -static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 4 } -}; - -static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 3 }, - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 3 }, - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 3 }, - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 3 }, - { FUNCUNIT_ae_subshift, 3 } -}; - -static xtensa_opcode_internal opcodes[] = { - { "excw", ICLASS_xt_iclass_excw, - 0, - Opcode_excw_encode_fns, 0, 0 }, - { "rfe", ICLASS_xt_iclass_rfe, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfe_encode_fns, 0, 0 }, - { "rfde", ICLASS_xt_iclass_rfde, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfde_encode_fns, 0, 0 }, - { "syscall", ICLASS_xt_iclass_syscall, - 0, - Opcode_syscall_encode_fns, 0, 0 }, - { "call12", ICLASS_xt_iclass_call12, - XTENSA_OPCODE_IS_CALL, - Opcode_call12_encode_fns, 0, 0 }, - { "call8", ICLASS_xt_iclass_call8, - XTENSA_OPCODE_IS_CALL, - Opcode_call8_encode_fns, 0, 0 }, - { "call4", ICLASS_xt_iclass_call4, - XTENSA_OPCODE_IS_CALL, - Opcode_call4_encode_fns, 0, 0 }, - { "callx12", ICLASS_xt_iclass_callx12, - XTENSA_OPCODE_IS_CALL, - Opcode_callx12_encode_fns, 0, 0 }, - { "callx8", ICLASS_xt_iclass_callx8, - XTENSA_OPCODE_IS_CALL, - Opcode_callx8_encode_fns, 0, 0 }, - { "callx4", ICLASS_xt_iclass_callx4, - XTENSA_OPCODE_IS_CALL, - Opcode_callx4_encode_fns, 0, 0 }, - { "entry", ICLASS_xt_iclass_entry, - 0, - Opcode_entry_encode_fns, 0, 0 }, - { "movsp", ICLASS_xt_iclass_movsp, - 0, - Opcode_movsp_encode_fns, 0, 0 }, - { "rotw", ICLASS_xt_iclass_rotw, - 0, - Opcode_rotw_encode_fns, 0, 0 }, - { "retw", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_encode_fns, 0, 0 }, - { "retw.n", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_n_encode_fns, 0, 0 }, - { "rfwo", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwo_encode_fns, 0, 0 }, - { "rfwu", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwu_encode_fns, 0, 0 }, - { "l32e", ICLASS_xt_iclass_l32e, - 0, - Opcode_l32e_encode_fns, 0, 0 }, - { "s32e", ICLASS_xt_iclass_s32e, - 0, - Opcode_s32e_encode_fns, 0, 0 }, - { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, - 0, - Opcode_rsr_windowbase_encode_fns, 0, 0 }, - { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, - 0, - Opcode_wsr_windowbase_encode_fns, 0, 0 }, - { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, - 0, - Opcode_xsr_windowbase_encode_fns, 0, 0 }, - { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, - 0, - Opcode_rsr_windowstart_encode_fns, 0, 0 }, - { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, - 0, - Opcode_wsr_windowstart_encode_fns, 0, 0 }, - { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, - 0, - Opcode_xsr_windowstart_encode_fns, 0, 0 }, - { "add.n", ICLASS_xt_iclass_add_n, - 0, - Opcode_add_n_encode_fns, 0, 0 }, - { "addi.n", ICLASS_xt_iclass_addi_n, - 0, - Opcode_addi_n_encode_fns, 0, 0 }, - { "beqz.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_n_encode_fns, 0, 0 }, - { "bnez.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_n_encode_fns, 0, 0 }, - { "ill.n", ICLASS_xt_iclass_ill_n, - 0, - Opcode_ill_n_encode_fns, 0, 0 }, - { "l32i.n", ICLASS_xt_iclass_loadi4, - 0, - Opcode_l32i_n_encode_fns, 0, 0 }, - { "mov.n", ICLASS_xt_iclass_mov_n, - 0, - Opcode_mov_n_encode_fns, 0, 0 }, - { "movi.n", ICLASS_xt_iclass_movi_n, - 0, - Opcode_movi_n_encode_fns, 0, 0 }, - { "nop.n", ICLASS_xt_iclass_nopn, - 0, - Opcode_nop_n_encode_fns, 0, 0 }, - { "ret.n", ICLASS_xt_iclass_retn, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_n_encode_fns, 0, 0 }, - { "s32i.n", ICLASS_xt_iclass_storei4, - 0, - Opcode_s32i_n_encode_fns, 0, 0 }, - { "rur.threadptr", ICLASS_rur_threadptr, - 0, - Opcode_rur_threadptr_encode_fns, 0, 0 }, - { "wur.threadptr", ICLASS_wur_threadptr, - 0, - Opcode_wur_threadptr_encode_fns, 0, 0 }, - { "addi", ICLASS_xt_iclass_addi, - 0, - Opcode_addi_encode_fns, 0, 0 }, - { "addmi", ICLASS_xt_iclass_addmi, - 0, - Opcode_addmi_encode_fns, 0, 0 }, - { "add", ICLASS_xt_iclass_addsub, - 0, - Opcode_add_encode_fns, 0, 0 }, - { "sub", ICLASS_xt_iclass_addsub, - 0, - Opcode_sub_encode_fns, 0, 0 }, - { "addx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx2_encode_fns, 0, 0 }, - { "addx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx4_encode_fns, 0, 0 }, - { "addx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx8_encode_fns, 0, 0 }, - { "subx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx2_encode_fns, 0, 0 }, - { "subx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx4_encode_fns, 0, 0 }, - { "subx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx8_encode_fns, 0, 0 }, - { "and", ICLASS_xt_iclass_bit, - 0, - Opcode_and_encode_fns, 0, 0 }, - { "or", ICLASS_xt_iclass_bit, - 0, - Opcode_or_encode_fns, 0, 0 }, - { "xor", ICLASS_xt_iclass_bit, - 0, - Opcode_xor_encode_fns, 0, 0 }, - { "beqi", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqi_encode_fns, 0, 0 }, - { "bnei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnei_encode_fns, 0, 0 }, - { "bgei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgei_encode_fns, 0, 0 }, - { "blti", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blti_encode_fns, 0, 0 }, - { "bbci", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbci_encode_fns, 0, 0 }, - { "bbsi", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbsi_encode_fns, 0, 0 }, - { "bgeui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeui_encode_fns, 0, 0 }, - { "bltui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltui_encode_fns, 0, 0 }, - { "beq", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beq_encode_fns, 0, 0 }, - { "bne", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bne_encode_fns, 0, 0 }, - { "bge", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bge_encode_fns, 0, 0 }, - { "blt", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blt_encode_fns, 0, 0 }, - { "bgeu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeu_encode_fns, 0, 0 }, - { "bltu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltu_encode_fns, 0, 0 }, - { "bany", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bany_encode_fns, 0, 0 }, - { "bnone", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnone_encode_fns, 0, 0 }, - { "ball", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_ball_encode_fns, 0, 0 }, - { "bnall", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnall_encode_fns, 0, 0 }, - { "bbc", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbc_encode_fns, 0, 0 }, - { "bbs", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbs_encode_fns, 0, 0 }, - { "beqz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_encode_fns, 0, 0 }, - { "bnez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_encode_fns, 0, 0 }, - { "bgez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgez_encode_fns, 0, 0 }, - { "bltz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltz_encode_fns, 0, 0 }, - { "call0", ICLASS_xt_iclass_call0, - XTENSA_OPCODE_IS_CALL, - Opcode_call0_encode_fns, 0, 0 }, - { "callx0", ICLASS_xt_iclass_callx0, - XTENSA_OPCODE_IS_CALL, - Opcode_callx0_encode_fns, 0, 0 }, - { "extui", ICLASS_xt_iclass_exti, - 0, - Opcode_extui_encode_fns, 0, 0 }, - { "ill", ICLASS_xt_iclass_ill, - 0, - Opcode_ill_encode_fns, 0, 0 }, - { "j", ICLASS_xt_iclass_jump, - XTENSA_OPCODE_IS_JUMP, - Opcode_j_encode_fns, 0, 0 }, - { "jx", ICLASS_xt_iclass_jumpx, - XTENSA_OPCODE_IS_JUMP, - Opcode_jx_encode_fns, 0, 0 }, - { "l16ui", ICLASS_xt_iclass_l16ui, - 0, - Opcode_l16ui_encode_fns, 0, 0 }, - { "l16si", ICLASS_xt_iclass_l16si, - 0, - Opcode_l16si_encode_fns, 0, 0 }, - { "l32i", ICLASS_xt_iclass_l32i, - 0, - Opcode_l32i_encode_fns, 0, 0 }, - { "l32r", ICLASS_xt_iclass_l32r, - 0, - Opcode_l32r_encode_fns, 0, 0 }, - { "l8ui", ICLASS_xt_iclass_l8i, - 0, - Opcode_l8ui_encode_fns, 0, 0 }, - { "loop", ICLASS_xt_iclass_loop, - XTENSA_OPCODE_IS_LOOP, - Opcode_loop_encode_fns, 0, 0 }, - { "loopnez", ICLASS_xt_iclass_loopz, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopnez_encode_fns, 0, 0 }, - { "loopgtz", ICLASS_xt_iclass_loopz, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopgtz_encode_fns, 0, 0 }, - { "movi", ICLASS_xt_iclass_movi, - 0, - Opcode_movi_encode_fns, 0, 0 }, - { "moveqz", ICLASS_xt_iclass_movz, - 0, - Opcode_moveqz_encode_fns, 0, 0 }, - { "movnez", ICLASS_xt_iclass_movz, - 0, - Opcode_movnez_encode_fns, 0, 0 }, - { "movltz", ICLASS_xt_iclass_movz, - 0, - Opcode_movltz_encode_fns, 0, 0 }, - { "movgez", ICLASS_xt_iclass_movz, - 0, - Opcode_movgez_encode_fns, 0, 0 }, - { "neg", ICLASS_xt_iclass_neg, - 0, - Opcode_neg_encode_fns, 0, 0 }, - { "abs", ICLASS_xt_iclass_neg, - 0, - Opcode_abs_encode_fns, 0, 0 }, - { "nop", ICLASS_xt_iclass_nop, - 0, - Opcode_nop_encode_fns, 0, 0 }, - { "ret", ICLASS_xt_iclass_return, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_encode_fns, 0, 0 }, - { "simcall", ICLASS_xt_iclass_simcall, - 0, - Opcode_simcall_encode_fns, 0, 0 }, - { "s16i", ICLASS_xt_iclass_s16i, - 0, - Opcode_s16i_encode_fns, 0, 0 }, - { "s32i", ICLASS_xt_iclass_s32i, - 0, - Opcode_s32i_encode_fns, 0, 0 }, - { "s8i", ICLASS_xt_iclass_s8i, - 0, - Opcode_s8i_encode_fns, 0, 0 }, - { "ssr", ICLASS_xt_iclass_sar, - 0, - Opcode_ssr_encode_fns, 0, 0 }, - { "ssl", ICLASS_xt_iclass_sar, - 0, - Opcode_ssl_encode_fns, 0, 0 }, - { "ssa8l", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8l_encode_fns, 0, 0 }, - { "ssa8b", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8b_encode_fns, 0, 0 }, - { "ssai", ICLASS_xt_iclass_sari, - 0, - Opcode_ssai_encode_fns, 0, 0 }, - { "sll", ICLASS_xt_iclass_shifts, - 0, - Opcode_sll_encode_fns, 0, 0 }, - { "src", ICLASS_xt_iclass_shiftst, - 0, - Opcode_src_encode_fns, 0, 0 }, - { "srl", ICLASS_xt_iclass_shiftt, - 0, - Opcode_srl_encode_fns, 0, 0 }, - { "sra", ICLASS_xt_iclass_shiftt, - 0, - Opcode_sra_encode_fns, 0, 0 }, - { "slli", ICLASS_xt_iclass_slli, - 0, - Opcode_slli_encode_fns, 0, 0 }, - { "srai", ICLASS_xt_iclass_srai, - 0, - Opcode_srai_encode_fns, 0, 0 }, - { "srli", ICLASS_xt_iclass_srli, - 0, - Opcode_srli_encode_fns, 0, 0 }, - { "memw", ICLASS_xt_iclass_memw, - 0, - Opcode_memw_encode_fns, 0, 0 }, - { "extw", ICLASS_xt_iclass_extw, - 0, - Opcode_extw_encode_fns, 0, 0 }, - { "isync", ICLASS_xt_iclass_isync, - 0, - Opcode_isync_encode_fns, 0, 0 }, - { "rsync", ICLASS_xt_iclass_sync, - 0, - Opcode_rsync_encode_fns, 0, 0 }, - { "esync", ICLASS_xt_iclass_sync, - 0, - Opcode_esync_encode_fns, 0, 0 }, - { "dsync", ICLASS_xt_iclass_sync, - 0, - Opcode_dsync_encode_fns, 0, 0 }, - { "rsil", ICLASS_xt_iclass_rsil, - 0, - Opcode_rsil_encode_fns, 0, 0 }, - { "rsr.lend", ICLASS_xt_iclass_rsr_lend, - 0, - Opcode_rsr_lend_encode_fns, 0, 0 }, - { "wsr.lend", ICLASS_xt_iclass_wsr_lend, - 0, - Opcode_wsr_lend_encode_fns, 0, 0 }, - { "xsr.lend", ICLASS_xt_iclass_xsr_lend, - 0, - Opcode_xsr_lend_encode_fns, 0, 0 }, - { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, - 0, - Opcode_rsr_lcount_encode_fns, 0, 0 }, - { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, - 0, - Opcode_wsr_lcount_encode_fns, 0, 0 }, - { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, - 0, - Opcode_xsr_lcount_encode_fns, 0, 0 }, - { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, - 0, - Opcode_rsr_lbeg_encode_fns, 0, 0 }, - { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, - 0, - Opcode_wsr_lbeg_encode_fns, 0, 0 }, - { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, - 0, - Opcode_xsr_lbeg_encode_fns, 0, 0 }, - { "rsr.sar", ICLASS_xt_iclass_rsr_sar, - 0, - Opcode_rsr_sar_encode_fns, 0, 0 }, - { "wsr.sar", ICLASS_xt_iclass_wsr_sar, - 0, - Opcode_wsr_sar_encode_fns, 0, 0 }, - { "xsr.sar", ICLASS_xt_iclass_xsr_sar, - 0, - Opcode_xsr_sar_encode_fns, 0, 0 }, - { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, - 0, - Opcode_rsr_litbase_encode_fns, 0, 0 }, - { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, - 0, - Opcode_wsr_litbase_encode_fns, 0, 0 }, - { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, - 0, - Opcode_xsr_litbase_encode_fns, 0, 0 }, - { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, - 0, - Opcode_rsr_configid0_encode_fns, 0, 0 }, - { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, - 0, - Opcode_wsr_configid0_encode_fns, 0, 0 }, - { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, - 0, - Opcode_rsr_configid1_encode_fns, 0, 0 }, - { "rsr.243", ICLASS_xt_iclass_rsr_243, - 0, - Opcode_rsr_243_encode_fns, 0, 0 }, - { "rsr.ps", ICLASS_xt_iclass_rsr_ps, - 0, - Opcode_rsr_ps_encode_fns, 0, 0 }, - { "wsr.ps", ICLASS_xt_iclass_wsr_ps, - 0, - Opcode_wsr_ps_encode_fns, 0, 0 }, - { "xsr.ps", ICLASS_xt_iclass_xsr_ps, - 0, - Opcode_xsr_ps_encode_fns, 0, 0 }, - { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, - 0, - Opcode_rsr_epc1_encode_fns, 0, 0 }, - { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, - 0, - Opcode_wsr_epc1_encode_fns, 0, 0 }, - { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, - 0, - Opcode_xsr_epc1_encode_fns, 0, 0 }, - { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, - 0, - Opcode_rsr_excsave1_encode_fns, 0, 0 }, - { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, - 0, - Opcode_wsr_excsave1_encode_fns, 0, 0 }, - { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, - 0, - Opcode_xsr_excsave1_encode_fns, 0, 0 }, - { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, - 0, - Opcode_rsr_epc2_encode_fns, 0, 0 }, - { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, - 0, - Opcode_wsr_epc2_encode_fns, 0, 0 }, - { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, - 0, - Opcode_xsr_epc2_encode_fns, 0, 0 }, - { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, - 0, - Opcode_rsr_excsave2_encode_fns, 0, 0 }, - { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, - 0, - Opcode_wsr_excsave2_encode_fns, 0, 0 }, - { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, - 0, - Opcode_xsr_excsave2_encode_fns, 0, 0 }, - { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, - 0, - Opcode_rsr_epc3_encode_fns, 0, 0 }, - { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, - 0, - Opcode_wsr_epc3_encode_fns, 0, 0 }, - { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, - 0, - Opcode_xsr_epc3_encode_fns, 0, 0 }, - { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, - 0, - Opcode_rsr_excsave3_encode_fns, 0, 0 }, - { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, - 0, - Opcode_wsr_excsave3_encode_fns, 0, 0 }, - { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, - 0, - Opcode_xsr_excsave3_encode_fns, 0, 0 }, - { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, - 0, - Opcode_rsr_epc4_encode_fns, 0, 0 }, - { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, - 0, - Opcode_wsr_epc4_encode_fns, 0, 0 }, - { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, - 0, - Opcode_xsr_epc4_encode_fns, 0, 0 }, - { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, - 0, - Opcode_rsr_excsave4_encode_fns, 0, 0 }, - { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, - 0, - Opcode_wsr_excsave4_encode_fns, 0, 0 }, - { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, - 0, - Opcode_xsr_excsave4_encode_fns, 0, 0 }, - { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, - 0, - Opcode_rsr_epc5_encode_fns, 0, 0 }, - { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, - 0, - Opcode_wsr_epc5_encode_fns, 0, 0 }, - { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, - 0, - Opcode_xsr_epc5_encode_fns, 0, 0 }, - { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, - 0, - Opcode_rsr_excsave5_encode_fns, 0, 0 }, - { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, - 0, - Opcode_wsr_excsave5_encode_fns, 0, 0 }, - { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, - 0, - Opcode_xsr_excsave5_encode_fns, 0, 0 }, - { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, - 0, - Opcode_rsr_epc6_encode_fns, 0, 0 }, - { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, - 0, - Opcode_wsr_epc6_encode_fns, 0, 0 }, - { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, - 0, - Opcode_xsr_epc6_encode_fns, 0, 0 }, - { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, - 0, - Opcode_rsr_excsave6_encode_fns, 0, 0 }, - { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, - 0, - Opcode_wsr_excsave6_encode_fns, 0, 0 }, - { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, - 0, - Opcode_xsr_excsave6_encode_fns, 0, 0 }, - { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, - 0, - Opcode_rsr_epc7_encode_fns, 0, 0 }, - { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, - 0, - Opcode_wsr_epc7_encode_fns, 0, 0 }, - { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, - 0, - Opcode_xsr_epc7_encode_fns, 0, 0 }, - { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, - 0, - Opcode_rsr_excsave7_encode_fns, 0, 0 }, - { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, - 0, - Opcode_wsr_excsave7_encode_fns, 0, 0 }, - { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, - 0, - Opcode_xsr_excsave7_encode_fns, 0, 0 }, - { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, - 0, - Opcode_rsr_eps2_encode_fns, 0, 0 }, - { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, - 0, - Opcode_wsr_eps2_encode_fns, 0, 0 }, - { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, - 0, - Opcode_xsr_eps2_encode_fns, 0, 0 }, - { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, - 0, - Opcode_rsr_eps3_encode_fns, 0, 0 }, - { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, - 0, - Opcode_wsr_eps3_encode_fns, 0, 0 }, - { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, - 0, - Opcode_xsr_eps3_encode_fns, 0, 0 }, - { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, - 0, - Opcode_rsr_eps4_encode_fns, 0, 0 }, - { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, - 0, - Opcode_wsr_eps4_encode_fns, 0, 0 }, - { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, - 0, - Opcode_xsr_eps4_encode_fns, 0, 0 }, - { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, - 0, - Opcode_rsr_eps5_encode_fns, 0, 0 }, - { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, - 0, - Opcode_wsr_eps5_encode_fns, 0, 0 }, - { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, - 0, - Opcode_xsr_eps5_encode_fns, 0, 0 }, - { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, - 0, - Opcode_rsr_eps6_encode_fns, 0, 0 }, - { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, - 0, - Opcode_wsr_eps6_encode_fns, 0, 0 }, - { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, - 0, - Opcode_xsr_eps6_encode_fns, 0, 0 }, - { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, - 0, - Opcode_rsr_eps7_encode_fns, 0, 0 }, - { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, - 0, - Opcode_wsr_eps7_encode_fns, 0, 0 }, - { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, - 0, - Opcode_xsr_eps7_encode_fns, 0, 0 }, - { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, - 0, - Opcode_rsr_excvaddr_encode_fns, 0, 0 }, - { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, - 0, - Opcode_wsr_excvaddr_encode_fns, 0, 0 }, - { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, - 0, - Opcode_xsr_excvaddr_encode_fns, 0, 0 }, - { "rsr.depc", ICLASS_xt_iclass_rsr_depc, - 0, - Opcode_rsr_depc_encode_fns, 0, 0 }, - { "wsr.depc", ICLASS_xt_iclass_wsr_depc, - 0, - Opcode_wsr_depc_encode_fns, 0, 0 }, - { "xsr.depc", ICLASS_xt_iclass_xsr_depc, - 0, - Opcode_xsr_depc_encode_fns, 0, 0 }, - { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, - 0, - Opcode_rsr_exccause_encode_fns, 0, 0 }, - { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, - 0, - Opcode_wsr_exccause_encode_fns, 0, 0 }, - { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, - 0, - Opcode_xsr_exccause_encode_fns, 0, 0 }, - { "rsr.prid", ICLASS_xt_iclass_rsr_prid, - 0, - Opcode_rsr_prid_encode_fns, 0, 0 }, - { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, - 0, - Opcode_rsr_vecbase_encode_fns, 0, 0 }, - { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, - 0, - Opcode_wsr_vecbase_encode_fns, 0, 0 }, - { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, - 0, - Opcode_xsr_vecbase_encode_fns, 0, 0 }, - { "mul16u", ICLASS_xt_mul16, - 0, - Opcode_mul16u_encode_fns, 0, 0 }, - { "mul16s", ICLASS_xt_mul16, - 0, - Opcode_mul16s_encode_fns, 0, 0 }, - { "mull", ICLASS_xt_mul32, - 0, - Opcode_mull_encode_fns, 0, 0 }, - { "muluh", ICLASS_xt_mul32h, - 0, - Opcode_muluh_encode_fns, 0, 0 }, - { "mulsh", ICLASS_xt_mul32h, - 0, - Opcode_mulsh_encode_fns, 0, 0 }, - { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_ll_encode_fns, 0, 0 }, - { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_hl_encode_fns, 0, 0 }, - { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_lh_encode_fns, 0, 0 }, - { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_hh_encode_fns, 0, 0 }, - { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_ll_encode_fns, 0, 0 }, - { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_hl_encode_fns, 0, 0 }, - { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_lh_encode_fns, 0, 0 }, - { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_hh_encode_fns, 0, 0 }, - { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_ll_encode_fns, 0, 0 }, - { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_hl_encode_fns, 0, 0 }, - { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_lh_encode_fns, 0, 0 }, - { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_hh_encode_fns, 0, 0 }, - { "mul.da.ll", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_ll_encode_fns, 0, 0 }, - { "mul.da.hl", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_hl_encode_fns, 0, 0 }, - { "mul.da.lh", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_lh_encode_fns, 0, 0 }, - { "mul.da.hh", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_hh_encode_fns, 0, 0 }, - { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_ll_encode_fns, 0, 0 }, - { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_hl_encode_fns, 0, 0 }, - { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_lh_encode_fns, 0, 0 }, - { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_hh_encode_fns, 0, 0 }, - { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_ll_encode_fns, 0, 0 }, - { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_hl_encode_fns, 0, 0 }, - { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_lh_encode_fns, 0, 0 }, - { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_hh_encode_fns, 0, 0 }, - { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_ll_encode_fns, 0, 0 }, - { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_hl_encode_fns, 0, 0 }, - { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_lh_encode_fns, 0, 0 }, - { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_hh_encode_fns, 0, 0 }, - { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_ll_encode_fns, 0, 0 }, - { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_hl_encode_fns, 0, 0 }, - { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_lh_encode_fns, 0, 0 }, - { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_hh_encode_fns, 0, 0 }, - { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_ll_encode_fns, 0, 0 }, - { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_hl_encode_fns, 0, 0 }, - { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_lh_encode_fns, 0, 0 }, - { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_hh_encode_fns, 0, 0 }, - { "mula.da.ll", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_ll_encode_fns, 0, 0 }, - { "mula.da.hl", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_hl_encode_fns, 0, 0 }, - { "mula.da.lh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_lh_encode_fns, 0, 0 }, - { "mula.da.hh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_hh_encode_fns, 0, 0 }, - { "muls.da.ll", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_ll_encode_fns, 0, 0 }, - { "muls.da.hl", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_hl_encode_fns, 0, 0 }, - { "muls.da.lh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_lh_encode_fns, 0, 0 }, - { "muls.da.hh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_hh_encode_fns, 0, 0 }, - { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_ll_encode_fns, 0, 0 }, - { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_hl_encode_fns, 0, 0 }, - { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_lh_encode_fns, 0, 0 }, - { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_hh_encode_fns, 0, 0 }, - { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_ll_encode_fns, 0, 0 }, - { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_hl_encode_fns, 0, 0 }, - { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_lh_encode_fns, 0, 0 }, - { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_hh_encode_fns, 0, 0 }, - { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, - { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, - { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, - { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, - { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, - { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, - { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, - { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, - { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, - { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, - { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, - { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, - { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, - { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, - { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, - { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, - { "lddec", ICLASS_xt_iclass_mac16_l, - 0, - Opcode_lddec_encode_fns, 0, 0 }, - { "ldinc", ICLASS_xt_iclass_mac16_l, - 0, - Opcode_ldinc_encode_fns, 0, 0 }, - { "rsr.m0", ICLASS_xt_iclass_rsr_m0, - 0, - Opcode_rsr_m0_encode_fns, 0, 0 }, - { "wsr.m0", ICLASS_xt_iclass_wsr_m0, - 0, - Opcode_wsr_m0_encode_fns, 0, 0 }, - { "xsr.m0", ICLASS_xt_iclass_xsr_m0, - 0, - Opcode_xsr_m0_encode_fns, 0, 0 }, - { "rsr.m1", ICLASS_xt_iclass_rsr_m1, - 0, - Opcode_rsr_m1_encode_fns, 0, 0 }, - { "wsr.m1", ICLASS_xt_iclass_wsr_m1, - 0, - Opcode_wsr_m1_encode_fns, 0, 0 }, - { "xsr.m1", ICLASS_xt_iclass_xsr_m1, - 0, - Opcode_xsr_m1_encode_fns, 0, 0 }, - { "rsr.m2", ICLASS_xt_iclass_rsr_m2, - 0, - Opcode_rsr_m2_encode_fns, 0, 0 }, - { "wsr.m2", ICLASS_xt_iclass_wsr_m2, - 0, - Opcode_wsr_m2_encode_fns, 0, 0 }, - { "xsr.m2", ICLASS_xt_iclass_xsr_m2, - 0, - Opcode_xsr_m2_encode_fns, 0, 0 }, - { "rsr.m3", ICLASS_xt_iclass_rsr_m3, - 0, - Opcode_rsr_m3_encode_fns, 0, 0 }, - { "wsr.m3", ICLASS_xt_iclass_wsr_m3, - 0, - Opcode_wsr_m3_encode_fns, 0, 0 }, - { "xsr.m3", ICLASS_xt_iclass_xsr_m3, - 0, - Opcode_xsr_m3_encode_fns, 0, 0 }, - { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo, - 0, - Opcode_rsr_acclo_encode_fns, 0, 0 }, - { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo, - 0, - Opcode_wsr_acclo_encode_fns, 0, 0 }, - { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo, - 0, - Opcode_xsr_acclo_encode_fns, 0, 0 }, - { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi, - 0, - Opcode_rsr_acchi_encode_fns, 0, 0 }, - { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi, - 0, - Opcode_wsr_acchi_encode_fns, 0, 0 }, - { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi, - 0, - Opcode_xsr_acchi_encode_fns, 0, 0 }, - { "rfi", ICLASS_xt_iclass_rfi, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfi_encode_fns, 0, 0 }, - { "waiti", ICLASS_xt_iclass_wait, - 0, - Opcode_waiti_encode_fns, 0, 0 }, - { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, - 0, - Opcode_rsr_interrupt_encode_fns, 0, 0 }, - { "wsr.intset", ICLASS_xt_iclass_wsr_intset, - 0, - Opcode_wsr_intset_encode_fns, 0, 0 }, - { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, - 0, - Opcode_wsr_intclear_encode_fns, 0, 0 }, - { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, - 0, - Opcode_rsr_intenable_encode_fns, 0, 0 }, - { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, - 0, - Opcode_wsr_intenable_encode_fns, 0, 0 }, - { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, - 0, - Opcode_xsr_intenable_encode_fns, 0, 0 }, - { "break", ICLASS_xt_iclass_break, - 0, - Opcode_break_encode_fns, 0, 0 }, - { "break.n", ICLASS_xt_iclass_break_n, - 0, - Opcode_break_n_encode_fns, 0, 0 }, - { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, - 0, - Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, - { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, - 0, - Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, - { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, - 0, - Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, - { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, - 0, - Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, - { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, - 0, - Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, - { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, - 0, - Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, - { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, - 0, - Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, - { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, - 0, - Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, - { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, - 0, - Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, - { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, - 0, - Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, - { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, - 0, - Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, - { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, - 0, - Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, - { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, - 0, - Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, - { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, - 0, - Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, - { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, - 0, - Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, - { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, - 0, - Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, - { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, - 0, - Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, - { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, - 0, - Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, - { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, - 0, - Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, - { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, - 0, - Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, - { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, - 0, - Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, - { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, - 0, - Opcode_rsr_debugcause_encode_fns, 0, 0 }, - { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, - 0, - Opcode_wsr_debugcause_encode_fns, 0, 0 }, - { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, - 0, - Opcode_xsr_debugcause_encode_fns, 0, 0 }, - { "rsr.icount", ICLASS_xt_iclass_rsr_icount, - 0, - Opcode_rsr_icount_encode_fns, 0, 0 }, - { "wsr.icount", ICLASS_xt_iclass_wsr_icount, - 0, - Opcode_wsr_icount_encode_fns, 0, 0 }, - { "xsr.icount", ICLASS_xt_iclass_xsr_icount, - 0, - Opcode_xsr_icount_encode_fns, 0, 0 }, - { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, - 0, - Opcode_rsr_icountlevel_encode_fns, 0, 0 }, - { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, - 0, - Opcode_wsr_icountlevel_encode_fns, 0, 0 }, - { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, - 0, - Opcode_xsr_icountlevel_encode_fns, 0, 0 }, - { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, - 0, - Opcode_rsr_ddr_encode_fns, 0, 0 }, - { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, - 0, - Opcode_wsr_ddr_encode_fns, 0, 0 }, - { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, - 0, - Opcode_xsr_ddr_encode_fns, 0, 0 }, - { "rfdo", ICLASS_xt_iclass_rfdo, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdo_encode_fns, 0, 0 }, - { "rfdd", ICLASS_xt_iclass_rfdd, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdd_encode_fns, 0, 0 }, - { "andb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_andb_encode_fns, 0, 0 }, - { "andbc", ICLASS_xt_iclass_bbool1, - 0, - Opcode_andbc_encode_fns, 0, 0 }, - { "orb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_orb_encode_fns, 0, 0 }, - { "orbc", ICLASS_xt_iclass_bbool1, - 0, - Opcode_orbc_encode_fns, 0, 0 }, - { "xorb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_xorb_encode_fns, 0, 0 }, - { "any4", ICLASS_xt_iclass_bbool4, - 0, - Opcode_any4_encode_fns, 0, 0 }, - { "all4", ICLASS_xt_iclass_bbool4, - 0, - Opcode_all4_encode_fns, 0, 0 }, - { "any8", ICLASS_xt_iclass_bbool8, - 0, - Opcode_any8_encode_fns, 0, 0 }, - { "all8", ICLASS_xt_iclass_bbool8, - 0, - Opcode_all8_encode_fns, 0, 0 }, - { "bf", ICLASS_xt_iclass_bbranch, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bf_encode_fns, 0, 0 }, - { "bt", ICLASS_xt_iclass_bbranch, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bt_encode_fns, 0, 0 }, - { "movf", ICLASS_xt_iclass_bmove, - 0, - Opcode_movf_encode_fns, 0, 0 }, - { "movt", ICLASS_xt_iclass_bmove, - 0, - Opcode_movt_encode_fns, 0, 0 }, - { "rsr.br", ICLASS_xt_iclass_RSR_BR, - 0, - Opcode_rsr_br_encode_fns, 0, 0 }, - { "wsr.br", ICLASS_xt_iclass_WSR_BR, - 0, - Opcode_wsr_br_encode_fns, 0, 0 }, - { "xsr.br", ICLASS_xt_iclass_XSR_BR, - 0, - Opcode_xsr_br_encode_fns, 0, 0 }, - { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, - 0, - Opcode_rsr_ccount_encode_fns, 0, 0 }, - { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, - 0, - Opcode_wsr_ccount_encode_fns, 0, 0 }, - { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, - 0, - Opcode_xsr_ccount_encode_fns, 0, 0 }, - { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, - 0, - Opcode_rsr_ccompare0_encode_fns, 0, 0 }, - { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, - 0, - Opcode_wsr_ccompare0_encode_fns, 0, 0 }, - { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, - 0, - Opcode_xsr_ccompare0_encode_fns, 0, 0 }, - { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, - 0, - Opcode_rsr_ccompare1_encode_fns, 0, 0 }, - { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, - 0, - Opcode_wsr_ccompare1_encode_fns, 0, 0 }, - { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, - 0, - Opcode_xsr_ccompare1_encode_fns, 0, 0 }, - { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, - 0, - Opcode_rsr_ccompare2_encode_fns, 0, 0 }, - { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, - 0, - Opcode_wsr_ccompare2_encode_fns, 0, 0 }, - { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, - 0, - Opcode_xsr_ccompare2_encode_fns, 0, 0 }, - { "ipf", ICLASS_xt_iclass_icache, - 0, - Opcode_ipf_encode_fns, 0, 0 }, - { "ihi", ICLASS_xt_iclass_icache, - 0, - Opcode_ihi_encode_fns, 0, 0 }, - { "ipfl", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_ipfl_encode_fns, 0, 0 }, - { "ihu", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_ihu_encode_fns, 0, 0 }, - { "iiu", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_iiu_encode_fns, 0, 0 }, - { "iii", ICLASS_xt_iclass_icache_inv, - 0, - Opcode_iii_encode_fns, 0, 0 }, - { "lict", ICLASS_xt_iclass_licx, - 0, - Opcode_lict_encode_fns, 0, 0 }, - { "licw", ICLASS_xt_iclass_licx, - 0, - Opcode_licw_encode_fns, 0, 0 }, - { "sict", ICLASS_xt_iclass_sicx, - 0, - Opcode_sict_encode_fns, 0, 0 }, - { "sicw", ICLASS_xt_iclass_sicx, - 0, - Opcode_sicw_encode_fns, 0, 0 }, - { "dhwb", ICLASS_xt_iclass_dcache, - 0, - Opcode_dhwb_encode_fns, 0, 0 }, - { "dhwbi", ICLASS_xt_iclass_dcache, - 0, - Opcode_dhwbi_encode_fns, 0, 0 }, - { "diwb", ICLASS_xt_iclass_dcache_ind, - 0, - Opcode_diwb_encode_fns, 0, 0 }, - { "diwbi", ICLASS_xt_iclass_dcache_ind, - 0, - Opcode_diwbi_encode_fns, 0, 0 }, - { "dhi", ICLASS_xt_iclass_dcache_inv, - 0, - Opcode_dhi_encode_fns, 0, 0 }, - { "dii", ICLASS_xt_iclass_dcache_inv, - 0, - Opcode_dii_encode_fns, 0, 0 }, - { "dpfr", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfr_encode_fns, 0, 0 }, - { "dpfw", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfw_encode_fns, 0, 0 }, - { "dpfro", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfro_encode_fns, 0, 0 }, - { "dpfwo", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfwo_encode_fns, 0, 0 }, - { "dpfl", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_dpfl_encode_fns, 0, 0 }, - { "dhu", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_dhu_encode_fns, 0, 0 }, - { "diu", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_diu_encode_fns, 0, 0 }, - { "sdct", ICLASS_xt_iclass_sdct, - 0, - Opcode_sdct_encode_fns, 0, 0 }, - { "ldct", ICLASS_xt_iclass_ldct, - 0, - Opcode_ldct_encode_fns, 0, 0 }, - { "rsr.prefctl", ICLASS_xt_iclass_rsr_prefctl, - 0, - Opcode_rsr_prefctl_encode_fns, 0, 0 }, - { "wsr.prefctl", ICLASS_xt_iclass_wsr_prefctl, - 0, - Opcode_wsr_prefctl_encode_fns, 0, 0 }, - { "xsr.prefctl", ICLASS_xt_iclass_xsr_prefctl, - 0, - Opcode_xsr_prefctl_encode_fns, 0, 0 }, - { "idtlb", ICLASS_xt_iclass_idtlb, - 0, - Opcode_idtlb_encode_fns, 0, 0 }, - { "pdtlb", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_pdtlb_encode_fns, 0, 0 }, - { "rdtlb0", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb0_encode_fns, 0, 0 }, - { "rdtlb1", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb1_encode_fns, 0, 0 }, - { "wdtlb", ICLASS_xt_iclass_wdtlb, - 0, - Opcode_wdtlb_encode_fns, 0, 0 }, - { "iitlb", ICLASS_xt_iclass_iitlb, - 0, - Opcode_iitlb_encode_fns, 0, 0 }, - { "pitlb", ICLASS_xt_iclass_ritlb, - 0, - Opcode_pitlb_encode_fns, 0, 0 }, - { "ritlb0", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb0_encode_fns, 0, 0 }, - { "ritlb1", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb1_encode_fns, 0, 0 }, - { "witlb", ICLASS_xt_iclass_witlb, - 0, - Opcode_witlb_encode_fns, 0, 0 }, - { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, - 0, - Opcode_rsr_cpenable_encode_fns, 0, 0 }, - { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, - 0, - Opcode_wsr_cpenable_encode_fns, 0, 0 }, - { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, - 0, - Opcode_xsr_cpenable_encode_fns, 0, 0 }, - { "clamps", ICLASS_xt_iclass_clamp, - 0, - Opcode_clamps_encode_fns, 0, 0 }, - { "min", ICLASS_xt_iclass_minmax, - 0, - Opcode_min_encode_fns, 0, 0 }, - { "max", ICLASS_xt_iclass_minmax, - 0, - Opcode_max_encode_fns, 0, 0 }, - { "minu", ICLASS_xt_iclass_minmax, - 0, - Opcode_minu_encode_fns, 0, 0 }, - { "maxu", ICLASS_xt_iclass_minmax, - 0, - Opcode_maxu_encode_fns, 0, 0 }, - { "nsa", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsa_encode_fns, 0, 0 }, - { "nsau", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsau_encode_fns, 0, 0 }, - { "sext", ICLASS_xt_iclass_sx, - 0, - Opcode_sext_encode_fns, 0, 0 }, - { "l32ai", ICLASS_xt_iclass_l32ai, - 0, - Opcode_l32ai_encode_fns, 0, 0 }, - { "s32ri", ICLASS_xt_iclass_s32ri, - 0, - Opcode_s32ri_encode_fns, 0, 0 }, - { "s32c1i", ICLASS_xt_iclass_s32c1i, - 0, - Opcode_s32c1i_encode_fns, 0, 0 }, - { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, - 0, - Opcode_rsr_scompare1_encode_fns, 0, 0 }, - { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, - 0, - Opcode_wsr_scompare1_encode_fns, 0, 0 }, - { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, - 0, - Opcode_xsr_scompare1_encode_fns, 0, 0 }, - { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, - 0, - Opcode_rsr_atomctl_encode_fns, 0, 0 }, - { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, - 0, - Opcode_wsr_atomctl_encode_fns, 0, 0 }, - { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, - 0, - Opcode_xsr_atomctl_encode_fns, 0, 0 }, - { "rer", ICLASS_xt_iclass_rer, - 0, - Opcode_rer_encode_fns, 0, 0 }, - { "wer", ICLASS_xt_iclass_wer, - 0, - Opcode_wer_encode_fns, 0, 0 }, - { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar, - 0, - Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 }, - { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar, - 0, - Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 }, - { "rur.ae_bithead", ICLASS_rur_ae_bithead, - 0, - Opcode_rur_ae_bithead_encode_fns, 0, 0 }, - { "wur.ae_bithead", ICLASS_wur_ae_bithead, - 0, - Opcode_wur_ae_bithead_encode_fns, 0, 0 }, - { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp, - 0, - Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, - { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp, - 0, - Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, - { "rur.ae_sd_no", ICLASS_rur_ae_sd_no, - 0, - Opcode_rur_ae_sd_no_encode_fns, 0, 0 }, - { "wur.ae_sd_no", ICLASS_wur_ae_sd_no, - 0, - Opcode_wur_ae_sd_no_encode_fns, 0, 0 }, - { "rur.ae_overflow", ICLASS_ae_iclass_rur_ae_overflow, - 0, - Opcode_rur_ae_overflow_encode_fns, 0, 0 }, - { "wur.ae_overflow", ICLASS_ae_iclass_wur_ae_overflow, - 0, - Opcode_wur_ae_overflow_encode_fns, 0, 0 }, - { "rur.ae_sar", ICLASS_ae_iclass_rur_ae_sar, - 0, - Opcode_rur_ae_sar_encode_fns, 0, 0 }, - { "wur.ae_sar", ICLASS_ae_iclass_wur_ae_sar, - 0, - Opcode_wur_ae_sar_encode_fns, 0, 0 }, - { "rur.ae_bitptr", ICLASS_ae_iclass_rur_ae_bitptr, - 0, - Opcode_rur_ae_bitptr_encode_fns, 0, 0 }, - { "wur.ae_bitptr", ICLASS_ae_iclass_wur_ae_bitptr, - 0, - Opcode_wur_ae_bitptr_encode_fns, 0, 0 }, - { "rur.ae_bitsused", ICLASS_ae_iclass_rur_ae_bitsused, - 0, - Opcode_rur_ae_bitsused_encode_fns, 0, 0 }, - { "wur.ae_bitsused", ICLASS_ae_iclass_wur_ae_bitsused, - 0, - Opcode_wur_ae_bitsused_encode_fns, 0, 0 }, - { "rur.ae_tablesize", ICLASS_ae_iclass_rur_ae_tablesize, - 0, - Opcode_rur_ae_tablesize_encode_fns, 0, 0 }, - { "wur.ae_tablesize", ICLASS_ae_iclass_wur_ae_tablesize, - 0, - Opcode_wur_ae_tablesize_encode_fns, 0, 0 }, - { "rur.ae_first_ts", ICLASS_ae_iclass_rur_ae_first_ts, - 0, - Opcode_rur_ae_first_ts_encode_fns, 0, 0 }, - { "wur.ae_first_ts", ICLASS_ae_iclass_wur_ae_first_ts, - 0, - Opcode_wur_ae_first_ts_encode_fns, 0, 0 }, - { "rur.ae_nextoffset", ICLASS_ae_iclass_rur_ae_nextoffset, - 0, - Opcode_rur_ae_nextoffset_encode_fns, 0, 0 }, - { "wur.ae_nextoffset", ICLASS_ae_iclass_wur_ae_nextoffset, - 0, - Opcode_wur_ae_nextoffset_encode_fns, 0, 0 }, - { "rur.ae_searchdone", ICLASS_ae_iclass_rur_ae_searchdone, - 0, - Opcode_rur_ae_searchdone_encode_fns, 0, 0 }, - { "wur.ae_searchdone", ICLASS_ae_iclass_wur_ae_searchdone, - 0, - Opcode_wur_ae_searchdone_encode_fns, 0, 0 }, - { "ae_lp16f.i", ICLASS_ae_iclass_lp16f_i, - 0, - Opcode_ae_lp16f_i_encode_fns, 0, 0 }, - { "ae_lp16f.iu", ICLASS_ae_iclass_lp16f_iu, - 0, - Opcode_ae_lp16f_iu_encode_fns, 0, 0 }, - { "ae_lp16f.x", ICLASS_ae_iclass_lp16f_x, - 0, - Opcode_ae_lp16f_x_encode_fns, 0, 0 }, - { "ae_lp16f.xu", ICLASS_ae_iclass_lp16f_xu, - 0, - Opcode_ae_lp16f_xu_encode_fns, 0, 0 }, - { "ae_lp24.i", ICLASS_ae_iclass_lp24_i, - 0, - Opcode_ae_lp24_i_encode_fns, 0, 0 }, - { "ae_lp24.iu", ICLASS_ae_iclass_lp24_iu, - 0, - Opcode_ae_lp24_iu_encode_fns, 0, 0 }, - { "ae_lp24.x", ICLASS_ae_iclass_lp24_x, - 0, - Opcode_ae_lp24_x_encode_fns, 0, 0 }, - { "ae_lp24.xu", ICLASS_ae_iclass_lp24_xu, - 0, - Opcode_ae_lp24_xu_encode_fns, 0, 0 }, - { "ae_lp24f.i", ICLASS_ae_iclass_lp24f_i, - 0, - Opcode_ae_lp24f_i_encode_fns, 0, 0 }, - { "ae_lp24f.iu", ICLASS_ae_iclass_lp24f_iu, - 0, - Opcode_ae_lp24f_iu_encode_fns, 0, 0 }, - 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0, - Opcode_ae_minabssp24s_encode_fns, 0, 0 }, - { "ae_maxabssp24s", ICLASS_icls_AE_MAXABSSP24S, - 0, - Opcode_ae_maxabssp24s_encode_fns, 0, 0 }, - { "ae_minabssq56s", ICLASS_icls_AE_MINABSSQ56S, - 0, - Opcode_ae_minabssq56s_encode_fns, 0, 0 }, - { "ae_maxabssq56s", ICLASS_icls_AE_MAXABSSQ56S, - 0, - Opcode_ae_maxabssq56s_encode_fns, 0, 0 }, - { "rur.ae_cbegin0", ICLASS_rur_ae_cbegin0, - 0, - Opcode_rur_ae_cbegin0_encode_fns, 0, 0 }, - { "wur.ae_cbegin0", ICLASS_wur_ae_cbegin0, - 0, - Opcode_wur_ae_cbegin0_encode_fns, 0, 0 }, - { "rur.ae_cend0", ICLASS_rur_ae_cend0, - 0, - Opcode_rur_ae_cend0_encode_fns, 0, 0 }, - { "wur.ae_cend0", ICLASS_wur_ae_cend0, - 0, - Opcode_wur_ae_cend0_encode_fns, 0, 0 }, - { "ae_lp24x2.c", ICLASS_icls_AE_LP24X2_C, - 0, - Opcode_ae_lp24x2_c_encode_fns, 0, 0 }, - { "ae_sp24x2s.c", ICLASS_icls_AE_SP24X2S_C, - 0, - Opcode_ae_sp24x2s_c_encode_fns, 0, 0 }, - { "ae_lp24x2f.c", ICLASS_icls_AE_LP24X2F_C, - 0, - Opcode_ae_lp24x2f_c_encode_fns, 0, 0 }, - { "ae_sp24x2f.c", ICLASS_icls_AE_SP24X2F_C, - 0, - Opcode_ae_sp24x2f_c_encode_fns, 0, 0 }, - { "ae_lp16x2f.c", ICLASS_icls_AE_LP16X2F_C, - 0, - Opcode_ae_lp16x2f_c_encode_fns, 0, 0 }, - { "ae_sp16x2f.c", ICLASS_icls_AE_SP16X2F_C, - 0, - Opcode_ae_sp16x2f_c_encode_fns, 0, 0 }, - { "ae_lp24.c", ICLASS_icls_AE_LP24_C, - 0, - Opcode_ae_lp24_c_encode_fns, 0, 0 }, - { "ae_sp24s.l.c", ICLASS_icls_AE_SP24S_L_C, - 0, - Opcode_ae_sp24s_l_c_encode_fns, 0, 0 }, - { "ae_lp24f.c", ICLASS_icls_AE_LP24F_C, - 0, - Opcode_ae_lp24f_c_encode_fns, 0, 0 }, - { "ae_sp24f.l.c", ICLASS_icls_AE_SP24F_L_C, - 0, - Opcode_ae_sp24f_l_c_encode_fns, 0, 0 }, - { "ae_lp16f.c", ICLASS_icls_AE_LP16F_C, - 0, - Opcode_ae_lp16f_c_encode_fns, 0, 0 }, - { "ae_sp16f.l.c", ICLASS_icls_AE_SP16F_L_C, - 0, - Opcode_ae_sp16f_l_c_encode_fns, 0, 0 }, - { "ae_lq56.c", ICLASS_icls_AE_LQ56_C, - 0, - Opcode_ae_lq56_c_encode_fns, 0, 0 }, - { "ae_sq56s.c", ICLASS_icls_AE_SQ56S_C, - 0, - Opcode_ae_sq56s_c_encode_fns, 0, 0 }, - { "ae_lq32f.c", ICLASS_icls_AE_LQ32F_C, - 0, - Opcode_ae_lq32f_c_encode_fns, 0, 0 }, - { "ae_sq32f.c", ICLASS_icls_AE_SQ32F_C, - 0, - Opcode_ae_sq32f_c_encode_fns, 0, 0 } -}; - -enum xtensa_opcode_id { - OPCODE_EXCW, - OPCODE_RFE, - OPCODE_RFDE, - OPCODE_SYSCALL, - OPCODE_CALL12, - OPCODE_CALL8, - OPCODE_CALL4, - OPCODE_CALLX12, - OPCODE_CALLX8, - OPCODE_CALLX4, - OPCODE_ENTRY, - OPCODE_MOVSP, - OPCODE_ROTW, - OPCODE_RETW, - OPCODE_RETW_N, - OPCODE_RFWO, - OPCODE_RFWU, - OPCODE_L32E, - OPCODE_S32E, - OPCODE_RSR_WINDOWBASE, - OPCODE_WSR_WINDOWBASE, - OPCODE_XSR_WINDOWBASE, - OPCODE_RSR_WINDOWSTART, - OPCODE_WSR_WINDOWSTART, - OPCODE_XSR_WINDOWSTART, - OPCODE_ADD_N, - OPCODE_ADDI_N, - OPCODE_BEQZ_N, - OPCODE_BNEZ_N, - OPCODE_ILL_N, - OPCODE_L32I_N, - OPCODE_MOV_N, - OPCODE_MOVI_N, - OPCODE_NOP_N, - OPCODE_RET_N, - OPCODE_S32I_N, - OPCODE_RUR_THREADPTR, - OPCODE_WUR_THREADPTR, - OPCODE_ADDI, - OPCODE_ADDMI, - OPCODE_ADD, - OPCODE_SUB, - OPCODE_ADDX2, - OPCODE_ADDX4, - OPCODE_ADDX8, - OPCODE_SUBX2, - OPCODE_SUBX4, - OPCODE_SUBX8, - OPCODE_AND, - OPCODE_OR, - OPCODE_XOR, - OPCODE_BEQI, - OPCODE_BNEI, - OPCODE_BGEI, - OPCODE_BLTI, - OPCODE_BBCI, - OPCODE_BBSI, - OPCODE_BGEUI, - OPCODE_BLTUI, - OPCODE_BEQ, - OPCODE_BNE, - OPCODE_BGE, - OPCODE_BLT, - OPCODE_BGEU, - OPCODE_BLTU, - OPCODE_BANY, - OPCODE_BNONE, - OPCODE_BALL, - OPCODE_BNALL, - OPCODE_BBC, - OPCODE_BBS, - OPCODE_BEQZ, - OPCODE_BNEZ, - OPCODE_BGEZ, - OPCODE_BLTZ, - OPCODE_CALL0, - OPCODE_CALLX0, - OPCODE_EXTUI, - OPCODE_ILL, - OPCODE_J, - OPCODE_JX, - OPCODE_L16UI, - OPCODE_L16SI, - OPCODE_L32I, - OPCODE_L32R, - OPCODE_L8UI, - OPCODE_LOOP, - OPCODE_LOOPNEZ, - OPCODE_LOOPGTZ, - OPCODE_MOVI, - OPCODE_MOVEQZ, - OPCODE_MOVNEZ, - OPCODE_MOVLTZ, - OPCODE_MOVGEZ, - OPCODE_NEG, - OPCODE_ABS, - OPCODE_NOP, - OPCODE_RET, - OPCODE_SIMCALL, - OPCODE_S16I, - OPCODE_S32I, - OPCODE_S8I, - OPCODE_SSR, - OPCODE_SSL, - OPCODE_SSA8L, - OPCODE_SSA8B, - OPCODE_SSAI, - OPCODE_SLL, - OPCODE_SRC, - OPCODE_SRL, - OPCODE_SRA, - OPCODE_SLLI, - OPCODE_SRAI, - OPCODE_SRLI, - OPCODE_MEMW, - OPCODE_EXTW, - OPCODE_ISYNC, - OPCODE_RSYNC, - OPCODE_ESYNC, - OPCODE_DSYNC, - OPCODE_RSIL, - OPCODE_RSR_LEND, - OPCODE_WSR_LEND, - OPCODE_XSR_LEND, - OPCODE_RSR_LCOUNT, - OPCODE_WSR_LCOUNT, - OPCODE_XSR_LCOUNT, - OPCODE_RSR_LBEG, - OPCODE_WSR_LBEG, - OPCODE_XSR_LBEG, - OPCODE_RSR_SAR, - OPCODE_WSR_SAR, - OPCODE_XSR_SAR, - OPCODE_RSR_LITBASE, - OPCODE_WSR_LITBASE, - OPCODE_XSR_LITBASE, - OPCODE_RSR_CONFIGID0, - OPCODE_WSR_CONFIGID0, - OPCODE_RSR_CONFIGID1, - OPCODE_RSR_243, - OPCODE_RSR_PS, - OPCODE_WSR_PS, - OPCODE_XSR_PS, - OPCODE_RSR_EPC1, - OPCODE_WSR_EPC1, - OPCODE_XSR_EPC1, - OPCODE_RSR_EXCSAVE1, - OPCODE_WSR_EXCSAVE1, - OPCODE_XSR_EXCSAVE1, - OPCODE_RSR_EPC2, - OPCODE_WSR_EPC2, - OPCODE_XSR_EPC2, - OPCODE_RSR_EXCSAVE2, - OPCODE_WSR_EXCSAVE2, - OPCODE_XSR_EXCSAVE2, - OPCODE_RSR_EPC3, - OPCODE_WSR_EPC3, - OPCODE_XSR_EPC3, - OPCODE_RSR_EXCSAVE3, - OPCODE_WSR_EXCSAVE3, - OPCODE_XSR_EXCSAVE3, - OPCODE_RSR_EPC4, - OPCODE_WSR_EPC4, - OPCODE_XSR_EPC4, - OPCODE_RSR_EXCSAVE4, - OPCODE_WSR_EXCSAVE4, - OPCODE_XSR_EXCSAVE4, - OPCODE_RSR_EPC5, - OPCODE_WSR_EPC5, - OPCODE_XSR_EPC5, - OPCODE_RSR_EXCSAVE5, - OPCODE_WSR_EXCSAVE5, - OPCODE_XSR_EXCSAVE5, - OPCODE_RSR_EPC6, - OPCODE_WSR_EPC6, - OPCODE_XSR_EPC6, - OPCODE_RSR_EXCSAVE6, - OPCODE_WSR_EXCSAVE6, - OPCODE_XSR_EXCSAVE6, - OPCODE_RSR_EPC7, - OPCODE_WSR_EPC7, - OPCODE_XSR_EPC7, - OPCODE_RSR_EXCSAVE7, - OPCODE_WSR_EXCSAVE7, - OPCODE_XSR_EXCSAVE7, - OPCODE_RSR_EPS2, - OPCODE_WSR_EPS2, - OPCODE_XSR_EPS2, - OPCODE_RSR_EPS3, - OPCODE_WSR_EPS3, - OPCODE_XSR_EPS3, - OPCODE_RSR_EPS4, - OPCODE_WSR_EPS4, - OPCODE_XSR_EPS4, - OPCODE_RSR_EPS5, - OPCODE_WSR_EPS5, - OPCODE_XSR_EPS5, - OPCODE_RSR_EPS6, - OPCODE_WSR_EPS6, - OPCODE_XSR_EPS6, - OPCODE_RSR_EPS7, - OPCODE_WSR_EPS7, - OPCODE_XSR_EPS7, - OPCODE_RSR_EXCVADDR, - OPCODE_WSR_EXCVADDR, - OPCODE_XSR_EXCVADDR, - OPCODE_RSR_DEPC, - OPCODE_WSR_DEPC, - OPCODE_XSR_DEPC, - OPCODE_RSR_EXCCAUSE, - OPCODE_WSR_EXCCAUSE, - OPCODE_XSR_EXCCAUSE, - OPCODE_RSR_PRID, - OPCODE_RSR_VECBASE, - OPCODE_WSR_VECBASE, - OPCODE_XSR_VECBASE, - OPCODE_MUL16U, - OPCODE_MUL16S, - OPCODE_MULL, - OPCODE_MULUH, - OPCODE_MULSH, - OPCODE_MUL_AA_LL, - OPCODE_MUL_AA_HL, - OPCODE_MUL_AA_LH, - OPCODE_MUL_AA_HH, - OPCODE_UMUL_AA_LL, - OPCODE_UMUL_AA_HL, - OPCODE_UMUL_AA_LH, - OPCODE_UMUL_AA_HH, - OPCODE_MUL_AD_LL, - OPCODE_MUL_AD_HL, - OPCODE_MUL_AD_LH, - OPCODE_MUL_AD_HH, - OPCODE_MUL_DA_LL, - OPCODE_MUL_DA_HL, - OPCODE_MUL_DA_LH, - OPCODE_MUL_DA_HH, - OPCODE_MUL_DD_LL, - OPCODE_MUL_DD_HL, - OPCODE_MUL_DD_LH, - OPCODE_MUL_DD_HH, - OPCODE_MULA_AA_LL, - OPCODE_MULA_AA_HL, - OPCODE_MULA_AA_LH, - OPCODE_MULA_AA_HH, - OPCODE_MULS_AA_LL, - OPCODE_MULS_AA_HL, - OPCODE_MULS_AA_LH, - OPCODE_MULS_AA_HH, - OPCODE_MULA_AD_LL, - OPCODE_MULA_AD_HL, - OPCODE_MULA_AD_LH, - OPCODE_MULA_AD_HH, - OPCODE_MULS_AD_LL, - OPCODE_MULS_AD_HL, - OPCODE_MULS_AD_LH, - OPCODE_MULS_AD_HH, - OPCODE_MULA_DA_LL, - OPCODE_MULA_DA_HL, - OPCODE_MULA_DA_LH, - OPCODE_MULA_DA_HH, - OPCODE_MULS_DA_LL, - OPCODE_MULS_DA_HL, - OPCODE_MULS_DA_LH, - OPCODE_MULS_DA_HH, - OPCODE_MULA_DD_LL, - OPCODE_MULA_DD_HL, - OPCODE_MULA_DD_LH, - OPCODE_MULA_DD_HH, - OPCODE_MULS_DD_LL, - OPCODE_MULS_DD_HL, - OPCODE_MULS_DD_LH, - OPCODE_MULS_DD_HH, - OPCODE_MULA_DA_LL_LDDEC, - OPCODE_MULA_DA_LL_LDINC, - OPCODE_MULA_DA_HL_LDDEC, - OPCODE_MULA_DA_HL_LDINC, - OPCODE_MULA_DA_LH_LDDEC, - OPCODE_MULA_DA_LH_LDINC, - OPCODE_MULA_DA_HH_LDDEC, - OPCODE_MULA_DA_HH_LDINC, - OPCODE_MULA_DD_LL_LDDEC, - OPCODE_MULA_DD_LL_LDINC, - OPCODE_MULA_DD_HL_LDDEC, - OPCODE_MULA_DD_HL_LDINC, - OPCODE_MULA_DD_LH_LDDEC, - OPCODE_MULA_DD_LH_LDINC, - OPCODE_MULA_DD_HH_LDDEC, - OPCODE_MULA_DD_HH_LDINC, - OPCODE_LDDEC, - OPCODE_LDINC, - OPCODE_RSR_M0, - OPCODE_WSR_M0, - OPCODE_XSR_M0, - OPCODE_RSR_M1, - OPCODE_WSR_M1, - OPCODE_XSR_M1, - OPCODE_RSR_M2, - OPCODE_WSR_M2, - OPCODE_XSR_M2, - OPCODE_RSR_M3, - OPCODE_WSR_M3, - OPCODE_XSR_M3, - OPCODE_RSR_ACCLO, - OPCODE_WSR_ACCLO, - OPCODE_XSR_ACCLO, - OPCODE_RSR_ACCHI, - OPCODE_WSR_ACCHI, - OPCODE_XSR_ACCHI, - OPCODE_RFI, - OPCODE_WAITI, - OPCODE_RSR_INTERRUPT, - OPCODE_WSR_INTSET, - OPCODE_WSR_INTCLEAR, - OPCODE_RSR_INTENABLE, - OPCODE_WSR_INTENABLE, - OPCODE_XSR_INTENABLE, - OPCODE_BREAK, - OPCODE_BREAK_N, - OPCODE_RSR_DBREAKA0, - OPCODE_WSR_DBREAKA0, - OPCODE_XSR_DBREAKA0, - OPCODE_RSR_DBREAKC0, - OPCODE_WSR_DBREAKC0, - OPCODE_XSR_DBREAKC0, - OPCODE_RSR_DBREAKA1, - OPCODE_WSR_DBREAKA1, - OPCODE_XSR_DBREAKA1, - OPCODE_RSR_DBREAKC1, - OPCODE_WSR_DBREAKC1, - OPCODE_XSR_DBREAKC1, - OPCODE_RSR_IBREAKA0, - OPCODE_WSR_IBREAKA0, - OPCODE_XSR_IBREAKA0, - OPCODE_RSR_IBREAKA1, - OPCODE_WSR_IBREAKA1, - OPCODE_XSR_IBREAKA1, - OPCODE_RSR_IBREAKENABLE, - OPCODE_WSR_IBREAKENABLE, - OPCODE_XSR_IBREAKENABLE, - OPCODE_RSR_DEBUGCAUSE, - OPCODE_WSR_DEBUGCAUSE, - OPCODE_XSR_DEBUGCAUSE, - OPCODE_RSR_ICOUNT, - OPCODE_WSR_ICOUNT, - OPCODE_XSR_ICOUNT, - OPCODE_RSR_ICOUNTLEVEL, - OPCODE_WSR_ICOUNTLEVEL, - OPCODE_XSR_ICOUNTLEVEL, - OPCODE_RSR_DDR, - OPCODE_WSR_DDR, - OPCODE_XSR_DDR, - OPCODE_RFDO, - OPCODE_RFDD, - OPCODE_ANDB, - OPCODE_ANDBC, - OPCODE_ORB, - OPCODE_ORBC, - OPCODE_XORB, - OPCODE_ANY4, - OPCODE_ALL4, - OPCODE_ANY8, - OPCODE_ALL8, - OPCODE_BF, - OPCODE_BT, - OPCODE_MOVF, - OPCODE_MOVT, - OPCODE_RSR_BR, - OPCODE_WSR_BR, - OPCODE_XSR_BR, - OPCODE_RSR_CCOUNT, - OPCODE_WSR_CCOUNT, - OPCODE_XSR_CCOUNT, - OPCODE_RSR_CCOMPARE0, - OPCODE_WSR_CCOMPARE0, - OPCODE_XSR_CCOMPARE0, - OPCODE_RSR_CCOMPARE1, - OPCODE_WSR_CCOMPARE1, - OPCODE_XSR_CCOMPARE1, - OPCODE_RSR_CCOMPARE2, - OPCODE_WSR_CCOMPARE2, - OPCODE_XSR_CCOMPARE2, - OPCODE_IPF, - OPCODE_IHI, - OPCODE_IPFL, - OPCODE_IHU, - OPCODE_IIU, - OPCODE_III, - OPCODE_LICT, - OPCODE_LICW, - OPCODE_SICT, - OPCODE_SICW, - OPCODE_DHWB, - OPCODE_DHWBI, - OPCODE_DIWB, - OPCODE_DIWBI, - OPCODE_DHI, - OPCODE_DII, - OPCODE_DPFR, - OPCODE_DPFW, - OPCODE_DPFRO, - OPCODE_DPFWO, - OPCODE_DPFL, - OPCODE_DHU, - OPCODE_DIU, - OPCODE_SDCT, - OPCODE_LDCT, - OPCODE_RSR_PREFCTL, - OPCODE_WSR_PREFCTL, - OPCODE_XSR_PREFCTL, - OPCODE_IDTLB, - OPCODE_PDTLB, - OPCODE_RDTLB0, - OPCODE_RDTLB1, - OPCODE_WDTLB, - OPCODE_IITLB, - OPCODE_PITLB, - OPCODE_RITLB0, - OPCODE_RITLB1, - OPCODE_WITLB, - OPCODE_RSR_CPENABLE, - OPCODE_WSR_CPENABLE, - OPCODE_XSR_CPENABLE, - OPCODE_CLAMPS, - OPCODE_MIN, - OPCODE_MAX, - OPCODE_MINU, - OPCODE_MAXU, - OPCODE_NSA, - OPCODE_NSAU, - OPCODE_SEXT, - OPCODE_L32AI, - OPCODE_S32RI, - OPCODE_S32C1I, - OPCODE_RSR_SCOMPARE1, - OPCODE_WSR_SCOMPARE1, - OPCODE_XSR_SCOMPARE1, - OPCODE_RSR_ATOMCTL, - OPCODE_WSR_ATOMCTL, - OPCODE_XSR_ATOMCTL, - OPCODE_RER, - OPCODE_WER, - OPCODE_RUR_AE_OVF_SAR, - OPCODE_WUR_AE_OVF_SAR, - OPCODE_RUR_AE_BITHEAD, - OPCODE_WUR_AE_BITHEAD, - OPCODE_RUR_AE_TS_FTS_BU_BP, - OPCODE_WUR_AE_TS_FTS_BU_BP, - OPCODE_RUR_AE_SD_NO, - OPCODE_WUR_AE_SD_NO, - OPCODE_RUR_AE_OVERFLOW, - OPCODE_WUR_AE_OVERFLOW, - OPCODE_RUR_AE_SAR, - OPCODE_WUR_AE_SAR, - OPCODE_RUR_AE_BITPTR, - OPCODE_WUR_AE_BITPTR, - OPCODE_RUR_AE_BITSUSED, - OPCODE_WUR_AE_BITSUSED, - OPCODE_RUR_AE_TABLESIZE, - OPCODE_WUR_AE_TABLESIZE, - OPCODE_RUR_AE_FIRST_TS, - OPCODE_WUR_AE_FIRST_TS, - OPCODE_RUR_AE_NEXTOFFSET, - OPCODE_WUR_AE_NEXTOFFSET, - OPCODE_RUR_AE_SEARCHDONE, - OPCODE_WUR_AE_SEARCHDONE, - OPCODE_AE_LP16F_I, - OPCODE_AE_LP16F_IU, - OPCODE_AE_LP16F_X, - OPCODE_AE_LP16F_XU, - OPCODE_AE_LP24_I, - OPCODE_AE_LP24_IU, - OPCODE_AE_LP24_X, - OPCODE_AE_LP24_XU, - OPCODE_AE_LP24F_I, - OPCODE_AE_LP24F_IU, - OPCODE_AE_LP24F_X, - OPCODE_AE_LP24F_XU, - OPCODE_AE_LP16X2F_I, - OPCODE_AE_LP16X2F_IU, - OPCODE_AE_LP16X2F_X, - OPCODE_AE_LP16X2F_XU, - OPCODE_AE_LP24X2F_I, - OPCODE_AE_LP24X2F_IU, - OPCODE_AE_LP24X2F_X, - OPCODE_AE_LP24X2F_XU, - OPCODE_AE_LP24X2_I, - OPCODE_AE_LP24X2_IU, - OPCODE_AE_LP24X2_X, - OPCODE_AE_LP24X2_XU, - OPCODE_AE_SP16X2F_I, - OPCODE_AE_SP16X2F_IU, - OPCODE_AE_SP16X2F_X, - OPCODE_AE_SP16X2F_XU, - OPCODE_AE_SP24X2S_I, - OPCODE_AE_SP24X2S_IU, - OPCODE_AE_SP24X2S_X, - OPCODE_AE_SP24X2S_XU, - OPCODE_AE_SP24X2F_I, - OPCODE_AE_SP24X2F_IU, - OPCODE_AE_SP24X2F_X, - OPCODE_AE_SP24X2F_XU, - OPCODE_AE_SP16F_L_I, - OPCODE_AE_SP16F_L_IU, - OPCODE_AE_SP16F_L_X, - OPCODE_AE_SP16F_L_XU, - OPCODE_AE_SP24S_L_I, - OPCODE_AE_SP24S_L_IU, - OPCODE_AE_SP24S_L_X, - OPCODE_AE_SP24S_L_XU, - OPCODE_AE_SP24F_L_I, - OPCODE_AE_SP24F_L_IU, - OPCODE_AE_SP24F_L_X, - OPCODE_AE_SP24F_L_XU, - OPCODE_AE_LQ56_I, - OPCODE_AE_LQ56_IU, - OPCODE_AE_LQ56_X, - OPCODE_AE_LQ56_XU, - OPCODE_AE_LQ32F_I, - OPCODE_AE_LQ32F_IU, - OPCODE_AE_LQ32F_X, - OPCODE_AE_LQ32F_XU, - OPCODE_AE_SQ56S_I, - OPCODE_AE_SQ56S_IU, - OPCODE_AE_SQ56S_X, - OPCODE_AE_SQ56S_XU, - OPCODE_AE_SQ32F_I, - OPCODE_AE_SQ32F_IU, - OPCODE_AE_SQ32F_X, - OPCODE_AE_SQ32F_XU, - OPCODE_AE_ZEROP48, - OPCODE_AE_MOVP48, - OPCODE_AE_SELP24_LL, - OPCODE_AE_SELP24_LH, - OPCODE_AE_SELP24_HL, - OPCODE_AE_SELP24_HH, - OPCODE_AE_MOVTP24X2, - OPCODE_AE_MOVFP24X2, - OPCODE_AE_MOVTP48, - OPCODE_AE_MOVFP48, - OPCODE_AE_MOVPA24X2, - OPCODE_AE_TRUNCP24A32X2, - OPCODE_AE_CVTA32P24_L, - OPCODE_AE_CVTA32P24_H, - OPCODE_AE_CVTP24A16X2_LL, - OPCODE_AE_CVTP24A16X2_LH, - OPCODE_AE_CVTP24A16X2_HL, - OPCODE_AE_CVTP24A16X2_HH, - OPCODE_AE_TRUNCP24Q48X2, - OPCODE_AE_TRUNCP16, - OPCODE_AE_ROUNDSP24Q48SYM, - OPCODE_AE_ROUNDSP24Q48ASYM, - OPCODE_AE_ROUNDSP16Q48SYM, - OPCODE_AE_ROUNDSP16Q48ASYM, - OPCODE_AE_ROUNDSP16SYM, - OPCODE_AE_ROUNDSP16ASYM, - OPCODE_AE_ZEROQ56, - OPCODE_AE_MOVQ56, - OPCODE_AE_MOVTQ56, - OPCODE_AE_MOVFQ56, - OPCODE_AE_CVTQ48A32S, - OPCODE_AE_CVTQ48P24S_L, - OPCODE_AE_CVTQ48P24S_H, - OPCODE_AE_SATQ48S, - OPCODE_AE_TRUNCQ32, - OPCODE_AE_ROUNDSQ32SYM, - OPCODE_AE_ROUNDSQ32ASYM, - OPCODE_AE_TRUNCA32Q48, - OPCODE_AE_MOVAP24S_L, - OPCODE_AE_MOVAP24S_H, - OPCODE_AE_TRUNCA16P24S_L, - OPCODE_AE_TRUNCA16P24S_H, - OPCODE_AE_ADDP24, - OPCODE_AE_SUBP24, - OPCODE_AE_NEGP24, - OPCODE_AE_ABSP24, - OPCODE_AE_MAXP24S, - OPCODE_AE_MINP24S, - OPCODE_AE_MAXBP24S, - OPCODE_AE_MINBP24S, - OPCODE_AE_ADDSP24S, - OPCODE_AE_SUBSP24S, - OPCODE_AE_NEGSP24S, - OPCODE_AE_ABSSP24S, - OPCODE_AE_ANDP48, - OPCODE_AE_NANDP48, - OPCODE_AE_ORP48, - OPCODE_AE_XORP48, - OPCODE_AE_LTP24S, - OPCODE_AE_LEP24S, - OPCODE_AE_EQP24, - OPCODE_AE_ADDQ56, - OPCODE_AE_SUBQ56, - OPCODE_AE_NEGQ56, - OPCODE_AE_ABSQ56, - OPCODE_AE_MAXQ56S, - OPCODE_AE_MINQ56S, - OPCODE_AE_MAXBQ56S, - OPCODE_AE_MINBQ56S, - OPCODE_AE_ADDSQ56S, - OPCODE_AE_SUBSQ56S, - OPCODE_AE_NEGSQ56S, - OPCODE_AE_ABSSQ56S, - OPCODE_AE_ANDQ56, - OPCODE_AE_NANDQ56, - OPCODE_AE_ORQ56, - OPCODE_AE_XORQ56, - OPCODE_AE_SLLIP24, - OPCODE_AE_SRLIP24, - OPCODE_AE_SRAIP24, - OPCODE_AE_SLLSP24, - OPCODE_AE_SRLSP24, - OPCODE_AE_SRASP24, - OPCODE_AE_SLLISP24S, - OPCODE_AE_SLLSSP24S, - OPCODE_AE_SLLIQ56, - OPCODE_AE_SRLIQ56, - OPCODE_AE_SRAIQ56, - OPCODE_AE_SLLSQ56, - OPCODE_AE_SRLSQ56, - OPCODE_AE_SRASQ56, - OPCODE_AE_SLLAQ56, - OPCODE_AE_SRLAQ56, - OPCODE_AE_SRAAQ56, - OPCODE_AE_SLLISQ56S, - OPCODE_AE_SLLSSQ56S, - OPCODE_AE_SLLASQ56S, - OPCODE_AE_LTQ56S, - OPCODE_AE_LEQ56S, - OPCODE_AE_EQQ56, - OPCODE_AE_NSAQ56S, - OPCODE_AE_MULSRFQ32SP24S_H, - OPCODE_AE_MULSRFQ32SP24S_L, - OPCODE_AE_MULARFQ32SP24S_H, - OPCODE_AE_MULARFQ32SP24S_L, - OPCODE_AE_MULRFQ32SP24S_H, - OPCODE_AE_MULRFQ32SP24S_L, - OPCODE_AE_MULSFQ32SP24S_H, - OPCODE_AE_MULSFQ32SP24S_L, - OPCODE_AE_MULAFQ32SP24S_H, - OPCODE_AE_MULAFQ32SP24S_L, - OPCODE_AE_MULFQ32SP24S_H, - OPCODE_AE_MULFQ32SP24S_L, - OPCODE_AE_MULFS32P16S_LL, - OPCODE_AE_MULFP24S_LL, - OPCODE_AE_MULP24S_LL, - OPCODE_AE_MULFS32P16S_LH, - OPCODE_AE_MULFP24S_LH, - OPCODE_AE_MULP24S_LH, - OPCODE_AE_MULFS32P16S_HL, - OPCODE_AE_MULFP24S_HL, - OPCODE_AE_MULP24S_HL, - OPCODE_AE_MULFS32P16S_HH, - OPCODE_AE_MULFP24S_HH, - OPCODE_AE_MULP24S_HH, - OPCODE_AE_MULAFS32P16S_LL, - OPCODE_AE_MULAFP24S_LL, - OPCODE_AE_MULAP24S_LL, - OPCODE_AE_MULAFS32P16S_LH, - OPCODE_AE_MULAFP24S_LH, - OPCODE_AE_MULAP24S_LH, - OPCODE_AE_MULAFS32P16S_HL, - OPCODE_AE_MULAFP24S_HL, - OPCODE_AE_MULAP24S_HL, - OPCODE_AE_MULAFS32P16S_HH, - OPCODE_AE_MULAFP24S_HH, - OPCODE_AE_MULAP24S_HH, - OPCODE_AE_MULSFS32P16S_LL, - OPCODE_AE_MULSFP24S_LL, - OPCODE_AE_MULSP24S_LL, - OPCODE_AE_MULSFS32P16S_LH, - OPCODE_AE_MULSFP24S_LH, - OPCODE_AE_MULSP24S_LH, - OPCODE_AE_MULSFS32P16S_HL, - OPCODE_AE_MULSFP24S_HL, - OPCODE_AE_MULSP24S_HL, - OPCODE_AE_MULSFS32P16S_HH, - OPCODE_AE_MULSFP24S_HH, - OPCODE_AE_MULSP24S_HH, - OPCODE_AE_MULAFS56P24S_LL, - OPCODE_AE_MULAS56P24S_LL, - OPCODE_AE_MULAFS56P24S_LH, - OPCODE_AE_MULAS56P24S_LH, - OPCODE_AE_MULAFS56P24S_HL, - OPCODE_AE_MULAS56P24S_HL, - OPCODE_AE_MULAFS56P24S_HH, - OPCODE_AE_MULAS56P24S_HH, - OPCODE_AE_MULSFS56P24S_LL, - OPCODE_AE_MULSS56P24S_LL, - OPCODE_AE_MULSFS56P24S_LH, - OPCODE_AE_MULSS56P24S_LH, - OPCODE_AE_MULSFS56P24S_HL, - OPCODE_AE_MULSS56P24S_HL, - OPCODE_AE_MULSFS56P24S_HH, - OPCODE_AE_MULSS56P24S_HH, - OPCODE_AE_MULFQ32SP16S_L, - OPCODE_AE_MULFQ32SP16S_H, - OPCODE_AE_MULFQ32SP16U_L, - OPCODE_AE_MULFQ32SP16U_H, - OPCODE_AE_MULQ32SP16S_L, - OPCODE_AE_MULQ32SP16S_H, - OPCODE_AE_MULQ32SP16U_L, - OPCODE_AE_MULQ32SP16U_H, - OPCODE_AE_MULAFQ32SP16S_L, - OPCODE_AE_MULAFQ32SP16S_H, - OPCODE_AE_MULAFQ32SP16U_L, - OPCODE_AE_MULAFQ32SP16U_H, - OPCODE_AE_MULAQ32SP16S_L, - OPCODE_AE_MULAQ32SP16S_H, - OPCODE_AE_MULAQ32SP16U_L, - OPCODE_AE_MULAQ32SP16U_H, - OPCODE_AE_MULSFQ32SP16S_L, - OPCODE_AE_MULSFQ32SP16S_H, - OPCODE_AE_MULSFQ32SP16U_L, - OPCODE_AE_MULSFQ32SP16U_H, - OPCODE_AE_MULSQ32SP16S_L, - OPCODE_AE_MULSQ32SP16S_H, - OPCODE_AE_MULSQ32SP16U_L, - OPCODE_AE_MULSQ32SP16U_H, - OPCODE_AE_MULZAAQ32SP16S_LL, - OPCODE_AE_MULZAAFQ32SP16S_LL, - OPCODE_AE_MULZAAQ32SP16U_LL, - OPCODE_AE_MULZAAFQ32SP16U_LL, - OPCODE_AE_MULZAAQ32SP16S_HH, - OPCODE_AE_MULZAAFQ32SP16S_HH, - OPCODE_AE_MULZAAQ32SP16U_HH, - OPCODE_AE_MULZAAFQ32SP16U_HH, - OPCODE_AE_MULZAAQ32SP16S_LH, - OPCODE_AE_MULZAAFQ32SP16S_LH, - OPCODE_AE_MULZAAQ32SP16U_LH, - OPCODE_AE_MULZAAFQ32SP16U_LH, - OPCODE_AE_MULZASQ32SP16S_LL, - OPCODE_AE_MULZASFQ32SP16S_LL, - OPCODE_AE_MULZASQ32SP16U_LL, - OPCODE_AE_MULZASFQ32SP16U_LL, - OPCODE_AE_MULZASQ32SP16S_HH, - OPCODE_AE_MULZASFQ32SP16S_HH, - OPCODE_AE_MULZASQ32SP16U_HH, - OPCODE_AE_MULZASFQ32SP16U_HH, - OPCODE_AE_MULZASQ32SP16S_LH, - OPCODE_AE_MULZASFQ32SP16S_LH, - OPCODE_AE_MULZASQ32SP16U_LH, - OPCODE_AE_MULZASFQ32SP16U_LH, - OPCODE_AE_MULZSAQ32SP16S_LL, - OPCODE_AE_MULZSAFQ32SP16S_LL, - OPCODE_AE_MULZSAQ32SP16U_LL, - OPCODE_AE_MULZSAFQ32SP16U_LL, - OPCODE_AE_MULZSAQ32SP16S_HH, - OPCODE_AE_MULZSAFQ32SP16S_HH, - OPCODE_AE_MULZSAQ32SP16U_HH, - OPCODE_AE_MULZSAFQ32SP16U_HH, - OPCODE_AE_MULZSAQ32SP16S_LH, - OPCODE_AE_MULZSAFQ32SP16S_LH, - OPCODE_AE_MULZSAQ32SP16U_LH, - OPCODE_AE_MULZSAFQ32SP16U_LH, - OPCODE_AE_MULZSSQ32SP16S_LL, - OPCODE_AE_MULZSSFQ32SP16S_LL, - OPCODE_AE_MULZSSQ32SP16U_LL, - OPCODE_AE_MULZSSFQ32SP16U_LL, - OPCODE_AE_MULZSSQ32SP16S_HH, - OPCODE_AE_MULZSSFQ32SP16S_HH, - OPCODE_AE_MULZSSQ32SP16U_HH, - OPCODE_AE_MULZSSFQ32SP16U_HH, - OPCODE_AE_MULZSSQ32SP16S_LH, - OPCODE_AE_MULZSSFQ32SP16S_LH, - OPCODE_AE_MULZSSQ32SP16U_LH, - OPCODE_AE_MULZSSFQ32SP16U_LH, - OPCODE_AE_MULZAAFP24S_HH_LL, - OPCODE_AE_MULZAAP24S_HH_LL, - OPCODE_AE_MULZAAFP24S_HL_LH, - OPCODE_AE_MULZAAP24S_HL_LH, - OPCODE_AE_MULZASFP24S_HH_LL, - OPCODE_AE_MULZASP24S_HH_LL, - OPCODE_AE_MULZASFP24S_HL_LH, - OPCODE_AE_MULZASP24S_HL_LH, - OPCODE_AE_MULZSAFP24S_HH_LL, - OPCODE_AE_MULZSAP24S_HH_LL, - OPCODE_AE_MULZSAFP24S_HL_LH, - OPCODE_AE_MULZSAP24S_HL_LH, - OPCODE_AE_MULZSSFP24S_HH_LL, - OPCODE_AE_MULZSSP24S_HH_LL, - OPCODE_AE_MULZSSFP24S_HL_LH, - OPCODE_AE_MULZSSP24S_HL_LH, - OPCODE_AE_MULAAFP24S_HH_LL, - OPCODE_AE_MULAAP24S_HH_LL, - OPCODE_AE_MULAAFP24S_HL_LH, - OPCODE_AE_MULAAP24S_HL_LH, - OPCODE_AE_MULASFP24S_HH_LL, - OPCODE_AE_MULASP24S_HH_LL, - OPCODE_AE_MULASFP24S_HL_LH, - OPCODE_AE_MULASP24S_HL_LH, - OPCODE_AE_MULSAFP24S_HH_LL, - OPCODE_AE_MULSAP24S_HH_LL, - OPCODE_AE_MULSAFP24S_HL_LH, - OPCODE_AE_MULSAP24S_HL_LH, - OPCODE_AE_MULSSFP24S_HH_LL, - OPCODE_AE_MULSSP24S_HH_LL, - OPCODE_AE_MULSSFP24S_HL_LH, - OPCODE_AE_MULSSP24S_HL_LH, - OPCODE_AE_SHA32, - OPCODE_AE_VLDL32T, - OPCODE_AE_VLDL16T, - OPCODE_AE_VLDL16C, - OPCODE_AE_VLDSHT, - OPCODE_AE_LB, - OPCODE_AE_LBI, - OPCODE_AE_LBK, - OPCODE_AE_LBKI, - OPCODE_AE_DB, - OPCODE_AE_DBI, - OPCODE_AE_VLEL32T, - OPCODE_AE_VLEL16T, - OPCODE_AE_SB, - OPCODE_AE_SBI, - OPCODE_AE_VLES16C, - OPCODE_AE_SBF, - OPCODE_AE_SLAASQ56S, - OPCODE_AE_ADDBRBA32, - OPCODE_AE_MINABSSP24S, - OPCODE_AE_MAXABSSP24S, - OPCODE_AE_MINABSSQ56S, - OPCODE_AE_MAXABSSQ56S, - OPCODE_RUR_AE_CBEGIN0, - OPCODE_WUR_AE_CBEGIN0, - OPCODE_RUR_AE_CEND0, - OPCODE_WUR_AE_CEND0, - OPCODE_AE_LP24X2_C, - OPCODE_AE_SP24X2S_C, - OPCODE_AE_LP24X2F_C, - OPCODE_AE_SP24X2F_C, - OPCODE_AE_LP16X2F_C, - OPCODE_AE_SP16X2F_C, - OPCODE_AE_LP24_C, - OPCODE_AE_SP24S_L_C, - OPCODE_AE_LP24F_C, - OPCODE_AE_SP24F_L_C, - OPCODE_AE_LP16F_C, - OPCODE_AE_SP16F_L_C, - OPCODE_AE_LQ56_C, - OPCODE_AE_SQ56S_C, - OPCODE_AE_LQ32F_C, - OPCODE_AE_SQ32F_C -}; - - -/* Slot-specific opcode decode functions. */ - -static int -Slot_inst_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst_get (insn) == 0) - { - if (Field_op1_Slot_inst_get (insn) == 0) - { - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_r_Slot_inst_get (insn) == 0) - { - if (Field_m_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_n_Slot_inst_get (insn) == 0) - return OPCODE_ILL; - if (Field_m_Slot_inst_get (insn) == 2) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_RET; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_RETW; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_JX; - } - if (Field_m_Slot_inst_get (insn) == 3) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_CALLX0; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_CALLX4; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_CALLX8; - if (Field_n_Slot_inst_get (insn) == 3) - return OPCODE_CALLX12; - } - } - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_MOVSP; - if (Field_r_Slot_inst_get (insn) == 2) - { - if (Field_s_Slot_inst_get (insn) == 0) - { - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_ISYNC; - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RSYNC; - if (Field_t_Slot_inst_get (insn) == 2) - return OPCODE_ESYNC; - if (Field_t_Slot_inst_get (insn) == 3) - return OPCODE_DSYNC; - if (Field_t_Slot_inst_get (insn) == 8) - return OPCODE_EXCW; - if (Field_t_Slot_inst_get (insn) == 12) - return OPCODE_MEMW; - if (Field_t_Slot_inst_get (insn) == 13) - return OPCODE_EXTW; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_NOP; - } - } - if (Field_r_Slot_inst_get (insn) == 3) - { - if (Field_t_Slot_inst_get (insn) == 0) - { - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_RFE; - if (Field_s_Slot_inst_get (insn) == 2) - return OPCODE_RFDE; - if (Field_s_Slot_inst_get (insn) == 4) - return OPCODE_RFWO; - if (Field_s_Slot_inst_get (insn) == 5) - return OPCODE_RFWU; - } - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFI; - } - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_BREAK; - if (Field_r_Slot_inst_get (insn) == 5) - { - if (Field_s_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SYSCALL; - if (Field_s_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SIMCALL; - } - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_RSIL; - if (Field_r_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_WAITI; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_ANY4; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_ALL4; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_ANY8; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_ALL8; - } - if (Field_op2_Slot_inst_get (insn) == 1) - return OPCODE_AND; - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_OR; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_XOR; - if (Field_op2_Slot_inst_get (insn) == 4) - { - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSR; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSL; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8L; - if (Field_r_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8B; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_thi3_Slot_inst_get (insn) == 0) - return OPCODE_SSAI; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_RER; - if (Field_r_Slot_inst_get (insn) == 7) - return OPCODE_WER; - if (Field_r_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_ROTW; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_NSA; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_NSAU; - } - if (Field_op2_Slot_inst_get (insn) == 5) - { - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_RITLB0; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IITLB; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_PITLB; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_WITLB; - if (Field_r_Slot_inst_get (insn) == 7) - return OPCODE_RITLB1; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_RDTLB0; - if (Field_r_Slot_inst_get (insn) == 12 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IDTLB; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_PDTLB; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_WDTLB; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_RDTLB1; - } - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_NEG; - if (Field_s_Slot_inst_get (insn) == 1) - return OPCODE_ABS; - } - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_ADD; - if (Field_op2_Slot_inst_get (insn) == 9) - return OPCODE_ADDX2; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_ADDX4; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_ADDX8; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_SUB; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_SUBX2; - if (Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_SUBX4; - if (Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_SUBX8; - } - if (Field_op1_Slot_inst_get (insn) == 1) - { - if ((Field_op2_Slot_inst_get (insn) == 0 || - Field_op2_Slot_inst_get (insn) == 1)) - return OPCODE_SLLI; - if ((Field_op2_Slot_inst_get (insn) == 2 || - Field_op2_Slot_inst_get (insn) == 3)) - return OPCODE_SRAI; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_SRLI; - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_XSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_XSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_XSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_XSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_XSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_XSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_XSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_XSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_XSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 32) - return OPCODE_XSR_M0; - if (Field_sr_Slot_inst_get (insn) == 33) - return OPCODE_XSR_M1; - if (Field_sr_Slot_inst_get (insn) == 34) - return OPCODE_XSR_M2; - if (Field_sr_Slot_inst_get (insn) == 35) - return OPCODE_XSR_M3; - if (Field_sr_Slot_inst_get (insn) == 40) - return OPCODE_XSR_PREFCTL; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_XSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_XSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_XSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_XSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_XSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_XSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_XSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_XSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_XSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_XSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_XSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_XSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_XSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_XSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_XSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_XSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_XSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_XSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_XSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_XSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_XSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_XSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_XSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_XSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_XSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_XSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_XSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_XSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_XSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_XSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_XSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_XSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_XSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_XSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_XSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_XSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_XSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_XSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_XSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_XSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_XSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_XSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_XSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_XSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_XSR_CCOMPARE2; - } - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_SRC; - if (Field_op2_Slot_inst_get (insn) == 9 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRL; - if (Field_op2_Slot_inst_get (insn) == 10 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SLL; - if (Field_op2_Slot_inst_get (insn) == 11 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRA; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_MUL16U; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_MUL16S; - if (Field_op2_Slot_inst_get (insn) == 15) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_LICT; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_SICT; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_LICW; - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_SICW; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_LDCT; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_SDCT; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_RFDO; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFDD; - } - } - if (Field_op1_Slot_inst_get (insn) == 2) - { - if (Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_ANDB; - if (Field_op2_Slot_inst_get (insn) == 1) - return OPCODE_ANDBC; - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_ORB; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_ORBC; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_XORB; - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_MULL; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_MULUH; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_MULSH; - } - if (Field_op1_Slot_inst_get (insn) == 3) - { - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_RSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_RSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_RSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_RSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_RSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_RSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_RSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_RSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_RSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 32) - return OPCODE_RSR_M0; - if (Field_sr_Slot_inst_get (insn) == 33) - return OPCODE_RSR_M1; - if (Field_sr_Slot_inst_get (insn) == 34) - return OPCODE_RSR_M2; - if (Field_sr_Slot_inst_get (insn) == 35) - return OPCODE_RSR_M3; - if (Field_sr_Slot_inst_get (insn) == 40) - return OPCODE_RSR_PREFCTL; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_RSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_RSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_RSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_RSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_RSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_RSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_RSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_RSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_RSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_RSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_RSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 176) - return OPCODE_RSR_CONFIGID0; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_RSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_RSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_RSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_RSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_RSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_RSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_RSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_RSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_RSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_RSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_RSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_RSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_RSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_RSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 208) - return OPCODE_RSR_CONFIGID1; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_RSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_RSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_RSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_RSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_RSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_RSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_RSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_RSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 226) - return OPCODE_RSR_INTERRUPT; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_RSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_RSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_RSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_RSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_RSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_RSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 235) - return OPCODE_RSR_PRID; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_RSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_RSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_RSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_RSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_RSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_RSR_CCOMPARE2; - if (Field_sr_Slot_inst_get (insn) == 243) - return OPCODE_RSR_243; - } - if (Field_op2_Slot_inst_get (insn) == 1) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_WSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_WSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_WSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_WSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_WSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_WSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_WSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_WSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_WSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 32) - return OPCODE_WSR_M0; - if (Field_sr_Slot_inst_get (insn) == 33) - return OPCODE_WSR_M1; - if (Field_sr_Slot_inst_get (insn) == 34) - return OPCODE_WSR_M2; - if (Field_sr_Slot_inst_get (insn) == 35) - return OPCODE_WSR_M3; - if (Field_sr_Slot_inst_get (insn) == 40) - return OPCODE_WSR_PREFCTL; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_WSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_WSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_WSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_WSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_WSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_WSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_WSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_WSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_WSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_WSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_WSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 176) - return OPCODE_WSR_CONFIGID0; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_WSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_WSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_WSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_WSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_WSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_WSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_WSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_WSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_WSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_WSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_WSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_WSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_WSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_WSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_WSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_WSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_WSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_WSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_WSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_WSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_WSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_WSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 226) - return OPCODE_WSR_INTSET; - if (Field_sr_Slot_inst_get (insn) == 227) - return OPCODE_WSR_INTCLEAR; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_WSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_WSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_WSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_WSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_WSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_WSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_WSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_WSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_WSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_WSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_WSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_WSR_CCOMPARE2; - } - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_SEXT; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_CLAMPS; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_MIN; - if (Field_op2_Slot_inst_get (insn) == 5) - return OPCODE_MAX; - if (Field_op2_Slot_inst_get (insn) == 6) - return OPCODE_MINU; - if (Field_op2_Slot_inst_get (insn) == 7) - return OPCODE_MAXU; - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_MOVEQZ; - if (Field_op2_Slot_inst_get (insn) == 9) - return OPCODE_MOVNEZ; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_MOVLTZ; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_MOVGEZ; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_MOVF; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_MOVT; - if (Field_op2_Slot_inst_get (insn) == 14) - { - if (Field_st_Slot_inst_get (insn) == 231) - return OPCODE_RUR_THREADPTR; - if (Field_st_Slot_inst_get (insn) == 240) - return OPCODE_RUR_AE_OVF_SAR; - if (Field_st_Slot_inst_get (insn) == 241) - return OPCODE_RUR_AE_BITHEAD; - if (Field_st_Slot_inst_get (insn) == 242) - return OPCODE_RUR_AE_TS_FTS_BU_BP; - if (Field_st_Slot_inst_get (insn) == 243) - return OPCODE_RUR_AE_SD_NO; - if (Field_st_Slot_inst_get (insn) == 246) - return OPCODE_RUR_AE_CBEGIN0; - if (Field_st_Slot_inst_get (insn) == 247) - return OPCODE_RUR_AE_CEND0; - } - if (Field_op2_Slot_inst_get (insn) == 15) - { - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_WUR_THREADPTR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_WUR_AE_OVF_SAR; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_WUR_AE_BITHEAD; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_WUR_AE_TS_FTS_BU_BP; - if (Field_sr_Slot_inst_get (insn) == 243) - return OPCODE_WUR_AE_SD_NO; - if (Field_sr_Slot_inst_get (insn) == 246) - return OPCODE_WUR_AE_CBEGIN0; - if (Field_sr_Slot_inst_get (insn) == 247) - return OPCODE_WUR_AE_CEND0; - } - } - if ((Field_op1_Slot_inst_get (insn) == 4 || - Field_op1_Slot_inst_get (insn) == 5)) - return OPCODE_EXTUI; - if (Field_op1_Slot_inst_get (insn) == 9) - { - if (Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_L32E; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_S32E; - } - } - if (Field_op0_Slot_inst_get (insn) == 1) - return OPCODE_L32R; - if (Field_op0_Slot_inst_get (insn) == 2) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_L8UI; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_L16UI; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_L32I; - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_S8I; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_S16I; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_S32I; - if (Field_r_Slot_inst_get (insn) == 7) - { - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_DPFR; - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_DPFW; - if (Field_t_Slot_inst_get (insn) == 2) - return OPCODE_DPFRO; - if (Field_t_Slot_inst_get (insn) == 3) - return OPCODE_DPFWO; - if (Field_t_Slot_inst_get (insn) == 4) - return OPCODE_DHWB; - if (Field_t_Slot_inst_get (insn) == 5) - return OPCODE_DHWBI; - if (Field_t_Slot_inst_get (insn) == 6) - return OPCODE_DHI; - if (Field_t_Slot_inst_get (insn) == 7) - return OPCODE_DII; - if (Field_t_Slot_inst_get (insn) == 8) - { - if (Field_op1_Slot_inst_get (insn) == 0) - return OPCODE_DPFL; - if (Field_op1_Slot_inst_get (insn) == 2) - return OPCODE_DHU; - if (Field_op1_Slot_inst_get (insn) == 3) - return OPCODE_DIU; - if (Field_op1_Slot_inst_get (insn) == 4) - return OPCODE_DIWB; - if (Field_op1_Slot_inst_get (insn) == 5) - return OPCODE_DIWBI; - } - if (Field_t_Slot_inst_get (insn) == 12) - return OPCODE_IPF; - if (Field_t_Slot_inst_get (insn) == 13) - { - if (Field_op1_Slot_inst_get (insn) == 0) - return OPCODE_IPFL; - if (Field_op1_Slot_inst_get (insn) == 2) - return OPCODE_IHU; - if (Field_op1_Slot_inst_get (insn) == 3) - return OPCODE_IIU; - } - if (Field_t_Slot_inst_get (insn) == 14) - return OPCODE_IHI; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_III; - } - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_L16SI; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_MOVI; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_L32AI; - if (Field_r_Slot_inst_get (insn) == 12) - return OPCODE_ADDI; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_ADDMI; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_S32C1I; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_S32RI; - } - if (Field_op0_Slot_inst_get (insn) == 4) - { - if (Field_ae_r10_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_I; - if (Field_ae_r10_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_X; - if (Field_ae_r10_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_I; - if (Field_ae_r10_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_X; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_IU; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_XU; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_CVTQ48A32S; - if (Field_ae_r10_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_IU; - if (Field_ae_r10_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_ae_s3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVP48; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVPA24X2; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_CVTA32P24_L; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_LL; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_HL; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVAP24S_L; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCA16P24S_L; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP16X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24X2_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCP24A32X2; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_CVTA32P24_H; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_LH; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_HH; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVAP24S_H; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCA16P24S_H; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_I; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_X; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_TRUNCA32Q48; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_I; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_X; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_NSAQ56S; - if (Field_ae_r32_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_IU; - if (Field_ae_r32_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_XU; - if (Field_ae_r32_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_IU; - if (Field_ae_r32_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_XU; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRLIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRAIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLISQ56S; - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SHA32; - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLDL32T; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SLLAQ56; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLDL16T; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SRLAQ56; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LBK; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SRAAQ56; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLEL32T; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SLLASQ56S; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLEL16T; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_MOVTQ56; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_MOVFQ56; - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LL_LDINC; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HL_LDINC; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LH_LDINC; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HH_LDINC; - } - if (Field_op2_Slot_inst_get (insn) == 1) - { - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LL_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HL_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LH_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HH_LDDEC; - } - if (Field_op2_Slot_inst_get (insn) == 2) - { - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_LL; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_HL; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_LH; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_HH; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LL; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HL; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LH; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HH; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_LL; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_HL; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_LH; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_HH; - } - if (Field_op2_Slot_inst_get (insn) == 3) - { - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_LL; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_HL; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_LH; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_HH; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_LL; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_HL; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_LH; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_HH; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_LL; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_HL; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_LH; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_HH; - } - if (Field_op2_Slot_inst_get (insn) == 4) - { - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LL_LDINC; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HL_LDINC; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LH_LDINC; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HH_LDINC; - } - if (Field_op2_Slot_inst_get (insn) == 5) - { - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LL_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HL_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LH_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HH_LDDEC; - } - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_LL; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_HL; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_LH; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_HH; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LL; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HL; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LH; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HH; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_LL; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_HL; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_LH; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_HH; - } - if (Field_op2_Slot_inst_get (insn) == 7) - { - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_LL; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_HL; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_LH; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_HH; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_LL; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_HL; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_LH; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_HH; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_LL; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_HL; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_LH; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_HH; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_LL; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_HL; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_LH; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_HH; - } - if (Field_op2_Slot_inst_get (insn) == 8) - { - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_rhi_Slot_inst_get (insn) == 0) - return OPCODE_LDINC; - } - if (Field_op2_Slot_inst_get (insn) == 9) - { - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_rhi_Slot_inst_get (insn) == 0) - return OPCODE_LDDEC; - } - if (Field_r_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_OVERFLOW; - if (Field_r_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_SBI; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_SAR; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_DB; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_SB; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_BITPTR; - if (Field_r_Slot_inst_get (insn) == 3 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_BITSUSED; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_TABLESIZE; - if (Field_r_Slot_inst_get (insn) == 5 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_FIRST_TS; - if (Field_r_Slot_inst_get (insn) == 6 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_NEXTOFFSET; - if (Field_r_Slot_inst_get (insn) == 7 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_SEARCHDONE; - if (Field_r_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_VLDSHT; - if (Field_r_Slot_inst_get (insn) == 12 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_VLES16C; - if (Field_r_Slot_inst_get (insn) == 13 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SBF; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_VLDL16C; - if (Field_s_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLSQ56; - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LB; - if (Field_s_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRLSQ56; - if (Field_s_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRASQ56; - if (Field_s_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLSSQ56S; - if (Field_s_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVQ56; - if (Field_s_Slot_inst_get (insn) == 8 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_OVERFLOW; - if (Field_s_Slot_inst_get (insn) == 9 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_SAR; - if (Field_s_Slot_inst_get (insn) == 10 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_BITPTR; - if (Field_s_Slot_inst_get (insn) == 11 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_BITSUSED; - if (Field_s_Slot_inst_get (insn) == 12 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_TABLESIZE; - if (Field_s_Slot_inst_get (insn) == 13 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_FIRST_TS; - if (Field_s_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_NEXTOFFSET; - if (Field_s_Slot_inst_get (insn) == 15 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_SEARCHDONE; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_LBKI; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_r_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_DBI; - if (Field_t_Slot_inst_get (insn) == 2 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_LBI; - } - if (Field_op0_Slot_inst_get (insn) == 5) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_CALL0; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_CALL4; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_CALL8; - if (Field_n_Slot_inst_get (insn) == 3) - return OPCODE_CALL12; - } - if (Field_op0_Slot_inst_get (insn) == 6) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_J; - if (Field_n_Slot_inst_get (insn) == 1) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_BEQZ; - if (Field_m_Slot_inst_get (insn) == 1) - return OPCODE_BNEZ; - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTZ; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEZ; - } - if (Field_n_Slot_inst_get (insn) == 2) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_BEQI; - if (Field_m_Slot_inst_get (insn) == 1) - return OPCODE_BNEI; - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTI; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEI; - } - if (Field_n_Slot_inst_get (insn) == 3) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_ENTRY; - if (Field_m_Slot_inst_get (insn) == 1) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_BF; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_BT; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_LOOP; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_LOOPNEZ; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_LOOPGTZ; - } - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTUI; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEUI; - } - } - if (Field_op0_Slot_inst_get (insn) == 7) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_BNONE; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_BEQ; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_BLT; - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_BLTU; - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_BALL; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_BBC; - if ((Field_r_Slot_inst_get (insn) == 6 || - Field_r_Slot_inst_get (insn) == 7)) - return OPCODE_BBCI; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_BANY; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_BNE; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_BGE; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_BGEU; - if (Field_r_Slot_inst_get (insn) == 12) - return OPCODE_BNALL; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_BBS; - if ((Field_r_Slot_inst_get (insn) == 14 || - Field_r_Slot_inst_get (insn) == 15)) - return OPCODE_BBSI; - } - return 0; -} - -static int -Slot_inst16b_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst16b_get (insn) == 12) - { - if (Field_i_Slot_inst16b_get (insn) == 0) - return OPCODE_MOVI_N; - if (Field_i_Slot_inst16b_get (insn) == 1) - { - if (Field_z_Slot_inst16b_get (insn) == 0) - return OPCODE_BEQZ_N; - if (Field_z_Slot_inst16b_get (insn) == 1) - return OPCODE_BNEZ_N; - } - } - if (Field_op0_Slot_inst16b_get (insn) == 13) - { - if (Field_r_Slot_inst16b_get (insn) == 0) - return OPCODE_MOV_N; - if (Field_r_Slot_inst16b_get (insn) == 15) - { - if (Field_t_Slot_inst16b_get (insn) == 0) - return OPCODE_RET_N; - if (Field_t_Slot_inst16b_get (insn) == 1) - return OPCODE_RETW_N; - if (Field_t_Slot_inst16b_get (insn) == 2) - return OPCODE_BREAK_N; - if (Field_t_Slot_inst16b_get (insn) == 3 && - Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_NOP_N; - if (Field_t_Slot_inst16b_get (insn) == 6 && - Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_ILL_N; - } - } - return 0; -} - -static int -Slot_inst16a_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst16a_get (insn) == 8) - return OPCODE_L32I_N; - if (Field_op0_Slot_inst16a_get (insn) == 9) - return OPCODE_S32I_N; - if (Field_op0_Slot_inst16a_get (insn) == 10) - return OPCODE_ADD_N; - if (Field_op0_Slot_inst16a_get (insn) == 11) - return OPCODE_ADDI_N; - return 0; -} - -static int -Slot_ae_slot0_decode (const xtensa_insnbuf insn) -{ - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_ADDBRBA32; - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 2 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_C; - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 2 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_C; - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 2 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_C; - if (Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf353_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_C; - if (Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_C; - if (Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_C; - if (Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_get (insn) == 2 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_C; - if (Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_C; - if (Field_combined1b97e84f_fld93_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld90_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_C; - if (Field_combined4b12daa6_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld85_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld122_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld119_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld97_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SELP24_LH; - if (Field_combined4b12daa6_fld122_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld85_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld119_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld97_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SELP24_HH; - if (Field_combined4b12daa6_fld122_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld85_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld119_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld97_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SELP24_HL; - if (Field_combined4b12daa6_fld85_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld122_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld119_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld97_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined4b12daa6_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 && - Field_combined4b12daa6_fld115_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SELP24_LL; - if (Field_ftsf212ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_J; - if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_EXTUI; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BGEZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BLTZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 8 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BEQZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 9 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BNEZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVI; - if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 88 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRAI; - if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 96 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SLLI; - if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 123 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVTQ56; - if (Field_ftsf216ae_slot0_Slot_ae_slot0_get (insn) == 418 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_HH; - if (Field_ftsf217_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4 && - Field_ae_r20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_L32I; - if (Field_ftsf218ae_slot0_Slot_ae_slot0_get (insn) == 419 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_I; - if (Field_ftsf219ae_slot0_Slot_ae_slot0_get (insn) == 420 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_HL; - if (Field_ftsf220ae_slot0_Slot_ae_slot0_get (insn) == 421 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_IU; - if (Field_ftsf221ae_slot0_Slot_ae_slot0_get (insn) == 422 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_X; - if (Field_ftsf222ae_slot0_Slot_ae_slot0_get (insn) == 423 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_XU; - if (Field_ftsf223ae_slot0_Slot_ae_slot0_get (insn) == 424 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_LH; - if (Field_ftsf224ae_slot0_Slot_ae_slot0_get (insn) == 425 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_I; - if (Field_ftsf225ae_slot0_Slot_ae_slot0_get (insn) == 426 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_IU; - if (Field_ftsf226ae_slot0_Slot_ae_slot0_get (insn) == 427 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_XU; - if (Field_ftsf227ae_slot0_Slot_ae_slot0_get (insn) == 428 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_X; - if (Field_ftsf228ae_slot0_Slot_ae_slot0_get (insn) == 429 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_I; - if (Field_ftsf229ae_slot0_Slot_ae_slot0_get (insn) == 430 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_IU; - if (Field_ftsf230ae_slot0_Slot_ae_slot0_get (insn) == 431 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_X; - if (Field_ftsf231ae_slot0_Slot_ae_slot0_get (insn) == 432 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_LL; - if (Field_ftsf232ae_slot0_Slot_ae_slot0_get (insn) == 433 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_XU; - if (Field_ftsf233ae_slot0_Slot_ae_slot0_get (insn) == 434 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_I; - if (Field_ftsf234ae_slot0_Slot_ae_slot0_get (insn) == 435 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_XU; - if (Field_ftsf235ae_slot0_Slot_ae_slot0_get (insn) == 436 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_IU; - if (Field_ftsf236ae_slot0_Slot_ae_slot0_get (insn) == 437 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_I; - if (Field_ftsf237ae_slot0_Slot_ae_slot0_get (insn) == 438 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_IU; - if (Field_ftsf238ae_slot0_Slot_ae_slot0_get (insn) == 439 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_X; - if (Field_ftsf239ae_slot0_Slot_ae_slot0_get (insn) == 440 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_X; - if (Field_ftsf240ae_slot0_Slot_ae_slot0_get (insn) == 441 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_XU; - if (Field_ftsf241ae_slot0_Slot_ae_slot0_get (insn) == 442 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_I; - if (Field_ftsf242ae_slot0_Slot_ae_slot0_get (insn) == 443 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_X; - if (Field_ftsf243ae_slot0_Slot_ae_slot0_get (insn) == 444 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_IU; - if (Field_ftsf244ae_slot0_Slot_ae_slot0_get (insn) == 445 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_XU; - if (Field_ftsf245ae_slot0_Slot_ae_slot0_get (insn) == 446 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVPA24X2; - if (Field_ftsf246ae_slot0_Slot_ae_slot0_get (insn) == 447 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_I; - if (Field_ftsf247ae_slot0_Slot_ae_slot0_get (insn) == 450 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_IU; - if (Field_ftsf248ae_slot0_Slot_ae_slot0_get (insn) == 451 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_X; - if (Field_ftsf249ae_slot0_Slot_ae_slot0_get (insn) == 452 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_X; - if (Field_ftsf250ae_slot0_Slot_ae_slot0_get (insn) == 453 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_XU; - if (Field_ftsf251ae_slot0_Slot_ae_slot0_get (insn) == 454 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_I; - if (Field_ftsf252ae_slot0_Slot_ae_slot0_get (insn) == 455 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_IU; - if (Field_ftsf253ae_slot0_Slot_ae_slot0_get (insn) == 456 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_XU; - if (Field_ftsf254ae_slot0_Slot_ae_slot0_get (insn) == 457 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_X; - if (Field_ftsf255ae_slot0_Slot_ae_slot0_get (insn) == 458 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_XU; - if (Field_ftsf256ae_slot0_Slot_ae_slot0_get (insn) == 459 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_IU; - if (Field_ftsf257ae_slot0_Slot_ae_slot0_get (insn) == 460 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_I; - if (Field_ftsf258ae_slot0_Slot_ae_slot0_get (insn) == 461 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_X; - if (Field_ftsf259ae_slot0_Slot_ae_slot0_get (insn) == 462 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_XU; - if (Field_ftsf260ae_slot0_Slot_ae_slot0_get (insn) == 463 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_I; - if (Field_ftsf261ae_slot0_Slot_ae_slot0_get (insn) == 464 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_I; - if (Field_ftsf262ae_slot0_Slot_ae_slot0_get (insn) == 465 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_IU; - if (Field_ftsf263ae_slot0_Slot_ae_slot0_get (insn) == 466 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_X; - if (Field_ftsf264ae_slot0_Slot_ae_slot0_get (insn) == 467 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_IU; - if (Field_ftsf265ae_slot0_Slot_ae_slot0_get (insn) == 468 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_XU; - if (Field_ftsf266ae_slot0_Slot_ae_slot0_get (insn) == 469 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_X; - if (Field_ftsf267ae_slot0_Slot_ae_slot0_get (insn) == 470 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_XU; - if (Field_ftsf268ae_slot0_Slot_ae_slot0_get (insn) == 471 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_TRUNCP24A32X2; - if (Field_ftsf269ae_slot0_Slot_ae_slot0_get (insn) == 472 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_I; - if (Field_ftsf270ae_slot0_Slot_ae_slot0_get (insn) == 946 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_I; - if (Field_ftsf271ae_slot0_Slot_ae_slot0_get (insn) == 947 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_IU; - if (Field_ftsf272ae_slot0_Slot_ae_slot0_get (insn) == 948 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_I; - if (Field_ftsf273ae_slot0_Slot_ae_slot0_get (insn) == 949 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_X; - if (Field_ftsf274ae_slot0_Slot_ae_slot0_get (insn) == 950 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_XU; - if (Field_ftsf275ae_slot0_Slot_ae_slot0_get (insn) == 951 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_I; - if (Field_ftsf276ae_slot0_Slot_ae_slot0_get (insn) == 952 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_IU; - if (Field_ftsf277ae_slot0_Slot_ae_slot0_get (insn) == 953 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_IU; - if (Field_ftsf278ae_slot0_Slot_ae_slot0_get (insn) == 954 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_X; - if (Field_ftsf279ae_slot0_Slot_ae_slot0_get (insn) == 15280 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTQ48A32S; - if (Field_ftsf281ae_slot0_Slot_ae_slot0_get (insn) == 60977 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_JX; - if (Field_ftsf282ae_slot0_Slot_ae_slot0_get (insn) == 61041 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SSR; - if (Field_ftsf283ae_slot0_Slot_ae_slot0_get (insn) == 30577 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf352ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_NOP; - if (Field_ftsf284ae_slot0_Slot_ae_slot0_get (insn) == 7641 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf354ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSA8B; - if (Field_ftsf286ae_slot0_Slot_ae_slot0_get (insn) == 3821 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf356ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSA8L; - if (Field_ftsf288ae_slot0_Slot_ae_slot0_get (insn) == 1911 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf359ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSL; - if (Field_ftsf290ae_slot0_Slot_ae_slot0_get (insn) == 478 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s8_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_LQ56_XU; - if (Field_ftsf292ae_slot0_Slot_ae_slot0_get (insn) == 1913 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ALL8; - if (Field_ftsf293_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBCI; - if (Field_ftsf293_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBSI; - if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 1915 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ANY8; - if (Field_ftsf295ae_slot0_Slot_ae_slot0_get (insn) == 959 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf358ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSAI; - if (Field_ftsf296ae_slot0_Slot_ae_slot0_get (insn) == 480 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_IU; - if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 962 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_I; - if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 963 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_IU; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 964 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLIQ56; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 965 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SRAIQ56; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 966 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SRLIQ56; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 968 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLISQ56S; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3868 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ABS; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3869 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_NEG; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3870 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRA; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3871 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRL; - if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7752 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf321_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVP48; - if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7753 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf353_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ANY4; - if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 31016 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf321_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVQ56; - if (Field_ftsf303ae_slot0_Slot_ae_slot0_get (insn) == 31017 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf321_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SLLSSQ56S; - if (Field_ftsf304ae_slot0_Slot_ae_slot0_get (insn) == 15509 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf369ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRASQ56; - if (Field_ftsf306ae_slot0_Slot_ae_slot0_get (insn) == 7755 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf368ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRLSQ56; - if (Field_ftsf308ae_slot0_Slot_ae_slot0_get (insn) == 1939 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf366ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SLLSQ56; - if (Field_ftsf309ae_slot0_Slot_ae_slot0_get (insn) == 485 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ALL4; - if (Field_ftsf310ae_slot0_Slot_ae_slot0_get (insn) == 972 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_X; - if (Field_ftsf311ae_slot0_Slot_ae_slot0_get (insn) == 973 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_XU; - if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 7792 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTA32P24_H; - if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 7793 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTA32P24_L; - if (Field_ftsf314ae_slot0_Slot_ae_slot0_get (insn) == 7794 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVAP24S_H; - if (Field_ftsf315ae_slot0_Slot_ae_slot0_get (insn) == 7795 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_TRUNCA16P24S_L; - if (Field_ftsf316ae_slot0_Slot_ae_slot0_get (insn) == 7796 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVAP24S_L; - if (Field_ftsf317ae_slot0_Slot_ae_slot0_get (insn) == 7797 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf353_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_NSAQ56S; - if (Field_ftsf318ae_slot0_Slot_ae_slot0_get (insn) == 3899 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf365ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_TRUNCA32Q48; - if (Field_ftsf319_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_ftsf361ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BT; - if (Field_ftsf320ae_slot0_Slot_ae_slot0_get (insn) == 975 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_TRUNCA16P24S_H; - if (Field_ftsf321_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_ae_s20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BLTUI; - if (Field_ftsf321_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld101_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld88_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld39_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 3 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLAASQ56S; - if (Field_ftsf322ae_slot0_Slot_ae_slot0_get (insn) == 3920 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVFQ56; - if (Field_ftsf323ae_slot0_Slot_ae_slot0_get (insn) == 3921 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLAQ56; - if (Field_ftsf324ae_slot0_Slot_ae_slot0_get (insn) == 3922 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLASQ56S; - if (Field_ftsf325ae_slot0_Slot_ae_slot0_get (insn) == 3923 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SLL; - if (Field_ftsf326ae_slot0_Slot_ae_slot0_get (insn) == 981 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf357_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRAAQ56; - if (Field_ftsf328ae_slot0_Slot_ae_slot0_get (insn) == 491 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRLAQ56; - if (Field_ftsf329ae_slot0_Slot_ae_slot0_get (insn) == 31 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SQ32F_XU; - if (Field_ftsf353_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld115_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld83_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld97_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld124_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld79_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld80_Slot_ae_slot0_get (insn) == 1 && - Field_combined1b97e84f_fld108_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_C; - if (Field_imm8_Slot_ae_slot0_get (insn) == 178 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADD; - if (Field_imm8_Slot_ae_slot0_get (insn) == 179 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX8; - if (Field_imm8_Slot_ae_slot0_get (insn) == 180 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX2; - if (Field_imm8_Slot_ae_slot0_get (insn) == 181 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AND; - if (Field_imm8_Slot_ae_slot0_get (insn) == 182 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ANDB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 183 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ANDBC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 184 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX4; - if (Field_imm8_Slot_ae_slot0_get (insn) == 185 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_CLAMPS; - if (Field_imm8_Slot_ae_slot0_get (insn) == 186 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MAX; - if (Field_imm8_Slot_ae_slot0_get (insn) == 187 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MIN; - if (Field_imm8_Slot_ae_slot0_get (insn) == 188 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MAXU; - if (Field_imm8_Slot_ae_slot0_get (insn) == 189 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MINU; - if (Field_imm8_Slot_ae_slot0_get (insn) == 190 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVEQZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 191 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVF; - if (Field_imm8_Slot_ae_slot0_get (insn) == 194 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVGEZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 195 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ORB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 196 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVLTZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 197 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ORBC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 198 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SEXT; - if (Field_imm8_Slot_ae_slot0_get (insn) == 199 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 200 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVNEZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 201 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRLI; - if (Field_imm8_Slot_ae_slot0_get (insn) == 202 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 203 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX4; - if (Field_imm8_Slot_ae_slot0_get (insn) == 204 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX2; - if (Field_imm8_Slot_ae_slot0_get (insn) == 205 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX8; - if (Field_imm8_Slot_ae_slot0_get (insn) == 206 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_XOR; - if (Field_imm8_Slot_ae_slot0_get (insn) == 207 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_XORB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 208 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVT; - if (Field_imm8_Slot_ae_slot0_get (insn) == 224 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_OR; - if (Field_imm8_Slot_ae_slot0_get (insn) == 244 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_r32_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SQ32F_X; - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5) - return OPCODE_L32R; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 0 && - Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP16X2F_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 6 && - Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP24F_L_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 7 && - Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP24S_L_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 8 && - Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP24X2F_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 9 && - Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SP24X2S_C; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 10 && - Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_LQ56_C; - if (Field_r_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_BNE; - if (Field_r_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_BNONE; - if (Field_r_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L16SI; - if (Field_r_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L8UI; - if (Field_r_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_ADDI; - if (Field_r_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L16UI; - if (Field_r_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BALL; - if (Field_r_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S16I; - if (Field_r_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BANY; - if (Field_r_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S32I; - if (Field_r_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBC; - if (Field_r_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S8I; - if (Field_r_Slot_ae_slot0_get (insn) == 8 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_ADDMI; - if (Field_r_Slot_ae_slot0_get (insn) == 9 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBS; - if (Field_r_Slot_ae_slot0_get (insn) == 10 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BEQ; - if (Field_r_Slot_ae_slot0_get (insn) == 11 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BGEU; - if (Field_r_Slot_ae_slot0_get (insn) == 12 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BGE; - if (Field_r_Slot_ae_slot0_get (insn) == 13 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BLT; - if (Field_r_Slot_ae_slot0_get (insn) == 14 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BLTU; - if (Field_r_Slot_ae_slot0_get (insn) == 15 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BNALL; - if (Field_t_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BEQI; - if (Field_t_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BGEI; - if (Field_t_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BGEUI; - if (Field_t_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BNEI; - if (Field_t_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BLTI; - if (Field_t_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_r_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BF; - return 0; -} - -static int -Slot_ae_slot1_decode (const xtensa_insnbuf insn) -{ - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 288 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULRFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 289 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULRFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 290 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULARFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 291 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULARFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 292 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSRFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 293 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSRFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 294 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 295 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 296 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 297 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 298 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 299 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP24S_L; - if (Field_combined1b97e84f_fld17_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld76_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf208_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld73_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld62_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld24_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld70_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld58_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5 && - Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MINABSSQ56S; - if (Field_combined1b97e84f_fld49_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf338_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld54_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r32_Slot_ae_slot1_get (insn) == 2 && - Field_combined1b97e84f_fld51_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld23_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MINABSSP24S; - if (Field_combined1b97e84f_fld49_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf338_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld54_Slot_ae_slot1_get (insn) == 0 && - Field_ae_r32_Slot_ae_slot1_get (insn) == 2 && - Field_combined1b97e84f_fld51_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld23_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MAXABSSP24S; - if (Field_combined1b97e84f_fld54_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld17_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld76_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf208_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld73_Slot_ae_slot1_get (insn) == 1 && - Field_combined1b97e84f_fld62_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld24_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld70_Slot_ae_slot1_get (insn) == 0 && - Field_combined1b97e84f_fld58_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MAXABSSQ56S; - if (Field_ftsf100ae_slot1_Slot_ae_slot1_get (insn) == 115 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_NEGSP24S; - if (Field_ftsf101ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf348ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ABSSP24S; - if (Field_ftsf103ae_slot1_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf349ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_NEGP24; - if (Field_ftsf104ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MAXBQ56S; - if (Field_ftsf105ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MINBQ56S; - if (Field_ftsf106ae_slot1_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ae_r32_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_EQQ56; - if (Field_ftsf107ae_slot1_Slot_ae_slot1_get (insn) == 48 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ADDSQ56S; - if (Field_ftsf108ae_slot1_Slot_ae_slot1_get (insn) == 49 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ANDQ56; - if (Field_ftsf109ae_slot1_Slot_ae_slot1_get (insn) == 50 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MAXQ56S; - if (Field_ftsf110ae_slot1_Slot_ae_slot1_get (insn) == 51 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ORQ56; - if (Field_ftsf111ae_slot1_Slot_ae_slot1_get (insn) == 52 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MINQ56S; - if (Field_ftsf112ae_slot1_Slot_ae_slot1_get (insn) == 53 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_SUBQ56; - if (Field_ftsf113ae_slot1_Slot_ae_slot1_get (insn) == 54 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_SUBSQ56S; - if (Field_ftsf114ae_slot1_Slot_ae_slot1_get (insn) == 55 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_XORQ56; - if (Field_ftsf115ae_slot1_Slot_ae_slot1_get (insn) == 56 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_NANDQ56; - if (Field_ftsf116ae_slot1_Slot_ae_slot1_get (insn) == 57 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ABSQ56; - if (Field_ftsf118ae_slot1_Slot_ae_slot1_get (insn) == 185 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_NEGSQ56S; - if (Field_ftsf119ae_slot1_Slot_ae_slot1_get (insn) == 185 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf338_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_SATQ48S; - if (Field_ftsf12_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf341ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LTQ56S; - if (Field_ftsf120ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf343ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ABSSQ56S; - if (Field_ftsf122ae_slot1_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf346ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_NEGQ56; - if (Field_ftsf124ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf339ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LEQ56S; - if (Field_ftsf125ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf350ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_TRUNCP24Q48X2; - if (Field_ftsf126ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ADDQ56; - if (Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAFP24S_HH_LL; - if (Field_ftsf128ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAFP24S_HL_LH; - if (Field_ftsf129ae_slot1_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAP24S_HH_LL; - if (Field_ftsf13_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf12_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_SLLISP24S; - if (Field_ftsf130ae_slot1_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_HL; - if (Field_ftsf131ae_slot1_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAP24S_HL_LH; - if (Field_ftsf132ae_slot1_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_LH; - if (Field_ftsf133ae_slot1_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_LL; - if (Field_ftsf134ae_slot1_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_HH; - if (Field_ftsf135ae_slot1_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_HH; - if (Field_ftsf136ae_slot1_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_HL; - if (Field_ftsf137ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_LH; - if (Field_ftsf138ae_slot1_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_HH; - if (Field_ftsf139ae_slot1_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_LL; - if (Field_ftsf140ae_slot1_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_HL; - if (Field_ftsf141ae_slot1_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_LH; - if (Field_ftsf142ae_slot1_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_LL; - if (Field_ftsf143ae_slot1_Slot_ae_slot1_get (insn) == 16 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_HL; - if (Field_ftsf144ae_slot1_Slot_ae_slot1_get (insn) == 17 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_HH; - if (Field_ftsf145ae_slot1_Slot_ae_slot1_get (insn) == 18 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_HL; - if (Field_ftsf146ae_slot1_Slot_ae_slot1_get (insn) == 19 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASFP24S_HH_LL; - if (Field_ftsf147ae_slot1_Slot_ae_slot1_get (insn) == 20 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_LH; - if (Field_ftsf148ae_slot1_Slot_ae_slot1_get (insn) == 21 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASFP24S_HL_LH; - if (Field_ftsf149ae_slot1_Slot_ae_slot1_get (insn) == 22 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASP24S_HH_LL; - if (Field_ftsf150ae_slot1_Slot_ae_slot1_get (insn) == 23 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASP24S_HL_LH; - if (Field_ftsf151ae_slot1_Slot_ae_slot1_get (insn) == 24 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_LL; - if (Field_ftsf152ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_HH; - if (Field_ftsf153ae_slot1_Slot_ae_slot1_get (insn) == 26 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_HL; - if (Field_ftsf154ae_slot1_Slot_ae_slot1_get (insn) == 27 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_LL; - if (Field_ftsf155ae_slot1_Slot_ae_slot1_get (insn) == 28 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_LH; - if (Field_ftsf156ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_HH; - if (Field_ftsf157ae_slot1_Slot_ae_slot1_get (insn) == 30 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_HL; - if (Field_ftsf158ae_slot1_Slot_ae_slot1_get (insn) == 31 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_LH; - if (Field_ftsf159ae_slot1_Slot_ae_slot1_get (insn) == 32 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_LH; - if (Field_ftsf160ae_slot1_Slot_ae_slot1_get (insn) == 33 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_LL; - if (Field_ftsf161ae_slot1_Slot_ae_slot1_get (insn) == 34 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_HH; - if (Field_ftsf162ae_slot1_Slot_ae_slot1_get (insn) == 35 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAFP24S_HH_LL; - if (Field_ftsf163ae_slot1_Slot_ae_slot1_get (insn) == 36 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_HL; - if (Field_ftsf164ae_slot1_Slot_ae_slot1_get (insn) == 37 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAFP24S_HL_LH; - if (Field_ftsf165ae_slot1_Slot_ae_slot1_get (insn) == 38 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAP24S_HH_LL; - if (Field_ftsf166ae_slot1_Slot_ae_slot1_get (insn) == 39 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAP24S_HL_LH; - if (Field_ftsf167ae_slot1_Slot_ae_slot1_get (insn) == 40 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_LH; - if (Field_ftsf168ae_slot1_Slot_ae_slot1_get (insn) == 41 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_HH; - if (Field_ftsf169ae_slot1_Slot_ae_slot1_get (insn) == 42 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_HL; - if (Field_ftsf170ae_slot1_Slot_ae_slot1_get (insn) == 43 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_LL; - if (Field_ftsf171ae_slot1_Slot_ae_slot1_get (insn) == 44 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_LH; - if (Field_ftsf172ae_slot1_Slot_ae_slot1_get (insn) == 45 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_HH; - if (Field_ftsf173ae_slot1_Slot_ae_slot1_get (insn) == 46 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_HL; - if (Field_ftsf174ae_slot1_Slot_ae_slot1_get (insn) == 47 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_LH; - if (Field_ftsf175ae_slot1_Slot_ae_slot1_get (insn) == 48 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_LL; - if (Field_ftsf176ae_slot1_Slot_ae_slot1_get (insn) == 49 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_LL; - if (Field_ftsf177ae_slot1_Slot_ae_slot1_get (insn) == 50 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_HH; - if (Field_ftsf178ae_slot1_Slot_ae_slot1_get (insn) == 51 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_LL; - if (Field_ftsf179ae_slot1_Slot_ae_slot1_get (insn) == 52 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_HL; - if (Field_ftsf180ae_slot1_Slot_ae_slot1_get (insn) == 53 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_HH; - if (Field_ftsf181ae_slot1_Slot_ae_slot1_get (insn) == 54 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_HL; - if (Field_ftsf182ae_slot1_Slot_ae_slot1_get (insn) == 55 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_LH; - if (Field_ftsf183ae_slot1_Slot_ae_slot1_get (insn) == 56 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_LH; - if (Field_ftsf184ae_slot1_Slot_ae_slot1_get (insn) == 57 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_LL; - if (Field_ftsf185ae_slot1_Slot_ae_slot1_get (insn) == 58 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_HH; - if (Field_ftsf186ae_slot1_Slot_ae_slot1_get (insn) == 59 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_LH; - if (Field_ftsf187ae_slot1_Slot_ae_slot1_get (insn) == 60 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_HL; - if (Field_ftsf188ae_slot1_Slot_ae_slot1_get (insn) == 61 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_LL; - if (Field_ftsf189ae_slot1_Slot_ae_slot1_get (insn) == 62 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSFP24S_HH_LL; - if (Field_ftsf190ae_slot1_Slot_ae_slot1_get (insn) == 63 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSFP24S_HL_LH; - if (Field_ftsf191ae_slot1_Slot_ae_slot1_get (insn) == 64 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_LL; - if (Field_ftsf192ae_slot1_Slot_ae_slot1_get (insn) == 65 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSP24S_HH_LL; - if (Field_ftsf193ae_slot1_Slot_ae_slot1_get (insn) == 66 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSP24S_HL_LH; - if (Field_ftsf194ae_slot1_Slot_ae_slot1_get (insn) == 67 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASFP24S_HH_LL; - if (Field_ftsf195ae_slot1_Slot_ae_slot1_get (insn) == 68 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZAAFP24S_HH_LL; - if (Field_ftsf196ae_slot1_Slot_ae_slot1_get (insn) == 69 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASFP24S_HL_LH; - if (Field_ftsf197ae_slot1_Slot_ae_slot1_get (insn) == 70 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASP24S_HH_LL; - if (Field_ftsf198ae_slot1_Slot_ae_slot1_get (insn) == 71 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASP24S_HL_LH; - if (Field_ftsf199ae_slot1_Slot_ae_slot1_get (insn) == 72 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZAAFP24S_HL_LH; - if (Field_ftsf200ae_slot1_Slot_ae_slot1_get (insn) == 73 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAFP24S_HH_LL; - if (Field_ftsf201ae_slot1_Slot_ae_slot1_get (insn) == 74 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAFP24S_HL_LH; - if (Field_ftsf202ae_slot1_Slot_ae_slot1_get (insn) == 75 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAP24S_HL_LH; - if (Field_ftsf203ae_slot1_Slot_ae_slot1_get (insn) == 76 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAP24S_HH_LL; - if (Field_ftsf204ae_slot1_Slot_ae_slot1_get (insn) == 77 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSFP24S_HH_LL; - if (Field_ftsf205ae_slot1_Slot_ae_slot1_get (insn) == 78 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSFP24S_HL_LH; - if (Field_ftsf206ae_slot1_Slot_ae_slot1_get (insn) == 79 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSP24S_HH_LL; - if (Field_ftsf207ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZAAP24S_HH_LL; - if (Field_ftsf209ae_slot1_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZSSP24S_HL_LH; - if (Field_ftsf210ae_slot1_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf337ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZAAP24S_HL_LH; - if (Field_ftsf211ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf332ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULAFS32P16S_HH; - if (Field_ftsf21ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MAXBP24S; - if (Field_ftsf22ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MINBP24S; - if (Field_ftsf23ae_slot1_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVFP48; - if (Field_ftsf24ae_slot1_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVTP48; - if (Field_ftsf25ae_slot1_Slot_ae_slot1_get (insn) == 20 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ADDP24; - if (Field_ftsf26ae_slot1_Slot_ae_slot1_get (insn) == 21 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ANDP48; - if (Field_ftsf27ae_slot1_Slot_ae_slot1_get (insn) == 22 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MAXP24S; - if (Field_ftsf28ae_slot1_Slot_ae_slot1_get (insn) == 23 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MINP24S; - if (Field_ftsf29ae_slot1_Slot_ae_slot1_get (insn) == 24 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ADDSP24S; - if (Field_ftsf30ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_NANDP48; - if (Field_ftsf31ae_slot1_Slot_ae_slot1_get (insn) == 26 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ORP48; - if (Field_ftsf32ae_slot1_Slot_ae_slot1_get (insn) == 27 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_HL; - if (Field_ftsf33ae_slot1_Slot_ae_slot1_get (insn) == 28 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_HH; - if (Field_ftsf34ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_LH; - if (Field_ftsf35ae_slot1_Slot_ae_slot1_get (insn) == 30 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_LL; - if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 31 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SUBP24; - if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SLLIP24; - if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRAIP24; - if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRLIP24; - if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 176 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16S_L; - if (Field_ftsf39ae_slot1_Slot_ae_slot1_get (insn) == 177 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16U_H; - if (Field_ftsf40ae_slot1_Slot_ae_slot1_get (insn) == 178 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16U_L; - if (Field_ftsf41ae_slot1_Slot_ae_slot1_get (insn) == 179 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16U_H; - if (Field_ftsf42ae_slot1_Slot_ae_slot1_get (insn) == 180 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16S_H; - if (Field_ftsf43ae_slot1_Slot_ae_slot1_get (insn) == 181 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16U_L; - if (Field_ftsf44ae_slot1_Slot_ae_slot1_get (insn) == 182 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16S_H; - if (Field_ftsf45ae_slot1_Slot_ae_slot1_get (insn) == 183 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16S_L; - if (Field_ftsf46ae_slot1_Slot_ae_slot1_get (insn) == 184 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16S_L; - if (Field_ftsf47ae_slot1_Slot_ae_slot1_get (insn) == 185 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16U_H; - if (Field_ftsf48ae_slot1_Slot_ae_slot1_get (insn) == 186 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16U_L; - if (Field_ftsf49ae_slot1_Slot_ae_slot1_get (insn) == 187 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16S_L; - if (Field_ftsf50ae_slot1_Slot_ae_slot1_get (insn) == 188 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16S_H; - if (Field_ftsf51ae_slot1_Slot_ae_slot1_get (insn) == 189 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16U_H; - if (Field_ftsf52ae_slot1_Slot_ae_slot1_get (insn) == 190 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16U_L; - if (Field_ftsf53ae_slot1_Slot_ae_slot1_get (insn) == 191 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16S_H; - if (Field_ftsf54ae_slot1_Slot_ae_slot1_get (insn) == 192 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16S_H; - if (Field_ftsf55ae_slot1_Slot_ae_slot1_get (insn) == 193 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16S_L; - if (Field_ftsf56ae_slot1_Slot_ae_slot1_get (insn) == 194 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16U_H; - if (Field_ftsf57ae_slot1_Slot_ae_slot1_get (insn) == 195 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSQ32SP16U_L; - if (Field_ftsf58ae_slot1_Slot_ae_slot1_get (insn) == 196 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16U_L; - if (Field_ftsf59ae_slot1_Slot_ae_slot1_get (insn) == 773 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_CVTQ48P24S_H; - if (Field_ftsf60ae_slot1_Slot_ae_slot1_get (insn) == 789 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ZEROQ56; - if (Field_ftsf61ae_slot1_Slot_ae_slot1_get (insn) == 405 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf330ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_NOP; - if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 198 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r10_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_CVTQ48P24S_L; - if (Field_ftsf64ae_slot1_Slot_ae_slot1_get (insn) == 1543 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVQ56; - if (Field_ftsf66ae_slot1_Slot_ae_slot1_get (insn) == 1559 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSQ32ASYM; - if (Field_ftsf67ae_slot1_Slot_ae_slot1_get (insn) == 791 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSQ32SYM; - if (Field_ftsf69ae_slot1_Slot_ae_slot1_get (insn) == 407 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf340_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_TRUNCQ32; - if (Field_ftsf71ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULSQ32SP16S_H; - if (Field_ftsf72ae_slot1_Slot_ae_slot1_get (insn) == 26 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULSQ32SP16S_L; - if (Field_ftsf73ae_slot1_Slot_ae_slot1_get (insn) == 417 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVP48; - if (Field_ftsf75ae_slot1_Slot_ae_slot1_get (insn) == 419 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16ASYM; - if (Field_ftsf76ae_slot1_Slot_ae_slot1_get (insn) == 421 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16SYM; - if (Field_ftsf77ae_slot1_Slot_ae_slot1_get (insn) == 423 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRASP24; - if (Field_ftsf78ae_slot1_Slot_ae_slot1_get (insn) == 425 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SLLSP24; - if (Field_ftsf79ae_slot1_Slot_ae_slot1_get (insn) == 427 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRLSP24; - if (Field_ftsf80ae_slot1_Slot_ae_slot1_get (insn) == 429 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_TRUNCP16; - if (Field_ftsf81ae_slot1_Slot_ae_slot1_get (insn) == 431 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ZEROP48; - if (Field_ftsf82ae_slot1_Slot_ae_slot1_get (insn) == 109 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r10_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_SLLSSP24S; - if (Field_ftsf84ae_slot1_Slot_ae_slot1_get (insn) == 881 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16Q48ASYM; - if (Field_ftsf86ae_slot1_Slot_ae_slot1_get (insn) == 883 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16Q48SYM; - if (Field_ftsf87ae_slot1_Slot_ae_slot1_get (insn) == 443 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSP24Q48ASYM; - if (Field_ftsf88ae_slot1_Slot_ae_slot1_get (insn) == 223 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf340_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSP24Q48SYM; - if (Field_ftsf89ae_slot1_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf334ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULSQ32SP16U_H; - if (Field_ftsf90ae_slot1_Slot_ae_slot1_get (insn) == 96 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_EQP24; - if (Field_ftsf91ae_slot1_Slot_ae_slot1_get (insn) == 97 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_LEP24S; - if (Field_ftsf92ae_slot1_Slot_ae_slot1_get (insn) == 49 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf208_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LTP24S; - if (Field_ftsf94ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf347_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MOVFP24X2; - if (Field_ftsf96ae_slot1_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MOVTP24X2; - if (Field_ftsf97ae_slot1_Slot_ae_slot1_get (insn) == 112 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SUBSP24S; - if (Field_ftsf98ae_slot1_Slot_ae_slot1_get (insn) == 113 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_XORP48; - if (Field_ftsf99ae_slot1_Slot_ae_slot1_get (insn) == 114 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ABSP24; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_LL; - return 0; -} - - -/* Instruction slots. */ - -static void -Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffffff); -} - -static void -Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); -} - -static void -Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static void -Slot_ae_format_Format_ae_slot1_31_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[0] & 0x80000000) >> 31); - slotbuf[0] = (slotbuf[0] & ~0x7ffffe) | ((insn[1] & 0x3fffff) << 1); -} - -static void -Slot_ae_format_Format_ae_slot1_31_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0x80000000) | ((slotbuf[0] & 0x1) << 31); - insn[1] = (insn[1] & ~0x3fffff) | ((slotbuf[0] & 0x7ffffe) >> 1); -} - -static void -Slot_ae_format_Format_ae_slot0_4_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[0] & 0x7ffffff0) >> 4); -} - -static void -Slot_ae_format_Format_ae_slot0_4_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0x7ffffff0) | ((slotbuf[0] & 0x7ffffff) << 4); -} - -static xtensa_get_field_fn -Slot_inst_get_field_fns[] = { - Field_t_Slot_inst_get, - Field_bbi4_Slot_inst_get, - Field_bbi_Slot_inst_get, - Field_imm12_Slot_inst_get, - Field_imm8_Slot_inst_get, - Field_s_Slot_inst_get, - Field_imm12b_Slot_inst_get, - Field_imm16_Slot_inst_get, - Field_m_Slot_inst_get, - Field_n_Slot_inst_get, - Field_offset_Slot_inst_get, - Field_op0_Slot_inst_get, - Field_op1_Slot_inst_get, - Field_op2_Slot_inst_get, - Field_r_Slot_inst_get, - Field_sa4_Slot_inst_get, - Field_sae4_Slot_inst_get, - Field_sae_Slot_inst_get, - Field_sal_Slot_inst_get, - Field_sargt_Slot_inst_get, - Field_sas4_Slot_inst_get, - Field_sas_Slot_inst_get, - Field_sr_Slot_inst_get, - Field_st_Slot_inst_get, - Field_thi3_Slot_inst_get, - Field_imm4_Slot_inst_get, - Field_mn_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r3_Slot_inst_get, - Field_rbit2_Slot_inst_get, - Field_rhi_Slot_inst_get, - Field_t3_Slot_inst_get, - Field_tbit2_Slot_inst_get, - Field_tlo_Slot_inst_get, - Field_w_Slot_inst_get, - Field_y_Slot_inst_get, - Field_x_Slot_inst_get, - Field_t2_Slot_inst_get, - Field_s2_Slot_inst_get, - Field_r2_Slot_inst_get, - Field_t4_Slot_inst_get, - Field_s4_Slot_inst_get, - Field_r4_Slot_inst_get, - Field_t8_Slot_inst_get, - Field_s8_Slot_inst_get, - Field_r8_Slot_inst_get, - Field_xt_wbr15_imm_Slot_inst_get, - Field_xt_wbr18_imm_Slot_inst_get, - Field_ae_r3_Slot_inst_get, - Field_ae_s_non_samt_Slot_inst_get, - Field_ae_s3_Slot_inst_get, - Field_ae_r32_Slot_inst_get, - Field_ae_samt_s_t_Slot_inst_get, - Field_ae_r20_Slot_inst_get, - Field_ae_r10_Slot_inst_get, - Field_ae_s20_Slot_inst_get, - Field_ae_fld_ohba_Slot_inst_get, - Field_ae_fld_ohba2_Slot_inst_get, - 0, - Field_ftsf12_Slot_inst_get, - Field_ftsf13_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst_set_field_fns[] = { - Field_t_Slot_inst_set, - Field_bbi4_Slot_inst_set, - Field_bbi_Slot_inst_set, - Field_imm12_Slot_inst_set, - Field_imm8_Slot_inst_set, - Field_s_Slot_inst_set, - Field_imm12b_Slot_inst_set, - Field_imm16_Slot_inst_set, - Field_m_Slot_inst_set, - Field_n_Slot_inst_set, - Field_offset_Slot_inst_set, - Field_op0_Slot_inst_set, - Field_op1_Slot_inst_set, - Field_op2_Slot_inst_set, - Field_r_Slot_inst_set, - Field_sa4_Slot_inst_set, - Field_sae4_Slot_inst_set, - Field_sae_Slot_inst_set, - Field_sal_Slot_inst_set, - Field_sargt_Slot_inst_set, - Field_sas4_Slot_inst_set, - Field_sas_Slot_inst_set, - Field_sr_Slot_inst_set, - Field_st_Slot_inst_set, - Field_thi3_Slot_inst_set, - Field_imm4_Slot_inst_set, - Field_mn_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r3_Slot_inst_set, - Field_rbit2_Slot_inst_set, - Field_rhi_Slot_inst_set, - Field_t3_Slot_inst_set, - Field_tbit2_Slot_inst_set, - Field_tlo_Slot_inst_set, - Field_w_Slot_inst_set, - Field_y_Slot_inst_set, - Field_x_Slot_inst_set, - Field_t2_Slot_inst_set, - Field_s2_Slot_inst_set, - Field_r2_Slot_inst_set, - Field_t4_Slot_inst_set, - Field_s4_Slot_inst_set, - Field_r4_Slot_inst_set, - Field_t8_Slot_inst_set, - Field_s8_Slot_inst_set, - Field_r8_Slot_inst_set, - Field_xt_wbr15_imm_Slot_inst_set, - Field_xt_wbr18_imm_Slot_inst_set, - Field_ae_r3_Slot_inst_set, - Field_ae_s_non_samt_Slot_inst_set, - Field_ae_s3_Slot_inst_set, - Field_ae_r32_Slot_inst_set, - Field_ae_samt_s_t_Slot_inst_set, - Field_ae_r20_Slot_inst_set, - Field_ae_r10_Slot_inst_set, - Field_ae_s20_Slot_inst_set, - Field_ae_fld_ohba_Slot_inst_set, - Field_ae_fld_ohba2_Slot_inst_set, - 0, - Field_ftsf12_Slot_inst_set, - Field_ftsf13_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16a_get_field_fns[] = { - Field_t_Slot_inst16a_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_get, - 0, - 0, - Field_r_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_get, - Field_st_Slot_inst16a_get, - 0, - Field_imm4_Slot_inst16a_get, - 0, - Field_i_Slot_inst16a_get, - Field_imm6lo_Slot_inst16a_get, - Field_imm6hi_Slot_inst16a_get, - Field_imm7lo_Slot_inst16a_get, - Field_imm7hi_Slot_inst16a_get, - Field_z_Slot_inst16a_get, - Field_imm6_Slot_inst16a_get, - Field_imm7_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst16a_get, - Field_s2_Slot_inst16a_get, - Field_r2_Slot_inst16a_get, - Field_t4_Slot_inst16a_get, - Field_s4_Slot_inst16a_get, - Field_r4_Slot_inst16a_get, - Field_t8_Slot_inst16a_get, - Field_s8_Slot_inst16a_get, - Field_r8_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst16a_set_field_fns[] = { - Field_t_Slot_inst16a_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_set, - 0, - 0, - Field_r_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_set, - Field_st_Slot_inst16a_set, - 0, - Field_imm4_Slot_inst16a_set, - 0, - Field_i_Slot_inst16a_set, - Field_imm6lo_Slot_inst16a_set, - Field_imm6hi_Slot_inst16a_set, - Field_imm7lo_Slot_inst16a_set, - Field_imm7hi_Slot_inst16a_set, - Field_z_Slot_inst16a_set, - Field_imm6_Slot_inst16a_set, - Field_imm7_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst16a_set, - Field_s2_Slot_inst16a_set, - Field_r2_Slot_inst16a_set, - Field_t4_Slot_inst16a_set, - Field_s4_Slot_inst16a_set, - Field_r4_Slot_inst16a_set, - Field_t8_Slot_inst16a_set, - Field_s8_Slot_inst16a_set, - Field_r8_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16b_get_field_fns[] = { - Field_t_Slot_inst16b_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_get, - 0, - 0, - Field_r_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_get, - Field_st_Slot_inst16b_get, - 0, - Field_imm4_Slot_inst16b_get, - 0, - Field_i_Slot_inst16b_get, - Field_imm6lo_Slot_inst16b_get, - Field_imm6hi_Slot_inst16b_get, - Field_imm7lo_Slot_inst16b_get, - Field_imm7hi_Slot_inst16b_get, - Field_z_Slot_inst16b_get, - Field_imm6_Slot_inst16b_get, - Field_imm7_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst16b_get, - Field_s2_Slot_inst16b_get, - Field_r2_Slot_inst16b_get, - Field_t4_Slot_inst16b_get, - Field_s4_Slot_inst16b_get, - Field_r4_Slot_inst16b_get, - Field_t8_Slot_inst16b_get, - Field_s8_Slot_inst16b_get, - Field_r8_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst16b_set_field_fns[] = { - Field_t_Slot_inst16b_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_set, - 0, - 0, - Field_r_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_set, - Field_st_Slot_inst16b_set, - 0, - Field_imm4_Slot_inst16b_set, - 0, - Field_i_Slot_inst16b_set, - Field_imm6lo_Slot_inst16b_set, - Field_imm6hi_Slot_inst16b_set, - Field_imm7lo_Slot_inst16b_set, - Field_imm7hi_Slot_inst16b_set, - Field_z_Slot_inst16b_set, - Field_imm6_Slot_inst16b_set, - Field_imm7_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst16b_set, - Field_s2_Slot_inst16b_set, - Field_r2_Slot_inst16b_set, - Field_t4_Slot_inst16b_set, - Field_s4_Slot_inst16b_set, - Field_r4_Slot_inst16b_set, - Field_t8_Slot_inst16b_set, - Field_s8_Slot_inst16b_set, - Field_r8_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_ae_slot1_get_field_fns[] = { - Field_t_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot1_get, - 0, - Field_ae_r20_Slot_ae_slot1_get, - Field_ae_r10_Slot_ae_slot1_get, - Field_ae_s20_Slot_ae_slot1_get, - 0, - 0, - Field_op0_s3_Slot_ae_slot1_get, - Field_ftsf12_Slot_ae_slot1_get, - Field_ftsf13_Slot_ae_slot1_get, - Field_ftsf14_Slot_ae_slot1_get, - Field_ftsf21ae_slot1_Slot_ae_slot1_get, - Field_ftsf22ae_slot1_Slot_ae_slot1_get, - Field_ftsf23ae_slot1_Slot_ae_slot1_get, - Field_ftsf24ae_slot1_Slot_ae_slot1_get, - Field_ftsf25ae_slot1_Slot_ae_slot1_get, - Field_ftsf26ae_slot1_Slot_ae_slot1_get, - Field_ftsf27ae_slot1_Slot_ae_slot1_get, - Field_ftsf28ae_slot1_Slot_ae_slot1_get, - Field_ftsf29ae_slot1_Slot_ae_slot1_get, - Field_ftsf30ae_slot1_Slot_ae_slot1_get, - Field_ftsf31ae_slot1_Slot_ae_slot1_get, - Field_ftsf32ae_slot1_Slot_ae_slot1_get, - Field_ftsf33ae_slot1_Slot_ae_slot1_get, - Field_ftsf34ae_slot1_Slot_ae_slot1_get, - Field_ftsf35ae_slot1_Slot_ae_slot1_get, - Field_ftsf36ae_slot1_Slot_ae_slot1_get, - Field_ftsf37ae_slot1_Slot_ae_slot1_get, - Field_ftsf38ae_slot1_Slot_ae_slot1_get, - Field_ftsf39ae_slot1_Slot_ae_slot1_get, - Field_ftsf40ae_slot1_Slot_ae_slot1_get, - Field_ftsf41ae_slot1_Slot_ae_slot1_get, - Field_ftsf42ae_slot1_Slot_ae_slot1_get, - Field_ftsf43ae_slot1_Slot_ae_slot1_get, - Field_ftsf44ae_slot1_Slot_ae_slot1_get, - Field_ftsf45ae_slot1_Slot_ae_slot1_get, - Field_ftsf46ae_slot1_Slot_ae_slot1_get, - Field_ftsf47ae_slot1_Slot_ae_slot1_get, - Field_ftsf48ae_slot1_Slot_ae_slot1_get, - Field_ftsf49ae_slot1_Slot_ae_slot1_get, - Field_ftsf50ae_slot1_Slot_ae_slot1_get, - Field_ftsf51ae_slot1_Slot_ae_slot1_get, - Field_ftsf52ae_slot1_Slot_ae_slot1_get, - Field_ftsf53ae_slot1_Slot_ae_slot1_get, - Field_ftsf54ae_slot1_Slot_ae_slot1_get, - Field_ftsf55ae_slot1_Slot_ae_slot1_get, - Field_ftsf56ae_slot1_Slot_ae_slot1_get, - Field_ftsf57ae_slot1_Slot_ae_slot1_get, - Field_ftsf58ae_slot1_Slot_ae_slot1_get, - Field_ftsf59ae_slot1_Slot_ae_slot1_get, - Field_ftsf60ae_slot1_Slot_ae_slot1_get, - Field_ftsf61ae_slot1_Slot_ae_slot1_get, - Field_ftsf63ae_slot1_Slot_ae_slot1_get, - Field_ftsf64ae_slot1_Slot_ae_slot1_get, - Field_ftsf66ae_slot1_Slot_ae_slot1_get, - Field_ftsf67ae_slot1_Slot_ae_slot1_get, - Field_ftsf69ae_slot1_Slot_ae_slot1_get, - Field_ftsf71ae_slot1_Slot_ae_slot1_get, - Field_ftsf72ae_slot1_Slot_ae_slot1_get, - Field_ftsf73ae_slot1_Slot_ae_slot1_get, - Field_ftsf75ae_slot1_Slot_ae_slot1_get, - Field_ftsf76ae_slot1_Slot_ae_slot1_get, - Field_ftsf77ae_slot1_Slot_ae_slot1_get, - Field_ftsf78ae_slot1_Slot_ae_slot1_get, - Field_ftsf79ae_slot1_Slot_ae_slot1_get, - Field_ftsf80ae_slot1_Slot_ae_slot1_get, - Field_ftsf81ae_slot1_Slot_ae_slot1_get, - Field_ftsf82ae_slot1_Slot_ae_slot1_get, - Field_ftsf84ae_slot1_Slot_ae_slot1_get, - Field_ftsf86ae_slot1_Slot_ae_slot1_get, - Field_ftsf87ae_slot1_Slot_ae_slot1_get, - Field_ftsf88ae_slot1_Slot_ae_slot1_get, - Field_ftsf89ae_slot1_Slot_ae_slot1_get, - Field_ftsf90ae_slot1_Slot_ae_slot1_get, - Field_ftsf91ae_slot1_Slot_ae_slot1_get, - Field_ftsf92ae_slot1_Slot_ae_slot1_get, - Field_ftsf94ae_slot1_Slot_ae_slot1_get, - Field_ftsf96ae_slot1_Slot_ae_slot1_get, - Field_ftsf97ae_slot1_Slot_ae_slot1_get, - Field_ftsf98ae_slot1_Slot_ae_slot1_get, - Field_ftsf99ae_slot1_Slot_ae_slot1_get, - Field_ftsf100ae_slot1_Slot_ae_slot1_get, - Field_ftsf101ae_slot1_Slot_ae_slot1_get, - Field_ftsf103ae_slot1_Slot_ae_slot1_get, - Field_ftsf104ae_slot1_Slot_ae_slot1_get, - Field_ftsf105ae_slot1_Slot_ae_slot1_get, - Field_ftsf106ae_slot1_Slot_ae_slot1_get, - Field_ftsf107ae_slot1_Slot_ae_slot1_get, - Field_ftsf108ae_slot1_Slot_ae_slot1_get, - Field_ftsf109ae_slot1_Slot_ae_slot1_get, - Field_ftsf110ae_slot1_Slot_ae_slot1_get, - Field_ftsf111ae_slot1_Slot_ae_slot1_get, - Field_ftsf112ae_slot1_Slot_ae_slot1_get, - Field_ftsf113ae_slot1_Slot_ae_slot1_get, - Field_ftsf114ae_slot1_Slot_ae_slot1_get, - Field_ftsf115ae_slot1_Slot_ae_slot1_get, - Field_ftsf116ae_slot1_Slot_ae_slot1_get, - Field_ftsf118ae_slot1_Slot_ae_slot1_get, - Field_ftsf119ae_slot1_Slot_ae_slot1_get, - Field_ftsf120ae_slot1_Slot_ae_slot1_get, - Field_ftsf122ae_slot1_Slot_ae_slot1_get, - Field_ftsf124ae_slot1_Slot_ae_slot1_get, - Field_ftsf125ae_slot1_Slot_ae_slot1_get, - Field_ftsf126ae_slot1_Slot_ae_slot1_get, - Field_ftsf127ae_slot1_Slot_ae_slot1_get, - Field_ftsf128ae_slot1_Slot_ae_slot1_get, - Field_ftsf129ae_slot1_Slot_ae_slot1_get, - Field_ftsf130ae_slot1_Slot_ae_slot1_get, - Field_ftsf131ae_slot1_Slot_ae_slot1_get, - Field_ftsf132ae_slot1_Slot_ae_slot1_get, - Field_ftsf133ae_slot1_Slot_ae_slot1_get, - Field_ftsf134ae_slot1_Slot_ae_slot1_get, - Field_ftsf135ae_slot1_Slot_ae_slot1_get, - Field_ftsf136ae_slot1_Slot_ae_slot1_get, - Field_ftsf137ae_slot1_Slot_ae_slot1_get, - Field_ftsf138ae_slot1_Slot_ae_slot1_get, - Field_ftsf139ae_slot1_Slot_ae_slot1_get, - Field_ftsf140ae_slot1_Slot_ae_slot1_get, - Field_ftsf141ae_slot1_Slot_ae_slot1_get, - Field_ftsf142ae_slot1_Slot_ae_slot1_get, - Field_ftsf143ae_slot1_Slot_ae_slot1_get, - Field_ftsf144ae_slot1_Slot_ae_slot1_get, - Field_ftsf145ae_slot1_Slot_ae_slot1_get, - Field_ftsf146ae_slot1_Slot_ae_slot1_get, - Field_ftsf147ae_slot1_Slot_ae_slot1_get, - Field_ftsf148ae_slot1_Slot_ae_slot1_get, - Field_ftsf149ae_slot1_Slot_ae_slot1_get, - Field_ftsf150ae_slot1_Slot_ae_slot1_get, - Field_ftsf151ae_slot1_Slot_ae_slot1_get, - Field_ftsf152ae_slot1_Slot_ae_slot1_get, - Field_ftsf153ae_slot1_Slot_ae_slot1_get, - Field_ftsf154ae_slot1_Slot_ae_slot1_get, - Field_ftsf155ae_slot1_Slot_ae_slot1_get, - Field_ftsf156ae_slot1_Slot_ae_slot1_get, - Field_ftsf157ae_slot1_Slot_ae_slot1_get, - Field_ftsf158ae_slot1_Slot_ae_slot1_get, - Field_ftsf159ae_slot1_Slot_ae_slot1_get, - Field_ftsf160ae_slot1_Slot_ae_slot1_get, - Field_ftsf161ae_slot1_Slot_ae_slot1_get, - Field_ftsf162ae_slot1_Slot_ae_slot1_get, - Field_ftsf163ae_slot1_Slot_ae_slot1_get, - Field_ftsf164ae_slot1_Slot_ae_slot1_get, - Field_ftsf165ae_slot1_Slot_ae_slot1_get, - Field_ftsf166ae_slot1_Slot_ae_slot1_get, - Field_ftsf167ae_slot1_Slot_ae_slot1_get, - Field_ftsf168ae_slot1_Slot_ae_slot1_get, - Field_ftsf169ae_slot1_Slot_ae_slot1_get, - Field_ftsf170ae_slot1_Slot_ae_slot1_get, - Field_ftsf171ae_slot1_Slot_ae_slot1_get, - Field_ftsf172ae_slot1_Slot_ae_slot1_get, - Field_ftsf173ae_slot1_Slot_ae_slot1_get, - Field_ftsf174ae_slot1_Slot_ae_slot1_get, - Field_ftsf175ae_slot1_Slot_ae_slot1_get, - Field_ftsf176ae_slot1_Slot_ae_slot1_get, - Field_ftsf177ae_slot1_Slot_ae_slot1_get, - Field_ftsf178ae_slot1_Slot_ae_slot1_get, - Field_ftsf179ae_slot1_Slot_ae_slot1_get, - Field_ftsf180ae_slot1_Slot_ae_slot1_get, - Field_ftsf181ae_slot1_Slot_ae_slot1_get, - Field_ftsf182ae_slot1_Slot_ae_slot1_get, - Field_ftsf183ae_slot1_Slot_ae_slot1_get, - Field_ftsf184ae_slot1_Slot_ae_slot1_get, - Field_ftsf185ae_slot1_Slot_ae_slot1_get, - Field_ftsf186ae_slot1_Slot_ae_slot1_get, - Field_ftsf187ae_slot1_Slot_ae_slot1_get, - Field_ftsf188ae_slot1_Slot_ae_slot1_get, - Field_ftsf189ae_slot1_Slot_ae_slot1_get, - Field_ftsf190ae_slot1_Slot_ae_slot1_get, - Field_ftsf191ae_slot1_Slot_ae_slot1_get, - Field_ftsf192ae_slot1_Slot_ae_slot1_get, - Field_ftsf193ae_slot1_Slot_ae_slot1_get, - Field_ftsf194ae_slot1_Slot_ae_slot1_get, - Field_ftsf195ae_slot1_Slot_ae_slot1_get, - Field_ftsf196ae_slot1_Slot_ae_slot1_get, - Field_ftsf197ae_slot1_Slot_ae_slot1_get, - Field_ftsf198ae_slot1_Slot_ae_slot1_get, - Field_ftsf199ae_slot1_Slot_ae_slot1_get, - Field_ftsf200ae_slot1_Slot_ae_slot1_get, - Field_ftsf201ae_slot1_Slot_ae_slot1_get, - Field_ftsf202ae_slot1_Slot_ae_slot1_get, - Field_ftsf203ae_slot1_Slot_ae_slot1_get, - Field_ftsf204ae_slot1_Slot_ae_slot1_get, - Field_ftsf205ae_slot1_Slot_ae_slot1_get, - Field_ftsf206ae_slot1_Slot_ae_slot1_get, - Field_ftsf207ae_slot1_Slot_ae_slot1_get, - Field_ftsf208_Slot_ae_slot1_get, - Field_ftsf209ae_slot1_Slot_ae_slot1_get, - Field_ftsf210ae_slot1_Slot_ae_slot1_get, - Field_ftsf211ae_slot1_Slot_ae_slot1_get, - Field_ftsf330ae_slot1_Slot_ae_slot1_get, - Field_ftsf332ae_slot1_Slot_ae_slot1_get, - Field_ftsf334ae_slot1_Slot_ae_slot1_get, - Field_ftsf336ae_slot1_Slot_ae_slot1_get, - Field_ftsf337ae_slot1_Slot_ae_slot1_get, - Field_ftsf338_Slot_ae_slot1_get, - Field_ftsf339ae_slot1_Slot_ae_slot1_get, - Field_ftsf340_Slot_ae_slot1_get, - Field_ftsf341ae_slot1_Slot_ae_slot1_get, - Field_ftsf342ae_slot1_Slot_ae_slot1_get, - Field_ftsf343ae_slot1_Slot_ae_slot1_get, - Field_ftsf344ae_slot1_Slot_ae_slot1_get, - Field_ftsf346ae_slot1_Slot_ae_slot1_get, - Field_ftsf347_Slot_ae_slot1_get, - Field_ftsf348ae_slot1_Slot_ae_slot1_get, - Field_ftsf349ae_slot1_Slot_ae_slot1_get, - Field_ftsf350ae_slot1_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_mul32x24fld_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_combined1b97e84f_fld54_Slot_ae_slot1_get, - Field_combined1b97e84f_fld17_Slot_ae_slot1_get, - Field_combined1b97e84f_fld76_Slot_ae_slot1_get, - Field_combined1b97e84f_fld73_Slot_ae_slot1_get, - Field_combined1b97e84f_fld62_Slot_ae_slot1_get, - Field_combined1b97e84f_fld24_Slot_ae_slot1_get, - Field_combined1b97e84f_fld70_Slot_ae_slot1_get, - Field_combined1b97e84f_fld58_Slot_ae_slot1_get, - Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_get, - Field_op0_s3_s3_Slot_ae_slot1_get, - Field_combined1b97e84f_fld49_Slot_ae_slot1_get, - Field_combined1b97e84f_fld51_Slot_ae_slot1_get, - Field_combined1b97e84f_fld23_Slot_ae_slot1_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_ae_slot1_set_field_fns[] = { - Field_t_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot1_set, - 0, - Field_ae_r20_Slot_ae_slot1_set, - Field_ae_r10_Slot_ae_slot1_set, - Field_ae_s20_Slot_ae_slot1_set, - 0, - 0, - Field_op0_s3_Slot_ae_slot1_set, - Field_ftsf12_Slot_ae_slot1_set, - Field_ftsf13_Slot_ae_slot1_set, - Field_ftsf14_Slot_ae_slot1_set, - Field_ftsf21ae_slot1_Slot_ae_slot1_set, - Field_ftsf22ae_slot1_Slot_ae_slot1_set, - Field_ftsf23ae_slot1_Slot_ae_slot1_set, - Field_ftsf24ae_slot1_Slot_ae_slot1_set, - Field_ftsf25ae_slot1_Slot_ae_slot1_set, - Field_ftsf26ae_slot1_Slot_ae_slot1_set, - Field_ftsf27ae_slot1_Slot_ae_slot1_set, - Field_ftsf28ae_slot1_Slot_ae_slot1_set, - Field_ftsf29ae_slot1_Slot_ae_slot1_set, - Field_ftsf30ae_slot1_Slot_ae_slot1_set, - Field_ftsf31ae_slot1_Slot_ae_slot1_set, - Field_ftsf32ae_slot1_Slot_ae_slot1_set, - Field_ftsf33ae_slot1_Slot_ae_slot1_set, - Field_ftsf34ae_slot1_Slot_ae_slot1_set, - Field_ftsf35ae_slot1_Slot_ae_slot1_set, - Field_ftsf36ae_slot1_Slot_ae_slot1_set, - Field_ftsf37ae_slot1_Slot_ae_slot1_set, - Field_ftsf38ae_slot1_Slot_ae_slot1_set, - Field_ftsf39ae_slot1_Slot_ae_slot1_set, - Field_ftsf40ae_slot1_Slot_ae_slot1_set, - Field_ftsf41ae_slot1_Slot_ae_slot1_set, - Field_ftsf42ae_slot1_Slot_ae_slot1_set, - Field_ftsf43ae_slot1_Slot_ae_slot1_set, - Field_ftsf44ae_slot1_Slot_ae_slot1_set, - Field_ftsf45ae_slot1_Slot_ae_slot1_set, - Field_ftsf46ae_slot1_Slot_ae_slot1_set, - Field_ftsf47ae_slot1_Slot_ae_slot1_set, - Field_ftsf48ae_slot1_Slot_ae_slot1_set, - Field_ftsf49ae_slot1_Slot_ae_slot1_set, - Field_ftsf50ae_slot1_Slot_ae_slot1_set, - Field_ftsf51ae_slot1_Slot_ae_slot1_set, - Field_ftsf52ae_slot1_Slot_ae_slot1_set, - Field_ftsf53ae_slot1_Slot_ae_slot1_set, - Field_ftsf54ae_slot1_Slot_ae_slot1_set, - Field_ftsf55ae_slot1_Slot_ae_slot1_set, - Field_ftsf56ae_slot1_Slot_ae_slot1_set, - Field_ftsf57ae_slot1_Slot_ae_slot1_set, - Field_ftsf58ae_slot1_Slot_ae_slot1_set, - Field_ftsf59ae_slot1_Slot_ae_slot1_set, - Field_ftsf60ae_slot1_Slot_ae_slot1_set, - Field_ftsf61ae_slot1_Slot_ae_slot1_set, - Field_ftsf63ae_slot1_Slot_ae_slot1_set, - Field_ftsf64ae_slot1_Slot_ae_slot1_set, - Field_ftsf66ae_slot1_Slot_ae_slot1_set, - Field_ftsf67ae_slot1_Slot_ae_slot1_set, - Field_ftsf69ae_slot1_Slot_ae_slot1_set, - Field_ftsf71ae_slot1_Slot_ae_slot1_set, - Field_ftsf72ae_slot1_Slot_ae_slot1_set, - Field_ftsf73ae_slot1_Slot_ae_slot1_set, - Field_ftsf75ae_slot1_Slot_ae_slot1_set, - Field_ftsf76ae_slot1_Slot_ae_slot1_set, - Field_ftsf77ae_slot1_Slot_ae_slot1_set, - Field_ftsf78ae_slot1_Slot_ae_slot1_set, - Field_ftsf79ae_slot1_Slot_ae_slot1_set, - Field_ftsf80ae_slot1_Slot_ae_slot1_set, - Field_ftsf81ae_slot1_Slot_ae_slot1_set, - Field_ftsf82ae_slot1_Slot_ae_slot1_set, - Field_ftsf84ae_slot1_Slot_ae_slot1_set, - Field_ftsf86ae_slot1_Slot_ae_slot1_set, - Field_ftsf87ae_slot1_Slot_ae_slot1_set, - Field_ftsf88ae_slot1_Slot_ae_slot1_set, - Field_ftsf89ae_slot1_Slot_ae_slot1_set, - Field_ftsf90ae_slot1_Slot_ae_slot1_set, - Field_ftsf91ae_slot1_Slot_ae_slot1_set, - Field_ftsf92ae_slot1_Slot_ae_slot1_set, - Field_ftsf94ae_slot1_Slot_ae_slot1_set, - Field_ftsf96ae_slot1_Slot_ae_slot1_set, - Field_ftsf97ae_slot1_Slot_ae_slot1_set, - Field_ftsf98ae_slot1_Slot_ae_slot1_set, - Field_ftsf99ae_slot1_Slot_ae_slot1_set, - Field_ftsf100ae_slot1_Slot_ae_slot1_set, - Field_ftsf101ae_slot1_Slot_ae_slot1_set, - Field_ftsf103ae_slot1_Slot_ae_slot1_set, - Field_ftsf104ae_slot1_Slot_ae_slot1_set, - Field_ftsf105ae_slot1_Slot_ae_slot1_set, - Field_ftsf106ae_slot1_Slot_ae_slot1_set, - Field_ftsf107ae_slot1_Slot_ae_slot1_set, - Field_ftsf108ae_slot1_Slot_ae_slot1_set, - Field_ftsf109ae_slot1_Slot_ae_slot1_set, - Field_ftsf110ae_slot1_Slot_ae_slot1_set, - Field_ftsf111ae_slot1_Slot_ae_slot1_set, - Field_ftsf112ae_slot1_Slot_ae_slot1_set, - Field_ftsf113ae_slot1_Slot_ae_slot1_set, - Field_ftsf114ae_slot1_Slot_ae_slot1_set, - Field_ftsf115ae_slot1_Slot_ae_slot1_set, - Field_ftsf116ae_slot1_Slot_ae_slot1_set, - Field_ftsf118ae_slot1_Slot_ae_slot1_set, - Field_ftsf119ae_slot1_Slot_ae_slot1_set, - Field_ftsf120ae_slot1_Slot_ae_slot1_set, - Field_ftsf122ae_slot1_Slot_ae_slot1_set, - Field_ftsf124ae_slot1_Slot_ae_slot1_set, - Field_ftsf125ae_slot1_Slot_ae_slot1_set, - Field_ftsf126ae_slot1_Slot_ae_slot1_set, - Field_ftsf127ae_slot1_Slot_ae_slot1_set, - Field_ftsf128ae_slot1_Slot_ae_slot1_set, - Field_ftsf129ae_slot1_Slot_ae_slot1_set, - Field_ftsf130ae_slot1_Slot_ae_slot1_set, - Field_ftsf131ae_slot1_Slot_ae_slot1_set, - Field_ftsf132ae_slot1_Slot_ae_slot1_set, - Field_ftsf133ae_slot1_Slot_ae_slot1_set, - Field_ftsf134ae_slot1_Slot_ae_slot1_set, - Field_ftsf135ae_slot1_Slot_ae_slot1_set, - Field_ftsf136ae_slot1_Slot_ae_slot1_set, - Field_ftsf137ae_slot1_Slot_ae_slot1_set, - Field_ftsf138ae_slot1_Slot_ae_slot1_set, - Field_ftsf139ae_slot1_Slot_ae_slot1_set, - Field_ftsf140ae_slot1_Slot_ae_slot1_set, - Field_ftsf141ae_slot1_Slot_ae_slot1_set, - Field_ftsf142ae_slot1_Slot_ae_slot1_set, - Field_ftsf143ae_slot1_Slot_ae_slot1_set, - Field_ftsf144ae_slot1_Slot_ae_slot1_set, - Field_ftsf145ae_slot1_Slot_ae_slot1_set, - Field_ftsf146ae_slot1_Slot_ae_slot1_set, - Field_ftsf147ae_slot1_Slot_ae_slot1_set, - Field_ftsf148ae_slot1_Slot_ae_slot1_set, - Field_ftsf149ae_slot1_Slot_ae_slot1_set, - Field_ftsf150ae_slot1_Slot_ae_slot1_set, - Field_ftsf151ae_slot1_Slot_ae_slot1_set, - Field_ftsf152ae_slot1_Slot_ae_slot1_set, - Field_ftsf153ae_slot1_Slot_ae_slot1_set, - Field_ftsf154ae_slot1_Slot_ae_slot1_set, - Field_ftsf155ae_slot1_Slot_ae_slot1_set, - Field_ftsf156ae_slot1_Slot_ae_slot1_set, - Field_ftsf157ae_slot1_Slot_ae_slot1_set, - Field_ftsf158ae_slot1_Slot_ae_slot1_set, - Field_ftsf159ae_slot1_Slot_ae_slot1_set, - Field_ftsf160ae_slot1_Slot_ae_slot1_set, - Field_ftsf161ae_slot1_Slot_ae_slot1_set, - Field_ftsf162ae_slot1_Slot_ae_slot1_set, - Field_ftsf163ae_slot1_Slot_ae_slot1_set, - Field_ftsf164ae_slot1_Slot_ae_slot1_set, - Field_ftsf165ae_slot1_Slot_ae_slot1_set, - Field_ftsf166ae_slot1_Slot_ae_slot1_set, - Field_ftsf167ae_slot1_Slot_ae_slot1_set, - Field_ftsf168ae_slot1_Slot_ae_slot1_set, - Field_ftsf169ae_slot1_Slot_ae_slot1_set, - Field_ftsf170ae_slot1_Slot_ae_slot1_set, - Field_ftsf171ae_slot1_Slot_ae_slot1_set, - Field_ftsf172ae_slot1_Slot_ae_slot1_set, - Field_ftsf173ae_slot1_Slot_ae_slot1_set, - Field_ftsf174ae_slot1_Slot_ae_slot1_set, - Field_ftsf175ae_slot1_Slot_ae_slot1_set, - Field_ftsf176ae_slot1_Slot_ae_slot1_set, - Field_ftsf177ae_slot1_Slot_ae_slot1_set, - Field_ftsf178ae_slot1_Slot_ae_slot1_set, - Field_ftsf179ae_slot1_Slot_ae_slot1_set, - Field_ftsf180ae_slot1_Slot_ae_slot1_set, - Field_ftsf181ae_slot1_Slot_ae_slot1_set, - Field_ftsf182ae_slot1_Slot_ae_slot1_set, - Field_ftsf183ae_slot1_Slot_ae_slot1_set, - Field_ftsf184ae_slot1_Slot_ae_slot1_set, - Field_ftsf185ae_slot1_Slot_ae_slot1_set, - Field_ftsf186ae_slot1_Slot_ae_slot1_set, - Field_ftsf187ae_slot1_Slot_ae_slot1_set, - Field_ftsf188ae_slot1_Slot_ae_slot1_set, - Field_ftsf189ae_slot1_Slot_ae_slot1_set, - Field_ftsf190ae_slot1_Slot_ae_slot1_set, - Field_ftsf191ae_slot1_Slot_ae_slot1_set, - Field_ftsf192ae_slot1_Slot_ae_slot1_set, - Field_ftsf193ae_slot1_Slot_ae_slot1_set, - Field_ftsf194ae_slot1_Slot_ae_slot1_set, - Field_ftsf195ae_slot1_Slot_ae_slot1_set, - Field_ftsf196ae_slot1_Slot_ae_slot1_set, - Field_ftsf197ae_slot1_Slot_ae_slot1_set, - Field_ftsf198ae_slot1_Slot_ae_slot1_set, - Field_ftsf199ae_slot1_Slot_ae_slot1_set, - Field_ftsf200ae_slot1_Slot_ae_slot1_set, - Field_ftsf201ae_slot1_Slot_ae_slot1_set, - Field_ftsf202ae_slot1_Slot_ae_slot1_set, - Field_ftsf203ae_slot1_Slot_ae_slot1_set, - Field_ftsf204ae_slot1_Slot_ae_slot1_set, - Field_ftsf205ae_slot1_Slot_ae_slot1_set, - Field_ftsf206ae_slot1_Slot_ae_slot1_set, - Field_ftsf207ae_slot1_Slot_ae_slot1_set, - Field_ftsf208_Slot_ae_slot1_set, - Field_ftsf209ae_slot1_Slot_ae_slot1_set, - Field_ftsf210ae_slot1_Slot_ae_slot1_set, - Field_ftsf211ae_slot1_Slot_ae_slot1_set, - Field_ftsf330ae_slot1_Slot_ae_slot1_set, - Field_ftsf332ae_slot1_Slot_ae_slot1_set, - Field_ftsf334ae_slot1_Slot_ae_slot1_set, - Field_ftsf336ae_slot1_Slot_ae_slot1_set, - Field_ftsf337ae_slot1_Slot_ae_slot1_set, - Field_ftsf338_Slot_ae_slot1_set, - Field_ftsf339ae_slot1_Slot_ae_slot1_set, - Field_ftsf340_Slot_ae_slot1_set, - Field_ftsf341ae_slot1_Slot_ae_slot1_set, - Field_ftsf342ae_slot1_Slot_ae_slot1_set, - Field_ftsf343ae_slot1_Slot_ae_slot1_set, - Field_ftsf344ae_slot1_Slot_ae_slot1_set, - Field_ftsf346ae_slot1_Slot_ae_slot1_set, - Field_ftsf347_Slot_ae_slot1_set, - Field_ftsf348ae_slot1_Slot_ae_slot1_set, - Field_ftsf349ae_slot1_Slot_ae_slot1_set, - Field_ftsf350ae_slot1_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_mul32x24fld_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_combined1b97e84f_fld54_Slot_ae_slot1_set, - Field_combined1b97e84f_fld17_Slot_ae_slot1_set, - Field_combined1b97e84f_fld76_Slot_ae_slot1_set, - Field_combined1b97e84f_fld73_Slot_ae_slot1_set, - Field_combined1b97e84f_fld62_Slot_ae_slot1_set, - Field_combined1b97e84f_fld24_Slot_ae_slot1_set, - Field_combined1b97e84f_fld70_Slot_ae_slot1_set, - Field_combined1b97e84f_fld58_Slot_ae_slot1_set, - Field_combined1b97e84f_fld131ae_slot1_Slot_ae_slot1_set, - Field_op0_s3_s3_Slot_ae_slot1_set, - Field_combined1b97e84f_fld49_Slot_ae_slot1_set, - Field_combined1b97e84f_fld51_Slot_ae_slot1_set, - Field_combined1b97e84f_fld23_Slot_ae_slot1_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_ae_slot0_get_field_fns[] = { - Field_t_Slot_ae_slot0_get, - 0, - Field_bbi_Slot_ae_slot0_get, - Field_imm12_Slot_ae_slot0_get, - Field_imm8_Slot_ae_slot0_get, - Field_s_Slot_ae_slot0_get, - Field_imm12b_Slot_ae_slot0_get, - Field_imm16_Slot_ae_slot0_get, - 0, - 0, - Field_offset_Slot_ae_slot0_get, - 0, - 0, - Field_op2_Slot_ae_slot0_get, - Field_r_Slot_ae_slot0_get, - 0, - 0, - Field_sae_Slot_ae_slot0_get, - Field_sal_Slot_ae_slot0_get, - Field_sargt_Slot_ae_slot0_get, - 0, - Field_sas_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_s4_Slot_ae_slot0_get, - 0, - 0, - Field_s8_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot0_get, - Field_ae_samt_s_t_Slot_ae_slot0_get, - Field_ae_r20_Slot_ae_slot0_get, - Field_ae_r10_Slot_ae_slot0_get, - Field_ae_s20_Slot_ae_slot0_get, - 0, - 0, - 0, - Field_ftsf12_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s4_Slot_ae_slot0_get, - Field_ftsf212ae_slot0_Slot_ae_slot0_get, - Field_ftsf213ae_slot0_Slot_ae_slot0_get, - Field_ftsf214ae_slot0_Slot_ae_slot0_get, - Field_ftsf215ae_slot0_Slot_ae_slot0_get, - Field_ftsf216ae_slot0_Slot_ae_slot0_get, - Field_ftsf217_Slot_ae_slot0_get, - Field_ftsf218ae_slot0_Slot_ae_slot0_get, - Field_ftsf219ae_slot0_Slot_ae_slot0_get, - Field_ftsf220ae_slot0_Slot_ae_slot0_get, - Field_ftsf221ae_slot0_Slot_ae_slot0_get, - Field_ftsf222ae_slot0_Slot_ae_slot0_get, - Field_ftsf223ae_slot0_Slot_ae_slot0_get, - Field_ftsf224ae_slot0_Slot_ae_slot0_get, - Field_ftsf225ae_slot0_Slot_ae_slot0_get, - Field_ftsf226ae_slot0_Slot_ae_slot0_get, - Field_ftsf227ae_slot0_Slot_ae_slot0_get, - Field_ftsf228ae_slot0_Slot_ae_slot0_get, - Field_ftsf229ae_slot0_Slot_ae_slot0_get, - Field_ftsf230ae_slot0_Slot_ae_slot0_get, - Field_ftsf231ae_slot0_Slot_ae_slot0_get, - Field_ftsf232ae_slot0_Slot_ae_slot0_get, - Field_ftsf233ae_slot0_Slot_ae_slot0_get, - Field_ftsf234ae_slot0_Slot_ae_slot0_get, - Field_ftsf235ae_slot0_Slot_ae_slot0_get, - Field_ftsf236ae_slot0_Slot_ae_slot0_get, - Field_ftsf237ae_slot0_Slot_ae_slot0_get, - Field_ftsf238ae_slot0_Slot_ae_slot0_get, - Field_ftsf239ae_slot0_Slot_ae_slot0_get, - Field_ftsf240ae_slot0_Slot_ae_slot0_get, - Field_ftsf241ae_slot0_Slot_ae_slot0_get, - Field_ftsf242ae_slot0_Slot_ae_slot0_get, - Field_ftsf243ae_slot0_Slot_ae_slot0_get, - Field_ftsf244ae_slot0_Slot_ae_slot0_get, - Field_ftsf245ae_slot0_Slot_ae_slot0_get, - Field_ftsf246ae_slot0_Slot_ae_slot0_get, - Field_ftsf247ae_slot0_Slot_ae_slot0_get, - Field_ftsf248ae_slot0_Slot_ae_slot0_get, - Field_ftsf249ae_slot0_Slot_ae_slot0_get, - Field_ftsf250ae_slot0_Slot_ae_slot0_get, - Field_ftsf251ae_slot0_Slot_ae_slot0_get, - Field_ftsf252ae_slot0_Slot_ae_slot0_get, - Field_ftsf253ae_slot0_Slot_ae_slot0_get, - Field_ftsf254ae_slot0_Slot_ae_slot0_get, - Field_ftsf255ae_slot0_Slot_ae_slot0_get, - Field_ftsf256ae_slot0_Slot_ae_slot0_get, - Field_ftsf257ae_slot0_Slot_ae_slot0_get, - Field_ftsf258ae_slot0_Slot_ae_slot0_get, - Field_ftsf259ae_slot0_Slot_ae_slot0_get, - Field_ftsf260ae_slot0_Slot_ae_slot0_get, - Field_ftsf261ae_slot0_Slot_ae_slot0_get, - Field_ftsf262ae_slot0_Slot_ae_slot0_get, - Field_ftsf263ae_slot0_Slot_ae_slot0_get, - Field_ftsf264ae_slot0_Slot_ae_slot0_get, - Field_ftsf265ae_slot0_Slot_ae_slot0_get, - Field_ftsf266ae_slot0_Slot_ae_slot0_get, - Field_ftsf267ae_slot0_Slot_ae_slot0_get, - Field_ftsf268ae_slot0_Slot_ae_slot0_get, - Field_ftsf269ae_slot0_Slot_ae_slot0_get, - Field_ftsf270ae_slot0_Slot_ae_slot0_get, - Field_ftsf271ae_slot0_Slot_ae_slot0_get, - Field_ftsf272ae_slot0_Slot_ae_slot0_get, - Field_ftsf273ae_slot0_Slot_ae_slot0_get, - Field_ftsf274ae_slot0_Slot_ae_slot0_get, - Field_ftsf275ae_slot0_Slot_ae_slot0_get, - Field_ftsf276ae_slot0_Slot_ae_slot0_get, - Field_ftsf277ae_slot0_Slot_ae_slot0_get, - Field_ftsf278ae_slot0_Slot_ae_slot0_get, - Field_ftsf279ae_slot0_Slot_ae_slot0_get, - Field_ftsf281ae_slot0_Slot_ae_slot0_get, - Field_ftsf282ae_slot0_Slot_ae_slot0_get, - Field_ftsf283ae_slot0_Slot_ae_slot0_get, - Field_ftsf284ae_slot0_Slot_ae_slot0_get, - Field_ftsf286ae_slot0_Slot_ae_slot0_get, - Field_ftsf288ae_slot0_Slot_ae_slot0_get, - Field_ftsf290ae_slot0_Slot_ae_slot0_get, - Field_ftsf292ae_slot0_Slot_ae_slot0_get, - Field_ftsf293_Slot_ae_slot0_get, - Field_ftsf294ae_slot0_Slot_ae_slot0_get, - Field_ftsf295ae_slot0_Slot_ae_slot0_get, - Field_ftsf296ae_slot0_Slot_ae_slot0_get, - Field_ftsf297ae_slot0_Slot_ae_slot0_get, - Field_ftsf298ae_slot0_Slot_ae_slot0_get, - Field_ftsf299ae_slot0_Slot_ae_slot0_get, - Field_ftsf300ae_slot0_Slot_ae_slot0_get, - Field_ftsf301ae_slot0_Slot_ae_slot0_get, - Field_ftsf302ae_slot0_Slot_ae_slot0_get, - Field_ftsf303ae_slot0_Slot_ae_slot0_get, - Field_ftsf304ae_slot0_Slot_ae_slot0_get, - Field_ftsf306ae_slot0_Slot_ae_slot0_get, - Field_ftsf308ae_slot0_Slot_ae_slot0_get, - Field_ftsf309ae_slot0_Slot_ae_slot0_get, - Field_ftsf310ae_slot0_Slot_ae_slot0_get, - Field_ftsf311ae_slot0_Slot_ae_slot0_get, - Field_ftsf312ae_slot0_Slot_ae_slot0_get, - Field_ftsf313ae_slot0_Slot_ae_slot0_get, - Field_ftsf314ae_slot0_Slot_ae_slot0_get, - Field_ftsf315ae_slot0_Slot_ae_slot0_get, - Field_ftsf316ae_slot0_Slot_ae_slot0_get, - Field_ftsf317ae_slot0_Slot_ae_slot0_get, - Field_ftsf318ae_slot0_Slot_ae_slot0_get, - Field_ftsf319_Slot_ae_slot0_get, - Field_ftsf320ae_slot0_Slot_ae_slot0_get, - Field_ftsf321_Slot_ae_slot0_get, - Field_ftsf322ae_slot0_Slot_ae_slot0_get, - Field_ftsf323ae_slot0_Slot_ae_slot0_get, - Field_ftsf324ae_slot0_Slot_ae_slot0_get, - Field_ftsf325ae_slot0_Slot_ae_slot0_get, - Field_ftsf326ae_slot0_Slot_ae_slot0_get, - Field_ftsf328ae_slot0_Slot_ae_slot0_get, - Field_ftsf329ae_slot0_Slot_ae_slot0_get, - Field_ftsf352ae_slot0_Slot_ae_slot0_get, - Field_ftsf353_Slot_ae_slot0_get, - Field_ftsf354ae_slot0_Slot_ae_slot0_get, - Field_ftsf356ae_slot0_Slot_ae_slot0_get, - Field_ftsf357_Slot_ae_slot0_get, - Field_ftsf358ae_slot0_Slot_ae_slot0_get, - Field_ftsf359ae_slot0_Slot_ae_slot0_get, - Field_ftsf360ae_slot0_Slot_ae_slot0_get, - Field_ftsf361ae_slot0_Slot_ae_slot0_get, - Field_ftsf362ae_slot0_Slot_ae_slot0_get, - Field_ftsf364ae_slot0_Slot_ae_slot0_get, - Field_ftsf365ae_slot0_Slot_ae_slot0_get, - Field_ftsf366ae_slot0_Slot_ae_slot0_get, - Field_ftsf368ae_slot0_Slot_ae_slot0_get, - Field_ftsf369ae_slot0_Slot_ae_slot0_get, - 0, - Field_combined1b97e84f_fld115_Slot_ae_slot0_get, - Field_combined1b97e84f_fld97_Slot_ae_slot0_get, - Field_combined1b97e84f_fld124_Slot_ae_slot0_get, - Field_combined1b97e84f_fld79_Slot_ae_slot0_get, - Field_combined1b97e84f_fld80_Slot_ae_slot0_get, - Field_combined1b97e84f_fld108_Slot_ae_slot0_get, - Field_combined1b97e84f_fld101_Slot_ae_slot0_get, - Field_combined1b97e84f_fld88_Slot_ae_slot0_get, - Field_combined1b97e84f_fld39_Slot_ae_slot0_get, - Field_op0_s4_s4_Slot_ae_slot0_get, - Field_combined1b97e84f_fld83_Slot_ae_slot0_get, - Field_combined1b97e84f_fld90_Slot_ae_slot0_get, - Field_combined1b97e84f_fld93_Slot_ae_slot0_get, - Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_get, - Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_get, - Field_combined4b12daa6_fld122_Slot_ae_slot0_get, - Field_combined4b12daa6_fld115_Slot_ae_slot0_get, - Field_combined4b12daa6_fld85_Slot_ae_slot0_get, - Field_combined4b12daa6_fld119_Slot_ae_slot0_get, - Field_combined4b12daa6_fld97_Slot_ae_slot0_get, - Field_combined4b12daa6_fld124_Slot_ae_slot0_get, - Field_combined4b12daa6_fld79_Slot_ae_slot0_get, - Field_combined4b12daa6_fld80_Slot_ae_slot0_get, - Field_combined4b12daa6_fld108_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_ae_slot0_set_field_fns[] = { - Field_t_Slot_ae_slot0_set, - 0, - Field_bbi_Slot_ae_slot0_set, - Field_imm12_Slot_ae_slot0_set, - Field_imm8_Slot_ae_slot0_set, - Field_s_Slot_ae_slot0_set, - Field_imm12b_Slot_ae_slot0_set, - Field_imm16_Slot_ae_slot0_set, - 0, - 0, - Field_offset_Slot_ae_slot0_set, - 0, - 0, - Field_op2_Slot_ae_slot0_set, - Field_r_Slot_ae_slot0_set, - 0, - 0, - Field_sae_Slot_ae_slot0_set, - Field_sal_Slot_ae_slot0_set, - Field_sargt_Slot_ae_slot0_set, - 0, - Field_sas_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_s4_Slot_ae_slot0_set, - 0, - 0, - Field_s8_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot0_set, - Field_ae_samt_s_t_Slot_ae_slot0_set, - Field_ae_r20_Slot_ae_slot0_set, - Field_ae_r10_Slot_ae_slot0_set, - Field_ae_s20_Slot_ae_slot0_set, - 0, - 0, - 0, - Field_ftsf12_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s4_Slot_ae_slot0_set, - Field_ftsf212ae_slot0_Slot_ae_slot0_set, - Field_ftsf213ae_slot0_Slot_ae_slot0_set, - Field_ftsf214ae_slot0_Slot_ae_slot0_set, - Field_ftsf215ae_slot0_Slot_ae_slot0_set, - Field_ftsf216ae_slot0_Slot_ae_slot0_set, - Field_ftsf217_Slot_ae_slot0_set, - Field_ftsf218ae_slot0_Slot_ae_slot0_set, - Field_ftsf219ae_slot0_Slot_ae_slot0_set, - Field_ftsf220ae_slot0_Slot_ae_slot0_set, - Field_ftsf221ae_slot0_Slot_ae_slot0_set, - Field_ftsf222ae_slot0_Slot_ae_slot0_set, - Field_ftsf223ae_slot0_Slot_ae_slot0_set, - Field_ftsf224ae_slot0_Slot_ae_slot0_set, - Field_ftsf225ae_slot0_Slot_ae_slot0_set, - Field_ftsf226ae_slot0_Slot_ae_slot0_set, - Field_ftsf227ae_slot0_Slot_ae_slot0_set, - Field_ftsf228ae_slot0_Slot_ae_slot0_set, - Field_ftsf229ae_slot0_Slot_ae_slot0_set, - Field_ftsf230ae_slot0_Slot_ae_slot0_set, - Field_ftsf231ae_slot0_Slot_ae_slot0_set, - Field_ftsf232ae_slot0_Slot_ae_slot0_set, - Field_ftsf233ae_slot0_Slot_ae_slot0_set, - Field_ftsf234ae_slot0_Slot_ae_slot0_set, - Field_ftsf235ae_slot0_Slot_ae_slot0_set, - Field_ftsf236ae_slot0_Slot_ae_slot0_set, - Field_ftsf237ae_slot0_Slot_ae_slot0_set, - Field_ftsf238ae_slot0_Slot_ae_slot0_set, - Field_ftsf239ae_slot0_Slot_ae_slot0_set, - Field_ftsf240ae_slot0_Slot_ae_slot0_set, - Field_ftsf241ae_slot0_Slot_ae_slot0_set, - Field_ftsf242ae_slot0_Slot_ae_slot0_set, - Field_ftsf243ae_slot0_Slot_ae_slot0_set, - Field_ftsf244ae_slot0_Slot_ae_slot0_set, - Field_ftsf245ae_slot0_Slot_ae_slot0_set, - Field_ftsf246ae_slot0_Slot_ae_slot0_set, - Field_ftsf247ae_slot0_Slot_ae_slot0_set, - Field_ftsf248ae_slot0_Slot_ae_slot0_set, - Field_ftsf249ae_slot0_Slot_ae_slot0_set, - Field_ftsf250ae_slot0_Slot_ae_slot0_set, - Field_ftsf251ae_slot0_Slot_ae_slot0_set, - Field_ftsf252ae_slot0_Slot_ae_slot0_set, - Field_ftsf253ae_slot0_Slot_ae_slot0_set, - Field_ftsf254ae_slot0_Slot_ae_slot0_set, - Field_ftsf255ae_slot0_Slot_ae_slot0_set, - Field_ftsf256ae_slot0_Slot_ae_slot0_set, - Field_ftsf257ae_slot0_Slot_ae_slot0_set, - Field_ftsf258ae_slot0_Slot_ae_slot0_set, - Field_ftsf259ae_slot0_Slot_ae_slot0_set, - Field_ftsf260ae_slot0_Slot_ae_slot0_set, - Field_ftsf261ae_slot0_Slot_ae_slot0_set, - Field_ftsf262ae_slot0_Slot_ae_slot0_set, - Field_ftsf263ae_slot0_Slot_ae_slot0_set, - Field_ftsf264ae_slot0_Slot_ae_slot0_set, - Field_ftsf265ae_slot0_Slot_ae_slot0_set, - Field_ftsf266ae_slot0_Slot_ae_slot0_set, - Field_ftsf267ae_slot0_Slot_ae_slot0_set, - Field_ftsf268ae_slot0_Slot_ae_slot0_set, - Field_ftsf269ae_slot0_Slot_ae_slot0_set, - Field_ftsf270ae_slot0_Slot_ae_slot0_set, - Field_ftsf271ae_slot0_Slot_ae_slot0_set, - Field_ftsf272ae_slot0_Slot_ae_slot0_set, - Field_ftsf273ae_slot0_Slot_ae_slot0_set, - Field_ftsf274ae_slot0_Slot_ae_slot0_set, - Field_ftsf275ae_slot0_Slot_ae_slot0_set, - Field_ftsf276ae_slot0_Slot_ae_slot0_set, - Field_ftsf277ae_slot0_Slot_ae_slot0_set, - Field_ftsf278ae_slot0_Slot_ae_slot0_set, - Field_ftsf279ae_slot0_Slot_ae_slot0_set, - Field_ftsf281ae_slot0_Slot_ae_slot0_set, - Field_ftsf282ae_slot0_Slot_ae_slot0_set, - Field_ftsf283ae_slot0_Slot_ae_slot0_set, - Field_ftsf284ae_slot0_Slot_ae_slot0_set, - Field_ftsf286ae_slot0_Slot_ae_slot0_set, - Field_ftsf288ae_slot0_Slot_ae_slot0_set, - Field_ftsf290ae_slot0_Slot_ae_slot0_set, - Field_ftsf292ae_slot0_Slot_ae_slot0_set, - Field_ftsf293_Slot_ae_slot0_set, - Field_ftsf294ae_slot0_Slot_ae_slot0_set, - Field_ftsf295ae_slot0_Slot_ae_slot0_set, - Field_ftsf296ae_slot0_Slot_ae_slot0_set, - Field_ftsf297ae_slot0_Slot_ae_slot0_set, - Field_ftsf298ae_slot0_Slot_ae_slot0_set, - Field_ftsf299ae_slot0_Slot_ae_slot0_set, - Field_ftsf300ae_slot0_Slot_ae_slot0_set, - Field_ftsf301ae_slot0_Slot_ae_slot0_set, - Field_ftsf302ae_slot0_Slot_ae_slot0_set, - Field_ftsf303ae_slot0_Slot_ae_slot0_set, - Field_ftsf304ae_slot0_Slot_ae_slot0_set, - Field_ftsf306ae_slot0_Slot_ae_slot0_set, - Field_ftsf308ae_slot0_Slot_ae_slot0_set, - Field_ftsf309ae_slot0_Slot_ae_slot0_set, - Field_ftsf310ae_slot0_Slot_ae_slot0_set, - Field_ftsf311ae_slot0_Slot_ae_slot0_set, - Field_ftsf312ae_slot0_Slot_ae_slot0_set, - Field_ftsf313ae_slot0_Slot_ae_slot0_set, - Field_ftsf314ae_slot0_Slot_ae_slot0_set, - Field_ftsf315ae_slot0_Slot_ae_slot0_set, - Field_ftsf316ae_slot0_Slot_ae_slot0_set, - Field_ftsf317ae_slot0_Slot_ae_slot0_set, - Field_ftsf318ae_slot0_Slot_ae_slot0_set, - Field_ftsf319_Slot_ae_slot0_set, - Field_ftsf320ae_slot0_Slot_ae_slot0_set, - Field_ftsf321_Slot_ae_slot0_set, - Field_ftsf322ae_slot0_Slot_ae_slot0_set, - Field_ftsf323ae_slot0_Slot_ae_slot0_set, - Field_ftsf324ae_slot0_Slot_ae_slot0_set, - Field_ftsf325ae_slot0_Slot_ae_slot0_set, - Field_ftsf326ae_slot0_Slot_ae_slot0_set, - Field_ftsf328ae_slot0_Slot_ae_slot0_set, - Field_ftsf329ae_slot0_Slot_ae_slot0_set, - Field_ftsf352ae_slot0_Slot_ae_slot0_set, - Field_ftsf353_Slot_ae_slot0_set, - Field_ftsf354ae_slot0_Slot_ae_slot0_set, - Field_ftsf356ae_slot0_Slot_ae_slot0_set, - Field_ftsf357_Slot_ae_slot0_set, - Field_ftsf358ae_slot0_Slot_ae_slot0_set, - Field_ftsf359ae_slot0_Slot_ae_slot0_set, - Field_ftsf360ae_slot0_Slot_ae_slot0_set, - Field_ftsf361ae_slot0_Slot_ae_slot0_set, - Field_ftsf362ae_slot0_Slot_ae_slot0_set, - Field_ftsf364ae_slot0_Slot_ae_slot0_set, - Field_ftsf365ae_slot0_Slot_ae_slot0_set, - Field_ftsf366ae_slot0_Slot_ae_slot0_set, - Field_ftsf368ae_slot0_Slot_ae_slot0_set, - Field_ftsf369ae_slot0_Slot_ae_slot0_set, - 0, - Field_combined1b97e84f_fld115_Slot_ae_slot0_set, - Field_combined1b97e84f_fld97_Slot_ae_slot0_set, - Field_combined1b97e84f_fld124_Slot_ae_slot0_set, - Field_combined1b97e84f_fld79_Slot_ae_slot0_set, - Field_combined1b97e84f_fld80_Slot_ae_slot0_set, - Field_combined1b97e84f_fld108_Slot_ae_slot0_set, - Field_combined1b97e84f_fld101_Slot_ae_slot0_set, - Field_combined1b97e84f_fld88_Slot_ae_slot0_set, - Field_combined1b97e84f_fld39_Slot_ae_slot0_set, - Field_op0_s4_s4_Slot_ae_slot0_set, - Field_combined1b97e84f_fld83_Slot_ae_slot0_set, - Field_combined1b97e84f_fld90_Slot_ae_slot0_set, - Field_combined1b97e84f_fld93_Slot_ae_slot0_set, - Field_combined1b97e84f_fld138ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld130ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld137ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld135ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld136ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld129ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld127ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld128ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld132ae_slot0_Slot_ae_slot0_set, - Field_combined1b97e84f_fld134ae_slot0_Slot_ae_slot0_set, - Field_combined4b12daa6_fld122_Slot_ae_slot0_set, - Field_combined4b12daa6_fld115_Slot_ae_slot0_set, - Field_combined4b12daa6_fld85_Slot_ae_slot0_set, - Field_combined4b12daa6_fld119_Slot_ae_slot0_set, - Field_combined4b12daa6_fld97_Slot_ae_slot0_set, - Field_combined4b12daa6_fld124_Slot_ae_slot0_set, - Field_combined4b12daa6_fld79_Slot_ae_slot0_set, - Field_combined4b12daa6_fld80_Slot_ae_slot0_set, - Field_combined4b12daa6_fld108_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_slot_internal slots[] = { - { "Inst", "x24", 0, - Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, - Slot_inst_get_field_fns, Slot_inst_set_field_fns, - Slot_inst_decode, "nop" }, - { "Inst16a", "x16a", 0, - Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, - Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, - Slot_inst16a_decode, "" }, - { "Inst16b", "x16b", 0, - Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, - Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, - Slot_inst16b_decode, "nop.n" }, - { "ae_slot1", "ae_format", 1, - Slot_ae_format_Format_ae_slot1_31_get, Slot_ae_format_Format_ae_slot1_31_set, - Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns, - Slot_ae_slot1_decode, "nop" }, - { "ae_slot0", "ae_format", 0, - Slot_ae_format_Format_ae_slot0_4_get, Slot_ae_format_Format_ae_slot0_4_set, - Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns, - Slot_ae_slot0_decode, "nop" } -}; - - -/* Instruction formats. */ - -static void -Format_x24_encode (xtensa_insnbuf insn) -{ - insn[0] = 0; - insn[1] = 0; -} - -static void -Format_x16a_encode (xtensa_insnbuf insn) -{ - insn[0] = 0x8; - insn[1] = 0; -} - -static void -Format_x16b_encode (xtensa_insnbuf insn) -{ - insn[0] = 0xc; - insn[1] = 0; -} - -static void -Format_ae_format_encode (xtensa_insnbuf insn) -{ - insn[0] = 0xf; - insn[1] = 0; -} - -static int Format_x24_slots[] = { 0 }; - -static int Format_x16a_slots[] = { 1 }; - -static int Format_x16b_slots[] = { 2 }; - -static int Format_ae_format_slots[] = { 4, 3 }; - -static xtensa_format_internal formats[] = { - { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, - { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, - { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, - { "ae_format", 8, Format_ae_format_encode, 2, Format_ae_format_slots } -}; - - -static int -format_decoder (const xtensa_insnbuf insn) -{ - if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0) - return 0; /* x24 */ - if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0) - return 1; /* x16a */ - if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0) - return 2; /* x16b */ - if ((insn[0] & 0xf) == 0xf && (insn[1] & 0xffc00000) == 0) - return 3; /* ae_format */ - return -1; -} - -static int length_table[16] = { - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8 -}; - -static int -length_decoder (const unsigned char *insn) -{ - int op0 = insn[0] & 0xf; - return length_table[op0]; -} - - -/* Top-level ISA structure. */ - -xtensa_isa_internal xtensa_modules = { - 0 /* little-endian */, - 8 /* insn_size */, 0, - 4, formats, format_decoder, length_decoder, - 5, slots, - 448 /* num_fields */, - 515, operands, - 710, iclasses, - 842, opcodes, 0, - 9, regfiles, - NUM_STATES, states, 0, - NUM_SYSREGS, sysregs, 0, - { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, - 0, interfaces, 0, - 4, funcUnits, 0 -}; diff --git a/overlays/xtensa_intel_byt_adsp/gdb/gdb/regformats/reg-xtensa.dat b/overlays/xtensa_intel_byt_adsp/gdb/gdb/regformats/reg-xtensa.dat deleted file mode 100644 index 89da5a1..0000000 --- a/overlays/xtensa_intel_byt_adsp/gdb/gdb/regformats/reg-xtensa.dat +++ /dev/null @@ -1,74 +0,0 @@ -name:xtensa -expedite:pc,windowbase,windowstart -32:pc -32:ar0 -32:ar1 -32:ar2 -32:ar3 -32:ar4 -32:ar5 -32:ar6 -32:ar7 -32:ar8 -32:ar9 -32:ar10 -32:ar11 -32:ar12 -32:ar13 -32:ar14 -32:ar15 -32:ar16 -32:ar17 -32:ar18 -32:ar19 -32:ar20 -32:ar21 -32:ar22 -32:ar23 -32:ar24 -32:ar25 -32:ar26 -32:ar27 -32:ar28 -32:ar29 -32:ar30 -32:ar31 -32:lbeg -32:lend -32:lcount -32:sar -32:prefctl -32:windowbase -32:windowstart -32:configid0 -32:sr176 -32:configid1 -32:sr208 -32:ps -32:threadptr -32:br -32:scompare1 -32:acclo -32:acchi -32:m0 -32:m1 -32:m2 -32:m3 -64:aep0 -64:aep1 -64:aep2 -64:aep3 -64:aep4 -64:aep5 -64:aep6 -64:aep7 -64:aeq0 -64:aeq1 -64:aeq2 -64:aeq3 -32:ae_ovf_sar -32:ae_bithead -32:ae_ts_fts_bu_bp -32:ae_sd_no -32:ae_cbegin0 -32:ae_cend0 diff --git a/overlays/xtensa_intel_byt_adsp/gdb/gdb/xtensa-config.c b/overlays/xtensa_intel_byt_adsp/gdb/gdb/xtensa-config.c deleted file mode 100644 index a7d966b..0000000 --- a/overlays/xtensa_intel_byt_adsp/gdb/gdb/xtensa-config.c +++ /dev/null @@ -1,314 +0,0 @@ -/* Configuration for the Xtensa architecture for GDB, the GNU debugger. - - Copyright (c) 2003-2017 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#define XTENSA_CONFIG_VERSION 0x60 - -#include "defs.h" -#include "xtensa-config.h" -#include "xtensa-tdep.h" - - - -/* Masked registers. */ -xtensa_reg_mask_t xtensa_submask0[] = { { 46, 0, 1 } }; -const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 }; -xtensa_reg_mask_t xtensa_submask1[] = { { 46, 1, 1 } }; -const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 }; -xtensa_reg_mask_t xtensa_submask2[] = { { 46, 2, 1 } }; -const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 }; -xtensa_reg_mask_t xtensa_submask3[] = { { 46, 3, 1 } }; -const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 }; -xtensa_reg_mask_t xtensa_submask4[] = { { 46, 4, 1 } }; -const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 }; -xtensa_reg_mask_t xtensa_submask5[] = { { 46, 5, 1 } }; -const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 }; -xtensa_reg_mask_t xtensa_submask6[] = { { 46, 6, 1 } }; -const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 }; -xtensa_reg_mask_t xtensa_submask7[] = { { 46, 7, 1 } }; -const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 }; -xtensa_reg_mask_t xtensa_submask8[] = { { 46, 8, 1 } }; -const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 }; -xtensa_reg_mask_t xtensa_submask9[] = { { 46, 9, 1 } }; -const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 }; -xtensa_reg_mask_t xtensa_submask10[] = { { 46, 10, 1 } }; -const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 }; -xtensa_reg_mask_t xtensa_submask11[] = { { 46, 11, 1 } }; -const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 }; -xtensa_reg_mask_t xtensa_submask12[] = { { 46, 12, 1 } }; -const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 }; -xtensa_reg_mask_t xtensa_submask13[] = { { 46, 13, 1 } }; -const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 }; -xtensa_reg_mask_t xtensa_submask14[] = { { 46, 14, 1 } }; -const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 }; -xtensa_reg_mask_t xtensa_submask15[] = { { 46, 15, 1 } }; -const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 }; -xtensa_reg_mask_t xtensa_submask16[] = { { 44, 0, 4 } }; -const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 }; -xtensa_reg_mask_t xtensa_submask17[] = { { 44, 5, 1 } }; -const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 }; -xtensa_reg_mask_t xtensa_submask18[] = { { 44, 18, 1 } }; -const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 }; -xtensa_reg_mask_t xtensa_submask19[] = { { 44, 4, 1 } }; -const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 }; -xtensa_reg_mask_t xtensa_submask20[] = { { 44, 16, 2 } }; -const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 }; -xtensa_reg_mask_t xtensa_submask21[] = { { 44, 8, 4 } }; -const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 }; -xtensa_reg_mask_t xtensa_submask22[] = { { 48, 0, 32 }, { 49, 0, 8 } }; -const xtensa_mask_t xtensa_mask22 = { 2, xtensa_submask22 }; -xtensa_reg_mask_t xtensa_submask23[] = { { 109, 8, 4 } }; -const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 }; -xtensa_reg_mask_t xtensa_submask24[] = { { 66, 6, 1 } }; -const xtensa_mask_t xtensa_mask24 = { 1, xtensa_submask24 }; -xtensa_reg_mask_t xtensa_submask25[] = { { 66, 0, 6 } }; -const xtensa_mask_t xtensa_mask25 = { 1, xtensa_submask25 }; -xtensa_reg_mask_t xtensa_submask26[] = { { 68, 0, 4 } }; -const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 }; -xtensa_reg_mask_t xtensa_submask27[] = { { 68, 4, 4 } }; -const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 }; -xtensa_reg_mask_t xtensa_submask28[] = { { 68, 12, 4 } }; -const xtensa_mask_t xtensa_mask28 = { 1, xtensa_submask28 }; -xtensa_reg_mask_t xtensa_submask29[] = { { 68, 8, 4 } }; -const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 }; -xtensa_reg_mask_t xtensa_submask30[] = { { 69, 0, 27 } }; -const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 }; -xtensa_reg_mask_t xtensa_submask31[] = { { 69, 27, 1 } }; -const xtensa_mask_t xtensa_mask31 = { 1, xtensa_submask31 }; - - -/* Register map. */ -static xtensa_register_t rmap[] = -{ - /* idx ofs bi sz al targno flags cp typ group name */ - XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0) - XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) - XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) - XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) - XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) - XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) - XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) - XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) - XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) - XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) - XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) - XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) - XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) - XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) - XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) - XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) - XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) - XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) - XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) - XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) - XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) - XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) - XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) - XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) - XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) - XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) - XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) - XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) - XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) - XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) - XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) - XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) - XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) - XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) - XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) - XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) - XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) - XTREG( 37,148, 8, 4, 4,0x0228,0x0006,-2, 2,0x1100,prefctl, 0,0,0,0,0,0) - XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) - XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) - XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) - XTREG( 41,164,32, 4, 4,0x02b0,0x0002,-2, 2,0x0000,sr176, 0,0,0,0,0,0) - XTREG( 42,168,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) - XTREG( 43,172,32, 4, 4,0x02d0,0x0002,-2, 2,0x0000,sr208, 0,0,0,0,0,0) - XTREG( 44,176,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) - XTREG( 45,180,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0) - XTREG( 46,184,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0) - XTREG( 47,188,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0) - XTREG( 48,192,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0) - XTREG( 49,196, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0) - XTREG( 50,200,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0) - XTREG( 51,204,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0) - XTREG( 52,208,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0) - XTREG( 53,212,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0) - XTREG( 54,216,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0, - "03:04:84:b2","03:04:84:a7",0,0,0,0) - XTREG( 55,224,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1, - "03:04:94:b2","03:04:94:a7",0,0,0,0) - XTREG( 56,232,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2, - "03:04:a4:b2","03:04:a4:a7",0,0,0,0) - XTREG( 57,240,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3, - "03:04:b4:b2","03:04:b4:a7",0,0,0,0) - XTREG( 58,248,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4, - "03:04:c4:b2","03:04:c4:a7",0,0,0,0) - XTREG( 59,256,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5, - "03:04:d4:b2","03:04:d4:a7",0,0,0,0) - XTREG( 60,264,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6, - "03:04:e4:b2","03:04:e4:a7",0,0,0,0) - XTREG( 61,272,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7, - "03:04:f4:b2","03:04:f4:a7",0,0,0,0) - XTREG( 62,280,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0, - "03:04:04:c3","03:04:04:c1",0,0,0,0) - XTREG( 63,288,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1, - "03:04:14:c3","03:04:44:c1",0,0,0,0) - XTREG( 64,296,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2, - "03:04:24:c3","03:04:84:c1",0,0,0,0) - XTREG( 65,304,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3, - "03:04:34:c3","03:04:c4:c1",0,0,0,0) - XTREG( 66,312, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0) - XTREG( 67,316,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0) - XTREG( 68,320,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0) - XTREG( 69,324,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no, 0,0,0,0,0,0) - XTREG( 70,328,32, 4, 4,0x03f6,0x0006, 1, 3,0x0110,ae_cbegin0, 0,0,0,0,0,0) - XTREG( 71,332,32, 4, 4,0x03f7,0x0006, 1, 3,0x0110,ae_cend0, 0,0,0,0,0,0) - XTREG( 72,336, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) - XTREG( 73,340, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) - XTREG( 74,344,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) - XTREG( 75,348,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) - XTREG( 76,352,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) - XTREG( 77,356,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) - XTREG( 78,360,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) - XTREG( 79,364,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) - XTREG( 80,368,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) - XTREG( 81,372,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) - XTREG( 82,376,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) - XTREG( 83,380,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) - XTREG( 84,384,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) - XTREG( 85,388,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) - XTREG( 86,392,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0) - XTREG( 87,396,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0) - XTREG( 88,400,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) - XTREG( 89,404,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) - XTREG( 90,408,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) - XTREG( 91,412,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) - XTREG( 92,416,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) - XTREG( 93,420,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0) - XTREG( 94,424,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0) - XTREG( 95,428,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) - XTREG( 96,432,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) - XTREG( 97,436,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) - XTREG( 98,440,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) - XTREG( 99,444,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) - XTREG(100,448,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0) - XTREG(101,452,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0) - XTREG(102,456, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0) - XTREG(103,460,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) - XTREG(104,464,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) - XTREG(105,468,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) - XTREG(106,472,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) - XTREG(107,476,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) - XTREG(108,480, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) - XTREG(109,484,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) - XTREG(110,488,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) - XTREG(111,492,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) - XTREG(112,496,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) - XTREG(113,500, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) - XTREG(114,504,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) - XTREG(115,508,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) - XTREG(116,512,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) - XTREG(117,516,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0) - XTREG(118,520,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0) - XTREG(119,524,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0) - XTREG(120,528,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0) - XTREG(121,532,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0) - XTREG(122,536,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0) - XTREG(123,540,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0) - XTREG(124,544,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0) - XTREG(125,548,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0) - XTREG(126,552,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0) - XTREG(127,556,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0) - XTREG(128,560,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0) - XTREG(129,564,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0) - XTREG(130,568,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0) - XTREG(131,572,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0) - XTREG(132,576,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0) - XTREG(133,580,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0) - XTREG(134,584, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0, - 0,0,&xtensa_mask0,0,0,0) - XTREG(135,585, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1, - 0,0,&xtensa_mask1,0,0,0) - XTREG(136,586, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2, - 0,0,&xtensa_mask2,0,0,0) - XTREG(137,587, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3, - 0,0,&xtensa_mask3,0,0,0) - XTREG(138,588, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4, - 0,0,&xtensa_mask4,0,0,0) - XTREG(139,589, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5, - 0,0,&xtensa_mask5,0,0,0) - XTREG(140,590, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6, - 0,0,&xtensa_mask6,0,0,0) - XTREG(141,591, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7, - 0,0,&xtensa_mask7,0,0,0) - XTREG(142,592, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8, - 0,0,&xtensa_mask8,0,0,0) - XTREG(143,593, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9, - 0,0,&xtensa_mask9,0,0,0) - XTREG(144,594, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10, - 0,0,&xtensa_mask10,0,0,0) - XTREG(145,595, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11, - 0,0,&xtensa_mask11,0,0,0) - XTREG(146,596, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12, - 0,0,&xtensa_mask12,0,0,0) - XTREG(147,597, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13, - 0,0,&xtensa_mask13,0,0,0) - XTREG(148,598, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14, - 0,0,&xtensa_mask14,0,0,0) - XTREG(149,599, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15, - 0,0,&xtensa_mask15,0,0,0) - XTREG(150,600, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel, - 0,0,&xtensa_mask16,0,0,0) - XTREG(151,604, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum, - 0,0,&xtensa_mask17,0,0,0) - XTREG(152,608, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe, - 0,0,&xtensa_mask18,0,0,0) - XTREG(153,612, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm, - 0,0,&xtensa_mask19,0,0,0) - XTREG(154,616, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc, - 0,0,&xtensa_mask20,0,0,0) - XTREG(155,620, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb, - 0,0,&xtensa_mask21,0,0,0) - XTREG(156,624,40, 8, 4,0x200e,0x0006,-2, 6,0x1010,acc, - 0,0,&xtensa_mask22,0,0,0) - XTREG(157,632, 4, 4, 4,0x2013,0x0006,-2, 6,0x1010,dbnum, - 0,0,&xtensa_mask23,0,0,0) - XTREG(158,636, 1, 4, 4,0x2014,0x0006, 1, 5,0x1010,ae_overflow, - 0,0,&xtensa_mask24,0,0,0) - XTREG(159,640, 6, 4, 4,0x2015,0x0006, 1, 5,0x1010,ae_sar, - 0,0,&xtensa_mask25,0,0,0) - XTREG(160,644, 4, 4, 4,0x2016,0x0006, 1, 5,0x1010,ae_bitptr, - 0,0,&xtensa_mask26,0,0,0) - XTREG(161,648, 4, 4, 4,0x2017,0x0006, 1, 5,0x1010,ae_bitsused, - 0,0,&xtensa_mask27,0,0,0) - XTREG(162,652, 4, 4, 4,0x2018,0x0006, 1, 5,0x1010,ae_tablesize, - 0,0,&xtensa_mask28,0,0,0) - XTREG(163,656, 4, 4, 4,0x2019,0x0006, 1, 5,0x1010,ae_first_ts, - 0,0,&xtensa_mask29,0,0,0) - XTREG(164,660,27, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_nextoffset, - 0,0,&xtensa_mask30,0,0,0) - XTREG_END -}; - -xtensa_gdbarch_tdep xtensa_tdep (rmap); diff --git a/overlays/xtensa_intel_byt_adsp/gdb/gdb/xtensa-xtregs.c b/overlays/xtensa_intel_byt_adsp/gdb/gdb/xtensa-xtregs.c deleted file mode 100644 index cada981..0000000 --- a/overlays/xtensa_intel_byt_adsp/gdb/gdb/xtensa-xtregs.c +++ /dev/null @@ -1,68 +0,0 @@ -/* Customized table mapping between kernel xtregset and GDB register cache. - - Copyright (c) 2007-2010 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - - -typedef struct { - int gdb_regnum; - int gdb_offset; - int ptrace_cp_offset; - int ptrace_offset; - int size; - int coproc; - int dbnum; - char* name -;} xtensa_regtable_t; - -#define XTENSA_ELF_XTREG_SIZE 152 - -const xtensa_regtable_t xtensa_regmap_table[] = { - /* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */ - { 46, 184, 24, 24, 4, -1, 0x0204, "br" }, - { 47, 188, 28, 28, 4, -1, 0x020c, "scompare1" }, - { 48, 192, 0, 0, 4, -1, 0x0210, "acclo" }, - { 49, 196, 4, 4, 4, -1, 0x0211, "acchi" }, - { 50, 200, 8, 8, 4, -1, 0x0220, "m0" }, - { 51, 204, 12, 12, 4, -1, 0x0221, "m1" }, - { 52, 208, 16, 16, 4, -1, 0x0222, "m2" }, - { 53, 212, 20, 20, 4, -1, 0x0223, "m3" }, - { 54, 216, 24, 56, 8, 1, 0x0060, "aep0" }, - { 55, 224, 32, 64, 8, 1, 0x0061, "aep1" }, - { 56, 232, 40, 72, 8, 1, 0x0062, "aep2" }, - { 57, 240, 48, 80, 8, 1, 0x0063, "aep3" }, - { 58, 248, 56, 88, 8, 1, 0x0064, "aep4" }, - { 59, 256, 64, 96, 8, 1, 0x0065, "aep5" }, - { 60, 264, 72, 104, 8, 1, 0x0066, "aep6" }, - { 61, 272, 80, 112, 8, 1, 0x0067, "aep7" }, - { 62, 280, 88, 120, 8, 1, 0x0068, "aeq0" }, - { 63, 288, 96, 128, 8, 1, 0x0069, "aeq1" }, - { 64, 296, 104, 136, 8, 1, 0x006a, "aeq2" }, - { 65, 304, 112, 144, 8, 1, 0x006b, "aeq3" }, - { 66, 312, 0, 32, 4, 1, 0x03f0, "ae_ovf_sar" }, - { 67, 316, 4, 36, 4, 1, 0x03f1, "ae_bithead" }, - { 68, 320, 8, 40, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" }, - { 69, 324, 12, 44, 4, 1, 0x03f3, "ae_sd_no" }, - { 70, 328, 16, 48, 4, 1, 0x03f6, "ae_cbegin0" }, - { 71, 332, 20, 52, 4, 1, 0x03f7, "ae_cend0" }, - { 0 } -}; - diff --git a/overlays/xtensa_intel_byt_adsp/gdb/gdbserver/xtensa-xtregs.cc b/overlays/xtensa_intel_byt_adsp/gdb/gdbserver/xtensa-xtregs.cc deleted file mode 100644 index cada981..0000000 --- a/overlays/xtensa_intel_byt_adsp/gdb/gdbserver/xtensa-xtregs.cc +++ /dev/null @@ -1,68 +0,0 @@ -/* Customized table mapping between kernel xtregset and GDB register cache. - - Copyright (c) 2007-2010 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - - -typedef struct { - int gdb_regnum; - int gdb_offset; - int ptrace_cp_offset; - int ptrace_offset; - int size; - int coproc; - int dbnum; - char* name -;} xtensa_regtable_t; - -#define XTENSA_ELF_XTREG_SIZE 152 - -const xtensa_regtable_t xtensa_regmap_table[] = { - /* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */ - { 46, 184, 24, 24, 4, -1, 0x0204, "br" }, - { 47, 188, 28, 28, 4, -1, 0x020c, "scompare1" }, - { 48, 192, 0, 0, 4, -1, 0x0210, "acclo" }, - { 49, 196, 4, 4, 4, -1, 0x0211, "acchi" }, - { 50, 200, 8, 8, 4, -1, 0x0220, "m0" }, - { 51, 204, 12, 12, 4, -1, 0x0221, "m1" }, - { 52, 208, 16, 16, 4, -1, 0x0222, "m2" }, - { 53, 212, 20, 20, 4, -1, 0x0223, "m3" }, - { 54, 216, 24, 56, 8, 1, 0x0060, "aep0" }, - { 55, 224, 32, 64, 8, 1, 0x0061, "aep1" }, - { 56, 232, 40, 72, 8, 1, 0x0062, "aep2" }, - { 57, 240, 48, 80, 8, 1, 0x0063, "aep3" }, - { 58, 248, 56, 88, 8, 1, 0x0064, "aep4" }, - { 59, 256, 64, 96, 8, 1, 0x0065, "aep5" }, - { 60, 264, 72, 104, 8, 1, 0x0066, "aep6" }, - { 61, 272, 80, 112, 8, 1, 0x0067, "aep7" }, - { 62, 280, 88, 120, 8, 1, 0x0068, "aeq0" }, - { 63, 288, 96, 128, 8, 1, 0x0069, "aeq1" }, - { 64, 296, 104, 136, 8, 1, 0x006a, "aeq2" }, - { 65, 304, 112, 144, 8, 1, 0x006b, "aeq3" }, - { 66, 312, 0, 32, 4, 1, 0x03f0, "ae_ovf_sar" }, - { 67, 316, 4, 36, 4, 1, 0x03f1, "ae_bithead" }, - { 68, 320, 8, 40, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" }, - { 69, 324, 12, 44, 4, 1, 0x03f3, "ae_sd_no" }, - { 70, 328, 16, 48, 4, 1, 0x03f6, "ae_cbegin0" }, - { 71, 332, 20, 52, 4, 1, 0x03f7, "ae_cend0" }, - { 0 } -}; - diff --git a/overlays/xtensa_intel_byt_adsp/gdb/include/xtensa-config.h b/overlays/xtensa_intel_byt_adsp/gdb/include/xtensa-config.h deleted file mode 100644 index f60dc1f..0000000 --- a/overlays/xtensa_intel_byt_adsp/gdb/include/xtensa-config.h +++ /dev/null @@ -1,174 +0,0 @@ -/* Xtensa configuration settings. - Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 - Free Software Foundation, Inc. - Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef XTENSA_CONFIG_H -#define XTENSA_CONFIG_H - -/* The macros defined here match those with the same names in the Xtensa - compile-time HAL (Hardware Abstraction Layer). Please refer to the - Xtensa System Software Reference Manual for documentation of these - macros. */ - -#undef XCHAL_HAVE_BE -#define XCHAL_HAVE_BE 0 - -#undef XCHAL_HAVE_DENSITY -#define XCHAL_HAVE_DENSITY 1 - -#undef XCHAL_HAVE_CONST16 -#define XCHAL_HAVE_CONST16 0 - -#undef XCHAL_HAVE_ABS -#define XCHAL_HAVE_ABS 1 - -#undef XCHAL_HAVE_ADDX -#define XCHAL_HAVE_ADDX 1 - -#undef XCHAL_HAVE_L32R -#define XCHAL_HAVE_L32R 1 - -#undef XSHAL_USE_ABSOLUTE_LITERALS -#define XSHAL_USE_ABSOLUTE_LITERALS 0 - -#undef XSHAL_HAVE_TEXT_SECTION_LITERALS -#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ - -#undef XCHAL_HAVE_MAC16 -#define XCHAL_HAVE_MAC16 1 - -#undef XCHAL_HAVE_MUL16 -#define XCHAL_HAVE_MUL16 1 - -#undef XCHAL_HAVE_MUL32 -#define XCHAL_HAVE_MUL32 1 - -#undef XCHAL_HAVE_MUL32_HIGH -#define XCHAL_HAVE_MUL32_HIGH 1 - -#undef XCHAL_HAVE_DIV32 -#define XCHAL_HAVE_DIV32 0 - -#undef XCHAL_HAVE_NSA -#define XCHAL_HAVE_NSA 1 - -#undef XCHAL_HAVE_MINMAX -#define XCHAL_HAVE_MINMAX 1 - -#undef XCHAL_HAVE_SEXT -#define XCHAL_HAVE_SEXT 1 - -#undef XCHAL_HAVE_LOOPS -#define XCHAL_HAVE_LOOPS 1 - -#undef XCHAL_HAVE_THREADPTR -#define XCHAL_HAVE_THREADPTR 1 - -#undef XCHAL_HAVE_RELEASE_SYNC -#define XCHAL_HAVE_RELEASE_SYNC 1 - -#undef XCHAL_HAVE_S32C1I -#define XCHAL_HAVE_S32C1I 1 - -#undef XCHAL_HAVE_BOOLEANS -#define XCHAL_HAVE_BOOLEANS 1 - -#undef XCHAL_HAVE_FP -#define XCHAL_HAVE_FP 0 - -#undef XCHAL_HAVE_FP_DIV -#define XCHAL_HAVE_FP_DIV 0 - -#undef XCHAL_HAVE_FP_RECIP -#define XCHAL_HAVE_FP_RECIP 0 - -#undef XCHAL_HAVE_FP_SQRT -#define XCHAL_HAVE_FP_SQRT 0 - -#undef XCHAL_HAVE_FP_RSQRT -#define XCHAL_HAVE_FP_RSQRT 0 - -#undef XCHAL_HAVE_DFP_accel -#define XCHAL_HAVE_DFP_accel 0 -#undef XCHAL_HAVE_WINDOWED -#define XCHAL_HAVE_WINDOWED 1 - -#undef XCHAL_NUM_AREGS -#define XCHAL_NUM_AREGS 32 - -#undef XCHAL_HAVE_WIDE_BRANCHES -#define XCHAL_HAVE_WIDE_BRANCHES 0 - -#undef XCHAL_HAVE_PREDICTED_BRANCHES -#define XCHAL_HAVE_PREDICTED_BRANCHES 0 - - -#undef XCHAL_ICACHE_SIZE -#define XCHAL_ICACHE_SIZE 49152 - -#undef XCHAL_DCACHE_SIZE -#define XCHAL_DCACHE_SIZE 98304 - -#undef XCHAL_ICACHE_LINESIZE -#define XCHAL_ICACHE_LINESIZE 128 - -#undef XCHAL_DCACHE_LINESIZE -#define XCHAL_DCACHE_LINESIZE 128 - -#undef XCHAL_ICACHE_LINEWIDTH -#define XCHAL_ICACHE_LINEWIDTH 7 - -#undef XCHAL_DCACHE_LINEWIDTH -#define XCHAL_DCACHE_LINEWIDTH 7 - -#undef XCHAL_DCACHE_IS_WRITEBACK -#define XCHAL_DCACHE_IS_WRITEBACK 1 - - -#undef XCHAL_HAVE_MMU -#define XCHAL_HAVE_MMU 0 - - -#undef XCHAL_HAVE_DEBUG -#define XCHAL_HAVE_DEBUG 1 - -#undef XCHAL_NUM_IBREAK -#define XCHAL_NUM_IBREAK 2 - -#undef XCHAL_NUM_DBREAK -#define XCHAL_NUM_DBREAK 2 - -#undef XCHAL_DEBUGLEVEL -#define XCHAL_DEBUGLEVEL 6 - - -#undef XCHAL_MAX_INSTRUCTION_SIZE -#define XCHAL_MAX_INSTRUCTION_SIZE 8 - -#undef XCHAL_INST_FETCH_WIDTH -#define XCHAL_INST_FETCH_WIDTH 8 - - -#undef XSHAL_ABI -#undef XTHAL_ABI_WINDOWED -#undef XTHAL_ABI_CALL0 -#define XSHAL_ABI XTHAL_ABI_WINDOWED -#define XTHAL_ABI_WINDOWED 0 -#define XTHAL_ABI_CALL0 1 - -#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_intel_byt_adsp/linux/arch/xtensa/variants/byt/include/variant/core.h b/overlays/xtensa_intel_byt_adsp/linux/arch/xtensa/variants/byt/include/variant/core.h deleted file mode 100644 index 0d7c79f..0000000 --- a/overlays/xtensa_intel_byt_adsp/linux/arch/xtensa/variants/byt/include/variant/core.h +++ /dev/null @@ -1,492 +0,0 @@ -/* - * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa - * processor CORE configuration - * - * See , which includes this file, for more details. - */ - -/* Xtensa processor core configuration information. - - Copyright (c) 1999-2017 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#ifndef _XTENSA_CORE_CONFIGURATION_H -#define _XTENSA_CORE_CONFIGURATION_H - - -/**************************************************************************** - Parameters Useful for Any Code, USER or PRIVILEGED - ****************************************************************************/ - -/* - * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is - * configured, and a value of 0 otherwise. These macros are always defined. - */ - - -/*---------------------------------------------------------------------- - ISA - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ -#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ -#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ -#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ -#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */ -#define XCHAL_HAVE_DEBUG 1 /* debug option */ -#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ -#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ -#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ -#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ -#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ -#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ -#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ -#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ -#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ -#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */ -#define XCHAL_HAVE_L32R 1 /* L32R instruction */ -#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ -#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ -#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ -#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ -#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ -#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ -#define XCHAL_HAVE_ABS 1 /* ABS instruction */ -/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ -/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ -#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ -#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ -#define XCHAL_HAVE_SPECULATION 0 /* speculation */ -#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ -#define XCHAL_NUM_CONTEXTS 1 /* */ -#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */ -#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ -#define XCHAL_HAVE_PRID 1 /* processor ID register */ -#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ -#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ -#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ -#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ -#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ -#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ -#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ -#define XCHAL_HAVE_MAC16 1 /* MAC16 package */ -#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ -#define XCHAL_HAVE_FP 0 /* floating point pkg */ -#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ -#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */ -#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ -#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ -#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ -#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ -#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */ -#define XCHAL_HAVE_HIFI2_MUL32X24 1 /* HiFi2 and 32x24 MACs */ -#define XCHAL_HAVE_HIFI2EP 1 /* HiFi2EP */ -#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ -#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ -#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ -#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ -#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ -#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ -#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ -#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ -#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ -#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ -#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ -#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ - - -/*---------------------------------------------------------------------- - MISC - ----------------------------------------------------------------------*/ - -#define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */ -#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */ -#define XCHAL_DATA_WIDTH 8 /* data width in bytes */ -/* In T1050, applies to selected core load and store instructions (see ISA): */ -#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ -#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/ -#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ -#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/ - -#define XCHAL_SW_VERSION 900005 /* sw version of this header */ - -#define XCHAL_CORE_ID "Intel_HiFiEP" /* alphanum core name - (CoreID) set in the Xtensa - Processor Generator */ - -#define XCHAL_BUILD_UNIQUE_ID 0x000668E9 /* 22-bit sw build ID */ - -/* - * These definitions describe the hardware targeted by this software. - */ -#define XCHAL_HW_CONFIGID0 0xC3B3CFFE /* ConfigID hi 32 bits*/ -#define XCHAL_HW_CONFIGID1 0x15455C8A /* ConfigID lo 32 bits*/ -#define XCHAL_HW_VERSION_NAME "LX4.0.5" /* full version name */ -#define XCHAL_HW_VERSION_MAJOR 2400 /* major ver# of targeted hw */ -#define XCHAL_HW_VERSION_MINOR 5 /* minor ver# of targeted hw */ -#define XCHAL_HW_VERSION 240005 /* major*100+minor */ -#define XCHAL_HW_REL_LX4 1 -#define XCHAL_HW_REL_LX4_0 1 -#define XCHAL_HW_REL_LX4_0_5 1 -#define XCHAL_HW_CONFIGID_RELIABLE 1 -/* If software targets a *range* of hardware versions, these are the bounds: */ -#define XCHAL_HW_MIN_VERSION_MAJOR 2400 /* major v of earliest tgt hw */ -#define XCHAL_HW_MIN_VERSION_MINOR 5 /* minor v of earliest tgt hw */ -#define XCHAL_HW_MIN_VERSION 240005 /* earliest targeted hw */ -#define XCHAL_HW_MAX_VERSION_MAJOR 2400 /* major v of latest tgt hw */ -#define XCHAL_HW_MAX_VERSION_MINOR 5 /* minor v of latest tgt hw */ -#define XCHAL_HW_MAX_VERSION 240005 /* latest targeted hw */ - - -/*---------------------------------------------------------------------- - CACHE - ----------------------------------------------------------------------*/ - -#define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ -#define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ -#define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */ -#define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */ - -#define XCHAL_ICACHE_SIZE 49152 /* I-cache size in bytes or 0 */ -#define XCHAL_DCACHE_SIZE 98304 /* D-cache size in bytes or 0 */ - -#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ -#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ - -#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ - - - - -/**************************************************************************** - Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code - ****************************************************************************/ - - -#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY - -/*---------------------------------------------------------------------- - CACHE - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ - -/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ - -/* Number of cache sets in log2(lines per way): */ -#define XCHAL_ICACHE_SETWIDTH 7 -#define XCHAL_DCACHE_SETWIDTH 8 - -/* Cache set associativity (number of ways): */ -#define XCHAL_ICACHE_WAYS 3 -#define XCHAL_DCACHE_WAYS 3 - -/* Cache features: */ -#define XCHAL_ICACHE_LINE_LOCKABLE 1 -#define XCHAL_DCACHE_LINE_LOCKABLE 1 -#define XCHAL_ICACHE_ECC_PARITY 0 -#define XCHAL_DCACHE_ECC_PARITY 0 - -/* Cache access size in bytes (affects operation of SICW instruction): */ -#define XCHAL_ICACHE_ACCESS_SIZE 8 -#define XCHAL_DCACHE_ACCESS_SIZE 8 - -/* Number of encoded cache attr bits (see for decoded bits): */ -#define XCHAL_CA_BITS 4 - - -/*---------------------------------------------------------------------- - INTERNAL I/D RAM/ROMs and XLMI - ----------------------------------------------------------------------*/ - -#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ -#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */ -#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ -#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ -#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ -#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ - -/* Instruction RAM 0: */ -#define XCHAL_INSTRAM0_VADDR 0xFF2C0000 -#define XCHAL_INSTRAM0_PADDR 0xFF2C0000 -#define XCHAL_INSTRAM0_SIZE 65536 -#define XCHAL_INSTRAM0_ECC_PARITY 0 - -/* Instruction RAM 1: */ -#define XCHAL_INSTRAM1_VADDR 0xFF2D0000 -#define XCHAL_INSTRAM1_PADDR 0xFF2D0000 -#define XCHAL_INSTRAM1_SIZE 16384 -#define XCHAL_INSTRAM1_ECC_PARITY 0 - -/* Data RAM 0: */ -#define XCHAL_DATARAM0_VADDR 0xFF300000 -#define XCHAL_DATARAM0_PADDR 0xFF300000 -#define XCHAL_DATARAM0_SIZE 131072 -#define XCHAL_DATARAM0_ECC_PARITY 0 - -/* Data RAM 1: */ -#define XCHAL_DATARAM1_VADDR 0xFF320000 -#define XCHAL_DATARAM1_PADDR 0xFF320000 -#define XCHAL_DATARAM1_SIZE 32768 -#define XCHAL_DATARAM1_ECC_PARITY 0 - -#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ - - -/*---------------------------------------------------------------------- - INTERRUPTS and TIMERS - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ -#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ -#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ -#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ -#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ -#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ -#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ -#define XCHAL_NUM_EXTINTERRUPTS 12 /* num of external interrupts */ -#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels - (not including level zero) */ -#define XCHAL_EXCM_LEVEL 5 /* level masked by PS.EXCM */ - /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ - -/* Masks of interrupts at each interrupt level: */ -#define XCHAL_INTLEVEL1_MASK 0x0000000F -#define XCHAL_INTLEVEL2_MASK 0x00000070 -#define XCHAL_INTLEVEL3_MASK 0x00000380 -#define XCHAL_INTLEVEL4_MASK 0x00200C00 -#define XCHAL_INTLEVEL5_MASK 0x000FF000 -#define XCHAL_INTLEVEL6_MASK 0x00000000 -#define XCHAL_INTLEVEL7_MASK 0x00100000 - -/* Masks of interrupts at each range 1..n of interrupt levels: */ -#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0000000F -#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x0000007F -#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x000003FF -#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00200FFF -#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x002FFFFF -#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x002FFFFF -#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF - -/* Level of each interrupt: */ -#define XCHAL_INT0_LEVEL 1 -#define XCHAL_INT1_LEVEL 1 -#define XCHAL_INT2_LEVEL 1 -#define XCHAL_INT3_LEVEL 1 -#define XCHAL_INT4_LEVEL 2 -#define XCHAL_INT5_LEVEL 2 -#define XCHAL_INT6_LEVEL 2 -#define XCHAL_INT7_LEVEL 3 -#define XCHAL_INT8_LEVEL 3 -#define XCHAL_INT9_LEVEL 3 -#define XCHAL_INT10_LEVEL 4 -#define XCHAL_INT11_LEVEL 4 -#define XCHAL_INT12_LEVEL 5 -#define XCHAL_INT13_LEVEL 5 -#define XCHAL_INT14_LEVEL 5 -#define XCHAL_INT15_LEVEL 5 -#define XCHAL_INT16_LEVEL 5 -#define XCHAL_INT17_LEVEL 5 -#define XCHAL_INT18_LEVEL 5 -#define XCHAL_INT19_LEVEL 5 -#define XCHAL_INT20_LEVEL 7 -#define XCHAL_INT21_LEVEL 4 -#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ -#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ -#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with - EXCSAVE/EPS/EPC_n, RFI n) */ - -/* Type of each interrupt: */ -#define XCHAL_INT0_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT1_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT2_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT3_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT5_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT6_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT7_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT8_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT9_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT12_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT20_TYPE XTHAL_INTTYPE_NMI -#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL - -/* Masks of interrupts for each type of interrupt: */ -#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 -#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0000134D -#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000 -#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x002FEC10 -#define XCHAL_INTTYPE_MASK_TIMER 0x000000A2 -#define XCHAL_INTTYPE_MASK_NMI 0x00100000 -#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 - -/* Interrupt numbers assigned to specific interrupt sources: */ -#define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */ -#define XCHAL_TIMER1_INTERRUPT 5 /* CCOMPARE1 */ -#define XCHAL_TIMER2_INTERRUPT 7 /* CCOMPARE2 */ -#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED -#define XCHAL_NMI_INTERRUPT 20 /* non-maskable interrupt */ - -/* Interrupt numbers for levels at which only one interrupt is configured: */ -#define XCHAL_INTLEVEL7_NUM 20 -/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */ - - -/* - * External interrupt vectors/levels. - * These macros describe how Xtensa processor interrupt numbers - * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) - * map to external BInterrupt pins, for those interrupts - * configured as external (level-triggered, edge-triggered, or NMI). - * See the Xtensa processor databook for more details. - */ - -/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */ -#define XCHAL_EXTINT0_NUM 4 /* (intlevel 2) */ -#define XCHAL_EXTINT1_NUM 10 /* (intlevel 4) */ -#define XCHAL_EXTINT2_NUM 11 /* (intlevel 4) */ -#define XCHAL_EXTINT3_NUM 13 /* (intlevel 5) */ -#define XCHAL_EXTINT4_NUM 14 /* (intlevel 5) */ -#define XCHAL_EXTINT5_NUM 15 /* (intlevel 5) */ -#define XCHAL_EXTINT6_NUM 16 /* (intlevel 5) */ -#define XCHAL_EXTINT7_NUM 17 /* (intlevel 5) */ -#define XCHAL_EXTINT8_NUM 18 /* (intlevel 5) */ -#define XCHAL_EXTINT9_NUM 19 /* (intlevel 5) */ -#define XCHAL_EXTINT10_NUM 20 /* (intlevel 7) */ -#define XCHAL_EXTINT11_NUM 21 /* (intlevel 4) */ - - -/*---------------------------------------------------------------------- - EXCEPTIONS and VECTORS - ----------------------------------------------------------------------*/ - -#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture - number: 1 == XEA1 (old) - 2 == XEA2 (new) - 0 == XEAX (extern) or TX */ -#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ -#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ -#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ -#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ -#define XCHAL_HAVE_HALT 0 /* halt architecture option */ -#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ -#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ -#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ -#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ -#define XCHAL_VECBASE_RESET_VADDR 0x00100400 /* VECBASE reset value */ -#define XCHAL_VECBASE_RESET_PADDR 0x00100400 -#define XCHAL_RESET_VECBASE_OVERLAP 0 - -#define XCHAL_RESET_VECTOR0_VADDR 0x00100000 -#define XCHAL_RESET_VECTOR0_PADDR 0x00100000 -#define XCHAL_RESET_VECTOR1_VADDR 0xFF2C0000 -#define XCHAL_RESET_VECTOR1_PADDR 0xFF2C0000 -#define XCHAL_RESET_VECTOR_VADDR 0x00100000 -#define XCHAL_RESET_VECTOR_PADDR 0x00100000 -#define XCHAL_USER_VECOFS 0x0000025C -#define XCHAL_USER_VECTOR_VADDR 0x0010065C -#define XCHAL_USER_VECTOR_PADDR 0x0010065C -#define XCHAL_KERNEL_VECOFS 0x0000023C -#define XCHAL_KERNEL_VECTOR_VADDR 0x0010063C -#define XCHAL_KERNEL_VECTOR_PADDR 0x0010063C -#define XCHAL_DOUBLEEXC_VECOFS 0x0000027C -#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x0010067C -#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x0010067C -#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 -#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 -#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 -#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 -#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 -#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 -#define XCHAL_WINDOW_VECTORS_VADDR 0x00100400 -#define XCHAL_WINDOW_VECTORS_PADDR 0x00100400 -#define XCHAL_INTLEVEL2_VECOFS 0x0000017C -#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x0010057C -#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x0010057C -#define XCHAL_INTLEVEL3_VECOFS 0x0000019C -#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x0010059C -#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x0010059C -#define XCHAL_INTLEVEL4_VECOFS 0x000001BC -#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x001005BC -#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x001005BC -#define XCHAL_INTLEVEL5_VECOFS 0x000001DC -#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x001005DC -#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x001005DC -#define XCHAL_INTLEVEL6_VECOFS 0x000001FC -#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x001005FC -#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x001005FC -#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS -#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR -#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR -#define XCHAL_NMI_VECOFS 0x0000021C -#define XCHAL_NMI_VECTOR_VADDR 0x0010061C -#define XCHAL_NMI_VECTOR_PADDR 0x0010061C -#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS -#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR -#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR - - -/*---------------------------------------------------------------------- - DEBUG - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ -#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ -#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ -#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ - - -/*---------------------------------------------------------------------- - MMU - ----------------------------------------------------------------------*/ - -/* See core-matmap.h header file for more details. */ - -#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ -#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ -#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ -#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ -#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ -#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ -#define XCHAL_HAVE_XLT_CACHEATTR 1 /* region prot. w/translation */ -#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table - [autorefill] and protection) - usable for an MMU-based OS */ -/* If none of the above last 4 are set, it's a custom TLB configuration. */ - -#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ -#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ -#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ - -#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ - - -#endif /* _XTENSA_CORE_CONFIGURATION_H */ - diff --git a/overlays/xtensa_intel_byt_adsp/linux/arch/xtensa/variants/byt/include/variant/tie-asm.h b/overlays/xtensa_intel_byt_adsp/linux/arch/xtensa/variants/byt/include/variant/tie-asm.h deleted file mode 100644 index d2d824c..0000000 --- a/overlays/xtensa_intel_byt_adsp/linux/arch/xtensa/variants/byt/include/variant/tie-asm.h +++ /dev/null @@ -1,311 +0,0 @@ -/* - * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE - * - * NOTE: This header file is not meant to be included directly. - */ - -/* This header file contains assembly-language definitions (assembly - macros, etc.) for this specific Xtensa processor's TIE extensions - and options. It is customized to this Xtensa processor configuration. - - Copyright (c) 1999-2017 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#ifndef _XTENSA_CORE_TIE_ASM_H -#define _XTENSA_CORE_TIE_ASM_H - -/* Selection parameter values for save-area save/restore macros: */ -/* Option vs. TIE: */ -#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ -#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ -#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ -/* Whether used automatically by compiler: */ -#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ -#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ -#define XTHAL_SAS_ANYCC 0x000C /* both of the above */ -/* ABI handling across function calls: */ -#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ -#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ -#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ -#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ -/* Misc */ -#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ -#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ - | ((ccuse) & XTHAL_SAS_ANYCC) \ - | ((abi) & XTHAL_SAS_ANYABI) ) - - - - /* - * Macro to save all non-coprocessor (extra) custom TIE and optional state - * (not including zero-overhead loop registers). - * Required parameters: - * ptr Save area pointer address register (clobbered) - * (register must contain a 4 byte aligned address). - * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS - * registers are clobbered, the remaining are unused). - * Optional parameters: - * continue If macro invoked as part of a larger store sequence, set to 1 - * if this is not the first in the sequence. Defaults to 0. - * ofs Offset from start of larger sequence (from value of first ptr - * in sequence) at which to store. Defaults to next available space - * (or 0 if is 0). - * select Select what category(ies) of registers to store, as a bitmask - * (see XTHAL_SAS_xxx constants). Defaults to all registers. - * alloc Select what category(ies) of registers to allocate; if any - * category is selected here that is not in , space for - * the corresponding registers is skipped without doing any load. - */ - .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 - xchal_sa_start \continue, \ofs - // Optional global register used by default by the compiler: - .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) - xchal_sa_align \ptr, 0, 1020, 4, 4 - l32i \at1, \ptr, .Lxchal_ofs_+0 - wur.THREADPTR \at1 // threadptr option - .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 - .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 1020, 4, 4 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 - .endif - // Optional caller-saved registers used by default by the compiler: - .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) - xchal_sa_align \ptr, 0, 1016, 4, 4 - l32i \at1, \ptr, .Lxchal_ofs_+0 - wsr.ACCLO \at1 // MAC16 option - l32i \at1, \ptr, .Lxchal_ofs_+4 - wsr.ACCHI \at1 // MAC16 option - .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 - .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 1016, 4, 4 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 - .endif - // Optional caller-saved registers not used by default by the compiler: - .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) - xchal_sa_align \ptr, 0, 1000, 4, 4 - l32i \at1, \ptr, .Lxchal_ofs_+0 - wsr.M0 \at1 // MAC16 option - l32i \at1, \ptr, .Lxchal_ofs_+4 - wsr.M1 \at1 // MAC16 option - l32i \at1, \ptr, .Lxchal_ofs_+8 - wsr.M2 \at1 // MAC16 option - l32i \at1, \ptr, .Lxchal_ofs_+12 - wsr.M3 \at1 // MAC16 option - l32i \at1, \ptr, .Lxchal_ofs_+16 - wsr.BR \at1 // boolean option - l32i \at1, \ptr, .Lxchal_ofs_+20 - wsr.SCOMPARE1 \at1 // conditional store option - .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 - .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 1000, 4, 4 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 - .endif - .endm // xchal_ncp_load - - -#define XCHAL_NCP_NUM_ATMPS 1 - - - - - /* - * Macro to save the state of TIE coprocessor AudioEngineLX. - * Required parameters: - * ptr Save area pointer address register (clobbered) - * (register must contain a 8 byte aligned address). - * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS - * registers are clobbered, the remaining are unused). - * Optional parameters are the same as for xchal_ncp_store. - */ -#define xchal_cp_AudioEngineLX_store xchal_cp1_store - .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 - xchal_sa_start \continue, \ofs - // Custom caller-saved registers not used by default by the compiler: - .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) - xchal_sa_align \ptr, 0, 0, 8, 8 - rur.AE_OVF_SAR \at1 // ureg 240 - s32i \at1, \ptr, .Lxchal_ofs_+0 - rur.AE_BITHEAD \at1 // ureg 241 - s32i \at1, \ptr, .Lxchal_ofs_+4 - rur.AE_TS_FTS_BU_BP \at1 // ureg 242 - s32i \at1, \ptr, .Lxchal_ofs_+8 - rur.AE_SD_NO \at1 // ureg 243 - s32i \at1, \ptr, .Lxchal_ofs_+12 - rur.AE_CBEGIN0 \at1 // ureg 246 - s32i \at1, \ptr, .Lxchal_ofs_+16 - rur.AE_CEND0 \at1 // ureg 247 - s32i \at1, \ptr, .Lxchal_ofs_+20 - AE_SP24X2S.I aep0, \ptr, .Lxchal_ofs_+24 - AE_SP24X2S.I aep1, \ptr, .Lxchal_ofs_+32 - AE_SP24X2S.I aep2, \ptr, .Lxchal_ofs_+40 - AE_SP24X2S.I aep3, \ptr, .Lxchal_ofs_+48 - AE_SP24X2S.I aep4, \ptr, .Lxchal_ofs_+56 - addi \ptr, \ptr, 64 - AE_SP24X2S.I aep5, \ptr, .Lxchal_ofs_+0 - AE_SP24X2S.I aep6, \ptr, .Lxchal_ofs_+8 - AE_SP24X2S.I aep7, \ptr, .Lxchal_ofs_+16 - AE_SQ56S.I aeq0, \ptr, .Lxchal_ofs_+24 - AE_SQ56S.I aeq1, \ptr, .Lxchal_ofs_+32 - AE_SQ56S.I aeq2, \ptr, .Lxchal_ofs_+40 - AE_SQ56S.I aeq3, \ptr, .Lxchal_ofs_+48 - .set .Lxchal_pofs_, .Lxchal_pofs_ + 64 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 56 - .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 0, 8, 8 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 120 - .endif - .endm // xchal_cp1_store - - /* - * Macro to restore the state of TIE coprocessor AudioEngineLX. - * Required parameters: - * ptr Save area pointer address register (clobbered) - * (register must contain a 8 byte aligned address). - * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS - * registers are clobbered, the remaining are unused). - * Optional parameters are the same as for xchal_ncp_load. - */ -#define xchal_cp_AudioEngineLX_load xchal_cp1_load - .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 - xchal_sa_start \continue, \ofs - // Custom caller-saved registers not used by default by the compiler: - .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) - xchal_sa_align \ptr, 0, 0, 8, 8 - l32i \at1, \ptr, .Lxchal_ofs_+0 - wur.AE_OVF_SAR \at1 // ureg 240 - l32i \at1, \ptr, .Lxchal_ofs_+4 - wur.AE_BITHEAD \at1 // ureg 241 - l32i \at1, \ptr, .Lxchal_ofs_+8 - wur.AE_TS_FTS_BU_BP \at1 // ureg 242 - l32i \at1, \ptr, .Lxchal_ofs_+12 - wur.AE_SD_NO \at1 // ureg 243 - l32i \at1, \ptr, .Lxchal_ofs_+16 - wur.AE_CBEGIN0 \at1 // ureg 246 - l32i \at1, \ptr, .Lxchal_ofs_+20 - wur.AE_CEND0 \at1 // ureg 247 - AE_LP24X2.I aep0, \ptr, .Lxchal_ofs_+24 - AE_LP24X2.I aep1, \ptr, .Lxchal_ofs_+32 - AE_LP24X2.I aep2, \ptr, .Lxchal_ofs_+40 - AE_LP24X2.I aep3, \ptr, .Lxchal_ofs_+48 - AE_LP24X2.I aep4, \ptr, .Lxchal_ofs_+56 - addi \ptr, \ptr, 64 - AE_LP24X2.I aep5, \ptr, .Lxchal_ofs_+0 - AE_LP24X2.I aep6, \ptr, .Lxchal_ofs_+8 - AE_LP24X2.I aep7, \ptr, .Lxchal_ofs_+16 - AE_LQ56.I aeq0, \ptr, .Lxchal_ofs_+24 - AE_LQ56.I aeq1, \ptr, .Lxchal_ofs_+32 - AE_LQ56.I aeq2, \ptr, .Lxchal_ofs_+40 - AE_LQ56.I aeq3, \ptr, .Lxchal_ofs_+48 - .set .Lxchal_pofs_, .Lxchal_pofs_ + 64 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 56 - .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 0, 8, 8 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 120 - .endif - .endm // xchal_cp1_load - -#define XCHAL_CP1_NUM_ATMPS 1 -#define XCHAL_SA_NUM_ATMPS 1 - - /* Empty macros for unconfigured coprocessors: */ - .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - -#endif /*_XTENSA_CORE_TIE_ASM_H*/ - diff --git a/overlays/xtensa_intel_byt_adsp/linux/arch/xtensa/variants/byt/include/variant/tie.h b/overlays/xtensa_intel_byt_adsp/linux/arch/xtensa/variants/byt/include/variant/tie.h deleted file mode 100644 index cf16fe2..0000000 --- a/overlays/xtensa_intel_byt_adsp/linux/arch/xtensa/variants/byt/include/variant/tie.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration - * - * NOTE: This header file is not meant to be included directly. - */ - -/* This header file describes this specific Xtensa processor's TIE extensions - that extend basic Xtensa core functionality. It is customized to this - Xtensa processor configuration. - - Copyright (c) 1999-2017 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#ifndef _XTENSA_CORE_TIE_H -#define _XTENSA_CORE_TIE_H - -#define XCHAL_CP_NUM 1 /* number of coprocessors */ -#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */ -#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */ -#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ - -/* Basic parameters of each coprocessor: */ -#define XCHAL_CP1_NAME "AudioEngineLX" -#define XCHAL_CP1_IDENT AudioEngineLX -#define XCHAL_CP1_SA_SIZE 120 /* size of state save area */ -#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */ -#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */ - -/* Filler info for unassigned coprocessors, to simplify arrays etc: */ -#define XCHAL_CP0_SA_SIZE 0 -#define XCHAL_CP0_SA_ALIGN 1 -#define XCHAL_CP2_SA_SIZE 0 -#define XCHAL_CP2_SA_ALIGN 1 -#define XCHAL_CP3_SA_SIZE 0 -#define XCHAL_CP3_SA_ALIGN 1 -#define XCHAL_CP4_SA_SIZE 0 -#define XCHAL_CP4_SA_ALIGN 1 -#define XCHAL_CP5_SA_SIZE 0 -#define XCHAL_CP5_SA_ALIGN 1 -#define XCHAL_CP6_SA_SIZE 0 -#define XCHAL_CP6_SA_ALIGN 1 -#define XCHAL_CP7_SA_SIZE 0 -#define XCHAL_CP7_SA_ALIGN 1 - -/* Save area for non-coprocessor optional and custom (TIE) state: */ -#define XCHAL_NCP_SA_SIZE 36 -#define XCHAL_NCP_SA_ALIGN 4 - -/* Total save area for optional and custom state (NCP + CPn): */ -#define XCHAL_TOTAL_SA_SIZE 176 /* with 16-byte align padding */ -#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */ - -/* - * Detailed contents of save areas. - * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) - * before expanding the XCHAL_xxx_SA_LIST() macros. - * - * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, - * dbnum,base,regnum,bitsz,gapsz,reset,x...) - * - * s = passed from XCHAL_*_LIST(s), eg. to select how to expand - * ccused = set if used by compiler without special options or code - * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) - * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) - * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) - * name = lowercase reg name (no quotes) - * galign = group byte alignment (power of 2) (galign >= align) - * align = register byte alignment (power of 2) - * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) - * (not including any pad bytes required to galign this or next reg) - * dbnum = unique target number f/debug (see ) - * base = reg shortname w/o index (or sr=special, ur=TIE user reg) - * regnum = reg index in regfile, or special/TIE-user reg number - * bitsz = number of significant bits (regfile width, or ur/sr mask bits) - * gapsz = intervening bits, if bitsz bits not stored contiguously - * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) - * reset = register reset value (or 0 if undefined at reset) - * x = reserved for future use (0 until then) - * - * To filter out certain registers, e.g. to expand only the non-global - * registers used by the compiler, you can do something like this: - * - * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) - * #define SELCC0(p...) - * #define SELCC1(abikind,p...) SELAK##abikind(p) - * #define SELAK0(p...) REG(p) - * #define SELAK1(p...) REG(p) - * #define SELAK2(p...) - * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ - * ...what you want to expand... - */ - -#define XCHAL_NCP_SA_NUM 9 -#define XCHAL_NCP_SA_LIST(s) \ - XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ - XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ - XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ - XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ - XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) - -#define XCHAL_CP0_SA_NUM 0 -#define XCHAL_CP0_SA_LIST(s) /* empty */ - -#define XCHAL_CP1_SA_NUM 18 -#define XCHAL_CP1_SA_LIST(s) \ - XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 7,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0, ae_sd_no, 4, 4, 4,0x03F3, ur,243, 28,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0, ae_cbegin0, 4, 4, 4,0x03F6, ur,246, 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0, ae_cend0, 4, 4, 4,0x03F7, ur,247, 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aep0, 8, 8, 8,0x0060, aep,0 , 48,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aep1, 8, 8, 8,0x0061, aep,1 , 48,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aep2, 8, 8, 8,0x0062, aep,2 , 48,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aep3, 8, 8, 8,0x0063, aep,3 , 48,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aep4, 8, 8, 8,0x0064, aep,4 , 48,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aep5, 8, 8, 8,0x0065, aep,5 , 48,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aep6, 8, 8, 8,0x0066, aep,6 , 48,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aep7, 8, 8, 8,0x0067, aep,7 , 48,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aeq0, 8, 8, 8,0x0068, aeq,0 , 56,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aeq1, 8, 8, 8,0x0069, aeq,1 , 56,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aeq2, 8, 8, 8,0x006A, aeq,2 , 56,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aeq3, 8, 8, 8,0x006B, aeq,3 , 56,0,0,0) - -#define XCHAL_CP2_SA_NUM 0 -#define XCHAL_CP2_SA_LIST(s) /* empty */ - -#define XCHAL_CP3_SA_NUM 0 -#define XCHAL_CP3_SA_LIST(s) /* empty */ - -#define XCHAL_CP4_SA_NUM 0 -#define XCHAL_CP4_SA_LIST(s) /* empty */ - -#define XCHAL_CP5_SA_NUM 0 -#define XCHAL_CP5_SA_LIST(s) /* empty */ - -#define XCHAL_CP6_SA_NUM 0 -#define XCHAL_CP6_SA_LIST(s) /* empty */ - -#define XCHAL_CP7_SA_NUM 0 -#define XCHAL_CP7_SA_LIST(s) /* empty */ - -/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ -#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8 - -#endif /*_XTENSA_CORE_TIE_H*/ -