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xtensa: remove unused intel_bdw and intel_byt 

Both intel_bdw and intel_byt are not being used in upstream
Zephyr project. So there is no need to build them.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2022-10-25 09:42:38 -07:00 committed by Stephanos Ioannidis
parent 44f489b715
commit eb98aaa5ef
24 changed files with 2 additions and 173384 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
.github/workflows/ci.yml vendored
View File

@ -52,8 +52,6 @@ on:
- xtensa-espressif_esp32_zephyr-elf
- xtensa-espressif_esp32s2_zephyr-elf
- xtensa-intel_apl_adsp_zephyr-elf
- xtensa-intel_bdw_adsp_zephyr-elf
- xtensa-intel_byt_adsp_zephyr-elf
- xtensa-intel_s1000_zephyr-elf
- xtensa-nxp_imx_adsp_zephyr-elf
- xtensa-nxp_imx8m_adsp_zephyr-elf
@ -160,8 +158,6 @@ jobs:
xtensa-espressif_esp32_zephyr-elf) build_target_xtensa_espressif_esp32_zephyr_elf="y";;
xtensa-espressif_esp32s2_zephyr-elf) build_target_xtensa_espressif_esp32s2_zephyr_elf="y";;
xtensa-intel_apl_adsp_zephyr-elf) build_target_xtensa_intel_apl_adsp_zephyr_elf="y";;
xtensa-intel_bdw_adsp_zephyr-elf) build_target_xtensa_intel_bdw_adsp_zephyr_elf="y";;
xtensa-intel_byt_adsp_zephyr-elf) build_target_xtensa_intel_byt_adsp_zephyr_elf="y";;
xtensa-intel_s1000_zephyr-elf) build_target_xtensa_intel_s1000_zephyr_elf="y";;
xtensa-nxp_imx_adsp_zephyr-elf) build_target_xtensa_nxp_imx_adsp_zephyr_elf="y";;
xtensa-nxp_imx8m_adsp_zephyr-elf) build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y";;
@ -196,8 +192,6 @@ jobs:
build_target_xtensa_espressif_esp32_zephyr_elf="y"
build_target_xtensa_espressif_esp32s2_zephyr_elf="y"
build_target_xtensa_intel_apl_adsp_zephyr_elf="y"
build_target_xtensa_intel_bdw_adsp_zephyr_elf="y"
build_target_xtensa_intel_byt_adsp_zephyr_elf="y"
build_target_xtensa_intel_s1000_zephyr_elf="y"
build_target_xtensa_nxp_imx_adsp_zephyr_elf="y"
build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y"
@ -272,8 +266,6 @@ jobs:
[ "${build_target_xtensa_espressif_esp32_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-espressif_esp32_zephyr-elf",'
[ "${build_target_xtensa_espressif_esp32s2_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-espressif_esp32s2_zephyr-elf",'
[ "${build_target_xtensa_intel_apl_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-intel_apl_adsp_zephyr-elf",'
[ "${build_target_xtensa_intel_bdw_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-intel_bdw_adsp_zephyr-elf",'
[ "${build_target_xtensa_intel_byt_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-intel_byt_adsp_zephyr-elf",'
[ "${build_target_xtensa_intel_s1000_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-intel_s1000_zephyr-elf",'
[ "${build_target_xtensa_nxp_imx_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx_adsp_zephyr-elf",'
[ "${build_target_xtensa_nxp_imx8m_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx8m_adsp_zephyr-elf",'
@ -1521,12 +1513,6 @@ jobs:
xtensa-intel_apl_adsp_zephyr-elf)
PLATFORM_ARGS+="-p intel_adsp_cavs15 "
;;
xtensa-intel_bdw_adsp_zephyr-elf)
# NOTE: no default user for this target is available
;;
xtensa-intel_byt_adsp_zephyr-elf)
# NOTE: no default user for this target is available
;;
xtensa-intel_s1000_zephyr-elf)
PLATFORM_ARGS+="-p intel_adsp_cavs18 "
;;

4
README.md
View File

@ -12,8 +12,8 @@ The toolchains for the following target architectures are supported:
- Nios II
- RISC-V (32-bit and 64-bit; RV32I, RV32E, RV64I)
- x86 (32-bit and 64-bit)
- Xtensa (sample_controller, intel_apl_adsp, intel_bdw_adsp, intel_byt_adsp,
intel_s1000, nxp_imx_adsp, nxp_imx8m_adsp, espressif_esp32, espressif_esp32s2)
- Xtensa (sample_controller, intel_apl_adsp, intel_s1000,
nxp_imx_adsp, nxp_imx8m_adsp, espressif_esp32, espressif_esp32s2)
The following host tools are available as part of the Zephyr SDK:

71
configs/xtensa-intel_bdw_adsp_zephyr-elf.config
View File

@ -1,71 +0,0 @@
CT_CONFIG_VERSION="3"
CT_EXPERIMENTAL=y
# CT_PREFIX_DIR_RO is not set
# CT_LOG_PROGRESS_BAR is not set
CT_ARCH_XTENSA=y
CT_XTENSA_CUSTOM=y
# CT_ARCH_USE_MMU is not set
CT_OVERLAY_NAME="intel_bdw_adsp"
CT_OVERLAY_LOCATION="./overlays"
CT_TARGET_VENDOR="intel_bdw_adsp_zephyr"
CT_TARGET_CFLAGS="-ftls-model=local-exec"
CT_BINUTILS_SRC_CUSTOM=y
CT_BINUTILS_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/binutils"
CT_NEWLIB_SRC_CUSTOM=y
CT_NEWLIB_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/newlib"
CT_LIBC_NEWLIB_TARGET_CFLAGS="-O2"
# CT_LIBC_NEWLIB_ENABLE_TARGET_OPTSPACE is not set
CT_LIBC_NEWLIB_IO_C99FMT=y
CT_LIBC_NEWLIB_IO_LL=y
CT_LIBC_NEWLIB_IO_FLOAT=y
# CT_LIBC_NEWLIB_FSEEK_OPTIMIZATION is not set
CT_LIBC_NEWLIB_DISABLE_SUPPLIED_SYSCALLS=y
CT_LIBC_NEWLIB_GLOBAL_ATEXIT=y
CT_LIBC_NEWLIB_LITE_EXIT=y
CT_LIBC_NEWLIB_MULTITHREAD=y
CT_LIBC_NEWLIB_RETARGETABLE_LOCKING=y
# CT_LIBC_NEWLIB_WIDE_ORIENT is not set
# CT_LIBC_NEWLIB_NANO_MALLOC is not set
# CT_LIBC_NEWLIB_NANO_FORMATTED_IO is not set
CT_LIBC_NEWLIB_EXTRA_SECTIONS=y
CT_GCC_SRC_CUSTOM=y
CT_GCC_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/gcc"
CT_CC_GCC_EXTRA_CONFIG_ARRAY="--with-gnu-ld --with-gnu-as --enable-initfini-array"
CT_CC_GCC_CONFIG_TLS=n
CT_CC_LANG_CXX=y
CT_DEBUG_GDB=y
CT_GDB_SRC_CUSTOM=y
CT_GDB_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/gdb"
CT_COMP_LIBS_NEWLIB_NANO=y
CT_NEWLIB_NANO_SRC_CUSTOM=y
CT_NEWLIB_NANO_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/newlib"
CT_NEWLIB_NANO_GCC_LIBSTDCXX=y
CT_NEWLIB_NANO_INSTALL_IN_TARGET=y
# CT_LIBC_NEWLIB_NANO_IO_C99FMT is not set
# CT_LIBC_NEWLIB_NANO_IO_LL is not set
CT_LIBC_NEWLIB_NANO_IO_FLOAT=y
# CT_LIBC_NEWLIB_NANO_IO_LDBL is not set
# CT_LIBC_NEWLIB_NANO_IO_POS_ARGS is not set
CT_LIBC_NEWLIB_NANO_FVWRITE_IN_STREAMIO=y
# CT_LIBC_NEWLIB_NANO_UNBUF_STREAM_OPT is not set
# CT_LIBC_NEWLIB_NANO_FSEEK_OPTIMIZATION is not set
CT_LIBC_NEWLIB_NANO_DISABLE_SUPPLIED_SYSCALLS=y
# CT_LIBC_NEWLIB_NANO_REGISTER_FINI is not set
CT_LIBC_NEWLIB_NANO_ATEXIT_DYNAMIC_ALLOC=y
CT_LIBC_NEWLIB_NANO_GLOBAL_ATEXIT=y
CT_LIBC_NEWLIB_NANO_LITE_EXIT=y
CT_LIBC_NEWLIB_NANO_REENT_SMALL=y
CT_LIBC_NEWLIB_NANO_MULTITHREAD=y
CT_LIBC_NEWLIB_NANO_RETARGETABLE_LOCKING=y
CT_LIBC_NEWLIB_NANO_EXTRA_SECTIONS=y
# CT_LIBC_NEWLIB_NANO_WIDE_ORIENT is not set
CT_LIBC_NEWLIB_NANO_ENABLE_TARGET_OPTSPACE=y
# CT_LIBC_NEWLIB_NANO_LTO is not set
CT_LIBC_NEWLIB_NANO_NANO_MALLOC=y
CT_LIBC_NEWLIB_NANO_NANO_FORMATTED_IO=y
CT_COMP_LIBS_PICOLIBC=y
CT_PICOLIBC_SRC_CUSTOM=y
CT_PICOLIBC_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/picolibc"
CT_LIBC_PICOLIBC_GLOBAL_ATEXIT=y
CT_LIBC_PICOLIBC_EXTRA_SECTIONS=y
CT_LIBC_PICOLIBC_EXTRA_CONFIG_ARRAY="-Dthread-local-storage=auto -Derrno-function=zephyr -Dsysroot-install=true -Dsysroot-install-skip-checks=true"

71
configs/xtensa-intel_byt_adsp_zephyr-elf.config
View File

@ -1,71 +0,0 @@
CT_CONFIG_VERSION="3"
CT_EXPERIMENTAL=y
# CT_PREFIX_DIR_RO is not set
# CT_LOG_PROGRESS_BAR is not set
CT_ARCH_XTENSA=y
CT_XTENSA_CUSTOM=y
# CT_ARCH_USE_MMU is not set
CT_OVERLAY_NAME="intel_byt_adsp"
CT_OVERLAY_LOCATION="./overlays"
CT_TARGET_VENDOR="intel_byt_adsp_zephyr"
CT_TARGET_CFLAGS="-ftls-model=local-exec"
CT_BINUTILS_SRC_CUSTOM=y
CT_BINUTILS_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/binutils"
CT_NEWLIB_SRC_CUSTOM=y
CT_NEWLIB_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/newlib"
CT_LIBC_NEWLIB_TARGET_CFLAGS="-O2"
# CT_LIBC_NEWLIB_ENABLE_TARGET_OPTSPACE is not set
CT_LIBC_NEWLIB_IO_C99FMT=y
CT_LIBC_NEWLIB_IO_LL=y
CT_LIBC_NEWLIB_IO_FLOAT=y
# CT_LIBC_NEWLIB_FSEEK_OPTIMIZATION is not set
CT_LIBC_NEWLIB_DISABLE_SUPPLIED_SYSCALLS=y
CT_LIBC_NEWLIB_GLOBAL_ATEXIT=y
CT_LIBC_NEWLIB_LITE_EXIT=y
CT_LIBC_NEWLIB_MULTITHREAD=y
CT_LIBC_NEWLIB_RETARGETABLE_LOCKING=y
# CT_LIBC_NEWLIB_WIDE_ORIENT is not set
# CT_LIBC_NEWLIB_NANO_MALLOC is not set
# CT_LIBC_NEWLIB_NANO_FORMATTED_IO is not set
CT_LIBC_NEWLIB_EXTRA_SECTIONS=y
CT_GCC_SRC_CUSTOM=y
CT_GCC_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/gcc"
CT_CC_GCC_EXTRA_CONFIG_ARRAY="--with-gnu-ld --with-gnu-as --enable-initfini-array"
CT_CC_GCC_CONFIG_TLS=n
CT_CC_LANG_CXX=y
CT_DEBUG_GDB=y
CT_GDB_SRC_CUSTOM=y
CT_GDB_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/gdb"
CT_COMP_LIBS_NEWLIB_NANO=y
CT_NEWLIB_NANO_SRC_CUSTOM=y
CT_NEWLIB_NANO_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/newlib"
CT_NEWLIB_NANO_GCC_LIBSTDCXX=y
CT_NEWLIB_NANO_INSTALL_IN_TARGET=y
# CT_LIBC_NEWLIB_NANO_IO_C99FMT is not set
# CT_LIBC_NEWLIB_NANO_IO_LL is not set
CT_LIBC_NEWLIB_NANO_IO_FLOAT=y
# CT_LIBC_NEWLIB_NANO_IO_LDBL is not set
# CT_LIBC_NEWLIB_NANO_IO_POS_ARGS is not set
CT_LIBC_NEWLIB_NANO_FVWRITE_IN_STREAMIO=y
# CT_LIBC_NEWLIB_NANO_UNBUF_STREAM_OPT is not set
# CT_LIBC_NEWLIB_NANO_FSEEK_OPTIMIZATION is not set
CT_LIBC_NEWLIB_NANO_DISABLE_SUPPLIED_SYSCALLS=y
# CT_LIBC_NEWLIB_NANO_REGISTER_FINI is not set
CT_LIBC_NEWLIB_NANO_ATEXIT_DYNAMIC_ALLOC=y
CT_LIBC_NEWLIB_NANO_GLOBAL_ATEXIT=y
CT_LIBC_NEWLIB_NANO_LITE_EXIT=y
CT_LIBC_NEWLIB_NANO_REENT_SMALL=y
CT_LIBC_NEWLIB_NANO_MULTITHREAD=y
CT_LIBC_NEWLIB_NANO_RETARGETABLE_LOCKING=y
CT_LIBC_NEWLIB_NANO_EXTRA_SECTIONS=y
# CT_LIBC_NEWLIB_NANO_WIDE_ORIENT is not set
CT_LIBC_NEWLIB_NANO_ENABLE_TARGET_OPTSPACE=y
# CT_LIBC_NEWLIB_NANO_LTO is not set
CT_LIBC_NEWLIB_NANO_NANO_MALLOC=y
CT_LIBC_NEWLIB_NANO_NANO_FORMATTED_IO=y
CT_COMP_LIBS_PICOLIBC=y
CT_PICOLIBC_SRC_CUSTOM=y
CT_PICOLIBC_CUSTOM_LOCATION="${GITHUB_WORKSPACE}/picolibc"
CT_LIBC_PICOLIBC_GLOBAL_ATEXIT=y
CT_LIBC_PICOLIBC_EXTRA_SECTIONS=y
CT_LIBC_PICOLIBC_EXTRA_CONFIG_ARRAY="-Dthread-local-storage=auto -Derrno-function=zephyr -Dsysroot-install=true -Dsysroot-install-skip-checks=true"

42144
overlays/xtensa_intel_bdw_adsp/binutils/bfd/xtensa-modules.c
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File diff suppressed because it is too large Load Diff

177
overlays/xtensa_intel_bdw_adsp/binutils/include/xtensa-config.h
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@ -1,177 +0,0 @@
/* Xtensa configuration settings.
Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
Free Software Foundation, Inc.
Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef XTENSA_CONFIG_H
#define XTENSA_CONFIG_H
/* The macros defined here match those with the same names in the Xtensa
compile-time HAL (Hardware Abstraction Layer). Please refer to the
Xtensa System Software Reference Manual for documentation of these
macros. */
#undef XCHAL_HAVE_BE
#define XCHAL_HAVE_BE 0
#undef XCHAL_HAVE_DENSITY
#define XCHAL_HAVE_DENSITY 1
#undef XCHAL_HAVE_CONST16
#define XCHAL_HAVE_CONST16 0
#undef XCHAL_HAVE_ABS
#define XCHAL_HAVE_ABS 1
#undef XCHAL_HAVE_ADDX
#define XCHAL_HAVE_ADDX 1
#undef XCHAL_HAVE_L32R
#define XCHAL_HAVE_L32R 1
#undef XSHAL_USE_ABSOLUTE_LITERALS
#define XSHAL_USE_ABSOLUTE_LITERALS 0
#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
#undef XCHAL_HAVE_MAC16
#define XCHAL_HAVE_MAC16 0
#undef XCHAL_HAVE_MUL16
#define XCHAL_HAVE_MUL16 1
#undef XCHAL_HAVE_MUL32
#define XCHAL_HAVE_MUL32 0
#undef XCHAL_HAVE_MUL32_HIGH
#define XCHAL_HAVE_MUL32_HIGH 0
#undef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 0
#undef XCHAL_HAVE_NSA
#define XCHAL_HAVE_NSA 1
#undef XCHAL_HAVE_MINMAX
#define XCHAL_HAVE_MINMAX 1
#undef XCHAL_HAVE_SEXT
#define XCHAL_HAVE_SEXT 1
#undef XCHAL_HAVE_LOOPS
#define XCHAL_HAVE_LOOPS 1
#undef XCHAL_HAVE_THREADPTR
#define XCHAL_HAVE_THREADPTR 1
#undef XCHAL_HAVE_RELEASE_SYNC
#define XCHAL_HAVE_RELEASE_SYNC 1
#undef XCHAL_HAVE_S32C1I
#define XCHAL_HAVE_S32C1I 1
#undef XCHAL_HAVE_BOOLEANS
#define XCHAL_HAVE_BOOLEANS 1
#undef XCHAL_HAVE_FP
#define XCHAL_HAVE_FP 0
#undef XCHAL_HAVE_FP_DIV
#define XCHAL_HAVE_FP_DIV 0
#undef XCHAL_HAVE_FP_RECIP
#define XCHAL_HAVE_FP_RECIP 0
#undef XCHAL_HAVE_FP_SQRT
#define XCHAL_HAVE_FP_SQRT 0
#undef XCHAL_HAVE_FP_RSQRT
#define XCHAL_HAVE_FP_RSQRT 0
#undef XCHAL_HAVE_DFP_accel
#define XCHAL_HAVE_DFP_accel 0
#undef XCHAL_HAVE_WINDOWED
#define XCHAL_HAVE_WINDOWED 1
#undef XCHAL_NUM_AREGS
#define XCHAL_NUM_AREGS 32
#undef XCHAL_HAVE_WIDE_BRANCHES
#define XCHAL_HAVE_WIDE_BRANCHES 0
#undef XCHAL_HAVE_PREDICTED_BRANCHES
#define XCHAL_HAVE_PREDICTED_BRANCHES 0
#undef XCHAL_ICACHE_SIZE
#define XCHAL_ICACHE_SIZE 0
#undef XCHAL_DCACHE_SIZE
#define XCHAL_DCACHE_SIZE 0
#undef XCHAL_ICACHE_LINESIZE
#define XCHAL_ICACHE_LINESIZE 128
#undef XCHAL_DCACHE_LINESIZE
#define XCHAL_DCACHE_LINESIZE 128
#undef XCHAL_ICACHE_LINEWIDTH
#define XCHAL_ICACHE_LINEWIDTH 7
#undef XCHAL_DCACHE_LINEWIDTH
#define XCHAL_DCACHE_LINEWIDTH 7
#undef XCHAL_DCACHE_IS_WRITEBACK
#define XCHAL_DCACHE_IS_WRITEBACK 0
#undef XCHAL_HAVE_MMU
#define XCHAL_HAVE_MMU 1
#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
#undef XCHAL_HAVE_DEBUG
#define XCHAL_HAVE_DEBUG 1
#undef XCHAL_NUM_IBREAK
#define XCHAL_NUM_IBREAK 2
#undef XCHAL_NUM_DBREAK
#define XCHAL_NUM_DBREAK 2
#undef XCHAL_DEBUGLEVEL
#define XCHAL_DEBUGLEVEL 6
#undef XCHAL_MAX_INSTRUCTION_SIZE
#define XCHAL_MAX_INSTRUCTION_SIZE 8
#undef XCHAL_INST_FETCH_WIDTH
#define XCHAL_INST_FETCH_WIDTH 4
#undef XSHAL_ABI
#undef XTHAL_ABI_WINDOWED
#undef XTHAL_ABI_CALL0
#define XSHAL_ABI XTHAL_ABI_WINDOWED
#define XTHAL_ABI_WINDOWED 0
#define XTHAL_ABI_CALL0 1
#endif /* !XTENSA_CONFIG_H */

177
overlays/xtensa_intel_bdw_adsp/gcc/include/xtensa-config.h
View File

@ -1,177 +0,0 @@
/* Xtensa configuration settings.
Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
Free Software Foundation, Inc.
Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef XTENSA_CONFIG_H
#define XTENSA_CONFIG_H
/* The macros defined here match those with the same names in the Xtensa
compile-time HAL (Hardware Abstraction Layer). Please refer to the
Xtensa System Software Reference Manual for documentation of these
macros. */
#undef XCHAL_HAVE_BE
#define XCHAL_HAVE_BE 0
#undef XCHAL_HAVE_DENSITY
#define XCHAL_HAVE_DENSITY 1
#undef XCHAL_HAVE_CONST16
#define XCHAL_HAVE_CONST16 0
#undef XCHAL_HAVE_ABS
#define XCHAL_HAVE_ABS 1
#undef XCHAL_HAVE_ADDX
#define XCHAL_HAVE_ADDX 1
#undef XCHAL_HAVE_L32R
#define XCHAL_HAVE_L32R 1
#undef XSHAL_USE_ABSOLUTE_LITERALS
#define XSHAL_USE_ABSOLUTE_LITERALS 0
#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
#undef XCHAL_HAVE_MAC16
#define XCHAL_HAVE_MAC16 0
#undef XCHAL_HAVE_MUL16
#define XCHAL_HAVE_MUL16 1
#undef XCHAL_HAVE_MUL32
#define XCHAL_HAVE_MUL32 0
#undef XCHAL_HAVE_MUL32_HIGH
#define XCHAL_HAVE_MUL32_HIGH 0
#undef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 0
#undef XCHAL_HAVE_NSA
#define XCHAL_HAVE_NSA 1
#undef XCHAL_HAVE_MINMAX
#define XCHAL_HAVE_MINMAX 1
#undef XCHAL_HAVE_SEXT
#define XCHAL_HAVE_SEXT 1
#undef XCHAL_HAVE_LOOPS
#define XCHAL_HAVE_LOOPS 1
#undef XCHAL_HAVE_THREADPTR
#define XCHAL_HAVE_THREADPTR 1
#undef XCHAL_HAVE_RELEASE_SYNC
#define XCHAL_HAVE_RELEASE_SYNC 1
#undef XCHAL_HAVE_S32C1I
#define XCHAL_HAVE_S32C1I 1
#undef XCHAL_HAVE_BOOLEANS
#define XCHAL_HAVE_BOOLEANS 1
#undef XCHAL_HAVE_FP
#define XCHAL_HAVE_FP 0
#undef XCHAL_HAVE_FP_DIV
#define XCHAL_HAVE_FP_DIV 0
#undef XCHAL_HAVE_FP_RECIP
#define XCHAL_HAVE_FP_RECIP 0
#undef XCHAL_HAVE_FP_SQRT
#define XCHAL_HAVE_FP_SQRT 0
#undef XCHAL_HAVE_FP_RSQRT
#define XCHAL_HAVE_FP_RSQRT 0
#undef XCHAL_HAVE_DFP_accel
#define XCHAL_HAVE_DFP_accel 0
#undef XCHAL_HAVE_WINDOWED
#define XCHAL_HAVE_WINDOWED 1
#undef XCHAL_NUM_AREGS
#define XCHAL_NUM_AREGS 32
#undef XCHAL_HAVE_WIDE_BRANCHES
#define XCHAL_HAVE_WIDE_BRANCHES 0
#undef XCHAL_HAVE_PREDICTED_BRANCHES
#define XCHAL_HAVE_PREDICTED_BRANCHES 0
#undef XCHAL_ICACHE_SIZE
#define XCHAL_ICACHE_SIZE 0
#undef XCHAL_DCACHE_SIZE
#define XCHAL_DCACHE_SIZE 0
#undef XCHAL_ICACHE_LINESIZE
#define XCHAL_ICACHE_LINESIZE 128
#undef XCHAL_DCACHE_LINESIZE
#define XCHAL_DCACHE_LINESIZE 128
#undef XCHAL_ICACHE_LINEWIDTH
#define XCHAL_ICACHE_LINEWIDTH 7
#undef XCHAL_DCACHE_LINEWIDTH
#define XCHAL_DCACHE_LINEWIDTH 7
#undef XCHAL_DCACHE_IS_WRITEBACK
#define XCHAL_DCACHE_IS_WRITEBACK 0
#undef XCHAL_HAVE_MMU
#define XCHAL_HAVE_MMU 1
#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
#undef XCHAL_HAVE_DEBUG
#define XCHAL_HAVE_DEBUG 1
#undef XCHAL_NUM_IBREAK
#define XCHAL_NUM_IBREAK 2
#undef XCHAL_NUM_DBREAK
#define XCHAL_NUM_DBREAK 2
#undef XCHAL_DEBUGLEVEL
#define XCHAL_DEBUGLEVEL 6
#undef XCHAL_MAX_INSTRUCTION_SIZE
#define XCHAL_MAX_INSTRUCTION_SIZE 8
#undef XCHAL_INST_FETCH_WIDTH
#define XCHAL_INST_FETCH_WIDTH 4
#undef XSHAL_ABI
#undef XTHAL_ABI_WINDOWED
#undef XTHAL_ABI_CALL0
#define XSHAL_ABI XTHAL_ABI_WINDOWED
#define XTHAL_ABI_WINDOWED 0
#define XTHAL_ABI_CALL0 1
#endif /* !XTENSA_CONFIG_H */

42144
overlays/xtensa_intel_bdw_adsp/gdb/bfd/xtensa-modules.c
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File diff suppressed because it is too large Load Diff

66
overlays/xtensa_intel_bdw_adsp/gdb/gdb/regformats/reg-xtensa.dat
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@ -1,66 +0,0 @@
name:xtensa
expedite:pc,windowbase,windowstart
32:pc
32:ar0
32:ar1
32:ar2
32:ar3
32:ar4
32:ar5
32:ar6
32:ar7
32:ar8
32:ar9
32:ar10
32:ar11
32:ar12
32:ar13
32:ar14
32:ar15
32:ar16
32:ar17
32:ar18
32:ar19
32:ar20
32:ar21
32:ar22
32:ar23
32:ar24
32:ar25
32:ar26
32:ar27
32:ar28
32:ar29
32:ar30
32:ar31
32:lbeg
32:lend
32:lcount
32:sar
32:prefctl
32:windowbase
32:windowstart
32:configid0
32:configid1
32:ps
32:br
32:scompare1
32:expstate
64:aep0
64:aep1
64:aep2
64:aep3
64:aep4
64:aep5
64:aep6
64:aep7
64:aeq0
64:aeq1
64:aeq2
64:aeq3
32:ae_ovf_sar
32:ae_bithead
32:ae_ts_fts_bu_bp
32:ae_sd_no
32:ae_cbegin0
32:ae_cend0

305
overlays/xtensa_intel_bdw_adsp/gdb/gdb/xtensa-config.c
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@ -1,305 +0,0 @@
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
Customer ID=4313; Build=0x5483e; Copyright (c) 2003-2015 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#define XTENSA_CONFIG_VERSION 0x60
#include "defs.h"
#include "xtensa-config.h"
#include "xtensa-tdep.h"
/* Masked registers. */
xtensa_reg_mask_t xtensa_submask0[] = { { 43, 0, 1 } };
const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
xtensa_reg_mask_t xtensa_submask1[] = { { 43, 1, 1 } };
const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
xtensa_reg_mask_t xtensa_submask2[] = { { 43, 2, 1 } };
const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
xtensa_reg_mask_t xtensa_submask3[] = { { 43, 3, 1 } };
const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
xtensa_reg_mask_t xtensa_submask4[] = { { 43, 4, 1 } };
const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
xtensa_reg_mask_t xtensa_submask5[] = { { 43, 5, 1 } };
const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
xtensa_reg_mask_t xtensa_submask6[] = { { 43, 6, 1 } };
const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
xtensa_reg_mask_t xtensa_submask7[] = { { 43, 7, 1 } };
const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };
xtensa_reg_mask_t xtensa_submask8[] = { { 43, 8, 1 } };
const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };
xtensa_reg_mask_t xtensa_submask9[] = { { 43, 9, 1 } };
const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };
xtensa_reg_mask_t xtensa_submask10[] = { { 43, 10, 1 } };
const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };
xtensa_reg_mask_t xtensa_submask11[] = { { 43, 11, 1 } };
const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };
xtensa_reg_mask_t xtensa_submask12[] = { { 43, 12, 1 } };
const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };
xtensa_reg_mask_t xtensa_submask13[] = { { 43, 13, 1 } };
const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };
xtensa_reg_mask_t xtensa_submask14[] = { { 43, 14, 1 } };
const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };
xtensa_reg_mask_t xtensa_submask15[] = { { 43, 15, 1 } };
const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };
xtensa_reg_mask_t xtensa_submask16[] = { { 42, 0, 4 } };
const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 };
xtensa_reg_mask_t xtensa_submask17[] = { { 42, 5, 1 } };
const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 };
xtensa_reg_mask_t xtensa_submask18[] = { { 42, 18, 1 } };
const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 };
xtensa_reg_mask_t xtensa_submask19[] = { { 42, 4, 1 } };
const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 };
xtensa_reg_mask_t xtensa_submask20[] = { { 42, 16, 2 } };
const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 };
xtensa_reg_mask_t xtensa_submask21[] = { { 42, 8, 4 } };
const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 };
xtensa_reg_mask_t xtensa_submask22[] = { { 102, 8, 4 } };
const xtensa_mask_t xtensa_mask22 = { 1, xtensa_submask22 };
xtensa_reg_mask_t xtensa_submask23[] = { { 58, 6, 1 } };
const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 };
xtensa_reg_mask_t xtensa_submask24[] = { { 58, 0, 6 } };
const xtensa_mask_t xtensa_mask24 = { 1, xtensa_submask24 };
xtensa_reg_mask_t xtensa_submask25[] = { { 60, 0, 4 } };
const xtensa_mask_t xtensa_mask25 = { 1, xtensa_submask25 };
xtensa_reg_mask_t xtensa_submask26[] = { { 60, 4, 4 } };
const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 };
xtensa_reg_mask_t xtensa_submask27[] = { { 60, 12, 4 } };
const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 };
xtensa_reg_mask_t xtensa_submask28[] = { { 60, 8, 4 } };
const xtensa_mask_t xtensa_mask28 = { 1, xtensa_submask28 };
xtensa_reg_mask_t xtensa_submask29[] = { { 61, 0, 27 } };
const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 };
xtensa_reg_mask_t xtensa_submask30[] = { { 61, 27, 1 } };
const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 };
/* Register map. */
static xtensa_register_t rmap[] =
{
/* idx ofs bi sz al targno flags cp typ group name */
XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
XTREG( 37,148,13, 4, 4,0x0228,0x0006,-2, 2,0x1100,prefctl, 0,0,0,0,0,0)
XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
XTREG( 43,172,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
XTREG( 44,176,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
XTREG( 45,180,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0)
XTREG( 46,184,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0,
"03:04:84:b2","03:04:84:a7",0,0,0,0)
XTREG( 47,192,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1,
"03:04:94:b2","03:04:94:a7",0,0,0,0)
XTREG( 48,200,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2,
"03:04:a4:b2","03:04:a4:a7",0,0,0,0)
XTREG( 49,208,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3,
"03:04:b4:b2","03:04:b4:a7",0,0,0,0)
XTREG( 50,216,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4,
"03:04:c4:b2","03:04:c4:a7",0,0,0,0)
XTREG( 51,224,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5,
"03:04:d4:b2","03:04:d4:a7",0,0,0,0)
XTREG( 52,232,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6,
"03:04:e4:b2","03:04:e4:a7",0,0,0,0)
XTREG( 53,240,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7,
"03:04:f4:b2","03:04:f4:a7",0,0,0,0)
XTREG( 54,248,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0,
"03:04:04:c3","03:04:04:c1",0,0,0,0)
XTREG( 55,256,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1,
"03:04:14:c3","03:04:44:c1",0,0,0,0)
XTREG( 56,264,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2,
"03:04:24:c3","03:04:84:c1",0,0,0,0)
XTREG( 57,272,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3,
"03:04:34:c3","03:04:c4:c1",0,0,0,0)
XTREG( 58,280, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0)
XTREG( 59,284,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0)
XTREG( 60,288,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0)
XTREG( 61,292,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no, 0,0,0,0,0,0)
XTREG( 62,296,32, 4, 4,0x03f6,0x0006, 1, 3,0x0110,ae_cbegin0, 0,0,0,0,0,0)
XTREG( 63,300,32, 4, 4,0x03f7,0x0006, 1, 3,0x0110,ae_cend0, 0,0,0,0,0,0)
XTREG( 64,304,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
XTREG( 65,308, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
XTREG( 66,312, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
XTREG( 67,316,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
XTREG( 68,320,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
XTREG( 69,324,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
XTREG( 70,328,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
XTREG( 71,332,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
XTREG( 72,336,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
XTREG( 73,340,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
XTREG( 74,344,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
XTREG( 75,348,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
XTREG( 76,352,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
XTREG( 77,356,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
XTREG( 78,360,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
XTREG( 79,364,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
XTREG( 80,368,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
XTREG( 81,372,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
XTREG( 82,376,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
XTREG( 83,380,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
XTREG( 84,384,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
XTREG( 85,388,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
XTREG( 86,392,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
XTREG( 87,396,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
XTREG( 88,400,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
XTREG( 89,404,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
XTREG( 90,408,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
XTREG( 91,412,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
XTREG( 92,416,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
XTREG( 93,420,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
XTREG( 94,424,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
XTREG( 95,428, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
XTREG( 96,432,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
XTREG( 97,436,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
XTREG( 98,440,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
XTREG( 99,444,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
XTREG(100,448,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
XTREG(101,452, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
XTREG(102,456,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
XTREG(103,460,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
XTREG(104,464,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
XTREG(105,468,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
XTREG(106,472, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
XTREG(107,476,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
XTREG(108,480,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
XTREG(109,484,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
XTREG(110,488,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
XTREG(111,492,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
XTREG(112,496,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
XTREG(113,500,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
XTREG(114,504,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
XTREG(115,508,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
XTREG(116,512,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
XTREG(117,516,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
XTREG(118,520,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
XTREG(119,524,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
XTREG(120,528,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
XTREG(121,532,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
XTREG(122,536,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
XTREG(123,540,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
XTREG(124,544,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
XTREG(125,548,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
XTREG(126,552,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
XTREG(127,556,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
XTREG(128,560,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
XTREG(129,564, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
0,0,&xtensa_mask0,0,0,0)
XTREG(130,565, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
0,0,&xtensa_mask1,0,0,0)
XTREG(131,566, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
0,0,&xtensa_mask2,0,0,0)
XTREG(132,567, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
0,0,&xtensa_mask3,0,0,0)
XTREG(133,568, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
0,0,&xtensa_mask4,0,0,0)
XTREG(134,569, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
0,0,&xtensa_mask5,0,0,0)
XTREG(135,570, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
0,0,&xtensa_mask6,0,0,0)
XTREG(136,571, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
0,0,&xtensa_mask7,0,0,0)
XTREG(137,572, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
0,0,&xtensa_mask8,0,0,0)
XTREG(138,573, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
0,0,&xtensa_mask9,0,0,0)
XTREG(139,574, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
0,0,&xtensa_mask10,0,0,0)
XTREG(140,575, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
0,0,&xtensa_mask11,0,0,0)
XTREG(141,576, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
0,0,&xtensa_mask12,0,0,0)
XTREG(142,577, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
0,0,&xtensa_mask13,0,0,0)
XTREG(143,578, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
0,0,&xtensa_mask14,0,0,0)
XTREG(144,579, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
0,0,&xtensa_mask15,0,0,0)
XTREG(145,580, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
0,0,&xtensa_mask16,0,0,0)
XTREG(146,584, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
0,0,&xtensa_mask17,0,0,0)
XTREG(147,588, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
0,0,&xtensa_mask18,0,0,0)
XTREG(148,592, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
0,0,&xtensa_mask19,0,0,0)
XTREG(149,596, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
0,0,&xtensa_mask20,0,0,0)
XTREG(150,600, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
0,0,&xtensa_mask21,0,0,0)
XTREG(151,604, 4, 4, 4,0x2012,0x0006,-2, 6,0x1010,dbnum,
0,0,&xtensa_mask22,0,0,0)
XTREG(152,608, 1, 4, 4,0x2014,0x0006, 1, 5,0x1010,ae_overflow,
0,0,&xtensa_mask23,0,0,0)
XTREG(153,612, 6, 4, 4,0x2015,0x0006, 1, 5,0x1010,ae_sar,
0,0,&xtensa_mask24,0,0,0)
XTREG(154,616, 4, 4, 4,0x2016,0x0006, 1, 5,0x1010,ae_bitptr,
0,0,&xtensa_mask25,0,0,0)
XTREG(155,620, 4, 4, 4,0x2017,0x0006, 1, 5,0x1010,ae_bitsused,
0,0,&xtensa_mask26,0,0,0)
XTREG(156,624, 4, 4, 4,0x2018,0x0006, 1, 5,0x1010,ae_tablesize,
0,0,&xtensa_mask27,0,0,0)
XTREG(157,628, 4, 4, 4,0x2019,0x0006, 1, 5,0x1010,ae_first_ts,
0,0,&xtensa_mask28,0,0,0)
XTREG(158,632,27, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_nextoffset,
0,0,&xtensa_mask29,0,0,0)
XTREG_END
};
xtensa_gdbarch_tdep xtensa_tdep (rmap);

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overlays/xtensa_intel_bdw_adsp/gdb/gdbserver/xtensa-xtregs.cc
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/* Customized table mapping between kernel xtregset and GDB register cache.
Customer ID=4313; Build=0x5483e; Copyright (c) 2007-2010 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
typedef struct {
int gdb_regnum;
int gdb_offset;
int ptrace_cp_offset;
int ptrace_offset;
int size;
int coproc;
int dbnum;
char* name
;} xtensa_regtable_t;
#define XTENSA_ELF_XTREG_SIZE 128
const xtensa_regtable_t xtensa_regmap_table[] = {
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
{ 43, 172, 0, 0, 4, -1, 0x0204, "br" },
{ 44, 176, 4, 4, 4, -1, 0x020c, "scompare1" },
{ 46, 184, 24, 32, 8, 1, 0x0060, "aep0" },
{ 47, 192, 32, 40, 8, 1, 0x0061, "aep1" },
{ 48, 200, 40, 48, 8, 1, 0x0062, "aep2" },
{ 49, 208, 48, 56, 8, 1, 0x0063, "aep3" },
{ 50, 216, 56, 64, 8, 1, 0x0064, "aep4" },
{ 51, 224, 64, 72, 8, 1, 0x0065, "aep5" },
{ 52, 232, 72, 80, 8, 1, 0x0066, "aep6" },
{ 53, 240, 80, 88, 8, 1, 0x0067, "aep7" },
{ 54, 248, 88, 96, 8, 1, 0x0068, "aeq0" },
{ 55, 256, 96, 104, 8, 1, 0x0069, "aeq1" },
{ 56, 264, 104, 112, 8, 1, 0x006a, "aeq2" },
{ 57, 272, 112, 120, 8, 1, 0x006b, "aeq3" },
{ 58, 280, 0, 8, 4, 1, 0x03f0, "ae_ovf_sar" },
{ 59, 284, 4, 12, 4, 1, 0x03f1, "ae_bithead" },
{ 60, 288, 8, 16, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" },
{ 61, 292, 12, 20, 4, 1, 0x03f3, "ae_sd_no" },
{ 62, 296, 16, 24, 4, 1, 0x03f6, "ae_cbegin0" },
{ 63, 300, 20, 28, 4, 1, 0x03f7, "ae_cend0" },
{ 0 }
};

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/* Xtensa configuration settings.
Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
Free Software Foundation, Inc.
Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef XTENSA_CONFIG_H
#define XTENSA_CONFIG_H
/* The macros defined here match those with the same names in the Xtensa
compile-time HAL (Hardware Abstraction Layer). Please refer to the
Xtensa System Software Reference Manual for documentation of these
macros. */
#undef XCHAL_HAVE_BE
#define XCHAL_HAVE_BE 0
#undef XCHAL_HAVE_DENSITY
#define XCHAL_HAVE_DENSITY 1
#undef XCHAL_HAVE_CONST16
#define XCHAL_HAVE_CONST16 0
#undef XCHAL_HAVE_ABS
#define XCHAL_HAVE_ABS 1
#undef XCHAL_HAVE_ADDX
#define XCHAL_HAVE_ADDX 1
#undef XCHAL_HAVE_L32R
#define XCHAL_HAVE_L32R 1
#undef XSHAL_USE_ABSOLUTE_LITERALS
#define XSHAL_USE_ABSOLUTE_LITERALS 0
#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
#undef XCHAL_HAVE_MAC16
#define XCHAL_HAVE_MAC16 0
#undef XCHAL_HAVE_MUL16
#define XCHAL_HAVE_MUL16 1
#undef XCHAL_HAVE_MUL32
#define XCHAL_HAVE_MUL32 0
#undef XCHAL_HAVE_MUL32_HIGH
#define XCHAL_HAVE_MUL32_HIGH 0
#undef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 0
#undef XCHAL_HAVE_NSA
#define XCHAL_HAVE_NSA 1
#undef XCHAL_HAVE_MINMAX
#define XCHAL_HAVE_MINMAX 1
#undef XCHAL_HAVE_SEXT
#define XCHAL_HAVE_SEXT 1
#undef XCHAL_HAVE_LOOPS
#define XCHAL_HAVE_LOOPS 1
#undef XCHAL_HAVE_THREADPTR
#define XCHAL_HAVE_THREADPTR 1
#undef XCHAL_HAVE_RELEASE_SYNC
#define XCHAL_HAVE_RELEASE_SYNC 1
#undef XCHAL_HAVE_S32C1I
#define XCHAL_HAVE_S32C1I 1
#undef XCHAL_HAVE_BOOLEANS
#define XCHAL_HAVE_BOOLEANS 1
#undef XCHAL_HAVE_FP
#define XCHAL_HAVE_FP 0
#undef XCHAL_HAVE_FP_DIV
#define XCHAL_HAVE_FP_DIV 0
#undef XCHAL_HAVE_FP_RECIP
#define XCHAL_HAVE_FP_RECIP 0
#undef XCHAL_HAVE_FP_SQRT
#define XCHAL_HAVE_FP_SQRT 0
#undef XCHAL_HAVE_FP_RSQRT
#define XCHAL_HAVE_FP_RSQRT 0
#undef XCHAL_HAVE_DFP_accel
#define XCHAL_HAVE_DFP_accel 0
#undef XCHAL_HAVE_WINDOWED
#define XCHAL_HAVE_WINDOWED 1
#undef XCHAL_NUM_AREGS
#define XCHAL_NUM_AREGS 32
#undef XCHAL_HAVE_WIDE_BRANCHES
#define XCHAL_HAVE_WIDE_BRANCHES 0
#undef XCHAL_HAVE_PREDICTED_BRANCHES
#define XCHAL_HAVE_PREDICTED_BRANCHES 0
#undef XCHAL_ICACHE_SIZE
#define XCHAL_ICACHE_SIZE 0
#undef XCHAL_DCACHE_SIZE
#define XCHAL_DCACHE_SIZE 0
#undef XCHAL_ICACHE_LINESIZE
#define XCHAL_ICACHE_LINESIZE 128
#undef XCHAL_DCACHE_LINESIZE
#define XCHAL_DCACHE_LINESIZE 128
#undef XCHAL_ICACHE_LINEWIDTH
#define XCHAL_ICACHE_LINEWIDTH 7
#undef XCHAL_DCACHE_LINEWIDTH
#define XCHAL_DCACHE_LINEWIDTH 7
#undef XCHAL_DCACHE_IS_WRITEBACK
#define XCHAL_DCACHE_IS_WRITEBACK 0
#undef XCHAL_HAVE_MMU
#define XCHAL_HAVE_MMU 1
#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
#undef XCHAL_HAVE_DEBUG
#define XCHAL_HAVE_DEBUG 1
#undef XCHAL_NUM_IBREAK
#define XCHAL_NUM_IBREAK 2
#undef XCHAL_NUM_DBREAK
#define XCHAL_NUM_DBREAK 2
#undef XCHAL_DEBUGLEVEL
#define XCHAL_DEBUGLEVEL 6
#undef XCHAL_MAX_INSTRUCTION_SIZE
#define XCHAL_MAX_INSTRUCTION_SIZE 8
#undef XCHAL_INST_FETCH_WIDTH
#define XCHAL_INST_FETCH_WIDTH 4
#undef XSHAL_ABI
#undef XTHAL_ABI_WINDOWED
#undef XTHAL_ABI_CALL0
#define XSHAL_ABI XTHAL_ABI_WINDOWED
#define XTHAL_ABI_WINDOWED 0
#define XTHAL_ABI_CALL0 1
#endif /* !XTENSA_CONFIG_H */

42978
overlays/xtensa_intel_byt_adsp/binutils/bfd/xtensa-modules.c
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174
overlays/xtensa_intel_byt_adsp/binutils/include/xtensa-config.h
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@ -1,174 +0,0 @@
/* Xtensa configuration settings.
Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
Free Software Foundation, Inc.
Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef XTENSA_CONFIG_H
#define XTENSA_CONFIG_H
/* The macros defined here match those with the same names in the Xtensa
compile-time HAL (Hardware Abstraction Layer). Please refer to the
Xtensa System Software Reference Manual for documentation of these
macros. */
#undef XCHAL_HAVE_BE
#define XCHAL_HAVE_BE 0
#undef XCHAL_HAVE_DENSITY
#define XCHAL_HAVE_DENSITY 1
#undef XCHAL_HAVE_CONST16
#define XCHAL_HAVE_CONST16 0
#undef XCHAL_HAVE_ABS
#define XCHAL_HAVE_ABS 1
#undef XCHAL_HAVE_ADDX
#define XCHAL_HAVE_ADDX 1
#undef XCHAL_HAVE_L32R
#define XCHAL_HAVE_L32R 1
#undef XSHAL_USE_ABSOLUTE_LITERALS
#define XSHAL_USE_ABSOLUTE_LITERALS 0
#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
#undef XCHAL_HAVE_MAC16
#define XCHAL_HAVE_MAC16 1
#undef XCHAL_HAVE_MUL16
#define XCHAL_HAVE_MUL16 1
#undef XCHAL_HAVE_MUL32
#define XCHAL_HAVE_MUL32 1
#undef XCHAL_HAVE_MUL32_HIGH
#define XCHAL_HAVE_MUL32_HIGH 1
#undef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 0
#undef XCHAL_HAVE_NSA
#define XCHAL_HAVE_NSA 1
#undef XCHAL_HAVE_MINMAX
#define XCHAL_HAVE_MINMAX 1
#undef XCHAL_HAVE_SEXT
#define XCHAL_HAVE_SEXT 1
#undef XCHAL_HAVE_LOOPS
#define XCHAL_HAVE_LOOPS 1
#undef XCHAL_HAVE_THREADPTR
#define XCHAL_HAVE_THREADPTR 1
#undef XCHAL_HAVE_RELEASE_SYNC
#define XCHAL_HAVE_RELEASE_SYNC 1
#undef XCHAL_HAVE_S32C1I
#define XCHAL_HAVE_S32C1I 1
#undef XCHAL_HAVE_BOOLEANS
#define XCHAL_HAVE_BOOLEANS 1
#undef XCHAL_HAVE_FP
#define XCHAL_HAVE_FP 0
#undef XCHAL_HAVE_FP_DIV
#define XCHAL_HAVE_FP_DIV 0
#undef XCHAL_HAVE_FP_RECIP
#define XCHAL_HAVE_FP_RECIP 0
#undef XCHAL_HAVE_FP_SQRT
#define XCHAL_HAVE_FP_SQRT 0
#undef XCHAL_HAVE_FP_RSQRT
#define XCHAL_HAVE_FP_RSQRT 0
#undef XCHAL_HAVE_DFP_accel
#define XCHAL_HAVE_DFP_accel 0
#undef XCHAL_HAVE_WINDOWED
#define XCHAL_HAVE_WINDOWED 1
#undef XCHAL_NUM_AREGS
#define XCHAL_NUM_AREGS 32
#undef XCHAL_HAVE_WIDE_BRANCHES
#define XCHAL_HAVE_WIDE_BRANCHES 0
#undef XCHAL_HAVE_PREDICTED_BRANCHES
#define XCHAL_HAVE_PREDICTED_BRANCHES 0
#undef XCHAL_ICACHE_SIZE
#define XCHAL_ICACHE_SIZE 49152
#undef XCHAL_DCACHE_SIZE
#define XCHAL_DCACHE_SIZE 98304
#undef XCHAL_ICACHE_LINESIZE
#define XCHAL_ICACHE_LINESIZE 128
#undef XCHAL_DCACHE_LINESIZE
#define XCHAL_DCACHE_LINESIZE 128
#undef XCHAL_ICACHE_LINEWIDTH
#define XCHAL_ICACHE_LINEWIDTH 7
#undef XCHAL_DCACHE_LINEWIDTH
#define XCHAL_DCACHE_LINEWIDTH 7
#undef XCHAL_DCACHE_IS_WRITEBACK
#define XCHAL_DCACHE_IS_WRITEBACK 1
#undef XCHAL_HAVE_MMU
#define XCHAL_HAVE_MMU 0
#undef XCHAL_HAVE_DEBUG
#define XCHAL_HAVE_DEBUG 1
#undef XCHAL_NUM_IBREAK
#define XCHAL_NUM_IBREAK 2
#undef XCHAL_NUM_DBREAK
#define XCHAL_NUM_DBREAK 2
#undef XCHAL_DEBUGLEVEL
#define XCHAL_DEBUGLEVEL 6
#undef XCHAL_MAX_INSTRUCTION_SIZE
#define XCHAL_MAX_INSTRUCTION_SIZE 8
#undef XCHAL_INST_FETCH_WIDTH
#define XCHAL_INST_FETCH_WIDTH 8
#undef XSHAL_ABI
#undef XTHAL_ABI_WINDOWED
#undef XTHAL_ABI_CALL0
#define XSHAL_ABI XTHAL_ABI_WINDOWED
#define XTHAL_ABI_WINDOWED 0
#define XTHAL_ABI_CALL0 1
#endif /* !XTENSA_CONFIG_H */

174
overlays/xtensa_intel_byt_adsp/gcc/include/xtensa-config.h
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@ -1,174 +0,0 @@
/* Xtensa configuration settings.
Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
Free Software Foundation, Inc.
Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef XTENSA_CONFIG_H
#define XTENSA_CONFIG_H
/* The macros defined here match those with the same names in the Xtensa
compile-time HAL (Hardware Abstraction Layer). Please refer to the
Xtensa System Software Reference Manual for documentation of these
macros. */
#undef XCHAL_HAVE_BE
#define XCHAL_HAVE_BE 0
#undef XCHAL_HAVE_DENSITY
#define XCHAL_HAVE_DENSITY 1
#undef XCHAL_HAVE_CONST16
#define XCHAL_HAVE_CONST16 0
#undef XCHAL_HAVE_ABS
#define XCHAL_HAVE_ABS 1
#undef XCHAL_HAVE_ADDX
#define XCHAL_HAVE_ADDX 1
#undef XCHAL_HAVE_L32R
#define XCHAL_HAVE_L32R 1
#undef XSHAL_USE_ABSOLUTE_LITERALS
#define XSHAL_USE_ABSOLUTE_LITERALS 0
#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
#undef XCHAL_HAVE_MAC16
#define XCHAL_HAVE_MAC16 1
#undef XCHAL_HAVE_MUL16
#define XCHAL_HAVE_MUL16 1
#undef XCHAL_HAVE_MUL32
#define XCHAL_HAVE_MUL32 1
#undef XCHAL_HAVE_MUL32_HIGH
#define XCHAL_HAVE_MUL32_HIGH 1
#undef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 0
#undef XCHAL_HAVE_NSA
#define XCHAL_HAVE_NSA 1
#undef XCHAL_HAVE_MINMAX
#define XCHAL_HAVE_MINMAX 1
#undef XCHAL_HAVE_SEXT
#define XCHAL_HAVE_SEXT 1
#undef XCHAL_HAVE_LOOPS
#define XCHAL_HAVE_LOOPS 1
#undef XCHAL_HAVE_THREADPTR
#define XCHAL_HAVE_THREADPTR 1
#undef XCHAL_HAVE_RELEASE_SYNC
#define XCHAL_HAVE_RELEASE_SYNC 1
#undef XCHAL_HAVE_S32C1I
#define XCHAL_HAVE_S32C1I 1
#undef XCHAL_HAVE_BOOLEANS
#define XCHAL_HAVE_BOOLEANS 1
#undef XCHAL_HAVE_FP
#define XCHAL_HAVE_FP 0
#undef XCHAL_HAVE_FP_DIV
#define XCHAL_HAVE_FP_DIV 0
#undef XCHAL_HAVE_FP_RECIP
#define XCHAL_HAVE_FP_RECIP 0
#undef XCHAL_HAVE_FP_SQRT
#define XCHAL_HAVE_FP_SQRT 0
#undef XCHAL_HAVE_FP_RSQRT
#define XCHAL_HAVE_FP_RSQRT 0
#undef XCHAL_HAVE_DFP_accel
#define XCHAL_HAVE_DFP_accel 0
#undef XCHAL_HAVE_WINDOWED
#define XCHAL_HAVE_WINDOWED 1
#undef XCHAL_NUM_AREGS
#define XCHAL_NUM_AREGS 32
#undef XCHAL_HAVE_WIDE_BRANCHES
#define XCHAL_HAVE_WIDE_BRANCHES 0
#undef XCHAL_HAVE_PREDICTED_BRANCHES
#define XCHAL_HAVE_PREDICTED_BRANCHES 0
#undef XCHAL_ICACHE_SIZE
#define XCHAL_ICACHE_SIZE 49152
#undef XCHAL_DCACHE_SIZE
#define XCHAL_DCACHE_SIZE 98304
#undef XCHAL_ICACHE_LINESIZE
#define XCHAL_ICACHE_LINESIZE 128
#undef XCHAL_DCACHE_LINESIZE
#define XCHAL_DCACHE_LINESIZE 128
#undef XCHAL_ICACHE_LINEWIDTH
#define XCHAL_ICACHE_LINEWIDTH 7
#undef XCHAL_DCACHE_LINEWIDTH
#define XCHAL_DCACHE_LINEWIDTH 7
#undef XCHAL_DCACHE_IS_WRITEBACK
#define XCHAL_DCACHE_IS_WRITEBACK 1
#undef XCHAL_HAVE_MMU
#define XCHAL_HAVE_MMU 0
#undef XCHAL_HAVE_DEBUG
#define XCHAL_HAVE_DEBUG 1
#undef XCHAL_NUM_IBREAK
#define XCHAL_NUM_IBREAK 2
#undef XCHAL_NUM_DBREAK
#define XCHAL_NUM_DBREAK 2
#undef XCHAL_DEBUGLEVEL
#define XCHAL_DEBUGLEVEL 6
#undef XCHAL_MAX_INSTRUCTION_SIZE
#define XCHAL_MAX_INSTRUCTION_SIZE 8
#undef XCHAL_INST_FETCH_WIDTH
#define XCHAL_INST_FETCH_WIDTH 8
#undef XSHAL_ABI
#undef XTHAL_ABI_WINDOWED
#undef XTHAL_ABI_CALL0
#define XSHAL_ABI XTHAL_ABI_WINDOWED
#define XTHAL_ABI_WINDOWED 0
#define XTHAL_ABI_CALL0 1
#endif /* !XTENSA_CONFIG_H */

42978
overlays/xtensa_intel_byt_adsp/gdb/bfd/xtensa-modules.c
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File diff suppressed because it is too large Load Diff

74
overlays/xtensa_intel_byt_adsp/gdb/gdb/regformats/reg-xtensa.dat
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@ -1,74 +0,0 @@
name:xtensa
expedite:pc,windowbase,windowstart
32:pc
32:ar0
32:ar1
32:ar2
32:ar3
32:ar4
32:ar5
32:ar6
32:ar7
32:ar8
32:ar9
32:ar10
32:ar11
32:ar12
32:ar13
32:ar14
32:ar15
32:ar16
32:ar17
32:ar18
32:ar19
32:ar20
32:ar21
32:ar22
32:ar23
32:ar24
32:ar25
32:ar26
32:ar27
32:ar28
32:ar29
32:ar30
32:ar31
32:lbeg
32:lend
32:lcount
32:sar
32:prefctl
32:windowbase
32:windowstart
32:configid0
32:sr176
32:configid1
32:sr208
32:ps
32:threadptr
32:br
32:scompare1
32:acclo
32:acchi
32:m0
32:m1
32:m2
32:m3
64:aep0
64:aep1
64:aep2
64:aep3
64:aep4
64:aep5
64:aep6
64:aep7
64:aeq0
64:aeq1
64:aeq2
64:aeq3
32:ae_ovf_sar
32:ae_bithead
32:ae_ts_fts_bu_bp
32:ae_sd_no
32:ae_cbegin0
32:ae_cend0

314
overlays/xtensa_intel_byt_adsp/gdb/gdb/xtensa-config.c
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@ -1,314 +0,0 @@
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
Copyright (c) 2003-2017 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#define XTENSA_CONFIG_VERSION 0x60
#include "defs.h"
#include "xtensa-config.h"
#include "xtensa-tdep.h"
/* Masked registers. */
xtensa_reg_mask_t xtensa_submask0[] = { { 46, 0, 1 } };
const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
xtensa_reg_mask_t xtensa_submask1[] = { { 46, 1, 1 } };
const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
xtensa_reg_mask_t xtensa_submask2[] = { { 46, 2, 1 } };
const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
xtensa_reg_mask_t xtensa_submask3[] = { { 46, 3, 1 } };
const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
xtensa_reg_mask_t xtensa_submask4[] = { { 46, 4, 1 } };
const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
xtensa_reg_mask_t xtensa_submask5[] = { { 46, 5, 1 } };
const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
xtensa_reg_mask_t xtensa_submask6[] = { { 46, 6, 1 } };
const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
xtensa_reg_mask_t xtensa_submask7[] = { { 46, 7, 1 } };
const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };
xtensa_reg_mask_t xtensa_submask8[] = { { 46, 8, 1 } };
const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };
xtensa_reg_mask_t xtensa_submask9[] = { { 46, 9, 1 } };
const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };
xtensa_reg_mask_t xtensa_submask10[] = { { 46, 10, 1 } };
const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };
xtensa_reg_mask_t xtensa_submask11[] = { { 46, 11, 1 } };
const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };
xtensa_reg_mask_t xtensa_submask12[] = { { 46, 12, 1 } };
const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };
xtensa_reg_mask_t xtensa_submask13[] = { { 46, 13, 1 } };
const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };
xtensa_reg_mask_t xtensa_submask14[] = { { 46, 14, 1 } };
const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };
xtensa_reg_mask_t xtensa_submask15[] = { { 46, 15, 1 } };
const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };
xtensa_reg_mask_t xtensa_submask16[] = { { 44, 0, 4 } };
const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 };
xtensa_reg_mask_t xtensa_submask17[] = { { 44, 5, 1 } };
const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 };
xtensa_reg_mask_t xtensa_submask18[] = { { 44, 18, 1 } };
const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 };
xtensa_reg_mask_t xtensa_submask19[] = { { 44, 4, 1 } };
const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 };
xtensa_reg_mask_t xtensa_submask20[] = { { 44, 16, 2 } };
const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 };
xtensa_reg_mask_t xtensa_submask21[] = { { 44, 8, 4 } };
const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 };
xtensa_reg_mask_t xtensa_submask22[] = { { 48, 0, 32 }, { 49, 0, 8 } };
const xtensa_mask_t xtensa_mask22 = { 2, xtensa_submask22 };
xtensa_reg_mask_t xtensa_submask23[] = { { 109, 8, 4 } };
const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 };
xtensa_reg_mask_t xtensa_submask24[] = { { 66, 6, 1 } };
const xtensa_mask_t xtensa_mask24 = { 1, xtensa_submask24 };
xtensa_reg_mask_t xtensa_submask25[] = { { 66, 0, 6 } };
const xtensa_mask_t xtensa_mask25 = { 1, xtensa_submask25 };
xtensa_reg_mask_t xtensa_submask26[] = { { 68, 0, 4 } };
const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 };
xtensa_reg_mask_t xtensa_submask27[] = { { 68, 4, 4 } };
const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 };
xtensa_reg_mask_t xtensa_submask28[] = { { 68, 12, 4 } };
const xtensa_mask_t xtensa_mask28 = { 1, xtensa_submask28 };
xtensa_reg_mask_t xtensa_submask29[] = { { 68, 8, 4 } };
const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 };
xtensa_reg_mask_t xtensa_submask30[] = { { 69, 0, 27 } };
const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 };
xtensa_reg_mask_t xtensa_submask31[] = { { 69, 27, 1 } };
const xtensa_mask_t xtensa_mask31 = { 1, xtensa_submask31 };
/* Register map. */
static xtensa_register_t rmap[] =
{
/* idx ofs bi sz al targno flags cp typ group name */
XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
XTREG( 37,148, 8, 4, 4,0x0228,0x0006,-2, 2,0x1100,prefctl, 0,0,0,0,0,0)
XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
XTREG( 41,164,32, 4, 4,0x02b0,0x0002,-2, 2,0x0000,sr176, 0,0,0,0,0,0)
XTREG( 42,168,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
XTREG( 43,172,32, 4, 4,0x02d0,0x0002,-2, 2,0x0000,sr208, 0,0,0,0,0,0)
XTREG( 44,176,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
XTREG( 45,180,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
XTREG( 46,184,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
XTREG( 47,188,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
XTREG( 48,192,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0)
XTREG( 49,196, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0)
XTREG( 50,200,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0)
XTREG( 51,204,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0)
XTREG( 52,208,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
XTREG( 53,212,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0)
XTREG( 54,216,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0,
"03:04:84:b2","03:04:84:a7",0,0,0,0)
XTREG( 55,224,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1,
"03:04:94:b2","03:04:94:a7",0,0,0,0)
XTREG( 56,232,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2,
"03:04:a4:b2","03:04:a4:a7",0,0,0,0)
XTREG( 57,240,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3,
"03:04:b4:b2","03:04:b4:a7",0,0,0,0)
XTREG( 58,248,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4,
"03:04:c4:b2","03:04:c4:a7",0,0,0,0)
XTREG( 59,256,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5,
"03:04:d4:b2","03:04:d4:a7",0,0,0,0)
XTREG( 60,264,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6,
"03:04:e4:b2","03:04:e4:a7",0,0,0,0)
XTREG( 61,272,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7,
"03:04:f4:b2","03:04:f4:a7",0,0,0,0)
XTREG( 62,280,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0,
"03:04:04:c3","03:04:04:c1",0,0,0,0)
XTREG( 63,288,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1,
"03:04:14:c3","03:04:44:c1",0,0,0,0)
XTREG( 64,296,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2,
"03:04:24:c3","03:04:84:c1",0,0,0,0)
XTREG( 65,304,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3,
"03:04:34:c3","03:04:c4:c1",0,0,0,0)
XTREG( 66,312, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0)
XTREG( 67,316,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0)
XTREG( 68,320,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0)
XTREG( 69,324,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no, 0,0,0,0,0,0)
XTREG( 70,328,32, 4, 4,0x03f6,0x0006, 1, 3,0x0110,ae_cbegin0, 0,0,0,0,0,0)
XTREG( 71,332,32, 4, 4,0x03f7,0x0006, 1, 3,0x0110,ae_cend0, 0,0,0,0,0,0)
XTREG( 72,336, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
XTREG( 73,340, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
XTREG( 74,344,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
XTREG( 75,348,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
XTREG( 76,352,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
XTREG( 77,356,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
XTREG( 78,360,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
XTREG( 79,364,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
XTREG( 80,368,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
XTREG( 81,372,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
XTREG( 82,376,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
XTREG( 83,380,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
XTREG( 84,384,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
XTREG( 85,388,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
XTREG( 86,392,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
XTREG( 87,396,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
XTREG( 88,400,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
XTREG( 89,404,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
XTREG( 90,408,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
XTREG( 91,412,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
XTREG( 92,416,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
XTREG( 93,420,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
XTREG( 94,424,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
XTREG( 95,428,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
XTREG( 96,432,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
XTREG( 97,436,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
XTREG( 98,440,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
XTREG( 99,444,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
XTREG(100,448,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
XTREG(101,452,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
XTREG(102,456, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
XTREG(103,460,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
XTREG(104,464,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
XTREG(105,468,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
XTREG(106,472,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
XTREG(107,476,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
XTREG(108,480, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
XTREG(109,484,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
XTREG(110,488,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
XTREG(111,492,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
XTREG(112,496,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
XTREG(113,500, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
XTREG(114,504,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
XTREG(115,508,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
XTREG(116,512,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
XTREG(117,516,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
XTREG(118,520,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
XTREG(119,524,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
XTREG(120,528,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
XTREG(121,532,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
XTREG(122,536,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
XTREG(123,540,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
XTREG(124,544,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
XTREG(125,548,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
XTREG(126,552,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
XTREG(127,556,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
XTREG(128,560,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
XTREG(129,564,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
XTREG(130,568,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
XTREG(131,572,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
XTREG(132,576,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
XTREG(133,580,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
XTREG(134,584, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
0,0,&xtensa_mask0,0,0,0)
XTREG(135,585, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
0,0,&xtensa_mask1,0,0,0)
XTREG(136,586, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
0,0,&xtensa_mask2,0,0,0)
XTREG(137,587, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
0,0,&xtensa_mask3,0,0,0)
XTREG(138,588, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
0,0,&xtensa_mask4,0,0,0)
XTREG(139,589, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
0,0,&xtensa_mask5,0,0,0)
XTREG(140,590, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
0,0,&xtensa_mask6,0,0,0)
XTREG(141,591, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
0,0,&xtensa_mask7,0,0,0)
XTREG(142,592, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
0,0,&xtensa_mask8,0,0,0)
XTREG(143,593, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
0,0,&xtensa_mask9,0,0,0)
XTREG(144,594, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
0,0,&xtensa_mask10,0,0,0)
XTREG(145,595, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
0,0,&xtensa_mask11,0,0,0)
XTREG(146,596, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
0,0,&xtensa_mask12,0,0,0)
XTREG(147,597, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
0,0,&xtensa_mask13,0,0,0)
XTREG(148,598, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
0,0,&xtensa_mask14,0,0,0)
XTREG(149,599, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
0,0,&xtensa_mask15,0,0,0)
XTREG(150,600, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
0,0,&xtensa_mask16,0,0,0)
XTREG(151,604, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
0,0,&xtensa_mask17,0,0,0)
XTREG(152,608, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
0,0,&xtensa_mask18,0,0,0)
XTREG(153,612, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
0,0,&xtensa_mask19,0,0,0)
XTREG(154,616, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
0,0,&xtensa_mask20,0,0,0)
XTREG(155,620, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
0,0,&xtensa_mask21,0,0,0)
XTREG(156,624,40, 8, 4,0x200e,0x0006,-2, 6,0x1010,acc,
0,0,&xtensa_mask22,0,0,0)
XTREG(157,632, 4, 4, 4,0x2013,0x0006,-2, 6,0x1010,dbnum,
0,0,&xtensa_mask23,0,0,0)
XTREG(158,636, 1, 4, 4,0x2014,0x0006, 1, 5,0x1010,ae_overflow,
0,0,&xtensa_mask24,0,0,0)
XTREG(159,640, 6, 4, 4,0x2015,0x0006, 1, 5,0x1010,ae_sar,
0,0,&xtensa_mask25,0,0,0)
XTREG(160,644, 4, 4, 4,0x2016,0x0006, 1, 5,0x1010,ae_bitptr,
0,0,&xtensa_mask26,0,0,0)
XTREG(161,648, 4, 4, 4,0x2017,0x0006, 1, 5,0x1010,ae_bitsused,
0,0,&xtensa_mask27,0,0,0)
XTREG(162,652, 4, 4, 4,0x2018,0x0006, 1, 5,0x1010,ae_tablesize,
0,0,&xtensa_mask28,0,0,0)
XTREG(163,656, 4, 4, 4,0x2019,0x0006, 1, 5,0x1010,ae_first_ts,
0,0,&xtensa_mask29,0,0,0)
XTREG(164,660,27, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_nextoffset,
0,0,&xtensa_mask30,0,0,0)
XTREG_END
};
xtensa_gdbarch_tdep xtensa_tdep (rmap);

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overlays/xtensa_intel_byt_adsp/gdb/gdb/xtensa-xtregs.c
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/* Customized table mapping between kernel xtregset and GDB register cache.
Copyright (c) 2007-2010 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
typedef struct {
int gdb_regnum;
int gdb_offset;
int ptrace_cp_offset;
int ptrace_offset;
int size;
int coproc;
int dbnum;
char* name
;} xtensa_regtable_t;
#define XTENSA_ELF_XTREG_SIZE 152
const xtensa_regtable_t xtensa_regmap_table[] = {
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
{ 46, 184, 24, 24, 4, -1, 0x0204, "br" },
{ 47, 188, 28, 28, 4, -1, 0x020c, "scompare1" },
{ 48, 192, 0, 0, 4, -1, 0x0210, "acclo" },
{ 49, 196, 4, 4, 4, -1, 0x0211, "acchi" },
{ 50, 200, 8, 8, 4, -1, 0x0220, "m0" },
{ 51, 204, 12, 12, 4, -1, 0x0221, "m1" },
{ 52, 208, 16, 16, 4, -1, 0x0222, "m2" },
{ 53, 212, 20, 20, 4, -1, 0x0223, "m3" },
{ 54, 216, 24, 56, 8, 1, 0x0060, "aep0" },
{ 55, 224, 32, 64, 8, 1, 0x0061, "aep1" },
{ 56, 232, 40, 72, 8, 1, 0x0062, "aep2" },
{ 57, 240, 48, 80, 8, 1, 0x0063, "aep3" },
{ 58, 248, 56, 88, 8, 1, 0x0064, "aep4" },
{ 59, 256, 64, 96, 8, 1, 0x0065, "aep5" },
{ 60, 264, 72, 104, 8, 1, 0x0066, "aep6" },
{ 61, 272, 80, 112, 8, 1, 0x0067, "aep7" },
{ 62, 280, 88, 120, 8, 1, 0x0068, "aeq0" },
{ 63, 288, 96, 128, 8, 1, 0x0069, "aeq1" },
{ 64, 296, 104, 136, 8, 1, 0x006a, "aeq2" },
{ 65, 304, 112, 144, 8, 1, 0x006b, "aeq3" },
{ 66, 312, 0, 32, 4, 1, 0x03f0, "ae_ovf_sar" },
{ 67, 316, 4, 36, 4, 1, 0x03f1, "ae_bithead" },
{ 68, 320, 8, 40, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" },
{ 69, 324, 12, 44, 4, 1, 0x03f3, "ae_sd_no" },
{ 70, 328, 16, 48, 4, 1, 0x03f6, "ae_cbegin0" },
{ 71, 332, 20, 52, 4, 1, 0x03f7, "ae_cend0" },
{ 0 }
};

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overlays/xtensa_intel_byt_adsp/gdb/gdbserver/xtensa-xtregs.cc
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/* Customized table mapping between kernel xtregset and GDB register cache.
Copyright (c) 2007-2010 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
typedef struct {
int gdb_regnum;
int gdb_offset;
int ptrace_cp_offset;
int ptrace_offset;
int size;
int coproc;
int dbnum;
char* name
;} xtensa_regtable_t;
#define XTENSA_ELF_XTREG_SIZE 152
const xtensa_regtable_t xtensa_regmap_table[] = {
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
{ 46, 184, 24, 24, 4, -1, 0x0204, "br" },
{ 47, 188, 28, 28, 4, -1, 0x020c, "scompare1" },
{ 48, 192, 0, 0, 4, -1, 0x0210, "acclo" },
{ 49, 196, 4, 4, 4, -1, 0x0211, "acchi" },
{ 50, 200, 8, 8, 4, -1, 0x0220, "m0" },
{ 51, 204, 12, 12, 4, -1, 0x0221, "m1" },
{ 52, 208, 16, 16, 4, -1, 0x0222, "m2" },
{ 53, 212, 20, 20, 4, -1, 0x0223, "m3" },
{ 54, 216, 24, 56, 8, 1, 0x0060, "aep0" },
{ 55, 224, 32, 64, 8, 1, 0x0061, "aep1" },
{ 56, 232, 40, 72, 8, 1, 0x0062, "aep2" },
{ 57, 240, 48, 80, 8, 1, 0x0063, "aep3" },
{ 58, 248, 56, 88, 8, 1, 0x0064, "aep4" },
{ 59, 256, 64, 96, 8, 1, 0x0065, "aep5" },
{ 60, 264, 72, 104, 8, 1, 0x0066, "aep6" },
{ 61, 272, 80, 112, 8, 1, 0x0067, "aep7" },
{ 62, 280, 88, 120, 8, 1, 0x0068, "aeq0" },
{ 63, 288, 96, 128, 8, 1, 0x0069, "aeq1" },
{ 64, 296, 104, 136, 8, 1, 0x006a, "aeq2" },
{ 65, 304, 112, 144, 8, 1, 0x006b, "aeq3" },
{ 66, 312, 0, 32, 4, 1, 0x03f0, "ae_ovf_sar" },
{ 67, 316, 4, 36, 4, 1, 0x03f1, "ae_bithead" },
{ 68, 320, 8, 40, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" },
{ 69, 324, 12, 44, 4, 1, 0x03f3, "ae_sd_no" },
{ 70, 328, 16, 48, 4, 1, 0x03f6, "ae_cbegin0" },
{ 71, 332, 20, 52, 4, 1, 0x03f7, "ae_cend0" },
{ 0 }
};

174
overlays/xtensa_intel_byt_adsp/gdb/include/xtensa-config.h
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/* Xtensa configuration settings.
Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
Free Software Foundation, Inc.
Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef XTENSA_CONFIG_H
#define XTENSA_CONFIG_H
/* The macros defined here match those with the same names in the Xtensa
compile-time HAL (Hardware Abstraction Layer). Please refer to the
Xtensa System Software Reference Manual for documentation of these
macros. */
#undef XCHAL_HAVE_BE
#define XCHAL_HAVE_BE 0
#undef XCHAL_HAVE_DENSITY
#define XCHAL_HAVE_DENSITY 1
#undef XCHAL_HAVE_CONST16
#define XCHAL_HAVE_CONST16 0
#undef XCHAL_HAVE_ABS
#define XCHAL_HAVE_ABS 1
#undef XCHAL_HAVE_ADDX
#define XCHAL_HAVE_ADDX 1
#undef XCHAL_HAVE_L32R
#define XCHAL_HAVE_L32R 1
#undef XSHAL_USE_ABSOLUTE_LITERALS
#define XSHAL_USE_ABSOLUTE_LITERALS 0
#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
#undef XCHAL_HAVE_MAC16
#define XCHAL_HAVE_MAC16 1
#undef XCHAL_HAVE_MUL16
#define XCHAL_HAVE_MUL16 1
#undef XCHAL_HAVE_MUL32
#define XCHAL_HAVE_MUL32 1
#undef XCHAL_HAVE_MUL32_HIGH
#define XCHAL_HAVE_MUL32_HIGH 1
#undef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 0
#undef XCHAL_HAVE_NSA
#define XCHAL_HAVE_NSA 1
#undef XCHAL_HAVE_MINMAX
#define XCHAL_HAVE_MINMAX 1
#undef XCHAL_HAVE_SEXT
#define XCHAL_HAVE_SEXT 1
#undef XCHAL_HAVE_LOOPS
#define XCHAL_HAVE_LOOPS 1
#undef XCHAL_HAVE_THREADPTR
#define XCHAL_HAVE_THREADPTR 1
#undef XCHAL_HAVE_RELEASE_SYNC
#define XCHAL_HAVE_RELEASE_SYNC 1
#undef XCHAL_HAVE_S32C1I
#define XCHAL_HAVE_S32C1I 1
#undef XCHAL_HAVE_BOOLEANS
#define XCHAL_HAVE_BOOLEANS 1
#undef XCHAL_HAVE_FP
#define XCHAL_HAVE_FP 0
#undef XCHAL_HAVE_FP_DIV
#define XCHAL_HAVE_FP_DIV 0
#undef XCHAL_HAVE_FP_RECIP
#define XCHAL_HAVE_FP_RECIP 0
#undef XCHAL_HAVE_FP_SQRT
#define XCHAL_HAVE_FP_SQRT 0
#undef XCHAL_HAVE_FP_RSQRT
#define XCHAL_HAVE_FP_RSQRT 0
#undef XCHAL_HAVE_DFP_accel
#define XCHAL_HAVE_DFP_accel 0
#undef XCHAL_HAVE_WINDOWED
#define XCHAL_HAVE_WINDOWED 1
#undef XCHAL_NUM_AREGS
#define XCHAL_NUM_AREGS 32
#undef XCHAL_HAVE_WIDE_BRANCHES
#define XCHAL_HAVE_WIDE_BRANCHES 0
#undef XCHAL_HAVE_PREDICTED_BRANCHES
#define XCHAL_HAVE_PREDICTED_BRANCHES 0
#undef XCHAL_ICACHE_SIZE
#define XCHAL_ICACHE_SIZE 49152
#undef XCHAL_DCACHE_SIZE
#define XCHAL_DCACHE_SIZE 98304
#undef XCHAL_ICACHE_LINESIZE
#define XCHAL_ICACHE_LINESIZE 128
#undef XCHAL_DCACHE_LINESIZE
#define XCHAL_DCACHE_LINESIZE 128
#undef XCHAL_ICACHE_LINEWIDTH
#define XCHAL_ICACHE_LINEWIDTH 7
#undef XCHAL_DCACHE_LINEWIDTH
#define XCHAL_DCACHE_LINEWIDTH 7
#undef XCHAL_DCACHE_IS_WRITEBACK
#define XCHAL_DCACHE_IS_WRITEBACK 1
#undef XCHAL_HAVE_MMU
#define XCHAL_HAVE_MMU 0
#undef XCHAL_HAVE_DEBUG
#define XCHAL_HAVE_DEBUG 1
#undef XCHAL_NUM_IBREAK
#define XCHAL_NUM_IBREAK 2
#undef XCHAL_NUM_DBREAK
#define XCHAL_NUM_DBREAK 2
#undef XCHAL_DEBUGLEVEL
#define XCHAL_DEBUGLEVEL 6
#undef XCHAL_MAX_INSTRUCTION_SIZE
#define XCHAL_MAX_INSTRUCTION_SIZE 8
#undef XCHAL_INST_FETCH_WIDTH
#define XCHAL_INST_FETCH_WIDTH 8
#undef XSHAL_ABI
#undef XTHAL_ABI_WINDOWED
#undef XTHAL_ABI_CALL0
#define XSHAL_ABI XTHAL_ABI_WINDOWED
#define XTHAL_ABI_WINDOWED 0
#define XTHAL_ABI_CALL0 1
#endif /* !XTENSA_CONFIG_H */

492
overlays/xtensa_intel_byt_adsp/linux/arch/xtensa/variants/byt/include/variant/core.h
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/*
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
* processor CORE configuration
*
* See <xtensa/config/core.h>, which includes this file, for more details.
*/
/* Xtensa processor core configuration information.
Copyright (c) 1999-2017 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XTENSA_CORE_CONFIGURATION_H
#define _XTENSA_CORE_CONFIGURATION_H
/****************************************************************************
Parameters Useful for Any Code, USER or PRIVILEGED
****************************************************************************/
/*
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
* configured, and a value of 0 otherwise. These macros are always defined.
*/
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
#define XCHAL_HAVE_DEBUG 1 /* debug option */
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
#define XCHAL_NUM_CONTEXTS 1 /* */
#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
#define XCHAL_HAVE_PRID 1 /* processor ID register */
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */
#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
#define XCHAL_HAVE_FP 0 /* floating point pkg */
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */
#define XCHAL_HAVE_HIFI2_MUL32X24 1 /* HiFi2 and 32x24 MACs */
#define XCHAL_HAVE_HIFI2EP 1 /* HiFi2EP */
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */
#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
/* In T1050, applies to selected core load and store instructions (see ISA): */
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */
#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/
#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/
#define XCHAL_SW_VERSION 900005 /* sw version of this header */
#define XCHAL_CORE_ID "Intel_HiFiEP" /* alphanum core name
(CoreID) set in the Xtensa
Processor Generator */
#define XCHAL_BUILD_UNIQUE_ID 0x000668E9 /* 22-bit sw build ID */
/*
* These definitions describe the hardware targeted by this software.
*/
#define XCHAL_HW_CONFIGID0 0xC3B3CFFE /* ConfigID hi 32 bits*/
#define XCHAL_HW_CONFIGID1 0x15455C8A /* ConfigID lo 32 bits*/
#define XCHAL_HW_VERSION_NAME "LX4.0.5" /* full version name */
#define XCHAL_HW_VERSION_MAJOR 2400 /* major ver# of targeted hw */
#define XCHAL_HW_VERSION_MINOR 5 /* minor ver# of targeted hw */
#define XCHAL_HW_VERSION 240005 /* major*100+minor */
#define XCHAL_HW_REL_LX4 1
#define XCHAL_HW_REL_LX4_0 1
#define XCHAL_HW_REL_LX4_0_5 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
/* If software targets a *range* of hardware versions, these are the bounds: */
#define XCHAL_HW_MIN_VERSION_MAJOR 2400 /* major v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION_MINOR 5 /* minor v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION 240005 /* earliest targeted hw */
#define XCHAL_HW_MAX_VERSION_MAJOR 2400 /* major v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION_MINOR 5 /* minor v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION 240005 /* latest targeted hw */
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */
#define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */
#define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */
#define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */
#define XCHAL_ICACHE_SIZE 49152 /* I-cache size in bytes or 0 */
#define XCHAL_DCACHE_SIZE 98304 /* D-cache size in bytes or 0 */
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */
/****************************************************************************
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
/* Number of cache sets in log2(lines per way): */
#define XCHAL_ICACHE_SETWIDTH 7
#define XCHAL_DCACHE_SETWIDTH 8
/* Cache set associativity (number of ways): */
#define XCHAL_ICACHE_WAYS 3
#define XCHAL_DCACHE_WAYS 3
/* Cache features: */
#define XCHAL_ICACHE_LINE_LOCKABLE 1
#define XCHAL_DCACHE_LINE_LOCKABLE 1
#define XCHAL_ICACHE_ECC_PARITY 0
#define XCHAL_DCACHE_ECC_PARITY 0
/* Cache access size in bytes (affects operation of SICW instruction): */
#define XCHAL_ICACHE_ACCESS_SIZE 8
#define XCHAL_DCACHE_ACCESS_SIZE 8
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
#define XCHAL_CA_BITS 4
/*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI
----------------------------------------------------------------------*/
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
/* Instruction RAM 0: */
#define XCHAL_INSTRAM0_VADDR 0xFF2C0000
#define XCHAL_INSTRAM0_PADDR 0xFF2C0000
#define XCHAL_INSTRAM0_SIZE 65536
#define XCHAL_INSTRAM0_ECC_PARITY 0
/* Instruction RAM 1: */
#define XCHAL_INSTRAM1_VADDR 0xFF2D0000
#define XCHAL_INSTRAM1_PADDR 0xFF2D0000
#define XCHAL_INSTRAM1_SIZE 16384
#define XCHAL_INSTRAM1_ECC_PARITY 0
/* Data RAM 0: */
#define XCHAL_DATARAM0_VADDR 0xFF300000
#define XCHAL_DATARAM0_PADDR 0xFF300000
#define XCHAL_DATARAM0_SIZE 131072
#define XCHAL_DATARAM0_ECC_PARITY 0
/* Data RAM 1: */
#define XCHAL_DATARAM1_VADDR 0xFF320000
#define XCHAL_DATARAM1_PADDR 0xFF320000
#define XCHAL_DATARAM1_SIZE 32768
#define XCHAL_DATARAM1_ECC_PARITY 0
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
/*----------------------------------------------------------------------
INTERRUPTS and TIMERS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
#define XCHAL_NUM_EXTINTERRUPTS 12 /* num of external interrupts */
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
(not including level zero) */
#define XCHAL_EXCM_LEVEL 5 /* level masked by PS.EXCM */
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
/* Masks of interrupts at each interrupt level: */
#define XCHAL_INTLEVEL1_MASK 0x0000000F
#define XCHAL_INTLEVEL2_MASK 0x00000070
#define XCHAL_INTLEVEL3_MASK 0x00000380
#define XCHAL_INTLEVEL4_MASK 0x00200C00
#define XCHAL_INTLEVEL5_MASK 0x000FF000
#define XCHAL_INTLEVEL6_MASK 0x00000000
#define XCHAL_INTLEVEL7_MASK 0x00100000
/* Masks of interrupts at each range 1..n of interrupt levels: */
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0000000F
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x0000007F
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x000003FF
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00200FFF
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x002FFFFF
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x002FFFFF
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
/* Level of each interrupt: */
#define XCHAL_INT0_LEVEL 1
#define XCHAL_INT1_LEVEL 1
#define XCHAL_INT2_LEVEL 1
#define XCHAL_INT3_LEVEL 1
#define XCHAL_INT4_LEVEL 2
#define XCHAL_INT5_LEVEL 2
#define XCHAL_INT6_LEVEL 2
#define XCHAL_INT7_LEVEL 3
#define XCHAL_INT8_LEVEL 3
#define XCHAL_INT9_LEVEL 3
#define XCHAL_INT10_LEVEL 4
#define XCHAL_INT11_LEVEL 4
#define XCHAL_INT12_LEVEL 5
#define XCHAL_INT13_LEVEL 5
#define XCHAL_INT14_LEVEL 5
#define XCHAL_INT15_LEVEL 5
#define XCHAL_INT16_LEVEL 5
#define XCHAL_INT17_LEVEL 5
#define XCHAL_INT18_LEVEL 5
#define XCHAL_INT19_LEVEL 5
#define XCHAL_INT20_LEVEL 7
#define XCHAL_INT21_LEVEL 4
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
EXCSAVE/EPS/EPC_n, RFI n) */
/* Type of each interrupt: */
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_NMI
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
/* Masks of interrupts for each type of interrupt: */
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0000134D
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x002FEC10
#define XCHAL_INTTYPE_MASK_TIMER 0x000000A2
#define XCHAL_INTTYPE_MASK_NMI 0x00100000
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
/* Interrupt numbers assigned to specific interrupt sources: */
#define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */
#define XCHAL_TIMER1_INTERRUPT 5 /* CCOMPARE1 */
#define XCHAL_TIMER2_INTERRUPT 7 /* CCOMPARE2 */
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
#define XCHAL_NMI_INTERRUPT 20 /* non-maskable interrupt */
/* Interrupt numbers for levels at which only one interrupt is configured: */
#define XCHAL_INTLEVEL7_NUM 20
/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */
/*
* External interrupt vectors/levels.
* These macros describe how Xtensa processor interrupt numbers
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
* map to external BInterrupt<n> pins, for those interrupts
* configured as external (level-triggered, edge-triggered, or NMI).
* See the Xtensa processor databook for more details.
*/
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
#define XCHAL_EXTINT0_NUM 4 /* (intlevel 2) */
#define XCHAL_EXTINT1_NUM 10 /* (intlevel 4) */
#define XCHAL_EXTINT2_NUM 11 /* (intlevel 4) */
#define XCHAL_EXTINT3_NUM 13 /* (intlevel 5) */
#define XCHAL_EXTINT4_NUM 14 /* (intlevel 5) */
#define XCHAL_EXTINT5_NUM 15 /* (intlevel 5) */
#define XCHAL_EXTINT6_NUM 16 /* (intlevel 5) */
#define XCHAL_EXTINT7_NUM 17 /* (intlevel 5) */
#define XCHAL_EXTINT8_NUM 18 /* (intlevel 5) */
#define XCHAL_EXTINT9_NUM 19 /* (intlevel 5) */
#define XCHAL_EXTINT10_NUM 20 /* (intlevel 7) */
#define XCHAL_EXTINT11_NUM 21 /* (intlevel 4) */
/*----------------------------------------------------------------------
EXCEPTIONS and VECTORS
----------------------------------------------------------------------*/
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
number: 1 == XEA1 (old)
2 == XEA2 (new)
0 == XEAX (extern) or TX */
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
#define XCHAL_VECBASE_RESET_VADDR 0x00100400 /* VECBASE reset value */
#define XCHAL_VECBASE_RESET_PADDR 0x00100400
#define XCHAL_RESET_VECBASE_OVERLAP 0
#define XCHAL_RESET_VECTOR0_VADDR 0x00100000
#define XCHAL_RESET_VECTOR0_PADDR 0x00100000
#define XCHAL_RESET_VECTOR1_VADDR 0xFF2C0000
#define XCHAL_RESET_VECTOR1_PADDR 0xFF2C0000
#define XCHAL_RESET_VECTOR_VADDR 0x00100000
#define XCHAL_RESET_VECTOR_PADDR 0x00100000
#define XCHAL_USER_VECOFS 0x0000025C
#define XCHAL_USER_VECTOR_VADDR 0x0010065C
#define XCHAL_USER_VECTOR_PADDR 0x0010065C
#define XCHAL_KERNEL_VECOFS 0x0000023C
#define XCHAL_KERNEL_VECTOR_VADDR 0x0010063C
#define XCHAL_KERNEL_VECTOR_PADDR 0x0010063C
#define XCHAL_DOUBLEEXC_VECOFS 0x0000027C
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x0010067C
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x0010067C
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
#define XCHAL_WINDOW_VECTORS_VADDR 0x00100400
#define XCHAL_WINDOW_VECTORS_PADDR 0x00100400
#define XCHAL_INTLEVEL2_VECOFS 0x0000017C
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x0010057C
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x0010057C
#define XCHAL_INTLEVEL3_VECOFS 0x0000019C
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x0010059C
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x0010059C
#define XCHAL_INTLEVEL4_VECOFS 0x000001BC
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x001005BC
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x001005BC
#define XCHAL_INTLEVEL5_VECOFS 0x000001DC
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x001005DC
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x001005DC
#define XCHAL_INTLEVEL6_VECOFS 0x000001FC
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x001005FC
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x001005FC
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
#define XCHAL_NMI_VECOFS 0x0000021C
#define XCHAL_NMI_VECTOR_VADDR 0x0010061C
#define XCHAL_NMI_VECTOR_PADDR 0x0010061C
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
/*----------------------------------------------------------------------
DEBUG
----------------------------------------------------------------------*/
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
/* See core-matmap.h header file for more details. */
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
#define XCHAL_HAVE_XLT_CACHEATTR 1 /* region prot. w/translation */
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
[autorefill] and protection)
usable for an MMU-based OS */
/* If none of the above last 4 are set, it's a custom TLB configuration. */
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
#endif /* _XTENSA_CORE_CONFIGURATION_H */

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overlays/xtensa_intel_byt_adsp/linux/arch/xtensa/variants/byt/include/variant/tie-asm.h
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@ -1,311 +0,0 @@
/*
* tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
*
* NOTE: This header file is not meant to be included directly.
*/
/* This header file contains assembly-language definitions (assembly
macros, etc.) for this specific Xtensa processor's TIE extensions
and options. It is customized to this Xtensa processor configuration.
Copyright (c) 1999-2017 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XTENSA_CORE_TIE_ASM_H
#define _XTENSA_CORE_TIE_ASM_H
/* Selection parameter values for save-area save/restore macros: */
/* Option vs. TIE: */
#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
/* Whether used automatically by compiler: */
#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
/* ABI handling across function calls: */
#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
/* Misc */
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
| ((ccuse) & XTHAL_SAS_ANYCC) \
| ((abi) & XTHAL_SAS_ANYABI) )
/*
* Macro to save all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters:
* continue If macro invoked as part of a larger store sequence, set to 1
* if this is not the first in the sequence. Defaults to 0.
* ofs Offset from start of larger sequence (from value of first ptr
* in sequence) at which to store. Defaults to next available space
* (or 0 if <continue> is 0).
* select Select what category(ies) of registers to store, as a bitmask
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
* alloc Select what category(ies) of registers to allocate; if any
* category is selected here that is not in <select>, space for
* the corresponding registers is skipped without doing any store.
*/
.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Optional global register used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
xchal_sa_align \ptr, 0, 1020, 4, 4
rur.THREADPTR \at1 // threadptr option
s32i \at1, \ptr, .Lxchal_ofs_+0
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1020, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
// Optional caller-saved registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4
rsr.ACCLO \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+0
rsr.ACCHI \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1016, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.endif
// Optional caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1000, 4, 4
rsr.M0 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+0
rsr.M1 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+4
rsr.M2 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+8
rsr.M3 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+12
rsr.BR \at1 // boolean option
s32i \at1, \ptr, .Lxchal_ofs_+16
rsr.SCOMPARE1 \at1 // conditional store option
s32i \at1, \ptr, .Lxchal_ofs_+20
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1000, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.endif
.endm // xchal_ncp_store
/*
* Macro to restore all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters:
* continue If macro invoked as part of a larger load sequence, set to 1
* if this is not the first in the sequence. Defaults to 0.
* ofs Offset from start of larger sequence (from value of first ptr
* in sequence) at which to load. Defaults to next available space
* (or 0 if <continue> is 0).
* select Select what category(ies) of registers to load, as a bitmask
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
* alloc Select what category(ies) of registers to allocate; if any
* category is selected here that is not in <select>, space for
* the corresponding registers is skipped without doing any load.
*/
.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Optional global register used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
xchal_sa_align \ptr, 0, 1020, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wur.THREADPTR \at1 // threadptr option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1020, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
// Optional caller-saved registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wsr.ACCLO \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+4
wsr.ACCHI \at1 // MAC16 option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1016, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.endif
// Optional caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1000, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wsr.M0 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+4
wsr.M1 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+8
wsr.M2 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+12
wsr.M3 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+16
wsr.BR \at1 // boolean option
l32i \at1, \ptr, .Lxchal_ofs_+20
wsr.SCOMPARE1 \at1 // conditional store option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1000, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.endif
.endm // xchal_ncp_load
#define XCHAL_NCP_NUM_ATMPS 1
/*
* Macro to save the state of TIE coprocessor AudioEngineLX.
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 8 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters are the same as for xchal_ncp_store.
*/
#define xchal_cp_AudioEngineLX_store xchal_cp1_store
.macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 0, 8, 8
rur.AE_OVF_SAR \at1 // ureg 240
s32i \at1, \ptr, .Lxchal_ofs_+0
rur.AE_BITHEAD \at1 // ureg 241
s32i \at1, \ptr, .Lxchal_ofs_+4
rur.AE_TS_FTS_BU_BP \at1 // ureg 242
s32i \at1, \ptr, .Lxchal_ofs_+8
rur.AE_SD_NO \at1 // ureg 243
s32i \at1, \ptr, .Lxchal_ofs_+12
rur.AE_CBEGIN0 \at1 // ureg 246
s32i \at1, \ptr, .Lxchal_ofs_+16
rur.AE_CEND0 \at1 // ureg 247
s32i \at1, \ptr, .Lxchal_ofs_+20
AE_SP24X2S.I aep0, \ptr, .Lxchal_ofs_+24
AE_SP24X2S.I aep1, \ptr, .Lxchal_ofs_+32
AE_SP24X2S.I aep2, \ptr, .Lxchal_ofs_+40
AE_SP24X2S.I aep3, \ptr, .Lxchal_ofs_+48
AE_SP24X2S.I aep4, \ptr, .Lxchal_ofs_+56
addi \ptr, \ptr, 64
AE_SP24X2S.I aep5, \ptr, .Lxchal_ofs_+0
AE_SP24X2S.I aep6, \ptr, .Lxchal_ofs_+8
AE_SP24X2S.I aep7, \ptr, .Lxchal_ofs_+16
AE_SQ56S.I aeq0, \ptr, .Lxchal_ofs_+24
AE_SQ56S.I aeq1, \ptr, .Lxchal_ofs_+32
AE_SQ56S.I aeq2, \ptr, .Lxchal_ofs_+40
AE_SQ56S.I aeq3, \ptr, .Lxchal_ofs_+48
.set .Lxchal_pofs_, .Lxchal_pofs_ + 64
.set .Lxchal_ofs_, .Lxchal_ofs_ + 56
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 0, 8, 8
.set .Lxchal_ofs_, .Lxchal_ofs_ + 120
.endif
.endm // xchal_cp1_store
/*
* Macro to restore the state of TIE coprocessor AudioEngineLX.
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 8 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters are the same as for xchal_ncp_load.
*/
#define xchal_cp_AudioEngineLX_load xchal_cp1_load
.macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 0, 8, 8
l32i \at1, \ptr, .Lxchal_ofs_+0
wur.AE_OVF_SAR \at1 // ureg 240
l32i \at1, \ptr, .Lxchal_ofs_+4
wur.AE_BITHEAD \at1 // ureg 241
l32i \at1, \ptr, .Lxchal_ofs_+8
wur.AE_TS_FTS_BU_BP \at1 // ureg 242
l32i \at1, \ptr, .Lxchal_ofs_+12
wur.AE_SD_NO \at1 // ureg 243
l32i \at1, \ptr, .Lxchal_ofs_+16
wur.AE_CBEGIN0 \at1 // ureg 246
l32i \at1, \ptr, .Lxchal_ofs_+20
wur.AE_CEND0 \at1 // ureg 247
AE_LP24X2.I aep0, \ptr, .Lxchal_ofs_+24
AE_LP24X2.I aep1, \ptr, .Lxchal_ofs_+32
AE_LP24X2.I aep2, \ptr, .Lxchal_ofs_+40
AE_LP24X2.I aep3, \ptr, .Lxchal_ofs_+48
AE_LP24X2.I aep4, \ptr, .Lxchal_ofs_+56
addi \ptr, \ptr, 64
AE_LP24X2.I aep5, \ptr, .Lxchal_ofs_+0
AE_LP24X2.I aep6, \ptr, .Lxchal_ofs_+8
AE_LP24X2.I aep7, \ptr, .Lxchal_ofs_+16
AE_LQ56.I aeq0, \ptr, .Lxchal_ofs_+24
AE_LQ56.I aeq1, \ptr, .Lxchal_ofs_+32
AE_LQ56.I aeq2, \ptr, .Lxchal_ofs_+40
AE_LQ56.I aeq3, \ptr, .Lxchal_ofs_+48
.set .Lxchal_pofs_, .Lxchal_pofs_ + 64
.set .Lxchal_ofs_, .Lxchal_ofs_ + 56
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 0, 8, 8
.set .Lxchal_ofs_, .Lxchal_ofs_ + 120
.endif
.endm // xchal_cp1_load
#define XCHAL_CP1_NUM_ATMPS 1
#define XCHAL_SA_NUM_ATMPS 1
/* Empty macros for unconfigured coprocessors: */
.macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
#endif /*_XTENSA_CORE_TIE_ASM_H*/

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/*
* tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
*
* NOTE: This header file is not meant to be included directly.
*/
/* This header file describes this specific Xtensa processor's TIE extensions
that extend basic Xtensa core functionality. It is customized to this
Xtensa processor configuration.
Copyright (c) 1999-2017 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XTENSA_CORE_TIE_H
#define _XTENSA_CORE_TIE_H
#define XCHAL_CP_NUM 1 /* number of coprocessors */
#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
/* Basic parameters of each coprocessor: */
#define XCHAL_CP1_NAME "AudioEngineLX"
#define XCHAL_CP1_IDENT AudioEngineLX
#define XCHAL_CP1_SA_SIZE 120 /* size of state save area */
#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
#define XCHAL_CP0_SA_SIZE 0
#define XCHAL_CP0_SA_ALIGN 1
#define XCHAL_CP2_SA_SIZE 0
#define XCHAL_CP2_SA_ALIGN 1
#define XCHAL_CP3_SA_SIZE 0
#define XCHAL_CP3_SA_ALIGN 1
#define XCHAL_CP4_SA_SIZE 0
#define XCHAL_CP4_SA_ALIGN 1
#define XCHAL_CP5_SA_SIZE 0
#define XCHAL_CP5_SA_ALIGN 1
#define XCHAL_CP6_SA_SIZE 0
#define XCHAL_CP6_SA_ALIGN 1
#define XCHAL_CP7_SA_SIZE 0
#define XCHAL_CP7_SA_ALIGN 1
/* Save area for non-coprocessor optional and custom (TIE) state: */
#define XCHAL_NCP_SA_SIZE 36
#define XCHAL_NCP_SA_ALIGN 4
/* Total save area for optional and custom state (NCP + CPn): */
#define XCHAL_TOTAL_SA_SIZE 176 /* with 16-byte align padding */
#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
/*
* Detailed contents of save areas.
* NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
* before expanding the XCHAL_xxx_SA_LIST() macros.
*
* XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
* dbnum,base,regnum,bitsz,gapsz,reset,x...)
*
* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
* ccused = set if used by compiler without special options or code
* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
* name = lowercase reg name (no quotes)
* galign = group byte alignment (power of 2) (galign >= align)
* align = register byte alignment (power of 2)
* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
* (not including any pad bytes required to galign this or next reg)
* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
* regnum = reg index in regfile, or special/TIE-user reg number
* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
* gapsz = intervening bits, if bitsz bits not stored contiguously
* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
* reset = register reset value (or 0 if undefined at reset)
* x = reserved for future use (0 until then)
*
* To filter out certain registers, e.g. to expand only the non-global
* registers used by the compiler, you can do something like this:
*
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
* #define SELCC0(p...)
* #define SELCC1(abikind,p...) SELAK##abikind(p)
* #define SELAK0(p...) REG(p)
* #define SELAK1(p...) REG(p)
* #define SELAK2(p...)
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
* ...what you want to expand...
*/
#define XCHAL_NCP_SA_NUM 9
#define XCHAL_NCP_SA_LIST(s) \
XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
#define XCHAL_CP0_SA_NUM 0
#define XCHAL_CP0_SA_LIST(s) /* empty */
#define XCHAL_CP1_SA_NUM 18
#define XCHAL_CP1_SA_LIST(s) \
XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 7,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, ae_sd_no, 4, 4, 4,0x03F3, ur,243, 28,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, ae_cbegin0, 4, 4, 4,0x03F6, ur,246, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, ae_cend0, 4, 4, 4,0x03F7, ur,247, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, aep0, 8, 8, 8,0x0060, aep,0 , 48,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, aep1, 8, 8, 8,0x0061, aep,1 , 48,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, aep2, 8, 8, 8,0x0062, aep,2 , 48,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, aep3, 8, 8, 8,0x0063, aep,3 , 48,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, aep4, 8, 8, 8,0x0064, aep,4 , 48,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, aep5, 8, 8, 8,0x0065, aep,5 , 48,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, aep6, 8, 8, 8,0x0066, aep,6 , 48,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, aep7, 8, 8, 8,0x0067, aep,7 , 48,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, aeq0, 8, 8, 8,0x0068, aeq,0 , 56,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, aeq1, 8, 8, 8,0x0069, aeq,1 , 56,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, aeq2, 8, 8, 8,0x006A, aeq,2 , 56,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, aeq3, 8, 8, 8,0x006B, aeq,3 , 56,0,0,0)
#define XCHAL_CP2_SA_NUM 0
#define XCHAL_CP2_SA_LIST(s) /* empty */
#define XCHAL_CP3_SA_NUM 0
#define XCHAL_CP3_SA_LIST(s) /* empty */
#define XCHAL_CP4_SA_NUM 0
#define XCHAL_CP4_SA_LIST(s) /* empty */
#define XCHAL_CP5_SA_NUM 0
#define XCHAL_CP5_SA_LIST(s) /* empty */
#define XCHAL_CP6_SA_NUM 0
#define XCHAL_CP6_SA_LIST(s) /* empty */
#define XCHAL_CP7_SA_NUM 0
#define XCHAL_CP7_SA_LIST(s) /* empty */
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8
#endif /*_XTENSA_CORE_TIE_H*/