target/arc: introduce basic smp support
With this commit we introduce basic SMP support for ARC targets. Only running smp application in telnet is supported, GDB is not supported yet. SMP support starts with running "smp target1 target2..." command during target initialization. This command creates linked list of targets and sets for each ->smp=1. Next running poll() function if one core is halted, it is necessary to poll other cores in list. And finally resuming execution it is necessary to restore context on each target and run each core. Major changes in this commit: * Add "arc_smp on/of" handlers. * Modify resume, poll functions to process slave cores. * Introduced arc_dbg_set_pc() and arc_ocd_poll_smp() functions * Introduced target/board snps_hsdk_smp.cfg files. Usage via telnet: > load /path/to/bin > resume <start_address> Signed-off-by: Evgeniy Didin <didin@synopsys.com>
This commit is contained in:
Evgeniy Didin
Kumar Gala
parent
a0e8edc4e7
commit
580d06d9dd
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@ -389,7 +389,7 @@ int arc32_start_core(struct target *target)
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CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc32->jtag_info, AUX_STATUS32_REG, &value));
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value &= ~SET_CORE_HALT_BIT; /* clear the HALT bit */
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CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc32->jtag_info, AUX_STATUS32_REG, value));
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LOG_DEBUG("Core started to run");
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LOG_DEBUG("Core %s started to run", target_name(target));
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#ifdef DEBUG
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CHECK_RETVAL(arc32_print_core_state(target));
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@ -32,6 +32,7 @@
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#include "target.h"
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#include "target_request.h"
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#include "target_type.h"
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#include "smp.h"
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#include "arc_dbg.h"
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#include "arc_jtag.h"
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@ -555,13 +555,72 @@ int arc_dbg_halt(struct target *target)
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return ERROR_OK;
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}
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static int arc_dbg_set_pc(struct target *target, int current, target_addr_t address)
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{
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int retval = ERROR_OK;
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uint32_t resume_pc = 0;
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struct arc32_common *arc32 = target_to_arc32(target);
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struct reg *pc = &arc32->core_cache->reg_list[arc32->pc_index_in_cache];
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/* current = 1: continue on current PC, otherwise continue at <address> */
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if (!current) {
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buf_set_u32(pc->value, 0, 32, address);
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pc->dirty = 1;
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pc->valid = 1;
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LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address);
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}
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if (!current)
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resume_pc = address;
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else
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resume_pc = buf_get_u32(pc->value, 0, 32);
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LOG_DEBUG("Target resumes from PC=0x%" PRIx32 ", pc.dirty=%i, pc.valid=%i",
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resume_pc, pc->dirty, pc->valid);
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/* check if GDB tells to set our PC where to continue from */
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if ((pc->valid == 1) && (resume_pc == buf_get_u32(pc->value, 0, 32))) {
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uint32_t value;
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value = buf_get_u32(pc->value, 0, 32);
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LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32, value);
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retval = arc_jtag_write_aux_reg_one(&arc32->jtag_info, AUX_PC_REG, value);
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}
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return retval;
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}
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static int arc_dbg_restore_smp(struct target *target, int current, target_addr_t address, int debug_execution)
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{
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int retval = 0;
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struct target_list *head;
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struct target *curr;
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head = target->head;
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LOG_DEBUG("Restoring smp");
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while (head != (struct target_list *)NULL) {
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curr = head->target;
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if ((curr != target) && (curr->state != TARGET_RUNNING)
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&& target_was_examined(curr)) {
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retval += arc32_restore_context(curr);
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retval = arc_dbg_set_pc(curr, current, address);
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arc32_enable_interrupts(curr, !debug_execution);
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retval += arc32_start_core(curr);
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}
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head = head->next;
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}
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return retval;
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}
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int arc_dbg_resume(struct target *target, int current, target_addr_t address,
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int handle_breakpoints, int debug_execution)
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{
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struct arc32_common *arc32 = target_to_arc32(target);
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struct breakpoint *breakpoint = NULL;
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uint32_t resume_pc = 0;
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struct reg *pc = &arc32->core_cache->reg_list[arc32->pc_index_in_cache];
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LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints:%i, debug_execution:%i",
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current, address, handle_breakpoints, debug_execution);
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@ -579,36 +638,20 @@ int arc_dbg_resume(struct target *target, int current, target_addr_t address,
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arc_dbg_enable_watchpoints(target);
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}
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/* current = 1: continue on current PC, otherwise continue at <address> */
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if (!current) {
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buf_set_u32(pc->value, 0, 32, address);
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pc->dirty = 1;
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pc->valid = 1;
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LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address);
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}
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if (!current)
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resume_pc = address;
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else
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resume_pc = buf_get_u32(pc->value,
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0, 32);
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/* We need to reset ARC cache variables so caches
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* would be invalidated and actual data
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* would be fetched from memory. */
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arc32_reset_caches_states(target);
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arc32_restore_context(target);
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LOG_DEBUG("Target resumes from PC=0x%" PRIx32 ", pc.dirty=%i, pc.valid=%i",
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resume_pc, pc->dirty, pc->valid);
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/* check if GDB tells to set our PC where to continue from */
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if ((pc->valid == 1) && (resume_pc == buf_get_u32(pc->value, 0, 32))) {
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uint32_t value;
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value = buf_get_u32(pc->value, 0, 32);
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LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32, value);
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arc_jtag_write_aux_reg_one(&arc32->jtag_info, AUX_PC_REG, value);
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int retval;
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if (target->smp) {
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target->gdb_service->core[0] = -1;
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retval = arc_dbg_restore_smp(target, current, address, debug_execution);
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if (retval != ERROR_OK)
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return retval;
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}
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arc32_restore_context(target);
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arc_dbg_set_pc(target, current, address);
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/* the front-end may request us not to handle breakpoints */
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if (handle_breakpoints) {
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@ -1046,6 +1046,44 @@ static int jim_handle_actionpoints_num(Jim_Interp *interp, int argc,
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return JIM_OK;
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}
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COMMAND_HANDLER(arc_handle_smp_off_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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/* check target is an smp target */
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struct target_list *head;
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struct target *curr;
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head = target->head;
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target->smp = 0;
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if (head != (struct target_list *)NULL) {
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while (head != (struct target_list *)NULL) {
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curr = head->target;
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curr->smp = 0;
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head = head->next;
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}
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/* fixes the target display to the debugger */
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target->gdb_service->target = target;
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}
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return ERROR_OK;
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}
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COMMAND_HANDLER(arc_handle_smp_on_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct target_list *head;
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struct target *curr;
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head = target->head;
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if (head != (struct target_list *)NULL) {
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target->smp = 1;
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while (head != (struct target_list *)NULL) {
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curr = head->target;
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curr->smp = 1;
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head = head->next;
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}
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}
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return ERROR_OK;
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}
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static const struct command_registration arc_jtag_command_group[] = {
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{
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.name = "always-check-status-rd",
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@ -1201,6 +1239,20 @@ static const struct command_registration arc_core_command_handlers[] = {
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.usage = "[<unsigned integer>]",
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.help = "Prints or sets amount of actionpoints in the processor.",
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},
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{
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.name = "smp_off",
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.handler = arc_handle_smp_off_command,
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.mode = COMMAND_EXEC,
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.usage = "arc smp_off",
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.help = "Stop smp handling",
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},
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{
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.name = "smp_on",
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.handler = arc_handle_smp_on_command,
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.mode = COMMAND_EXEC,
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.usage = "arc smp_on",
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.help = "Restart smp handling",
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},
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COMMAND_REGISTRATION_DONE
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};
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@ -44,6 +44,33 @@ static int arc_ocd_init_arch_info(struct target *target,
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return ERROR_OK;
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}
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static int arc_ocd_poll_smp(struct target *target)
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{
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struct target_list *head;
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struct target *curr;
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int retval = 0;
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foreach_smp_target(head, target->head) {
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curr = head->target;
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/* skip calling context */
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if (curr == target)
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continue;
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if (!target_was_examined(curr))
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continue;
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/* skip targets that were already halted */
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if (curr->state == TARGET_HALTED)
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continue;
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/* avoid recursion in arc_ocd_poll() */
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curr->smp = 0;
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arc_ocd_poll(curr);
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curr->smp = 1;
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}
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return retval;
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}
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/* ----- Exported functions ------------------------------------------------ */
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int arc_ocd_poll(struct target *target)
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@ -53,7 +80,6 @@ int arc_ocd_poll(struct target *target)
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/* gdb calls continuously through this arc_poll() function */
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CHECK_RETVAL(arc_jtag_status(&arc32->jtag_info, &status));
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/* check for processor halted */
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if (status & ARC_JTAG_STAT_RU) {
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if (target->state != TARGET_RUNNING){
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@ -68,6 +94,13 @@ int arc_ocd_poll(struct target *target)
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LOG_DEBUG("ARC core is halted or in reset.");
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CHECK_RETVAL(arc_dbg_debug_entry(target));
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int retval = 0;
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if (target->smp) {
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retval = arc_ocd_poll_smp(target);
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if (retval != ERROR_OK)
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return retval;
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}
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target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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} else if (target->state == TARGET_DEBUG_RUNNING) {
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@ -0,0 +1,36 @@
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# Copyright (C) 2019 Synopsys, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the
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# Free Software Foundation, Inc.,
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#
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# Synopsys DesignWare ARC AXS103 Software Development Platform (HS38 cores)
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#
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# Configure JTAG cable
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# SDP has built-in FT2232 chip, which is similiar to Digilent HS-1, except that
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# it uses channgel B for JTAG, instead of channel A.
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source [find interface/ftdi/snps_sdp.cfg]
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adapter_khz 10000
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# ARCs supports only JTAG.
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transport select jtag
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# Configure SoC
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source [find target/snps_hsdk_smp.cfg]
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# Initialize
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init
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reset halt
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@ -0,0 +1,95 @@
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# Copyright (C) 2019 Synopsys, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the
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# Free Software Foundation, Inc.,
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#
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# HS Development Kit SoC.
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#
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# Contains quad-core ARC HS38.
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#
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source [find cpu/arc/hs.tcl]
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set _coreid 0
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set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
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# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
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# OpenOCD is concerned EM and HS are identical.
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set _CHIPNAME arc-em
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# OpenOCD discovers JTAG TAPs in reverse order.
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# ARC HS38 core 4
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set _TARGETNAME $_CHIPNAME.cpu4
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jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1
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target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
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$_TARGETNAME configure -coreid $_coreid
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$_TARGETNAME configure -dbgbase $_dbgbase
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# Flush L2$.
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$_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME"
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set _coreid [expr $_coreid + 1]
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set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
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arc_hs_init_regs
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# Enable L2 cache support for core 4.
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$_TARGETNAME arc has-l2cache true
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# ARC HS38 core 3
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set _TARGETNAME1 $_CHIPNAME.cpu3
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jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1
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target create $_TARGETNAME1 arcv2 -chain-position $_TARGETNAME1
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$_TARGETNAME1 configure -coreid $_coreid
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$_TARGETNAME1 configure -dbgbase $_dbgbase
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$_TARGETNAME1 configure -event reset-assert "arc_common_reset $_TARGETNAME1"
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set _coreid [expr $_coreid + 1]
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set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
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arc_hs_init_regs
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# Enable L2 cache support for core 3.
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$_TARGETNAME1 arc has-l2cache true
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# ARC HS38 core 2
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set _TARGETNAME2 $_CHIPNAME.cpu2
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jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
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target create $_TARGETNAME2 arcv2 -chain-position $_TARGETNAME2
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$_TARGETNAME2 configure -coreid $_coreid
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$_TARGETNAME2 configure -dbgbase $_dbgbase
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$_TARGETNAME2 configure -event reset-assert "arc_common_reset $_TARGETNAME2"
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set _coreid [expr $_coreid + 1]
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set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
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arc_hs_init_regs
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# Enable L2 cache support for core 2.
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$_TARGETNAME2 arc has-l2cache true
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# ARC HS38 core 1
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set _TARGETNAME3 $_CHIPNAME.cpu1
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jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1
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target create $_TARGETNAME3 arcv2 -chain-position $_TARGETNAME3
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$_TARGETNAME3 configure -coreid $_coreid
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$_TARGETNAME3 configure -dbgbase $_dbgbase
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$_TARGETNAME3 configure -event reset-assert "arc_common_reset $_TARGETNAME3"
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set _coreid [expr $_coreid + 1]
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set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
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arc_hs_init_regs
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# Enable L2 cache support for core 1.
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$_TARGETNAME3 arc has-l2cache true
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target smp $_CHIPNAME.cpu4 $_CHIPNAME.cpu3 $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
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