SWI: Add SWI pseudo peripheral
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
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@ -12,5 +12,6 @@ src/HW_models/NHW_EGU.c
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src/HW_models/NHW_misc.c
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src/HW_models/NHW_RNG.c
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src/HW_models/NHW_RTC.c
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src/HW_models/NHW_SWI.c
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src/HW_models/NHW_TIMER.c
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src/HW_models/weak_stubs.c
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@ -0,0 +1,18 @@
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/*
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* Copyright (c) 2023, Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* SWI
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* https://infocenter.nordicsemi.com/topic/ps_nrf5340/swi.html?cp=4_0_0_6_32
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*
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* This file just allocates the RAM addresses booked for the SW interrupts
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* This is with all likelihood a model of no-HW
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*/
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#include <stdint.h>
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#include "NHW_config.h"
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int NRF_SWI_regs[NHW_SWI_TOTAL_INST];
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@ -322,6 +322,12 @@
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#define NHW_RTC_HAS_SHORT_COMP_CLEAR 1
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#define NHW_RTC_N_CC {4, 4, 4, 4}
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#define NHW_SWI_TOTAL_INST 4
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#define NHW_SWI_NET0 0
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#define NHW_SWI_NET1 1
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#define NHW_SWI_NET2 2
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#define NHW_SWI_NET3 3
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#define NHW_TIMER_TOTAL_INST 6
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#define NHW_TIMER_APP0 0
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#define NHW_TIMER_APP1 1
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@ -169,14 +169,15 @@ extern NRF_TIMER_Type NRF_TIMER_regs[];
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#define NRF_TIMER1_NS_BASE (&NRF_TIMER_regs[NHW_TIMER_NET1])
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#undef NRF_TIMER2_NS_BASE
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#define NRF_TIMER2_NS_BASE (&NRF_TIMER_regs[NHW_TIMER_NET2])
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extern int NRF_SWI_regs[];
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#undef NRF_SWI0_NS_BASE
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#define NRF_SWI0_NS_BASE NULL
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#define NRF_SWI0_NS_BASE (&NRF_SWI_regs[NHW_SWI_NET0])
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#undef NRF_SWI1_NS_BASE
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#define NRF_SWI1_NS_BASE NULL
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#define NRF_SWI1_NS_BASE (&NRF_SWI_regs[NHW_SWI_NET1])
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#undef NRF_SWI2_NS_BASE
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#define NRF_SWI2_NS_BASE NULL
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#define NRF_SWI2_NS_BASE (&NRF_SWI_regs[NHW_SWI_NET2])
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#undef NRF_SWI3_NS_BASE
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#define NRF_SWI3_NS_BASE NULL
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#define NRF_SWI3_NS_BASE (&NRF_SWI_regs[NHW_SWI_NET3])
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#undef NRF_APPMUTEX_NS_BASE
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#define NRF_APPMUTEX_NS_BASE NULL
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#undef NRF_APPMUTEX_S_BASE
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