Model a nrf52833 instead of a nrf52832

Motivation for the change:

The nrf52833 is for the purpose of these models practically the
same as a 52832, but it includes the HEADER_MASK register in the
AES_CCM module which is needed for proper encrypted BIS support.

Changing the version of the HW we model can cause minor trouble
for users, i.e. require them to change the configuration of their SW,
but at this point is believed most users will desire sooner or
later full BLE ISO support.

Change:

* Changed version we compile as from NRF52832_XXAA to NRF52833_XXAA
* Number of interrupts increased to 47 (32 was too low even for 52832)
* Updated all documentation references to point to 52833 docs
* Updated description of missing features (no new 52833 features
  implemented so far)

******************************************************************
Expect backwards/forward compatibility changes from/to this commit
******************************************************************

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This commit is contained in:
Alberto Escolar Piedras 2023-01-23 17:07:16 +01:00
parent 60ecd4642d
commit 6f8b238a53
22 changed files with 53 additions and 20 deletions

View File

@ -35,7 +35,7 @@ WARNINGS:=-Wall -pedantic
COVERAGE:=
CFLAGS:=${ARCH} ${DEBUG} ${OPT} ${WARNINGS} -MMD -MP -std=c11 \
${INCLUDES} -fdata-sections -ffunction-sections \
-DNRF52832_XXAA
-DNRF52833_XXAA
LDFLAGS:=${ARCH} ${COVERAGE}
CPPFLAGS:=

View File

@ -24,4 +24,4 @@ Current limitations and pending things to do:
Not implemented, and no plans to implement:
* WDT, QDEC, LPCOMP, COMP, PWM, PDM, ACL, NVMC, MWU, SPIM/S, I2S, FPU, USB,
UART, QSPI, GPIO, CRYPTOCELL, UICR
UART, UARTE, QSPI, GPIO, CRYPTOCELL, UICR

View File

@ -1,5 +1,5 @@
**Models of some of the HW present in a NRF52xxx.**<br>
Where relevant differences exist, these models try to align with a NRF52382.
Where relevant differences exist, these models try to align with a NRF52833.
This repo contains both models of the NRF52 HW as well as some replacement nrfx
HAL functions. When used in combination with the real nrfx, these should enable code
@ -23,7 +23,7 @@ export NRFX_BASE=/some_path/nrfx/
See the [nrfx/hal/README.md](../src/nrfx/hal/README.md) for more details.
This models can be used directly with
These models can be used directly with
[Zephyr's nrf52_bsim target](https://docs.zephyrproject.org/latest/boards/posix/nrf52_bsim/doc/index.html).
The NRF_RADIO peripheral model uses [BabbleSim](http://babblesim.github.io)
@ -39,7 +39,7 @@ its BLE stack to function. For more details please see the notes on the source
files for each peripheral model.
These models are based solely on
[the public SOC specifications](https://infocenter.nordicsemi.com/topic/struct_nrf52/struct/nrf52832.html?cp=3_1)
[the public SOC specifications](https://infocenter.nordicsemi.com/topic/struct_nrf52/struct/nrf52833.html)
They have been developed without any other knowledge and probably contain
inacuracies, and defects.

View File

@ -5,7 +5,7 @@
*/
/**
* AR Accelerated address resolver
* http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/aar.html?cp=2_0_0_28#frontpage_aar
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/aar.html?cp=4_1_0_5_1
*/
#include "NRF_AAR.h"
#include <string.h>

View File

@ -6,7 +6,7 @@
/*
* CCM AES CCM mode encryption
* http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/ccm.html?cp=2_0_0_27#topic
* https://infocenter.nordicsemi.com/index.jsp?topic=%2Fps_nrf52833%2Fccm.html&cp=4_1_0_5_3
*
* Notes:
*
@ -27,6 +27,10 @@
* according to their length
*
* 3. TASKS_STOP is not really supported
*
* 4. TASK_RATEOVERRIDE and RATEOVERRIDE are not supported
*
* 5. HEADERMASK is not yet supported
*/
#include "NRF_AES_CCM.h"

View File

@ -16,7 +16,7 @@
/*
* AES electronic codebook mode encryption
* http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/ecb.html?cp=2_0_0_26#concept_vnj_kgy_xr
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/ecb.html?cp=4_1_0_5_5
*/
bs_time_t Timer_ECB = TIME_NEVER; /* Time when the ECB will finish */

View File

@ -14,7 +14,14 @@
/*
* CLOCK Clock control
* http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/clock.html?cp=2_0_0_16#frontpage_clock
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/clock.html?cp=4_1_0_4_3
*
* Notes:
*
* 1. EVENTS_CTSTARTED/STOPPED not supported
*
* 2. The clocks are ready in 1 delta cycle (i.e. almost instantaneously),
* HFXODEBOUNCE and LFXODEBOUNCE are ignored
*/
//Note: We assume the 32.768 KHz clock does not drift relative to the 64MHz one

View File

@ -8,6 +8,7 @@
/*
* This is only a stub of the register interface with no functionality behind
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/egu.html?cp=4_1_0_5_6
*/
NRF_EGU_Type NRF_EGU_regs[6];

View File

@ -8,7 +8,7 @@
/*
* Factory information configuration registers
* http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/ficr.html?cp=2_0_0_11#concept_xb5_mpx_vr
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/ficr.html?cp=4_1_0_3_3
*/
//TOLOW: we start with all registers just as 0. It could be interesting to let people load them from command line

View File

@ -7,6 +7,7 @@
/*
* This is only a stub of the register interface with no functionality behind
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/gpio.html?cp=4_1_0_5_7
*/
NRF_GPIO_Type NRF_P0_regs = {0};

View File

@ -7,6 +7,7 @@
/*
* This is only a stub of the register interface with no functionality behind
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/gpiote.html?cp=4_1_0_5_8
*/
NRF_GPIOTE_Type NRF_GPIOTE_regs = {0};

View File

@ -7,6 +7,7 @@
/*
* This is only a stub of the register interface with no functionality behind
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/nvmc.html?cp=4_1_0_3_2
*/
NRF_NVMC_Type NRF_NVMC_regs = {0};

View File

@ -7,6 +7,7 @@
/*
* This is only a stub of the register interface with no functionality behind
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/power.html?cp=4_1_0_4_2
*/
NRF_POWER_Type NRF_POWER_regs = {0};

View File

@ -20,7 +20,7 @@
/*
* PPI Programmable peripheral interconnect
* http://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.nrf52%2Fdita%2Fnrf52%2Fchips%2Fnrf52840_ps.html&cp=2_0_0
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/ppi.html?cp=4_1_0_5_14
*
*/

View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2017 Oticon A/S
* Copyright (c) 2023 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -22,7 +23,7 @@
/**
* RADIO 2.4 GHz Radio
* http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/radio.html?cp=2_0_0_21#concept_lhd_ygj_4r
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/radio.html?cp=4_1_0_5_17
*
* Note: as of now, only 1&2Mbps BLE packet formats are supported, there is quite many notes around in the code
* where changes would be required to support other formats
@ -45,6 +46,17 @@
*
* Note11: During reception we assume that CRCPOLY and CRCINIT are correct on both sides, and just rely on the phy bit error reporting to save processing time
* On transmission we generate the correct CRC for correctness of the channel dump traces (and Ellisys traces)
*
* Note12: Nothing related to 802.15.4 (including energy detection (ED) and CCA) is implemented
*
* Note13: Nothing related to AoA/AoD features (CTE, DFE) is implemented
*
* Note14: No 52833 new radio state change events (EVENTS_FRAMESTART, EVENTS_EDEND, EVENTS_EDSTOPPED, EVENTS_CCAIDLE, EVENTS_CCABUSY, EVENTS_CCASTOPPED,
* EVENTS_RATEBOOST, EVENTS_TXREADY, EVENTS_RXREADY, EVENTS_MHRMATCH, EVENTS_SYNC,EVENTS_PHYEND & EVENTS_CTEPRESENT) implemented
*
* Note15: PDUSTAT not yet implemented
*
* Note16: No antenna switching
*/
NRF_RADIO_Type NRF_RADIO_regs;

View File

@ -14,7 +14,7 @@
/*
* RNG Random number generator
* http://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.nrf52840.ps%2Frng.html&cp=2_0_0_24&anchor=concept_h35_c1l_cs
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/rng.html?cp=4_1_0_5_18
*
* Very rough model
*/

View File

@ -17,7 +17,7 @@
/*
* RTC Real-time counter
*
* http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/rtc.html?cp=2_0_0_23#concept_rvn_vkj_sr
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/rtc.html?cp=4_1_0_5_19
*/
/* To simplify, so far it is only modeled what the current BLE controller uses

View File

@ -7,6 +7,7 @@
/*
* This is only a stub of the register interface with no functionality behind
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/temp.html?cp=4_1_0_5_25
*/
NRF_TEMP_Type NRF_TEMP_regs = {0};

View File

@ -14,7 +14,7 @@
/*
* TIMER Timer/counter
* http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/timer.html?cp=2_0_0_22#concept_xbd_hqp_sr
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/timer.html?cp=4_1_0_5_27
*/
/**

View File

@ -363,7 +363,7 @@ const char *hw_irq_ctrl_get_name(unsigned int irq)
/* The names are taken from the IRQn_Type in the MDK header.
* with the suffix '_IRQn' removed.
*/
static const char *irqnames_nrf52832[] = {
static const char *irqnames_nrf52833[] = {
[0] = "POWER_CLOCK",
[1] = "RADIO",
[2] = "UARTE0_UART0",
@ -401,10 +401,14 @@ const char *hw_irq_ctrl_get_name(unsigned int irq)
[34] = "RTC2",
[35] = "I2S",
[36] = "FPU",
[37] = "USBD",
[38] = "UARTE1",
[39] = "PWM3",
[40] = "SPIM3",
};
if (irq < sizeof(irqnames_nrf52832)/sizeof(irqnames_nrf52832[0])) {
return irqnames_nrf52832[irq];
if (irq < sizeof(irqnames_nrf52833)/sizeof(irqnames_nrf52833[0])) {
return irqnames_nrf52833[irq];
} else {
return NULL;
}

View File

@ -52,7 +52,7 @@ const char *hw_irq_ctrl_get_name(unsigned int irq);
*/
#define PHONY_HARD_IRQ 0xFFFF
#define NRF_HW_NBR_IRQs 32
#define NRF_HW_NBR_IRQs 47
#ifdef __cplusplus
}

View File

@ -12,7 +12,7 @@
IRQn_Type nrfx_get_irq_number(void const * p_reg){
/*
* Peripheral numbers match interrupt numbers
* See https://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.ps.v1.1/memory.html?cp=3_1_0_7_2#memorymap
* See https://infocenter.nordicsemi.com/index.jsp?topic=%2Fstruct_nrf52%2Fstruct%2Fnrf52833.html
*/
#define IS_PERIPHERAL_REG(p, per, nbr) \