Model a nrf52833 instead of a nrf52832
Motivation for the change: The nrf52833 is for the purpose of these models practically the same as a 52832, but it includes the HEADER_MASK register in the AES_CCM module which is needed for proper encrypted BIS support. Changing the version of the HW we model can cause minor trouble for users, i.e. require them to change the configuration of their SW, but at this point is believed most users will desire sooner or later full BLE ISO support. Change: * Changed version we compile as from NRF52832_XXAA to NRF52833_XXAA * Number of interrupts increased to 47 (32 was too low even for 52832) * Updated all documentation references to point to 52833 docs * Updated description of missing features (no new 52833 features implemented so far) ****************************************************************** Expect backwards/forward compatibility changes from/to this commit ****************************************************************** Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This commit is contained in:
parent
60ecd4642d
commit
6f8b238a53
2
Makefile
2
Makefile
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@ -35,7 +35,7 @@ WARNINGS:=-Wall -pedantic
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COVERAGE:=
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CFLAGS:=${ARCH} ${DEBUG} ${OPT} ${WARNINGS} -MMD -MP -std=c11 \
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${INCLUDES} -fdata-sections -ffunction-sections \
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-DNRF52832_XXAA
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-DNRF52833_XXAA
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LDFLAGS:=${ARCH} ${COVERAGE}
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CPPFLAGS:=
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2
TODO.txt
2
TODO.txt
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@ -24,4 +24,4 @@ Current limitations and pending things to do:
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Not implemented, and no plans to implement:
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* WDT, QDEC, LPCOMP, COMP, PWM, PDM, ACL, NVMC, MWU, SPIM/S, I2S, FPU, USB,
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UART, QSPI, GPIO, CRYPTOCELL, UICR
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UART, UARTE, QSPI, GPIO, CRYPTOCELL, UICR
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@ -1,5 +1,5 @@
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**Models of some of the HW present in a NRF52xxx.**<br>
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Where relevant differences exist, these models try to align with a NRF52382.
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Where relevant differences exist, these models try to align with a NRF52833.
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This repo contains both models of the NRF52 HW as well as some replacement nrfx
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HAL functions. When used in combination with the real nrfx, these should enable code
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@ -23,7 +23,7 @@ export NRFX_BASE=/some_path/nrfx/
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See the [nrfx/hal/README.md](../src/nrfx/hal/README.md) for more details.
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This models can be used directly with
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These models can be used directly with
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[Zephyr's nrf52_bsim target](https://docs.zephyrproject.org/latest/boards/posix/nrf52_bsim/doc/index.html).
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The NRF_RADIO peripheral model uses [BabbleSim](http://babblesim.github.io)
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@ -39,7 +39,7 @@ its BLE stack to function. For more details please see the notes on the source
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files for each peripheral model.
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These models are based solely on
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[the public SOC specifications](https://infocenter.nordicsemi.com/topic/struct_nrf52/struct/nrf52832.html?cp=3_1)
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[the public SOC specifications](https://infocenter.nordicsemi.com/topic/struct_nrf52/struct/nrf52833.html)
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They have been developed without any other knowledge and probably contain
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inacuracies, and defects.
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@ -5,7 +5,7 @@
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*/
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/**
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* AR — Accelerated address resolver
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* http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/aar.html?cp=2_0_0_28#frontpage_aar
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* https://infocenter.nordicsemi.com/topic/ps_nrf52833/aar.html?cp=4_1_0_5_1
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*/
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#include "NRF_AAR.h"
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#include <string.h>
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@ -6,7 +6,7 @@
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/*
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* CCM — AES CCM mode encryption
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* http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/ccm.html?cp=2_0_0_27#topic
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* https://infocenter.nordicsemi.com/index.jsp?topic=%2Fps_nrf52833%2Fccm.html&cp=4_1_0_5_3
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*
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* Notes:
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*
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@ -27,6 +27,10 @@
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* according to their length
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*
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* 3. TASKS_STOP is not really supported
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*
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* 4. TASK_RATEOVERRIDE and RATEOVERRIDE are not supported
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*
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* 5. HEADERMASK is not yet supported
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*/
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#include "NRF_AES_CCM.h"
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@ -16,7 +16,7 @@
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/*
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* AES electronic codebook mode encryption
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* http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/ecb.html?cp=2_0_0_26#concept_vnj_kgy_xr
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* https://infocenter.nordicsemi.com/topic/ps_nrf52833/ecb.html?cp=4_1_0_5_5
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*/
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bs_time_t Timer_ECB = TIME_NEVER; /* Time when the ECB will finish */
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@ -14,7 +14,14 @@
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/*
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* CLOCK — Clock control
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* http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/clock.html?cp=2_0_0_16#frontpage_clock
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* https://infocenter.nordicsemi.com/topic/ps_nrf52833/clock.html?cp=4_1_0_4_3
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*
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* Notes:
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*
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* 1. EVENTS_CTSTARTED/STOPPED not supported
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*
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* 2. The clocks are ready in 1 delta cycle (i.e. almost instantaneously),
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* HFXODEBOUNCE and LFXODEBOUNCE are ignored
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*/
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//Note: We assume the 32.768 KHz clock does not drift relative to the 64MHz one
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@ -8,6 +8,7 @@
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/*
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* This is only a stub of the register interface with no functionality behind
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* https://infocenter.nordicsemi.com/topic/ps_nrf52833/egu.html?cp=4_1_0_5_6
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*/
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NRF_EGU_Type NRF_EGU_regs[6];
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@ -8,7 +8,7 @@
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/*
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* Factory information configuration registers
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* http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/ficr.html?cp=2_0_0_11#concept_xb5_mpx_vr
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* https://infocenter.nordicsemi.com/topic/ps_nrf52833/ficr.html?cp=4_1_0_3_3
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*/
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//TOLOW: we start with all registers just as 0. It could be interesting to let people load them from command line
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@ -7,6 +7,7 @@
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/*
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* This is only a stub of the register interface with no functionality behind
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* https://infocenter.nordicsemi.com/topic/ps_nrf52833/gpio.html?cp=4_1_0_5_7
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*/
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NRF_GPIO_Type NRF_P0_regs = {0};
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@ -7,6 +7,7 @@
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/*
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* This is only a stub of the register interface with no functionality behind
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* https://infocenter.nordicsemi.com/topic/ps_nrf52833/gpiote.html?cp=4_1_0_5_8
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*/
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NRF_GPIOTE_Type NRF_GPIOTE_regs = {0};
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/*
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* This is only a stub of the register interface with no functionality behind
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* https://infocenter.nordicsemi.com/topic/ps_nrf52833/nvmc.html?cp=4_1_0_3_2
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*/
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NRF_NVMC_Type NRF_NVMC_regs = {0};
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/*
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* This is only a stub of the register interface with no functionality behind
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* https://infocenter.nordicsemi.com/topic/ps_nrf52833/power.html?cp=4_1_0_4_2
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*/
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NRF_POWER_Type NRF_POWER_regs = {0};
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/*
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* PPI — Programmable peripheral interconnect
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* http://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.nrf52%2Fdita%2Fnrf52%2Fchips%2Fnrf52840_ps.html&cp=2_0_0
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* https://infocenter.nordicsemi.com/topic/ps_nrf52833/ppi.html?cp=4_1_0_5_14
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*
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*/
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2017 Oticon A/S
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* Copyright (c) 2023 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* RADIO — 2.4 GHz Radio
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* http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/radio.html?cp=2_0_0_21#concept_lhd_ygj_4r
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* https://infocenter.nordicsemi.com/topic/ps_nrf52833/radio.html?cp=4_1_0_5_17
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*
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* Note: as of now, only 1&2Mbps BLE packet formats are supported, there is quite many notes around in the code
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* where changes would be required to support other formats
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*
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* Note11: During reception we assume that CRCPOLY and CRCINIT are correct on both sides, and just rely on the phy bit error reporting to save processing time
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* On transmission we generate the correct CRC for correctness of the channel dump traces (and Ellisys traces)
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*
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* Note12: Nothing related to 802.15.4 (including energy detection (ED) and CCA) is implemented
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*
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* Note13: Nothing related to AoA/AoD features (CTE, DFE) is implemented
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*
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* Note14: No 52833 new radio state change events (EVENTS_FRAMESTART, EVENTS_EDEND, EVENTS_EDSTOPPED, EVENTS_CCAIDLE, EVENTS_CCABUSY, EVENTS_CCASTOPPED,
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* EVENTS_RATEBOOST, EVENTS_TXREADY, EVENTS_RXREADY, EVENTS_MHRMATCH, EVENTS_SYNC,EVENTS_PHYEND & EVENTS_CTEPRESENT) implemented
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*
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* Note15: PDUSTAT not yet implemented
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*
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* Note16: No antenna switching
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*/
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NRF_RADIO_Type NRF_RADIO_regs;
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/*
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* RNG — Random number generator
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* http://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.nrf52840.ps%2Frng.html&cp=2_0_0_24&anchor=concept_h35_c1l_cs
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* https://infocenter.nordicsemi.com/topic/ps_nrf52833/rng.html?cp=4_1_0_5_18
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*
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* Very rough model
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*/
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/*
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* RTC — Real-time counter
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*
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* http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/rtc.html?cp=2_0_0_23#concept_rvn_vkj_sr
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* https://infocenter.nordicsemi.com/topic/ps_nrf52833/rtc.html?cp=4_1_0_5_19
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*/
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/* To simplify, so far it is only modeled what the current BLE controller uses
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/*
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* This is only a stub of the register interface with no functionality behind
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* https://infocenter.nordicsemi.com/topic/ps_nrf52833/temp.html?cp=4_1_0_5_25
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*/
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NRF_TEMP_Type NRF_TEMP_regs = {0};
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/*
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* TIMER — Timer/counter
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* http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/timer.html?cp=2_0_0_22#concept_xbd_hqp_sr
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* https://infocenter.nordicsemi.com/topic/ps_nrf52833/timer.html?cp=4_1_0_5_27
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*/
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/**
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/* The names are taken from the IRQn_Type in the MDK header.
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* with the suffix '_IRQn' removed.
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*/
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static const char *irqnames_nrf52832[] = {
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static const char *irqnames_nrf52833[] = {
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[0] = "POWER_CLOCK",
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[1] = "RADIO",
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[2] = "UARTE0_UART0",
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[34] = "RTC2",
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[35] = "I2S",
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[36] = "FPU",
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[37] = "USBD",
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[38] = "UARTE1",
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[39] = "PWM3",
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[40] = "SPIM3",
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};
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if (irq < sizeof(irqnames_nrf52832)/sizeof(irqnames_nrf52832[0])) {
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return irqnames_nrf52832[irq];
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if (irq < sizeof(irqnames_nrf52833)/sizeof(irqnames_nrf52833[0])) {
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return irqnames_nrf52833[irq];
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} else {
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return NULL;
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}
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*/
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#define PHONY_HARD_IRQ 0xFFFF
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#define NRF_HW_NBR_IRQs 32
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#define NRF_HW_NBR_IRQs 47
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#ifdef __cplusplus
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}
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IRQn_Type nrfx_get_irq_number(void const * p_reg){
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/*
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* Peripheral numbers match interrupt numbers
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* See https://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.ps.v1.1/memory.html?cp=3_1_0_7_2#memorymap
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* See https://infocenter.nordicsemi.com/index.jsp?topic=%2Fstruct_nrf52%2Fstruct%2Fnrf52833.html
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*/
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#define IS_PERIPHERAL_REG(p, per, nbr) \
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