lib: fix update libmetal to SHA f3f365d3f4f1
The "85fb139 (Refactor equal processor headers into new generic ones) commit had deleted some deprecated files, which also need to be removed from the Zephyr libmetal module for alignment. Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
This commit is contained in:
Arnaud Pouliquen
Johan Hedberg
parent
55aac79513
commit
cebd92d15c
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@ -1,3 +0,0 @@
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collect (PROJECT_LIB_HEADERS atomic.h)
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collect (PROJECT_LIB_HEADERS cpu.h)
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@ -1,15 +0,0 @@
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/*
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* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* @file gcc/atomic.h
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* @brief GCC specific atomic primitives for libmetal.
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*/
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#ifndef __METAL_AARCH64_ATOMIC__H__
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#define __METAL_AARCH64_ATOMIC__H__
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#endif /* __METAL_ARM_ATOMIC__H__ */
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@ -1,3 +0,0 @@
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collect (PROJECT_LIB_HEADERS atomic.h)
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collect (PROJECT_LIB_HEADERS cpu.h)
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@ -1,15 +0,0 @@
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/*
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* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* @file arm/atomic.h
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* @brief Arm specific atomic primitives for libmetal.
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*/
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#ifndef __METAL_ARM_ATOMIC__H__
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#define __METAL_ARM_ATOMIC__H__
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#endif /* __METAL_ARM_ATOMIC__H__ */
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@ -1,17 +0,0 @@
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/*
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* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* @file cpu.h
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* @brief CPU specific primitives
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*/
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#ifndef __METAL_ARM_CPU__H__
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#define __METAL_ARM_CPU__H__
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#define metal_cpu_yield()
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#endif /* __METAL_ARM_CPU__H__ */
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@ -1,2 +0,0 @@
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collect (PROJECT_LIB_HEADERS cpu.h)
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@ -1,2 +0,0 @@
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collect (PROJECT_LIB_HEADERS cpu.h)
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@ -1,17 +0,0 @@
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/*
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* Copyright (c) 2018, Pinecone Inc. and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* @file cpu.h
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* @brief CPU specific primitives
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*/
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#ifndef __METAL_CSKY_CPU__H__
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#define __METAL_CSKY_CPU__H__
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#define metal_cpu_yield()
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#endif /* __METAL_CSKY_CPU__H__ */
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@ -1,2 +0,0 @@
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collect (PROJECT_LIB_HEADERS atomic.h)
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collect (PROJECT_LIB_HEADERS cpu.h)
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@ -1,15 +0,0 @@
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/*
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* Copyright (c) 2023 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* @file hosted/atomic.h
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* @brief Hosted environment atomic primitives for libmetal.
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*/
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#ifndef __METAL_HOSTED_ATOMIC__H__
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#define __METAL_HOSTED_ATOMIC__H__
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#endif /* __METAL_HOSTED_ATOMIC__H__ */
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@ -1,3 +0,0 @@
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collect (PROJECT_LIB_HEADERS atomic.h)
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collect (PROJECT_LIB_HEADERS cpu.h)
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@ -1,15 +0,0 @@
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/*
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* Copyright (c) 2017, Xilinx Inc. and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* @file microblaze/atomic.h
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* @brief Microblaze specific atomic primitives for libmetal
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*/
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#ifndef __METAL_MICROBLAZE_ATOMIC__H__
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#define __METAL_MICROBLAZE_ATOMIC__H__
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#endif /* __METAL_MICROBLAZE_ATOMIC__H__ */
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@ -1,20 +0,0 @@
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/*
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* Copyright (c) 2017, Xilinx Inc. and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* @file cpu.h
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* @brief CPU specific primitives on microblaze platform.
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*/
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#ifndef __METAL_MICROBLAZE__H__
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#define __METAL_MICROBLAZE__H__
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#include <stdint.h>
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#include <metal/atomic.h>
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#define metal_cpu_yield()
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#endif /* __METAL_MICROBLAZE__H__ */
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@ -1,2 +0,0 @@
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collect (PROJECT_LIB_HEADERS cpu.h)
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@ -1,17 +0,0 @@
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/*
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* Copyright (c) 2018, Pinecone Inc. and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* @file cpu.h
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* @brief CPU specific primitives
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*/
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#ifndef __METAL_RISCV_CPU__H__
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#define __METAL_RISCV_CPU__H__
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#define metal_cpu_yield()
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#endif /* __METAL_RISCV_CPU__H__ */
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@ -1,3 +0,0 @@
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collect (PROJECT_LIB_HEADERS atomic.h)
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collect (PROJECT_LIB_HEADERS cpu.h)
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@ -1,16 +0,0 @@
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/*
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* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* @file gcc/atomic.h
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* @brief GCC specific atomic primitives for libmetal.
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*/
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#ifndef __METAL_X86_ATOMIC__H__
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#define __METAL_X86_ATOMIC__H__
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#endif /* __METAL_X86_ATOMIC__H__ */
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@ -1,3 +0,0 @@
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collect (PROJECT_LIB_HEADERS atomic.h)
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collect (PROJECT_LIB_HEADERS cpu.h)
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@ -1,16 +0,0 @@
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/*
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* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* @file gcc/atomic.h
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* @brief GCC specific atomic primitives for libmetal.
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*/
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#ifndef __METAL_X86_64_ATOMIC__H__
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#define __METAL_X86_64_ATOMIC__H__
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#endif /* __METAL_X86_64_ATOMIC__H__ */
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@ -1,2 +0,0 @@
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collect (PROJECT_LIB_HEADERS atomic.h)
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collect (PROJECT_LIB_HEADERS cpu.h)
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@ -1,15 +0,0 @@
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/*
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* Copyright (c) 2021, Xiaomi Inc. and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* @file xtensa/atomic.h
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* @brief Xtensa specific atomic primitives for libmetal.
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*/
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#ifndef __METAL_XTENSA_ATOMIC__H__
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#define __METAL_XTENSA_ATOMIC__H__
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#endif /* __METAL_XTENSA_ATOMIC__H__ */
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@ -1,5 +0,0 @@
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collect (PROJECT_LIB_HEADERS sys.h)
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collect (PROJECT_LIB_SOURCES irq.c)
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# vim: expandtab:ts=2:sw=2:smartindent
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@ -1,72 +0,0 @@
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/*
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* Copyright (c) 2016 - 2017, Xilinx Inc. and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* @file generic/xlnx_common/irq.c
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* @brief generic libmetal Xilinx irq controller definitions.
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*/
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#include <metal/errno.h>
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#include <metal/irq_controller.h>
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#include <metal/sys.h>
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#include <metal/log.h>
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#include <metal/mutex.h>
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#include <metal/list.h>
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#include <metal/utilities.h>
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#include <metal/alloc.h>
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#define MAX_IRQS XLNX_MAXIRQS
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static struct metal_irq irqs[MAX_IRQS]; /**< Linux IRQs array */
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static void metal_xlnx_irq_set_enable(struct metal_irq_controller *irq_cntr,
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int irq, unsigned int state)
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{
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if (irq < irq_cntr->irq_base ||
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irq >= irq_cntr->irq_base + irq_cntr->irq_num) {
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metal_log(METAL_LOG_ERROR, "%s: invalid irq %d\n",
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__func__, irq);
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return;
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} else if (state == METAL_IRQ_ENABLE) {
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sys_irq_enable((unsigned int)irq);
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} else {
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sys_irq_disable((unsigned int)irq);
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}
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}
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/**< Xilinx common platform IRQ controller */
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static METAL_IRQ_CONTROLLER_DECLARE(xlnx_irq_cntr,
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0, MAX_IRQS,
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NULL,
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metal_xlnx_irq_set_enable, NULL,
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irqs);
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/**
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* @brief default handler
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*/
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void metal_xlnx_irq_isr(void *arg)
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{
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unsigned int vector;
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vector = (uintptr_t)arg;
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if (vector >= MAX_IRQS) {
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return;
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}
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(void)metal_irq_handle(&irqs[vector], (int)vector);
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}
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int metal_xlnx_irq_init(void)
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{
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int ret;
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ret = metal_irq_register_controller(&xlnx_irq_cntr);
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if (ret < 0) {
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metal_log(METAL_LOG_ERROR, "%s: register irq controller failed.\n",
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__func__);
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return ret;
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}
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return 0;
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}
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/*
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* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* @file freertos/xlnx_common/sys.h
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* @brief freertos Xilinx common system primitives for libmetal.
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*/
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#ifndef __METAL_FREERTOS_SYS__H__
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#error "Include metal/sys.h instead of metal/freertos/@PROJECT_MACHINE@/sys.h"
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#endif
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#ifndef __METAL_FREERTOS_XLNX_COMMON_SYS__H__
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#define __METAL_FREERTOS_XLNX_COMMON_SYS__H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief metal_xlnx_irq_isr
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*
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* Xilinx interrupt ISR can be registered to the Xilinx embeddedsw
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* IRQ controller driver.
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*
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* @param[in] arg input argument, interrupt vector id.
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*/
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void metal_xlnx_irq_isr(void *arg);
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/**
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* @brief metal_xlnx_irq_int
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*
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* Xilinx interrupt controller initialization. It will initialize
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* the metal Xilinx IRQ controller data structure.
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*
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* @return 0 for success, or negative value for failure
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*/
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int metal_xlnx_irq_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __METAL_FREERTOS_XLNX_COMMON_SYS__H__ */
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@ -1,6 +0,0 @@
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collect (PROJECT_LIB_HEADERS sys.h)
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collect (PROJECT_LIB_SOURCES sys.c)
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add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common)
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# vim: expandtab:ts=2:sw=2:smartindent
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@ -1,99 +0,0 @@
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/*
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* Copyright (c) 2014, Mentor Graphics Corporation
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* Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* @file freertos/zynq7/sys.c
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* @brief machine specific system primitives implementation.
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*/
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#include <metal/compiler.h>
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#include <metal/io.h>
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#include <metal/sys.h>
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#include <stdint.h>
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#include "xil_cache.h"
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#include "xil_exception.h"
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#include "xil_mmu.h"
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#include "xscugic.h"
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/* Translation table is 16K in size */
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#define ARM_AR_MEM_TTB_SIZE (16*1024)
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/* Each TTB descriptor covers a 1MB region */
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#define ARM_AR_MEM_TTB_SECT_SIZE (1024*1024)
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/* Mask off lower bits of addr */
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#define ARM_AR_MEM_TTB_SECT_SIZE_MASK (~(ARM_AR_MEM_TTB_SECT_SIZE-1UL))
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void sys_irq_restore_enable(unsigned int flags)
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{
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Xil_ExceptionEnableMask(~flags);
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}
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unsigned int sys_irq_save_disable(void)
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{
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unsigned int state = mfcpsr() & XIL_EXCEPTION_ALL;
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if (state != XIL_EXCEPTION_ALL) {
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Xil_ExceptionDisableMask(XIL_EXCEPTION_ALL);
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}
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return state;
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}
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void metal_machine_cache_flush(void *addr, unsigned int len)
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{
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if (!addr && !len)
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Xil_DCacheFlush();
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else
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Xil_DCacheFlushRange((intptr_t)addr, len);
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}
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void metal_machine_cache_invalidate(void *addr, unsigned int len)
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{
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if (!addr && !len)
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Xil_DCacheInvalidate();
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else
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Xil_DCacheInvalidateRange((intptr_t)addr, len);
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}
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/**
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* @brief poll function until some event happens
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*/
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void metal_weak metal_generic_default_poll(void)
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{
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metal_asm volatile("wfi");
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}
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void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
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size_t size, unsigned int flags)
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{
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unsigned int section_offset;
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unsigned int ttb_addr;
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if (!flags)
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return va;
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/*
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* Ensure the virtual and physical addresses are aligned on a
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* section boundary
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*/
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pa &= ARM_AR_MEM_TTB_SECT_SIZE_MASK;
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/*
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* Loop through entire region of memory (one MMU section at a time).
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* Each section requires a TTB entry.
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||||
*/
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for (section_offset = 0; section_offset < size;
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section_offset += ARM_AR_MEM_TTB_SECT_SIZE) {
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/* Calculate translation table entry for this memory section */
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ttb_addr = (pa + section_offset);
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/* Write translation table entry value to entry address */
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Xil_SetTlbAttributes(ttb_addr, flags);
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}
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return va;
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}
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|
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@ -1,46 +0,0 @@
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/*
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* Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
|
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*
|
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* SPDX-License-Identifier: BSD-3-Clause
|
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*/
|
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|
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/*
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* @file freertos/zynq7/sys.h
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* @brief freertos zynq7 system primitives for libmetal.
|
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*/
|
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#ifndef __METAL_FREERTOS_SYS__H__
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#error "Include metal/sys.h instead of metal/freertos/@PROJECT_MACHINE@/sys.h"
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#endif
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#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/sys.h>
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#include "xscugic.h"
|
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#ifndef __METAL_FREERTOS_ZYNQ7_SYS__H__
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#define __METAL_FREERTOS_ZYNQ7_SYS__H__
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#ifdef __cplusplus
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extern "C" {
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#endif
|
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#ifdef METAL_INTERNAL
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#define XLNX_MAXIRQS XSCUGIC_MAX_NUM_INTR_INPUTS
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|
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static inline void sys_irq_enable(unsigned int vector)
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||||
{
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XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
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}
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static inline void sys_irq_disable(unsigned int vector)
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||||
{
|
||||
XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
|
||||
}
|
||||
|
||||
#endif /* METAL_INTERNAL */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __METAL_FREERTOS_ZYNQ7_SYS__H__ */
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
collect (PROJECT_LIB_HEADERS sys.h)
|
||||
|
||||
collect (PROJECT_LIB_SOURCES sys.c)
|
||||
|
||||
add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common)
|
||||
# vim: expandtab:ts=2:sw=2:smartindent
|
||||
|
|
@ -1,105 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2017, Xilinx Inc. and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file freertos/zynqmp_a53/sys.c
|
||||
* @brief machine specific system primitives implementation.
|
||||
*/
|
||||
|
||||
#include <metal/compiler.h>
|
||||
#include <metal/io.h>
|
||||
#include <metal/sys.h>
|
||||
#include <stdint.h>
|
||||
#include "xil_cache.h"
|
||||
#include "xil_exception.h"
|
||||
#include "xil_mmu.h"
|
||||
#include "xreg_cortexa53.h"
|
||||
#include "xscugic.h"
|
||||
|
||||
#define MB (1024 * 1024UL)
|
||||
#define GB (1024 * 1024 * 1024UL)
|
||||
|
||||
void sys_irq_restore_enable(unsigned int flags)
|
||||
{
|
||||
Xil_ExceptionEnableMask(~flags);
|
||||
}
|
||||
|
||||
unsigned int sys_irq_save_disable(void)
|
||||
{
|
||||
unsigned int state = mfcpsr() & XIL_EXCEPTION_ALL;
|
||||
|
||||
if (state != XIL_EXCEPTION_ALL) {
|
||||
Xil_ExceptionDisableMask(XIL_EXCEPTION_ALL);
|
||||
}
|
||||
return state;
|
||||
}
|
||||
|
||||
void metal_machine_cache_flush(void *addr, unsigned int len)
|
||||
{
|
||||
if (!addr && !len)
|
||||
Xil_DCacheFlush();
|
||||
else
|
||||
Xil_DCacheFlushRange((intptr_t)addr, len);
|
||||
}
|
||||
|
||||
void metal_machine_cache_invalidate(void *addr, unsigned int len)
|
||||
{
|
||||
if (!addr && !len)
|
||||
Xil_DCacheInvalidate();
|
||||
else
|
||||
Xil_DCacheInvalidateRange((intptr_t)addr, len);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief poll function until some event happens
|
||||
*/
|
||||
void metal_weak metal_generic_default_poll(void)
|
||||
{
|
||||
metal_asm volatile("wfi");
|
||||
}
|
||||
|
||||
void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
|
||||
size_t size, unsigned int flags)
|
||||
{
|
||||
unsigned long section_offset;
|
||||
unsigned long ttb_addr;
|
||||
#if defined(__aarch64__)
|
||||
unsigned long ttb_size = (pa < 4*GB) ? 2*MB : 1*GB;
|
||||
#else
|
||||
unsigned long ttb_size = 1*MB;
|
||||
#endif
|
||||
|
||||
if (!flags)
|
||||
return va;
|
||||
|
||||
/* Ensure alignment on a section boundary */
|
||||
pa &= ~(ttb_size-1UL);
|
||||
|
||||
/*
|
||||
* Loop through entire region of memory (one MMU section at a time).
|
||||
* Each section requires a TTB entry.
|
||||
*/
|
||||
for (section_offset = 0; section_offset < size; ) {
|
||||
/* Calculate translation table entry for this memory section */
|
||||
ttb_addr = (pa + section_offset);
|
||||
|
||||
/* Write translation table entry value to entry address */
|
||||
Xil_SetTlbAttributes(ttb_addr, flags);
|
||||
|
||||
#if defined(__aarch64__)
|
||||
/*
|
||||
* recalculate if we started below 4GB and going above in
|
||||
* 64bit mode
|
||||
*/
|
||||
if (ttb_addr >= 4*GB) {
|
||||
ttb_size = 1*GB;
|
||||
}
|
||||
#endif
|
||||
section_offset += ttb_size;
|
||||
}
|
||||
|
||||
return va;
|
||||
}
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2017, Xilinx Inc. and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file freertos/zynqmp_a53/sys.h
|
||||
* @brief freertos zynqmp_a53 system primitives for libmetal.
|
||||
*/
|
||||
|
||||
#ifndef __METAL_FREERTOS_SYS__H__
|
||||
#error "Include metal/sys.h instead of metal/freertos/@PROJECT_MACHINE@/sys.h"
|
||||
#endif
|
||||
|
||||
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/sys.h>
|
||||
#include "xscugic.h"
|
||||
|
||||
#ifndef __METAL_FREERTOS_ZYNQMP_A53_SYS__H__
|
||||
#define __METAL_FREERTOS_ZYNQMP_A53_SYS__H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef METAL_INTERNAL
|
||||
|
||||
#define XLNX_MAXIRQS XSCUGIC_MAX_NUM_INTR_INPUTS
|
||||
|
||||
static inline void sys_irq_enable(unsigned int vector)
|
||||
{
|
||||
XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
|
||||
}
|
||||
|
||||
static inline void sys_irq_disable(unsigned int vector)
|
||||
{
|
||||
XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
|
||||
}
|
||||
|
||||
#endif /* METAL_INTERNAL */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __METAL_FREERTOS_ZYNQMP_A53_SYS__H__ */
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
collect (PROJECT_LIB_HEADERS sys.h)
|
||||
|
||||
collect (PROJECT_LIB_SOURCES sys.c)
|
||||
|
||||
add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common)
|
||||
# vim: expandtab:ts=2:sw=2:smartindent
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
|
||||
* Copyright (C) 2022, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file freertos/zynqmp_r5/sys.c
|
||||
* @brief machine specific system primitives implementation.
|
||||
*/
|
||||
|
||||
#include <metal/compiler.h>
|
||||
#include <metal/io.h>
|
||||
#include <metal/sys.h>
|
||||
#include <stdint.h>
|
||||
#include "xil_cache.h"
|
||||
#include "xil_exception.h"
|
||||
#include "xil_mmu.h"
|
||||
#include "xil_mpu.h"
|
||||
#include "xreg_cortexr5.h"
|
||||
#include "xscugic.h"
|
||||
|
||||
void sys_irq_restore_enable(unsigned int flags)
|
||||
{
|
||||
Xil_ExceptionEnableMask(~flags);
|
||||
}
|
||||
|
||||
unsigned int sys_irq_save_disable(void)
|
||||
{
|
||||
unsigned int state = mfcpsr() & XIL_EXCEPTION_ALL;
|
||||
|
||||
if (state != XIL_EXCEPTION_ALL) {
|
||||
Xil_ExceptionDisableMask(XIL_EXCEPTION_ALL);
|
||||
}
|
||||
return state;
|
||||
}
|
||||
|
||||
void metal_machine_cache_flush(void *addr, unsigned int len)
|
||||
{
|
||||
if (!addr && !len)
|
||||
Xil_DCacheFlush();
|
||||
else
|
||||
Xil_DCacheFlushRange((intptr_t)addr, len);
|
||||
}
|
||||
|
||||
void metal_machine_cache_invalidate(void *addr, unsigned int len)
|
||||
{
|
||||
if (!addr && !len)
|
||||
Xil_DCacheInvalidate();
|
||||
else
|
||||
Xil_DCacheInvalidateRange((intptr_t)addr, len);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief poll function until some event happens
|
||||
*/
|
||||
void metal_weak metal_generic_default_poll(void)
|
||||
{
|
||||
metal_asm volatile("wfi");
|
||||
}
|
||||
|
||||
/**
|
||||
* The code moved to cortexr5/xil_mpu.c:Xil_MemMap()
|
||||
* NULL in pa masks possible Xil_MemMap() errors.
|
||||
*/
|
||||
void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
|
||||
size_t size, unsigned int flags)
|
||||
{
|
||||
void *__attribute__((unused)) physaddr;
|
||||
|
||||
physaddr = Xil_MemMap(pa, size, flags);
|
||||
metal_assert(physaddr == (void *)pa);
|
||||
return va;
|
||||
}
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file freertos/zynqmp_r5/sys.h
|
||||
* @brief freertos zynqmp_r5 system primitives for libmetal.
|
||||
*/
|
||||
|
||||
#ifndef __METAL_FREERTOS_SYS__H__
|
||||
#error "Include metal/sys.h instead of metal/freertos/@PROJECT_MACHINE@/sys.h"
|
||||
#endif
|
||||
|
||||
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/sys.h>
|
||||
#include "xscugic.h"
|
||||
|
||||
#ifndef __METAL_FREERTOS_ZYNQMP_R5_SYS__H__
|
||||
#define __METAL_FREERTOS_ZYNQMP_R5_SYS__H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef METAL_INTERNAL
|
||||
|
||||
#define XLNX_MAXIRQS XSCUGIC_MAX_NUM_INTR_INPUTS
|
||||
|
||||
static inline void sys_irq_enable(unsigned int vector)
|
||||
{
|
||||
XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
|
||||
}
|
||||
|
||||
static inline void sys_irq_disable(unsigned int vector)
|
||||
{
|
||||
XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
|
||||
}
|
||||
|
||||
#endif /* METAL_INTERNAL */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __METAL_FREERTOS_ZYNQMP_R5_SYS__H__ */
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
collect (PROJECT_LIB_HEADERS sys.h)
|
||||
|
||||
collect (PROJECT_LIB_SOURCES sys.c)
|
||||
|
||||
check_include_files(xintc.h HAS_XINTC)
|
||||
if (HAS_XINTC)
|
||||
add_definitions(-DHAS_XINTC)
|
||||
endif(HAS_XINTC)
|
||||
|
||||
add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common)
|
||||
# vim: expandtab:ts=2:sw=2:smartindent
|
||||
|
|
@ -1,148 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2017, Xilinx Inc. and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file generic/microblaze_generic/sys.c
|
||||
* @brief machine specific system primitives implementation.
|
||||
*/
|
||||
|
||||
#include <metal/assert.h>
|
||||
#include <metal/io.h>
|
||||
#include <metal/sys.h>
|
||||
#include <stdint.h>
|
||||
#include <xil_cache.h>
|
||||
#include <xil_exception.h>
|
||||
#ifdef HAS_XINTC
|
||||
#include <xintc.h>
|
||||
#include <xparameters.h>
|
||||
#endif /* HAS_XINTC */
|
||||
|
||||
#define MSR_IE 0x2UL /* MicroBlaze status register interrupt enable mask */
|
||||
|
||||
#if (XPAR_MICROBLAZE_USE_MSR_INSTR != 0)
|
||||
unsigned int sys_irq_save_disable(void)
|
||||
{
|
||||
unsigned int state;
|
||||
|
||||
metal_asm volatile(" mfs %0, rmsr\n"
|
||||
" msrclr r0, %1\n"
|
||||
: "=r"(state)
|
||||
: "i"(MSR_IE)
|
||||
: "memory");
|
||||
|
||||
return state &= MSR_IE;
|
||||
}
|
||||
|
||||
void sys_irq_restore_enable(unsigned int flags)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
if (flags)
|
||||
metal_asm volatile(" msrset %0, %1\n"
|
||||
: "=r"(tmp)
|
||||
: "i"(MSR_IE)
|
||||
: "memory");
|
||||
}
|
||||
|
||||
#else /* XPAR_MICROBLAZE_USE_MSR_INSTR == 0 */
|
||||
unsigned int sys_irq_save_disable(void)
|
||||
{
|
||||
unsigned int tmp, state;
|
||||
|
||||
metal_asm volatile (" mfs %0, rmsr\n"
|
||||
" andi %1, %0, %2\n"
|
||||
" mts rmsr, %1\n"
|
||||
: "=r"(state), "=r"(tmp)
|
||||
: "i"(~MSR_IE)
|
||||
: "memory");
|
||||
|
||||
return state &= MSR_IE;
|
||||
}
|
||||
|
||||
void sys_irq_restore_enable(unsigned int flags)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
if (flags)
|
||||
metal_asm volatile(" mfs %0, rmsr\n"
|
||||
" or %0, %0, %1\n"
|
||||
" mts rmsr, %0\n"
|
||||
: "=r"(tmp)
|
||||
: "r"(flags)
|
||||
: "memory");
|
||||
}
|
||||
#endif /* XPAR_MICROBLAZE_USE_MSR_INSTR */
|
||||
|
||||
static void sys_irq_change(unsigned int vector, int is_enable)
|
||||
{
|
||||
#ifdef HAS_XINTC
|
||||
XIntc_Config *cfgptr;
|
||||
unsigned int ier;
|
||||
unsigned int mask;
|
||||
|
||||
mask = 1 >> ((vector%32)-1); /* set bit corresponding to interrupt */
|
||||
mask = is_enable ? mask : ~mask; /* if disable then turn off bit */
|
||||
|
||||
cfgptr = XIntc_LookupConfig(vector/32);
|
||||
Xil_AssertVoid(cfgptr != NULL);
|
||||
Xil_AssertVoid(vector < XPAR_INTC_MAX_NUM_INTR_INPUTS);
|
||||
|
||||
ier = XIntc_In32(cfgptr->BaseAddress + XIN_IER_OFFSET);
|
||||
|
||||
XIntc_Out32(cfgptr->BaseAddress + XIN_IER_OFFSET,
|
||||
(ier | mask));
|
||||
#else
|
||||
(void)vector;
|
||||
(void)is_enable;
|
||||
metal_assert(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void metal_weak sys_irq_enable(unsigned int vector)
|
||||
{
|
||||
sys_irq_change(vector, 1);
|
||||
}
|
||||
|
||||
void metal_weak sys_irq_disable(unsigned int vector)
|
||||
{
|
||||
sys_irq_change(vector, 0);
|
||||
}
|
||||
|
||||
|
||||
void metal_machine_cache_flush(void *addr, unsigned int len)
|
||||
{
|
||||
if (!addr && !len) {
|
||||
Xil_DCacheFlush();
|
||||
} else{
|
||||
Xil_DCacheFlushRange((intptr_t)addr, len);
|
||||
}
|
||||
}
|
||||
|
||||
void metal_machine_cache_invalidate(void *addr, unsigned int len)
|
||||
{
|
||||
if (!addr && !len) {
|
||||
Xil_DCacheInvalidate();
|
||||
} else {
|
||||
Xil_DCacheInvalidateRange((intptr_t)addr, len);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief make microblaze wait
|
||||
*/
|
||||
void metal_weak metal_generic_default_poll(void)
|
||||
{
|
||||
metal_asm volatile("nop");
|
||||
}
|
||||
|
||||
void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
|
||||
size_t size, unsigned int flags)
|
||||
{
|
||||
(void)pa;
|
||||
(void)size;
|
||||
(void)flags;
|
||||
return va;
|
||||
}
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2017, Xilinx Inc. and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file generic/microblaze_generic/sys.h
|
||||
* @brief generic microblaze system primitives for libmetal.
|
||||
*/
|
||||
|
||||
#ifndef __METAL_GENERIC_SYS__H__
|
||||
#error "Include metal/sys.h instead of metal/generic/@PROJECT_MACHINE@/sys.h"
|
||||
#endif
|
||||
|
||||
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/sys.h>
|
||||
|
||||
#ifndef __METAL_GENERIC_MICROBLAZE_SYS__H__
|
||||
#define __METAL_GENERIC_MICROBLAZE_SYS__H__
|
||||
|
||||
#include <metal/compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef METAL_INTERNAL
|
||||
|
||||
#ifndef XLNX_MAXIRQS
|
||||
#define XLNX_MAXIRQS 32
|
||||
#endif
|
||||
|
||||
void metal_weak sys_irq_enable(unsigned int vector);
|
||||
|
||||
void metal_weak sys_irq_disable(unsigned int vector);
|
||||
|
||||
#endif /* METAL_INTERNAL */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __METAL_GENERIC_MICROBLAZE_SYS__H__ */
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
collect (PROJECT_LIB_HEADERS sys.h)
|
||||
|
||||
collect (PROJECT_LIB_SOURCES irq.c)
|
||||
|
||||
# vim: expandtab:ts=2:sw=2:smartindent
|
||||
|
|
@ -1,72 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2016 - 2017, Xilinx Inc. and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file generic/xlnx_common/irq.c
|
||||
* @brief generic libmetal Xilinx irq controller definitions.
|
||||
*/
|
||||
|
||||
#include <metal/errno.h>
|
||||
#include <metal/irq_controller.h>
|
||||
#include <metal/sys.h>
|
||||
#include <metal/log.h>
|
||||
#include <metal/mutex.h>
|
||||
#include <metal/list.h>
|
||||
#include <metal/utilities.h>
|
||||
#include <metal/alloc.h>
|
||||
|
||||
#define MAX_IRQS XLNX_MAXIRQS
|
||||
|
||||
static struct metal_irq irqs[MAX_IRQS]; /**< Linux IRQs array */
|
||||
|
||||
static void metal_xlnx_irq_set_enable(struct metal_irq_controller *irq_cntr,
|
||||
int irq, unsigned int state)
|
||||
{
|
||||
if (irq < irq_cntr->irq_base ||
|
||||
irq >= irq_cntr->irq_base + irq_cntr->irq_num) {
|
||||
metal_log(METAL_LOG_ERROR, "%s: invalid irq %d\n",
|
||||
__func__, irq);
|
||||
return;
|
||||
} else if (state == METAL_IRQ_ENABLE) {
|
||||
sys_irq_enable((unsigned int)irq);
|
||||
} else {
|
||||
sys_irq_disable((unsigned int)irq);
|
||||
}
|
||||
}
|
||||
|
||||
/**< Xilinx common platform IRQ controller */
|
||||
static METAL_IRQ_CONTROLLER_DECLARE(xlnx_irq_cntr,
|
||||
0, MAX_IRQS,
|
||||
NULL,
|
||||
metal_xlnx_irq_set_enable, NULL,
|
||||
irqs);
|
||||
|
||||
/**
|
||||
* @brief default handler
|
||||
*/
|
||||
void metal_xlnx_irq_isr(void *arg)
|
||||
{
|
||||
unsigned int vector;
|
||||
|
||||
vector = (uintptr_t)arg;
|
||||
if (vector >= MAX_IRQS) {
|
||||
return;
|
||||
}
|
||||
(void)metal_irq_handle(&irqs[vector], (int)vector);
|
||||
}
|
||||
|
||||
int metal_xlnx_irq_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = metal_irq_register_controller(&xlnx_irq_cntr);
|
||||
if (ret < 0) {
|
||||
metal_log(METAL_LOG_ERROR, "%s: register irq controller failed.\n",
|
||||
__func__);
|
||||
return ret;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file generic/xlnx_common/sys.h
|
||||
* @brief generic xlnx_common system primitives for libmetal.
|
||||
*/
|
||||
|
||||
#ifndef __METAL_GENERIC_SYS__H__
|
||||
#error "Include metal/sys.h instead of metal/generic/@PROJECT_MACHINE@/sys.h"
|
||||
#endif
|
||||
|
||||
#ifndef __METAL_GENERIC_XLNX_COMMON_SYS__H__
|
||||
#define __METAL_GENERIC_XLNX_COMMON_SYS__H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief metal_xlnx_irq_isr
|
||||
*
|
||||
* Xilinx interrupt ISR can be registered to the Xilinx embeddedsw
|
||||
* IRQ controller driver.
|
||||
*
|
||||
* @param[in] arg input argument, interrupt vector id.
|
||||
*/
|
||||
void metal_xlnx_irq_isr(void *arg);
|
||||
|
||||
/**
|
||||
* @brief metal_xlnx_irq_int
|
||||
*
|
||||
* Xilinx interrupt controller initialization. It will initialize
|
||||
* the metal Xilinx IRQ controller data structure.
|
||||
*
|
||||
* @return 0 for success, or negative value for failure
|
||||
*/
|
||||
int metal_xlnx_irq_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __METAL_GENERIC_XLNX_COMMON_SYS__H__ */
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
collect (PROJECT_LIB_HEADERS sys.h)
|
||||
collect (PROJECT_LIB_SOURCES sys.c)
|
||||
|
|
@ -1,109 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Xilinx Inc. and Contributors. All rights reserved.
|
||||
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file generic/xlnx_common/zynqmp_aarch64/sys.c
|
||||
* @brief machine specific system primitives implementation.
|
||||
*/
|
||||
|
||||
#include <metal/compiler.h>
|
||||
#include <metal/io.h>
|
||||
#include <metal/sys.h>
|
||||
#include <stdint.h>
|
||||
#include "xil_cache.h"
|
||||
#include "xil_exception.h"
|
||||
#include "xil_mmu.h"
|
||||
#include "xscugic.h"
|
||||
|
||||
#ifdef VERSAL_NET
|
||||
#include "xcpu_cortexa78.h"
|
||||
#elif defined(versal)
|
||||
#include "xcpu_cortexa72.h"
|
||||
#else
|
||||
#include "xreg_cortexa53.h"
|
||||
#endif /* defined(versal) */
|
||||
|
||||
void sys_irq_restore_enable(unsigned int flags)
|
||||
{
|
||||
Xil_ExceptionEnableMask(~flags);
|
||||
}
|
||||
|
||||
unsigned int sys_irq_save_disable(void)
|
||||
{
|
||||
unsigned int state = mfcpsr() & XIL_EXCEPTION_ALL;
|
||||
|
||||
if (state != XIL_EXCEPTION_ALL)
|
||||
Xil_ExceptionDisableMask(XIL_EXCEPTION_ALL);
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
void metal_machine_cache_flush(void *addr, unsigned int len)
|
||||
{
|
||||
if (!addr && !len)
|
||||
Xil_DCacheFlush();
|
||||
else
|
||||
Xil_DCacheFlushRange((intptr_t)addr, len);
|
||||
}
|
||||
|
||||
void metal_machine_cache_invalidate(void *addr, unsigned int len)
|
||||
{
|
||||
if (!addr && !len)
|
||||
Xil_DCacheInvalidate();
|
||||
else
|
||||
Xil_DCacheInvalidateRange((intptr_t)addr, len);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief poll function until some event happens
|
||||
*/
|
||||
void metal_weak metal_generic_default_poll(void)
|
||||
{
|
||||
metal_asm volatile("wfi");
|
||||
}
|
||||
|
||||
void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
|
||||
size_t size, unsigned int flags)
|
||||
{
|
||||
unsigned long section_offset;
|
||||
unsigned long ttb_addr;
|
||||
#if defined(__aarch64__)
|
||||
unsigned long ttb_size = (pa < 4 * GB) ? 2 * MB : 1 * GB;
|
||||
#else
|
||||
unsigned long ttb_size = 1 * MB;
|
||||
#endif /* defined(__aarch64__) */
|
||||
|
||||
if (!flags)
|
||||
return va;
|
||||
|
||||
/* Ensure alignment on a section boundary */
|
||||
pa &= ~(ttb_size - 1UL);
|
||||
|
||||
/*
|
||||
* Loop through entire region of memory (one MMU section at a time).
|
||||
* Each section requires a TTB entry.
|
||||
*/
|
||||
for (section_offset = 0; section_offset < size; ) {
|
||||
/* Calculate translation table entry for this memory section */
|
||||
ttb_addr = (pa + section_offset);
|
||||
|
||||
/* Write translation table entry value to entry address */
|
||||
Xil_SetTlbAttributes(ttb_addr, flags);
|
||||
|
||||
#if defined(__aarch64__)
|
||||
/*
|
||||
* recalculate if we started below 4GB and going above in
|
||||
* 64bit mode
|
||||
*/
|
||||
if (ttb_addr >= 4 * GB)
|
||||
ttb_size = 1 * GB;
|
||||
#endif
|
||||
section_offset += ttb_size;
|
||||
}
|
||||
|
||||
return va;
|
||||
}
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Xilinx Inc. and Contributors. All rights reserved.
|
||||
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file generic/xlnx_common/zynqmp_aarch64/sys.h
|
||||
* @brief generic zynqmp_aarch64 system primitives for libmetal.
|
||||
*/
|
||||
|
||||
#ifndef __METAL_GENERIC_SYS__H__
|
||||
#error "Include metal/sys.h instead of metal/generic/@PROJECT_MACHINE@/sys.h"
|
||||
#endif
|
||||
|
||||
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/sys.h>
|
||||
#include "xscugic.h"
|
||||
|
||||
#ifndef __METAL_GENERIC_ZYNQMP_XLNX_COMMON_AARCH64_SYS__H__
|
||||
#define __METAL_GENERIC_ZYNQMP_XLNX_COMMON_AARCH64_SYS__H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef METAL_INTERNAL
|
||||
|
||||
#define XLNX_MAXIRQS XSCUGIC_MAX_NUM_INTR_INPUTS
|
||||
|
||||
static inline void sys_irq_enable(unsigned int vector)
|
||||
{
|
||||
XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
|
||||
}
|
||||
|
||||
static inline void sys_irq_disable(unsigned int vector)
|
||||
{
|
||||
XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
|
||||
}
|
||||
|
||||
#endif /* METAL_INTERNAL */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __METAL_GENERIC_ZYNQMP_XLNX_COMMON_AARCH64_SYS__H__ */
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
collect (PROJECT_LIB_HEADERS sys.h)
|
||||
|
||||
collect (PROJECT_LIB_SOURCES sys.c)
|
||||
|
||||
add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common)
|
||||
# vim: expandtab:ts=2:sw=2:smartindent
|
||||
|
|
@ -1,96 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2014, Mentor Graphics Corporation
|
||||
* Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file generic/zynq7/sys.c
|
||||
* @brief machine specific system primitives implementation.
|
||||
*/
|
||||
|
||||
#include <metal/compiler.h>
|
||||
#include <metal/io.h>
|
||||
#include <metal/sys.h>
|
||||
#include <stdint.h>
|
||||
#include "xil_cache.h"
|
||||
#include "xil_mmu.h"
|
||||
#include "xil_exception.h"
|
||||
#include "xscugic.h"
|
||||
|
||||
/* Each TTB descriptor covers a 1MB region */
|
||||
#define ARM_AR_MEM_TTB_SECT_SIZE (1024*1024)
|
||||
|
||||
/* Mask off lower bits of addr */
|
||||
#define ARM_AR_MEM_TTB_SECT_SIZE_MASK (~(ARM_AR_MEM_TTB_SECT_SIZE-1UL))
|
||||
|
||||
void sys_irq_restore_enable(unsigned int flags)
|
||||
{
|
||||
Xil_ExceptionEnableMask(~flags);
|
||||
}
|
||||
|
||||
unsigned int sys_irq_save_disable(void)
|
||||
{
|
||||
unsigned int state = mfcpsr() & XIL_EXCEPTION_ALL;
|
||||
|
||||
if (state != XIL_EXCEPTION_ALL) {
|
||||
Xil_ExceptionDisableMask(XIL_EXCEPTION_ALL);
|
||||
}
|
||||
return state;
|
||||
}
|
||||
|
||||
void metal_machine_cache_flush(void *addr, unsigned int len)
|
||||
{
|
||||
if (!addr && !len)
|
||||
Xil_DCacheFlush();
|
||||
else
|
||||
Xil_DCacheFlushRange((intptr_t)addr, len);
|
||||
}
|
||||
|
||||
void metal_machine_cache_invalidate(void *addr, unsigned int len)
|
||||
{
|
||||
if (!addr && !len)
|
||||
Xil_DCacheInvalidate();
|
||||
else
|
||||
Xil_DCacheInvalidateRange((intptr_t)addr, len);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief poll function until some event happens
|
||||
*/
|
||||
void metal_weak metal_generic_default_poll(void)
|
||||
{
|
||||
metal_asm volatile("wfi");
|
||||
}
|
||||
|
||||
void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
|
||||
size_t size, unsigned int flags)
|
||||
{
|
||||
unsigned int section_offset;
|
||||
unsigned int ttb_addr;
|
||||
|
||||
if (!flags)
|
||||
return va;
|
||||
/*
|
||||
* Ensure the virtual and physical addresses are aligned on a
|
||||
* section boundary
|
||||
*/
|
||||
pa &= ARM_AR_MEM_TTB_SECT_SIZE_MASK;
|
||||
|
||||
/*
|
||||
* Loop through entire region of memory (one MMU section at a time).
|
||||
* Each section requires a TTB entry.
|
||||
*/
|
||||
for (section_offset = 0; section_offset < size;
|
||||
section_offset += ARM_AR_MEM_TTB_SECT_SIZE) {
|
||||
|
||||
/* Calculate translation table entry for this memory section */
|
||||
ttb_addr = (pa + section_offset);
|
||||
|
||||
/* Write translation table entry value to entry address */
|
||||
Xil_SetTlbAttributes(ttb_addr, flags);
|
||||
}
|
||||
|
||||
return va;
|
||||
}
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file generic/zynq7/sys.h
|
||||
* @brief generic zynq7 system primitives for libmetal.
|
||||
*/
|
||||
|
||||
#ifndef __METAL_GENERIC_SYS__H__
|
||||
#error "Include metal/sys.h instead of metal/generic/@PROJECT_MACHINE@/sys.h"
|
||||
#endif
|
||||
|
||||
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/sys.h>
|
||||
#include "xscugic.h"
|
||||
|
||||
#ifndef __METAL_GENERIC_ZYNQ7_SYS__H__
|
||||
#define __METAL_GENERIC_ZYNQ7_SYS__H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef METAL_INTERNAL
|
||||
|
||||
#define XLNX_MAXIRQS XSCUGIC_MAX_NUM_INTR_INPUTS
|
||||
|
||||
static inline void sys_irq_enable(unsigned int vector)
|
||||
{
|
||||
XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
|
||||
}
|
||||
|
||||
static inline void sys_irq_disable(unsigned int vector)
|
||||
{
|
||||
XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
|
||||
}
|
||||
|
||||
#endif /* METAL_INTERNAL */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __METAL_GENERIC_ZYNQ7_SYS__H__ */
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
collect (PROJECT_LIB_HEADERS sys.h)
|
||||
|
||||
collect (PROJECT_LIB_SOURCES sys.c)
|
||||
|
||||
add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common)
|
||||
# vim: expandtab:ts=2:sw=2:smartindent
|
||||
|
|
@ -1,105 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file generic/zynqmp_a53/sys.c
|
||||
* @brief machine specific system primitives implementation.
|
||||
*/
|
||||
|
||||
#include <metal/compiler.h>
|
||||
#include <metal/io.h>
|
||||
#include <metal/sys.h>
|
||||
#include <stdint.h>
|
||||
#include "xil_cache.h"
|
||||
#include "xil_exception.h"
|
||||
#include "xil_mmu.h"
|
||||
#include "xreg_cortexa53.h"
|
||||
#include "xscugic.h"
|
||||
|
||||
#define MB (1024 * 1024UL)
|
||||
#define GB (1024 * 1024 * 1024UL)
|
||||
|
||||
void sys_irq_restore_enable(unsigned int flags)
|
||||
{
|
||||
Xil_ExceptionEnableMask(~flags);
|
||||
}
|
||||
|
||||
unsigned int sys_irq_save_disable(void)
|
||||
{
|
||||
unsigned int state = mfcpsr() & XIL_EXCEPTION_ALL;
|
||||
|
||||
if (state != XIL_EXCEPTION_ALL) {
|
||||
Xil_ExceptionDisableMask(XIL_EXCEPTION_ALL);
|
||||
}
|
||||
return state;
|
||||
}
|
||||
|
||||
void metal_machine_cache_flush(void *addr, unsigned int len)
|
||||
{
|
||||
if (!addr && !len)
|
||||
Xil_DCacheFlush();
|
||||
else
|
||||
Xil_DCacheFlushRange((intptr_t)addr, len);
|
||||
}
|
||||
|
||||
void metal_machine_cache_invalidate(void *addr, unsigned int len)
|
||||
{
|
||||
if (!addr && !len)
|
||||
Xil_DCacheInvalidate();
|
||||
else
|
||||
Xil_DCacheInvalidateRange((intptr_t)addr, len);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief poll function until some event happens
|
||||
*/
|
||||
void metal_weak metal_generic_default_poll(void)
|
||||
{
|
||||
metal_asm volatile("wfi");
|
||||
}
|
||||
|
||||
void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
|
||||
size_t size, unsigned int flags)
|
||||
{
|
||||
unsigned long section_offset;
|
||||
unsigned long ttb_addr;
|
||||
#if defined(__aarch64__)
|
||||
unsigned long ttb_size = (pa < 4*GB) ? 2*MB : 1*GB;
|
||||
#else
|
||||
unsigned long ttb_size = 1*MB;
|
||||
#endif
|
||||
|
||||
if (!flags)
|
||||
return va;
|
||||
|
||||
/* Ensure alignment on a section boundary */
|
||||
pa &= ~(ttb_size-1UL);
|
||||
|
||||
/*
|
||||
* Loop through entire region of memory (one MMU section at a time).
|
||||
* Each section requires a TTB entry.
|
||||
*/
|
||||
for (section_offset = 0; section_offset < size; ) {
|
||||
/* Calculate translation table entry for this memory section */
|
||||
ttb_addr = (pa + section_offset);
|
||||
|
||||
/* Write translation table entry value to entry address */
|
||||
Xil_SetTlbAttributes(ttb_addr, flags);
|
||||
|
||||
#if defined(__aarch64__)
|
||||
/*
|
||||
* recalculate if we started below 4GB and going above in
|
||||
* 64bit mode
|
||||
*/
|
||||
if (ttb_addr >= 4*GB) {
|
||||
ttb_size = 1*GB;
|
||||
}
|
||||
#endif
|
||||
section_offset += ttb_size;
|
||||
}
|
||||
|
||||
return va;
|
||||
}
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file generic/zynqmp_a53/sys.h
|
||||
* @brief generic zynqmp_a53 system primitives for libmetal.
|
||||
*/
|
||||
|
||||
#ifndef __METAL_GENERIC_SYS__H__
|
||||
#error "Include metal/sys.h instead of metal/generic/@PROJECT_MACHINE@/sys.h"
|
||||
#endif
|
||||
|
||||
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/sys.h>
|
||||
#include "xscugic.h"
|
||||
|
||||
#ifndef __METAL_GENERIC_ZYNQMP_A53_SYS__H__
|
||||
#define __METAL_GENERIC_ZYNQMP_A53_SYS__H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef METAL_INTERNAL
|
||||
|
||||
#define XLNX_MAXIRQS XSCUGIC_MAX_NUM_INTR_INPUTS
|
||||
|
||||
static inline void sys_irq_enable(unsigned int vector)
|
||||
{
|
||||
XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
|
||||
}
|
||||
|
||||
static inline void sys_irq_disable(unsigned int vector)
|
||||
{
|
||||
XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
|
||||
}
|
||||
|
||||
#endif /* METAL_INTERNAL */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __METAL_GENERIC_ZYNQMP_A53_SYS__H__ */
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
collect (PROJECT_LIB_HEADERS sys.h)
|
||||
|
||||
add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common)
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Xilinx Inc. and Contributors. All rights reserved.
|
||||
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file generic/zynqmp_a72/sys.h
|
||||
* @brief generic zynqmp_a72 system primitives for libmetal.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The header file is still required as generic/sys.h expects
|
||||
* "./@PROJECT_MACHINE@/sys.h" to still exist.
|
||||
*/
|
||||
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/zynqmp_aarch64/sys.h>
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
collect (PROJECT_LIB_HEADERS sys.h)
|
||||
|
||||
add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common)
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Xilinx Inc. and Contributors. All rights reserved.
|
||||
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file generic/zynqmp_a78/sys.h
|
||||
* @brief generic zynqmp_a78 system primitives for libmetal.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The header file is still required as generic/sys.h expects
|
||||
* "./@PROJECT_MACHINE@/sys.h" to still exist.
|
||||
*/
|
||||
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/zynqmp_aarch64/sys.h>
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
collect (PROJECT_LIB_HEADERS sys.h)
|
||||
|
||||
collect (PROJECT_LIB_SOURCES sys.c)
|
||||
|
||||
add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common)
|
||||
# vim: expandtab:ts=2:sw=2:smartindent
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
|
||||
* Copyright (C) 2022, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file generic/zynqmp_r5/sys.c
|
||||
* @brief machine specific system primitives implementation.
|
||||
*/
|
||||
|
||||
#include <metal/compiler.h>
|
||||
#include <metal/io.h>
|
||||
#include <metal/sys.h>
|
||||
#include <stdint.h>
|
||||
#include "xil_cache.h"
|
||||
#include "xil_exception.h"
|
||||
#include "xil_mmu.h"
|
||||
#include "xil_mpu.h"
|
||||
#include "xreg_cortexr5.h"
|
||||
#include "xscugic.h"
|
||||
|
||||
void sys_irq_restore_enable(unsigned int flags)
|
||||
{
|
||||
Xil_ExceptionEnableMask(~flags);
|
||||
}
|
||||
|
||||
unsigned int sys_irq_save_disable(void)
|
||||
{
|
||||
unsigned int state = mfcpsr() & XIL_EXCEPTION_ALL;
|
||||
|
||||
if (state != XIL_EXCEPTION_ALL) {
|
||||
Xil_ExceptionDisableMask(XIL_EXCEPTION_ALL);
|
||||
}
|
||||
return state;
|
||||
}
|
||||
|
||||
void metal_machine_cache_flush(void *addr, unsigned int len)
|
||||
{
|
||||
if (!addr && !len)
|
||||
Xil_DCacheFlush();
|
||||
else
|
||||
Xil_DCacheFlushRange((intptr_t)addr, len);
|
||||
}
|
||||
|
||||
void metal_machine_cache_invalidate(void *addr, unsigned int len)
|
||||
{
|
||||
if (!addr && !len)
|
||||
Xil_DCacheInvalidate();
|
||||
else
|
||||
Xil_DCacheInvalidateRange((intptr_t)addr, len);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief poll function until some event happens
|
||||
*/
|
||||
void metal_weak metal_generic_default_poll(void)
|
||||
{
|
||||
metal_asm volatile("wfi");
|
||||
}
|
||||
|
||||
/**
|
||||
* The code moved to cortexr5/xil_mpu.c:Xil_MemMap()
|
||||
* NULL in pa masks possible Xil_MemMap() errors.
|
||||
*/
|
||||
void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
|
||||
size_t size, unsigned int flags)
|
||||
{
|
||||
void *__attribute__((unused)) physaddr;
|
||||
|
||||
physaddr = Xil_MemMap(pa, size, flags);
|
||||
metal_assert(physaddr == (void *)pa);
|
||||
return va;
|
||||
}
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file generic/zynqmp_r5/sys.h
|
||||
* @brief generic zynqmp_r5 system primitives for libmetal.
|
||||
*/
|
||||
|
||||
#ifndef __METAL_GENERIC_SYS__H__
|
||||
#error "Include metal/sys.h instead of metal/system/generic/@PROJECT_MACHINE@/sys.h"
|
||||
#endif
|
||||
|
||||
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/sys.h>
|
||||
#include "xscugic.h"
|
||||
|
||||
#ifndef __METAL_GENERIC_ZYNQMP_R5_SYS__H__
|
||||
#define __METAL_GENERIC_ZYNQMP_R5_SYS__H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef METAL_INTERNAL
|
||||
|
||||
#define XLNX_MAXIRQS XSCUGIC_MAX_NUM_INTR_INPUTS
|
||||
|
||||
static inline void sys_irq_enable(unsigned int vector)
|
||||
{
|
||||
XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
|
||||
}
|
||||
|
||||
static inline void sys_irq_disable(unsigned int vector)
|
||||
{
|
||||
XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
|
||||
}
|
||||
|
||||
#endif /* METAL_INTERNAL */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __METAL_GENERIC_ZYNQMP_R5_SYS__H__ */
|
||||
Loading…
Reference in New Issue