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stm32cube: update stm32h7 to version V1.7.0 

Update Cube version for STM32H7xx series
   on https://github.com/STMicroelectronics
   from version v1.6.0
   to version v1.7.0

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2020-07-21 18:11:56 +02:00 committed by Carles Cufí
parent 6b330f0af9
commit cea57f86d3
66 changed files with 4169 additions and 1739 deletions
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9
stm32cube/stm32h7xx/README
View File

@ -35,13 +35,4 @@ License Link:
https://opensource.org/licenses/BSD-3-Clause
Patch List:
*Extend public SetFlashLatency API to all families
The LL_SetFlashLatency public API is now defined for families
beyond G4, L4 and L5.
Impacted files:
drivers/include/stm32h7xx_ll_utils.h
drivers/src/stm32h7xx_ll_utils.c
ST Bug tracker ID: XXXXX
See release_note.html from STM32Cube

35
stm32cube/stm32h7xx/drivers/include/Legacy/stm32_hal_legacy.h
View File

@ -241,7 +241,7 @@
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4)
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@ -313,8 +313,8 @@
#endif /* STM32L4 */
#if defined(STM32G0)
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
#endif
#if defined(STM32H7)
@ -955,7 +955,7 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7)
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@ -1450,7 +1450,7 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
@ -1472,7 +1472,7 @@
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
#endif /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */
#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@ -1563,10 +1563,10 @@
*/
#if defined(STM32G0)
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
#endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
@ -3243,9 +3243,8 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32L4)
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@ -3373,7 +3372,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@ -3481,9 +3480,9 @@
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
/* alias CMSIS for compatibilities */
#define SDIO_IRQn SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler
@ -3751,9 +3750,9 @@
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32L4)
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
#endif
#endif /* STM32L4 || STM32F4 || STM32F7 */
/**
* @}
*/

4
stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gpio.h
View File

@ -296,8 +296,8 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
(((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
((MODE) == GPIO_MODE_OUTPUT_OD) ||\

3
stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gpio_ex.h
View File

@ -303,7 +303,6 @@ extern "C" {
#define GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */
#endif /* PSSI */
#define GPIO_AF13_TIM1 ((uint8_t)0x0D) /* TIM1 Alternate Function mapping */
#define GPIO_AF13_TIM8 ((uint8_t)0x0D) /* TIM8 Alternate Function mapping : available on STM32H74xxx/STM32H75xxx */
/**
* @brief AF 14 selection
@ -364,7 +363,7 @@ extern "C" {
#define GPIOI_PIN_AVAILABLE GPIO_PIN_All
#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All
#define GPIOH_PIN_AVAILABLE GPIO_PIN_All
#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \
#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
/**

17
stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hrtim.h
View File

@ -654,11 +654,6 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
* @{
* @brief Constants defining timer high-resolution clock prescaler ratio.
*/
#define HRTIM_PRESCALERRATIO_MUL32 (0x00000000U) /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_MUL16 (0x00000001U) /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_MUL8 (0x00000002U) /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_MUL4 (0x00000003U) /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_MUL2 (0x00000004U) /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
@ -2083,12 +2078,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
((FAULT) == HRTIM_FAULT_5))
#define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
(((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
(((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
@ -3117,11 +3107,6 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
* @arg 0x0 to 0x4 for timers A to E
* @param __PRESCALER__ specifies the clock prescaler new value.
* This parameter can be one of the following values:
* @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)

44
stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_nand.h
View File

@ -271,33 +271,33 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
/** @defgroup NAND_Private_Constants NAND Private Constants
* @{
*/
#define NAND_DEVICE ((uint32_t)0x80000000U)
#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
#define NAND_DEVICE 0x80000000UL
#define NAND_WRITE_TIMEOUT 0x01000000UL
#define CMD_AREA ((uint32_t)(1UL<<16U)) /* A16 = CLE high */
#define ADDR_AREA ((uint32_t)(1UL<<17U)) /* A17 = ALE high */
#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
#define NAND_CMD_AREA_A ((uint8_t)0x00U)
#define NAND_CMD_AREA_B ((uint8_t)0x01U)
#define NAND_CMD_AREA_C ((uint8_t)0x50U)
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
#define NAND_CMD_AREA_A 0x00U
#define NAND_CMD_AREA_B 0x01U
#define NAND_CMD_AREA_C 0x50U
#define NAND_CMD_AREA_TRUE1 0x30U
#define NAND_CMD_WRITE0 ((uint8_t)0x80U)
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
#define NAND_CMD_ERASE0 ((uint8_t)0x60U)
#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
#define NAND_CMD_READID ((uint8_t)0x90U)
#define NAND_CMD_STATUS ((uint8_t)0x70U)
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
#define NAND_CMD_RESET ((uint8_t)0xFFU)
#define NAND_CMD_WRITE0 0x80U
#define NAND_CMD_WRITE_TRUE1 0x10U
#define NAND_CMD_ERASE0 0x60U
#define NAND_CMD_ERASE1 0xD0U
#define NAND_CMD_READID 0x90U
#define NAND_CMD_STATUS 0x70U
#define NAND_CMD_LOCK_STATUS 0x7AU
#define NAND_CMD_RESET 0xFFU
/* NAND memory status */
#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
#define NAND_BUSY ((uint32_t)0x00000000U)
#define NAND_ERROR ((uint32_t)0x00000001U)
#define NAND_READY ((uint32_t)0x00000040U)
#define NAND_VALID_ADDRESS 0x00000100UL
#define NAND_INVALID_ADDRESS 0x00000200UL
#define NAND_TIMEOUT_ERROR 0x00000400UL
#define NAND_BUSY 0x00000000UL
#define NAND_ERROR 0x00000001UL
#define NAND_READY 0x00000040UL
/**
* @}
*/

30
stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_nor.h
View File

@ -245,29 +245,29 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
* @{
*/
/* NOR device IDs addresses */
#define MC_ADDRESS ((uint16_t)0x0000U)
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
#define MC_ADDRESS ((uint16_t)0x0000)
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
/* NOR CFI IDs addresses */
#define CFI1_ADDRESS ((uint16_t)0x61U)
#define CFI2_ADDRESS ((uint16_t)0x62U)
#define CFI3_ADDRESS ((uint16_t)0x63U)
#define CFI4_ADDRESS ((uint16_t)0x64U)
#define CFI1_ADDRESS ((uint16_t)0x61)
#define CFI2_ADDRESS ((uint16_t)0x62)
#define CFI3_ADDRESS ((uint16_t)0x63)
#define CFI4_ADDRESS ((uint16_t)0x64)
/* NOR operation wait timeout */
#define NOR_TMEOUT ((uint16_t)0xFFFFU)
#define NOR_TMEOUT ((uint16_t)0xFFFF)
/* NOR memory data width */
#define NOR_MEMORY_8B ((uint8_t)0x0U)
#define NOR_MEMORY_16B ((uint8_t)0x1U)
#define NOR_MEMORY_8B ((uint8_t)0x0)
#define NOR_MEMORY_16B ((uint8_t)0x1)
/* NOR memory device read/write start address */
#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000)
#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000)
#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000)
#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000)
/**
* @}
*/

31
stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_ospi.h
View File

@ -259,6 +259,9 @@ typedef struct
This parameter can be a value of @ref OSPIM_IOPort */
uint32_t IOHighPort; /* It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins.
This parameter can be a value of @ref OSPIM_IOPort */
uint32_t Req2AckTime; /* It indicates the minimum switching duration (in number of clock cycles) expected
if some signals are multiplexed in the OSPI IO Manager with the other OSPI.
This parameter can be a value between 1 and 256 */
}OSPIM_CfgTypeDef;
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
@ -683,7 +686,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
* @{
*/
/** @brief Reset OSPI handle state.
* @param __HANDLE__: OSPI handle.
* @param __HANDLE__ specifies the OSPI Handle.
* @retval None
*/
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
@ -697,20 +700,20 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
#endif
/** @brief Enable the OSPI peripheral.
* @param __HANDLE__: specifies the OSPI Handle.
* @param __HANDLE__ specifies the OSPI Handle.
* @retval None
*/
#define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
/** @brief Disable the OSPI peripheral.
* @param __HANDLE__: specifies the OSPI Handle.
* @param __HANDLE__ specifies the OSPI Handle.
* @retval None
*/
#define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
/** @brief Enable the specified OSPI interrupt.
* @param __HANDLE__: specifies the OSPI Handle.
* @param __INTERRUPT__: specifies the OSPI interrupt source to enable.
* @param __HANDLE__ specifies the OSPI Handle.
* @param __INTERRUPT__ specifies the OSPI interrupt source to enable.
* This parameter can be one of the following values:
* @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
* @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
@ -723,8 +726,8 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
/** @brief Disable the specified OSPI interrupt.
* @param __HANDLE__: specifies the OSPI Handle.
* @param __INTERRUPT__: specifies the OSPI interrupt source to disable.
* @param __HANDLE__ specifies the OSPI Handle.
* @param __INTERRUPT__ specifies the OSPI interrupt source to disable.
* This parameter can be one of the following values:
* @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
* @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
@ -736,8 +739,8 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
#define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Check whether the specified OSPI interrupt source is enabled or not.
* @param __HANDLE__: specifies the OSPI Handle.
* @param __INTERRUPT__: specifies the OSPI interrupt source to check.
* @param __HANDLE__ specifies the OSPI Handle.
* @param __INTERRUPT__ specifies the OSPI interrupt source to check.
* This parameter can be one of the following values:
* @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
* @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
@ -750,8 +753,8 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
/**
* @brief Check whether the selected OSPI flag is set or not.
* @param __HANDLE__: specifies the OSPI Handle.
* @param __FLAG__: specifies the OSPI flag to check.
* @param __HANDLE__ specifies the OSPI Handle.
* @param __FLAG__ specifies the OSPI flag to check.
* This parameter can be one of the following values:
* @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag
* @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag
@ -764,8 +767,8 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
/** @brief Clears the specified OSPI's flag status.
* @param __HANDLE__: specifies the OSPI Handle.
* @param __FLAG__: specifies the OSPI clear register flag that needs to be set
* @param __HANDLE__ specifies the OSPI Handle.
* @param __FLAG__ specifies the OSPI clear register flag that needs to be set
* This parameter can be one of the following values:
* @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag
* @arg HAL_OSPI_FLAG_SM: OSPI Status match flag
@ -1046,6 +1049,8 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi,
((PORT) == HAL_OSPIM_IOPORT_7_HIGH) || \
((PORT) == HAL_OSPIM_IOPORT_8_LOW) || \
((PORT) == HAL_OSPIM_IOPORT_8_HIGH))
#define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U))
/**
@endcond
*/

19
stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pssi.h
View File

@ -239,6 +239,9 @@ typedef enum
#define PSSI_FLAG_RTT1B PSSI_SR_RTT1B /*!< 1 Byte Fifo Flag*/
#define PSSI_FLAG_RTT4B PSSI_SR_RTT4B /*!< 4 Bytes Fifo Flag*/
/**
* @}
*/
@ -253,6 +256,9 @@ typedef enum
/**
* @}
*/
/**
* @}
*/
@ -403,6 +409,7 @@ typedef enum
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PSSI_Exported_Functions
* @{
@ -411,6 +418,7 @@ typedef enum
/** @addtogroup PSSI_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *******************************/
HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi);
HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi);
@ -420,6 +428,8 @@ void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi);
HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, pPSSI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID);
/**
* @}
*/
@ -427,6 +437,7 @@ HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSS
/** @addtogroup PSSI_Exported_Functions_Group2
* @{
*/
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
@ -434,6 +445,7 @@ HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDa
HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);
HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi);
void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi);
/**
* @}
*/
@ -441,10 +453,13 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi);
/** @addtogroup PSSI_Exported_Functions_Group3
* @{
*/
void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi);
void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi);
void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi);
void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi);
/**
* @}
*/
@ -452,9 +467,11 @@ void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi);
/** @addtogroup PSSI_Exported_Functions_Group4
* @{
*/
/* Peripheral State functions ***************************************************/
HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi);
uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi);
uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi);
/**
* @}
*/

124
stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_qspi.h
View File

@ -12,7 +12,7 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@ -25,11 +25,11 @@
extern "C" {
#endif
#if defined(QUADSPI)
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
#if defined(QUADSPI)
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
@ -46,35 +46,27 @@
/**
* @brief QSPI Init structure definition
*/
typedef struct
{
uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
This parameter can be a number between 0 and 255 */
uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
This parameter can be a value between 1 and 32 */
uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
This parameter can be a value of @ref QSPI_SampleShifting */
uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
required to address the flash memory. The flash capacity can be up to 4GB
(addressed using 32 bits) in indirect mode, but the addressable space in
memory-mapped mode is limited to 256MB
This parameter can be a number between 0 and 31 */
uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
of clock cycles which the chip select must remain high between commands.
This parameter can be a value of @ref QSPI_ChipSelectHighTime */
uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
This parameter can be a value of @ref QSPI_ClockMode */
uint32_t FlashID; /* Specifies the Flash which will be used,
This parameter can be a value of @ref QSPI_Flash_Select */
uint32_t DualFlash; /* Specifies the Dual Flash Mode State
This parameter can be a value of @ref QSPI_DualFlash_Mode */
}QSPI_InitTypeDef;
@ -102,7 +94,7 @@ typedef enum
typedef struct __QSPI_HandleTypeDef
#else
typedef struct
#endif/* USE_HAL_QSPI_REGISTER_CALLBACKS */
#endif
{
QUADSPI_TypeDef *Instance; /* QSPI registers base address */
QSPI_InitTypeDef Init; /* QSPI communication parameters */
@ -112,7 +104,7 @@ typedef struct
uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
__IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
__IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */
MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */
__IO HAL_LockTypeDef Lock; /* Locking object */
__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
__IO uint32_t ErrorCode; /* QSPI Error code */
@ -157,13 +149,13 @@ typedef struct
This parameter can be a value of @ref QSPI_AlternateBytesMode */
uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
This parameter can be a value of @ref QSPI_DataMode */
uint32_t NbData; /* Specifies the number of data to transfer.
uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
until end of memory)*/
uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
This parameter can be a value of @ref QSPI_DdrMode */
uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
system clock in DDR mode.
uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data
output by one half of system clock in DDR mode.
This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
uint32_t SIOOMode; /* Specifies the send instruction only once mode
This parameter can be a value of @ref QSPI_SIOOMode */
@ -195,7 +187,7 @@ typedef struct
{
uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
This parameter can be any value between 0 and 0xFFFF */
uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
This parameter can be a value of @ref QSPI_TimeOutActivation */
}QSPI_MemoryMappedTypeDef;
@ -235,11 +227,11 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_ErrorCode QSPI Error Code
* @{
*/
#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */
#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */
#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
#endif
@ -250,7 +242,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
* @{
*/
#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!<No clock cycle shift to sample data*/
#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/
#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
/**
* @}
@ -259,7 +251,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
* @{
*/
#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U) /*!<nCS stay high for at least 1 clock cycle between commands*/
#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/
#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
@ -274,7 +266,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_ClockMode QSPI Clock Mode
* @{
*/
#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/
#define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/
#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
/**
* @}
@ -283,7 +275,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_Flash_Select QSPI Flash Select
* @{
*/
#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000) /*!<FLASH 1 selected*/
#define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/
#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
/**
* @}
@ -293,7 +285,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
* @{
*/
#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000) /*!<Dual-flash mode disabled*/
#define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/
/**
* @}
*/
@ -301,7 +293,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_AddressSize QSPI Address Size
* @{
*/
#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/
#define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/
#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
@ -312,7 +304,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
* @{
*/
#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
@ -323,7 +315,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
* @{
*/
#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/
#define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/
#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
@ -334,7 +326,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_AddressMode QSPI Address Mode
* @{
*/
#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/
#define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/
#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
@ -345,7 +337,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
* @{
*/
#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/
#define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/
#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
@ -356,7 +348,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_DataMode QSPI Data Mode
* @{
*/
#define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
#define QSPI_DATA_NONE 0x00000000U /*!<No data*/
#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
@ -367,7 +359,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_DdrMode QSPI DDR Mode
* @{
*/
#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/
#define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/
#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
/**
* @}
@ -376,8 +368,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
* @{
*/
#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/
#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
#define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/
#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/
/**
* @}
*/
@ -385,7 +377,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
* @{
*/
#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/
#define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/
#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
/**
* @}
@ -394,7 +386,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_MatchMode QSPI Match Mode
* @{
*/
#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/
#define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/
#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
/**
* @}
@ -403,7 +395,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
* @{
*/
#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/
#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/
#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
/**
* @}
@ -412,7 +404,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
* @{
*/
#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/
#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/
#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
/**
* @}
@ -447,7 +439,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
* @brief QSPI Timeout definition
* @{
*/
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
/**
* @}
*/
@ -461,7 +453,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
* @{
*/
/** @brief Reset QSPI handle state.
* @param __HANDLE__: QSPI handle.
* @param __HANDLE__ : QSPI handle.
* @retval None
*/
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
@ -475,20 +467,20 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
#endif
/** @brief Enable the QSPI peripheral.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Disable the QSPI peripheral.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Enable the specified QSPI interrupt.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __INTERRUPT__ : specifies the QSPI interrupt source to enable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@ -501,8 +493,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @brief Disable the specified QSPI interrupt.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __INTERRUPT__ : specifies the QSPI interrupt source to disable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@ -514,8 +506,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Check whether the specified QSPI interrupt source is enabled or not.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __INTERRUPT__: specifies the QSPI interrupt source to check.
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __INTERRUPT__ : specifies the QSPI interrupt source to check.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@ -528,8 +520,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/**
* @brief Check whether the selected QSPI flag is set or not.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __FLAG__: specifies the QSPI flag to check.
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __FLAG__ : specifies the QSPI flag to check.
* This parameter can be one of the following values:
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
* @arg QSPI_FLAG_TO: QSPI Timeout flag
@ -542,8 +534,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
/** @brief Clears the specified QSPI's flag status.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __FLAG__: specifies the QSPI clear register flag that needs to be set
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __FLAG__ : specifies the QSPI clear register flag that needs to be set
* This parameter can be one of the following values:
* @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
@ -560,12 +552,22 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @addtogroup QSPI_Exported_Functions
* @{
*/
/** @addtogroup QSPI_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
/**
* @}
*/
/** @addtogroup QSPI_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
/* QSPI IRQ handler method */
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
@ -628,12 +630,15 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint3
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup QSPI_Private_Macros QSPI Private Macros
* @{
*/
* @{
*/
#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
@ -655,7 +660,6 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint3
#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
((CLKMODE) == QSPI_CLOCK_MODE_3))
#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \
((FLASH_ID) == QSPI_FLASH_ID_2))
@ -732,11 +736,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint3
* @}
*/
/**
* @}
*/
#endif /* QUADSPI */
#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
#ifdef __cplusplus
}

83
stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc.h
View File

@ -294,10 +294,10 @@ typedef struct
/** @defgroup RCC_PLL1_VCI_Range RCC PLL1 VCI Range
* @{
*/
#define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0
#define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1
#define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2
#define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3
#define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0 /*!< Clock range frequency between 1 and 2 MHz */
#define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1 /*!< Clock range frequency between 2 and 4 MHz */
#define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2 /*!< Clock range frequency between 4 and 8 MHz */
#define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3 /*!< Clock range frequency between 8 and 16 MHz */
/**
@ -1176,6 +1176,7 @@ typedef struct
} while(0)
#endif /* DCMI && PSSI */
#if defined(CRYP)
#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
@ -1183,7 +1184,9 @@ typedef struct
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
UNUSED(tmpreg); \
} while(0)
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_HASH_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
@ -1191,6 +1194,7 @@ typedef struct
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
UNUSED(tmpreg); \
} while(0)
#endif /* HASH */
#define __HAL_RCC_RNG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@ -1280,8 +1284,12 @@ typedef struct
#else
#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
#endif /* DCMI && PSSI */
#if defined(CRYP)
#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
#endif /* HASH */
#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
#if defined(RCC_AHB2ENR_D2SRAM1EN)
@ -1316,8 +1324,12 @@ typedef struct
#else
#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U)
#endif /* DCMI && PSSI */
#if defined(CRYP)
#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) != 0U)
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) != 0U)
#endif /* HASH */
#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U)
#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U)
#if defined(RCC_AHB2ENR_D2SRAM1EN)
@ -1346,8 +1358,12 @@ typedef struct
#else
#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) == 0U)
#endif /* DCMI && PSSI */
#if defined(CRYP)
#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) == 0U)
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) == 0U)
#endif /* HASH */
#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U)
#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U)
#if defined(RCC_AHB2ENR_D2SRAM1EN)
@ -2711,7 +2727,7 @@ typedef struct
tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
UNUSED(tmpreg); \
} while(0)
#if defined(CRYP)
#define __HAL_RCC_C1_CRYP_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
@ -2719,7 +2735,9 @@ typedef struct
tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
UNUSED(tmpreg); \
} while(0)
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_C1_HASH_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
@ -2727,6 +2745,7 @@ typedef struct
tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
UNUSED(tmpreg); \
} while(0)
#endif /* HASH */
#define __HAL_RCC_C1_RNG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@ -2769,8 +2788,12 @@ typedef struct
} while(0)
#define __HAL_RCC_C1_DCMI_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
#if defined(CRYP)
#define __HAL_RCC_C1_CRYP_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_C1_HASH_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
#endif /* HASH */
#define __HAL_RCC_C1_RNG_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
#define __HAL_RCC_C1_SDMMC2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
#define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
@ -3734,6 +3757,7 @@ typedef struct
UNUSED(tmpreg); \
} while(0)
#if defined(CRYP)
#define __HAL_RCC_C2_CRYP_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
@ -3741,7 +3765,9 @@ typedef struct
tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
UNUSED(tmpreg); \
} while(0)
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_C2_HASH_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
@ -3749,6 +3775,7 @@ typedef struct
tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
UNUSED(tmpreg); \
} while(0)
#endif /* HASH */
#define __HAL_RCC_C2_RNG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@ -3791,8 +3818,12 @@ typedef struct
} while(0)
#define __HAL_RCC_C2_DCMI_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
#if defined(CRYP)
#define __HAL_RCC_C2_CRYP_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_C2_HASH_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
#endif /* HASH */
#define __HAL_RCC_C2_RNG_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
#define __HAL_RCC_C2_SDMMC2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
#define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
@ -4528,7 +4559,7 @@ typedef struct
/** @brief Enable or disable the AHB3 peripheral reset.
*/
#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x7FFFFFFFU)
#define __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
#if defined(JPEG)
@ -4637,8 +4668,12 @@ typedef struct
#else
#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
#endif /* DCMI && PSSI */
#if defined(CRYP)
#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
#endif /* HASH */
#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))
#if defined(RCC_AHB2RSTR_HSEMRST)
@ -4655,8 +4690,12 @@ typedef struct
#else
#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))
#endif /* DCMI && PSSI */
#if defined(CRYP)
#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))
#endif /* HASH */
#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))
#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))
#if defined(RCC_AHB2RSTR_HSEMRST)
@ -5240,8 +5279,12 @@ typedef struct
#else
#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
#endif /* DCMI && PSSI */
#if defined(CRYP)
#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
#endif /* HASH */
#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
@ -5267,8 +5310,12 @@ typedef struct
#else
#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
#endif /* DCMI && PSSI */
#if defined(CRYP)
#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
#endif /* HASH */
#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
@ -5301,8 +5348,12 @@ typedef struct
#else
#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U)
#endif /* DCMI && PSSI */
#if defined(CRYP)
#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != 0U)
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != 0U)
#endif /* HASH */
#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U)
#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U)
#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
@ -5328,8 +5379,12 @@ typedef struct
#else
#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == 0U)
#endif /* DCMI && PSSI */
#if defined(CRYP)
#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == 0U)
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == 0U)
#endif /* HASH */
#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U)
#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U)
@ -6010,8 +6065,12 @@ typedef struct
*/
#define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
#if defined(CRYP)
#define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
#endif /* HASH */
#define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
@ -6019,8 +6078,12 @@ typedef struct
#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
#define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
#if defined(CRYP)
#define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
#endif /* HASH */
#define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
@ -6298,8 +6361,12 @@ typedef struct
*/
#define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
#if defined(CRYP)
#define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
#endif /* HASH */
#define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
@ -6307,8 +6374,12 @@ typedef struct
#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
#define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
#if defined(CRYP)
#define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
#endif /* CRYP */
#if defined(HASH)
#define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
#endif /* HASH */
#define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))

155
stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc_ex.h
View File

@ -461,10 +461,10 @@ typedef struct
/** @defgroup RCC_PLL2_VCI_Range RCC PLL2 VCI Range
* @{
*/
#define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0
#define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1
#define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2
#define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3
#define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0 /*!< Clock range frequency between 1 and 2 MHz */
#define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1 /*!< Clock range frequency between 2 and 4 MHz */
#define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2 /*!< Clock range frequency between 4 and 8 MHz */
#define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3 /*!< Clock range frequency between 8 and 16 MHz */
/**
* @}
@ -484,10 +484,10 @@ typedef struct
/** @defgroup RCC_PLL3_VCI_Range RCC PLL3 VCI Range
* @{
*/
#define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0
#define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1
#define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2
#define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3
#define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0 /*!< Clock range frequency between 1 and 2 MHz */
#define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1 /*!< Clock range frequency between 2 and 4 MHz */
#define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2 /*!< Clock range frequency between 4 and 8 MHz */
#define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3 /*!< Clock range frequency between 8 and 16 MHz */
/**
* @}
@ -1511,6 +1511,14 @@ typedef struct
#endif /*DUAL_CORE*/
/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
* @{
*/
#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
/**
* @}
*/
/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
* @{
*/
@ -3403,6 +3411,134 @@ typedef struct
/**
* @}
*/
/**
* @brief Enable the RCC LSE CSS Extended Interrupt Line.
* @retval None
*/
#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Disable the RCC LSE CSS Extended Interrupt Line.
* @retval None
*/
#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Enable the RCC LSE CSS Event Line.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Disable the RCC LSE CSS Event Line.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
#if defined(DUAL_CORE)
/**
* @brief Enable the RCC LSE CSS Extended Interrupt Line for CM4.
* @retval None
*/
#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Disable the RCC LSE CSS Extended Interrupt Line for CM4.
* @retval None
*/
#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Enable the RCC LSE CSS Event Line for CM4.
* @retval None.
*/
#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Disable the RCC LSE CSS Event Line for CM4.
* @retval None.
*/
#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
#endif /* DUAL_CORE */
/**
* @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
* @retval EXTI RCC LSE CSS Line Status.
*/
#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
/**
* @brief Clear the RCC LSE CSS EXTI flag.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
#if defined(DUAL_CORE)
/**
* @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not for CM4.
* @retval EXTI RCC LSE CSS Line Status.
*/
#define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
/**
* @brief Clear the RCC LSE CSS EXTI flag or not for CM4.
* @retval None.
*/
#define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS)
#endif /* DUAL_CORE */
/**
* @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Enable the specified CRS interrupts.
* @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
@ -3583,6 +3719,9 @@ void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);
void HAL_RCCEx_EnableLSECSS(void);
void HAL_RCCEx_DisableLSECSS(void);
void HAL_RCCEx_EnableLSECSS_IT(void);
void HAL_RCCEx_LSECSS_IRQHandler(void);
void HAL_RCCEx_LSECSS_Callback(void);
#if defined(DUAL_CORE)
void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx);
#endif /*DUAL_CORE*/

6
stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_usart.h
View File

@ -228,6 +228,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
#define HAL_USART_ERROR_RTO ((uint32_t)0x00000080U) /*!< Receiver Timeout error */
/**
* @}
*/
@ -352,6 +353,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */
#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */
#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */
#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */
#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */
#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */
@ -406,6 +408,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
#define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */
#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */
#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */
/**
* @}
*/
@ -462,6 +465,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @arg @ref USART_FLAG_TC Transmission Complete flag
* @arg @ref USART_FLAG_RXNE Receive data register not empty flag
* @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag
* @arg @ref USART_FLAG_RTOF Receiver Timeout flag
* @arg @ref USART_FLAG_IDLE Idle Line detection flag
* @arg @ref USART_FLAG_ORE OverRun Error flag
* @arg @ref USART_FLAG_NE Noise Error flag
@ -482,6 +486,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag
* @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag
* @retval None
*/
@ -632,6 +637,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @retval None

3
stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_usart_ex.h
View File

@ -46,7 +46,7 @@ extern "C" {
* @{
*/
#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
/**
* @}
@ -169,7 +169,6 @@ extern "C" {
} \
} while(0U)
/**
* @brief Ensure that USART frame length is valid.
* @param __LENGTH__ USART frame length.

44
stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dma.h
View File

@ -969,6 +969,50 @@ __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32
return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL));
}
/**
* @brief Enable DMA stream bufferable transfer.
* @rmtoll CR TRBUFF LL_DMA_EnableBufferableTransfer
* @param DMAx DMAx Instance
* @param Stream This parameter can be one of the following values:
* @arg @ref LL_DMA_STREAM_0
* @arg @ref LL_DMA_STREAM_1
* @arg @ref LL_DMA_STREAM_2
* @arg @ref LL_DMA_STREAM_3
* @arg @ref LL_DMA_STREAM_4
* @arg @ref LL_DMA_STREAM_5
* @arg @ref LL_DMA_STREAM_6
* @arg @ref LL_DMA_STREAM_7
* @retval None
*/
__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
{
register uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
}
/**
* @brief Disable DMA stream bufferable transfer.
* @rmtoll CR TRBUFF LL_DMA_DisableBufferableTransfer
* @param DMAx DMAx Instance
* @param Stream This parameter can be one of the following values:
* @arg @ref LL_DMA_STREAM_0
* @arg @ref LL_DMA_STREAM_1
* @arg @ref LL_DMA_STREAM_2
* @arg @ref LL_DMA_STREAM_3
* @arg @ref LL_DMA_STREAM_4
* @arg @ref LL_DMA_STREAM_5
* @arg @ref LL_DMA_STREAM_6
* @arg @ref LL_DMA_STREAM_7
* @retval None
*/
__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
{
register uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
}
/**
* @brief Set Number of data to transfer.
* @rmtoll NDTR NDT LL_DMA_SetDataLength

192
stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_fmc.h
View File

@ -457,10 +457,10 @@ typedef struct
/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
* @{
*/
#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
/**
* @}
*/
@ -468,8 +468,8 @@ typedef struct
/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
* @{
*/
#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
/**
* @}
*/
@ -477,9 +477,9 @@ typedef struct
/** @defgroup FMC_Memory_Type FMC Memory Type
* @{
*/
#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
/**
* @}
*/
@ -487,9 +487,9 @@ typedef struct
/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
* @{
*/
#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
/**
* @}
*/
@ -497,8 +497,8 @@ typedef struct
/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
* @{
*/
#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
@ -506,8 +506,8 @@ typedef struct
/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
* @{
*/
#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
/**
* @}
*/
@ -515,8 +515,8 @@ typedef struct
/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
* @{
*/
#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
/**
* @}
*/
@ -524,8 +524,8 @@ typedef struct
/** @defgroup FMC_Wait_Timing FMC Wait Timing
* @{
*/
#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
/**
* @}
*/
@ -533,8 +533,8 @@ typedef struct
/** @defgroup FMC_Write_Operation FMC Write Operation
* @{
*/
#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
/**
* @}
*/
@ -542,8 +542,8 @@ typedef struct
/** @defgroup FMC_Wait_Signal FMC Wait Signal
* @{
*/
#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
/**
* @}
*/
@ -551,8 +551,8 @@ typedef struct
/** @defgroup FMC_Extended_Mode FMC Extended Mode
* @{
*/
#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
/**
* @}
*/
@ -560,8 +560,8 @@ typedef struct
/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
* @{
*/
#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
/**
* @}
*/
@ -569,7 +569,7 @@ typedef struct
/** @defgroup FMC_Page_Size FMC Page Size
* @{
*/
#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0)
#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1)
#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1))
@ -581,8 +581,8 @@ typedef struct
/** @defgroup FMC_Write_Burst FMC Write Burst
* @{
*/
#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
/**
* @}
*/
@ -590,8 +590,8 @@ typedef struct
/** @defgroup FMC_Continous_Clock FMC Continuous Clock
* @{
*/
#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
/**
* @}
*/
@ -600,7 +600,7 @@ typedef struct
* @{
*/
#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000)
/**
* @}
*/
@ -608,10 +608,10 @@ typedef struct
/** @defgroup FMC_Access_Mode FMC Access Mode
* @{
*/
#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
/**
* @}
*/
@ -627,7 +627,7 @@ typedef struct
/** @defgroup FMC_NAND_Bank FMC NAND Bank
* @{
*/
#define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
/**
* @}
*/
@ -635,8 +635,8 @@ typedef struct
/** @defgroup FMC_Wait_feature FMC Wait feature
* @{
*/
#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
/**
* @}
*/
@ -644,7 +644,7 @@ typedef struct
/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
* @{
*/
#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
/**
* @}
*/
@ -652,8 +652,8 @@ typedef struct
/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
* @{
*/
#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
/**
* @}
*/
@ -661,8 +661,8 @@ typedef struct
/** @defgroup FMC_ECC FMC ECC
* @{
*/
#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
/**
* @}
*/
@ -670,12 +670,12 @@ typedef struct
/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
* @{
*/
#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
/**
* @}
*/
@ -690,8 +690,8 @@ typedef struct
/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
* @{
*/
#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U)
#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U)
#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
/**
* @}
*/
@ -699,10 +699,10 @@ typedef struct
/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
* @{
*/
#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U)
#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U)
#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U)
#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U)
#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
/**
* @}
*/
@ -710,9 +710,9 @@ typedef struct
/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
* @{
*/
#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U)
#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U)
#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U)
#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
/**
* @}
*/
@ -720,9 +720,9 @@ typedef struct
/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
* @{
*/
#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
/**
* @}
*/
@ -730,8 +730,8 @@ typedef struct
/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
* @{
*/
#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U)
#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U)
#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
/**
* @}
*/
@ -739,9 +739,9 @@ typedef struct
/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
* @{
*/
#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U)
#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U)
#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180U)
#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
/**
* @}
*/
@ -749,8 +749,8 @@ typedef struct
/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
* @{
*/
#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U)
#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U)
#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
/**
* @}
*/
@ -758,9 +758,9 @@ typedef struct
/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
* @{
*/
#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U)
#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U)
#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00U)
#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
/**
* @}
*/
@ -768,8 +768,8 @@ typedef struct
/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
* @{
*/
#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U)
#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U)
#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
/**
* @}
*/
@ -777,9 +777,9 @@ typedef struct
/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
* @{
*/
#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U)
#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U)
#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U)
#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
/**
* @}
*/
@ -787,13 +787,13 @@ typedef struct
/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
* @{
*/
#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U)
#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U)
#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U)
#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U)
#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U)
#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U)
#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U)
#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
/**
* @}
*/
@ -803,7 +803,7 @@ typedef struct
*/
#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U)
#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
/**
* @}
*/
@ -811,7 +811,7 @@ typedef struct
/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
* @{
*/
#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U)
#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
/**
@ -826,10 +826,10 @@ typedef struct
/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
* @{
*/
#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
#define FMC_IT_LEVEL ((uint32_t)0x00000010U)
#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
#define FMC_IT_LEVEL ((uint32_t)0x00000010)
#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
/**
* @}
*/
@ -837,10 +837,10 @@ typedef struct
/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
* @{
*/
#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
#define FMC_FLAG_LEVEL ((uint32_t)0x00000002U)
#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
#define FMC_FLAG_FEMPT ((uint32_t)0x00000040U)
#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE

15
stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_hrtim.h
View File

@ -608,11 +608,6 @@ static const uint8_t REG_SHIFT_TAB_FLTxE[] =
* @{
* @brief Constants defining timer high-resolution clock prescaler ratio.
*/
#define LL_HRTIM_PRESCALERRATIO_MUL32 0x00000000U /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U) /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U) /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U) /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U) /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
@ -2568,11 +2563,6 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, ui
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
@ -2598,11 +2588,6 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @retval Prescaler Returned value can be one of the following values:
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4

42
stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_lptim.h
View File

@ -375,7 +375,7 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL));
return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
}
/**
@ -428,7 +428,7 @@ __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE)? 1UL : 0UL));
return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
}
/**
@ -772,7 +772,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL));
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
}
/**
@ -1063,7 +1063,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL));
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
}
/**
@ -1093,7 +1093,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL));
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
}
/**
@ -1115,7 +1115,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL));
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
}
/**
@ -1137,7 +1137,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL));
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
}
/**
@ -1159,7 +1159,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL));
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
}
/**
@ -1181,7 +1181,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL));
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
}
/**
@ -1203,7 +1203,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL));
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
}
/**
@ -1225,7 +1225,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL));
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
}
/**
@ -1266,7 +1266,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL));
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
}
/**
@ -1299,7 +1299,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL));
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
}
/**
@ -1332,7 +1332,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL));
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
}
/**
@ -1365,7 +1365,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL));
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
}
/**
@ -1394,11 +1394,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
* @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
* @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL));
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
}
/**
@ -1427,11 +1427,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
* @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
* @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL));
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
}
/**
@ -1460,11 +1460,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
* @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
* @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
{
return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL);
return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
}
/**

24
stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_rcc.h
View File

@ -1419,9 +1419,9 @@ typedef struct
* @retval SYSCLK clock frequency (in Hz)
*/
#if defined(RCC_D1CFGR_D1CPRE)
#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos])
#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU))
#else
#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos])
#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU))
#endif /* RCC_D1CFGR_D1CPRE */
/**
@ -1440,9 +1440,9 @@ typedef struct
* @retval HCLK clock frequency (in Hz)
*/
#if defined(RCC_D1CFGR_HPRE)
#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos])
#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU))
#else
#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos])
#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU))
#endif /* RCC_D1CFGR_HPRE */
/**
@ -1457,9 +1457,9 @@ typedef struct
* @retval PCLK1 clock frequency (in Hz)
*/
#if defined(RCC_D2CFGR_D2PPRE1)
#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos])
#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU))
#else
#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos])
#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU))
#endif /* RCC_D2CFGR_D2PPRE1 */
/**
@ -1474,9 +1474,9 @@ typedef struct
* @retval PCLK2 clock frequency (in Hz)
*/
#if defined(RCC_D2CFGR_D2PPRE2)
#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos])
#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU))
#else
#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos])
#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU))
#endif /* RCC_D2CFGR_D2PPRE2 */
/**
@ -1491,9 +1491,9 @@ typedef struct
* @retval PCLK1 clock frequency (in Hz)
*/
#if defined(RCC_D1CFGR_D1PPRE)
#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos])
#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos]) & 0x1FU))
#else
#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos])
#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos]) & 0x1FU))
#endif /* RCC_D1CFGR_D1PPRE */
/**
@ -1508,9 +1508,9 @@ typedef struct
* @retval PCLK1 clock frequency (in Hz)
*/
#if defined(RCC_D3CFGR_D3PPRE)
#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos])
#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos]) & 0x1FU))
#else
#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos])
#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos]) & 0x1FU))
#endif /* RCC_D3CFGR_D3PPRE */
/**

7
stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_tim.h
View File

@ -220,13 +220,14 @@ typedef struct
This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
This parameter must be a number between 0x00 and 0xFF.
GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
} LL_TIM_InitTypeDef;
@ -1734,7 +1735,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
* @param TIMx Timer instance
* @param RepetitionCounter between Min_Data=0 and Max_Data=255
* @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)

21
stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_usart.h
View File

@ -2651,7 +2651,8 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
{
/* In Asynchronous mode, the following bits must be kept cleared:
- LINEN, CLKEN bits in the USART_CR2 register,
- SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
- SCEN, IREN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
}
@ -2687,7 +2688,8 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
{
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
- SCEN, IREN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
/* set the UART/USART in Synchronous mode */
@ -2727,7 +2729,8 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
{
/* In LIN mode, the following bits must be kept cleared:
- STOP and CLKEN bits in the USART_CR2 register,
- IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
- IREN, SCEN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
/* Set the UART/USART in LIN mode */
@ -2765,7 +2768,8 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
{
/* In Half Duplex mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.*/
- SCEN and IREN bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
/* set the UART/USART in Half Duplex mode */
@ -2805,7 +2809,8 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
{
/* In Smartcard mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- IREN and HDSEL bits in the USART_CR3 register.*/
- IREN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
/* Configure Stop bits to 1.5 bits */
@ -2848,7 +2853,8 @@ __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
{
/* In IRDA mode, the following bits must be kept cleared:
- LINEN, STOP and CLKEN bits in the USART_CR2 register,
- SCEN and HDSEL bits in the USART_CR3 register.*/
- SCEN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
/* set the UART/USART in IRDA mode */
@ -2886,7 +2892,8 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
{
/* In Multi Processor mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
- IREN, SCEN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
}

16
stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_utils.h
View File

@ -121,13 +121,13 @@ typedef struct
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_SetFRACN(). */
uint32_t VCO_Input; /*!< Fractional part of the multiplication factor for PLL VCO.
uint32_t VCO_Input; /*!< PLL clock Input range.
This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_SetVCOInputRange(). */
uint32_t VCO_Output; /*!< Fractional part of the multiplication factor for PLL VCO.
uint32_t VCO_Output; /*!< PLL clock Output range.
This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE
This feature can be modified afterwards using unitary function
@ -213,11 +213,11 @@ typedef struct
#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000005UL /*!< LQFP144 package type */
#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x00000006UL /*!< LQFP144 with SMPS package type */
#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007UL /*!< UFBGA169 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 0x00000010UL /*!< UFBGA176 or LQFP176 package type */
#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x00000011UL /*!< LQFP176 with SMPS package type */
#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x00000012UL /*!< UFBGA176 with SMPS package type */
#define LL_UTILS_PACKAGETYPE_TFBGA216 0x00000014UL /*!< TFBGA216 package type */
#define LL_UTILS_PACKAGETYPE_TFBGA225 0x00000016UL /*!< TFBGA225 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 0x00000008UL /*!< UFBGA176 or LQFP176 package type */
#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x00000009UL /*!< LQFP176 with SMPS package type */
#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x0000000AUL /*!< UFBGA176 with SMPS package type */
#define LL_UTILS_PACKAGETYPE_TFBGA216 0x0000000CUL /*!< TFBGA216 package type */
#define LL_UTILS_PACKAGETYPE_TFBGA225 0x0000000EUL /*!< TFBGA225 package type */
#endif /* SYSCFG_PKGR_PKG */
/**
* @}
@ -355,7 +355,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,
uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
/**
* @}

41
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal.c
View File

@ -47,10 +47,10 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
* @brief STM32H7xx HAL Driver version number V1.7.0
* @brief STM32H7xx HAL Driver version number V1.8.0
*/
#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
#define __STM32H7xx_HAL_VERSION_SUB1 (0x07UL) /*!< [23:16] sub1 version */
#define __STM32H7xx_HAL_VERSION_SUB1 (0x08UL) /*!< [23:16] sub1 version */
#define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */
#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
@ -134,6 +134,8 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
HAL_StatusTypeDef HAL_Init(void)
{
uint32_t common_system_clock;
#if defined(DUAL_CORE) && defined(CORE_CM4)
/* Configure Cortex-M4 Instruction cache through ART accelerator */
__HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */
@ -146,18 +148,24 @@ HAL_StatusTypeDef HAL_Init(void)
/* Update the SystemCoreClock global variable */
#if defined(RCC_D1CFGR_D1CPRE)
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
#else
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
#endif
/* Update the SystemD2Clock global variable */
#if defined(RCC_D1CFGR_HPRE)
SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
#endif /* DUAL_CORE && CORE_CM4 */
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
{
@ -259,32 +267,11 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
return HAL_ERROR;
}
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Cortex-M7 detected */
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
{
return HAL_ERROR;
}
}
else
{
/* Cortex-M4 detected */
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000UL / (uint32_t)uwTickFreq)) > 0U)
{
return HAL_ERROR;
}
}
#else
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
{
return HAL_ERROR;
}
#endif
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))

6
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dac.c
View File

@ -1112,15 +1112,15 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
/* Clear DAC_MCR_MODEx bits */
tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
/* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
if ((sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_EXTERNAL) == DAC_CHIPCONNECT_EXTERNAL)
if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
{
connectOnChip = 0x00000000UL;
}
else if ((sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_INTERNAL) == DAC_CHIPCONNECT_INTERNAL)
else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL)
{
connectOnChip = DAC_MCR_MODE1_0;
}
else /* (sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_BOTH) == DAC_CHIPCONNECT_BOTH */
else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */
{
if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE)
{

27
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dma.c
View File

@ -146,6 +146,19 @@ typedef struct
#define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U)
#if defined(UART9)
#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
(((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
(((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
(((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )) || \
(((__REQUEST__) >= DMA_REQUEST_UART9_RX) && ((__REQUEST__) <= DMA_REQUEST_USART10_TX )))
#else
#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
(((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
(((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
(((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )))
#endif
/**
* @}
*/
@ -278,6 +291,20 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
}
/* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be
lock when transfering data to/from USART/UART */
#if (STM32H7_DEV_ID == 0x450UL)
if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
{
#endif /* STM32H7_DEV_ID == 0x450UL */
if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U)
{
registerValue |= DMA_SxCR_TRBUFF;
}
#if (STM32H7_DEV_ID == 0x450UL)
}
#endif /* STM32H7_DEV_ID == 0x450UL */
/* Write to DMA Stream CR register */
((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue;

54
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_gpio.c
View File

@ -198,26 +198,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
if (iocurrent != 0x00U)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
temp &= ~(0xFU << ((position & 0x07U) * 4U));
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
GPIOx->AFR[position >> 3U] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
GPIOx->MODER = temp;
/* In case of Output or Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
@ -243,6 +223,26 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
temp |= ((GPIO_Init->Pull) << (position * 2U));
GPIOx->PUPDR = temp;
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
temp &= ~(0xFU << ((position & 0x07U) * 4U));
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
GPIOx->AFR[position >> 3U] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
GPIOx->MODER = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
@ -333,9 +333,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
tmp &= (0x0FUL << (4U * (position & 0x03U)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
{
tmp = 0x0FUL << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
/* Clear EXTI line configuration for Current CPU */
EXTI_CurrentCPU->IMR1 &= ~(iocurrent);
EXTI_CurrentCPU->EMR1 &= ~(iocurrent);
@ -343,6 +340,9 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/* Clear Rising Falling edge configuration */
EXTI->RTSR1 &= ~(iocurrent);
EXTI->FTSR1 &= ~(iocurrent);
tmp = 0x0FUL << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/
@ -352,14 +352,14 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ;
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
}
position++;

221
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_i2c.c
View File

@ -351,13 +351,13 @@
/* Private define to centralize the enable/disable of Interrupts */
#define I2C_XFER_TX_IT (0x00000001U)
#define I2C_XFER_RX_IT (0x00000002U)
#define I2C_XFER_LISTEN_IT (0x00000004U)
#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */
#define I2C_XFER_ERROR_IT (0x00000011U)
#define I2C_XFER_CPLT_IT (0x00000012U)
#define I2C_XFER_RELOAD_IT (0x00000012U)
#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */
#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */
#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */
/* Private define Sequential Transfer Options default/reset value */
#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
@ -410,6 +410,9 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
/* Private function to treat different error callback */
static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
/* Private function to flush TXDR register */
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
@ -4251,9 +4254,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
/* Process Locked */
__HAL_LOCK(hi2c);
/* Disable Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
/* Disable Interrupts and Store Previous state */
if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
}
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
}
else
{
/* Do nothing */
}
/* Set State at HAL_I2C_STATE_ABORT */
hi2c->State = HAL_I2C_STATE_ABORT;
@ -5001,6 +5016,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
{
uint32_t tmpoptions = hi2c->XferOptions;
uint32_t treatdmanack = 0U;
HAL_I2C_StateTypeDef tmpstate;
/* Process locked */
__HAL_LOCK(hi2c);
@ -5079,8 +5095,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
/* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
tmpstate = hi2c->State;
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
{
if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
{
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
}
else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
}
else
{
/* Do nothing */
}
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
}
@ -5369,9 +5401,27 @@ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
*/
static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
}
else
{
/* Do nothing */
}
if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
/* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
@ -5426,19 +5476,36 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmperror;
uint32_t tmpITFlags = ITFlags;
uint32_t tmp;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Disable Interrupts and Store Previous state */
if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
}
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
}
else
{
/* Do nothing */
}
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
/* Reset handle parameters */
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = NULL;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET)
if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@ -5447,12 +5514,18 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
/* Fetch Last receive data if any */
if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
{
/* Read data from RXDR */
tmp = (uint8_t)hi2c->Instance->RXDR;
UNUSED(tmp);
}
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
/* Disable Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
/* Store current volatile hi2c->ErrorCode, misra rule */
tmperror = hi2c->ErrorCode;
@ -5466,6 +5539,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
@ -5500,6 +5574,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
@ -5546,12 +5621,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
uint32_t tmpITFlags = ITFlags;
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
/* Disable Interrupts and Store Previous state */
if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
}
else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
}
else
{
/* Do nothing */
}
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@ -5565,6 +5654,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
if (hi2c->hdmatx != NULL)
{
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
@ -5572,6 +5664,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
if (hi2c->hdmarx != NULL)
{
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
@ -5608,7 +5703,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
@ -5631,6 +5725,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -5646,6 +5741,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -5660,6 +5756,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
else
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -5733,6 +5830,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
uint32_t tmppreviousstate;
/* Reset handle parameters */
hi2c->Mode = HAL_I2C_MODE_NONE;
@ -5752,7 +5850,6 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
/* keep HAL_I2C_STATE_LISTEN if set */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = I2C_Slave_ISR_IT;
}
else
@ -5767,16 +5864,19 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
/* Set HAL_I2C_STATE_READY */
hi2c->State = HAL_I2C_STATE_READY;
}
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = NULL;
}
/* Abort DMA TX transfer if any */
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
tmppreviousstate = hi2c->PreviousState;
if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
}
if (hi2c->hdmatx != NULL)
if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@ -5792,13 +5892,20 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
}
}
else
{
I2C_TreatErrorCallback(hi2c);
}
}
/* Abort DMA RX transfer if any */
else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
{
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
{
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
}
if (hi2c->hdmarx != NULL)
if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@ -5814,10 +5921,28 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
}
}
else
{
I2C_TreatErrorCallback(hi2c);
}
}
else if (hi2c->State == HAL_I2C_STATE_ABORT)
else
{
I2C_TreatErrorCallback(hi2c);
}
}
/**
* @brief I2C Error callback treatment.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
{
if (hi2c->State == HAL_I2C_STATE_ABORT)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -5831,6 +5956,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
}
else
{
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -6062,30 +6189,16 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Reset AbortCpltCallback */
hi2c->hdmatx->XferAbortCallback = NULL;
hi2c->hdmarx->XferAbortCallback = NULL;
/* Check if come from abort from user */
if (hi2c->State == HAL_I2C_STATE_ABORT)
if (hi2c->hdmatx != NULL)
{
hi2c->State = HAL_I2C_STATE_READY;
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->AbortCpltCallback(hi2c);
#else
HAL_I2C_AbortCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
hi2c->hdmatx->XferAbortCallback = NULL;
}
else
if (hi2c->hdmarx != NULL)
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->ErrorCallback(hi2c);
#else
HAL_I2C_ErrorCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
hi2c->hdmarx->XferAbortCallback = NULL;
}
I2C_TreatErrorCallback(hi2c);
}
/**
@ -6362,19 +6475,19 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
}
if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
@ -6400,7 +6513,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
@ -6454,19 +6567,19 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
}
if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;

100
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_jpeg.c
View File

@ -1100,7 +1100,11 @@ HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg
HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf)
{
uint32_t error;
uint32_t numberMCU, hfactor, vfactor, hMCU, vMCU;
uint32_t numberMCU;
uint32_t hfactor;
uint32_t vfactor;
uint32_t hMCU;
uint32_t vMCU;
/* Check the JPEG handle allocation */
if ((hjpeg == NULL) || (pConf == NULL))
@ -1285,7 +1289,9 @@ HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTy
*/
HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
{
uint32_t yblockNb, cBblockNb, cRblockNb;
uint32_t yblockNb;
uint32_t cBblockNb;
uint32_t cRblockNb;
/* Check the JPEG handle allocation */
if ((hjpeg == NULL) || (pInfo == NULL))
@ -2192,7 +2198,8 @@ void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputB
*/
HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg)
{
uint32_t tickstart, tmpContext;
uint32_t tickstart;
uint32_t tmpContext;
tmpContext = hjpeg->Context;
/*Reset the Context operation and method*/
@ -2522,7 +2529,11 @@ uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg)
*/
static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK)
{
uint32_t i, p, l, code, si;
uint32_t i;
uint32_t p;
uint32_t l;
uint32_t code;
uint32_t si;
/* Figure C.1: Generation of table of Huffman code sizes */
p = 0;
@ -2688,7 +2699,9 @@ static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCH
{
HAL_StatusTypeDef error;
JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable;
uint32_t i, lsb, msb;
uint32_t i;
uint32_t lsb;
uint32_t msb;
__IO uint32_t *address, *addressDef;
if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC0))
@ -3053,7 +3066,11 @@ static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg)
static uint32_t JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable,
__IO uint32_t *QTableAddress)
{
uint32_t i, j, quantRow, quantVal, ScaleFactor;
uint32_t i;
uint32_t j;
uint32_t quantRow;
uint32_t quantVal;
uint32_t ScaleFactor;
__IO uint32_t *tableAddress;
tableAddress = QTableAddress;
@ -3455,7 +3472,10 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg)
*/
static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords)
{
uint32_t index, nBwords, nbBytes, dataword;
uint32_t index;
uint32_t nb_words;
uint32_t nb_bytes;
uint32_t dataword;
if (hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords * 4UL)))
{
@ -3482,8 +3502,8 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor
}
else if (hjpeg->OutDataLength > hjpeg->JpegOutCount)
{
nBwords = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL;
for (index = 0; index < nBwords; index++)
nb_words = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL;
for (index = 0; index < nb_words; index++)
{
/*Transfer 32 bits from the JPEG output FIFO*/
dataword = hjpeg->Instance->DOR;
@ -3505,9 +3525,9 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor
}
else
{
nbBytes = hjpeg->OutDataLength - hjpeg->JpegOutCount;
nb_bytes = hjpeg->OutDataLength - hjpeg->JpegOutCount;
dataword = hjpeg->Instance->DOR;
for (index = 0; index < nbBytes; index++)
for (index = 0; index < nb_bytes; index++)
{
hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * (index & 0x3UL))) & 0xFFUL);
hjpeg->JpegOutCount++;
@ -3521,8 +3541,8 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor
hjpeg->JpegOutCount = 0;
nbBytes = 4UL - nbBytes;
for (index = nbBytes; index < 4UL; index++)
nb_bytes = 4UL - nb_bytes;
for (index = nb_bytes; index < 4UL; index++)
{
hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * index)) & 0xFFUL);
hjpeg->JpegOutCount++;
@ -3546,7 +3566,11 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor
*/
static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords)
{
uint32_t nbBytes = 0, nBwords, index, Dataword, inputCount;
uint32_t nb_bytes = 0;
uint32_t nb_words;
uint32_t index;
uint32_t dataword;
uint32_t input_count;
if ((hjpeg->InDataLength == 0UL) || (nbRequestWords == 0UL))
{
@ -3555,7 +3579,7 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord
}
else if (hjpeg->InDataLength > hjpeg->JpegInCount)
{
nbBytes = hjpeg->InDataLength - hjpeg->JpegInCount;
nb_bytes = hjpeg->InDataLength - hjpeg->JpegInCount;
}
else if (hjpeg->InDataLength == hjpeg->JpegInCount)
{
@ -3571,39 +3595,39 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord
hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL);
}
hjpeg->JpegInCount = 0;
nbBytes = hjpeg->InDataLength;
nb_bytes = hjpeg->InDataLength;
}
else
{
/* Nothing to do */
}
if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nbBytes > 0UL))
if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nb_bytes > 0UL))
{
nBwords = nbBytes / 4UL;
if (nBwords >= nbRequestWords)
nb_words = nb_bytes / 4UL;
if (nb_words >= nbRequestWords)
{
for (index = 0; index < nbRequestWords; index++)
{
inputCount = hjpeg->JpegInCount;
hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | \
(((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1UL])) << 8) | \
(((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2UL])) << 16) | \
(((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3UL])) << 24));
input_count = hjpeg->JpegInCount;
hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \
(((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \
(((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \
(((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24));
hjpeg->JpegInCount += 4UL;
}
}
else /*nBwords < nbRequestWords*/
else /*nb_words < nbRequestWords*/
{
if (nBwords > 0UL)
if (nb_words > 0UL)
{
for (index = 0; index < nBwords; index++)
for (index = 0; index < nb_words; index++)
{
inputCount = hjpeg->JpegInCount;
hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | \
(((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1UL])) << 8) | \
(((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2UL])) << 16) | \
(((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3UL])) << 24));
input_count = hjpeg->JpegInCount;
hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \
(((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \
(((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \
(((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24));
hjpeg->JpegInCount += 4UL;
}
@ -3611,13 +3635,13 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord
else
{
/* end of file*/
Dataword = 0;
for (index = 0; index < nbBytes; index++)
dataword = 0;
for (index = 0; index < nb_bytes; index++)
{
Dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL));
dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL));
hjpeg->JpegInCount++;
}
hjpeg->Instance->DIR = Dataword;
hjpeg->Instance->DIR = dataword;
}
}
}
@ -3850,7 +3874,9 @@ static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg)
*/
static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg)
{
uint32_t tmpContext, count, dataOut;
uint32_t tmpContext;
uint32_t count;
uint32_t dataOut;
for (count = JPEG_FIFO_SIZE; count > 0UL; count--)
{

213
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_lptim.c
View File

@ -174,7 +174,6 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @addtogroup LPTIM_Private_Constants
* @{
*/
@ -183,6 +182,7 @@
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
@ -235,16 +235,19 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
{
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
}
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
{
assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
@ -278,13 +281,17 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
{
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL));
}
if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL));
}
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
{
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT));
}
/* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
@ -298,25 +305,35 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
hlptim->Init.UpdateMode |
hlptim->Init.CounterSource);
if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
/* Glitch filters for internal triggers and external inputs are configured
* only if an internal clock source is provided to the LPTIM
*/
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
{
tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
hlptim->Init.UltraLowPowerClock.SampleTime);
}
if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
/* Configure the active edge or edges used by the counter only if LPTIM is
* clocked by an external clock source
*/
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
{
tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity);
}
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable External trigger and set the trigger source */
tmpcfgr |= (hlptim->Init.Trigger.Source |
hlptim->Init.Trigger.ActiveEdge |
hlptim->Init.Trigger.SampleTime);
tmpcfgr |= (hlptim->Init.Trigger.Source |
hlptim->Init.Trigger.ActiveEdge);
}
/* Write to LPTIMx CFGR */
hlptim->Instance->CFGR = tmpcfgr;
/* Configure LPTIM input sources */
if ((hlptim->Instance == LPTIM1)||(hlptim->Instance == LPTIM2))
if ((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM2))
{
/* Check LPTIM Input1 and Input2 sources */
assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
@ -327,7 +344,7 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
}
else
{
if(hlptim->Instance == LPTIM3)
if (hlptim->Instance == LPTIM3)
{
/* Check LPTIM3 Input1 source */
assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
@ -2307,17 +2324,17 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t
{
HAL_StatusTypeDef result = HAL_OK;
uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
do
do
{
count--;
if (count == 0UL)
{
count--;
if (count == 0UL)
{
result = HAL_TIMEOUT;
}
result = HAL_TIMEOUT;
}
while((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
}
while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
return result;
return result;
}
/**
@ -2344,29 +2361,29 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
/* Save LPTIM source clock */
switch ((uint32_t)hlptim->Instance)
{
case LPTIM1_BASE:
tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
break;
case LPTIM2_BASE:
tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE();
break;
case LPTIM1_BASE:
tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
break;
case LPTIM2_BASE:
tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE();
break;
#if defined(LPTIM3)
case LPTIM3_BASE:
tmpclksource = __HAL_RCC_GET_LPTIM3_SOURCE();
break;
case LPTIM3_BASE:
tmpclksource = __HAL_RCC_GET_LPTIM3_SOURCE();
break;
#endif /* LPTIM3 */
#if defined(LPTIM4)
case LPTIM4_BASE:
tmpclksource = __HAL_RCC_GET_LPTIM4_SOURCE();
break;
case LPTIM4_BASE:
tmpclksource = __HAL_RCC_GET_LPTIM4_SOURCE();
break;
#endif /* LPTIM4 */
#if defined(LPTIM5)
case LPTIM5_BASE:
tmpclksource = __HAL_RCC_GET_LPTIM5_SOURCE();
break;
case LPTIM5_BASE:
tmpclksource = __HAL_RCC_GET_LPTIM5_SOURCE();
break;
#endif /* LPTIM5 */
default:
break;
default:
break;
}
/* Save LPTIM configuration registers */
@ -2379,34 +2396,34 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
/*********** Reset LPTIM ***********/
switch ((uint32_t)hlptim->Instance)
{
case LPTIM1_BASE:
__HAL_RCC_LPTIM1_FORCE_RESET();
__HAL_RCC_LPTIM1_RELEASE_RESET();
break;
case LPTIM2_BASE:
__HAL_RCC_LPTIM2_FORCE_RESET();
__HAL_RCC_LPTIM2_RELEASE_RESET();
break;
case LPTIM1_BASE:
__HAL_RCC_LPTIM1_FORCE_RESET();
__HAL_RCC_LPTIM1_RELEASE_RESET();
break;
case LPTIM2_BASE:
__HAL_RCC_LPTIM2_FORCE_RESET();
__HAL_RCC_LPTIM2_RELEASE_RESET();
break;
#if defined(LPTIM3)
case LPTIM3_BASE:
__HAL_RCC_LPTIM3_FORCE_RESET();
__HAL_RCC_LPTIM3_RELEASE_RESET();
break;
case LPTIM3_BASE:
__HAL_RCC_LPTIM3_FORCE_RESET();
__HAL_RCC_LPTIM3_RELEASE_RESET();
break;
#endif /* LPTIM3 */
#if defined(LPTIM4)
case LPTIM4_BASE:
__HAL_RCC_LPTIM4_FORCE_RESET();
__HAL_RCC_LPTIM4_RELEASE_RESET();
break;
case LPTIM4_BASE:
__HAL_RCC_LPTIM4_FORCE_RESET();
__HAL_RCC_LPTIM4_RELEASE_RESET();
break;
#endif /* LPTIM4 */
#if defined(LPTIM5)
case LPTIM5_BASE:
__HAL_RCC_LPTIM5_FORCE_RESET();
__HAL_RCC_LPTIM5_RELEASE_RESET();
break;
case LPTIM5_BASE:
__HAL_RCC_LPTIM5_FORCE_RESET();
__HAL_RCC_LPTIM5_RELEASE_RESET();
break;
#endif /* LPTIM5 */
default:
break;
default:
break;
}
/*********** Restore LPTIM Config ***********/
@ -2415,29 +2432,29 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
/* Force LPTIM source kernel clock from APB */
switch ((uint32_t)hlptim->Instance)
{
case LPTIM1_BASE:
__HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_D2PCLK1);
break;
case LPTIM2_BASE:
__HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_D3PCLK1);
break;
case LPTIM1_BASE:
__HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_D2PCLK1);
break;
case LPTIM2_BASE:
__HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_D3PCLK1);
break;
#if defined(LPTIM3)
case LPTIM3_BASE:
__HAL_RCC_LPTIM3_CONFIG(RCC_LPTIM3CLKSOURCE_D3PCLK1);
break;
case LPTIM3_BASE:
__HAL_RCC_LPTIM3_CONFIG(RCC_LPTIM3CLKSOURCE_D3PCLK1);
break;
#endif /* LPTIM3 */
#if defined(LPTIM4)
case LPTIM4_BASE:
__HAL_RCC_LPTIM4_CONFIG(RCC_LPTIM4CLKSOURCE_D3PCLK1);
break;
case LPTIM4_BASE:
__HAL_RCC_LPTIM4_CONFIG(RCC_LPTIM4CLKSOURCE_D3PCLK1);
break;
#endif /* LPTIM4 */
#if defined(LPTIM5)
case LPTIM5_BASE:
__HAL_RCC_LPTIM5_CONFIG(RCC_LPTIM5CLKSOURCE_D3PCLK1);
break;
case LPTIM5_BASE:
__HAL_RCC_LPTIM5_CONFIG(RCC_LPTIM5CLKSOURCE_D3PCLK1);
break;
#endif /* LPTIM5 */
default:
break;
default:
break;
}
if (tmpCMP != 0UL)
@ -2472,29 +2489,29 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
/* Restore LPTIM source kernel clock */
switch ((uint32_t)hlptim->Instance)
{
case LPTIM1_BASE:
__HAL_RCC_LPTIM1_CONFIG(tmpclksource);
break;
case LPTIM2_BASE:
__HAL_RCC_LPTIM2_CONFIG(tmpclksource);
break;
case LPTIM1_BASE:
__HAL_RCC_LPTIM1_CONFIG(tmpclksource);
break;
case LPTIM2_BASE:
__HAL_RCC_LPTIM2_CONFIG(tmpclksource);
break;
#if defined(LPTIM3)
case LPTIM3_BASE:
__HAL_RCC_LPTIM3_CONFIG(tmpclksource);
break;
case LPTIM3_BASE:
__HAL_RCC_LPTIM3_CONFIG(tmpclksource);
break;
#endif /* LPTIM3 */
#if defined(LPTIM4)
case LPTIM4_BASE:
__HAL_RCC_LPTIM4_CONFIG(tmpclksource);
break;
case LPTIM4_BASE:
__HAL_RCC_LPTIM4_CONFIG(tmpclksource);
break;
#endif /* LPTIM4 */
#if defined(LPTIM5)
case LPTIM5_BASE:
__HAL_RCC_LPTIM5_CONFIG(tmpclksource);
break;
case LPTIM5_BASE:
__HAL_RCC_LPTIM5_CONFIG(tmpclksource);
break;
#endif /* LPTIM5 */
default:
break;
default:
break;
}
}

131
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_mmc.c
View File

@ -387,7 +387,6 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
{
uint32_t errorstate;
MMC_InitTypeDef Init;
HAL_StatusTypeDef status;
/* Default SDMMC peripheral configuration for MMC card initialization */
Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
@ -397,18 +396,10 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
Init.ClockDiv = SDMMC_INIT_CLK_DIV;
/* Initialize SDMMC peripheral interface with default configuration */
status = SDMMC_Init(hmmc->Instance, Init);
if(status == HAL_ERROR)
{
return HAL_ERROR;
}
(void)SDMMC_Init(hmmc->Instance, Init);
/* Set Power State to ON */
status = SDMMC_PowerState_ON(hmmc->Instance);
if(status == HAL_ERROR)
{
return HAL_ERROR;
}
(void)SDMMC_PowerState_ON(hmmc->Instance);
/* Identify card operating voltage */
errorstate = MMC_PowerON(hmmc);
@ -428,6 +419,17 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
return HAL_ERROR;
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
return HAL_OK;
}
@ -568,20 +570,6 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
add *= 512U;
}
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
{
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
@ -755,20 +743,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
add *= 512U;
}
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
{
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
@ -943,20 +917,6 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
add *= 512U;
}
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
{
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
@ -1050,20 +1010,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData
add *= 512U;
}
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
{
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
@ -1158,20 +1104,6 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData
add *= 512U;
}
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
{
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode = errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
@ -1268,20 +1200,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat
add *= 512U;
}
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
{
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
@ -2755,29 +2673,6 @@ HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData,
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = 0;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
{
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = 512;

168
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_ospi.c
View File

@ -377,11 +377,8 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
#endif
/* Configure the default timeout for the OSPI memory access */
status = HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
}
(void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
if (status == HAL_OK)
{
/* Configure memory type, device size, chip select high time, clocked chip select high time, delay block bypass, free running clock, clock mode */
MODIFY_REG(hospi->Instance->DCR1,
(OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_CKCSHT |
@ -408,33 +405,33 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
if (status == HAL_OK)
{
/* Configure clock prescaler */
MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
/* Configure clock prescaler */
MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
/* Configure Dual Quad mode */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad);
/* Configure Dual Quad mode */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad);
/* Configure sample shifting and delay hold quarter cycle */
MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
/* Configure sample shifting and delay hold quarter cycle */
MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
/* Enable OctoSPI */
__HAL_OSPI_ENABLE(hospi);
/* Enable OctoSPI */
__HAL_OSPI_ENABLE(hospi);
/* Enable free running clock if needed : must be done after OSPI enable */
if (hospi->Init.FreeRunningClock == HAL_OSPI_FREERUNCLK_ENABLE)
{
SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
}
/* Enable free running clock if needed : must be done after OSPI enable */
if (hospi->Init.FreeRunningClock == HAL_OSPI_FREERUNCLK_ENABLE)
{
SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
}
/* Initialize the OSPI state */
if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
{
hospi->State = HAL_OSPI_STATE_HYPERBUS_INIT;
}
else
{
hospi->State = HAL_OSPI_STATE_READY;
}
/* Initialize the OSPI state */
if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
{
hospi->State = HAL_OSPI_STATE_HYPERBUS_INIT;
}
else
{
hospi->State = HAL_OSPI_STATE_READY;
}
}
}
}
@ -2457,6 +2454,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *
assert_param(IS_OSPIM_PORT(cfg->NCSPort));
assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort));
assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort));
assert_param(IS_OSPIM_REQ2ACKTIME(cfg->Req2AckTime));
if (hospi->Instance == OCTOSPI1)
{
@ -2494,13 +2492,29 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *
}
/***************** Deactivation of previous configuration *****************/
if (IOM_cfg[instance].ClkPort != 0U)
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U)
{
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
/* De-multiplexing should be performed */
CLEAR_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN);
if (other_instance == 1U)
{
SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKSRC);
SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSSRC);
SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLSRC_1);
SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHSRC_1);
}
}
else
{
if (IOM_cfg[instance].ClkPort != 0U)
{
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
}
}
/********************* Deactivation of other instance *********************/
@ -2508,38 +2522,79 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *
(cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) ||
(cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
{
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) &&
(cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) && (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
{
/* Multiplexing should be performed */
SET_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN);
}
else
{
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
}
}
/******************** Activation of new configuration *********************/
MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort-1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos)));
if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
if ((cfg->Req2AckTime - 1U) > ((OCTOSPIM->CR & OCTOSPIM_CR_REQ2ACK_TIME) >> OCTOSPIM_CR_REQ2ACK_TIME_Pos))
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
(OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
}
else
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
(OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
MODIFY_REG(OCTOSPIM->CR, OCTOSPIM_CR_REQ2ACK_TIME, ((cfg->Req2AckTime - 1U) << OCTOSPIM_CR_REQ2ACK_TIME_Pos));
}
if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U)
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
(OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), OCTOSPIM_PCR_CLKEN);
MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN);
if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN);
}
else
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN);
}
if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0));
}
else
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0));
}
}
else
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
(OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
(OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
}
else
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
(OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
}
if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
(OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
}
else
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
(OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
}
}
/******* Re-enable both OctoSPI after configure OctoSPI IO Manager ********/
@ -2905,7 +2960,14 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *
if (instance_nb == 2U)
{
value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) == 0U)
{
value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
}
else
{
value = OCTOSPIM_PCR_NCSSRC;
}
}
/* Get the information about the instance */

17
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_pssi.c
View File

@ -185,6 +185,7 @@ void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
void PSSI_DMAError(DMA_HandleTypeDef *hdma);
void PSSI_DMAAbort(DMA_HandleTypeDef *hdma);
/* Private functions to handle IT transfer */
static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode);
@ -613,6 +614,10 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u
uint32_t tickstart;
uint32_t transfer_size = Size;
#if defined (__GNUC__)
__IO uint16_t *pdr_16bits = (__IO uint16_t *)(&(hpssi->Instance->DR));
#endif /* __GNUC__ */
if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size%2U) != 0U)) ||
((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size%4U) != 0U)))
@ -682,7 +687,11 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u
return HAL_ERROR;
}
/* Write data to DR */
#if defined (__GNUC__)
*pdr_16bits = *pbuffer;
#else
*(__IO uint16_t *)((uint32_t)(&hpssi->Instance->DR)) = *pbuffer;
#endif /* __GNUC__ */
/* Increment Buffer pointer */
pbuffer++;
@ -763,6 +772,9 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui
{
uint32_t tickstart;
uint32_t transfer_size = Size;
#if defined (__GNUC__)
__IO uint16_t *pdr_16bits = (__IO uint16_t *)(&(hpssi->Instance->DR));
#endif /* __GNUC__ */
if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size%2U) != 0U)) ||
@ -833,7 +845,12 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui
}
/* Read data from DR */
#if defined (__GNUC__)
*pbuffer = *pdr_16bits;
#else
*pbuffer = *(__IO uint16_t *)((uint32_t)&hpssi->Instance->DR);
#endif /* __GNUC__ */
pbuffer++;
transfer_size -= 2U;

418
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_qspi.c
View File

@ -24,7 +24,7 @@
[..]
(#) As prerequisite, fill in the HAL_QSPI_MspInit() :
(++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
(++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
(++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
(++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
(++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
(++) If interrupt mode is used, enable and configure QuadSPI global
@ -64,7 +64,7 @@
(++) In polling mode, the output of the function is done when the transfer is complete.
(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
(++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
(++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
*** Auto-polling functional mode ***
====================================
@ -137,7 +137,7 @@
(++) In polling mode, the output of the function is done when the transfer
complete bit is set and the busy bit cleared.
(++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
the transfer complete bi is set.
the transfer complete bit is set.
*** Control functions ***
=========================
@ -146,6 +146,7 @@
(#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
(#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
(#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
(#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed.
*** Callback registration ***
=============================================
@ -218,7 +219,7 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@ -226,18 +227,17 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
#if defined(QUADSPI)
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#ifdef HAL_QSPI_MODULE_ENABLED
#if defined(QUADSPI)
/** @defgroup QSPI QSPI
* @brief QSPI HAL module driver
* @{
*/
#ifdef HAL_QSPI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
@ -245,7 +245,7 @@
/** @defgroup QSPI_Private_Constants QSPI Private Constants
* @{
*/
#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!<Indirect write mode*/
#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U /*!<Indirect write mode*/
#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/
@ -300,7 +300,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
/**
* @brief Initialize the QSPI mode according to the specified parameters
* in the QSPI_InitTypeDef and initialize the associated handle.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
@ -329,13 +329,8 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
}
/* Process locked */
__HAL_LOCK(hqspi);
if(hqspi->State == HAL_QSPI_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hqspi->Lock = HAL_UNLOCKED;
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
/* Reset Callback pointers in HAL_QSPI_STATE_RESET only */
@ -359,8 +354,9 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
/* Init the low level hardware : GPIO, CLOCK */
HAL_QSPI_MspInit(hqspi);
#endif
/* Configure the default timeout for the QSPI memory access */
HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
}
/* Configure QSPI FIFO Threshold */
@ -392,16 +388,13 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
hqspi->State = HAL_QSPI_STATE_READY;
}
/* Release Lock */
__HAL_UNLOCK(hqspi);
/* Return function status */
return status;
}
/**
* @brief De-Initialize the QSPI peripheral.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
@ -412,9 +405,6 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hqspi);
/* Disable the QSPI Peripheral Clock */
__HAL_QSPI_DISABLE(hqspi);
@ -437,15 +427,12 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
/* Initialize the QSPI state */
hqspi->State = HAL_QSPI_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hqspi);
return HAL_OK;
}
/**
* @brief Initialize the QSPI MSP.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
@ -460,7 +447,7 @@ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
/**
* @brief DeInitialize the QSPI MSP.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
@ -499,7 +486,7 @@ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
/**
* @brief Handle QSPI interrupt request.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
@ -509,7 +496,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
uint32_t itsource = READ_REG(hqspi->Instance->CR);
/* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
if(((flag & QSPI_FLAG_FT) == QSPI_FLAG_FT) && ((itsource & QSPI_IT_FT) == QSPI_IT_FT))
if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U))
{
data_reg = &hqspi->Instance->DR;
@ -521,7 +508,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
if (hqspi->TxXferCount > 0U)
{
/* Fill the FIFO until the threshold is reached */
*(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr;
*((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
hqspi->pTxBuffPtr++;
hqspi->TxXferCount--;
}
@ -542,7 +529,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
if (hqspi->RxXferCount > 0U)
{
/* Read the FIFO until the threshold is reached */
*hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
*hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
@ -559,6 +546,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
{
/* Nothing to do */
}
/* FIFO Threshold callback */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->FifoThresholdCallback(hqspi);
@ -568,7 +556,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* QSPI Transfer Complete interrupt occurred -------------------------------*/
else if(((flag & QSPI_FLAG_TC) == QSPI_FLAG_TC) && ((itsource & QSPI_IT_TC) == QSPI_IT_TC))
else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
@ -579,7 +567,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
/* Transfer complete callback */
if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
{
if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@ -588,6 +576,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
__HAL_MDMA_DISABLE(hqspi->hmdma);
}
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@ -600,7 +589,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
{
if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@ -616,7 +605,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
if (hqspi->RxXferCount > 0U)
{
/* Read the last data received in the FIFO until it is empty */
*hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
*hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
@ -628,6 +617,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
}
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@ -688,7 +678,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* QSPI Status Match interrupt occurred ------------------------------------*/
else if(((flag & QSPI_FLAG_SM)== QSPI_FLAG_SM) && ((itsource & QSPI_IT_SM) == QSPI_IT_SM))
else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
@ -712,7 +702,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* QSPI Transfer Error interrupt occurred ----------------------------------*/
else if(((flag & QSPI_FLAG_TE) == QSPI_FLAG_TE) && ((itsource & QSPI_IT_TE) == QSPI_IT_TE))
else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
@ -723,7 +713,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
/* Set error code */
hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@ -761,7 +751,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* QSPI Timeout interrupt occurred -----------------------------------------*/
else if(((flag & QSPI_FLAG_TO) == QSPI_FLAG_TO) && ((itsource & QSPI_IT_TO) == QSPI_IT_TO))
else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
@ -773,6 +763,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
HAL_QSPI_TimeOutCallback(hqspi);
#endif
}
else
{
/* Nothing to do */
@ -781,7 +772,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
/**
* @brief Set the command configuration.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information
* @param Timeout : Timeout duration
* @note This function is used only in Indirect Read or Write Modes
@ -849,7 +840,6 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe
/* Update QSPI state */
hqspi->State = HAL_QSPI_STATE_READY;
}
}
else
{
@ -872,7 +862,7 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe
/**
* @brief Set the command configuration in interrupt mode.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
@ -971,10 +961,11 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp
/**
* @brief Transmit an amount of data in blocking mode.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer
* @param Timeout : Timeout duration
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
@ -1013,7 +1004,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u
break;
}
*(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr;
*((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
hqspi->pTxBuffPtr++;
hqspi->TxXferCount--;
}
@ -1054,8 +1045,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u
/**
* @brief Receive an amount of data in blocking mode.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer
* @param Timeout : Timeout duration
* @note This function is used only in Indirect Read Mode
* @retval HAL status
@ -1100,7 +1091,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
break;
}
*hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
*hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
@ -1114,6 +1105,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
{
/* Clear Transfer Complete bit */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
}
}
@ -1139,8 +1131,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
/**
* @brief Send an amount of data in non-blocking mode with interrupt.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
@ -1199,8 +1191,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData
/**
* @brief Receive an amount of data in non-blocking mode with interrupt.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@ -1263,18 +1255,15 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
/**
* @brief Send an amount of data in non-blocking mode with DMA.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @note If MDMA peripheral access is configured as halfword, the number
* of data and the fifo threshold should be aligned on halfword
* @note If MDMA peripheral access is configured as word, the number
* of data and the fifo threshold should be aligned on word
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
/* Process locked */
__HAL_LOCK(hqspi);
@ -1286,64 +1275,75 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat
if(pData != NULL )
{
/* Configure counters of the handle */
hqspi->TxXferCount = data_size;
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
/* Configure counters and size of the handle */
hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->pTxBuffPtr = pData;
/* Configure size and pointer of the handle */
hqspi->TxXferSize = hqspi->TxXferCount;
hqspi->pTxBuffPtr = pData;
/* Configure QSPI: CCR register with functional mode as indirect write */
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
/* Configure QSPI: CCR register with functional mode as indirect write */
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
/* Set the QSPI MDMA transfer complete callback */
hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt;
/* Set the QSPI MDMA transfer complete callback */
hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt;
/* Set the MDMA error callback */
hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
/* Set the MDMA error callback */
hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
/* Clear the MDMA abort callback */
hqspi->hmdma->XferAbortCallback = NULL;
/* Clear the MDMA abort callback */
hqspi->hmdma->XferAbortCallback = NULL;
/* In Transmit mode , the MDMA destination is the QSPI DR register : Force the MDMA Destination Increment to disable */
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE);
/* In Transmit mode , the MDMA destination is the QSPI DR register : Force the MDMA Destination Increment to disable */
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE);
/* Update MDMA configuration with the correct SourceInc field for Write operation */
if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE)
{
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE);
}
else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD)
{
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD);
}
else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD)
{
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD);
}
else
{
/* in case of incorrect source data size */
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
status = HAL_ERROR;
}
/* Update MDMA configuration with the correct SourceInc field for Write operation */
if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE)
{
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE);
}
else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD)
{
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD);
}
else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD)
{
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD);
}
else
{
/* in case of incorrect source data size */
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
status = HAL_ERROR;
}
/* Enable the QSPI transfer error and complete Interrupts : Workaround for QSPI low kernel clock frequency */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE |QSPI_IT_TC);
/* Enable the QSPI transmit MDMA */
if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK)
{
/* Process unlocked */
__HAL_UNLOCK(hqspi);
/* Enable the QSPI transmit MDMA */
if(HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK)
{
/* Process unlocked */
__HAL_UNLOCK(hqspi);
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
/* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
}
/* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
}
else
{
status = HAL_ERROR;
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
hqspi->State = HAL_QSPI_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
}
else
{
@ -1367,8 +1367,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer.
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer.
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@ -1376,6 +1376,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
/* Process locked */
__HAL_LOCK(hqspi);
@ -1387,35 +1388,26 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
if(pData != NULL )
{
/* Configure counters of the handle */
hqspi->RxXferCount = data_size;
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
/* Configure size and pointer of the handle */
hqspi->RxXferSize = hqspi->RxXferCount;
hqspi->pRxBuffPtr = pData;
/* Configure counters and size of the handle */
hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->pRxBuffPtr = pData;
/* Set the QSPI MDMA transfer complete callback */
hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt;
/* Set the QSPI DMA transfer complete callback */
hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt;
/* Set the MDMA error callback */
hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
/* Set the MDMA error callback */
hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
/* Clear the MDMA abort callback */
hqspi->hmdma->XferAbortCallback = NULL;
/* QSPI need to be configured to indirect mode before starting
the MDMA to avoid primatury triggering for the MDMA transfert */
/* Configure QSPI: CCR register with functional as indirect read */
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
/* Start the transfer by re-writing the address in AR register */
WRITE_REG(hqspi->Instance->AR, addr_reg);
/* Clear the MDMA abort callback */
hqspi->hmdma->XferAbortCallback = NULL;
/* In Receive mode , the MDMA source is the QSPI DR register : Force the MDMA Source Increment to disable */
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE);
@ -1439,21 +1431,37 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
status = HAL_ERROR;
}
/* Configure QSPI: CCR register with functional as indirect read */
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
/* Enable the MDMA */
if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK)
{
/* Process unlocked */
__HAL_UNLOCK(hqspi);
/* Start the transfer by re-writing the address in AR register */
WRITE_REG(hqspi->Instance->AR, addr_reg);
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
/* Enable the MDMA */
if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK)
{
/* Process unlocked */
__HAL_UNLOCK(hqspi);
/* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
}
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
/* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
}
else
{
status = HAL_ERROR;
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
hqspi->State = HAL_QSPI_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
}
else
{
hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
/* Process unlocked */
@ -1473,9 +1481,9 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
/**
* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
* @param hqspi: QSPI handle
* @param cmd: structure that contains the command configuration information.
* @param cfg: structure that contains the polling configuration information.
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information.
* @param cfg : structure that contains the polling configuration information.
* @param Timeout : Timeout duration
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
@ -1574,9 +1582,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy
/**
* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
* @param hqspi: QSPI handle
* @param cmd: structure that contains the command configuration information.
* @param cfg: structure that contains the polling configuration information.
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information.
* @param cfg : structure that contains the polling configuration information.
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
@ -1678,9 +1686,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman
/**
* @brief Configure the Memory Mapped mode.
* @param hqspi: QSPI handle
* @param cmd: structure that contains the command configuration information.
* @param cfg: structure that contains the memory mapped configuration information.
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information.
* @param cfg : structure that contains the memory mapped configuration information.
* @note This function is used only in Memory mapped Mode
* @retval HAL status
*/
@ -1733,9 +1741,9 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT
if (status == HAL_OK)
{
/* Configure QSPI: CR register with timeout counter enable */
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
{
assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
@ -1767,7 +1775,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT
/**
* @brief Transfer Error callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
@ -1782,7 +1790,7 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Abort completed callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
@ -1797,7 +1805,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Command completed callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
@ -1812,7 +1820,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Rx Transfer completed callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
@ -1827,10 +1835,10 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Tx Transfer completed callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
@ -1843,7 +1851,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief FIFO Threshold callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
@ -1858,7 +1866,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Status Match callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
@ -1873,7 +1881,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Timeout callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
@ -2115,7 +2123,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS
/**
* @brief Return the QSPI handle state.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval HAL state
*/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
@ -2126,7 +2134,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
/**
* @brief Return the QSPI error code.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval QSPI Error Code
*/
uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
@ -2136,7 +2144,7 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
/**
* @brief Abort the current transmission.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
@ -2150,7 +2158,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
/* Process unlocked */
__HAL_UNLOCK(hqspi);
if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@ -2169,7 +2177,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
/* Wait until TC flag is set to go back in idle state */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
if(status == HAL_OK)
if (status == HAL_OK)
{
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
@ -2179,6 +2187,9 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
if (status == HAL_OK)
{
/* Reset functional mode configuration to indirect write mode by default */
CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
/* Update state */
hqspi->State = HAL_QSPI_STATE_READY;
}
@ -2189,7 +2200,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
/**
* @brief Abort the current transmission (non-blocking function)
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
@ -2208,7 +2219,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
/* Disable all interrupts */
__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@ -2217,10 +2228,15 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt;
if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK)
{
/* Set error code to DMA */
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
status = HAL_ERROR;
/* Abort Complete callback */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->AbortCpltCallback(hqspi);
#else
HAL_QSPI_AbortCpltCallback(hqspi);
#endif
}
}
else
@ -2239,8 +2255,8 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
}
/** @brief Set QSPI timeout.
* @param hqspi: QSPI handle.
* @param Timeout: Timeout for the QSPI memory access.
* @param hqspi : QSPI handle.
* @param Timeout : Timeout for the QSPI memory access.
* @retval None
*/
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
@ -2249,8 +2265,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
}
/** @brief Set QSPI Fifo threshold.
* @param hqspi: QSPI handle.
* @param Threshold: Threshold of the Fifo (value between 1 and 16).
* @param hqspi : QSPI handle.
* @param Threshold : Threshold of the Fifo (value between 1 and 16).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
@ -2282,7 +2298,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t
}
/** @brief Get QSPI Fifo threshold.
* @param hqspi: QSPI handle.
* @param hqspi : QSPI handle.
* @retval Fifo threshold (value between 1 and 16)
*/
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
@ -2331,14 +2347,22 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashI
* @}
*/
/**
* @}
*/
/** @defgroup QSPI_Private_Functions QSPI Private Functions
* @{
*/
/**
* @brief DMA QSPI receive process complete callback.
* @param hmdma: MDMA handle
* @param hmdma : MDMA handle
* @retval None
*/
static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma)
{
QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent);
hqspi->RxXferCount = 0U;
/* Enable the QSPI transfer complete Interrupt */
@ -2347,12 +2371,12 @@ static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma)
/**
* @brief DMA QSPI transmit process complete callback.
* @param hmdma: MDMA handle
* @param hmdma : MDMA handle
* @retval None
*/
static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma)
{
QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent);
hqspi->TxXferCount = 0U;
/* Enable the QSPI transfer complete Interrupt */
@ -2361,12 +2385,12 @@ static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma)
/**
* @brief DMA QSPI communication error callback.
* @param hmdma: MDMA handle
* @param hmdma : MDMA handle
* @retval None
*/
static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma)
{
QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent);
hqspi->RxXferCount = 0U;
hqspi->TxXferCount = 0U;
@ -2382,12 +2406,12 @@ static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma)
/**
* @brief MDMA QSPI abort complete callback.
* @param hmdma: MDMA handle
* @param hmdma : MDMA handle
* @retval None
*/
static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
{
QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent);
hqspi->RxXferCount = 0U;
hqspi->TxXferCount = 0U;
@ -2418,13 +2442,14 @@ static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
#endif
}
}
/**
* @brief Wait for a flag state until timeout.
* @param hqspi: QSPI handle
* @param Flag: Flag checked
* @param State: Value of the flag expected
* @param Tickstart: Tick start value
* @param Timeout: Duration of the timeout
* @param hqspi : QSPI handle
* @param Flag : Flag checked
* @param State : Value of the flag expected
* @param Tickstart : Tick start value
* @param Timeout : Duration of the timeout
* @retval HAL status
*/
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
@ -2450,9 +2475,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp
/**
* @brief Configure the communication registers.
* @param hqspi: QSPI handle
* @param cmd: structure that contains the command configuration information
* @param FunctionalMode: functional mode to configured
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information
* @param FunctionalMode : functional mode to configured
* This parameter can be one of the following values:
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
@ -2606,16 +2631,15 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
* @}
*/
/**
* @}
*/
#endif /* QUADSPI */
#endif /* HAL_QSPI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(QUADSPI) */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

46
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rcc.c
View File

@ -228,8 +228,9 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
/* Reset CFGR register */
CLEAR_REG(RCC->CFGR);
/* Update the SystemCoreClock global variable */
/* Update the SystemCoreClock and SystemD2Clock global variables */
SystemCoreClock = HSI_VALUE;
SystemD2Clock = HSI_VALUE;
/* Adapt Systick interrupt period */
if(HAL_InitTick(uwTickPrio) != HAL_OK)
@ -859,7 +860,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
* contains the configuration information for the RCC peripheral.
* @param FLatency: FLASH Latency, this parameter depend on device selected
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* @note The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency
* and updated by HAL_InitTick() function called within this function
*
* @note The HSI is used (enabled by hardware) as system clock source after
@ -882,6 +883,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
{
HAL_StatusTypeDef halstatus;
uint32_t tickstart;
uint32_t common_system_clock;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
@ -1174,10 +1176,23 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
/* Update the SystemCoreClock global variable */
#if defined(RCC_D1CFGR_D1CPRE)
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
#else
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
#endif
#if defined(RCC_D1CFGR_HPRE)
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
#endif /* DUAL_CORE && CORE_CM4 */
/* Configure the source of time base considering new system clocks settings*/
halstatus = HAL_InitTick (uwTickPrio);
@ -1429,11 +1444,26 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
#if defined(RCC_D1CFGR_HPRE)
SystemD2Clock = (HAL_RCCEx_GetD1SysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
uint32_t common_system_clock;
#if defined(RCC_D1CFGR_D1CPRE)
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
#else
SystemD2Clock = (HAL_RCCEx_GetD1SysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
#endif
#if defined(RCC_D1CFGR_HPRE)
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
#endif /* DUAL_CORE && CORE_CM4 */
return SystemD2Clock;
}
@ -1451,7 +1481,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
#else
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> POSITION_VAL(RCC_CDCFGR2_CDPPRE1_0)]);
return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
#endif
}

84
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rcc_ex.c
View File

@ -2635,21 +2635,37 @@ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks)
}
/**
* @brief Returns the main Core frequency
* @note Each time core clock changes, this function must be called to update the
* right system core clock value. Otherwise, any configuration based on this function will be incorrect.
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* @brief Returns the main System frequency
* @note Each time System clock changes, this function must be called to update the
* right core clock value. Otherwise, any configuration based on this function will be incorrect.
* @note The SystemCoreClock CMSIS variable is used to store System current Core Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
{
uint32_t common_system_clock;
#if defined(RCC_D1CFGR_D1CPRE)
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
#else
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
#endif
return SystemCoreClock;
/* Update the SystemD2Clock global variable */
#if defined(RCC_D1CFGR_HPRE)
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
#endif /* DUAL_CORE && CORE_CM4 */
return common_system_clock;
}
/**
* @}
@ -2683,6 +2699,28 @@ void HAL_RCCEx_DisableLSECSS(void)
__HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
}
/**
* @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
* @note LSE Clock Security System Interrupt is mapped on EXTI line 18
* @retval None
*/
void HAL_RCCEx_EnableLSECSS_IT(void)
{
/* Enable LSE CSS */
SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
/* Enable LSE CSS IT */
__HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
/* Enable IT on EXTI Line 18 */
#if defined(DUAL_CORE) && defined(CORE_CM4)
__HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT();
#else
__HAL_RCC_LSECSS_EXTI_ENABLE_IT();
#endif /* DUAL_CORE && CORE_CM4 */
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
}
/**
* @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock
* @param WakeUpClk: Wakeup clock
@ -3351,6 +3389,38 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t D
return status;
}
/**
* @brief Handle the RCC LSE Clock Security System interrupt request.
* @retval None
*/
void HAL_RCCEx_LSECSS_IRQHandler(void)
{
/* Check RCC LSE CSSF flag */
if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
{
/* Clear RCC LSE CSS pending bit */
__HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
/* RCC LSE Clock Security System interrupt user callback */
HAL_RCCEx_LSECSS_Callback();
}
}
/**
* @brief RCCEx LSE Clock Security System interrupt callback.
* @retval none
*/
__weak void HAL_RCCEx_LSECSS_Callback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
*/
}
/**
* @}
*/

154
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sd.c
View File

@ -464,7 +464,6 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
{
uint32_t errorstate;
HAL_StatusTypeDef status;
SD_InitTypeDef Init;
uint32_t sdmmc_clk;
@ -475,27 +474,22 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
Init.ClockDiv = SDMMC_INIT_CLK_DIV;
#if (USE_SD_TRANSCEIVER != 0U) || defined (USE_SD_DIRPOL)
#if (USE_SD_TRANSCEIVER != 0U)
if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
{
/* Set Transceiver polarity */
hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
}
#elif defined (USE_SD_DIRPOL)
/* Set Transceiver polarity */
hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
#endif /* USE_SD_TRANSCEIVER */
/* Initialize SDMMC peripheral interface with default configuration */
status = SDMMC_Init(hsd->Instance, Init);
if(status != HAL_OK)
{
return HAL_ERROR;
}
(void)SDMMC_Init(hsd->Instance, Init);
/* Set Power State to ON */
status = SDMMC_PowerState_ON(hsd->Instance);
if(status != HAL_OK)
{
return HAL_ERROR;
}
(void)SDMMC_PowerState_ON(hsd->Instance);
/* wait 74 Cycles: required power up waiting time before starting
the SD initialization sequence */
@ -528,6 +522,17 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
return HAL_ERROR;
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
return HAL_OK;
}
@ -684,17 +689,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
add *= 512U;
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * BLOCKSIZE;
@ -877,17 +871,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
add *= 512U;
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * BLOCKSIZE;
@ -1071,17 +1054,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui
add *= 512U;
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
@ -1175,17 +1147,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u
add *= 512U;
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
@ -1281,17 +1242,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
add *= 512U;
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
@ -1390,16 +1340,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
add *= 512U;
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
@ -2342,6 +2282,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT
{
uint32_t sd_status[16];
uint32_t errorstate;
HAL_StatusTypeDef status = HAL_OK;
errorstate = SD_SendSDStatus(hsd, sd_status);
if(errorstate != HAL_SD_ERROR_NONE)
@ -2350,7 +2291,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
status = HAL_ERROR;
}
else
{
@ -2380,7 +2321,18 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT
pStatus->VideoSpeedClass = (uint8_t)((sd_status[4] & 0xFF000000U) >> 24U);
}
return HAL_OK;
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode = errorstate;
hsd->State = HAL_SD_STATE_READY;
status = HAL_ERROR;
}
return status;
}
/**
@ -2419,6 +2371,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
{
SDMMC_InitTypeDef Init;
uint32_t errorstate;
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_SDMMC_BUS_WIDE(WideMode));
@ -2460,8 +2413,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
status = HAL_ERROR;
}
else
{
@ -2495,10 +2447,20 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
(void)SDMMC_Init(hsd->Instance, Init);
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
status = HAL_ERROR;
}
/* Change State */
hsd->State = HAL_SD_STATE_READY;
return HAL_OK;
return status;
}
/**
@ -2516,6 +2478,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode)
{
uint32_t tickstart;
uint32_t errorstate;
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
@ -2743,6 +2706,16 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
}
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
status = HAL_ERROR;
}
/* Change State */
hsd->State = HAL_SD_STATE_READY;
return status;
@ -3548,7 +3521,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
{
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
if (errorstate != HAL_SD_ERROR_NONE)
{
@ -3557,16 +3530,13 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
/* Configure the SD DPSM (Data Path State Machine) */
sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT;
sdmmc_datainitstructure.DataLength = 64;
sdmmc_datainitstructure.DataLength = 64U;
sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;
if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
{
return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
}
(void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure);
errorstate = SDMMC_CmdSwitch(hsd->Instance,SDMMC_SDR25_SWITCH_PATTERN);
@ -3662,7 +3632,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd)
{
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
if (errorstate != HAL_SD_ERROR_NONE)
{
@ -3671,7 +3641,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd)
/* Configure the SD DPSM (Data Path State Machine) */
sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT;
sdmmc_datainitstructure.DataLength = 64;
sdmmc_datainitstructure.DataLength = 64U;
sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
@ -3790,7 +3760,7 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd)
{
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
if (errorstate != HAL_SD_ERROR_NONE)
{
@ -3799,7 +3769,7 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd)
/* Configure the SD DPSM (Data Path State Machine) */
sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT;
sdmmc_datainitstructure.DataLength = 64;
sdmmc_datainitstructure.DataLength = 64U;
sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;

22
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sd_ex.c
View File

@ -139,17 +139,6 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3
add *= 512U;
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
@ -231,17 +220,6 @@ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint
add *= 512U;
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;

14
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_tim.c
View File

@ -2617,10 +2617,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
}
/* Check the parameters */
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
@ -2783,7 +2783,7 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Enable the encoder interface channels */
switch (Channel)
@ -2827,7 +2827,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@ -2873,7 +2873,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Enable the encoder interface channels */
/* Enable the capture compare Interrupts 1 and/or 2 */
@ -2923,7 +2923,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@ -2978,7 +2978,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
uint32_t *pData2, uint16_t Length)
{
/* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
if (htim->State == HAL_TIM_STATE_BUSY)
{
@ -3112,7 +3112,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */

13
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_usart.c
View File

@ -317,7 +317,8 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
- HDSEL, SCEN and IREN bits in the USART_CR3 register.
*/
husart->Instance->CR2 &= ~USART_CR2_LINEN;
husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
@ -2091,7 +2092,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR));
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF | USART_ISR_UDR));
if (errorflags == 0U)
{
/* USART in mode Receiver ---------------------------------------------------*/
@ -2146,6 +2147,14 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
husart->ErrorCode |= HAL_USART_ERROR_ORE;
}
/* USART Receiver Timeout interrupt occurred ---------------------------------*/
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
{
__HAL_UART_CLEAR_FLAG(husart, UART_CLEAR_RTOF);
husart->ErrorCode |= HAL_USART_ERROR_RTO;
}
/* USART SPI slave underrun error interrupt occurred -------------------------*/
if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{

6
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_usart_ex.c
View File

@ -57,10 +57,10 @@
/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
* @{
*/
/* UART RX FIFO depth */
/* USART RX FIFO depth */
#define RX_FIFO_DEPTH 8U
/* UART TX FIFO depth */
/* USART TX FIFO depth */
#define TX_FIFO_DEPTH 8U
/**
* @}
@ -243,7 +243,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart)
/* Restore USART configuration */
WRITE_REG(husart->Instance->CR1, tmpcr1);
husart->SlaveMode = USART_SLAVEMODE_ENABLE;
husart->SlaveMode = USART_SLAVEMODE_DISABLE;
husart->State = HAL_USART_STATE_READY;

88
stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_fmc.c
View File

@ -194,6 +194,8 @@
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
{
uint32_t flashaccess;
uint32_t btcr_reg;
uint32_t mask;
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
@ -226,38 +228,42 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini
flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
}
MODIFY_REG(Device->BTCR[Init->NSBank],
(FMC_BCRx_MBKEN |
FMC_BCRx_MUXEN |
FMC_BCRx_MTYP |
FMC_BCRx_MWID |
FMC_BCRx_FACCEN |
FMC_BCRx_BURSTEN |
FMC_BCRx_WAITPOL |
FMC_BCRx_WAITCFG |
FMC_BCRx_WREN |
FMC_BCRx_WAITEN |
FMC_BCRx_EXTMOD |
FMC_BCRx_ASYNCWAIT |
FMC_BCRx_CBURSTRW |
FMC_BCR1_CCLKEN |
FMC_BCR1_WFDIS |
FMC_BCRx_CPSIZE),
(flashaccess |
Init->DataAddressMux |
Init->MemoryType |
Init->MemoryDataWidth |
Init->BurstAccessMode |
Init->WaitSignalPolarity |
Init->WaitSignalActive |
Init->WriteOperation |
Init->WaitSignal |
Init->ExtendedMode |
Init->AsynchronousWait |
Init->WriteBurst |
Init->ContinuousClock |
Init->WriteFifo |
Init->PageSize));
btcr_reg = (flashaccess | \
Init->DataAddressMux | \
Init->MemoryType | \
Init->MemoryDataWidth | \
Init->BurstAccessMode | \
Init->WaitSignalPolarity | \
Init->WaitSignalActive | \
Init->WriteOperation | \
Init->WaitSignal | \
Init->ExtendedMode | \
Init->AsynchronousWait | \
Init->WriteBurst);
btcr_reg |= Init->ContinuousClock;
btcr_reg |= Init->WriteFifo;
btcr_reg |= Init->PageSize;
mask = (FMC_BCRx_MBKEN |
FMC_BCRx_MUXEN |
FMC_BCRx_MTYP |
FMC_BCRx_MWID |
FMC_BCRx_FACCEN |
FMC_BCRx_BURSTEN |
FMC_BCRx_WAITPOL |
FMC_BCRx_WAITCFG |
FMC_BCRx_WREN |
FMC_BCRx_WAITEN |
FMC_BCRx_EXTMOD |
FMC_BCRx_ASYNCWAIT |
FMC_BCRx_CBURSTRW);
mask |= FMC_BCR1_CCLKEN;
mask |= FMC_BCR1_WFDIS;
mask |= FMC_BCRx_CPSIZE;
MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
/* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
@ -556,6 +562,9 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
assert_param(IS_FMC_NAND_BANK(Bank));
/* Prevent unused argument(s) compilation warning if no assert_param check */
UNUSED(Bank);
/* NAND bank 3 registers configuration */
MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |
((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
@ -583,6 +592,9 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
assert_param(IS_FMC_NAND_BANK(Bank));
/* Prevent unused argument(s) compilation warning if no assert_param check */
UNUSED(Bank);
/* NAND bank 3 registers configuration */
MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |
((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
@ -608,6 +620,9 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
__FMC_NAND_DISABLE(Device, Bank);
/* De-initialize the NAND Bank */
/* Prevent unused argument(s) compilation warning if no assert_param check */
UNUSED(Bank);
/* Set the FMC_NAND_BANK3 registers to their reset values */
WRITE_REG(Device->PCR, 0x00000018U);
WRITE_REG(Device->SR, 0x00000040U);
@ -650,6 +665,9 @@ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
assert_param(IS_FMC_NAND_BANK(Bank));
/* Enable ECC feature */
/* Prevent unused argument(s) compilation warning if no assert_param check */
UNUSED(Bank);
SET_BIT(Device->PCR, FMC_PCR_ECCEN);
return HAL_OK;
@ -669,6 +687,9 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
assert_param(IS_FMC_NAND_BANK(Bank));
/* Disable ECC feature */
/* Prevent unused argument(s) compilation warning if no assert_param check */
UNUSED(Bank);
CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
return HAL_OK;
@ -706,6 +727,9 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui
}
}
/* Prevent unused argument(s) compilation warning if no assert_param check */
UNUSED(Bank);
/* Get the ECCR register value */
*ECCval = (uint32_t)Device->ECCR;

23
stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_gpio.c
View File

@ -220,8 +220,6 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
if (currentpin != 0x00000000U)
{
/* Pin Mode configuration */
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
@ -230,6 +228,13 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
/* Speed mode configuration */
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
/* Check Output mode parameters */
assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
/* Output mode configuration*/
LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
}
/* Pull-up Pull down resistor configuration*/
@ -240,7 +245,7 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
/* Check Alternate parameter */
assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
/* Speed mode configuration */
/* Alternate function configuration */
if (currentpin < LL_GPIO_PIN_8)
{
LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
@ -250,19 +255,13 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
}
}
/* Pin Mode configuration */
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
}
pinpos++;
}
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
/* Check Output mode parameters */
assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
/* Output mode configuration*/
LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
}
return (SUCCESS);
}

70
stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_lptim.c
View File

@ -226,25 +226,25 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
/* Save LPTIM source clock */
switch ((uint32_t)LPTIMx)
{
case LPTIM1_BASE:
tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
break;
case LPTIM2_BASE:
tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
break;
case LPTIM1_BASE:
tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
break;
case LPTIM2_BASE:
tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
break;
#if defined(LPTIM3)&&defined(LPTIM4)&&defined(LPTIM5)
case LPTIM3_BASE:
case LPTIM4_BASE:
case LPTIM5_BASE:
tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE);
break;
case LPTIM3_BASE:
case LPTIM4_BASE:
case LPTIM5_BASE:
tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE);
break;
#elif defined(LPTIM3)
case LPTIM3_BASE:
tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE);
break;
case LPTIM3_BASE:
tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE);
break;
#endif /* LPTIM3 && LPTIM4 && LPTIM5 */
default:
break;
default:
break;
}
/* Save LPTIM configuration registers */
@ -265,25 +265,25 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
/* Force LPTIM source kernel clock from APB */
switch ((uint32_t)LPTIMx)
{
case LPTIM1_BASE:
LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
break;
case LPTIM2_BASE:
LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK4);
break;
case LPTIM1_BASE:
LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
break;
case LPTIM2_BASE:
LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK4);
break;
#if defined(LPTIM3)&&defined(LPTIM4)&&defined(LPTIM5)
case LPTIM3_BASE:
case LPTIM4_BASE:
case LPTIM5_BASE:
LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE_PCLK4);
break;
case LPTIM3_BASE:
case LPTIM4_BASE:
case LPTIM5_BASE:
LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE_PCLK4);
break;
#elif defined(LPTIM3)
case LPTIM3_BASE:
LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE_PCLK4);
break;
case LPTIM3_BASE:
LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE_PCLK4);
break;
#endif /* LPTIM3 && LPTIM4 && LPTIM5*/
default:
break;
default:
break;
}
if (tmpCMP != 0UL)
@ -296,7 +296,8 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
} while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
}
while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
}
@ -311,7 +312,8 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
} while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
}
while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_ARROK(LPTIMx);
}

2
stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_tim.c
View File

@ -338,7 +338,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
TIM_InitStruct->RepetitionCounter = 0x00000000U;
}
/**

263
stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_utils.c
View File

@ -224,8 +224,6 @@
* @{
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t *latency);
static ErrorStatus UTILS_SetFlashLatency(uint32_t latency);
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
static ErrorStatus UTILS_IsPLLsReady(void);
/**
@ -341,7 +339,7 @@ void LL_mDelay(uint32_t Delay)
(++) +----------------------------------------------------------------------------+
#else
(+) The maximum frequency of the SYSCLK is 280 MHz and HCLK is 140 MHz.
(+) The maximum frequency of the SYSCLK is 280 MHz and HCLK is 280 MHz.
(+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 140 MHz.
@endverbatim
@internal
@ -399,14 +397,6 @@ void LL_SetSystemCoreClock(uint32_t CPU_Frequency)
{
/* HCLK clock frequency */
SystemCoreClock = CPU_Frequency;
/* Update the SystemD2Clock global variable */
#if defined(RCC_D1CFGR_HPRE)
SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
}
/**
@ -505,7 +495,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS
* @note Function is based on the following formula:
* - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
* - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
* - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz (PLLVCO_output = PLLVCO_input * PLLN)
* - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(*) (PLLVCO_output = PLLVCO_input * PLLN)
* - PLLP: ensure that max frequency at 400000000 Hz or 280000000 Hz(*) is reached (PLLVCO_output / PLLP)
* @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
* @param HSEBypass This parameter can be one of the following values:
@ -604,63 +594,29 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa
return status;
}
/**
* @}
*/
/**
* @brief Update number of Flash wait states in line with new frequency and current
voltage range.
* @param HCLKFrequency HCLK frequency
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Latency has been modified
* - ERROR: Latency cannot be modified
*/
ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency)
{
ErrorStatus status;
uint32_t latency;
status = UTILS_CalculateFlashLatency(HCLKFrequency, &latency);
if(status == SUCCESS)
{
status = UTILS_SetFlashLatency(latency);
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup UTILS_LL_Private_Functions
* @{
*/
/**
* @brief Calculate and check the Flash wait states number according to the
new HCLK frequency and current voltage range.
* @param HCLK_Frequency HCLK frequency
* @param latency This parameter can be one of the following values:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
* @arg @ref LL_FLASH_LATENCY_2
* @arg @ref LL_FLASH_LATENCY_3
* @arg @ref LL_FLASH_LATENCY_4
* @arg @ref LL_FLASH_LATENCY_5
* @arg @ref LL_FLASH_LATENCY_6
* @arg @ref LL_FLASH_LATENCY_7
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Latency has been modified
* - ERROR: Latency cannot be modified
*/
static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t *latency)
ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
{
ErrorStatus status = SUCCESS;
uint32_t timeout;
uint32_t getlatency;
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
/* Frequency cannot be equal to 0 */
if(HCLK_Frequency == 0U)
if (HCLK_Frequency == 0U)
{
status = ERROR;
}
@ -672,37 +628,36 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t
if((HCLK_Frequency > UTILS_SCALE0_LATENCY5_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY6_FREQ))
{
/* 264 < HCLK <= 280 => 6WS (7 CPU cycles) */
*latency = LL_FLASH_LATENCY_6;
latency = LL_FLASH_LATENCY_6;
}
else if((HCLK_Frequency > UTILS_SCALE0_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY5_FREQ))
{
/* 220 < HCLK <= 264 => 5WS (6 CPU cycles) */
*latency = LL_FLASH_LATENCY_5;
latency = LL_FLASH_LATENCY_5;
}
else if((HCLK_Frequency > UTILS_SCALE0_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY4_FREQ))
{
/* 176 < HCLK <= 220 => 4WS (5 CPU cycles) */
*latency = LL_FLASH_LATENCY_4;
latency = LL_FLASH_LATENCY_4;
}
else if((HCLK_Frequency > UTILS_SCALE0_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ))
{
/* 132 < HCLK <= 176 => 3WS (4 CPU cycles) */
*latency = LL_FLASH_LATENCY_3;
latency = LL_FLASH_LATENCY_3;
}
else if((HCLK_Frequency > UTILS_SCALE0_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY2_FREQ))
{
/* 88 < HCLK <= 132 => 2WS (3 CPU cycles) */
*latency = LL_FLASH_LATENCY_2;
latency = LL_FLASH_LATENCY_2;
}
else if((HCLK_Frequency > UTILS_SCALE0_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY1_FREQ))
{
/* 44 < HCLK <= 88 => 1WS (2 CPU cycles) */
*latency = LL_FLASH_LATENCY_1;
latency = LL_FLASH_LATENCY_1;
}
else if(HCLK_Frequency <= UTILS_SCALE0_LATENCY0_FREQ)
{
/* HCLK <= 44 => 0WS (1 CPU cycles) */
*latency = LL_FLASH_LATENCY_0;
/* HCLK <= 44 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
}
else
{
@ -714,17 +669,17 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t
if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY5_FREQ))
{
/* 210 < HCLK <= 225 => 5WS (6 CPU cycles) */
*latency = LL_FLASH_LATENCY_5;
latency = LL_FLASH_LATENCY_5;
}
else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY4_FREQ))
{
/* 168 < HCLK <= 210 => 4WS (5 CPU cycles) */
*latency = LL_FLASH_LATENCY_4;
latency = LL_FLASH_LATENCY_4;
}
else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ))
{
/* 126 < HCLK <= 168 => 3WS (4 CPU cycles) */
*latency = LL_FLASH_LATENCY_3;
latency = LL_FLASH_LATENCY_3;
}
else if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
#else
@ -734,17 +689,16 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t
#endif /*POWER_DOMAINS_NUMBER == 2U*/
{
/* 140 < HCLK <= 210 => 2WS (3 CPU cycles) */
*latency = LL_FLASH_LATENCY_2;
latency = LL_FLASH_LATENCY_2;
}
else if((HCLK_Frequency > UTILS_SCALE1_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ))
{
/* 70 < HCLK <= 140 => 1WS (2 CPU cycles) */
*latency = LL_FLASH_LATENCY_1;
latency = LL_FLASH_LATENCY_1;
}
else if(HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ)
{
/* HCLK <= 70 => 0WS (1 CPU cycles) */
*latency = LL_FLASH_LATENCY_0;
/* HCLK <= 70 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
}
else
{
@ -757,7 +711,7 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t
if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY4_FREQ))
{
/* 136 < HCLK <= 160 => 4WS (5 CPU cycles) */
*latency = LL_FLASH_LATENCY_4;
latency = LL_FLASH_LATENCY_4;
}
else if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ))
#else
@ -765,22 +719,21 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t
#endif /*POWER_DOMAINS_NUMBER == 2U*/
{
/* 165 < HCLK <= 220 => 3WS (4 CPU cycles) */
*latency = LL_FLASH_LATENCY_3;
latency = LL_FLASH_LATENCY_3;
}
else if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ))
{
/* 110 < HCLK <= 165 => 2WS (3 CPU cycles) */
*latency = LL_FLASH_LATENCY_2;
latency = LL_FLASH_LATENCY_2;
}
else if((HCLK_Frequency > UTILS_SCALE2_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ))
{
/* 55 < HCLK <= 110 => 1WS (2 CPU cycles) */
*latency = LL_FLASH_LATENCY_1;
latency = LL_FLASH_LATENCY_1;
}
else if(HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ)
{
/* HCLK <= 55 => 0WS (1 CPU cycles) */
*latency = LL_FLASH_LATENCY_0;
/* HCLK <= 55 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
}
else
{
@ -793,7 +746,7 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t
if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY4_FREQ))
{
/* 180 < HCLK <= 225 => 4WS (5 CPU cycles) */
*latency = LL_FLASH_LATENCY_4;
latency = LL_FLASH_LATENCY_4;
}
else if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ))
#else
@ -801,55 +754,62 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t
#endif /*POWER_DOMAINS_NUMBER == 3U*/
{
/* 135 < HCLK <= 180 => 3WS (4 CPU cycles) */
*latency = LL_FLASH_LATENCY_3;
latency = LL_FLASH_LATENCY_3;
}
else if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ))
{
/* 90 < HCLK <= 135 => 2WS (3 CPU cycles) */
*latency = LL_FLASH_LATENCY_2;
latency = LL_FLASH_LATENCY_2;
}
else if((HCLK_Frequency > UTILS_SCALE3_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY1_FREQ))
{
/* 45 < HCLK <= 90 => 1WS (2 CPU cycles) */
*latency = LL_FLASH_LATENCY_1;
latency = LL_FLASH_LATENCY_1;
}
else if(HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ)
{
/* HCLK <= 45 => 0WS (1 CPU cycles) */
*latency = LL_FLASH_LATENCY_0;
/* HCLK <= 45 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
}
else
{
status = ERROR;
}
}
if(status == SUCCESS)
{
LL_FLASH_SetLatency(latency);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
timeout = 2;
do
{
/* Wait for Flash latency to be updated */
getlatency = LL_FLASH_GetLatency();
timeout--;
} while ((getlatency != latency) && (timeout > 0U));
if(getlatency != latency)
{
status = ERROR;
}
}
}
return status;
}
/**
* @brief Update number of Flash wait states
* @param latency Flash Latency
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Latency has been modified
* - ERROR: Latency cannot be modified
* @}
*/
static ErrorStatus UTILS_SetFlashLatency(uint32_t latency)
{
ErrorStatus status = SUCCESS;
LL_FLASH_SetLatency(latency);
/** @addtogroup UTILS_LL_Private_Functions
* @{
*/
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(LL_FLASH_GetLatency() != latency)
{
status = ERROR;
}
return status;
}
/**
* @brief Function to check that PLL can be modified
@ -918,8 +878,8 @@ static ErrorStatus UTILS_IsPLLsReady(void)
*/
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
ErrorStatus status;
uint32_t new_hclk_frequency, new_latency;
ErrorStatus status = SUCCESS;
uint32_t new_hclk_frequency;
assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->SYSCLKDivider));
assert_param(IS_LL_UTILS_AHB_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
@ -931,63 +891,72 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_
/* Calculate the new HCLK frequency */
new_hclk_frequency = LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
/* Calculate the new FLASH latency according to the new HCLK frequency */
status = UTILS_CalculateFlashLatency(new_hclk_frequency, &new_latency);
/* Increasing the number of wait states because of higher CPU frequency */
if (SystemD2Clock < new_hclk_frequency)
{
/* Set FLASH latency to highest latency */
status = LL_SetFlashLatency(new_hclk_frequency);
}
/* Update system clock configuration */
if(status == SUCCESS)
{
/* Increasing the number of wait states because of higher CPU frequency */
if(LL_FLASH_GetLatency() < new_latency)
/* Enable PLL */
LL_RCC_PLL1_Enable();
while (LL_RCC_PLL1_IsReady() != 1U)
{
status = UTILS_SetFlashLatency(new_latency);
/* Wait for PLL ready */
}
/* Update system clock configuration */
if(status == SUCCESS)
/* Set All APBxPrescaler to the Highest Divider */
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16);
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16);
LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16);
LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16);
/* Set SYS prescaler*/
LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider);
/* Set AHB prescaler*/
LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
/* Sysclk activation on the main PLL */
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
{
/* Enable PLL */
LL_RCC_PLL1_Enable();
while (LL_RCC_PLL1_IsReady() != 1U)
{
/* Wait for PLL ready */
}
/* Set All APBxPrescaler to the Highest Divider */
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16);
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16);
LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16);
LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16);
/* Set SYS prescaler*/
LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider);
/* Set AHB prescaler*/
LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
/* Sysclk activation on the main PLL */
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
{
/* Wait for system clock switch to PLL */
}
/* Set APBn prescaler*/
LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider);
LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider);
/* Update SystemCoreClock variable */
LL_SetSystemCoreClock(SYSCLK_Frequency);
/* Wait for system clock switch to PLL */
}
/* Set APBn prescaler*/
LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider);
LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider);
/* Decreasing the number of wait states because of lower CPU frequency */
if(LL_FLASH_GetLatency() > new_latency)
if (SystemD2Clock > new_hclk_frequency)
{
status = UTILS_SetFlashLatency(new_latency);
/* Set FLASH latency to lowest latency */
status = LL_SetFlashLatency(new_hclk_frequency);
}
/* Update the SystemD2Clock global variable */
#if defined(RCC_D1CFGR_HPRE)
SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
/* Update SystemCoreClock variable */
#if defined(DUAL_CORE) && defined(CORE_CM4)
LL_SetSystemCoreClock(SystemD2Clock);
#else
LL_SetSystemCoreClock(SYSCLK_Frequency);
#endif /* DUAL_CORE && CORE_CM4 */
}
return status;
}

705
stm32cube/stm32h7xx/release_note.html
View File

@ -68,10 +68,617 @@
<div class="col-sm-12 col-lg-8">
<h2 id="update-history"><strong>Update History</strong></h2>
<div class="collapse">
<input type="checkbox" id="collapse-section9" checked aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.6.0 / 02-December-2019</strong></label>
<input type="checkbox" id="collapse-section10" checked aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.7.0 / 14-February-2020</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
<li><p>Maintenance release</p></li>
<li><p>Add support of the value line STM32H7B0 devices over STM32H7B3I-EVAL board. Two examples, with several configurations, are available to show how to boot from internal flash, configure the external memories and jump to user application (located on an external memory)</p></li>
<li>Add STM32H7B3I-EVAL demonstrations source code with preconfigured projects on EWARM, Keil and STM32CubeIDE toolchains:
<ul>
<li>Source code available for:
<ul>
<li><strong>MenuLauncher</strong>: Execution from internal flash, allowing to select one of the following sub-demonstrations</li>
<li><strong>AudioPlayer</strong>: Audio Player Demonstration(playing music in WAV and MP3 formats, low power, …)</li>
<li><strong>ClockAndWeather</strong>: Clock and Weather Demonstration(Allow to retrieve the time and weather forecast for up six cities, …)<br />
</li>
<li><strong>TouchGFX</strong>: Touch GFX graphical library demonstration(Smart recipe with video instruction, Washing machine UI with video instruction, …)</li>
<li><strong>STemWin</strong>: STemWin graphical library demonstration(Graphical Effect and Rocket Game)</li>
<li><strong>EmbeddedWizard</strong>: Embedded Wizard GUI demonstration(Climate Cabinet, WashingMachine, …)</li>
</ul></li>
<li>All binaries and Media demonstration files are available from the STM32H7B3I-EVAL board web page in the Binary Delivery section.
<ul>
<li>Please refer to : <a href="https://www.st.com/en/product/stm32h7b3i-eval.html">https://www.st.com/en/product/stm32h7b3i-eval.html</a></li>
</ul></li>
</ul></li>
<li>Add support of STM32H743I-EVAL source code with preconfigured projects on EWARM, Keil and SW4STM32 toolchains:
<ul>
<li>Source code available for:
<ul>
<li><strong>TouchGFX</strong>: Touch GFX graphical library demonstration</li>
<li><strong>STemWin</strong>: STemWin graphical library demonstration</li>
<li><strong>EmbeddedWizard</strong>: Embedded Wizard GUI demonstration</li>
</ul></li>
</ul></li>
<li>Add support of STM32H747I-EVAL source code with preconfigured projects on EWARM, Keil and SW4STM32 toolchains:
<ul>
<li>Source code available for:
<ul>
<li><strong>MenuLauncher</strong>: Execution from internal flash, allowing to select one of the following sub-demonstrations</li>
<li><strong>TouchGFX</strong>: Touch GFX graphical library demonstration</li>
<li><strong>STemWin</strong>: STemWin graphical library demonstration</li>
<li><strong>EmbeddedWizard</strong>: Embedded Wizard GUI demonstration</li>
</ul></li>
</ul></li>
<li><p>Add support of STM32H7B3I-DK demonstrations for Keil and STM32CubeIDE toolchains</p></li>
<li><strong>CMSIS Device</strong> updates (Please Refer to the <a href="Drivers/CMSIS/Device/ST/STM32H7xx/Release_Notes.html">release notes</a> for detailed)
<ul>
<li>General updates to align Bits and registers definitions with the STM32H7 reference manual</li>
<li>Update “ErrorStatus” enumeration definition in stm32h7xx.h file with SUCCESS set to numerical value zero</li>
<li>Add definition of DMA_SxCR_TRBUFF bit field of DMA SxCR register allowing to enabled/disable bufferable transfers</li>
<li>Remove RCC_AHB2ENR_CRYPEN/RCC_AHB2RSTR_CRYPRST/RCC_AHB2LPENR_CRYPLPEN and RCC_AHB2ENR_HASHEN/RCC_AHB2RSTR_HASHRST/RCC_AHB2LPENR_HASHLPEN from H7 devices that doesn’t support CRYP/HASH (STM32H742/43/45/47/A3)</li>
<li>Add STM32H7_DEV_ID define allowing to identfy the H7 Device ID</li>
<li>Update OCTOSPIM_TypeDef structure definition with 3 PCR registers instead of 8 (on STM32H7A3/B3/B0 devices supporting OctoSPI)</li>
<li>Add definition for OCTOSPIM_CR_MUXEN and OCTOSPIM_CR_REQ2ACK_TIME in order to support OctoSPI IO Manager multiplexed mode feature (on STM32H7A3/B3/B0 devices supporting OctoSPI)</li>
<li>Update system_stm32h7xx.c to reflect the current core clock in SystemCoreClock global variable (Corex-M7 or Corext-M4 clock depending of the current context in case of Dual Core)</li>
<li>Add EWARM linker files for STM32H7A3 devices with reduced Flash size to 1MB:
<ul>
<li>stm32h7a3xg_flash.icf, stm32h7a3xg_flash_rw_sram1.icf, stm32h7a3xg_flash_rw_sram2.icf.</li>
<li>stm32h7a3xgq_flash.icf, stm32h7a3xgq_flash_rw_sram1.icf, stm32h7a3xgq_flash_rw_sram2.icf.</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL Drivers</strong> updates (Please Refer to the <a href="Drivers/STM32H7xx_HAL_Driver/Release_Notes.html">release notes</a> for detailed)
<ul>
<li>General updates to fix known defects and enhancements implementation.</li>
<li><strong>OSPI</strong>: <strong>Add support of multiplexed mode feature</strong></li>
</ul></li>
<li><strong>BSP</strong> updates
<ul>
<li>Minor updates of <strong>STM32H7B3I-EVAL</strong> and <strong>STM32H7B3I-DK</strong> BSP drivers to fix misra warnings</li>
</ul></li>
<li><strong>Middleware</strong> updates
<ul>
<li>Update of <strong>USB Host</strong> library to new version <strong>V3.3.4</strong></li>
</ul></li>
<li><strong>Projects</strong> updates
<ul>
<li>Examples:
<ul>
<li>New HAL examples (STM32H7B3I-EVAL):
<ul>
<li>OTFDEC_EncryptionDecryption</li>
<li>OTFDEC_ExecutingAesInstruction</li>
</ul></li>
</ul></li>
<li>Applications:
<ul>
<li>For <strong>STM32H7B0xx</strong> Value line devices based on STM32H7B3I-EVAL board, ExtMem_CodeExecution applications are provided with two sub-applications:
<ul>
<li>ExtMem_Boot: Reference boot code executing from internal Flash memory, enabling to configure external memories, then jumping to the user application located in an external memory. Two use cases are possible:
<ul>
<li>XiP: This use case is intended for eXecution in Place from external Flash memory (Octo-SPI or FMC-NOR). The user application code shall be linked to the target execution memory address (external Octo-SPI NOR Flash memory).</li>
<li>BootROM: This use case is intended to demonstrate how to boot from internal Flash memory, configure the external memories, copy user application binary from the SDMMC Flash memory or from Octo-SPI Flash memory to the external memories, and then jump to the user application. The user application code shall be linked to the target execution memory address (external SDRAM/SRAM)</li>
</ul></li>
<li>ExtMem_Application
<ul>
<li>XiP from Octo-SPI or NOR-FMC Flash memory, data stored in external SDRAM</li>
<li>XiP from Octo-SPI or NOR-FMC Flash memory, data stored in external SRAM</li>
<li>XiP from Octo-SPI or NOR-FMC Flash memory, data stored in internal SRAM</li>
<li>BootROM: execution from external SDRAM, data stored in internal SRAM<br />
</li>
<li>BootROM: execution from external SRAM, data stored in internal SRAM</li>
</ul></li>
</ul></li>
</ul></li>
<li>Demonstrations:
<ul>
<li>STM32H7B3I-EVAL: Six sub-demonstrations
<ul>
<li>MenuLauncher based sub-demo</li>
<li>AudioPlayer based sub-demo</li>
<li>ClockAndWeather based sub-demo</li>
<li>TouchGFX based sub-demo</li>
<li>STemWin based sub-demo</li>
<li>EmbeddedWizard based sub-demo</li>
</ul></li>
<li>STM32H743I-EVAL: Three sub-demonstrations
<ul>
<li>TouchGFX based sub-demo</li>
<li>STemWin based sub-demo</li>
<li>EmbeddedWizard based sub-demo</li>
</ul></li>
<li>STM32H747I-EVAL: Four sub-demonstrations
<ul>
<li>MenuLauncher based sub-demo</li>
<li>TouchGFX based sub-demo</li>
<li>STemWin based sub-demo</li>
<li>EmbeddedWizard based sub-demo</li>
</ul></li>
</ul></li>
</ul></li>
</ul>
<h2 id="contents">Contents</h2>
<h3 id="projects">Projects</h3>
<ul>
<li><p>The STM32CubeH7 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains. The exhaustive list of projects is provided in this table <a href="Projects/STM32CubeProjectsList.html">STM32CubeProjectsList.html</a>.</p></li>
<li><p>Projects Release Note is available <a href="Projects/Release_Notes.html">release notes</a></p></li>
</ul>
<h3 id="components">Components</h3>
<table>
<caption>Drivers</caption>
<thead>
<tr class="header">
<th style="text-align: left;">Name</th>
<th style="text-align: center;">Version</th>
<th style="text-align: center;">License</th>
<th style="text-align: center;">Release note</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td style="text-align: left;">Cortex-M CMSIS</td>
<td style="text-align: center;">V5.4.0</td>
<td style="text-align: center;"><a href="Drivers/CMSIS/LICENSE.txt">Apache License 2.0</a></td>
<td style="text-align: center;"><a href="Drivers/CMSIS/docs/General/html/index.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">STM32H7xx CMSIS</td>
<td style="text-align: center;">V1.7.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/Apache-2.0">Apache License 2.0</a></td>
<td style="text-align: center;"><a href="Drivers/CMSIS/Device/ST/STM32H7xx/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">STM32H7xx HAL</td>
<td style="text-align: center;">V1.7.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/STM32H7xx_HAL_Driver/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;"><strong>BSP STM32H7B3I-EVAL</strong></td>
<td style="text-align: center;"><strong>V1.0.1</strong></td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/STM32H7B3I-EVAL/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;"><strong>BSP STM32H7B3I-DK</strong></td>
<td style="text-align: center;"><strong>V1.0.1</strong></td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/STM32H7B3I-DK/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP STM32H743I-EVAL</td>
<td style="text-align: center;">V2.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/STM32H743I-EVAL/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">BSP STM32H7xx_Nucleo</td>
<td style="text-align: center;">V1.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/STM32H7xx_Nucleo/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP STM32H745I-DISCO</td>
<td style="text-align: center;">V2.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/STM32H745I-DISCO/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">BSP STM32H747I-EVAL</td>
<td style="text-align: center;">V2.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/STM32H747I-EVAL/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP STM32H747I-DISCO</td>
<td style="text-align: center;">V2.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/STM32H747I-DISCO/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">BSP STM32H750B-DK</td>
<td style="text-align: center;">V2.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/STM32H750B-DK/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP Adafruit_Shield</td>
<td style="text-align: center;">V4.0.4</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Adafruit_Shield/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">BSP Common</td>
<td style="text-align: center;">V6.0.1</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/common/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP adv7533</td>
<td style="text-align: center;">v2.0.1</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/adv7533/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">BSP ampire480272</td>
<td style="text-align: center;">v1.0.3</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/ampire480272/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP ampire640480</td>
<td style="text-align: center;">v1.0.3</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/ampire640480/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">BSP cs42l51</td>
<td style="text-align: center;">v2.0.1</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/cs42l51/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP exc7200</td>
<td style="text-align: center;">v2.0.1</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/exc7200/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">BSP ft6x06</td>
<td style="text-align: center;">v2.0.1</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/ft6x06/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP ft5336</td>
<td style="text-align: center;">v2.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/ft5336/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">BSP lan8742</td>
<td style="text-align: center;">v1.0.1</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/lan8742/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP mfxstm32l152</td>
<td style="text-align: center;">v3.0.2</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/mfxstm32l152/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">BSP m24lr64</td>
<td style="text-align: center;">v1.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/m24lr64/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP mt25tl01g</td>
<td style="text-align: center;">v2.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/mt25tl01g/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">BSP mx25lm51245g</td>
<td style="text-align: center;">v2.0.1</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/mx25lm51245g/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP mt48lc4m32b2</td>
<td style="text-align: center;">v1.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/mt48lc4m32b2/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">BSP is42s32800j</td>
<td style="text-align: center;">v1.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/is42s32800j/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP is42s32800g</td>
<td style="text-align: center;">v1.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/is42s32800g/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">BSP is42s16800j</td>
<td style="text-align: center;">v1.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/is42s16800j/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP otm8009a</td>
<td style="text-align: center;">v2.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/otm8009a/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">BSP ov9655</td>
<td style="text-align: center;">v2.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/ov9655/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP ov5640</td>
<td style="text-align: center;">v1.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/ov5640/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">BSP rk043fn48h</td>
<td style="text-align: center;">v1.0.3</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/rk043fn48h/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP rk070er9427</td>
<td style="text-align: center;">v1.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/rk070er9427/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">BSP s5k5cag</td>
<td style="text-align: center;">v2.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/s5k5cag/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP st7735</td>
<td style="text-align: center;">v2.0.2</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/st7735/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">BSP stmpe811</td>
<td style="text-align: center;">v3.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/stmpe811/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP ts3510</td>
<td style="text-align: center;">v2.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/ts3510/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">BSP wm8994</td>
<td style="text-align: center;">v3.0.2</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/wm8994/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">BSP es_wifi</td>
<td style="text-align: center;">v1.5.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Drivers/BSP/Components/es_wifi/Release_Notes.html">release notes</a></td>
</tr>
</tbody>
</table>
<table>
<caption>Middlewares</caption>
<thead>
<tr class="header">
<th style="text-align: left;">Name</th>
<th style="text-align: center;">Version</th>
<th style="text-align: center;">License</th>
<th style="text-align: center;">Release note</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td style="text-align: left;"><strong>STM32 USB Host Library</strong></td>
<td style="text-align: center;"><strong>V3.3.4</strong></td>
<td style="text-align: center;"><a href="http://www.st.com/SLA0044">SLA0044</a></td>
<td style="text-align: center;"><a href="Middlewares/ST/STM32_USB_Host_Library/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">STM32 USB Device Library</td>
<td style="text-align: center;">V2.5.3</td>
<td style="text-align: center;"><a href="http://www.st.com/SLA0044">SLA0044</a></td>
<td style="text-align: center;"><a href="Middlewares/ST/STM32_USB_Device_Library/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">FatFS</td>
<td style="text-align: center;">R0.12c</td>
<td style="text-align: center;"><a href="Middlewares/Third_Party/FatFs/doc/en/appnote.html#license">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Middlewares/Third_Party/FatFs/doc/updates.txt">release notes</a> ST modified 20191011 <a href="Middlewares/Third_Party/FatFs/src/st_readme.txt">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">FreeRTOS MPU</td>
<td style="text-align: center;">V10.2.1</td>
<td style="text-align: center;"><a href="Middlewares/Third_Party/FreeRTOS/License/license.txt">MIT</a></td>
<td style="text-align: center;"><a href="Middlewares/Third_Party/FreeRTOS/Source/readme.txt">release notes</a> ST modified 20190719 <a href="Middlewares/Third_Party/FreeRTOS/Source/st_readme.txt">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">LwIP</td>
<td style="text-align: center;">V2.0.3</td>
<td style="text-align: center;"><a href="Middlewares/Third_Party/LwIP/COPYING">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Middlewares/Third_Party/LwIP/CHANGELOG">release notes</a> ST modified 20180813 <a href="Middlewares/Third_Party/LwIP/st_readme.txt">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">STemWin</td>
<td style="text-align: center;">V5.44</td>
<td style="text-align: center;"><a href="http://www.st.com/SLA0044">SLA0044</a></td>
<td style="text-align: center;"><a href="Middlewares/ST/STemWin/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">TouchGFX</td>
<td style="text-align: center;">V4.12.3</td>
<td style="text-align: center;"><a href="Middlewares/ST/TouchGFX/license.txt">SLA0044</a></td>
<td style="text-align: center;"><a href="Middlewares/ST/TouchGFX/changelog.txt">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">LibJPEG</td>
<td style="text-align: center;">V8d</td>
<td style="text-align: center;"><a href="Middlewares/Third_Party/LibJPEG/README">Independent JPEG Group License</a></td>
<td style="text-align: center;"><a href="Middlewares/Third_Party/LibJPEG/change.log">release notes</a> ST modified 20190329 <a href="Middlewares/Third_Party/LibJPEG/st_readme.txt">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">mbedTLS</td>
<td style="text-align: center;">V2.14.1</td>
<td style="text-align: center;"><a href="Middlewares/Third_Party/mbedTLS/apache-2.0.txt">Apache License 2.0</a></td>
<td style="text-align: center;"><a href="Middlewares/Third_Party/mbedTLS/ChangeLog">release notes</a> ST modified 20190329 <a href="Middlewares/Third_Party/mbedTLS/st_readme.txt">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">STM32 PDM audio software decoding Library</td>
<td style="text-align: center;">V3.1.0</td>
<td style="text-align: center;"><a href="http://www.st.com/software_license_agreement_image_v2">SLA0047</a></td>
<td style="text-align: center;"><a href="Middlewares/ST/STM32_Audio/Addons/PDM/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">OpenAmp</td>
<td style="text-align: center;">V2018.10</td>
<td style="text-align: center;"><a href="Middlewares/Third_Party/OpenAMP/open-amp/LICENSE.md">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Middlewares/Third_Party/OpenAMP/open-amp/README.md">release notes</a> ST modified 20191011 <a href="Middlewares/Third_Party/OpenAMP/open-amp/st_readme.txt">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">STM32_Network_Library</td>
<td style="text-align: center;">V1.0.4</td>
<td style="text-align: center;"><a href="Middlewares/ST/STM32_Network_Library/Software_License_Agreement_SLA0044.pdf">SLA0044</a></td>
<td style="text-align: center;"><a href="Middlewares/ST/STM32_Network_Library/Release_notes.html">release notes</a></td>
</tr>
</tbody>
</table>
<table>
<caption>Utilities</caption>
<thead>
<tr class="header">
<th style="text-align: left;">Name</th>
<th style="text-align: center;">Version</th>
<th style="text-align: center;">License</th>
<th style="text-align: center;">Release note</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td style="text-align: left;">CPU</td>
<td style="text-align: center;">V1.1.2 [BS</td>
<td style="text-align: center;">D-3-Clause](https://opensource.org/licenses/BSD-3-Clause) [rel</td>
<td style="text-align: center;">ease notes](Utilities/CPU/Release_Notes.html)</td>
</tr>
<tr class="even">
<td style="text-align: left;">Fonts</td>
<td style="text-align: center;">V2.0.2 [BS</td>
<td style="text-align: center;">D-3-Clause](https://opensource.org/licenses/BSD-3-Clause) [rel</td>
<td style="text-align: center;">ease notes](Utilities/Fonts/Release_Notes.html)</td>
</tr>
<tr class="odd">
<td style="text-align: left;">Lcd_Trace</td>
<td style="text-align: center;">V1.1.0 [BS</td>
<td style="text-align: center;">D-3-Clause](https://opensource.org/licenses/BSD-3-Clause) [rel</td>
<td style="text-align: center;">ease notes](Utilities/Lcd_Trace/Release_Notes.html)</td>
</tr>
<tr class="even">
<td style="text-align: left;">JPEG</td>
<td style="text-align: center;">V2.0.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Utilities/JPEG/Release_Notes.html">release notes</a></td>
</tr>
<tr class="odd">
<td style="text-align: left;">ResourcesManager</td>
<td style="text-align: center;">V1.4.0</td>
<td style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause">BSD-3-Clause</a></td>
<td style="text-align: center;"><a href="Utilities/ResourcesManager/Release_Notes.html">release notes</a></td>
</tr>
<tr class="even">
<td style="text-align: left;">Basic_GUI</td>
<td style="text-align: center;">V1.0.2 [BS</td>
<td style="text-align: center;">D-3-Clause](https://opensource.org/licenses/BSD-3-Clause) [rel</td>
<td style="text-align: center;">ease notes](Utilities/Basic_GUI/Release_Notes.html)</td>
</tr>
<tr class="odd">
<td style="text-align: left;">Common</td>
<td style="text-align: center;">V1.3.0 [BS</td>
<td style="text-align: center;">D-3-Clause](https://opensource.org/licenses/BSD-3-Clause) [rel</td>
<td style="text-align: center;">ease notes](Utilities/Common/Release_Notes.html)</td>
</tr>
</tbody>
</table>
<h2 id="known-limitations">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
<li>Full duplex Transmit/receive feature not available
<ul>
<li>stm32h7xx_hal_i2s_ex.h/stm32h7xx_hal_i2s_ex.c HAL driver are empty files as full duplex feature is not available in this release</li>
</ul></li>
</ul></li>
<li><strong>HAL PSSI</strong>:
<ul>
<li>New PSSI driver provided supporting both modes : DMA mode recommended/ polling mode has hardware limitation confirmed and mentioned in the STM32H7A3/B3xx/B0xx erratasheet.</li>
</ul></li>
<li>OpenAMP-based applications (available on STM32H745I-DISCO, STM32H747I-DISCO and STM32H747I-EVAL) come with known compilation warning
<ul>
<li>Related to the OpenAmp third party stack</li>
<li>Related to ST application implementation For warning details please refer to the corresponding applications readme.txt files</li>
</ul></li>
<li>STM32H747I-DISCO and STM32H750B-DK TouchGFX demonstrations come with known compilation warnings on SW4STM32 IDE:
<ul>
<li>Warnings related to the Libjpeg third party MW</li>
</ul></li>
<li><strong>LwIP</strong>-based applications (available on NUCLEO-H743ZI and STM32H743I-EVAL) come with known compilation warning on EWARM V8.30
<ul>
<li>Related to the combination of LWIP third party stack and EWARM V8.30</li>
</ul></li>
<li><p>No impact of these warnings on the functional behavior</p></li>
<li><strong>STM32H7B3I-EVAL</strong>
<ul>
<li>STM32CubeIDE project is not provided for <strong>AudioPlayer Demonstrations</strong></li>
<li>STM32CubeIDE project is not provided for <strong>STemWin Demonstrations</strong></li>
</ul></li>
<li><strong>STM32H7B3I-DK</strong>
<ul>
<li>STM32CubeIDE project is not provided for <strong>AudioPlayer Demonstrations</strong></li>
<li>STM32CubeIDE project is not provided for <strong>VideoPlayer Demonstrations</strong></li>
</ul></li>
<li><strong>STM32H743I-EVAL</strong>
<ul>
<li>SW4STM32 project is not provided for <strong>TouchGFX Demonstrations</strong></li>
<li>Keil project is not provided for <strong>STemWin Demonstrations</strong></li>
</ul></li>
</ul>
<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1 + ST-LINKV3, patch available here:
<ul>
<li><a href="Utilities\PC_Software\IDEs_Patches\EWARM\EWARMv8_STM32H7xx_Support_V1.2.zip">Utilities\PC_Software\IDEs_Patches\EWARM\EWARMv8_STM32H7xx_Support_V1.2.zip</a>
<ul>
<li>This patch supports STM32H743/753/747/757/745/755/750/742/7B3/7A3/7B0 devices</li>
<li>Note: For STM32H750xx value line devices, this patch allows to program correctly internal flash and the external QSPI flash of the STM32H750B-DISCO board . However, “verify” phase after programming is not functional for the QSPI flash.</li>
</ul></li>
</ul></li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27 + ST-LINKV3, patch available here:
<ul>
<li><a href="Utilities\PC_Software\IDEs_Patches\MDK-ARM\Keil.STM32H7xx_DFP.2.3.4.zip">Utilities\PC_Software\IDEs_Patches\MDK-ARM\Keil.STM32H7xx_DFP.2.3.4.zip</a>
<ul>
<li>This patch supports STM32H743/753/747/757/745/755/750/742/7B3/7A3/7B0 devices devices</li>
</ul></li>
</ul></li>
</ul>
<h2 id="supported-devices-and-eval-boards">Supported Devices and EVAL boards</h2>
<ul>
<li>STM32H743/753/747/757/745/755/750/742/7B3/7A3/7B0 devices</li>
<li>STM32H7B3I-EVAL revD</li>
<li>STM32H7B3I-DK revB</li>
<li>NUCLEO-H7A3ZI-Q revD</li>
<li>STM32H743I-EVAL rev.B/rev.E</li>
<li>NUCLEO-H743ZI rev.B and NUCLEO-H743ZI2 rev.B</li>
<li>NUCLEO-H745ZI-Q rev.B</li>
<li>STM32H745I-DISCO rev.B</li>
<li>STM32H747I-EVAL rev.E</li>
<li>STM32H747I-DISCO rev.D</li>
<li>STM32H750B-DISCO rev.B</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.6.0 / 02-December-2019</strong></label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
<ul>
<li><p>Official release to support STM32H7A3xx, STM32H7A3xxQ, STM32H7B3xx, STM32H7B3xxQ, STM32H7B0xx and STM32H7B0xxQ new devices</p></li>
<li><p>Add support of the STM32H7B3I-DK, STM32H7B3I-EVAL and NUCLEO-H7A3ZI-Q boards. Several examples applications and demonstrations are available on EWARM, Keil and <strong>STM32CubeIDE</strong> IDEs</p></li>
<li><p>Add support of the value line STM32H7B0 devices over STM32H7B3I-DK discovery board. Two examples, with several configurations, are available to show how to boot from internal flash, configure the external memories and jump to user application (located on an external memory)</p></li>
@ -81,7 +688,7 @@
<ul>
<li>Source code available for:
<ul>
<li><strong>MenuLauncher</strong>: Execution from internal flash, allowing to select one of the following sub-demonstration that are executed from external octoSPI NOR flash</li>
<li><strong>MenuLauncher</strong>: Execution from internal flash, allowing to select one of the following sub-demonstrations</li>
<li><strong>AudioPlayer</strong>: Audio Player Demonstration(playing music in WAV and MP3 formats, low power, …)</li>
<li><strong>VideoPlayer</strong>: Video Player Demonstration(movies in AVI mjpeg/wav format, …)</li>
<li><strong>ClockAndWeather</strong>: Clock and Weather Demonstration(Allow to retrieve the time and weather forecast for up six cities, …)<br />
@ -217,13 +824,13 @@
</ul></li>
</ul></li>
</ul>
<h2 id="contents">Contents</h2>
<h3 id="projects">Projects</h3>
<h2 id="contents-1">Contents</h2>
<h3 id="projects-1">Projects</h3>
<ul>
<li><p>The STM32CubeH7 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains. The exhaustive list of projects is provided in this table <a href="Projects/STM32CubeProjectsList.html">STM32CubeProjectsList.html</a>.</p></li>
<li><p>Projects Release Note is available <a href="Projects/Release_Notes.html">release notes</a></p></li>
</ul>
<h3 id="components">Components</h3>
<h3 id="components-1">Components</h3>
<table>
<caption>Drivers</caption>
<thead>
@ -617,7 +1224,7 @@
</tr>
</tbody>
</table>
<h2 id="known-limitations">Known Limitations</h2>
<h2 id="known-limitations-1">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@ -649,7 +1256,7 @@
<li><p><strong>STM32H7B3I-DK</strong> demonstration is provided with EWARM toolchain only</p></li>
<li><p>Value Line applications, STM32H7B3I-DK_CodeExecution, are not supported with STM32CubeIDE toolchain</p></li>
</ul>
<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1 + ST-LINKV3, patch available here:
<ul>
@ -667,11 +1274,11 @@
</ul></li>
</ul></li>
</ul>
<h2 id="supported-devices-and-eval-boards">Supported Devices and EVAL boards</h2>
<h2 id="supported-devices-and-eval-boards-1">Supported Devices and EVAL boards</h2>
<ul>
<li>STM32H743/753/747/757/745/755/750/742/<strong>7B3</strong>/<strong>7A3</strong>/<strong>7B0</strong> devices</li>
<li><strong>STM32H7B3I-EVAL</strong> revD</li>
<li><strong>STM32H7B3I-DK</strong> revD</li>
<li><strong>STM32H7B3I-DK</strong> revB</li>
<li><strong>NUCLEO-H7A3ZI-Q</strong> revD</li>
<li>STM32H743I-EVAL rev.B/rev.E</li>
<li>NUCLEO-H743ZI rev.B and NUCLEO-H743ZI2 rev.B</li>
@ -709,7 +1316,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true"><strong>V1.5.0 / 28-June-2019</strong></label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li><p>Maintenance release.</p></li>
<li>Add <strong>Dual Core</strong> demonstrations source code with preconfigured projects on EWARM, MDK-ARM and SW4STM32 IDEs:
@ -783,13 +1390,13 @@
<li>Update all template projects to add “USE_SPI_CRC” definition to “stm32h7xx_hal_conf.h”. This define is set to 1 by default and customizable by the HAL user</li>
</ul></li>
</ul>
<h2 id="contents-1">Contents</h2>
<h3 id="projects-1">Projects</h3>
<h2 id="contents-2">Contents</h2>
<h3 id="projects-2">Projects</h3>
<ul>
<li><p>The STM32CubeH7 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains. The exhaustive list of projects is provided in this table <a href="Projects/STM32CubeProjectsList.html">STM32CubeProjectsList.html</a>.</p></li>
<li><p>Projects Release Note is available <a href="Projects/Release_Notes.html">release notes</a></p></li>
</ul>
<h3 id="components-1">Components</h3>
<h3 id="components-2">Components</h3>
<table>
<caption>Drivers</caption>
<thead>
@ -1087,7 +1694,7 @@
</tr>
</tbody>
</table>
<h2 id="known-limitations-1">Known Limitations</h2>
<h2 id="known-limitations-2">Known Limitations</h2>
<ul>
<li>OpenAMP-based applications (available on STM32H745I-DISCO, STM32H747I-DISCO and STM32H747I-EVAL) come with known compilation warning
<ul>
@ -1112,7 +1719,7 @@
<li>The source code for this demonstration will be available in next STM32CubeH7 releases</li>
</ul></li>
</ul>
<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2 + ST-LINKV3, patch available here:
<ul>
@ -1130,7 +1737,7 @@
</ul></li>
</ul></li>
</ul>
<h2 id="supported-devices-and-eval-boards-1">Supported Devices and EVAL boards</h2>
<h2 id="supported-devices-and-eval-boards-2">Supported Devices and EVAL boards</h2>
<ul>
<li>STM32H743/753/747/757/745/755/750/742 devices</li>
<li>STM32H743I-EVAL rev.B/rev.E</li>
@ -1159,7 +1766,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.4.0 / 05-April-2019</strong></label>
<div>
<h2 id="main-changes-2">Main Changes</h2>
<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>First official release to support STM32H7 <strong>Rev.V</strong> all lines:
<ul>
@ -1378,13 +1985,13 @@
</ul></li>
</ul></li>
</ul>
<h2 id="contents-2">Contents</h2>
<h3 id="projects-2">Projects</h3>
<h2 id="contents-3">Contents</h2>
<h3 id="projects-3">Projects</h3>
<ul>
<li><p>The STM32CubeH7 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains. The exhaustive list of projects is provided in this table <a href="Projects/STM32CubeProjectsList.html">STM32CubeProjectsList.html</a>.</p></li>
<li><p>Projects Release Note is available <a href="Projects/Release_Notes.html">release notes</a></p></li>
</ul>
<h3 id="components-2">Components</h3>
<h3 id="components-3">Components</h3>
<table>
<caption>Drivers</caption>
<thead>
@ -1682,7 +2289,7 @@
</tr>
</tbody>
</table>
<h2 id="known-limitations-2">Known Limitations</h2>
<h2 id="known-limitations-3">Known Limitations</h2>
<ul>
<li><strong>HAL SD</strong>:
<ul>
@ -1705,7 +2312,7 @@
<li>The source code for these demonstrations will be available in next STM32CubeH7 releases</li>
</ul></li>
</ul>
<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
<h2 id="development-toolchains-and-compilers-3">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2 + ST-LINKV3, patch available here:
<ul>
@ -1723,7 +2330,7 @@
</ul></li>
</ul></li>
</ul>
<h2 id="supported-devices-and-eval-boards-2">Supported Devices and EVAL boards</h2>
<h2 id="supported-devices-and-eval-boards-3">Supported Devices and EVAL boards</h2>
<ul>
<li>STM32H743/753/<strong>747</strong>/<strong>757</strong>/<strong>745</strong>/<strong>755</strong>/750/<strong>742</strong> devices</li>
<li><strong>STM32H743I-EVAL</strong> rev.B/rev.E</li>
@ -1774,7 +2381,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.3.2 / 31-January-2019</strong></label>
<div>
<h2 id="main-changes-3">Main Changes</h2>
<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li><p>Patch release to add definition of UID_BASE (Unique device ID register base address) to the CMSIS STM32H7xx include files.</p></li>
<li><strong>CMSIS</strong>
@ -1787,7 +2394,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.3.1 / 18-January-2019</strong></label>
<div>
<h2 id="main-changes-4">Main Changes</h2>
<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li><p>Patch release to Fix LwIP and mbedTLS applications : enhance Ethernet zero-copy feature allowing to fix ping behavior.</p></li>
<li><strong>Projects</strong>
@ -1808,7 +2415,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label>
<div>
<h2 id="main-changes-5">Main Changes</h2>
<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li><strong>Add support for STM32H750xx value line</strong>
<ul>
@ -1856,13 +2463,13 @@
</ul></li>
</ul></li>
</ul>
<h2 id="contents-3">Contents</h2>
<h3 id="projects-3">Projects</h3>
<h2 id="contents-4">Contents</h2>
<h3 id="projects-4">Projects</h3>
<ul>
<li><p>The STM32CubeH7 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains. The exhaustive list of projects is provided in this table <a href="Projects/STM32CubeProjectsList.html">STM32CubeProjectsList.html</a>.</p></li>
<li><p>Projects Release Note is available <a href="Projects/Release_Notes.html">release notes</a></p></li>
</ul>
<h3 id="components-3">Components</h3>
<h3 id="components-4">Components</h3>
<table>
<caption>Drivers</caption>
<thead>
@ -2106,7 +2713,7 @@
</tr>
</tbody>
</table>
<h2 id="development-toolchains-and-compilers-3">Development Toolchains and Compilers</h2>
<h2 id="development-toolchains-and-compilers-4">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V7.80.4 + ST-LINK
<ul>
@ -2129,7 +2736,7 @@
<li>Note : rely on the STM32CubeProgarmmer to load the external flash application (QSPI flash and FMC-NOR flash)</li>
</ul></li>
</ul>
<h2 id="supported-devices-and-eval-boards-3">Supported Devices and EVAL boards</h2>
<h2 id="supported-devices-and-eval-boards-4">Supported Devices and EVAL boards</h2>
<ul>
<li>STM32H743/753 devices</li>
<li><strong>STM32H750</strong> devices</li>
@ -2145,7 +2752,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label>
<div>
<h2 id="main-changes-6">Main Changes</h2>
<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li><strong>Maintenance release.</strong></li>
<li>General update to fix known defects and several implementations enhancement</li>
@ -2171,13 +2778,13 @@
<li>Update cache management for all examples and applications.</li>
</ul></li>
</ul>
<h2 id="contents-4">Contents</h2>
<h3 id="projects-4">Projects</h3>
<h2 id="contents-5">Contents</h2>
<h3 id="projects-5">Projects</h3>
<ul>
<li><p>The STM32CubeH7 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains. The exhaustive list of projects is provided in this table <a href="Projects/STM32CubeProjectsList.html">STM32CubeProjectsList.html</a>.</p></li>
<li><p>Projects Release Note is available <a href="Projects/Release_Notes.html">release notes</a></p></li>
</ul>
<h3 id="components-4">Components</h3>
<h3 id="components-5">Components</h3>
<table>
<caption>Drivers</caption>
<thead>
@ -2421,13 +3028,13 @@
</tr>
</tbody>
</table>
<h2 id="development-toolchains-and-compilers-4">Development Toolchains and Compilers</h2>
<h2 id="development-toolchains-and-compilers-5">Development Toolchains and Compilers</h2>
<ul>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.23 + ST-LINK</li>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V7.80.4 + ST-LINK</li>
<li>System Workbench for STM32 (SW4STM32) toolchain V1.14 + ST-Link</li>
</ul>
<h2 id="supported-devices-and-eval-boards-4">Supported Devices and EVAL boards</h2>
<h2 id="supported-devices-and-eval-boards-5">Supported Devices and EVAL boards</h2>
<ul>
<li>STM32H743/753 devices</li>
<li>STM32H743XI-EVAL</li>
@ -2442,7 +3049,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label>
<div>
<h2 id="main-changes-7">Main Changes</h2>
<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li><strong>Official release to add Demonstration Firmware for STM32H743I_EVAL.</strong></li>
<li>General update to fix known defects and several implementations enhancement</li>
@ -2490,13 +3097,13 @@
</ul></li>
</ul></li>
</ul>
<h2 id="contents-5">Contents</h2>
<h3 id="projects-5">Projects</h3>
<h2 id="contents-6">Contents</h2>
<h3 id="projects-6">Projects</h3>
<ul>
<li><p>The STM32CubeH7 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains. The exhaustive list of projects is provided in this table <a href="Projects/STM32CubeProjectsList.html">STM32CubeProjectsList.html</a>.</p></li>
<li><p>Projects Release Note is available <a href="Projects/Release_Notes.html">release notes</a></p></li>
</ul>
<h3 id="components-5">Components</h3>
<h3 id="components-6">Components</h3>
<table>
<caption>Drivers</caption>
<thead>
@ -2740,13 +3347,13 @@
</tr>
</tbody>
</table>
<h2 id="development-toolchains-and-compilers-5">Development Toolchains and Compilers</h2>
<h2 id="development-toolchains-and-compilers-6">Development Toolchains and Compilers</h2>
<ul>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.23 + ST-LINK</li>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V7.80.4 + ST-LINK</li>
<li>System Workbench for STM32 (SW4STM32) toolchain V1.14 + ST-Link</li>
</ul>
<h2 id="supported-devices-and-eval-boards-5">Supported Devices and EVAL boards</h2>
<h2 id="supported-devices-and-eval-boards-6">Supported Devices and EVAL boards</h2>
<ul>
<li>STM32H743/753 devices</li>
<li>STM32H743XI-EVAL</li>
@ -2761,17 +3368,17 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label>
<div>
<h2 id="main-changes-8">Main Changes</h2>
<h2 id="main-changes-9">Main Changes</h2>
<ul>
<li><strong>First official release of STM32CubeH7 (STM32Cube for STM32H7 Series)</strong></li>
</ul>
<h2 id="contents-6">Contents</h2>
<h3 id="projects-6">Projects</h3>
<h2 id="contents-7">Contents</h2>
<h3 id="projects-7">Projects</h3>
<ul>
<li><p>The STM32CubeH7 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains. The exhaustive list of projects is provided in this table <a href="Projects/STM32CubeProjectsList.html">STM32CubeProjectsList.html</a>.</p></li>
<li><p>Projects Release Note is available <a href="Projects/Release_Notes.html">release notes</a></p></li>
</ul>
<h3 id="components-6">Components</h3>
<h3 id="components-7">Components</h3>
<table>
<caption>Drivers</caption>
<thead>
@ -3015,13 +3622,13 @@
</tr>
</tbody>
</table>
<h2 id="development-toolchains-and-compilers-6">Development Toolchains and Compilers</h2>
<h2 id="development-toolchains-and-compilers-7">Development Toolchains and Compilers</h2>
<ul>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.23 + ST-LINK</li>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V7.80.4 + ST-LINK</li>
<li>System Workbench for STM32 (SW4STM32) toolchain V1.14 + ST-Link</li>
</ul>
<h2 id="supported-devices-and-eval-boards-6">Supported Devices and EVAL boards</h2>
<h2 id="supported-devices-and-eval-boards-7">Supported Devices and EVAL boards</h2>
<ul>
<li>STM32H743/753 devices</li>
<li>STM32H743XI-EVAL</li>

23
stm32cube/stm32h7xx/soc/stm32h742xx.h
View File

@ -8403,6 +8403,9 @@ typedef struct
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_TRBUFF_Pos (20U)
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@ -14529,12 +14532,6 @@ typedef struct
#define RCC_AHB2ENR_DCMIEN_Pos (0U)
#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
#define RCC_AHB2ENR_CRYPEN_Pos (4U)
#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
#define RCC_AHB2ENR_HASHEN_Pos (5U)
#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
#define RCC_AHB2ENR_RNGEN_Pos (6U)
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
@ -14848,12 +14845,6 @@ typedef struct
#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
#define RCC_AHB2RSTR_HASHRST_Pos (5U)
#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
#define RCC_AHB2RSTR_RNGRST_Pos (6U)
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
@ -15223,12 +15214,6 @@ typedef struct
#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
@ -20369,6 +20354,8 @@ typedef struct
/* DBG */
/* */
/******************************************************************************/
/********************************* DEVICE ID ********************************/
#define STM32H7_DEV_ID 0x450UL
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

23
stm32cube/stm32h7xx/soc/stm32h743xx.h
View File

@ -8498,6 +8498,9 @@ typedef struct
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_TRBUFF_Pos (20U)
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@ -15162,12 +15165,6 @@ typedef struct
#define RCC_AHB2ENR_DCMIEN_Pos (0U)
#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
#define RCC_AHB2ENR_CRYPEN_Pos (4U)
#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
#define RCC_AHB2ENR_HASHEN_Pos (5U)
#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
#define RCC_AHB2ENR_RNGEN_Pos (6U)
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
@ -15487,12 +15484,6 @@ typedef struct
#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
#define RCC_AHB2RSTR_HASHRST_Pos (5U)
#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
#define RCC_AHB2RSTR_RNGRST_Pos (6U)
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
@ -15868,12 +15859,6 @@ typedef struct
#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
@ -21017,6 +21002,8 @@ typedef struct
/* DBG */
/* */
/******************************************************************************/
/********************************* DEVICE ID ********************************/
#define STM32H7_DEV_ID 0x450UL
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

23
stm32cube/stm32h7xx/soc/stm32h745xx.h
View File

@ -8601,6 +8601,9 @@ typedef struct
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_TRBUFF_Pos (20U)
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@ -15753,12 +15756,6 @@ typedef struct
#define RCC_AHB2ENR_DCMIEN_Pos (0U)
#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
#define RCC_AHB2ENR_CRYPEN_Pos (4U)
#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
#define RCC_AHB2ENR_HASHEN_Pos (5U)
#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
#define RCC_AHB2ENR_RNGEN_Pos (6U)
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
@ -16084,12 +16081,6 @@ typedef struct
#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
#define RCC_AHB2RSTR_HASHRST_Pos (5U)
#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
#define RCC_AHB2RSTR_RNGRST_Pos (6U)
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
@ -16477,12 +16468,6 @@ typedef struct
#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
@ -21671,6 +21656,8 @@ typedef struct
/* DBG */
/* */
/******************************************************************************/
/********************************* DEVICE ID ********************************/
#define STM32H7_DEV_ID 0x450UL
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

23
stm32cube/stm32h7xx/soc/stm32h747xx.h
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@ -8684,6 +8684,9 @@ typedef struct
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_TRBUFF_Pos (20U)
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@ -18913,12 +18916,6 @@ typedef struct
#define RCC_AHB2ENR_DCMIEN_Pos (0U)
#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
#define RCC_AHB2ENR_CRYPEN_Pos (4U)
#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
#define RCC_AHB2ENR_HASHEN_Pos (5U)
#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
#define RCC_AHB2ENR_RNGEN_Pos (6U)
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
@ -19247,12 +19244,6 @@ typedef struct
#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
#define RCC_AHB2RSTR_HASHRST_Pos (5U)
#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
#define RCC_AHB2RSTR_RNGRST_Pos (6U)
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
@ -19643,12 +19634,6 @@ typedef struct
#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
@ -24844,6 +24829,8 @@ typedef struct
/* DBG */
/* */
/******************************************************************************/
/********************************* DEVICE ID ********************************/
#define STM32H7_DEV_ID 0x450UL
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

5
stm32cube/stm32h7xx/soc/stm32h750xx.h
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@ -8691,6 +8691,9 @@ typedef struct
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_TRBUFF_Pos (20U)
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@ -21285,6 +21288,8 @@ typedef struct
/* DBG */
/* */
/******************************************************************************/
/********************************* DEVICE ID ********************************/
#define STM32H7_DEV_ID 0x450UL
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

5
stm32cube/stm32h7xx/soc/stm32h753xx.h
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@ -8691,6 +8691,9 @@ typedef struct
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_TRBUFF_Pos (20U)
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@ -21286,6 +21289,8 @@ typedef struct
/* DBG */
/* */
/******************************************************************************/
/********************************* DEVICE ID ********************************/
#define STM32H7_DEV_ID 0x450UL
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

5
stm32cube/stm32h7xx/soc/stm32h755xx.h
View File

@ -8794,6 +8794,9 @@ typedef struct
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_TRBUFF_Pos (20U)
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@ -21940,6 +21943,8 @@ typedef struct
/* DBG */
/* */
/******************************************************************************/
/********************************* DEVICE ID ********************************/
#define STM32H7_DEV_ID 0x450UL
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

5
stm32cube/stm32h7xx/soc/stm32h757xx.h
View File

@ -8877,6 +8877,9 @@ typedef struct
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_TRBUFF_Pos (20U)
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@ -25113,6 +25116,8 @@ typedef struct
/* DBG */
/* */
/******************************************************************************/
/********************************* DEVICE ID ********************************/
#define STM32H7_DEV_ID 0x450UL
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

83
stm32cube/stm32h7xx/soc/stm32h7a3xx.h
View File

@ -874,11 +874,7 @@ typedef struct
__IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */
__IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */
__IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */
uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */
__IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */
__IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */
__IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */
__IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */
uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */
__IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC
For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
} GFXMMU_TypeDef;
@ -1821,7 +1817,7 @@ typedef struct
typedef struct
{
__IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */
__IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */
__IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */
} OCTOSPIM_TypeDef;
/**
@ -6497,6 +6493,9 @@ typedef struct
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_TRBUFF_Pos (20U)
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@ -9463,29 +9462,6 @@ typedef struct
#define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_HWCFGR register ****************/
#define GFXMMU_HWCFGR_TBD_Pos (0U)
#define GFXMMU_HWCFGR_TBD_Msk (0xFFFFFFFFUL << GFXMMU_HWCFGR_TBD_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_HWCFGR_TBD GFXMMU_HWCFGR_TBD_Msk /*!< TBD[31:0] bits (To be defined) */
/****************** Bits definition for GFXMMU_VERR register ******************/
#define GFXMMU_VERR_MINREV_Pos (0U)
#define GFXMMU_VERR_MINREV_Msk (0xFUL << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */
#define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define GFXMMU_VERR_MAJREV_Pos (4U)
#define GFXMMU_VERR_MAJREV_Msk (0xFUL << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/****************** Bits definition for GFXMMU_IPIDR register *****************/
#define GFXMMU_IPIDR_ID_Pos (0U)
#define GFXMMU_IPIDR_ID_Msk (0xFFFFFFFFUL << GFXMMU_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_IPIDR_ID GFXMMU_IPIDR_ID_Msk /*!< ID[31:0] bits (Identification code) */
/****************** Bits definition for GFXMMU_SIDR register ******************/
#define GFXMMU_SIDR_SID_Pos (0U)
#define GFXMMU_SIDR_SID_Msk (0xFFFFFFFFUL << GFXMMU_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_SIDR_SID GFXMMU_SIDR_SID_Msk /*!< SID[31:0] bits (Size and id) */
/****************** Bits definition for GFXMMU_LUTxL register *****************/
#define GFXMMU_LUTxL_EN_Pos (0U)
#define GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */
@ -13342,12 +13318,6 @@ typedef struct
#define RCC_AHB2ENR_HSEMEN_Pos (2U)
#define RCC_AHB2ENR_HSEMEN_Msk (0x1UL << RCC_AHB2ENR_HSEMEN_Pos) /*!< 0x00000004 */
#define RCC_AHB2ENR_HSEMEN RCC_AHB2ENR_HSEMEN_Msk
#define RCC_AHB2ENR_CRYPEN_Pos (4U)
#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
#define RCC_AHB2ENR_HASHEN_Pos (5U)
#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
#define RCC_AHB2ENR_RNGEN_Pos (6U)
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
@ -13663,12 +13633,6 @@ typedef struct
#define RCC_AHB2RSTR_HSEMRST_Pos (2U)
#define RCC_AHB2RSTR_HSEMRST_Msk (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos) /*!< 0x00000004 */
#define RCC_AHB2RSTR_HSEMRST RCC_AHB2RSTR_HSEMRST_Msk
#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
#define RCC_AHB2RSTR_HASHRST_Pos (5U)
#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
#define RCC_AHB2RSTR_RNGRST_Pos (6U)
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
@ -14096,12 +14060,6 @@ typedef struct
#define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos (0U)
#define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos) /*!< 0x00000001 */
#define RCC_AHB2LPENR_DCMI_PSSILPEN RCC_AHB2LPENR_DCMI_PSSILPEN_Msk
#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
@ -18949,39 +18907,48 @@ typedef struct
/* OCTOSPIM */
/* */
/******************************************************************************/
/*************** Bit definition for OCTOSPIM_CR register ********************/
#define OCTOSPIM_CR_MUXEN_Pos (0U)
#define OCTOSPIM_CR_MUXEN_Msk (0x1UL << OCTOSPIM_CR_MUXEN_Pos) /*!< 0x00000001 */
#define OCTOSPIM_CR_MUXEN OCTOSPIM_CR_MUXEN_Msk /*!< Multiplexed mode enable */
#define OCTOSPIM_CR_REQ2ACK_TIME_Pos (16U)
#define OCTOSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */
#define OCTOSPIM_CR_REQ2ACK_TIME OCTOSPIM_CR_REQ2ACK_TIME_Msk /*!< REQ to ACK time */
/*************** Bit definition for OCTOSPIM_PCR register *******************/
#define OCTOSPIM_PCR_CLKEN_Pos (0U)
#define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */
#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
#define OCTOSPIM_PCR_CLKSRC_Pos (1U)
#define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */
#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */
#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */
#define OCTOSPIM_PCR_DQSEN_Pos (4U)
#define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */
#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
#define OCTOSPIM_PCR_DQSSRC_Pos (5U)
#define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */
#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
#define OCTOSPIM_PCR_NCSEN_Pos (8U)
#define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100 */
#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */
#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */
#define OCTOSPIM_PCR_NCSSRC_Pos (9U)
#define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200 */
#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
#define OCTOSPIM_PCR_IOLEN_Pos (16U)
#define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000 */
#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
#define OCTOSPIM_PCR_IOLSRC_Pos (17U)
#define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000 */
#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
#define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */
#define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */
#define OCTOSPIM_PCR_IOHEN_Pos (24U)
#define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000 */
#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
#define OCTOSPIM_PCR_IOHSRC_Pos (25U)
#define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000 */
#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
#define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000 */
#define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000 */
/******************************************************************************/
@ -19751,6 +19718,8 @@ typedef struct
/* DBG */
/* */
/******************************************************************************/
/********************************* DEVICE ID ********************************/
#define STM32H7_DEV_ID 0x480UL
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

83
stm32cube/stm32h7xx/soc/stm32h7a3xxq.h
View File

@ -875,11 +875,7 @@ typedef struct
__IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */
__IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */
__IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */
uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */
__IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */
__IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */
__IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */
__IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */
uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */
__IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC
For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
} GFXMMU_TypeDef;
@ -1822,7 +1818,7 @@ typedef struct
typedef struct
{
__IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */
__IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */
__IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */
} OCTOSPIM_TypeDef;
/**
@ -6498,6 +6494,9 @@ typedef struct
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_TRBUFF_Pos (20U)
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@ -9464,29 +9463,6 @@ typedef struct
#define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_HWCFGR register ****************/
#define GFXMMU_HWCFGR_TBD_Pos (0U)
#define GFXMMU_HWCFGR_TBD_Msk (0xFFFFFFFFUL << GFXMMU_HWCFGR_TBD_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_HWCFGR_TBD GFXMMU_HWCFGR_TBD_Msk /*!< TBD[31:0] bits (To be defined) */
/****************** Bits definition for GFXMMU_VERR register ******************/
#define GFXMMU_VERR_MINREV_Pos (0U)
#define GFXMMU_VERR_MINREV_Msk (0xFUL << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */
#define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define GFXMMU_VERR_MAJREV_Pos (4U)
#define GFXMMU_VERR_MAJREV_Msk (0xFUL << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/****************** Bits definition for GFXMMU_IPIDR register *****************/
#define GFXMMU_IPIDR_ID_Pos (0U)
#define GFXMMU_IPIDR_ID_Msk (0xFFFFFFFFUL << GFXMMU_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_IPIDR_ID GFXMMU_IPIDR_ID_Msk /*!< ID[31:0] bits (Identification code) */
/****************** Bits definition for GFXMMU_SIDR register ******************/
#define GFXMMU_SIDR_SID_Pos (0U)
#define GFXMMU_SIDR_SID_Msk (0xFFFFFFFFUL << GFXMMU_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_SIDR_SID GFXMMU_SIDR_SID_Msk /*!< SID[31:0] bits (Size and id) */
/****************** Bits definition for GFXMMU_LUTxL register *****************/
#define GFXMMU_LUTxL_EN_Pos (0U)
#define GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */
@ -13354,12 +13330,6 @@ typedef struct
#define RCC_AHB2ENR_HSEMEN_Pos (2U)
#define RCC_AHB2ENR_HSEMEN_Msk (0x1UL << RCC_AHB2ENR_HSEMEN_Pos) /*!< 0x00000004 */
#define RCC_AHB2ENR_HSEMEN RCC_AHB2ENR_HSEMEN_Msk
#define RCC_AHB2ENR_CRYPEN_Pos (4U)
#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
#define RCC_AHB2ENR_HASHEN_Pos (5U)
#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
#define RCC_AHB2ENR_RNGEN_Pos (6U)
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
@ -13675,12 +13645,6 @@ typedef struct
#define RCC_AHB2RSTR_HSEMRST_Pos (2U)
#define RCC_AHB2RSTR_HSEMRST_Msk (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos) /*!< 0x00000004 */
#define RCC_AHB2RSTR_HSEMRST RCC_AHB2RSTR_HSEMRST_Msk
#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
#define RCC_AHB2RSTR_HASHRST_Pos (5U)
#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
#define RCC_AHB2RSTR_RNGRST_Pos (6U)
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
@ -14108,12 +14072,6 @@ typedef struct
#define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos (0U)
#define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos) /*!< 0x00000001 */
#define RCC_AHB2LPENR_DCMI_PSSILPEN RCC_AHB2LPENR_DCMI_PSSILPEN_Msk
#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
@ -18961,39 +18919,48 @@ typedef struct
/* OCTOSPIM */
/* */
/******************************************************************************/
/*************** Bit definition for OCTOSPIM_CR register ********************/
#define OCTOSPIM_CR_MUXEN_Pos (0U)
#define OCTOSPIM_CR_MUXEN_Msk (0x1UL << OCTOSPIM_CR_MUXEN_Pos) /*!< 0x00000001 */
#define OCTOSPIM_CR_MUXEN OCTOSPIM_CR_MUXEN_Msk /*!< Multiplexed mode enable */
#define OCTOSPIM_CR_REQ2ACK_TIME_Pos (16U)
#define OCTOSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */
#define OCTOSPIM_CR_REQ2ACK_TIME OCTOSPIM_CR_REQ2ACK_TIME_Msk /*!< REQ to ACK time */
/*************** Bit definition for OCTOSPIM_PCR register *******************/
#define OCTOSPIM_PCR_CLKEN_Pos (0U)
#define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */
#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
#define OCTOSPIM_PCR_CLKSRC_Pos (1U)
#define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */
#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */
#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */
#define OCTOSPIM_PCR_DQSEN_Pos (4U)
#define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */
#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
#define OCTOSPIM_PCR_DQSSRC_Pos (5U)
#define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */
#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
#define OCTOSPIM_PCR_NCSEN_Pos (8U)
#define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100 */
#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */
#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */
#define OCTOSPIM_PCR_NCSSRC_Pos (9U)
#define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200 */
#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
#define OCTOSPIM_PCR_IOLEN_Pos (16U)
#define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000 */
#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
#define OCTOSPIM_PCR_IOLSRC_Pos (17U)
#define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000 */
#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
#define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */
#define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */
#define OCTOSPIM_PCR_IOHEN_Pos (24U)
#define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000 */
#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
#define OCTOSPIM_PCR_IOHSRC_Pos (25U)
#define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000 */
#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
#define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000 */
#define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000 */
/******************************************************************************/
@ -19763,6 +19730,8 @@ typedef struct
/* DBG */
/* */
/******************************************************************************/
/********************************* DEVICE ID ********************************/
#define STM32H7_DEV_ID 0x480UL
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

65
stm32cube/stm32h7xx/soc/stm32h7b0xx.h
View File

@ -877,11 +877,7 @@ typedef struct
__IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */
__IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */
__IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */
uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */
__IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */
__IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */
__IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */
__IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */
uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */
__IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC
For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
} GFXMMU_TypeDef;
@ -1893,7 +1889,7 @@ typedef struct
typedef struct
{
__IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */
__IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */
__IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */
} OCTOSPIM_TypeDef;
/**
@ -6751,6 +6747,9 @@ typedef struct
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_TRBUFF_Pos (20U)
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@ -9716,29 +9715,6 @@ typedef struct
#define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_HWCFGR register ****************/
#define GFXMMU_HWCFGR_TBD_Pos (0U)
#define GFXMMU_HWCFGR_TBD_Msk (0xFFFFFFFFUL << GFXMMU_HWCFGR_TBD_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_HWCFGR_TBD GFXMMU_HWCFGR_TBD_Msk /*!< TBD[31:0] bits (To be defined) */
/****************** Bits definition for GFXMMU_VERR register ******************/
#define GFXMMU_VERR_MINREV_Pos (0U)
#define GFXMMU_VERR_MINREV_Msk (0xFUL << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */
#define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define GFXMMU_VERR_MAJREV_Pos (4U)
#define GFXMMU_VERR_MAJREV_Msk (0xFUL << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/****************** Bits definition for GFXMMU_IPIDR register *****************/
#define GFXMMU_IPIDR_ID_Pos (0U)
#define GFXMMU_IPIDR_ID_Msk (0xFFFFFFFFUL << GFXMMU_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_IPIDR_ID GFXMMU_IPIDR_ID_Msk /*!< ID[31:0] bits (Identification code) */
/****************** Bits definition for GFXMMU_SIDR register ******************/
#define GFXMMU_SIDR_SID_Pos (0U)
#define GFXMMU_SIDR_SID_Msk (0xFFFFFFFFUL << GFXMMU_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_SIDR_SID GFXMMU_SIDR_SID_Msk /*!< SID[31:0] bits (Size and id) */
/****************** Bits definition for GFXMMU_LUTxL register *****************/
#define GFXMMU_LUTxL_EN_Pos (0U)
#define GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */
@ -19417,39 +19393,48 @@ typedef struct
/* OCTOSPIM */
/* */
/******************************************************************************/
/*************** Bit definition for OCTOSPIM_CR register ********************/
#define OCTOSPIM_CR_MUXEN_Pos (0U)
#define OCTOSPIM_CR_MUXEN_Msk (0x1UL << OCTOSPIM_CR_MUXEN_Pos) /*!< 0x00000001 */
#define OCTOSPIM_CR_MUXEN OCTOSPIM_CR_MUXEN_Msk /*!< Multiplexed mode enable */
#define OCTOSPIM_CR_REQ2ACK_TIME_Pos (16U)
#define OCTOSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */
#define OCTOSPIM_CR_REQ2ACK_TIME OCTOSPIM_CR_REQ2ACK_TIME_Msk /*!< REQ to ACK time */
/*************** Bit definition for OCTOSPIM_PCR register *******************/
#define OCTOSPIM_PCR_CLKEN_Pos (0U)
#define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */
#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
#define OCTOSPIM_PCR_CLKSRC_Pos (1U)
#define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */
#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */
#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */
#define OCTOSPIM_PCR_DQSEN_Pos (4U)
#define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */
#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
#define OCTOSPIM_PCR_DQSSRC_Pos (5U)
#define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */
#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
#define OCTOSPIM_PCR_NCSEN_Pos (8U)
#define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100 */
#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */
#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */
#define OCTOSPIM_PCR_NCSSRC_Pos (9U)
#define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200 */
#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
#define OCTOSPIM_PCR_IOLEN_Pos (16U)
#define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000 */
#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
#define OCTOSPIM_PCR_IOLSRC_Pos (17U)
#define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000 */
#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
#define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */
#define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */
#define OCTOSPIM_PCR_IOHEN_Pos (24U)
#define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000 */
#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
#define OCTOSPIM_PCR_IOHSRC_Pos (25U)
#define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000 */
#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
#define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000 */
#define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000 */
/******************************************************************************/
@ -20219,6 +20204,8 @@ typedef struct
/* DBG */
/* */
/******************************************************************************/
/********************************* DEVICE ID ********************************/
#define STM32H7_DEV_ID 0x480UL
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

65
stm32cube/stm32h7xx/soc/stm32h7b0xxq.h
View File

@ -878,11 +878,7 @@ typedef struct
__IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */
__IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */
__IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */
uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */
__IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */
__IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */
__IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */
__IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */
uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */
__IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC
For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
} GFXMMU_TypeDef;
@ -1894,7 +1890,7 @@ typedef struct
typedef struct
{
__IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */
__IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */
__IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */
} OCTOSPIM_TypeDef;
/**
@ -6752,6 +6748,9 @@ typedef struct
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_TRBUFF_Pos (20U)
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@ -9717,29 +9716,6 @@ typedef struct
#define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_HWCFGR register ****************/
#define GFXMMU_HWCFGR_TBD_Pos (0U)
#define GFXMMU_HWCFGR_TBD_Msk (0xFFFFFFFFUL << GFXMMU_HWCFGR_TBD_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_HWCFGR_TBD GFXMMU_HWCFGR_TBD_Msk /*!< TBD[31:0] bits (To be defined) */
/****************** Bits definition for GFXMMU_VERR register ******************/
#define GFXMMU_VERR_MINREV_Pos (0U)
#define GFXMMU_VERR_MINREV_Msk (0xFUL << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */
#define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define GFXMMU_VERR_MAJREV_Pos (4U)
#define GFXMMU_VERR_MAJREV_Msk (0xFUL << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/****************** Bits definition for GFXMMU_IPIDR register *****************/
#define GFXMMU_IPIDR_ID_Pos (0U)
#define GFXMMU_IPIDR_ID_Msk (0xFFFFFFFFUL << GFXMMU_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_IPIDR_ID GFXMMU_IPIDR_ID_Msk /*!< ID[31:0] bits (Identification code) */
/****************** Bits definition for GFXMMU_SIDR register ******************/
#define GFXMMU_SIDR_SID_Pos (0U)
#define GFXMMU_SIDR_SID_Msk (0xFFFFFFFFUL << GFXMMU_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_SIDR_SID GFXMMU_SIDR_SID_Msk /*!< SID[31:0] bits (Size and id) */
/****************** Bits definition for GFXMMU_LUTxL register *****************/
#define GFXMMU_LUTxL_EN_Pos (0U)
#define GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */
@ -19429,39 +19405,48 @@ typedef struct
/* OCTOSPIM */
/* */
/******************************************************************************/
/*************** Bit definition for OCTOSPIM_CR register ********************/
#define OCTOSPIM_CR_MUXEN_Pos (0U)
#define OCTOSPIM_CR_MUXEN_Msk (0x1UL << OCTOSPIM_CR_MUXEN_Pos) /*!< 0x00000001 */
#define OCTOSPIM_CR_MUXEN OCTOSPIM_CR_MUXEN_Msk /*!< Multiplexed mode enable */
#define OCTOSPIM_CR_REQ2ACK_TIME_Pos (16U)
#define OCTOSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */
#define OCTOSPIM_CR_REQ2ACK_TIME OCTOSPIM_CR_REQ2ACK_TIME_Msk /*!< REQ to ACK time */
/*************** Bit definition for OCTOSPIM_PCR register *******************/
#define OCTOSPIM_PCR_CLKEN_Pos (0U)
#define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */
#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
#define OCTOSPIM_PCR_CLKSRC_Pos (1U)
#define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */
#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */
#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */
#define OCTOSPIM_PCR_DQSEN_Pos (4U)
#define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */
#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
#define OCTOSPIM_PCR_DQSSRC_Pos (5U)
#define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */
#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
#define OCTOSPIM_PCR_NCSEN_Pos (8U)
#define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100 */
#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */
#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */
#define OCTOSPIM_PCR_NCSSRC_Pos (9U)
#define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200 */
#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
#define OCTOSPIM_PCR_IOLEN_Pos (16U)
#define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000 */
#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
#define OCTOSPIM_PCR_IOLSRC_Pos (17U)
#define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000 */
#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
#define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */
#define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */
#define OCTOSPIM_PCR_IOHEN_Pos (24U)
#define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000 */
#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
#define OCTOSPIM_PCR_IOHSRC_Pos (25U)
#define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000 */
#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
#define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000 */
#define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000 */
/******************************************************************************/
@ -20231,6 +20216,8 @@ typedef struct
/* DBG */
/* */
/******************************************************************************/
/********************************* DEVICE ID ********************************/
#define STM32H7_DEV_ID 0x480UL
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

65
stm32cube/stm32h7xx/soc/stm32h7b3xx.h
View File

@ -877,11 +877,7 @@ typedef struct
__IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */
__IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */
__IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */
uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */
__IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */
__IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */
__IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */
__IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */
uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */
__IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC
For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
} GFXMMU_TypeDef;
@ -1893,7 +1889,7 @@ typedef struct
typedef struct
{
__IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */
__IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */
__IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */
} OCTOSPIM_TypeDef;
/**
@ -6751,6 +6747,9 @@ typedef struct
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_TRBUFF_Pos (20U)
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@ -9717,29 +9716,6 @@ typedef struct
#define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_HWCFGR register ****************/
#define GFXMMU_HWCFGR_TBD_Pos (0U)
#define GFXMMU_HWCFGR_TBD_Msk (0xFFFFFFFFUL << GFXMMU_HWCFGR_TBD_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_HWCFGR_TBD GFXMMU_HWCFGR_TBD_Msk /*!< TBD[31:0] bits (To be defined) */
/****************** Bits definition for GFXMMU_VERR register ******************/
#define GFXMMU_VERR_MINREV_Pos (0U)
#define GFXMMU_VERR_MINREV_Msk (0xFUL << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */
#define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define GFXMMU_VERR_MAJREV_Pos (4U)
#define GFXMMU_VERR_MAJREV_Msk (0xFUL << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/****************** Bits definition for GFXMMU_IPIDR register *****************/
#define GFXMMU_IPIDR_ID_Pos (0U)
#define GFXMMU_IPIDR_ID_Msk (0xFFFFFFFFUL << GFXMMU_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_IPIDR_ID GFXMMU_IPIDR_ID_Msk /*!< ID[31:0] bits (Identification code) */
/****************** Bits definition for GFXMMU_SIDR register ******************/
#define GFXMMU_SIDR_SID_Pos (0U)
#define GFXMMU_SIDR_SID_Msk (0xFFFFFFFFUL << GFXMMU_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_SIDR_SID GFXMMU_SIDR_SID_Msk /*!< SID[31:0] bits (Size and id) */
/****************** Bits definition for GFXMMU_LUTxL register *****************/
#define GFXMMU_LUTxL_EN_Pos (0U)
#define GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */
@ -19418,39 +19394,48 @@ typedef struct
/* OCTOSPIM */
/* */
/******************************************************************************/
/*************** Bit definition for OCTOSPIM_CR register ********************/
#define OCTOSPIM_CR_MUXEN_Pos (0U)
#define OCTOSPIM_CR_MUXEN_Msk (0x1UL << OCTOSPIM_CR_MUXEN_Pos) /*!< 0x00000001 */
#define OCTOSPIM_CR_MUXEN OCTOSPIM_CR_MUXEN_Msk /*!< Multiplexed mode enable */
#define OCTOSPIM_CR_REQ2ACK_TIME_Pos (16U)
#define OCTOSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */
#define OCTOSPIM_CR_REQ2ACK_TIME OCTOSPIM_CR_REQ2ACK_TIME_Msk /*!< REQ to ACK time */
/*************** Bit definition for OCTOSPIM_PCR register *******************/
#define OCTOSPIM_PCR_CLKEN_Pos (0U)
#define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */
#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
#define OCTOSPIM_PCR_CLKSRC_Pos (1U)
#define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */
#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */
#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */
#define OCTOSPIM_PCR_DQSEN_Pos (4U)
#define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */
#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
#define OCTOSPIM_PCR_DQSSRC_Pos (5U)
#define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */
#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
#define OCTOSPIM_PCR_NCSEN_Pos (8U)
#define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100 */
#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */
#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */
#define OCTOSPIM_PCR_NCSSRC_Pos (9U)
#define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200 */
#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
#define OCTOSPIM_PCR_IOLEN_Pos (16U)
#define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000 */
#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
#define OCTOSPIM_PCR_IOLSRC_Pos (17U)
#define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000 */
#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
#define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */
#define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */
#define OCTOSPIM_PCR_IOHEN_Pos (24U)
#define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000 */
#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
#define OCTOSPIM_PCR_IOHSRC_Pos (25U)
#define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000 */
#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
#define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000 */
#define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000 */
/******************************************************************************/
@ -20220,6 +20205,8 @@ typedef struct
/* DBG */
/* */
/******************************************************************************/
/********************************* DEVICE ID ********************************/
#define STM32H7_DEV_ID 0x480UL
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

65
stm32cube/stm32h7xx/soc/stm32h7b3xxq.h
View File

@ -878,11 +878,7 @@ typedef struct
__IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */
__IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */
__IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */
uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */
__IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */
__IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */
__IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */
__IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */
uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */
__IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC
For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
} GFXMMU_TypeDef;
@ -1894,7 +1890,7 @@ typedef struct
typedef struct
{
__IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */
__IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */
__IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */
} OCTOSPIM_TypeDef;
/**
@ -6752,6 +6748,9 @@ typedef struct
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_TRBUFF_Pos (20U)
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@ -9718,29 +9717,6 @@ typedef struct
#define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_HWCFGR register ****************/
#define GFXMMU_HWCFGR_TBD_Pos (0U)
#define GFXMMU_HWCFGR_TBD_Msk (0xFFFFFFFFUL << GFXMMU_HWCFGR_TBD_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_HWCFGR_TBD GFXMMU_HWCFGR_TBD_Msk /*!< TBD[31:0] bits (To be defined) */
/****************** Bits definition for GFXMMU_VERR register ******************/
#define GFXMMU_VERR_MINREV_Pos (0U)
#define GFXMMU_VERR_MINREV_Msk (0xFUL << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */
#define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define GFXMMU_VERR_MAJREV_Pos (4U)
#define GFXMMU_VERR_MAJREV_Msk (0xFUL << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/****************** Bits definition for GFXMMU_IPIDR register *****************/
#define GFXMMU_IPIDR_ID_Pos (0U)
#define GFXMMU_IPIDR_ID_Msk (0xFFFFFFFFUL << GFXMMU_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_IPIDR_ID GFXMMU_IPIDR_ID_Msk /*!< ID[31:0] bits (Identification code) */
/****************** Bits definition for GFXMMU_SIDR register ******************/
#define GFXMMU_SIDR_SID_Pos (0U)
#define GFXMMU_SIDR_SID_Msk (0xFFFFFFFFUL << GFXMMU_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_SIDR_SID GFXMMU_SIDR_SID_Msk /*!< SID[31:0] bits (Size and id) */
/****************** Bits definition for GFXMMU_LUTxL register *****************/
#define GFXMMU_LUTxL_EN_Pos (0U)
#define GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */
@ -19430,39 +19406,48 @@ typedef struct
/* OCTOSPIM */
/* */
/******************************************************************************/
/*************** Bit definition for OCTOSPIM_CR register ********************/
#define OCTOSPIM_CR_MUXEN_Pos (0U)
#define OCTOSPIM_CR_MUXEN_Msk (0x1UL << OCTOSPIM_CR_MUXEN_Pos) /*!< 0x00000001 */
#define OCTOSPIM_CR_MUXEN OCTOSPIM_CR_MUXEN_Msk /*!< Multiplexed mode enable */
#define OCTOSPIM_CR_REQ2ACK_TIME_Pos (16U)
#define OCTOSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */
#define OCTOSPIM_CR_REQ2ACK_TIME OCTOSPIM_CR_REQ2ACK_TIME_Msk /*!< REQ to ACK time */
/*************** Bit definition for OCTOSPIM_PCR register *******************/
#define OCTOSPIM_PCR_CLKEN_Pos (0U)
#define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */
#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
#define OCTOSPIM_PCR_CLKSRC_Pos (1U)
#define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */
#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */
#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */
#define OCTOSPIM_PCR_DQSEN_Pos (4U)
#define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */
#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
#define OCTOSPIM_PCR_DQSSRC_Pos (5U)
#define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */
#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
#define OCTOSPIM_PCR_NCSEN_Pos (8U)
#define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100 */
#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */
#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */
#define OCTOSPIM_PCR_NCSSRC_Pos (9U)
#define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200 */
#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
#define OCTOSPIM_PCR_IOLEN_Pos (16U)
#define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000 */
#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
#define OCTOSPIM_PCR_IOLSRC_Pos (17U)
#define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000 */
#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
#define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */
#define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */
#define OCTOSPIM_PCR_IOHEN_Pos (24U)
#define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000 */
#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
#define OCTOSPIM_PCR_IOHSRC_Pos (25U)
#define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000 */
#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
#define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000 */
#define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000 */
/******************************************************************************/
@ -20232,6 +20217,8 @@ typedef struct
/* DBG */
/* */
/******************************************************************************/
/********************************* DEVICE ID ********************************/
#define STM32H7_DEV_ID 0x480UL
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

10
stm32cube/stm32h7xx/soc/stm32h7xx.h
View File

@ -60,7 +60,7 @@
#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
!defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx) && \
!defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ)
!defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ)
/* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
/* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
@ -94,10 +94,10 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.7.0
* @brief CMSIS Device version number V1.8.0
*/
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
@ -167,8 +167,8 @@ typedef enum
typedef enum
{
ERROR = 0,
SUCCESS = !ERROR
SUCCESS = 0,
ERROR = !SUCCESS
} ErrorStatus;
/**

61
stm32cube/stm32h7xx/soc/system_stm32h7xx.c
View File

@ -10,7 +10,7 @@
* before branch to main program. This call is made inside
* the "startup_stm32h7xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* - SystemCoreClock variable: Contains the core clock, it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
@ -204,13 +204,25 @@ void SystemInit (void)
/* Disable all interrupts */
RCC->CIER = 0x00000000;
#if (STM32H7_DEV_ID == 0x450UL)
/* dual core CM7 or single core line */
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
{
/* if stm32h7 revY*/
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t*)0x51008108) = 0x000000001U;
}
#endif
#if defined (DATA_IN_D2_SRAM)
/* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock ((AHB SRAM clock) */
#if defined(RCC_AHB2ENR_D2SRAM1EN)
/* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
#if defined(RCC_AHB2ENR_D2SRAM3EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
#elif defined(RCC_AHB2ENR_D2SRAM2EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
#else
RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
#endif /* RCC_AHB2ENR_D2SRAM1EN */
#endif /* RCC_AHB2ENR_D2SRAM3EN */
tmpreg = RCC->AHB2ENR;
(void) tmpreg;
@ -225,17 +237,10 @@ void SystemInit (void)
#endif /* VECT_TAB_SRAM */
#else
/* dual core CM7 or single core line */
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
{
/* if stm32h7 revY*/
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t*)0x51008108) = 0x000000001U;
}
/* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM */
SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
#else
SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
@ -284,22 +289,24 @@ void SystemInit (void)
void SystemCoreClockUpdate (void)
{
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
uint32_t common_system_clock;
float_t fracn1, pllvco;
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
break;
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
SystemCoreClock = CSI_VALUE;
common_system_clock = CSI_VALUE;
break;
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
common_system_clock = HSE_VALUE;
break;
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
@ -336,16 +343,16 @@ void SystemCoreClockUpdate (void)
break;
}
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
}
else
{
SystemCoreClock = 0U;
common_system_clock = 0U;
}
break;
default:
SystemCoreClock = CSI_VALUE;
common_system_clock = CSI_VALUE;
break;
}
@ -353,22 +360,28 @@ void SystemCoreClockUpdate (void)
#if defined (RCC_D1CFGR_D1CPRE)
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
/* SystemCoreClock frequency : CM7 CPU frequency */
SystemCoreClock >>= tmp;
/* common_system_clock frequency : CM7 CPU frequency */
common_system_clock >>= tmp;
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
/* SystemCoreClock frequency : CM7 CPU frequency */
SystemCoreClock >>= tmp;
/* common_system_clock frequency : CM7 CPU frequency */
common_system_clock >>= tmp;
/* SystemD2Clock frequency : AXI and AHBs Clock frequency */
SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
#endif /* DUAL_CORE && CORE_CM4 */
}

373
stm32cube/stm32h7xx/soc/system_stm32h7xx_dualcore_boot_cm4_cm7.c Normal file
View File

@ -0,0 +1,373 @@
/**
******************************************************************************
* @file system_stm32h7xx_dualcore_boot_cm4_cm7.c
* @author MCD Application Team
* @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
* This provides system initialization template function is case of
* an application using a dual core STM32H7 device where
* Cortex-M7 and Cortex-M4 boot are enabled at the FLASH option bytes
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32h7xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock, it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32h7xx_system
* @{
*/
/** @addtogroup STM32H7xx_System_Private_Includes
* @{
*/
#include "stm32h7xx.h"
#include <math.h>
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (CSI_VALUE)
#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* CSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 64000000;
uint32_t SystemD2Clock = 64000000;
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting and vector table location
* configuration.
* @param None
* @retval None
*/
void SystemInit (void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
#endif
/*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt signal is
detectable by the CPU after a WFI/WFE instruction.*/
SCB->SCR |= SCB_SCR_SEVONPEND_Pos;
#ifdef CORE_CM7
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= RCC_CR_HSION;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
RCC->CR &= 0xEAF6ED7FU;
/* Reset D1CFGR register */
RCC->D1CFGR = 0x00000000;
/* Reset D2CFGR register */
RCC->D2CFGR = 0x00000000;
/* Reset D3CFGR register */
RCC->D3CFGR = 0x00000000;
/* Reset PLLCKSELR register */
RCC->PLLCKSELR = 0x00000000;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x00000000;
/* Reset PLL1DIVR register */
RCC->PLL1DIVR = 0x00000000;
/* Reset PLL1FRACR register */
RCC->PLL1FRACR = 0x00000000;
/* Reset PLL2DIVR register */
RCC->PLL2DIVR = 0x00000000;
/* Reset PLL2FRACR register */
RCC->PLL2FRACR = 0x00000000;
/* Reset PLL3DIVR register */
RCC->PLL3DIVR = 0x00000000;
/* Reset PLL3FRACR register */
RCC->PLL3FRACR = 0x00000000;
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
/* Disable all interrupts */
RCC->CIER = 0x00000000;
/* Enable CortexM7 HSEM EXTI line (line 78)*/
EXTI_D2->EMR3 |= 0x4000UL;
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
{
/* if stm32h7 revY*/
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t*)0x51008108) = 0x000000001U;
}
#endif /* CORE_CM7*/
#ifdef CORE_CM4
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
#else
#ifdef CORE_CM7
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM */
#else
SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
#else
#error Please #define CORE_CM4 or CORE_CM7
#endif
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock , it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
* - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
*
* (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 4 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
* (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 64 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
uint32_t common_system_clock;
float_t fracn1, pllvco;
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
break;
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
common_system_clock = CSI_VALUE;
break;
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
common_system_clock = HSE_VALUE;
break;
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
if (pllm != 0U)
{
switch (pllsource)
{
case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
default:
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
}
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
}
else
{
common_system_clock = 0U;
}
break;
default:
common_system_clock = CSI_VALUE;
break;
}
/* Compute SystemClock frequency --------------------------------------------------*/
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
/* common_system_clock frequency : CM7 CPU frequency */
common_system_clock >>= tmp;
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
#endif /* DUAL_CORE && CORE_CM4 */
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file system_stm32h7xx_dualcore_bootcm4_cm7gated.c
* @author MCD Application Team
* @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
* This file provides system initialization template function is case of
* an application using a dual core STM32H7 device where :
* Cortex-M4 boot is enabled at the FLASH option bytes
* Cortex-M7 boot is disabled at the FLASH option bytes
* Cortex-M7 boot can be enabled by the the Cortex-M4 (when needed)
* using the appropriate HAL function "HAL_RCCEx_EnableBootCore"
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32h7xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock, it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32h7xx_system
* @{
*/
/** @addtogroup STM32H7xx_System_Private_Includes
* @{
*/
#include "stm32h7xx.h"
#include <math.h>
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (CSI_VALUE)
#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* CSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 64000000;
uint32_t SystemD2Clock = 64000000;
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting and vector table location
* configuration.
* @param None
* @retval None
*/
void SystemInit (void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
#endif
#ifdef CORE_CM4
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= RCC_CR_HSION;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
RCC->CR &= 0xEAF6ED7FU;
/* Reset D1CFGR register */
RCC->D1CFGR = 0x00000000;
/* Reset D2CFGR register */
RCC->D2CFGR = 0x00000000;
/* Reset D3CFGR register */
RCC->D3CFGR = 0x00000000;
/* Reset PLLCKSELR register */
RCC->PLLCKSELR = 0x00000000;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x00000000;
/* Reset PLL1DIVR register */
RCC->PLL1DIVR = 0x00000000;
/* Reset PLL1FRACR register */
RCC->PLL1FRACR = 0x00000000;
/* Reset PLL2DIVR register */
RCC->PLL2DIVR = 0x00000000;
/* Reset PLL2FRACR register */
RCC->PLL2FRACR = 0x00000000;
/* Reset PLL3DIVR register */
RCC->PLL3DIVR = 0x00000000;
/* Reset PLL3FRACR register */
RCC->PLL3FRACR = 0x00000000;
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
/* Disable all interrupts */
RCC->CIER = 0x00000000;
#endif /* CORE_CM4*/
#ifdef CORE_CM4
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
#else
#ifdef CORE_CM7
/* dual core CM7 or single core line */
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
{
/* if stm32h7 revY*/
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t*)0x51008108) = 0x000000001U;
}
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
#else
#error Please #define CORE_CM4 or CORE_CM7
#endif
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock , it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
* - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
*
* (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 4 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
* (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 64 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
uint32_t common_system_clock;
float_t fracn1, pllvco;
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
break;
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
common_system_clock = CSI_VALUE;
break;
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
common_system_clock = HSE_VALUE;
break;
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
if (pllm != 0U)
{
switch (pllsource)
{
case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
default:
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
}
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
}
else
{
common_system_clock = 0U;
}
break;
default:
common_system_clock = CSI_VALUE;
break;
}
/* Compute SystemClock frequency --------------------------------------------------*/
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
/* common_system_clock frequency : CM7 CPU frequency */
common_system_clock >>= tmp;
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
#endif /* DUAL_CORE && CORE_CM4 */
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file system_stm32h7xx_dualcore_bootcm7_cm4gated.c
* @author MCD Application Team
* @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
* This file provides system initialization template functions is case of
* an application using a dual core STM32H7 device where :
* Cortex-M7 boot is enabled at FLASH option bytes
* Cortex-M4 boot is disabled at FLASH option bytes
* Cortex-M4 boot can be enabled by the the Cortex-M7 (when needed)
* using the appropriate HAL function "HAL_RCCEx_EnableBootCore"
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32h7xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock, it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32h7xx_system
* @{
*/
/** @addtogroup STM32H7xx_System_Private_Includes
* @{
*/
#include "stm32h7xx.h"
#include <math.h>
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (CSI_VALUE)
#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* CSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 64000000;
uint32_t SystemD2Clock = 64000000;
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting and vector table location
* configuration.
* @param None
* @retval None
*/
void SystemInit (void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
#endif
#ifdef CORE_CM7
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= RCC_CR_HSION;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
RCC->CR &= 0xEAF6ED7FU;
/* Reset D1CFGR register */
RCC->D1CFGR = 0x00000000;
/* Reset D2CFGR register */
RCC->D2CFGR = 0x00000000;
/* Reset D3CFGR register */
RCC->D3CFGR = 0x00000000;
/* Reset PLLCKSELR register */
RCC->PLLCKSELR = 0x00000000;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x00000000;
/* Reset PLL1DIVR register */
RCC->PLL1DIVR = 0x00000000;
/* Reset PLL1FRACR register */
RCC->PLL1FRACR = 0x00000000;
/* Reset PLL2DIVR register */
RCC->PLL2DIVR = 0x00000000;
/* Reset PLL2FRACR register */
RCC->PLL2FRACR = 0x00000000;
/* Reset PLL3DIVR register */
RCC->PLL3DIVR = 0x00000000;
/* Reset PLL3FRACR register */
RCC->PLL3FRACR = 0x00000000;
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
/* Disable all interrupts */
RCC->CIER = 0x00000000;
/* dual core CM7 or single core line */
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
{
/* if stm32h7 revY*/
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t*)0x51008108) = 0x000000001U;
}
#endif /* CORE_CM7*/
#ifdef CORE_CM4
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
#else
#ifdef CORE_CM7
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
#else
#error Please #define CORE_CM4 or CORE_CM7
#endif
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock , it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
* - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
*
* (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 4 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
* (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 64 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
uint32_t common_system_clock;
float_t fracn1, pllvco;
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
break;
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
common_system_clock = CSI_VALUE;
break;
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
common_system_clock = HSE_VALUE;
break;
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
if (pllm != 0U)
{
switch (pllsource)
{
case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
default:
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
}
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
}
else
{
common_system_clock = 0U;
}
break;
default:
common_system_clock = CSI_VALUE;
break;
}
/* Compute SystemClock frequency --------------------------------------------------*/
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
/* common_system_clock frequency : CM7 CPU frequency */
common_system_clock >>= tmp;
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
#endif /* DUAL_CORE && CORE_CM4 */
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@ -0,0 +1,378 @@
/**
******************************************************************************
* @file system_stm32h7xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
* This provides system initialization template function is case of
* an application using a single core STM32H7 device
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32h7xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32h7xx_system
* @{
*/
/** @addtogroup STM32H7xx_System_Private_Includes
* @{
*/
#include "stm32h7xx.h"
#include <math.h>
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (CSI_VALUE)
#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* CSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
/* #define DATA_IN_D2_SRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 64000000;
uint32_t SystemD2Clock = 64000000;
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting and vector table location
* configuration.
* @param None
* @retval None
*/
void SystemInit (void)
{
#if defined (DATA_IN_D2_SRAM)
__IO uint32_t tmpreg;
#endif /* DATA_IN_D2_SRAM */
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= RCC_CR_HSION;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
RCC->CR &= 0xEAF6ED7FU;
#if defined(D3_SRAM_BASE)
/* Reset D1CFGR register */
RCC->D1CFGR = 0x00000000;
/* Reset D2CFGR register */
RCC->D2CFGR = 0x00000000;
/* Reset D3CFGR register */
RCC->D3CFGR = 0x00000000;
#else
/* Reset CDCFGR1 register */
RCC->CDCFGR1 = 0x00000000;
/* Reset CDCFGR2 register */
RCC->CDCFGR2 = 0x00000000;
/* Reset SRDCFGR register */
RCC->SRDCFGR = 0x00000000;
#endif
/* Reset PLLCKSELR register */
RCC->PLLCKSELR = 0x00000000;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x00000000;
/* Reset PLL1DIVR register */
RCC->PLL1DIVR = 0x00000000;
/* Reset PLL1FRACR register */
RCC->PLL1FRACR = 0x00000000;
/* Reset PLL2DIVR register */
RCC->PLL2DIVR = 0x00000000;
/* Reset PLL2FRACR register */
RCC->PLL2FRACR = 0x00000000;
/* Reset PLL3DIVR register */
RCC->PLL3DIVR = 0x00000000;
/* Reset PLL3FRACR register */
RCC->PLL3FRACR = 0x00000000;
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
/* Disable all interrupts */
RCC->CIER = 0x00000000;
#if (STM32H7_DEV_ID == 0x450UL)
/* single core line */
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
{
/* if stm32h7 revY*/
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t*)0x51008108) = 0x000000001U;
}
#endif
#if defined (DATA_IN_D2_SRAM)
/* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
#if defined(RCC_AHB2ENR_D2SRAM3EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
#elif defined(RCC_AHB2ENR_D2SRAM2EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
#else
RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
#endif /* RCC_AHB2ENR_D2SRAM3EN */
tmpreg = RCC->AHB2ENR;
(void) tmpreg;
#endif /* DATA_IN_D2_SRAM */
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
#else
SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock , it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
* - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
*
* (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 4 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
* (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 64 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
float_t fracn1, pllvco;
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
break;
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
SystemCoreClock = CSI_VALUE;
break;
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
if (pllm != 0U)
{
switch (pllsource)
{
case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
default:
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
}
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
}
else
{
SystemCoreClock = 0U;
}
break;
default:
SystemCoreClock = CSI_VALUE;
break;
}
/* Compute SystemClock frequency --------------------------------------------------*/
#if defined (RCC_D1CFGR_D1CPRE)
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
/* SystemCoreClock frequency : CM7 CPU frequency */
SystemCoreClock >>= tmp;
/* SystemD2Clock frequency : AXI and AHBs Clock frequency */
SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
SystemCoreClock >>= tmp;
/* SystemD2Clock frequency : AXI and AHBs Clock frequency */
SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/