stm32cube: update stm32f4 to version V1.26.0
Update Cube version for STM32F4xx series on https://github.com/STMicroelectronics from version v1.25.2 to version v1.26.0 Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
parent
2219f386e8
commit
b2a3a44357
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@ -32,6 +32,7 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_FLASH_RAMFUNC drivers/src/stm3
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_FMPI2C drivers/src/stm32f4xx_hal_fmpi2c.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_FMPI2C_EX drivers/src/stm32f4xx_hal_fmpi2c_ex.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_FMPSMBUS drivers/src/stm32f4xx_hal_fmpsmbus.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_FMPSMBUS_EX drivers/src/stm32f4xx_hal_fmpsmbus_ex.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_GPIO drivers/src/stm32f4xx_hal_gpio.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_HASH drivers/src/stm32f4xx_hal_hash.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_HASH_EX drivers/src/stm32f4xx_hal_hash_ex.c)
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@ -6,7 +6,7 @@ Origin:
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http://www.st.com/en/embedded-software/stm32cubef4.html
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Status:
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version v1.25.2
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version v1.26.0
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Purpose:
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ST Microelectronics official MCU package for STM32F4 series.
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@ -23,7 +23,7 @@ URL:
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https://github.com/STMicroelectronics/STM32CubeF4
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Commit:
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2d5b78e2da98fb44e028d87f4ff815427991affc
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d599a824dfe257bee2aeff403caf592da816b126
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Maintained-by:
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External
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@ -35,6 +35,7 @@ License Link:
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https://opensource.org/licenses/BSD-3-Clause
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Patch List:
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--> please check that the following list is still valid:
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*Changes from official delivery:
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-dos2unix applied
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@ -23,7 +23,7 @@
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#define STM32_HAL_LEGACY
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#ifdef __cplusplus
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extern "C" {
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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@ -38,7 +38,6 @@
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#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
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#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
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#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
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/**
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* @}
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*/
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@ -241,7 +240,7 @@
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#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
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#endif
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#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4)
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#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
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#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
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#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
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#endif
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@ -313,8 +312,13 @@
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#endif /* STM32L4 */
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#if defined(STM32G0)
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#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
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#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
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#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
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#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
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#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
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#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
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#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
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#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
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#endif
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#if defined(STM32H7)
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@ -591,24 +595,24 @@
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#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
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#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
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#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
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#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
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#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
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#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
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#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
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#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
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#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
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#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
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#if defined(STM32L1)
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#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
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#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
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#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
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#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
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#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
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#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
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#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
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#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
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#endif /* STM32L1 */
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#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
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#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
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#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
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#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
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#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
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#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
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#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
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#endif /* STM32F0 || STM32F3 || STM32F1 */
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#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
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@ -643,6 +647,10 @@
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#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
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#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
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#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
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#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
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#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
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#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
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#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
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#endif /* STM32G4 */
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#if defined(STM32H7)
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@ -765,49 +773,6 @@
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#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
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#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
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/** @brief Constants defining the events that can be selected to configure the
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* set/reset crossbar of a timer output
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*/
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#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
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#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
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#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
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#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
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#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
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#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
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#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
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#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
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#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
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#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
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#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
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#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
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#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
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#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
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#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
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#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
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#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
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#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
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/** @brief Constants defining the event filtering applied to external events
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* by a timer
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*/
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#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
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#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
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#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
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#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
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#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
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/** @brief Constants defining the DLL calibration periods (in micro seconds)
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*/
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#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
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#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
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#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
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#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7)
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#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
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#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
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#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
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#endif
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#if defined(STM32L4) || defined(STM32L5)
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#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
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#elif defined(STM32G4)
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#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
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#endif
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/**
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* @}
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#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
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#if defined(STM32H7)
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#define I2S_IT_TXE I2S_IT_TXP
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#define I2S_IT_RXNE I2S_IT_RXP
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#define I2S_IT_TXE I2S_IT_TXP
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#define I2S_IT_RXNE I2S_IT_RXP
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#define I2S_FLAG_TXE I2S_FLAG_TXP
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#define I2S_FLAG_RXNE I2S_FLAG_RXP
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#define I2S_FLAG_TXE I2S_FLAG_TXP
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#define I2S_FLAG_RXNE I2S_FLAG_RXP
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#endif
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#if defined(STM32F7)
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#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
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#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
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#endif
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/**
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* @}
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#if defined(STM32H7)
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#define SPI_FLAG_TXE SPI_FLAG_TXP
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#define SPI_FLAG_RXNE SPI_FLAG_RXP
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#define SPI_FLAG_TXE SPI_FLAG_TXP
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#define SPI_FLAG_RXNE SPI_FLAG_RXP
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#define SPI_IT_TXE SPI_IT_TXP
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#define SPI_IT_RXNE SPI_IT_RXP
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#define SPI_IT_TXE SPI_IT_TXP
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#define SPI_IT_RXNE SPI_IT_RXP
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#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
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#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
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#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
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#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
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#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
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#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
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#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
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#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
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#endif /* STM32H7 */
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#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
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#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
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#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
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#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
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#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
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#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
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#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
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#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
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#endif /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */
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#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
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/**
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* @}
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*/
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#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
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#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
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#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
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#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
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#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
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)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
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#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
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#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
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#if defined(STM32L0)
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#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
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#endif
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#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
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#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
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#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
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)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
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#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
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#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
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#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
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#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
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#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
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/**
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/**
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* @}
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*/
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*/
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/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
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* @{
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#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
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#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
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#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
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#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
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)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
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|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
|
||||
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
|
||||
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
|
||||
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
|
||||
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
|
||||
#if defined(STM32F4)
|
||||
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
|
||||
|
@ -1554,19 +1527,19 @@
|
|||
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
|
||||
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
|
||||
#endif /* STM32F4 */
|
||||
/**
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32G0)
|
||||
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
|
||||
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
|
||||
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
|
||||
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
|
||||
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
|
||||
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
|
||||
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
|
||||
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
|
||||
#endif
|
||||
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
|
||||
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
|
||||
|
@ -1611,9 +1584,9 @@
|
|||
|
||||
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
|
||||
|
||||
/**
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
|
@ -1862,15 +1835,15 @@
|
|||
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
|
||||
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
|
||||
#else
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
|
||||
#endif /* STM32H7 */
|
||||
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
|
||||
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
|
||||
|
@ -2081,8 +2054,8 @@
|
|||
*/
|
||||
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
|
||||
((WAVE) == DAC_WAVE_NOISE)|| \
|
||||
((WAVE) == DAC_WAVE_TRIANGLE))
|
||||
((WAVE) == DAC_WAVE_NOISE)|| \
|
||||
((WAVE) == DAC_WAVE_TRIANGLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -2138,7 +2111,7 @@
|
|||
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
|
||||
#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -2275,7 +2248,8 @@
|
|||
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
|
||||
|
||||
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
|
||||
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
|
||||
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
|
||||
)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
|
||||
|
||||
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
|
||||
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
|
||||
|
@ -3243,9 +3217,8 @@
|
|||
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
|
||||
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
|
||||
|
||||
#if defined(STM32L4)
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
|
||||
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
|
||||
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
|
||||
#else
|
||||
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
|
||||
#endif
|
||||
|
@ -3373,7 +3346,7 @@
|
|||
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
|
||||
#else
|
||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||
#endif
|
||||
|
@ -3393,19 +3366,19 @@
|
|||
#else
|
||||
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
|
||||
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
|
||||
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
|
||||
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
|
||||
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
|
||||
#endif /* STM32F1 */
|
||||
|
||||
#define IS_ALARM IS_RTC_ALARM
|
||||
|
@ -3481,9 +3454,9 @@
|
|||
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
|
||||
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
|
||||
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
|
||||
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
|
||||
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
|
||||
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
|
||||
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
|
||||
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
|
||||
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
|
||||
/* alias CMSIS for compatibilities */
|
||||
#define SDIO_IRQn SDMMC1_IRQn
|
||||
#define SDIO_IRQHandler SDMMC1_IRQHandler
|
||||
|
@ -3589,6 +3562,13 @@
|
|||
#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
|
||||
#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
|
||||
|
||||
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
|
||||
#define USART_OVERSAMPLING_16 0x00000000U
|
||||
#define USART_OVERSAMPLING_8 USART_CR1_OVER8
|
||||
|
||||
#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
|
||||
((__SAMPLING__) == USART_OVERSAMPLING_8))
|
||||
#endif /* STM32F0 || STM32F3 || STM32F7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -3751,7 +3731,7 @@
|
|||
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7)
|
||||
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
|
||||
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
|
||||
#endif /* STM32L4 || STM32F4 || STM32F7 */
|
||||
/**
|
||||
|
|
|
@ -28,6 +28,9 @@
|
|||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
/* Include low level driver */
|
||||
#include "stm32f4xx_ll_adc.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
|
|
@ -304,17 +304,18 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
|
|||
*/
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
|
||||
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
|
||||
defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
|
||||
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||
defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
|
||||
defined(STM32F412Cx)
|
||||
#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||
|
||||
STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE ||
|
||||
STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
|
||||
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
|
||||
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
||||
#if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || \
|
||||
defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || \
|
||||
defined(STM32F469xx) || defined(STM32F479xx)
|
||||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \
|
||||
((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
|
||||
#endif /* STM32F411xE || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
|
||||
|
||||
#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
|
||||
((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
|
||||
|
|
|
@ -255,7 +255,7 @@ typedef enum
|
|||
HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */
|
||||
HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */
|
||||
HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */
|
||||
HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up fropm Rx msg callback ID */
|
||||
HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up from Rx msg callback ID */
|
||||
HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */
|
||||
|
||||
HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */
|
||||
|
@ -295,11 +295,11 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to
|
|||
#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
|
||||
#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
|
||||
#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
|
||||
#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
|
||||
#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
|
||||
#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
|
||||
#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
|
||||
#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
|
||||
|
|
|
@ -121,7 +121,7 @@ typedef struct
|
|||
* b6 Error information
|
||||
* 0 : No Error
|
||||
* 1 : Error
|
||||
* b5 IP initilisation status
|
||||
* b5 IP initialization status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP initialized. HAL CEC Init function already called)
|
||||
* b4-b3 (not used)
|
||||
|
@ -138,7 +138,7 @@ typedef struct
|
|||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 IP initilisation status
|
||||
* b5 IP initialization status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP initialized)
|
||||
* b4-b2 (not used)
|
||||
|
|
|
@ -79,6 +79,7 @@
|
|||
#define HAL_PCD_MODULE_ENABLED
|
||||
#define HAL_HCD_MODULE_ENABLED
|
||||
#define HAL_FMPI2C_MODULE_ENABLED
|
||||
#define HAL_FMPSMBUS_MODULE_ENABLED
|
||||
#define HAL_SPDIFRX_MODULE_ENABLED
|
||||
#define HAL_DFSDM_MODULE_ENABLED
|
||||
#define HAL_LPTIM_MODULE_ENABLED
|
||||
|
@ -163,6 +164,7 @@
|
|||
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
|
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
|
||||
#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */
|
||||
#define USE_HAL_FMPSMBUS_REGISTER_CALLBACKS 0U /* FMPSMBUS register callback disabled */
|
||||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
|
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
|
||||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
|
||||
|
@ -451,6 +453,10 @@
|
|||
#include "stm32f4xx_hal_fmpi2c.h"
|
||||
#endif /* HAL_FMPI2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FMPSMBUS_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_fmpsmbus.h"
|
||||
#endif /* HAL_FMPSMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPDIFRX_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_spdifrx.h"
|
||||
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
|
||||
|
|
|
@ -65,6 +65,7 @@ typedef struct
|
|||
uint32_t HeaderSize; /*!< The size of header buffer in word */
|
||||
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
|
||||
uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
|
||||
uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
|
||||
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
|
||||
Vector only once and to skip configuration for consecutive processings.
|
||||
This parameter can be a value of @ref CRYP_Configuration_Skip */
|
||||
|
@ -210,6 +211,17 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
|
|||
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
|
||||
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */
|
||||
#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -6,7 +6,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
|
@ -18,36 +18,34 @@
|
|||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_HAL_DAC_H
|
||||
#define __STM32F4xx_HAL_DAC_H
|
||||
#ifndef STM32F4xx_HAL_DAC_H
|
||||
#define STM32F4xx_HAL_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
|
||||
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
|
||||
defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
|
||||
defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
#if defined(DAC)
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Types DAC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
|
@ -56,16 +54,17 @@ typedef enum
|
|||
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
|
||||
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
|
||||
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
|
||||
}HAL_DAC_StateTypeDef;
|
||||
|
||||
} HAL_DAC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC handle Structure definition
|
||||
* @brief DAC handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __DAC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
{
|
||||
DAC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
|
@ -80,32 +79,35 @@ typedef struct
|
|||
__IO uint32_t ErrorCode; /*!< DAC Error code */
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
|
||||
void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
|
||||
void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
|
||||
void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
|
||||
void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
}DAC_HandleTypeDef;
|
||||
} DAC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC Configuration regular Channel structure definition
|
||||
* @brief DAC Configuration regular Channel structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
}DAC_ChannelConfTypeDef;
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
|
||||
} DAC_ChannelConfTypeDef;
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
|
@ -117,25 +119,29 @@ typedef enum
|
|||
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
|
||||
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
|
||||
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
|
||||
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
|
||||
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
|
||||
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
|
||||
HAL_DAC_MSP_INIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
|
||||
HAL_DAC_MSP_DEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
|
||||
HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
|
||||
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
|
||||
}HAL_DAC_CallbackIDTypeDef;
|
||||
} HAL_DAC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DAC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Constants DAC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
@ -144,77 +150,89 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
|||
* @{
|
||||
*/
|
||||
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
|
||||
#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_trigger_selection DAC Trigger Selection
|
||||
/** @defgroup DAC_trigger_selection DAC trigger selection
|
||||
* @{
|
||||
*/
|
||||
#define DAC_TRIGGER_NONE 0x00000000UL /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE (DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
|
||||
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer DAC Output Buffer
|
||||
/** @defgroup DAC_output_buffer DAC output buffer
|
||||
* @{
|
||||
*/
|
||||
#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
|
||||
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
|
||||
#define DAC_OUTPUTBUFFER_DISABLE (DAC_CR_BOFF1)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection DAC Channel Selection
|
||||
/** @defgroup DAC_Channel_selection DAC Channel selection
|
||||
* @{
|
||||
*/
|
||||
#define DAC_CHANNEL_1 0x00000000U
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#define DAC_CHANNEL_2 0x00000010U
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignment DAC Data Alignment
|
||||
/** @defgroup DAC_data_alignment DAC data alignment
|
||||
* @{
|
||||
*/
|
||||
#define DAC_ALIGN_12B_R 0x00000000U
|
||||
#define DAC_ALIGN_12B_L 0x00000004U
|
||||
#define DAC_ALIGN_8B_R 0x00000008U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition DAC Flags Definition
|
||||
/** @defgroup DAC_flags_definition DAC flags definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
|
||||
#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
|
||||
#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_IT_definition DAC IT Definition
|
||||
/** @defgroup DAC_IT_definition DAC IT definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
|
||||
#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
|
||||
#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -224,89 +242,146 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
|||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Macros DAC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DAC handle state
|
||||
/** @brief Reset DAC handle state.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_DAC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_DAC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the DAC channel
|
||||
/** @brief Enable the DAC channel.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __DAC_Channel__ specifies the DAC channel
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
|
||||
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
|
||||
|
||||
/** @brief Disable the DAC channel
|
||||
/** @brief Disable the DAC channel.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __DAC_Channel__ specifies the DAC channel.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
|
||||
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
|
||||
|
||||
/** @brief Enable the DAC interrupt
|
||||
/** @brief Set DHR12R1 alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
/** @brief Set DHR12R2 alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
/** @brief Set DHR12RD alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
|
||||
|
||||
/** @brief Enable the DAC interrupt.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __INTERRUPT__ specifies the DAC interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the DAC interrupt
|
||||
/** @brief Disable the DAC interrupt.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __INTERRUPT__ specifies the DAC interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Checks if the specified DAC interrupt source is enabled or disabled.
|
||||
/** @brief Check whether the specified DAC interrupt source is enabled or not.
|
||||
* @param __HANDLE__ DAC handle
|
||||
* @param __INTERRUPT__ DAC interrupt source to check
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
|
||||
* @retval State of interruption (SET or RESET)
|
||||
*/
|
||||
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/** @brief Get the selected DAC's flag status.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
|
||||
* @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
|
||||
* @param __FLAG__ specifies the DAC flag to get.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
|
||||
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the DAC's flag.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
|
||||
* @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
|
||||
* @param __FLAG__ specifies the DAC flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
|
||||
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include DAC HAL Extension module */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Private_Macros DAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
|
||||
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2))
|
||||
#else
|
||||
#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
|
||||
((ALIGN) == DAC_ALIGN_12B_L) || \
|
||||
((ALIGN) == DAC_ALIGN_8B_R))
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include DAC HAL Extended module */
|
||||
#include "stm32f4xx_hal_dac_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
@ -314,11 +389,12 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
|||
/** @addtogroup DAC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions *********************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -326,12 +402,27 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
|
|||
/** @addtogroup DAC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
|
||||
uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
|
||||
|
||||
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/* DAC callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
|
||||
pDAC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -340,8 +431,8 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
|||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -349,21 +440,10 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui
|
|||
/** @addtogroup DAC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
|
||||
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
|
||||
|
||||
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/* DAC callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -371,78 +451,23 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_D
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup DAC_Private_Constants DAC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DAC_Private_Macros DAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
|
||||
((ALIGN) == DAC_ALIGN_12B_L) || \
|
||||
((ALIGN) == DAC_ALIGN_8B_R))
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2))
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
|
||||
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
/** @brief Set DHR12R1 alignment
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__))
|
||||
|
||||
/** @brief Set DHR12R2 alignment
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))
|
||||
|
||||
/** @brief Set DHR12RD alignment
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DAC_Private_Functions DAC Private Functions
|
||||
* @{
|
||||
*/
|
||||
void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
|
||||
STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
|
||||
STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx ||\
|
||||
STM32F413xx || STM32F423xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DAC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -451,6 +476,7 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_D
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_HAL_DAC_H */
|
||||
|
||||
#endif /* STM32F4xx_HAL_DAC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
@ -1,12 +1,12 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_dac.h
|
||||
* @file stm32f4xx_hal_dac_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DAC HAL Extension module.
|
||||
* @brief Header file of DAC HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
|
@ -18,62 +18,66 @@
|
|||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_HAL_DAC_EX_H
|
||||
#define __STM32F4xx_HAL_DAC_EX_H
|
||||
#ifndef STM32F4xx_HAL_DAC_EX_H
|
||||
#define STM32F4xx_HAL_DAC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
|
||||
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
|
||||
defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
|
||||
defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
#if defined(DAC)
|
||||
|
||||
/** @addtogroup DACEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Exported_Constants DAC Exported Constants
|
||||
|
||||
/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
|
||||
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
|
||||
* @{
|
||||
*/
|
||||
#define DAC_LFSRUNMASK_BIT0 0x00000000U /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1 0x00000000U /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
|
||||
#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -83,46 +87,23 @@
|
|||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DACEx_Exported_Functions
|
||||
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DACEx_Private_Macros DACEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Extension features functions ***********************************************/
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
|
||||
|
||||
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Private_Constants DAC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Private_Macros DAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
|
||||
|
@ -151,25 +132,68 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Private_Functions DAC Private Functions
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Extended features functions ***********************************************/
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
|
||||
STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
|
||||
STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx ||\
|
||||
STM32F413xx || STM32F423xx */
|
||||
/* IO operation functions *****************************************************/
|
||||
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#endif
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#endif
|
||||
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
|
||||
/* are called by HAL_DAC_Start_DMA */
|
||||
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DAC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -178,6 +202,6 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_HAL_DAC_EX_H */
|
||||
#endif /* STM32F4xx_HAL_DAC_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
@ -107,7 +107,14 @@ typedef enum
|
|||
}while (0U)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((packed))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
|
@ -118,7 +125,14 @@ typedef enum
|
|||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
|
@ -130,7 +144,7 @@ typedef enum
|
|||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler */
|
||||
#if defined (__CC_ARM) /* ARM Compiler V5*/
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
|
@ -142,9 +156,9 @@ typedef enum
|
|||
/**
|
||||
* @brief __RAM_FUNC definition
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
/* ARM Compiler
|
||||
------------
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
/* ARM Compiler V4/V5 and V6
|
||||
--------------------------
|
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
|
@ -174,9 +188,9 @@ typedef enum
|
|||
/**
|
||||
* @brief __NOINLINE definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
|
||||
/* ARM & GNUCompiler
|
||||
----------------
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
|
||||
/* ARM V4/V5 and V6 & GNU Compiler
|
||||
-------------------------------
|
||||
*/
|
||||
#define __NOINLINE __attribute__ ( (noinline) )
|
||||
|
||||
|
|
|
@ -22,7 +22,7 @@
|
|||
#define STM32F4xx_HAL_DMA2D_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
@ -71,7 +71,8 @@ typedef struct
|
|||
This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
|
||||
|
||||
uint32_t OutputOffset; /*!< Specifies the Offset value.
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x0000 and Max_Data = 0x3FFF. */
|
||||
|
||||
|
||||
|
||||
|
@ -85,7 +86,8 @@ typedef struct
|
|||
typedef struct
|
||||
{
|
||||
uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x0000 and Max_Data = 0x3FFF. */
|
||||
|
||||
uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
|
||||
This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
|
||||
|
@ -93,9 +95,12 @@ typedef struct
|
|||
uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
|
||||
This parameter can be one value of @ref DMA2D_Alpha_Mode. */
|
||||
|
||||
uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
|
||||
@note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
|
||||
uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value
|
||||
in case of A8 or A4 color mode.
|
||||
This parameter must be a number between Min_Data = 0x00
|
||||
and Max_Data = 0xFF except for the color modes detailed below.
|
||||
@note In case of A8 or A4 color mode (ARGB),
|
||||
this parameter must be a number between
|
||||
Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
|
||||
- InputAlpha[24:31] is the alpha value ALPHA[0:7]
|
||||
- InputAlpha[16:23] is the red value RED[0:7]
|
||||
|
@ -116,46 +121,46 @@ typedef enum
|
|||
HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
|
||||
HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */
|
||||
HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */
|
||||
}HAL_DMA2D_StateTypeDef;
|
||||
} HAL_DMA2D_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA2D handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA2D_HandleTypeDef
|
||||
{
|
||||
DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
|
||||
DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
|
||||
|
||||
DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
|
||||
DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
|
||||
|
||||
void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */
|
||||
void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */
|
||||
|
||||
void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */
|
||||
void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */
|
||||
|
||||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
||||
void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */
|
||||
void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */
|
||||
|
||||
void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */
|
||||
void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */
|
||||
|
||||
void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */
|
||||
void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */
|
||||
|
||||
void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */
|
||||
void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */
|
||||
|
||||
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
|
||||
|
||||
DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
|
||||
DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA2D lock. */
|
||||
HAL_LockTypeDef Lock; /*!< DMA2D lock. */
|
||||
|
||||
__IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
|
||||
__IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA2D error code. */
|
||||
__IO uint32_t ErrorCode; /*!< DMA2D error code. */
|
||||
} DMA2D_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL DMA2D Callback pointer definition
|
||||
*/
|
||||
typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */
|
||||
typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */
|
||||
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
|
@ -226,10 +231,10 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Poin
|
|||
/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
|
||||
#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
|
||||
#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */
|
||||
#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value
|
||||
with original alpha channel value */
|
||||
with original alpha channel value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -277,7 +282,8 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Poin
|
|||
/** @defgroup DMA2D_Aliases DMA2D API Aliases
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
|
||||
#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
|
||||
for compatibility with legacy code */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -294,7 +300,7 @@ typedef enum
|
|||
HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */
|
||||
HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */
|
||||
HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */
|
||||
}HAL_DMA2D_CallbackIDTypeDef;
|
||||
} HAL_DMA2D_CallbackIDTypeDef;
|
||||
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
|
@ -311,10 +317,10 @@ typedef enum
|
|||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
}while(0)
|
||||
#else
|
||||
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
|
||||
|
@ -420,12 +426,13 @@ typedef enum
|
|||
|
||||
/* Initialization and de-initialization functions *******************************/
|
||||
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
|
||||
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
|
||||
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d);
|
||||
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d);
|
||||
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d);
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
|
||||
pDMA2D_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
|
||||
|
||||
|
@ -439,16 +446,22 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_
|
|||
*/
|
||||
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
|
||||
uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
|
||||
uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
|
||||
uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
|
||||
uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
|
||||
uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
|
||||
uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||||
|
@ -568,13 +581,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
|
|||
/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER))
|
||||
#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\
|
||||
|| ((LAYER) == DMA2D_FOREGROUND_LAYER))
|
||||
|
||||
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
|
||||
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
|
||||
|
||||
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
|
||||
((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
|
||||
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \
|
||||
((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
|
||||
((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \
|
||||
((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
|
||||
((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
|
||||
|
||||
#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
|
||||
|
@ -582,11 +598,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
|
|||
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
|
||||
#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
|
||||
|
||||
#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
|
||||
#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_RGB888) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_RGB565) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_L8) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_AL44) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_AL88) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_L4) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_A8) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_A4))
|
||||
|
||||
#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
|
||||
|
@ -601,11 +622,11 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
|
|||
#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
|
||||
#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
|
||||
#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
|
||||
((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
|
||||
((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
|
||||
((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
|
||||
((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
|
||||
#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
|
||||
((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
|
||||
((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
|
||||
((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
|
||||
((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -923,7 +923,7 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
|||
|
||||
/**
|
||||
* @brief Reset DSI handle state.
|
||||
* @param __HANDLE__: DSI handle
|
||||
* @param __HANDLE__ DSI handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
|
||||
|
|
|
@ -243,19 +243,19 @@ typedef struct
|
|||
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
|
||||
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
||||
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
||||
(((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
|
||||
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
|
||||
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
||||
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
||||
(((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
|
||||
|
||||
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
|
||||
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
|
||||
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
|
||||
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
|
||||
|
||||
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
|
||||
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
|
||||
|
||||
#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
|
||||
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
|
||||
|
||||
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
|
||||
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
|
||||
|
||||
#if !defined (GPIOD)
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
|
|
|
@ -496,7 +496,8 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint
|
|||
*
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
#define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
|
||||
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified FMPI2C flag is set or not.
|
||||
* @param __HANDLE__ specifies the FMPI2C Handle.
|
||||
|
@ -522,7 +523,8 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint
|
|||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define FMPI2C_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
#define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
|
||||
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the FMPI2C pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the FMPI2C Handle.
|
||||
|
@ -542,7 +544,7 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint
|
|||
* @retval None
|
||||
*/
|
||||
#define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
|
||||
: ((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
||||
: ((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
||||
|
||||
/** @brief Enable the specified FMPI2C peripheral.
|
||||
* @param __HANDLE__ specifies the FMPI2C Handle.
|
||||
|
@ -584,7 +586,8 @@ void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c);
|
|||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID, pFMPI2C_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID,
|
||||
pFMPI2C_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_UnRegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_FMPI2C_RegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, pFMPI2C_AddrCallbackTypeDef pCallback);
|
||||
|
@ -599,49 +602,70 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2
|
|||
*/
|
||||
/* IO operation functions ****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials,
|
||||
uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress);
|
||||
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FMPI2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
/******* FMPI2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c);
|
||||
void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c);
|
||||
|
@ -733,7 +757,8 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
|
|||
#define IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPI2C_OTHER_FRAME) || \
|
||||
((REQUEST) == FMPI2C_OTHER_AND_LAST_FRAME))
|
||||
|
||||
#define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
|
||||
#define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
|
||||
(uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
|
||||
|
||||
#define FMPI2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 16U))
|
||||
#define FMPI2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U))
|
||||
|
@ -744,13 +769,15 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
|
|||
#define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
#define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
||||
|
||||
#define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
|
||||
(uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||
|
||||
#define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
|
||||
|
||||
#define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == ((__FLAG__) & FMPI2C_FLAG_MASK)) ? SET : RESET)
|
||||
#define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == \
|
||||
((__FLAG__) & FMPI2C_FLAG_MASK)) ? SET : RESET)
|
||||
#define FMPI2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
/**
|
||||
* @}
|
||||
|
|
|
@ -39,7 +39,6 @@ extern "C" {
|
|||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FMPI2CEx_Exported_Constants FMPI2C Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
@ -67,22 +66,49 @@ extern "C" {
|
|||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup FMPI2CEx_Exported_Macros FMPI2C Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FMPI2CEx_Exported_Functions FMPI2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FMPI2CEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
/** @addtogroup FMPI2CEx_Exported_Functions_Group1 FMPI2C Extended Filter Mode Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_FMPI2CEx_ConfigAnalogFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t DigitalFilter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FMPI2CEx_Exported_Functions_Group2 FMPI2C Extended WakeUp Mode Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FMPI2CEx_Exported_Functions_Group3 FMPI2C Extended FastModePlus Functions
|
||||
* @{
|
||||
*/
|
||||
void HAL_FMPI2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup FMPI2CEx_Private_Constants FMPI2C Extended Private Constants
|
||||
|
@ -98,15 +124,12 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
|||
* @{
|
||||
*/
|
||||
#define IS_FMPI2C_ANALOG_FILTER(FILTER) (((FILTER) == FMPI2C_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == FMPI2C_ANALOGFILTER_DISABLE))
|
||||
((FILTER) == FMPI2C_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_FMPI2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
|
||||
#define IS_FMPI2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SCL)) == FMPI2C_FASTMODEPLUS_SCL) || \
|
||||
(((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA))
|
||||
|
||||
|
||||
|
||||
(((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -128,14 +151,6 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FMPI2C_CR1_PE */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
@ -28,6 +28,7 @@ extern "C" {
|
|||
#if defined(FMPI2C_CR1_PE)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
#include "stm32f4xx_hal_fmpsmbus_ex.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
|
@ -66,7 +67,7 @@ typedef struct
|
|||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
|
||||
This parameter can be a value of @ref FMPSMBUS_own_address2_masks. */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
|
@ -359,7 +360,8 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus
|
|||
#define FMPSMBUS_IT_ADDRI FMPI2C_CR1_ADDRIE
|
||||
#define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE
|
||||
#define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE
|
||||
#define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)
|
||||
#define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | \
|
||||
FMPSMBUS_IT_TXI)
|
||||
#define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)
|
||||
#define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI)
|
||||
#define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI)
|
||||
|
@ -409,10 +411,10 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus
|
|||
*/
|
||||
#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
(__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET)
|
||||
#endif
|
||||
|
@ -463,7 +465,8 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus
|
|||
*
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_FMPSMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
#define __HAL_FMPSMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified FMPSMBUS flag is set or not.
|
||||
* @param __HANDLE__ specifies the FMPSMBUS Handle.
|
||||
|
@ -489,7 +492,8 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus
|
|||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define FMPSMBUS_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_FMPSMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET)
|
||||
#define __HAL_FMPSMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
(((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the FMPSMBUS pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the FMPSMBUS Handle.
|
||||
|
@ -540,15 +544,15 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus
|
|||
*/
|
||||
|
||||
#define IS_FMPSMBUS_ANALOG_FILTER(FILTER) (((FILTER) == FMPSMBUS_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE))
|
||||
((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_FMPSMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
|
||||
#define IS_FMPSMBUS_ADDRESSING_MODE(MODE) (((MODE) == FMPSMBUS_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT))
|
||||
((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT))
|
||||
|
||||
#define IS_FMPSMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPSMBUS_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE))
|
||||
((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE))
|
||||
|
||||
#define IS_FMPSMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPSMBUS_OA2_NOMASK) || \
|
||||
((MASK) == FMPSMBUS_OA2_MASK01) || \
|
||||
|
@ -566,47 +570,49 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus
|
|||
((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE))
|
||||
|
||||
#define IS_FMPSMBUS_PEC(PEC) (((PEC) == FMPSMBUS_PEC_DISABLE) || \
|
||||
((PEC) == FMPSMBUS_PEC_ENABLE))
|
||||
((PEC) == FMPSMBUS_PEC_ENABLE))
|
||||
|
||||
#define IS_FMPSMBUS_PERIPHERAL_MODE(MODE) (((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST) || \
|
||||
((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \
|
||||
((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP))
|
||||
#define IS_FMPSMBUS_PERIPHERAL_MODE(MODE) (((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST) || \
|
||||
((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \
|
||||
((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP))
|
||||
|
||||
#define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \
|
||||
((MODE) == FMPSMBUS_AUTOEND_MODE) || \
|
||||
((MODE) == FMPSMBUS_SOFTEND_MODE) || \
|
||||
((MODE) == FMPSMBUS_SENDPEC_MODE) || \
|
||||
((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \
|
||||
((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | FMPSMBUS_RELOAD_MODE )))
|
||||
#define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \
|
||||
((MODE) == FMPSMBUS_AUTOEND_MODE) || \
|
||||
((MODE) == FMPSMBUS_SOFTEND_MODE) || \
|
||||
((MODE) == FMPSMBUS_SENDPEC_MODE) || \
|
||||
((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \
|
||||
((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | FMPSMBUS_RELOAD_MODE )))
|
||||
|
||||
|
||||
#define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) || \
|
||||
((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \
|
||||
((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == FMPSMBUS_NO_STARTSTOP))
|
||||
((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \
|
||||
((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == FMPSMBUS_NO_STARTSTOP))
|
||||
|
||||
|
||||
#define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
|
||||
((REQUEST) == FMPSMBUS_FIRST_FRAME) || \
|
||||
((REQUEST) == FMPSMBUS_NEXT_FRAME) || \
|
||||
((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC))
|
||||
#define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
|
||||
((REQUEST) == FMPSMBUS_FIRST_FRAME) || \
|
||||
((REQUEST) == FMPSMBUS_NEXT_FRAME) || \
|
||||
((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC))
|
||||
|
||||
#define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \
|
||||
((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
|
||||
|
||||
#define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | FMPI2C_CR1_PECEN)))
|
||||
#define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
|
||||
#define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
|
||||
(uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | FMPI2C_CR1_PECEN)))
|
||||
#define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
|
||||
(uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
|
||||
|
||||
#define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
|
||||
|
||||
#define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U)
|
||||
#define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U)
|
||||
|
@ -614,7 +620,8 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus
|
|||
#define FMPSMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_PECBYTE)
|
||||
#define FMPSMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & FMPI2C_CR1_ALERTEN)
|
||||
|
||||
#define FMPSMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET)
|
||||
#define FMPSMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \
|
||||
((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET)
|
||||
#define FMPSMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
|
||||
#define IS_FMPSMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
|
@ -630,8 +637,8 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus
|
|||
*/
|
||||
|
||||
/** @addtogroup FMPSMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus);
|
||||
|
@ -643,7 +650,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmps
|
|||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, pFMPSMBUS_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID,
|
||||
pFMPSMBUS_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, pFMPSMBUS_AddrCallbackTypeDef pCallback);
|
||||
|
@ -654,28 +662,33 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf
|
|||
*/
|
||||
|
||||
/** @addtogroup FMPSMBUS_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/** @addtogroup Blocking_mode_Polling Blocking mode Polling
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials,
|
||||
uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress);
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
|
||||
|
@ -686,8 +699,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_DisableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbu
|
|||
*/
|
||||
|
||||
/** @addtogroup FMPSMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
/******* FMPSMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
|
||||
void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus);
|
||||
void HAL_FMPSMBUS_ER_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus);
|
||||
|
@ -704,8 +717,8 @@ void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
|
|||
*/
|
||||
|
||||
/** @addtogroup FMPSMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State and Errors functions **************************************************/
|
||||
uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus);
|
||||
|
|
|
@ -0,0 +1,130 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_fmpsmbus_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FMPSMBUS HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F4xx_HAL_FMPSMBUS_EX_H
|
||||
#define STM32F4xx_HAL_FMPSMBUS_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(FMPI2C_CR1_PE)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FMPSMBUSEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FMPSMBUSEx_Exported_Constants FMPSMBUS Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FMPSMBUSEx_FastModePlus FMPSMBUS Extended Fast Mode Plus
|
||||
* @{
|
||||
*/
|
||||
#define FMPSMBUS_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /*!< Enable Fast Mode Plus on FMPI2C1 SCL pins */
|
||||
#define FMPSMBUS_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /*!< Enable Fast Mode Plus on FMPI2C1 SDA pins */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup FMPSMBUSEx_Exported_Macros FMPSMBUS Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FMPSMBUSEx_Exported_Functions FMPSMBUS Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FMPSMBUSEx_Exported_Functions_Group3 FMPSMBUS Extended FastModePlus Functions
|
||||
* @{
|
||||
*/
|
||||
void HAL_FMPSMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup FMPSMBUSEx_Private_Constants FMPSMBUS Extended Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FMPSMBUSEx_Private_Macro FMPSMBUS Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMPSMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SCL)) == FMPSMBUS_FASTMODEPLUS_SCL) || \
|
||||
(((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SDA)) == FMPSMBUS_FASTMODEPLUS_SDA))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup FMPSMBUSEx_Private_Functions FMPSMBUS Extended Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32f4xx_hal_fmpfmpsmbus_ex.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FMPI2C_CR1_PE */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F4xx_HAL_FMPSMBUS_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
@ -116,21 +116,22 @@ typedef enum
|
|||
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */
|
||||
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP (MODE_PP | MODE_OUTPUT) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD (MODE_OD | MODE_OUTPUT) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP (MODE_PP | MODE_AF) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD (MODE_OD | MODE_AF) /*!< Alternate Function Open Drain Mode */
|
||||
|
||||
#define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */
|
||||
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
|
||||
|
||||
#define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING (EXTI_MODE | GPIO_MODE_IT | RISING_EDGE) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING (EXTI_MODE | GPIO_MODE_IT | FALLING_EDGE) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING (EXTI_MODE | GPIO_MODE_IT | RISING_EDGE | FALLING_EDGE) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define GPIO_MODE_EVT_RISING (EXTI_MODE | GPIO_MODE_EVT | RISING_EDGE) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING (EXTI_MODE | GPIO_MODE_EVT | FALLING_EDGE) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING (EXTI_MODE | GPIO_MODE_EVT | RISING_EDGE | FALLING_EDGE) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -252,6 +253,21 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
|||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE 0x00000003U
|
||||
#define EXTI_MODE 0x10000000U
|
||||
#define GPIO_MODE_IT 0x00010000U
|
||||
#define GPIO_MODE_EVT 0x00020000U
|
||||
#define RISING_EDGE 0x00100000U
|
||||
#define FALLING_EDGE 0x00200000U
|
||||
#define GPIO_OUTPUT_TYPE 0x00000010U
|
||||
|
||||
#define MODE_INPUT 0x00000000U /*!< Input Mode */
|
||||
#define MODE_OUTPUT 0x00000001U /*!< Output Mode */
|
||||
#define MODE_AF 0x00000002U /*!< Alternate Function Mode */
|
||||
#define MODE_ANALOG 0x00000003U /*!< Analog Mode */
|
||||
|
||||
#define MODE_PP 0x00000000U /*!< Push Pull Mode */
|
||||
#define MODE_OD 0x00000010U /*!< Open Drain Mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
@ -1448,15 +1448,15 @@
|
|||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||
((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
|
||||
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
|
||||
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF4_I2C1) || \
|
||||
((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || \
|
||||
((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
|
||||
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
|
||||
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
||||
((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \
|
||||
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM9) || \
|
||||
((AF) == GPIO_AF3_TIM10) || ((AF) == GPIO_AF3_TIM11) || \
|
||||
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
|
||||
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
|
||||
((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI4) || \
|
||||
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF7_USART1) || \
|
||||
((AF) == GPIO_AF7_USART2) || ((AF) == GPIO_AF8_USART6) || \
|
||||
((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \
|
||||
((AF) == GPIO_AF15_EVENTOUT))
|
||||
|
||||
((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF15_EVENTOUT))
|
||||
#endif /* STM32F401xC || STM32F401xE */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------- STM32F410xx------------------------*/
|
||||
|
|
|
@ -22,7 +22,7 @@
|
|||
#define STM32F4xx_HAL_HASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
@ -51,7 +51,7 @@ typedef struct
|
|||
|
||||
uint32_t KeySize; /*!< The key size is used only in HMAC operation. */
|
||||
|
||||
uint8_t* pKey; /*!< The key is used only in HMAC operation. */
|
||||
uint8_t *pKey; /*!< The key is used only in HMAC operation. */
|
||||
|
||||
} HASH_InitTypeDef;
|
||||
|
||||
|
@ -66,7 +66,7 @@ typedef enum
|
|||
HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
|
||||
HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */
|
||||
HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */
|
||||
}HAL_HASH_StateTypeDef;
|
||||
} HAL_HASH_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL phase structures definition
|
||||
|
@ -81,7 +81,7 @@ typedef enum
|
|||
(step 2 consists in entering the message text) */
|
||||
HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase
|
||||
(step 3 consists in entering the outer hash function key) */
|
||||
}HAL_HASH_PhaseTypeDef;
|
||||
} HAL_HASH_PhaseTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL HASH mode suspend definitions
|
||||
|
@ -90,7 +90,7 @@ typedef enum
|
|||
{
|
||||
HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */
|
||||
HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */
|
||||
}HAL_HASH_SuspendTypeDef;
|
||||
} HAL_HASH_SuspendTypeDef;
|
||||
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
|
||||
/**
|
||||
|
@ -103,7 +103,7 @@ typedef enum
|
|||
HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */
|
||||
HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */
|
||||
HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */
|
||||
}HAL_HASH_CallbackIDTypeDef;
|
||||
} HAL_HASH_CallbackIDTypeDef;
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
|
@ -155,15 +155,15 @@ typedef struct
|
|||
__IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */
|
||||
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */
|
||||
void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH input completion callback */
|
||||
|
||||
void (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH digest computation completion callback */
|
||||
void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH digest computation completion callback */
|
||||
|
||||
void (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH error callback */
|
||||
void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH error callback */
|
||||
|
||||
void (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp Init callback */
|
||||
void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */
|
||||
void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
|
||||
} HASH_HandleTypeDef;
|
||||
|
@ -172,7 +172,7 @@ typedef struct
|
|||
/**
|
||||
* @brief HAL HASH Callback pointer definition
|
||||
*/
|
||||
typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */
|
||||
typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer to a HASH common callback functions */
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
|
@ -250,7 +250,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
|
|||
/** @defgroup HASH_alias HASH API alias
|
||||
* @{
|
||||
*/
|
||||
#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
|
||||
#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -288,8 +288,8 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
|
|||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \
|
||||
((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
|
||||
((HASH->SR & (__FLAG__)) == (__FLAG__)) )
|
||||
((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
|
||||
((HASH->SR & (__FLAG__)) == (__FLAG__)) )
|
||||
|
||||
|
||||
/** @brief Clear the specified HASH flag.
|
||||
|
@ -366,7 +366,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
|
|||
* @brief Set the number of valid bits in the last word written in data register DIN.
|
||||
* @param __SIZE__ size in bytes of last data written in Data register.
|
||||
* @retval None
|
||||
*/
|
||||
*/
|
||||
#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
|
||||
|
||||
/**
|
||||
|
@ -390,11 +390,11 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
|
|||
*/
|
||||
#if defined(HASH_CR_MDMAT)
|
||||
#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \
|
||||
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
|
||||
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
|
||||
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
|
||||
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
|
||||
#else
|
||||
#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : 16)
|
||||
#endif
|
||||
#endif /* HASH_CR_MDMAT*/
|
||||
/**
|
||||
* @brief Return number of words already pushed in the FIFO.
|
||||
* @retval Number of words already pushed in the FIFO
|
||||
|
@ -428,7 +428,8 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
|
|||
* @param __SIZE__ input data buffer size.
|
||||
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
|
||||
*/
|
||||
#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
|
||||
#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET)\
|
||||
|| (((__SIZE__) % 4U) == 0U))
|
||||
/**
|
||||
* @brief Ensure that handle phase is set to HASH processing.
|
||||
* @param __HANDLE__ HASH handle.
|
||||
|
@ -471,7 +472,8 @@ void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
|
|||
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
|
||||
pHASH_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
|
@ -486,12 +488,16 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS
|
|||
|
||||
|
||||
/* HASH processing using polling *********************************************/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
|
||||
|
||||
/**
|
||||
|
@ -503,12 +509,16 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p
|
|||
*/
|
||||
|
||||
/* HASH processing using IT **************************************************/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
|
||||
/**
|
||||
* @}
|
||||
|
@ -520,9 +530,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
|
|||
|
||||
/* HASH processing using DMA *************************************************/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -533,8 +543,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu
|
|||
*/
|
||||
|
||||
/* HASH-MAC processing using polling *****************************************/
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -544,8 +556,10 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
|
|||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -571,8 +585,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
|
|||
/* Peripheral State methods **************************************************/
|
||||
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
|
||||
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
|
||||
void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
|
||||
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
|
||||
void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
|
||||
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
|
||||
|
@ -592,14 +606,18 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
|
|||
*/
|
||||
|
||||
/* Private functions */
|
||||
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
uint32_t Timeout, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
uint32_t Timeout, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
|
||||
/**
|
||||
|
|
|
@ -22,7 +22,7 @@
|
|||
#define STM32F4xx_HAL_HASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
@ -51,12 +51,16 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -66,12 +70,16 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
|
|||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -81,9 +89,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
|
|||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -92,8 +100,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
|
|||
/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -102,8 +112,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
@ -33,7 +33,7 @@ extern "C" {
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HCD
|
||||
/** @addtogroup HCD HCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
@ -112,6 +112,10 @@ typedef struct
|
|||
#define HCD_SPEED_FULL USBH_FSLS_SPEED
|
||||
#define HCD_SPEED_LOW USBH_FSLS_SPEED
|
||||
|
||||
#define HCD_DEVICE_SPEED_HIGH 0U
|
||||
#define HCD_DEVICE_SPEED_FULL 1U
|
||||
#define HCD_DEVICE_SPEED_LOW 2U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -263,9 +267,6 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
|
||||
|
@ -294,20 +295,11 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
|
|||
* @}
|
||||
*/
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup HCD_Private_Functions HCD Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
|
|
@ -85,7 +85,7 @@ typedef struct
|
|||
* 01 : Abort (Abort user request on going)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 Peripheral initilisation status
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called)
|
||||
* b4 (not used)
|
||||
|
|
|
@ -516,7 +516,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
|||
*/
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __SR__ copy of I2S SR regsiter.
|
||||
* @param __SR__ copy of I2S SR register.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
||||
|
@ -531,7 +531,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
|||
& ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
||||
* @param __CR2__ copy of I2S CR2 regsiter.
|
||||
* @param __CR2__ copy of I2S CR2 register.
|
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
|
|
|
@ -83,9 +83,9 @@ typedef struct
|
|||
* 01 : (Not Used)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 IP initilisation status
|
||||
* b5 IP initialisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP not initialized. HAL IRDA Init function already called)
|
||||
* 1 : Init done (IP initialized. HAL IRDA Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
|
@ -100,9 +100,9 @@ typedef struct
|
|||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 IP initilisation status
|
||||
* b5 IP initialisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP not initialized)
|
||||
* 1 : Init done (IP initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
|
|
|
@ -84,13 +84,10 @@ typedef struct
|
|||
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
|
||||
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
|
||||
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -128,7 +125,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
/* Initialization/Start functions ********************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -137,7 +134,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
|||
* @{
|
||||
*/
|
||||
/* I/O operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -356,10 +356,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
|||
*/
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
|
@ -495,7 +495,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
|||
* @retval Interrupt status.
|
||||
*/
|
||||
|
||||
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief LPTIM Option Register
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
|
@ -513,50 +514,58 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
|||
* @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR\
|
||||
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR\
|
||||
&= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable event on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR\
|
||||
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable event on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR\
|
||||
&= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
#if defined(EXTI_IMR_MR23)
|
||||
|
||||
/**
|
||||
* @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR\
|
||||
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR\
|
||||
&= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR\
|
||||
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR\
|
||||
&= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
|
||||
|
@ -571,26 +580,29 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
|||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
|
||||
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
|
||||
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.
|
||||
* @retval Line Status.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR\
|
||||
& LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Clear the LPTIM Wake-up Timer associated Exti line flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR\
|
||||
= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER\
|
||||
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
#endif /* EXTI_IMR_MR23 */
|
||||
|
||||
/**
|
||||
|
@ -603,9 +615,9 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
|||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group1
|
||||
* @brief Initialization and Configuration functions.
|
||||
* @{
|
||||
*/
|
||||
* @brief Initialization and Configuration functions.
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
|
||||
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
|
||||
|
@ -618,9 +630,9 @@ void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
|
|||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group2
|
||||
* @brief Start-Stop operation functions.
|
||||
* @{
|
||||
*/
|
||||
* @brief Start-Stop operation functions.
|
||||
* @{
|
||||
*/
|
||||
/* Start/Stop operation functions *********************************************/
|
||||
/* ################################# PWM Mode ################################*/
|
||||
/* Blocking mode: Polling */
|
||||
|
@ -674,9 +686,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
|||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group3
|
||||
* @brief Read operation functions.
|
||||
* @{
|
||||
*/
|
||||
* @brief Read operation functions.
|
||||
* @{
|
||||
*/
|
||||
/* Reading operation functions ************************************************/
|
||||
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
|
||||
|
@ -686,9 +698,9 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
|
|||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group4
|
||||
* @brief LPTIM IRQ handler and callback functions.
|
||||
* @{
|
||||
*/
|
||||
* @brief LPTIM IRQ handler and callback functions.
|
||||
* @{
|
||||
*/
|
||||
/* LPTIM IRQ functions *******************************************************/
|
||||
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
|
@ -703,7 +715,8 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
|
|||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
|
||||
pLPTIM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
/**
|
||||
|
@ -711,9 +724,9 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_
|
|||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Group5
|
||||
* @brief Peripheral State functions.
|
||||
* @{
|
||||
*/
|
||||
* @brief Peripheral State functions.
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
|
@ -783,13 +796,13 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
|
|||
((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
|
||||
((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
|
||||
|
||||
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_5))
|
||||
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_5))
|
||||
|
||||
#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
|
||||
((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
|
||||
|
|
|
@ -54,7 +54,7 @@ typedef enum
|
|||
HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */
|
||||
HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */
|
||||
HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */
|
||||
HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfert State */
|
||||
HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfer State */
|
||||
HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */
|
||||
}HAL_MMC_StateTypeDef;
|
||||
/**
|
||||
|
|
|
@ -976,11 +976,10 @@ typedef struct
|
|||
* a Power On Reset (POR).
|
||||
* @param __RTCCLKSource__ specifies the RTC clock source.
|
||||
* This parameter can be one of the following values:
|
||||
@arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock.
|
||||
* @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
|
||||
* @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
|
||||
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
|
||||
* as RTC clock, where x:[2,31]
|
||||
* @arg @ref RCC_RTCCLKSOURCE_NO_CLK : No clock selected as RTC clock.
|
||||
* @arg @ref RCC_RTCCLKSOURCE_LSE : LSE selected as RTC clock.
|
||||
* @arg @ref RCC_RTCCLKSOURCE_LSI : LSI selected as RTC clock.
|
||||
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
|
||||
* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
|
||||
* work in STOP and STANDBY modes, and can be used as wake-up source.
|
||||
* However, when the HSE clock is used as RTC clock source, the RTC
|
||||
|
@ -1007,8 +1006,7 @@ typedef struct
|
|||
/**
|
||||
* @brief Get the RTC and HSE clock divider (RTCPRE).
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
|
||||
* as RTC clock, where x:[2,31]
|
||||
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
|
||||
*/
|
||||
#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
|
||||
|
||||
|
|
|
@ -103,7 +103,7 @@ typedef struct
|
|||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
|
||||
uint32_t PLLSAIM; /*!< Specifies division factor for PLL VCO input clock.
|
||||
This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
|
||||
|
||||
uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
|
||||
|
@ -4969,7 +4969,6 @@ typedef struct
|
|||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||
#define __HAL_RCC_USART3_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
|
||||
|
@ -4977,7 +4976,6 @@ typedef struct
|
|||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
|
||||
|
||||
#if defined(STM32F413xx) || defined(STM32F423xx)
|
||||
#define __HAL_RCC_UART4_CLK_ENABLE() do { \
|
||||
|
@ -5098,9 +5096,7 @@ typedef struct
|
|||
#endif /* STM32F413xx || STM32F423xx */
|
||||
#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
|
||||
#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
|
||||
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||
#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
|
||||
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
|
||||
#if defined(STM32F413xx) || defined(STM32F423xx)
|
||||
#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
|
||||
#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
|
||||
|
@ -5140,9 +5136,7 @@ typedef struct
|
|||
#endif /* STM32F413xx || STM32F423xx */
|
||||
#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
|
||||
#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
|
||||
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||
#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
|
||||
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */
|
||||
#if defined(STM32F413xx) || defined(STM32F423xx)
|
||||
#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
|
||||
#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
|
||||
|
@ -5171,9 +5165,7 @@ typedef struct
|
|||
#endif /* STM32F413xx || STM32F423xx */
|
||||
#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
|
||||
#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
|
||||
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||
#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
|
||||
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */
|
||||
#if defined(STM32F413xx) || defined(STM32F423xx)
|
||||
#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
|
||||
#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
|
||||
|
@ -5445,9 +5437,7 @@ typedef struct
|
|||
#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
|
||||
#endif /* STM32F413xx || STM32F423xx */
|
||||
#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
|
||||
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||
#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
|
||||
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
|
||||
#if defined(STM32F413xx) || defined(STM32F423xx)
|
||||
#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
|
||||
#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
|
||||
|
@ -5475,9 +5465,7 @@ typedef struct
|
|||
#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
|
||||
#endif /* STM32F413xx || STM32F423xx */
|
||||
#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
|
||||
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||
#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
|
||||
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
|
||||
#if defined(STM32F413xx) || defined(STM32F423xx)
|
||||
#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
|
||||
#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
|
||||
|
@ -5633,9 +5621,7 @@ typedef struct
|
|||
#endif /* STM32F413xx || STM32F423xx */
|
||||
#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
|
||||
#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
|
||||
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||
#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
|
||||
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
|
||||
#if defined(STM32F413xx) || defined(STM32F423xx)
|
||||
#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
|
||||
#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
|
||||
|
@ -5664,9 +5650,7 @@ typedef struct
|
|||
#endif /* STM32F413xx || STM32F423xx */
|
||||
#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
|
||||
#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
|
||||
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||
#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
|
||||
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
|
||||
#if defined(STM32F413xx) || defined(STM32F423xx)
|
||||
#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
|
||||
#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
|
||||
|
@ -6384,7 +6368,7 @@ typedef struct
|
|||
* @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
|
||||
* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
|
||||
* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
|
||||
|
@ -6392,7 +6376,7 @@ typedef struct
|
|||
/** @brief Macro to get the DFSDM1 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
|
||||
* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
|
||||
* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock.
|
||||
*/
|
||||
#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
|
||||
|
||||
|
@ -6420,7 +6404,7 @@ typedef struct
|
|||
* @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
|
||||
* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
|
||||
* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__))
|
||||
|
@ -6428,7 +6412,7 @@ typedef struct
|
|||
/** @brief Macro to get the DFSDM2 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
|
||||
* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
|
||||
* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock.
|
||||
*/
|
||||
#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
|
||||
|
||||
|
@ -6867,16 +6851,8 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
|
|||
/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F411xE)
|
||||
#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
|
||||
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
|
||||
#else /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||
|
||||
STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410Tx || STM32F410Cx ||
|
||||
STM32F410Rx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Cx || STM32F412Rx ||
|
||||
STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||
#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
|
||||
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
|
||||
#endif /* STM32F411xE */
|
||||
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
||||
#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
|
||||
|
|
|
@ -105,12 +105,11 @@ typedef struct
|
|||
with [1 Sec / SecondFraction +1] granularity.
|
||||
This field will be used only by HAL_RTC_GetTime function */
|
||||
|
||||
uint32_t DayLightSaving; /*!< Specifies DayLight Save Operation.
|
||||
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
|
||||
uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time,
|
||||
please use HAL_RTC_DST_xxx functions */
|
||||
|
||||
uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
|
||||
in CR register to store the operation.
|
||||
This parameter can be a value of @ref RTC_StoreOperation_Definitions */
|
||||
uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time,
|
||||
please use HAL_RTC_DST_xxx functions */
|
||||
}RTC_TimeTypeDef;
|
||||
|
||||
/**
|
||||
|
@ -701,6 +700,11 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
|
|||
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -22,7 +22,7 @@
|
|||
#define __STM32F4xx_HAL_SAI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
@ -56,7 +56,7 @@ typedef enum
|
|||
HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */
|
||||
HAL_SAI_STATE_TIMEOUT = 0x03U, /*!< SAI timeout state */
|
||||
HAL_SAI_STATE_ERROR = 0x04U /*!< SAI error state */
|
||||
}HAL_SAI_StateTypeDef;
|
||||
} HAL_SAI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SAI Callback prototype
|
||||
|
@ -132,13 +132,14 @@ typedef struct
|
|||
|
||||
uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
|
||||
This parameter can be a value of @ref SAI_Block_Clock_Strobing */
|
||||
}SAI_InitTypeDef;
|
||||
} SAI_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
|
||||
* @brief SAI Frame Init structure definition
|
||||
* @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware).
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
|
@ -162,13 +163,15 @@ typedef struct
|
|||
|
||||
uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset.
|
||||
This parameter can be a value of @ref SAI_Block_FS_Offset */
|
||||
}SAI_FrameInitTypeDef;
|
||||
} SAI_FrameInitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
|
||||
* @brief SAI Block Slot Init Structure definition
|
||||
* @note For SPDIF protocol, these parameters are not used (set by hardware).
|
||||
* @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware).
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
|
@ -184,7 +187,7 @@ typedef struct
|
|||
|
||||
uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated.
|
||||
This parameter can be a value of @ref SAI_Block_Slot_Active */
|
||||
}SAI_SlotInitTypeDef;
|
||||
} SAI_SlotInitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -22,7 +22,7 @@
|
|||
#define __STM32F4xx_HAL_SAI_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
|
@ -55,7 +55,7 @@ typedef enum
|
|||
HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */
|
||||
HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */
|
||||
HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receiving State */
|
||||
HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfert State */
|
||||
HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfer State */
|
||||
HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */
|
||||
}HAL_SD_StateTypeDef;
|
||||
/**
|
||||
|
|
|
@ -101,7 +101,7 @@ typedef struct
|
|||
* 11 : Error
|
||||
* b5 IP initilisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called)
|
||||
* 1 : Init done (IP initialized. HAL SMARTCARD Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
|
@ -118,7 +118,7 @@ typedef struct
|
|||
* xx : Should be set to 00
|
||||
* b5 IP initilisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP not initialized)
|
||||
* 1 : Init done (IP initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
|
|
|
@ -86,7 +86,7 @@ typedef struct
|
|||
* 01 : Abort (Abort user request on going)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 IP initilisation status
|
||||
* b5 IP initialisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP initialized and ready to use. HAL SMBUS Init function called)
|
||||
* b4 (not used)
|
||||
|
@ -609,7 +609,7 @@ void HAL_SMBUS_AbortCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
@ -493,7 +493,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __SR__ copy of SPI SR regsiter.
|
||||
* @param __SR__ copy of SPI SR register.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
|
||||
|
@ -505,10 +505,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
* @arg SPI_FLAG_FRE: Frame format error flag
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
|
||||
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
|
||||
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
||||
* @param __CR2__ copy of SPI CR2 regsiter.
|
||||
* @param __CR2__ copy of SPI CR2 register.
|
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
|
@ -516,15 +517,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
|
||||
(__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks if SPI Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI Mode.
|
||||
* This parameter can be a value of @ref SPI_Mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
|
||||
((__MODE__) == SPI_MODE_MASTER))
|
||||
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
|
||||
((__MODE__) == SPI_MODE_MASTER))
|
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI Direction Mode.
|
||||
|
@ -561,25 +563,25 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
* This parameter can be a value of @ref SPI_Clock_Polarity
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
|
||||
((__CPOL__) == SPI_POLARITY_HIGH))
|
||||
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
|
||||
((__CPOL__) == SPI_POLARITY_HIGH))
|
||||
|
||||
/** @brief Checks if SPI Clock Phase parameter is in allowed range.
|
||||
* @param __CPHA__ specifies the SPI Clock Phase.
|
||||
* This parameter can be a value of @ref SPI_Clock_Phase
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
|
||||
((__CPHA__) == SPI_PHASE_2EDGE))
|
||||
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
|
||||
((__CPHA__) == SPI_PHASE_2EDGE))
|
||||
|
||||
/** @brief Checks if SPI Slave Select parameter is in allowed range.
|
||||
* @param __NSS__ specifies the SPI Slave Select management parameter.
|
||||
* This parameter can be a value of @ref SPI_Slave_Select_management
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_INPUT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_OUTPUT))
|
||||
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_INPUT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_OUTPUT))
|
||||
|
||||
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
|
||||
* @param __PRESCALER__ specifies the SPI Baudrate prescaler.
|
||||
|
@ -600,16 +602,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
* This parameter can be a value of @ref SPI_MSB_LSB_transmission
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
|
||||
((__BIT__) == SPI_FIRSTBIT_LSB))
|
||||
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
|
||||
((__BIT__) == SPI_FIRSTBIT_LSB))
|
||||
|
||||
/** @brief Checks if SPI TI mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI TI mode.
|
||||
* This parameter can be a value of @ref SPI_TI_mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
|
||||
((__MODE__) == SPI_TIMODE_ENABLE))
|
||||
#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
|
||||
((__MODE__) == SPI_TIMODE_ENABLE))
|
||||
|
||||
/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
|
||||
* @param __CALCULATION__ specifies the SPI CRC calculation enable state.
|
||||
|
@ -624,7 +626,9 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))
|
||||
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
|
||||
((__POLYNOMIAL__) <= 0xFFFFU) && \
|
||||
(((__POLYNOMIAL__)&0x1U) != 0U))
|
||||
|
||||
/** @brief Checks if DMA handle is valid.
|
||||
* @param __HANDLE__ specifies a DMA Handle.
|
||||
|
|
|
@ -75,7 +75,7 @@ typedef enum
|
|||
typedef struct __SRAM_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
|
||||
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
|
||||
{
|
||||
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
|
|
|
@ -294,6 +294,26 @@ typedef enum
|
|||
HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
|
||||
} HAL_TIM_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Channel States definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
|
||||
HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
|
||||
HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
|
||||
} HAL_TIM_ChannelStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA Burst States definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
|
||||
HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
|
||||
HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
|
||||
} HAL_TIM_DMABurstStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Active channel structures definition
|
||||
*/
|
||||
|
@ -315,13 +335,16 @@ typedef struct __TIM_HandleTypeDef
|
|||
typedef struct
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
{
|
||||
TIM_TypeDef *Instance; /*!< Register base address */
|
||||
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
|
||||
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
|
||||
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
|
||||
This array is accessed by a @ref DMA_Handle_index */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
|
||||
TIM_TypeDef *Instance; /*!< Register base address */
|
||||
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
|
||||
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
|
||||
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
|
||||
This array is accessed by a @ref DMA_Handle_index */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
|
||||
__IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */
|
||||
__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
|
||||
__IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
|
||||
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
|
||||
|
@ -360,34 +383,34 @@ typedef struct
|
|||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
|
||||
,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
|
||||
,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
|
||||
,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
|
||||
,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
|
||||
,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
|
||||
,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
|
||||
,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
|
||||
,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
|
||||
,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
|
||||
,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
|
||||
,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
|
||||
,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
|
||||
,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
|
||||
,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
|
||||
,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
|
||||
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
|
||||
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
|
||||
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
|
||||
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
|
||||
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
|
||||
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
|
||||
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
|
||||
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
|
||||
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
|
||||
|
||||
,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
|
||||
,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
|
||||
,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
|
||||
,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
|
||||
,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
|
||||
,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
|
||||
,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
|
||||
,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
|
||||
,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
|
||||
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
|
||||
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
|
||||
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
|
||||
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
|
||||
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
|
||||
, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
|
||||
, HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
|
||||
} HAL_TIM_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
|
@ -931,24 +954,24 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
|||
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
|
||||
* @{
|
||||
*/
|
||||
#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -993,25 +1016,45 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
|||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
|
||||
(__HANDLE__)->Base_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
|
||||
(__HANDLE__)->Base_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
|
||||
} while(0)
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
|
@ -1710,15 +1753,15 @@ mode.
|
|||
#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
|
||||
((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
|
||||
|
||||
#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
|
||||
#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
|
||||
|
@ -1729,6 +1772,8 @@ mode.
|
|||
((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
|
||||
|
||||
#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
|
||||
|
||||
#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
|
||||
|
||||
#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
|
||||
|
@ -1759,6 +1804,44 @@ mode.
|
|||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
|
||||
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
|
||||
|
||||
#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
|
||||
(__HANDLE__)->ChannelState[3])
|
||||
|
||||
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
|
||||
((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
|
||||
|
||||
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
|
||||
(__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
|
||||
} while(0)
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
|
||||
(__HANDLE__)->ChannelNState[3])
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
|
||||
((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
|
||||
(__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -1930,9 +2013,15 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC
|
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HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
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HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
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uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
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HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
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uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
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uint32_t DataLength);
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HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
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HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
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uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
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HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
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uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
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uint32_t DataLength);
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HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
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HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
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uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
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@ -1978,6 +2067,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
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HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
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HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
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HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
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/* Peripheral Channel state functions ************************************************/
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HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
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HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
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HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
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/**
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* @}
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*/
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@ -1997,7 +2091,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
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void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
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uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
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void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
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void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
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void TIM_DMAError(DMA_HandleTypeDef *hdma);
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void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
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@ -129,66 +129,66 @@ typedef struct
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* @{
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*/
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#if defined(SPDIFRX)
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#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
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((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
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((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
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((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
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(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
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((TIM_REMAP) == TIM_TIM5_LSI) || \
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((TIM_REMAP) == TIM_TIM5_LSE) || \
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((TIM_REMAP) == TIM_TIM5_RTC))) || \
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(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
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((TIM_REMAP) == TIM_TIM11_SPDIFRX) || \
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((TIM_REMAP) == TIM_TIM11_HSE))))
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#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
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((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
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((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
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((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
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(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
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((TIM_REMAP) == TIM_TIM5_LSI) || \
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((TIM_REMAP) == TIM_TIM5_LSE) || \
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((TIM_REMAP) == TIM_TIM5_RTC))) || \
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(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
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((TIM_REMAP) == TIM_TIM11_SPDIFRX) || \
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((TIM_REMAP) == TIM_TIM11_HSE))))
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#elif defined(TIM2)
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#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP)
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#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
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((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
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((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
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((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
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(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
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((TIM_REMAP) == TIM_TIM5_LSI) || \
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((TIM_REMAP) == TIM_TIM5_LSE) || \
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((TIM_REMAP) == TIM_TIM5_RTC))) || \
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(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
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((TIM_REMAP) == TIM_TIM11_HSE))) || \
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(((INSTANCE) == TIM1) && (((TIM_REMAP) == TIM_TIM1_TIM3_TRGO) || \
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((TIM_REMAP) == TIM_TIM1_LPTIM))) || \
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(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_TIM3_TRGO) || \
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((TIM_REMAP) == TIM_TIM5_LPTIM))) || \
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(((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_TIM3_TRGO) || \
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((TIM_REMAP) == TIM_TIM9_LPTIM))))
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#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
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((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
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((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
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((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
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(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
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((TIM_REMAP) == TIM_TIM5_LSI) || \
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((TIM_REMAP) == TIM_TIM5_LSE) || \
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((TIM_REMAP) == TIM_TIM5_RTC))) || \
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(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
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((TIM_REMAP) == TIM_TIM11_HSE))) || \
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(((INSTANCE) == TIM1) && (((TIM_REMAP) == TIM_TIM1_TIM3_TRGO) || \
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((TIM_REMAP) == TIM_TIM1_LPTIM))) || \
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(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_TIM3_TRGO) || \
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((TIM_REMAP) == TIM_TIM5_LPTIM))) || \
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(((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_TIM3_TRGO) || \
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((TIM_REMAP) == TIM_TIM9_LPTIM))))
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#elif defined(TIM8)
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#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
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((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
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((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
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((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
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(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
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((TIM_REMAP) == TIM_TIM5_LSI) || \
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((TIM_REMAP) == TIM_TIM5_LSE) || \
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((TIM_REMAP) == TIM_TIM5_RTC))) || \
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(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
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||||
((TIM_REMAP) == TIM_TIM11_HSE))))
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#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
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((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
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((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
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((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
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(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
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((TIM_REMAP) == TIM_TIM5_LSI) || \
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((TIM_REMAP) == TIM_TIM5_LSE) || \
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((TIM_REMAP) == TIM_TIM5_RTC))) || \
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(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
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((TIM_REMAP) == TIM_TIM11_HSE))))
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#else
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#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
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((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ETH_PTP) || \
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((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
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((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
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(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
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((TIM_REMAP) == TIM_TIM5_LSI) || \
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((TIM_REMAP) == TIM_TIM5_LSE) || \
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((TIM_REMAP) == TIM_TIM5_RTC))) || \
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(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
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((TIM_REMAP) == TIM_TIM11_HSE))))
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#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
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((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ETH_PTP) || \
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((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
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((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
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(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
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((TIM_REMAP) == TIM_TIM5_LSI) || \
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((TIM_REMAP) == TIM_TIM5_LSE) || \
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((TIM_REMAP) == TIM_TIM5_RTC))) || \
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(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
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((TIM_REMAP) == TIM_TIM11_HSE))))
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#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */
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#else
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#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
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((((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
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((TIM_REMAP) == TIM_TIM5_LSI) || \
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((TIM_REMAP) == TIM_TIM5_LSE) || \
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((TIM_REMAP) == TIM_TIM5_RTC))) || \
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(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
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((TIM_REMAP) == TIM_TIM11_HSE))))
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#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
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((((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
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((TIM_REMAP) == TIM_TIM5_LSI) || \
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((TIM_REMAP) == TIM_TIM5_LSE) || \
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((TIM_REMAP) == TIM_TIM5_RTC))) || \
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(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
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((TIM_REMAP) == TIM_TIM11_HSE))))
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#endif /* SPDIFRX */
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/**
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@ -318,6 +318,7 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
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*/
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/* Extended Peripheral State functions ***************************************/
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||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
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HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
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/**
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* @}
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*/
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@ -88,7 +88,7 @@ typedef struct
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* 11 : Error
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||||
* b5 Peripheral initialization status
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||||
* 0 : Reset (Peripheral not initialized)
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* 1 : Init done (Peripheral not initialized. HAL UART Init function already called)
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* 1 : Init done (Peripheral initialized. HAL UART Init function already called)
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* b4-b3 (not used)
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||||
* xx : Should be set to 00
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* b2 Intrinsic process state
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|
@ -105,7 +105,7 @@ typedef struct
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|||
* xx : Should be set to 00
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||||
* b5 Peripheral initialization status
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||||
* 0 : Reset (Peripheral not initialized)
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||||
* 1 : Init done (Peripheral not initialized)
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* 1 : Init done (Peripheral initialized)
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||||
* b4-b2 (not used)
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||||
* xxx : Should be set to 000
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||||
* b1 Rx state
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@ -135,6 +135,15 @@ typedef enum
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|||
Value is allowed for gState only */
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||||
} HAL_UART_StateTypeDef;
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||||
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||||
/**
|
||||
* @brief HAL UART Reception type definition
|
||||
* @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
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||||
* It is expected to admit following values :
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||||
* HAL_UART_RECEPTION_STANDARD = 0x00U,
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* HAL_UART_RECEPTION_TOIDLE = 0x01U,
|
||||
*/
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||||
typedef uint32_t HAL_UART_RxTypeTypeDef;
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||||
/**
|
||||
* @brief UART handle Structure definition
|
||||
*/
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||||
|
@ -156,6 +165,8 @@ typedef struct __UART_HandleTypeDef
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||||
__IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
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||||
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||||
__IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
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||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
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||||
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||||
DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
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|
@ -181,6 +192,7 @@ typedef struct __UART_HandleTypeDef
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void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
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||||
void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */
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||||
void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
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||||
void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */
|
||||
|
||||
void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
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||||
void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
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|
@ -213,6 +225,7 @@ typedef enum
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|||
* @brief HAL UART Callback pointer definition
|
||||
*/
|
||||
typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
|
||||
typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
|
||||
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
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||||
|
@ -369,6 +382,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
|
||||
* @{
|
||||
*/
|
||||
#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
|
||||
#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -682,6 +704,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
|
|||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
|
@ -702,6 +727,11 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
|
|||
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
|
||||
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/* Transfer Abort functions */
|
||||
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
|
||||
|
@ -720,6 +750,8 @@ void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
|
|||
void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
|
||||
void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
|
||||
|
||||
void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -825,6 +857,9 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
|
|||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -56,7 +56,7 @@ typedef struct
|
|||
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
|
||||
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
|
||||
|
||||
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
|
||||
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
|
||||
This parameter can be a value of @ref WWDG_EWI_Mode */
|
||||
|
||||
} WWDG_InitTypeDef;
|
||||
|
@ -68,17 +68,17 @@ typedef struct
|
|||
typedef struct __WWDG_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
{
|
||||
WWDG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
|
||||
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
|
||||
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
|
||||
|
||||
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
|
||||
#endif
|
||||
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
} WWDG_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
|
@ -87,8 +87,8 @@ typedef struct
|
|||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
|
||||
HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
|
||||
HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */
|
||||
HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */
|
||||
} HAL_WWDG_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
|
@ -96,7 +96,7 @@ typedef enum
|
|||
*/
|
||||
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
|
||||
|
||||
#endif
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -260,9 +260,10 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
|
|||
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
|
||||
pWWDG_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
|
||||
#endif
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -6,7 +6,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
|
@ -18,8 +18,8 @@
|
|||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_LL_DAC_H
|
||||
#define __STM32F4xx_LL_DAC_H
|
||||
#ifndef STM32F4xx_LL_DAC_H
|
||||
#define STM32F4xx_LL_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
@ -48,52 +48,86 @@ extern "C" {
|
|||
|
||||
/* Internal masks for DAC channels definition */
|
||||
/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
|
||||
/* - channel bits position into register CR */
|
||||
/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
|
||||
/* - channel bits position into register SWTRIG */
|
||||
/* - channel register offset of data holding register DHRx */
|
||||
/* - channel register offset of data output register DORx */
|
||||
#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
|
||||
#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
|
||||
#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
|
||||
|
||||
#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
|
||||
#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
|
||||
CR, MCR, CCR, SHHR, SHRR of channel 1 */
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
|
||||
#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
|
||||
CR, MCR, CCR, SHHR, SHRR of channel 2 */
|
||||
#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
|
||||
#else
|
||||
#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET)
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
|
||||
#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
|
||||
#else
|
||||
#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
|
||||
#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
|
||||
#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
|
||||
#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
|
||||
#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
|
||||
DHR12Rx channel 1 (shifted left of 20 bits) */
|
||||
#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
|
||||
DHR12Rx channel 1 (shifted left of 24 bits) */
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
|
||||
#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
|
||||
#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
|
||||
#define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus
|
||||
DHR12Rx channel 1 (shifted left of 16 bits) */
|
||||
#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
|
||||
DHR12Rx channel 1 (shifted left of 20 bits) */
|
||||
#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
|
||||
DHR12Rx channel 1 (shifted left of 24 bits) */
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
|
||||
#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
|
||||
#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
|
||||
#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
|
||||
#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL
|
||||
#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
|
||||
#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
|
||||
#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
|
||||
| DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
|
||||
|
||||
#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
|
||||
#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
|
||||
#define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus
|
||||
DORx channel 2 (shifted left of 28 bits) */
|
||||
#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
|
||||
#else
|
||||
#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
|
||||
#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
|
||||
DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
|
||||
#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
|
||||
to position 0 */
|
||||
#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
|
||||
to position 0 */
|
||||
|
||||
#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx
|
||||
channel 1 or 2 versus DHR12Rx channel 1
|
||||
(shifted left of 16 bits) */
|
||||
#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
|
||||
channel 1 or 2 versus DHR12Rx channel 1
|
||||
(shifted left of 20 bits) */
|
||||
#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
|
||||
channel 1 or 2 versus DHR12Rx channel 1
|
||||
(shifted left of 24 bits) */
|
||||
#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx
|
||||
channel 1 or 2 versus DORx channel 1
|
||||
(shifted left of 28 bits) */
|
||||
|
||||
/* DAC registers bits positions */
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
|
||||
#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
|
||||
#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
#endif
|
||||
#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
|
||||
#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
|
||||
#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
|
||||
|
||||
/* Miscellaneous data */
|
||||
#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
|
||||
#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
|
||||
bits (voltage range determined by analog voltage
|
||||
references Vref+ and Vref-, refer to reference manual) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -105,27 +139,16 @@ extern "C" {
|
|||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Driver macro reserved for internal use: isolate bits with the
|
||||
* selected mask and shift them to the register LSB
|
||||
* (shift mask on register position bit 0).
|
||||
* @param __BITS__ Bits in register 32 bits
|
||||
* @param __MASK__ Mask in register 32 bits
|
||||
* @retval Bits in register 32 bits
|
||||
*/
|
||||
#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
|
||||
(((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
|
||||
|
||||
/**
|
||||
* @brief Driver macro reserved for internal use: set a pointer to
|
||||
* a register from a register basis from which an offset
|
||||
* is applied.
|
||||
* @param __REG__ Register basis from which the offset is applied.
|
||||
* @param __REG_OFFFSET__ Offset to be applied (unit number of registers).
|
||||
* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
|
||||
* @retval Pointer to register address
|
||||
*/
|
||||
*/
|
||||
#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
|
||||
((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
|
||||
((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -143,28 +166,38 @@ extern "C" {
|
|||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
|
||||
uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
|
||||
internal (SW start) or from external peripheral
|
||||
(timer event, external interrupt line).
|
||||
This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_DAC_SetTriggerSource(). */
|
||||
|
||||
uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_DAC_SetWaveAutoGeneration(). */
|
||||
|
||||
uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
|
||||
If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
|
||||
If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
|
||||
@note If waveform automatic generation mode is disabled, this parameter is discarded.
|
||||
If waveform automatic generation mode is set to noise, this parameter
|
||||
can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
|
||||
If waveform automatic generation mode is set to triangle,
|
||||
this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
|
||||
@note If waveform automatic generation mode is disabled,
|
||||
this parameter is discarded.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_DAC_SetWaveNoiseLFSR(),
|
||||
@ref LL_DAC_SetWaveTriangleAmplitude()
|
||||
depending on the wave automatic generation selected. */
|
||||
|
||||
uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
|
||||
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_DAC_SetOutputBuffer(). */
|
||||
} LL_DAC_InitTypeDef;
|
||||
|
||||
/**
|
||||
|
@ -183,7 +216,6 @@ typedef struct
|
|||
*/
|
||||
/* DAC channel 1 flags */
|
||||
#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
/* DAC channel 2 flags */
|
||||
#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
|
||||
|
@ -219,13 +251,13 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
|
||||
#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
|
||||
#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -233,9 +265,9 @@ typedef struct
|
|||
/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
|
||||
#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
|
||||
#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
|
||||
#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
|
||||
#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
|
||||
#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -243,7 +275,7 @@ typedef struct
|
|||
/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
|
||||
* @{
|
||||
*/
|
||||
#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
|
||||
#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
|
||||
#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
|
||||
#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
|
||||
#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
|
||||
|
@ -262,7 +294,7 @@ typedef struct
|
|||
/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
|
||||
* @{
|
||||
*/
|
||||
#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
|
||||
#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
|
||||
#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
|
||||
#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
|
||||
#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
|
||||
|
@ -281,18 +313,17 @@ typedef struct
|
|||
/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
|
||||
* @{
|
||||
*/
|
||||
#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
|
||||
#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
|
||||
#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
|
||||
* @{
|
||||
*/
|
||||
#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
|
||||
#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
|
||||
#define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
|
||||
#define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -303,15 +334,15 @@ typedef struct
|
|||
/* List of DAC registers intended to be used (most commonly) with */
|
||||
/* DMA transfer. */
|
||||
/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
|
||||
#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
|
||||
#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
|
||||
#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
|
||||
#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
|
||||
#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
|
||||
#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
|
||||
* @note Only DAC IP HW delays are defined in DAC LL driver driver,
|
||||
* @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
|
||||
* not timeout values.
|
||||
* For details on delays values, refer to descriptions in source code
|
||||
* above each literal definition.
|
||||
|
@ -330,7 +361,7 @@ typedef struct
|
|||
/* Literal set to maximum value (refer to device datasheet, */
|
||||
/* parameter "tWAKEUP"). */
|
||||
/* Unit: us */
|
||||
#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
|
||||
#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
|
||||
|
||||
/* Delay for DAC channel voltage settling time. */
|
||||
/* Note: DAC channel startup time depends on board application environment: */
|
||||
|
@ -343,7 +374,8 @@ typedef struct
|
|||
/* Literal set to maximum value (refer to device datasheet, */
|
||||
/* parameter "tSETTLING"). */
|
||||
/* Unit: us */
|
||||
#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
|
||||
#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -423,33 +455,33 @@ typedef struct
|
|||
*/
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
|
||||
(((__DECIMAL_NB__) == 1U) \
|
||||
(((__DECIMAL_NB__) == 1UL) \
|
||||
? ( \
|
||||
LL_DAC_CHANNEL_1 \
|
||||
) \
|
||||
: \
|
||||
(((__DECIMAL_NB__) == 2U) \
|
||||
(((__DECIMAL_NB__) == 2UL) \
|
||||
? ( \
|
||||
LL_DAC_CHANNEL_2 \
|
||||
) \
|
||||
: \
|
||||
( \
|
||||
0 \
|
||||
0UL \
|
||||
) \
|
||||
) \
|
||||
)
|
||||
#else
|
||||
#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
|
||||
(((__DECIMAL_NB__) == 1U) \
|
||||
(((__DECIMAL_NB__) == 1UL) \
|
||||
? ( \
|
||||
LL_DAC_CHANNEL_1 \
|
||||
) \
|
||||
: \
|
||||
( \
|
||||
0 \
|
||||
0UL \
|
||||
) \
|
||||
)
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
/**
|
||||
* @brief Helper macro to define the DAC conversion data full-scale digital
|
||||
|
@ -463,7 +495,7 @@ typedef struct
|
|||
* @retval ADC conversion data equivalent voltage value (unit: mVolt)
|
||||
*/
|
||||
#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
|
||||
((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
|
||||
((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
|
||||
|
||||
/**
|
||||
* @brief Helper macro to calculate the DAC conversion data (unit: digital
|
||||
|
@ -474,8 +506,8 @@ typedef struct
|
|||
* @ref LL_DAC_ConvertData12RightAligned().
|
||||
* @note Analog reference voltage (Vref+) must be either known from
|
||||
* user board environment or can be calculated using ADC measurement
|
||||
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
|
||||
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
|
||||
* and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
|
||||
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
|
||||
* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
|
||||
* (unit: mVolt).
|
||||
* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
|
||||
|
@ -486,9 +518,9 @@ typedef struct
|
|||
#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
|
||||
__DAC_VOLTAGE__,\
|
||||
__DAC_RESOLUTION__) \
|
||||
((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
|
||||
/ (__VREFANALOG_VOLTAGE__) \
|
||||
)
|
||||
((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
|
||||
/ (__VREFANALOG_VOLTAGE__) \
|
||||
)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -503,10 +535,6 @@ typedef struct
|
|||
/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the conversion trigger source for the selected DAC channel.
|
||||
* @note For conversion trigger source to be effective, DAC trigger
|
||||
|
@ -663,7 +691,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Set the noise waveform generation for the selected DAC channel:
|
||||
* @brief Get the noise waveform generation for the selected DAC channel:
|
||||
* Noise mode and parameters LFSR (linear feedback shift register).
|
||||
* @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
|
||||
* CR MAMP2 LL_DAC_GetWaveNoiseLFSR
|
||||
|
@ -727,7 +755,8 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC
|
|||
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
|
||||
__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
|
||||
uint32_t TriangleAmplitude)
|
||||
{
|
||||
MODIFY_REG(DACx->CR,
|
||||
DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
|
||||
|
@ -735,7 +764,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Set the triangle waveform generation for the selected DAC channel:
|
||||
* @brief Get the triangle waveform generation for the selected DAC channel:
|
||||
* triangle mode and amplitude.
|
||||
* @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
|
||||
* CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
|
||||
|
@ -878,9 +907,9 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (READ_BIT(DACx->CR,
|
||||
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
== (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
|
||||
return ((READ_BIT(DACx->CR,
|
||||
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
== (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -896,7 +925,8 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_
|
|||
* LL_DMA_ConfigAddresses(DMA1,
|
||||
* LL_DMA_CHANNEL_1,
|
||||
* (uint32_t)&< array or variable >,
|
||||
* LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
|
||||
* LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
|
||||
* LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
|
||||
* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
|
||||
* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
|
||||
* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
|
||||
|
@ -921,7 +951,8 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C
|
|||
{
|
||||
/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
|
||||
/* DAC channel selected. */
|
||||
return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
|
||||
return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
|
||||
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
|
@ -988,9 +1019,9 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (READ_BIT(DACx->CR,
|
||||
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
== (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
|
||||
return ((READ_BIT(DACx->CR,
|
||||
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
== (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1055,15 +1086,17 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (READ_BIT(DACx->CR,
|
||||
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
== (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
|
||||
return ((READ_BIT(DACx->CR,
|
||||
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
== (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Trig DAC conversion by software for the selected DAC channel.
|
||||
* @note Preliminarily, DAC trigger must be set to software trigger
|
||||
* using function @ref LL_DAC_SetTriggerSource()
|
||||
* using function
|
||||
* @ref LL_DAC_Init()
|
||||
* @ref LL_DAC_SetTriggerSource()
|
||||
* with parameter "LL_DAC_TRIGGER_SOFTWARE".
|
||||
* and DAC trigger must be enabled using
|
||||
* function @ref LL_DAC_EnableTrigger().
|
||||
|
@ -1106,11 +1139,10 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha
|
|||
*/
|
||||
__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
|
||||
{
|
||||
register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
|
||||
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
|
||||
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
|
||||
|
||||
MODIFY_REG(*preg,
|
||||
DAC_DHR12R1_DACC1DHR,
|
||||
Data);
|
||||
MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1131,11 +1163,10 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_
|
|||
*/
|
||||
__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
|
||||
{
|
||||
register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
|
||||
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
|
||||
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
|
||||
|
||||
MODIFY_REG(*preg,
|
||||
DAC_DHR12L1_DACC1DHR,
|
||||
Data);
|
||||
MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1156,11 +1187,10 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t
|
|||
*/
|
||||
__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
|
||||
{
|
||||
register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
|
||||
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
|
||||
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
|
||||
|
||||
MODIFY_REG(*preg,
|
||||
DAC_DHR8R1_DACC1DHR,
|
||||
Data);
|
||||
MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
|
||||
}
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
|
@ -1175,7 +1205,8 @@ __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t
|
|||
* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
|
||||
__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
|
||||
uint32_t DataChannel2)
|
||||
{
|
||||
MODIFY_REG(DACx->DHR12RD,
|
||||
(DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
|
||||
|
@ -1193,7 +1224,8 @@ __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uin
|
|||
* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
|
||||
__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
|
||||
uint32_t DataChannel2)
|
||||
{
|
||||
/* Note: Data of DAC channel 2 shift value subtracted of 4 because */
|
||||
/* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
|
||||
|
@ -1214,14 +1246,15 @@ __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint
|
|||
* @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
|
||||
__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
|
||||
uint32_t DataChannel2)
|
||||
{
|
||||
MODIFY_REG(DACx->DHR8RD,
|
||||
(DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
|
||||
((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
|
||||
}
|
||||
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
/**
|
||||
* @brief Retrieve output data currently generated for the selected DAC channel.
|
||||
* @note Whatever alignment and resolution settings
|
||||
|
@ -1241,7 +1274,8 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
|
||||
__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
|
||||
& DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
|
||||
|
||||
return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
|
||||
}
|
||||
|
@ -1253,6 +1287,8 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D
|
|||
/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get DAC underrun flag for DAC channel 1
|
||||
* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
|
||||
|
@ -1261,7 +1297,7 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
|
||||
{
|
||||
return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
|
||||
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
|
@ -1273,7 +1309,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
|
||||
{
|
||||
return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
|
||||
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
|
||||
}
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
|
@ -1365,7 +1401,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
|
||||
{
|
||||
return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
|
||||
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
|
@ -1377,7 +1413,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
|
||||
{
|
||||
return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
|
||||
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
|
||||
}
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
|
@ -1390,9 +1426,9 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
|
|||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
|
||||
ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
|
||||
void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
|
||||
ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
|
||||
ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
|
||||
void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -1417,6 +1453,6 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_LL_DAC_H */
|
||||
#endif /* STM32F4xx_LL_DAC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
@ -285,14 +285,24 @@ typedef struct
|
|||
/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
|
||||
* @{
|
||||
*/
|
||||
#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
|
||||
#if defined (DMA_SxCR_CHSEL_3)
|
||||
#define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 /* Select Channel8 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) /* Select Channel9 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) /* Select Channel10 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel11 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) /* Select Channel12 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel13 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel14 of DMA Instance */
|
||||
#define LL_DMA_CHANNEL_15 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel15 of DMA Instance */
|
||||
#endif /* DMA_SxCR_CHSEL_3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -66,73 +66,103 @@ typedef struct
|
|||
uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
|
||||
- This parameter can be one value of @ref DMA2D_LL_EC_MODE.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/
|
||||
This parameter can be modified afterwards,
|
||||
using unitary function @ref LL_DMA2D_SetMode(). */
|
||||
|
||||
uint32_t ColorMode; /*!< Specifies the color format of the output image.
|
||||
- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
|
||||
This parameter can be modified afterwards using,
|
||||
unitary function @ref LL_DMA2D_SetOutputColorMode(). */
|
||||
|
||||
uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
This parameter can be modified afterwards,
|
||||
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
function @ref LL_DMA2D_ConfigOutputColor(). */
|
||||
|
||||
uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
This parameter can be modified afterwards
|
||||
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
function @ref LL_DMA2D_ConfigOutputColor(). */
|
||||
|
||||
uint32_t OutputRed; /*!< Specifies the Red value of the output image.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
This parameter can be modified afterwards
|
||||
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
function @ref LL_DMA2D_ConfigOutputColor(). */
|
||||
|
||||
uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter is not considered if RGB888 or RGB565 color mode is selected.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
This parameter can be modified afterwards using,
|
||||
unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
function @ref LL_DMA2D_ConfigOutputColor(). */
|
||||
|
||||
uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
|
||||
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
|
||||
This parameter can be modified afterwards,
|
||||
using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
|
||||
|
||||
|
||||
|
||||
uint32_t LineOffset; /*!< Specifies the output line offset value.
|
||||
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
|
||||
This parameter can be modified afterwards,
|
||||
using unitary function @ref LL_DMA2D_SetLineOffset(). */
|
||||
|
||||
uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
|
||||
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x0000 and Max_Data = 0xFFFF.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
|
||||
This parameter can be modified afterwards,
|
||||
using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
|
||||
|
||||
uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transfered.
|
||||
uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred.
|
||||
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
|
||||
This parameter can be modified afterwards using,
|
||||
unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
|
||||
|
||||
|
||||
} LL_DMA2D_InitTypeDef;
|
||||
|
@ -143,7 +173,8 @@ typedef struct
|
|||
typedef struct
|
||||
{
|
||||
uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
|
||||
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
|
||||
|
||||
This parameter can be modified afterwards using unitary functions
|
||||
- @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
|
||||
|
@ -213,7 +244,8 @@ typedef struct
|
|||
- @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
|
||||
|
||||
uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
|
||||
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
|
||||
|
||||
This parameter can be modified afterwards using unitary functions
|
||||
- @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
|
||||
|
@ -231,45 +263,68 @@ typedef struct
|
|||
uint32_t ColorMode; /*!< Specifies the color format of the output image.
|
||||
- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
|
||||
This parameter can be modified afterwards using
|
||||
unitary function @ref LL_DMA2D_SetOutputColorMode(). */
|
||||
|
||||
uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
This parameter can be modified afterwards using,
|
||||
unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
function @ref LL_DMA2D_ConfigOutputColor(). */
|
||||
|
||||
uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
This parameter can be modified afterwards,
|
||||
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
function @ref LL_DMA2D_ConfigOutputColor(). */
|
||||
|
||||
uint32_t OutputRed; /*!< Specifies the Red value of the output image.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
This parameter can be modified afterwards,
|
||||
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
function @ref LL_DMA2D_ConfigOutputColor(). */
|
||||
|
||||
uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter is not considered if RGB888 or RGB565 color mode is selected.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
This parameter can be modified afterwards,
|
||||
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
function @ref LL_DMA2D_ConfigOutputColor(). */
|
||||
|
||||
} LL_DMA2D_ColorTypeDef;
|
||||
|
@ -357,9 +412,11 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
|
||||
#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by programmed alpha value */
|
||||
#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by programmed alpha value
|
||||
with original alpha channel value */
|
||||
#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by
|
||||
programmed alpha value */
|
||||
#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by
|
||||
programmed alpha value with,
|
||||
original alpha channel value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -493,7 +493,7 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FMC_Access_Mode FMC Access Mode
|
||||
* @{
|
||||
*/
|
||||
|
|
|
@ -361,11 +361,11 @@ typedef struct
|
|||
* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
|
||||
*/
|
||||
#define __LL_FMPI2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
|
||||
((((uint32_t)(__PRESCALER__) << FMPI2C_TIMINGR_PRESC_Pos) & FMPI2C_TIMINGR_PRESC) | \
|
||||
(((uint32_t)(__DATA_SETUP_TIME__) << FMPI2C_TIMINGR_SCLDEL_Pos) & FMPI2C_TIMINGR_SCLDEL) | \
|
||||
(((uint32_t)(__DATA_HOLD_TIME__) << FMPI2C_TIMINGR_SDADEL_Pos) & FMPI2C_TIMINGR_SDADEL) | \
|
||||
(((uint32_t)(__CLOCK_HIGH_PERIOD__) << FMPI2C_TIMINGR_SCLH_Pos) & FMPI2C_TIMINGR_SCLH) | \
|
||||
(((uint32_t)(__CLOCK_LOW_PERIOD__) << FMPI2C_TIMINGR_SCLL_Pos) & FMPI2C_TIMINGR_SCLL))
|
||||
((((uint32_t)(__PRESCALER__) << FMPI2C_TIMINGR_PRESC_Pos) & FMPI2C_TIMINGR_PRESC) | \
|
||||
(((uint32_t)(__DATA_SETUP_TIME__) << FMPI2C_TIMINGR_SCLDEL_Pos) & FMPI2C_TIMINGR_SCLDEL) | \
|
||||
(((uint32_t)(__DATA_HOLD_TIME__) << FMPI2C_TIMINGR_SDADEL_Pos) & FMPI2C_TIMINGR_SDADEL) | \
|
||||
(((uint32_t)(__CLOCK_HIGH_PERIOD__) << FMPI2C_TIMINGR_SCLH_Pos) & FMPI2C_TIMINGR_SCLH) | \
|
||||
(((uint32_t)(__CLOCK_LOW_PERIOD__) << FMPI2C_TIMINGR_SCLL_Pos) & FMPI2C_TIMINGR_SCLL))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -584,12 +584,12 @@ __STATIC_INLINE uint32_t LL_FMPI2C_DMA_GetRegAddr(FMPI2C_TypeDef *FMPI2Cx, uint3
|
|||
if (Direction == LL_FMPI2C_DMA_REG_DATA_TRANSMIT)
|
||||
{
|
||||
/* return address of TXDR register */
|
||||
data_reg_addr = (uint32_t) & (FMPI2Cx->TXDR);
|
||||
data_reg_addr = (uint32_t) &(FMPI2Cx->TXDR);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* return address of RXDR register */
|
||||
data_reg_addr = (uint32_t) & (FMPI2Cx->RXDR);
|
||||
data_reg_addr = (uint32_t) &(FMPI2Cx->RXDR);
|
||||
}
|
||||
|
||||
return data_reg_addr;
|
||||
|
@ -1125,7 +1125,7 @@ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx, uint32_
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
|
||||
* @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
|
||||
* @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the FMPI2Cx Instance.
|
||||
* @rmtoll TIMEOUTR TIMEOUTB LL_FMPI2C_GetSMBusTimeoutB
|
||||
|
@ -2052,7 +2052,9 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx)
|
|||
__STATIC_INLINE void LL_FMPI2C_HandleTransfer(FMPI2C_TypeDef *FMPI2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
|
||||
uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
|
||||
{
|
||||
MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_SADD | FMPI2C_CR2_ADD10 | (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_RELOAD |
|
||||
MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_SADD | FMPI2C_CR2_ADD10 |
|
||||
(FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) |
|
||||
FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_RELOAD |
|
||||
FMPI2C_CR2_NBYTES | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_HEAD10R,
|
||||
SlaveAddr | SlaveAddrSize | (TransferSize << FMPI2C_CR2_NBYTES_Pos) | EndMode | Request);
|
||||
}
|
||||
|
@ -2119,7 +2121,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPECCompare(FMPI2C_TypeDef *FMPI
|
|||
* @rmtoll PECR PEC LL_FMPI2C_GetSMBusPEC
|
||||
* @param FMPI2Cx FMPI2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(FMPI2Cx->PECR, FMPI2C_PECR_PEC));
|
||||
|
|
|
@ -939,7 +939,8 @@ __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMas
|
|||
*/
|
||||
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
|
||||
uint32_t odr = READ_REG(GPIOx->ODR);
|
||||
WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -1468,7 +1468,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Indicate the status of General call address reception (Slave mode).
|
||||
* @note RESET: No Generall call address
|
||||
* @note RESET: No General call address
|
||||
* SET: General call address received.
|
||||
* @note This status is cleared by hardware after a STOP condition or repeated START condition.
|
||||
* @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
|
||||
|
|
|
@ -236,7 +236,6 @@ __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
|
|||
return (READ_REG(IWDGx->RLR));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -283,7 +282,6 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
|
|||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -155,7 +155,7 @@ typedef struct
|
|||
/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
|
||||
* @{
|
||||
*/
|
||||
#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
|
||||
#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
|
||||
#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
|
||||
/**
|
||||
* @}
|
||||
|
@ -258,7 +258,6 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined(LPTIM_OR_OR)
|
||||
|
||||
/** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
|
||||
* @{
|
||||
|
@ -270,7 +269,6 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* LPTIM_OR_OR */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -620,7 +618,6 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
|
|||
{
|
||||
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
|
||||
}
|
||||
#if defined(LPTIM_OR_OR)
|
||||
|
||||
/**
|
||||
* @brief Set LPTIM input 1 source (default GPIO).
|
||||
|
@ -637,7 +634,6 @@ __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
|
|||
{
|
||||
MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src);
|
||||
}
|
||||
#endif /* LPTIM_OR_OR */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
@ -5338,7 +5338,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
|
|||
*/
|
||||
__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
|
||||
{
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
|
||||
MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
|
||||
#if defined(RCC_PLLI2SCFGR_PLLI2SM)
|
||||
MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
|
||||
|
@ -5458,7 +5458,7 @@ __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PL
|
|||
*/
|
||||
__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
|
||||
{
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
|
||||
MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
|
||||
#if defined(RCC_PLLI2SCFGR_PLLI2SM)
|
||||
MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
|
||||
|
@ -5662,7 +5662,7 @@ __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_
|
|||
*/
|
||||
__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
|
||||
{
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
|
||||
MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
|
||||
#if defined(RCC_PLLI2SCFGR_PLLI2SM)
|
||||
MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
|
||||
|
@ -5924,9 +5924,9 @@ __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)
|
|||
__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)
|
||||
{
|
||||
#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
|
||||
register uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
|
||||
register uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
|
||||
register uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
|
||||
uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
|
||||
uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
|
||||
uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
|
||||
return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1);
|
||||
#else
|
||||
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
|
||||
|
|
|
@ -301,7 +301,9 @@ typedef struct
|
|||
#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
|
||||
#define SDMMC_CARD_LOCKED 0x02000000U
|
||||
|
||||
#ifndef SDMMC_DATATIMEOUT
|
||||
#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
|
||||
#endif /* SDMMC_DATATIMEOUT */
|
||||
|
||||
#define SDMMC_0TO7BITS 0x000000FFU
|
||||
#define SDMMC_8TO15BITS 0x0000FF00U
|
||||
|
@ -455,7 +457,7 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_LL_Data_Length Data Lenght
|
||||
/** @defgroup SDIO_LL_Data_Length Data Length
|
||||
* @{
|
||||
*/
|
||||
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
|
||||
|
@ -1089,6 +1091,7 @@ uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
|
|||
uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
|
||||
uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
|
||||
uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
|
||||
uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
|
||||
uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA);
|
||||
uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
|
||||
uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
|
||||
|
|
|
@ -710,8 +710,8 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
|
||||
{
|
||||
register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
|
||||
register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
|
||||
uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
|
||||
uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
|
||||
return (Ssm | Ssoe);
|
||||
}
|
||||
|
||||
|
@ -1242,10 +1242,10 @@ typedef struct
|
|||
/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
|
||||
* @{
|
||||
*/
|
||||
#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
|
||||
#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
|
||||
#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
|
||||
#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
|
||||
#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */
|
||||
#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */
|
||||
#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */
|
||||
#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -1580,7 +1580,7 @@ __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the master clock ouput (Pin MCK)
|
||||
* @brief Enable the master clock output (Pin MCK)
|
||||
* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
|
||||
* @param SPIx SPI Instance
|
||||
* @retval None
|
||||
|
@ -1591,7 +1591,7 @@ __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the master clock ouput (Pin MCK)
|
||||
* @brief Disable the master clock output (Pin MCK)
|
||||
* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
|
||||
* @param SPIx SPI Instance
|
||||
* @retval None
|
||||
|
@ -1602,7 +1602,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the master clock ouput (Pin MCK) is enabled
|
||||
* @brief Check if the master clock output (Pin MCK) is enabled
|
||||
* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
|
|
|
@ -204,13 +204,14 @@ typedef struct
|
|||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
|
||||
|
||||
uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
|
||||
uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
|
||||
reaches zero, an update event is generated and counting restarts
|
||||
from the RCR value (N).
|
||||
This means in PWM mode that (N+1) corresponds to:
|
||||
- the number of PWM periods in edge-aligned mode
|
||||
- the number of half PWM period in center-aligned mode
|
||||
This parameter must be a number between 0x00 and 0xFF.
|
||||
GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
|
||||
Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
|
||||
} LL_TIM_InitTypeDef;
|
||||
|
@ -507,8 +508,8 @@ typedef struct
|
|||
/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
|
||||
#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
|
||||
#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
|
||||
#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -518,8 +519,8 @@ typedef struct
|
|||
*/
|
||||
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
|
||||
#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
|
||||
/**
|
||||
* @}
|
||||
|
@ -902,14 +903,32 @@ typedef struct
|
|||
#define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /*!< TIM11 channel 1 is connected to GPIO */
|
||||
#if defined(SPDIFRX)
|
||||
#define LL_TIM_TIM11_TI1_RMP_SPDIFRX (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to SPDIFRX */
|
||||
|
||||
/* Legacy define */
|
||||
#define LL_TIM_TIM11_TI1_RMP_GPIO1 LL_TIM_TIM11_TI1_RMP_SPDIFRX /*!< Legacy define for LL_TIM_TIM11_TI1_RMP_SPDIFRX */
|
||||
|
||||
#else
|
||||
#define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */
|
||||
#endif
|
||||
#endif /* SPDIFRX */
|
||||
#define LL_TIM_TIM11_TI1_RMP_GPIO2 (TIM_OR_TI1_RMP | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */
|
||||
#define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1_RMP_1 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to HSE_RTC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP)
|
||||
|
||||
#define LL_TIM_LPTIM_REMAP_MASK 0x10000000U
|
||||
|
||||
#define LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO LL_TIM_LPTIM_REMAP_MASK /*!< TIM9_ITR1 is connected to TIM3 TRGO */
|
||||
#define LL_TIM_TIM9_ITR1_RMP_LPTIM (LL_TIM_LPTIM_REMAP_MASK | LPTIM_OR_TIM9_ITR1_RMP) /*!< TIM9_ITR1 is connected to LPTIM1 output */
|
||||
|
||||
#define LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO LL_TIM_LPTIM_REMAP_MASK /*!< TIM5_ITR1 is connected to TIM3 TRGO */
|
||||
#define LL_TIM_TIM5_ITR1_RMP_LPTIM (LL_TIM_LPTIM_REMAP_MASK | LPTIM_OR_TIM5_ITR1_RMP) /*!< TIM5_ITR1 is connected to LPTIM1 output */
|
||||
|
||||
#define LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO LL_TIM_LPTIM_REMAP_MASK /*!< TIM1_ITR2 is connected to TIM3 TRGO */
|
||||
#define LL_TIM_TIM1_ITR2_RMP_LPTIM (LL_TIM_LPTIM_REMAP_MASK | LPTIM_OR_TIM1_ITR2_RMP) /*!< TIM1_ITR2 is connected to LPTIM1 output */
|
||||
|
||||
#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -1210,7 +1229,16 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
|
||||
uint32_t counter_mode;
|
||||
|
||||
counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
|
||||
|
||||
if (counter_mode == 0U)
|
||||
{
|
||||
counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
|
||||
}
|
||||
|
||||
return counter_mode;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1383,7 +1411,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
|
|||
* whether or not a timer instance supports a repetition counter.
|
||||
* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
|
||||
* @param TIMx Timer instance
|
||||
* @param RepetitionCounter between Min_Data=0 and Max_Data=255
|
||||
* @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
|
||||
|
@ -1611,8 +1639,8 @@ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
|
||||
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
|
||||
(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
|
||||
|
@ -1646,8 +1674,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel,
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -1675,8 +1703,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -1705,7 +1733,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -1733,7 +1761,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -1766,7 +1794,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -1794,7 +1822,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel,
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -1815,8 +1843,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
|
||||
|
||||
}
|
||||
|
@ -1837,8 +1865,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
|
||||
|
||||
}
|
||||
|
@ -1859,9 +1887,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
|
||||
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
|
@ -1881,8 +1909,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
|
||||
}
|
||||
|
||||
|
@ -1902,8 +1930,8 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
|
||||
}
|
||||
|
||||
|
@ -1923,9 +1951,9 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
|
||||
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
|
@ -1948,8 +1976,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
|
||||
}
|
||||
|
||||
|
@ -1971,8 +1999,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
|
||||
}
|
||||
|
||||
|
@ -1996,9 +2024,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
|
||||
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
|
@ -2193,8 +2221,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
|
||||
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
|
||||
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
|
||||
|
@ -2221,8 +2249,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -2245,8 +2273,8 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
|
||||
}
|
||||
|
||||
|
@ -2271,8 +2299,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -2296,8 +2324,8 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel,
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
|
||||
}
|
||||
|
||||
|
@ -2334,8 +2362,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -2371,8 +2399,8 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
|
||||
}
|
||||
|
||||
|
@ -2400,7 +2428,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
|
||||
ICPolarity << SHIFT_TAB_CCxP[iChannel]);
|
||||
}
|
||||
|
@ -2428,7 +2456,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
|
||||
SHIFT_TAB_CCxP[iChannel]);
|
||||
}
|
||||
|
@ -3006,9 +3034,13 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB
|
|||
* @brief Remap TIM inputs (input channel, internal/external triggers).
|
||||
* @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
|
||||
* a some timer inputs can be remapped.
|
||||
* @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
|
||||
* @rmtoll TIM1_OR ITR2_RMP LL_TIM_SetRemap\n
|
||||
* TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
|
||||
* TIM5_OR ITR1_RMP LL_TIM_SetRemap\n
|
||||
* TIM5_OR TI4_RMP LL_TIM_SetRemap\n
|
||||
* TIM11_OR TI1_RMP LL_TIM_SetRemap
|
||||
* TIM9_OR ITR1_RMP LL_TIM_SetRemap\n
|
||||
* TIM11_OR TI1_RMP LL_TIM_SetRemap\n
|
||||
* LPTIM1_OR OR LL_TIM_SetRemap
|
||||
* @param TIMx Timer instance
|
||||
* @param Remap Remap param depends on the TIMx. Description available only
|
||||
* in CHM version of the User Manual (not in .pdf).
|
||||
|
@ -3016,6 +3048,12 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB
|
|||
*
|
||||
* Below description summarizes "Timer Instance" and "Remap" param combinations:
|
||||
*
|
||||
* TIM1: one of the following values
|
||||
*
|
||||
* ITR2_RMP can be one of the following values
|
||||
* @arg @ref LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO (*)
|
||||
* @arg @ref LL_TIM_TIM1_ITR2_RMP_LPTIM (*)
|
||||
*
|
||||
* TIM2: one of the following values
|
||||
*
|
||||
* ITR1_RMP can be one of the following values
|
||||
|
@ -3029,6 +3067,14 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB
|
|||
* @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
|
||||
* @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
|
||||
* @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
|
||||
* @arg @ref LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO (*)
|
||||
* @arg @ref LL_TIM_TIM5_ITR1_RMP_LPTIM (*)
|
||||
*
|
||||
* TIM9: one of the following values
|
||||
*
|
||||
* ITR1_RMP can be one of the following values
|
||||
* @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO (*)
|
||||
* @arg @ref LL_TIM_TIM9_ITR1_RMP_LPTIM (*)
|
||||
*
|
||||
* TIM11: one of the following values
|
||||
*
|
||||
|
@ -3044,7 +3090,22 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
|
||||
{
|
||||
#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP)
|
||||
if ((Remap & LL_TIM_LPTIM_REMAP_MASK) == LL_TIM_LPTIM_REMAP_MASK)
|
||||
{
|
||||
/* Connect TIMx internal trigger to LPTIM1 output */
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);
|
||||
MODIFY_REG(LPTIM1->OR,
|
||||
(LPTIM_OR_TIM1_ITR2_RMP | LPTIM_OR_TIM5_ITR1_RMP | LPTIM_OR_TIM9_ITR1_RMP),
|
||||
Remap & ~(LL_TIM_LPTIM_REMAP_MASK));
|
||||
}
|
||||
else
|
||||
{
|
||||
MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
|
||||
}
|
||||
#else
|
||||
MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
|
||||
#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -1043,8 +1043,8 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
|
||||
{
|
||||
register uint32_t usartdiv = 0x0U;
|
||||
register uint32_t brrresult = 0x0U;
|
||||
uint32_t usartdiv = 0x0U;
|
||||
uint32_t brrresult = 0x0U;
|
||||
|
||||
usartdiv = USARTx->BRR;
|
||||
|
||||
|
|
|
@ -186,6 +186,8 @@ typedef struct
|
|||
|
||||
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
|
||||
|
||||
uint32_t XferSize; /*!< OTG Channel transfer size. */
|
||||
|
||||
uint32_t xfer_len; /*!< Current transfer length. */
|
||||
|
||||
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
|
||||
|
|
|
@ -279,6 +279,7 @@ void LL_mDelay(uint32_t Delay);
|
|||
*/
|
||||
|
||||
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
|
||||
ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
|
||||
|
|
|
@ -50,11 +50,11 @@
|
|||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief STM32F4xx HAL Driver version number V1.7.10
|
||||
* @brief STM32F4xx HAL Driver version number V1.7.11
|
||||
*/
|
||||
#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
|
||||
#define __STM32F4xx_HAL_VERSION_SUB2 (0x0AU) /*!< [15:8] sub2 version */
|
||||
#define __STM32F4xx_HAL_VERSION_SUB2 (0x0BU) /*!< [15:8] sub2 version */
|
||||
#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
|
||||
|(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
* @file stm32f4xx_hal_adc.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
|
||||
* functionalities of the Analog to Digital Converter (ADC) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
* + State and errors functions
|
||||
|
@ -814,6 +814,14 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
|
|||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Set ADC error code to ADC IP internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
@ -905,13 +913,17 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
|
|||
{
|
||||
if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
|
||||
{
|
||||
/* Update ADC state machine to timeout */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
|
||||
{
|
||||
/* Update ADC state machine to timeout */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -976,13 +988,17 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
|
|||
{
|
||||
if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
|
||||
{
|
||||
/* Update ADC state machine to timeout */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
|
||||
{
|
||||
/* Update ADC state machine to timeout */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -1122,6 +1138,14 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
|
|||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Set ADC error code to ADC IP internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
@ -1364,6 +1388,13 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
|
|||
}
|
||||
}
|
||||
|
||||
/* Check ADC DMA Mode */
|
||||
/* - disable the DMA Mode if it is already enabled */
|
||||
if((hadc->Instance->CR2 & ADC_CR2_DMA) == ADC_CR2_DMA)
|
||||
{
|
||||
CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
|
||||
}
|
||||
|
||||
/* Start conversion if ADC is effectively enabled */
|
||||
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
|
||||
{
|
||||
|
@ -1457,6 +1488,14 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
|
|||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Set ADC error code to ADC IP internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
@ -1490,7 +1529,17 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
|
|||
|
||||
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
|
||||
/* DMA transfer is on going) */
|
||||
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
|
||||
if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
|
||||
{
|
||||
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
|
||||
|
||||
/* Check if DMA channel effectively disabled */
|
||||
if (tmp_hal_status != HAL_OK)
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable ADC overrun interrupt */
|
||||
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
|
||||
|
|
|
@ -227,6 +227,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
|
|||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Set ADC error code to ADC IP internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
@ -325,6 +333,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
|
|||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Set ADC error code to ADC IP internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
@ -411,10 +427,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
|
|||
{
|
||||
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
|
||||
{
|
||||
hadc->State= HAL_ADC_STATE_TIMEOUT;
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
return HAL_TIMEOUT;
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
|
||||
{
|
||||
hadc->State= HAL_ADC_STATE_TIMEOUT;
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -684,6 +704,14 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
|
|||
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Set ADC error code to ADC IP internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
|
|
@ -120,7 +120,7 @@
|
|||
submitted (the sleep mode is not yet entered), and become
|
||||
HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective.
|
||||
|
||||
(#) The wake-up from sleep mode can be trigged by two ways:
|
||||
(#) The wake-up from sleep mode can be triggered by two ways:
|
||||
(++) Using HAL_CAN_WakeUp(). When returning from this function,
|
||||
the sleep mode is exited (if return status is HAL_OK).
|
||||
(++) When a start of Rx CAN frame is detected by the CAN peripheral,
|
||||
|
@ -537,19 +537,19 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
|
|||
* the configuration information for CAN module
|
||||
* @param CallbackID ID of the callback to be registered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID
|
||||
* @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID
|
||||
* @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID
|
||||
* @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID
|
||||
* @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID
|
||||
* @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID
|
||||
* @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID
|
||||
* @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID
|
||||
* @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID
|
||||
* @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID
|
||||
* @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID
|
||||
* @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID
|
||||
* @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID
|
||||
* @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID
|
||||
* @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID
|
||||
* @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @param pCallback pointer to the Callback function
|
||||
|
@ -680,19 +680,19 @@ HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Call
|
|||
* the configuration information for CAN module
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID
|
||||
* @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID
|
||||
* @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID
|
||||
* @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID
|
||||
* @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID
|
||||
* @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID
|
||||
* @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID
|
||||
* @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID
|
||||
* @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID
|
||||
* @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID
|
||||
* @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID
|
||||
* @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID
|
||||
* @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID
|
||||
* @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID
|
||||
* @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID
|
||||
* @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID
|
||||
* @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @retval HAL status
|
||||
|
@ -1901,7 +1901,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
|
|||
/* Check if message is still pending */
|
||||
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
|
||||
{
|
||||
/* Receive FIFO 0 mesage pending Callback */
|
||||
/* Receive FIFO 0 message pending Callback */
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
/* Call registered callback*/
|
||||
hcan->RxFifo0MsgPendingCallback(hcan);
|
||||
|
@ -1950,7 +1950,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
|
|||
/* Check if message is still pending */
|
||||
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
|
||||
{
|
||||
/* Receive FIFO 1 mesage pending Callback */
|
||||
/* Receive FIFO 1 message pending Callback */
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
/* Call registered callback*/
|
||||
hcan->RxFifo1MsgPendingCallback(hcan);
|
||||
|
|
|
@ -822,19 +822,15 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
|
|||
/* CEC TX byte request interrupt ------------------------------------------------*/
|
||||
if ((reg & CEC_FLAG_TXBR) != 0U)
|
||||
{
|
||||
--hcec->TxXferCount;
|
||||
if (hcec->TxXferCount == 0U)
|
||||
{
|
||||
/* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
|
||||
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
|
||||
hcec->Instance->TXDR = *hcec->pTxBuffPtr;
|
||||
hcec->pTxBuffPtr++;
|
||||
}
|
||||
else
|
||||
{
|
||||
hcec->Instance->TXDR = *hcec->pTxBuffPtr;
|
||||
hcec->pTxBuffPtr++;
|
||||
hcec->TxXferCount--;
|
||||
}
|
||||
/* In all cases transmit the byte */
|
||||
hcec->Instance->TXDR = *hcec->pTxBuffPtr;
|
||||
hcec->pTxBuffPtr++;
|
||||
/* clear Tx-Byte request flag */
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
|
||||
}
|
||||
|
|
|
@ -586,6 +586,8 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD
|
|||
hcryp->Init.HeaderSize = pConf->HeaderSize;
|
||||
hcryp->Init.B0 = pConf->B0;
|
||||
hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
|
||||
hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
|
||||
hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
|
||||
|
||||
/* Set the key size(This bit field is don’t care in the DES or TDES modes) data type, AlgoMode and operating mode*/
|
||||
#if defined (CRYP)
|
||||
|
@ -660,7 +662,9 @@ HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD
|
|||
pConf->Header = hcryp->Init.Header ;
|
||||
pConf->HeaderSize = hcryp->Init.HeaderSize;
|
||||
pConf->B0 = hcryp->Init.B0;
|
||||
pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
|
||||
pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
|
||||
pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
|
||||
pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hcryp);
|
||||
|
@ -692,8 +696,8 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
|
|||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcryp);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_MspInit could be implemented in the user file
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_MspInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
@ -708,8 +712,8 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
|
|||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcryp);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_MspDeInit could be implemented in the user file
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_MspDeInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
@ -2157,8 +2161,8 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
|
|||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcryp);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_InCpltCallback could be implemented in the user file
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_InCpltCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
@ -2173,8 +2177,8 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
|
|||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcryp);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_OutCpltCallback could be implemented in the user file
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_OutCpltCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
@ -5540,17 +5544,17 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
|
|||
hcryp->CrypInCount++;
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
|
||||
hcryp->CrypInCount++;
|
||||
if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
|
||||
{
|
||||
/* Call Input transfer complete callback */
|
||||
if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
|
||||
{
|
||||
/* Call Input transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
#else
|
||||
/*Call legacy weak Input complete callback*/
|
||||
HAL_CRYP_InCpltCallback(hcryp);
|
||||
/*Call legacy weak Input complete callback*/
|
||||
HAL_CRYP_InCpltCallback(hcryp);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
}
|
||||
else /* Last block of payload < 128bit*/
|
||||
{
|
||||
|
@ -5599,10 +5603,24 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
|
|||
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
|
||||
{
|
||||
uint32_t loopcounter;
|
||||
uint32_t size_in_bytes;
|
||||
uint32_t tmp;
|
||||
uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
|
||||
0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
|
||||
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
|
||||
|
||||
/***************************** Header phase for GCM/GMAC or CCM *********************************/
|
||||
|
||||
if ((hcryp->Init.HeaderSize != 0U))
|
||||
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
|
||||
{
|
||||
size_in_bytes = hcryp->Init.HeaderSize * 4U;
|
||||
}
|
||||
else
|
||||
{
|
||||
size_in_bytes = hcryp->Init.HeaderSize;
|
||||
}
|
||||
|
||||
if (size_in_bytes != 0U)
|
||||
{
|
||||
|
||||
#if defined(CRYP)
|
||||
|
@ -5613,10 +5631,10 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
|
|||
/* Enable the CRYP peripheral */
|
||||
__HAL_CRYP_ENABLE(hcryp);
|
||||
|
||||
if ((hcryp->Init.HeaderSize % 4U) == 0U)
|
||||
if ((size_in_bytes % 16U) == 0U)
|
||||
{
|
||||
/* HeaderSize %4, no padding */
|
||||
for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
|
||||
for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
|
@ -5646,7 +5664,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
|
|||
else
|
||||
{
|
||||
/*Write header block in the IN FIFO without last block */
|
||||
for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
|
||||
for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
|
@ -5673,16 +5691,34 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
|
|||
}
|
||||
}
|
||||
/* Last block optionally pad the data with zeros*/
|
||||
for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
|
||||
for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
|
||||
{
|
||||
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
}
|
||||
while (loopcounter < 4U)
|
||||
/* If the header size is a multiple of words */
|
||||
if ((size_in_bytes % 4U) == 0U)
|
||||
{
|
||||
/* pad the data with zeros to have a complete block */
|
||||
hcryp->Instance->DIN = 0x0U;
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enter last bytes, padded with zeroes */
|
||||
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
|
||||
hcryp->Instance->DIN = tmp;
|
||||
loopcounter++;
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
/* Wait for CCF IFEM to be raised */
|
||||
if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
|
||||
|
@ -5728,10 +5764,11 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
|
|||
__HAL_CRYP_ENABLE(hcryp);
|
||||
|
||||
}
|
||||
if ((hcryp->Init.HeaderSize % 4U) == 0U)
|
||||
/* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */
|
||||
if ((size_in_bytes % 16U) == 0U)
|
||||
{
|
||||
/* HeaderSize %4, no padding */
|
||||
for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
|
||||
/* No padding */
|
||||
for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
|
||||
{
|
||||
/* Write the input block in the data input register */
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
|
@ -5763,7 +5800,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
|
|||
else
|
||||
{
|
||||
/*Write header block in the IN FIFO without last block */
|
||||
for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
|
||||
for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
|
||||
{
|
||||
/* Write the input block in the data input register */
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
|
@ -5791,17 +5828,35 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
|
|||
/* Clear CCF flag */
|
||||
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
|
||||
}
|
||||
/* Last block optionally pad the data with zeros*/
|
||||
for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
|
||||
/* Write last complete words */
|
||||
for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
|
||||
{
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
}
|
||||
while (loopcounter < 4U)
|
||||
/* If the header size is a multiple of words */
|
||||
if ((size_in_bytes % 4U) == 0U)
|
||||
{
|
||||
/*Pad the data with zeros to have a complete block */
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enter last bytes, padded with zeroes */
|
||||
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
|
||||
hcryp->Instance->DINR = tmp;
|
||||
loopcounter++;
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
|
||||
if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
|
||||
|
@ -5852,9 +5907,23 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
|
|||
{
|
||||
__IO uint32_t count = 0U;
|
||||
uint32_t loopcounter;
|
||||
uint32_t headersize_in_bytes;
|
||||
uint32_t tmp;
|
||||
uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
|
||||
0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
|
||||
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
|
||||
|
||||
/***************************** Header phase for GCM/GMAC or CCM *********************************/
|
||||
if ((hcryp->Init.HeaderSize != 0U))
|
||||
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
|
||||
{
|
||||
headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
|
||||
}
|
||||
else
|
||||
{
|
||||
headersize_in_bytes = hcryp->Init.HeaderSize;
|
||||
}
|
||||
|
||||
if (headersize_in_bytes != 0U)
|
||||
{
|
||||
|
||||
#if defined(CRYP)
|
||||
|
@ -5865,10 +5934,10 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
|
|||
/* Enable the CRYP peripheral */
|
||||
__HAL_CRYP_ENABLE(hcryp);
|
||||
|
||||
if ((hcryp->Init.HeaderSize % 4U) == 0U)
|
||||
if ((headersize_in_bytes % 16U) == 0U)
|
||||
{
|
||||
/* HeaderSize %4, no padding */
|
||||
for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
|
||||
for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
|
@ -5903,7 +5972,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
|
|||
else
|
||||
{
|
||||
/*Write header block in the IN FIFO without last block */
|
||||
for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
|
||||
for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
|
@ -5935,16 +6004,34 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
|
|||
} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
|
||||
}
|
||||
/* Last block optionally pad the data with zeros*/
|
||||
for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
|
||||
for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
|
||||
{
|
||||
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
}
|
||||
while (loopcounter < 4U)
|
||||
/* If the header size is a multiple of words */
|
||||
if ((headersize_in_bytes % 4U) == 0U)
|
||||
{
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
hcryp->Instance->DIN = 0x0U;
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enter last bytes, padded with zeroes */
|
||||
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
|
||||
hcryp->Instance->DIN = tmp;
|
||||
loopcounter++;
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
/* Wait for IFEM to be raised */
|
||||
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
|
||||
|
@ -5999,10 +6086,10 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
|
|||
/* Enable the CRYP peripheral */
|
||||
__HAL_CRYP_ENABLE(hcryp);
|
||||
}
|
||||
if ((hcryp->Init.HeaderSize % 4U) == 0U)
|
||||
if ((headersize_in_bytes % 16U) == 0U)
|
||||
{
|
||||
/* HeaderSize %4, no padding */
|
||||
for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
|
||||
for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U)
|
||||
{
|
||||
/* Write the input block in the data input register */
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
|
@ -6041,7 +6128,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
|
|||
else
|
||||
{
|
||||
/*Write header block in the IN FIFO without last block */
|
||||
for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
|
||||
for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
|
||||
{
|
||||
/* Write the Input block in the Data Input register */
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
|
@ -6077,18 +6164,35 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
|
|||
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
|
||||
}
|
||||
/* Last block optionally pad the data with zeros*/
|
||||
for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
|
||||
for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes /4U) % 4U)); loopcounter++)
|
||||
{
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
}
|
||||
while (loopcounter < 4U)
|
||||
/* If the header size is a multiple of words */
|
||||
if ((headersize_in_bytes % 4U) == 0U)
|
||||
{
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enter last bytes, padded with zeroes */
|
||||
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
|
||||
hcryp->Instance->DINR = tmp;
|
||||
loopcounter++;
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
|
||||
/*Wait on CCF flag*/
|
||||
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
|
||||
do
|
||||
|
@ -6147,10 +6251,25 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
|
|||
uint32_t lastwordsize;
|
||||
uint32_t npblb;
|
||||
#endif
|
||||
uint32_t headersize_in_bytes;
|
||||
uint32_t tmp;
|
||||
uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
|
||||
0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
|
||||
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
|
||||
|
||||
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
|
||||
{
|
||||
headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
|
||||
}
|
||||
else
|
||||
{
|
||||
headersize_in_bytes = hcryp->Init.HeaderSize;
|
||||
}
|
||||
|
||||
/***************************** Header phase *********************************/
|
||||
|
||||
#if defined(CRYP)
|
||||
if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
|
||||
if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
|
||||
{
|
||||
/* Disable interrupts */
|
||||
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
|
||||
|
@ -6170,7 +6289,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
|
|||
/* Enable the CRYP peripheral */
|
||||
__HAL_CRYP_ENABLE(hcryp);
|
||||
}
|
||||
else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
|
||||
else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)
|
||||
|
||||
{
|
||||
/* HeaderSize %4, no padding */
|
||||
|
@ -6186,21 +6305,41 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
|
|||
else
|
||||
{
|
||||
/* Last block optionally pad the data with zeros*/
|
||||
for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
|
||||
for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++)
|
||||
{
|
||||
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
}
|
||||
while (loopcounter < 4U)
|
||||
if ((headersize_in_bytes % 4U) == 0U)
|
||||
{
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = 0x0U;
|
||||
loopcounter++;
|
||||
hcryp->CrypHeaderCount++;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enter last bytes, padded with zeros */
|
||||
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
|
||||
hcryp->Instance->DIN = tmp;
|
||||
loopcounter++;
|
||||
hcryp->CrypHeaderCount++;
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = 0x0U;
|
||||
loopcounter++;
|
||||
hcryp->CrypHeaderCount++;
|
||||
}
|
||||
}
|
||||
}
|
||||
#else /* AES */
|
||||
|
||||
if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
|
||||
if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
|
||||
{
|
||||
/* Set the phase */
|
||||
hcryp->Phase = CRYP_PHASE_PROCESS;
|
||||
|
@ -6284,7 +6423,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
|
|||
}
|
||||
}
|
||||
}
|
||||
else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
|
||||
else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)
|
||||
{
|
||||
/* Write the input block in the IN FIFO */
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
|
@ -6299,16 +6438,37 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
|
|||
else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
|
||||
{
|
||||
/* Last block optionally pad the data with zeros*/
|
||||
for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
|
||||
for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++)
|
||||
{
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
}
|
||||
/* If the header size is a multiple of words */
|
||||
if ((headersize_in_bytes % 4U) == 0U)
|
||||
{
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
hcryp->CrypHeaderCount++;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enter last bytes, padded with zeros */
|
||||
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
|
||||
hcryp->Instance->DINR = tmp;
|
||||
loopcounter++;
|
||||
hcryp->CrypHeaderCount++;
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
/* pad the data with zeros to have a complete block */
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
hcryp->CrypHeaderCount++;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* End AES or CRYP */
|
||||
|
|
|
@ -128,10 +128,17 @@
|
|||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
/* Assume first Init.HeaderSize is in words */
|
||||
uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */
|
||||
uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */
|
||||
uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */
|
||||
uint32_t tagaddr = (uint32_t)AuthTag;
|
||||
|
||||
/* Correct headerlength if Init.HeaderSize is actually in bytes */
|
||||
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
|
||||
{
|
||||
headerlength /= 4U;
|
||||
}
|
||||
|
||||
if (hcryp->State == HAL_CRYP_STATE_READY)
|
||||
{
|
||||
/* Process locked */
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -2,10 +2,9 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_dac_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief DAC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of DAC extension peripheral:
|
||||
* + Extended features functions
|
||||
* @brief Extended DAC HAL module driver.
|
||||
* This file provides firmware functions to manage the extended
|
||||
* functionalities of the DAC peripheral.
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
|
@ -13,9 +12,18 @@
|
|||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
|
||||
|
||||
*** Dual mode IO operation ***
|
||||
==============================
|
||||
[..]
|
||||
(+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
|
||||
Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
|
||||
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
|
||||
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
|
||||
Channel 1 and Channel 2.
|
||||
|
||||
*** Signal generation operation ***
|
||||
===================================
|
||||
[..]
|
||||
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
|
||||
(+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
|
||||
|
||||
|
@ -23,7 +31,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
|
@ -42,31 +50,29 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
|
||||
#if defined(DAC)
|
||||
|
||||
/** @defgroup DACEx DACEx
|
||||
* @brief DAC driver modules
|
||||
* @brief DAC Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
|
||||
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
|
||||
defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
|
||||
defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Exported_Functions DAC Exported Functions
|
||||
|
||||
/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
*
|
||||
/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
|
||||
* @brief Extended IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Extended features functions #####
|
||||
|
@ -83,31 +89,80 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @brief Enables DAC and starts conversion of both channels.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval The selected DAC channel data output value.
|
||||
* @retval HAL status
|
||||
*/
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
uint32_t tmp_swtrig = 0UL;
|
||||
|
||||
tmp |= hdac->Instance->DOR1;
|
||||
|
||||
tmp |= hdac->Instance->DOR2 << 16U;
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
return tmp;
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
|
||||
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
|
||||
|
||||
/* Check if software trigger enabled */
|
||||
if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
|
||||
{
|
||||
tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
|
||||
}
|
||||
if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)))
|
||||
{
|
||||
tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
|
||||
}
|
||||
/* Enable the selected DAC software conversion*/
|
||||
SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @brief Disables DAC and stop conversion of both channels.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
|
||||
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the selected DAC channel wave generation.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* DAC_CHANNEL_1 / DAC_CHANNEL_2
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @param Amplitude Select max triangle amplitude.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
|
||||
|
@ -124,7 +179,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
|
|||
* @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
@ -136,8 +191,9 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32
|
|||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the selected wave generation for the selected DAC channel */
|
||||
MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
|
||||
/* Enable the triangle wave generation for the selected DAC channel */
|
||||
MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
|
||||
(DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
@ -150,12 +206,13 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @brief Enable or disable the selected DAC channel wave generation.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* DAC_CHANNEL_1 / DAC_CHANNEL_2
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @param Amplitude Unmask DAC channel LFSR for noise wave generation.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
|
||||
|
@ -172,7 +229,7 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32
|
|||
* @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
@ -184,8 +241,9 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
|
|||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the selected wave generation for the selected DAC channel */
|
||||
MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
|
||||
/* Enable the noise wave generation for the selected DAC channel */
|
||||
MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
|
||||
(DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
@ -197,6 +255,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
/**
|
||||
* @brief Set the specified data holding register value for dual DAC channel.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
|
@ -206,15 +265,16 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
|
|||
* DAC_ALIGN_8B_R: 8bit right data alignment selected
|
||||
* DAC_ALIGN_12B_L: 12bit left data alignment selected
|
||||
* DAC_ALIGN_12B_R: 12bit right data alignment selected
|
||||
* @param Data1 Data for DAC Channel2 to be loaded in the selected data holding register.
|
||||
* @param Data2 Data for DAC Channel1 to be loaded in the selected data holding register.
|
||||
* @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
|
||||
* @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register.
|
||||
* @note In dual mode, a unique register access is required to write in both
|
||||
* DAC channels at the same time.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
|
||||
{
|
||||
uint32_t data = 0U, tmp = 0U;
|
||||
uint32_t data;
|
||||
uint32_t tmp;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(Alignment));
|
||||
|
@ -242,36 +302,34 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align
|
|||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Conversion complete callback in non blocking mode for Channel2
|
||||
* @brief Conversion complete callback in non-blocking mode for Channel2.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
|
||||
__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ConvCpltCallback could be implemented in the user file
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Conversion half DMA transfer callback in non blocking mode for Channel2
|
||||
* @brief Conversion half DMA transfer callback in non-blocking mode for Channel2.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
|
||||
__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ConvHalfCpltCallbackCh2 could be implemented in the user file
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
@ -285,13 +343,14 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
|
|||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ErrorCallback could be implemented in the user file
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA underrun DAC callback for channel2.
|
||||
* @brief DMA underrun DAC callback for Channel2.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
|
@ -300,11 +359,66 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
|
|||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Set the specified data holding register value for DAC channel.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
/**
|
||||
* @brief Return the last data output value of the selected DAC channel.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
uint32_t tmp = 0UL;
|
||||
|
||||
tmp |= hdac->Instance->DOR1;
|
||||
|
||||
tmp |= hdac->Instance->DOR2 << 16UL;
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
return tmp;
|
||||
}
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Private_Functions DACEx private functions
|
||||
* @brief Extended private functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
/**
|
||||
* @brief DMA conversion complete callback.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
|
@ -313,7 +427,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
|
|||
*/
|
||||
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
hdac->ConvCpltCallbackCh2(hdac);
|
||||
|
@ -321,7 +435,7 @@ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
|
|||
HAL_DACEx_ConvCpltCallbackCh2(hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -332,24 +446,24 @@ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
|
|||
*/
|
||||
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
/* Conversion complete callback */
|
||||
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
||||
/* Conversion complete callback */
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
hdac->ConvHalfCpltCallbackCh2(hdac);
|
||||
#else
|
||||
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
|
||||
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA error callback
|
||||
* @brief DMA error callback.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
||||
|
||||
/* Set DAC error code to DMA error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
|
||||
|
@ -360,24 +474,22 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
|
|||
HAL_DACEx_ErrorCallbackCh2(hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
}
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
|
||||
STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
|
||||
STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx ||\
|
||||
STM32F413xx || STM32F423xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DAC */
|
||||
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -106,7 +106,7 @@
|
|||
When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registering feature is not available
|
||||
and weak (surcharged) callbacks are used.
|
||||
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
@ -959,7 +959,7 @@ HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_
|
|||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -1037,7 +1037,7 @@ HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCM
|
|||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
|
@ -102,7 +102,27 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
|
|||
#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
|
||||
if(hdcmi->State == HAL_DCMI_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hdcmi->Lock = HAL_UNLOCKED;
|
||||
/* Init the low level hardware */
|
||||
/* Init the DCMI Callback settings */
|
||||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
|
||||
hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
|
||||
hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
|
||||
hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
|
||||
hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
|
||||
if(hdcmi->MspInitCallback == NULL)
|
||||
{
|
||||
/* Legacy weak MspInit Callback */
|
||||
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
|
||||
}
|
||||
/* Initialize the low level hardware (MSP) */
|
||||
hdcmi->MspInitCallback(hdcmi);
|
||||
#else
|
||||
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
||||
HAL_DCMI_MspInit(hdcmi);
|
||||
#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
|
||||
HAL_DCMI_MspInit(hdcmi);
|
||||
}
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -2289,7 +2289,7 @@ HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
|
|||
* @brief Custom lane pins configuration
|
||||
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
|
||||
* the configuration information for the DSI.
|
||||
* @param CustomLane Function to be applyed on selected lane.
|
||||
* @param CustomLane Function to be applied on selected lane.
|
||||
* This parameter can be any value of @arg DSI_CustomLane
|
||||
* @param Lane select between clock or data lane 0 or data lane 1.
|
||||
* This parameter can be any value of @arg DSI_Lane_Select
|
||||
|
|
|
@ -93,7 +93,7 @@
|
|||
[..]
|
||||
(+) A specific option field manage the different steps of a sequential transfer
|
||||
(+) Option field values are defined through @ref FMPI2C_XFEROPTIONS and are listed below:
|
||||
(++) FMPI2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
|
||||
(++) FMPI2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
|
||||
(++) FMPI2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
|
||||
and data to transfer without a final stop condition
|
||||
(++) FMPI2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
|
||||
|
@ -112,7 +112,7 @@
|
|||
or HAL_FMPI2C_Master_Seq_Receive_IT(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME)
|
||||
or HAL_FMPI2C_Master_Seq_Transmit_DMA(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME)
|
||||
or HAL_FMPI2C_Master_Seq_Receive_DMA(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME).
|
||||
Then usage of this option FMPI2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
|
||||
Then usage of this option FMPI2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
|
||||
without stopping the communication and so generate a restart condition.
|
||||
(++) FMPI2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
|
||||
interface.
|
||||
|
@ -122,7 +122,7 @@
|
|||
or HAL_FMPI2C_Master_Seq_Receive_DMA(option FMPI2C_FIRST_FRAME then FMPI2C_OTHER_FRAME).
|
||||
Then usage of this option FMPI2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
|
||||
|
||||
(+) Differents sequential FMPI2C interfaces are listed below:
|
||||
(+) Different sequential FMPI2C interfaces are listed below:
|
||||
(++) Sequential transmit in master FMPI2C mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Master_Seq_Transmit_IT()
|
||||
or using @ref HAL_FMPI2C_Master_Seq_Transmit_DMA()
|
||||
(+++) At transmission end of current frame transfer, @ref HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
|
||||
|
@ -391,8 +391,10 @@ static void FMPI2C_ITListenCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
|
|||
static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode);
|
||||
|
||||
/* Private functions to handle IT transfer */
|
||||
static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
|
||||
static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
|
||||
static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
|
||||
static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
|
||||
|
||||
/* Private functions for FMPI2C transfer IRQ handler */
|
||||
static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources);
|
||||
|
@ -401,7 +403,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf
|
|||
static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources);
|
||||
|
||||
/* Private functions to handle flags during polling transfer */
|
||||
static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
|
||||
static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status,
|
||||
uint32_t Timeout, uint32_t Tickstart);
|
||||
static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
|
||||
static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
|
||||
static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
|
||||
|
@ -418,7 +421,8 @@ static void FMPI2C_TreatErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c);
|
|||
static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c);
|
||||
|
||||
/* Private function to handle start, restart or stop a transfer */
|
||||
static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
|
||||
static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
|
||||
uint32_t Request);
|
||||
|
||||
/* Private function to Convert Specific options */
|
||||
static void FMPI2C_ConvertOtherXferOptions(FMPI2C_HandleTypeDef *hfmpi2c);
|
||||
|
@ -433,8 +437,8 @@ static void FMPI2C_ConvertOtherXferOptions(FMPI2C_HandleTypeDef *hfmpi2c);
|
|||
*/
|
||||
|
||||
/** @defgroup FMPI2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
|
@ -673,7 +677,8 @@ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c)
|
|||
* @param pCallback pointer to the Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID, pFMPI2C_CallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID,
|
||||
pFMPI2C_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -978,8 +983,8 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2
|
|||
*/
|
||||
|
||||
/** @defgroup FMPI2C_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
|
@ -1061,7 +1066,8 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2
|
|||
* @param Timeout Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
|
@ -1175,7 +1181,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint
|
|||
* @param Timeout Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
|
@ -1551,7 +1558,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_
|
|||
* @param Size Amount of data to be sent
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size)
|
||||
{
|
||||
uint32_t xfermode;
|
||||
|
||||
|
@ -1787,7 +1795,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uin
|
|||
* @param Size Amount of data to be sent
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size)
|
||||
{
|
||||
uint32_t xfermode;
|
||||
HAL_StatusTypeDef dmaxferstatus;
|
||||
|
@ -1930,7 +1939,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c,
|
|||
* @param Size Amount of data to be sent
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size)
|
||||
{
|
||||
uint32_t xfermode;
|
||||
HAL_StatusTypeDef dmaxferstatus;
|
||||
|
@ -2281,7 +2291,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui
|
|||
* @param Timeout Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
|
@ -2373,8 +2384,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D
|
|||
}
|
||||
}
|
||||
|
||||
}
|
||||
while (hfmpi2c->XferCount > 0U);
|
||||
} while (hfmpi2c->XferCount > 0U);
|
||||
|
||||
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
||||
/* Wait until STOPF flag is reset */
|
||||
|
@ -2416,7 +2426,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D
|
|||
* @param Timeout Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
|
@ -2508,8 +2519,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De
|
|||
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
|
||||
}
|
||||
}
|
||||
}
|
||||
while (hfmpi2c->XferCount > 0U);
|
||||
} while (hfmpi2c->XferCount > 0U);
|
||||
|
||||
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
||||
/* Wait until STOPF flag is reset */
|
||||
|
@ -2549,7 +2559,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De
|
|||
* @param Size Amount of data to be sent
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint32_t xfermode;
|
||||
|
@ -2640,7 +2651,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
|
|||
* @param Size Amount of data to be sent
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint32_t xfermode;
|
||||
|
@ -2730,7 +2742,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t
|
|||
* @param Size Amount of data to be sent
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint32_t xfermode;
|
||||
|
@ -2874,7 +2887,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16
|
|||
* @param Size Amount of data to be read
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint32_t xfermode;
|
||||
|
@ -3125,8 +3139,7 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16
|
|||
|
||||
/* Increment Trials */
|
||||
FMPI2C_Trials++;
|
||||
}
|
||||
while (FMPI2C_Trials < Trials);
|
||||
} while (FMPI2C_Trials < Trials);
|
||||
|
||||
/* Update FMPI2C state */
|
||||
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
|
||||
|
@ -3157,7 +3170,8 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16
|
|||
* @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions)
|
||||
{
|
||||
uint32_t xfermode;
|
||||
uint32_t xferrequest = FMPI2C_GENERATE_START_WRITE;
|
||||
|
@ -3241,7 +3255,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2
|
|||
* @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions)
|
||||
{
|
||||
uint32_t xfermode;
|
||||
uint32_t xferrequest = FMPI2C_GENERATE_START_WRITE;
|
||||
|
@ -3403,7 +3418,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi
|
|||
* @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions)
|
||||
{
|
||||
uint32_t xfermode;
|
||||
uint32_t xferrequest = FMPI2C_GENERATE_START_READ;
|
||||
|
@ -3487,7 +3503,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c
|
|||
* @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions)
|
||||
{
|
||||
uint32_t xfermode;
|
||||
uint32_t xferrequest = FMPI2C_GENERATE_START_READ;
|
||||
|
@ -3647,7 +3664,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2
|
|||
* @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
|
||||
|
@ -3742,7 +3760,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c
|
|||
* @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions)
|
||||
{
|
||||
HAL_StatusTypeDef dmaxferstatus;
|
||||
|
||||
|
@ -3921,7 +3940,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2
|
|||
* @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
|
||||
|
@ -4016,7 +4036,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c,
|
|||
* @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions)
|
||||
{
|
||||
HAL_StatusTypeDef dmaxferstatus;
|
||||
|
||||
|
@ -4301,8 +4322,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint
|
|||
*/
|
||||
|
||||
/** @defgroup FMPI2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function handles FMPI2C event interrupt request.
|
||||
|
@ -4540,8 +4561,8 @@ __weak void HAL_FMPI2C_AbortCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
|
|||
*/
|
||||
|
||||
/** @defgroup FMPI2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
||||
* @brief Peripheral State, Mode and Error functions
|
||||
*
|
||||
* @brief Peripheral State, Mode and Error functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State, Mode and Error functions #####
|
||||
|
@ -4578,11 +4599,11 @@ HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Return the FMPI2C error code.
|
||||
* @brief Return the FMPI2C error code.
|
||||
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified FMPI2C.
|
||||
* @retval FMPI2C Error Code
|
||||
*/
|
||||
* @retval FMPI2C Error Code
|
||||
*/
|
||||
uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c)
|
||||
{
|
||||
return hfmpi2c->ErrorCode;
|
||||
|
@ -4768,7 +4789,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp
|
|||
/* So clear Flag NACKF only */
|
||||
if (hfmpi2c->XferCount == 0U)
|
||||
{
|
||||
if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) && (tmpoptions == FMPI2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
|
||||
/* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
|
||||
if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) && (tmpoptions == FMPI2C_FIRST_AND_LAST_FRAME))
|
||||
{
|
||||
/* Call FMPI2C Listen complete process */
|
||||
FMPI2C_ITListenCplt(hfmpi2c, tmpITFlags);
|
||||
|
@ -4828,7 +4850,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp
|
|||
FMPI2C_ITSlaveSeqCplt(hfmpi2c);
|
||||
}
|
||||
}
|
||||
else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_ADDR) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_ADDRI) != RESET))
|
||||
else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_ADDR) != RESET) && \
|
||||
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_ADDRI) != RESET))
|
||||
{
|
||||
FMPI2C_ITAddrCplt(hfmpi2c, tmpITFlags);
|
||||
}
|
||||
|
@ -4836,7 +4859,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp
|
|||
{
|
||||
/* Write data to TXDR only if XferCount not reach "0" */
|
||||
/* A TXIS flag can be set, during STOP treatment */
|
||||
/* Check if all Datas have already been sent */
|
||||
/* Check if all data have already been sent */
|
||||
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
|
||||
if (hfmpi2c->XferCount > 0U)
|
||||
{
|
||||
|
@ -5064,7 +5087,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm
|
|||
|
||||
if (treatdmanack == 1U)
|
||||
{
|
||||
if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) && (tmpoptions == FMPI2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
|
||||
/* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
|
||||
if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) && (tmpoptions == FMPI2C_FIRST_AND_LAST_FRAME))
|
||||
{
|
||||
/* Call FMPI2C Listen complete process */
|
||||
FMPI2C_ITListenCplt(hfmpi2c, ITFlags);
|
||||
|
@ -5152,7 +5176,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm
|
|||
* @param Tickstart Tick start value
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
|
||||
static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
|
||||
{
|
||||
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
|
||||
|
||||
|
@ -5205,7 +5230,8 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c
|
|||
* @param Tickstart Tick start value
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
|
||||
static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
|
||||
{
|
||||
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE);
|
||||
|
||||
|
@ -5720,7 +5746,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
|
|||
}
|
||||
else if (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
|
||||
{
|
||||
/* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
|
||||
/* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
|
||||
FMPI2C_ITSlaveSeqCplt(hfmpi2c);
|
||||
|
||||
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
|
||||
|
@ -5857,7 +5883,7 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode)
|
|||
/* Disable all interrupts */
|
||||
FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT | FMPI2C_XFER_TX_IT);
|
||||
|
||||
/* If state is an abort treatment on goind, don't change state */
|
||||
/* If state is an abort treatment on going, don't change state */
|
||||
/* This change will be do later */
|
||||
if (hfmpi2c->State != HAL_FMPI2C_STATE_ABORT)
|
||||
{
|
||||
|
@ -5869,7 +5895,8 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode)
|
|||
|
||||
/* Abort DMA TX transfer if any */
|
||||
tmppreviousstate = hfmpi2c->PreviousState;
|
||||
if ((hfmpi2c->hdmatx != NULL) && ((tmppreviousstate == FMPI2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_TX)))
|
||||
if ((hfmpi2c->hdmatx != NULL) && ((tmppreviousstate == FMPI2C_STATE_MASTER_BUSY_TX) || \
|
||||
(tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_TX)))
|
||||
{
|
||||
if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN)
|
||||
{
|
||||
|
@ -5898,7 +5925,8 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode)
|
|||
}
|
||||
}
|
||||
/* Abort DMA RX transfer if any */
|
||||
else if ((hfmpi2c->hdmarx != NULL) && ((tmppreviousstate == FMPI2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_RX)))
|
||||
else if ((hfmpi2c->hdmarx != NULL) && ((tmppreviousstate == FMPI2C_STATE_MASTER_BUSY_RX) || \
|
||||
(tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_RX)))
|
||||
{
|
||||
if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN)
|
||||
{
|
||||
|
@ -6211,7 +6239,8 @@ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma)
|
|||
* @param Tickstart Tick start value
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
|
||||
static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status,
|
||||
uint32_t Timeout, uint32_t Tickstart)
|
||||
{
|
||||
while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == Status)
|
||||
{
|
||||
|
@ -6443,7 +6472,8 @@ static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2
|
|||
* @arg @ref FMPI2C_GENERATE_START_WRITE Generate Restart for write request.
|
||||
* @retval None
|
||||
*/
|
||||
static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
|
||||
static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
|
||||
uint32_t Request)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
|
||||
|
@ -6451,8 +6481,11 @@ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAdd
|
|||
assert_param(IS_TRANSFER_REQUEST(Request));
|
||||
|
||||
/* update CR2 register */
|
||||
MODIFY_REG(hfmpi2c->Instance->CR2, ((FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | FMPI2C_CR2_START | FMPI2C_CR2_STOP)), \
|
||||
(uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
|
||||
MODIFY_REG(hfmpi2c->Instance->CR2,
|
||||
((FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | \
|
||||
(FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | FMPI2C_CR2_START | FMPI2C_CR2_STOP)), \
|
||||
(uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) |
|
||||
(((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -6592,7 +6625,7 @@ static void FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t Interrupt
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Convert FMPI2Cx OTHER_xxx XferOptions to functionnal XferOptions.
|
||||
* @brief Convert FMPI2Cx OTHER_xxx XferOptions to functional XferOptions.
|
||||
* @param hfmpi2c FMPI2C handle.
|
||||
* @retval None
|
||||
*/
|
||||
|
|
|
@ -70,7 +70,7 @@
|
|||
|
||||
/** @defgroup FMPI2CEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
|
|
|
@ -204,7 +204,8 @@
|
|||
/** @addtogroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions
|
||||
* @{
|
||||
*/
|
||||
static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
|
||||
static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, FlagStatus Status,
|
||||
uint32_t Timeout);
|
||||
|
||||
static void FMPSMBUS_Enable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest);
|
||||
static void FMPSMBUS_Disable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest);
|
||||
|
@ -215,7 +216,8 @@ static void FMPSMBUS_ConvertOtherXferOptions(FMPSMBUS_HandleTypeDef *hfmpsmbus);
|
|||
|
||||
static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus);
|
||||
|
||||
static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
|
||||
static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
|
||||
uint32_t Request);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -227,8 +229,8 @@ static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t
|
|||
*/
|
||||
|
||||
/** @defgroup FMPSMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
|
@ -580,7 +582,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmps
|
|||
* @param pCallback pointer to the Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, pFMPSMBUS_CallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID,
|
||||
pFMPSMBUS_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -859,8 +862,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf
|
|||
*/
|
||||
|
||||
/** @defgroup FMPSMBUS_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
|
@ -912,7 +915,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf
|
|||
* @param XferOptions Options of Transfer, value of @ref FMPSMBUS_XferOptions_definition
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
|
@ -951,7 +955,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm
|
|||
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
|
||||
if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE))
|
||||
{
|
||||
FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_GENERATE_START_WRITE);
|
||||
FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize,
|
||||
FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_GENERATE_START_WRITE);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -1011,7 +1016,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm
|
|||
* @param XferOptions Options of Transfer, value of @ref FMPSMBUS_XferOptions_definition
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
|
@ -1051,7 +1057,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmb
|
|||
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
|
||||
if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE))
|
||||
{
|
||||
FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_GENERATE_START_READ);
|
||||
FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize,
|
||||
FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_GENERATE_START_READ);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -1166,7 +1173,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus
|
|||
* @param XferOptions Options of Transfer, value of @ref FMPSMBUS_XferOptions_definition
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
|
||||
|
@ -1214,7 +1222,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmb
|
|||
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
|
||||
if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE))
|
||||
{
|
||||
FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_NO_STARTSTOP);
|
||||
FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize,
|
||||
FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_NO_STARTSTOP);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -1260,7 +1269,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmb
|
|||
* @param XferOptions Options of Transfer, value of @ref FMPSMBUS_XferOptions_definition
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
|
||||
|
@ -1418,7 +1428,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus
|
|||
* @param Timeout Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials,
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
|
@ -1527,8 +1538,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus,
|
|||
|
||||
/* Increment Trials */
|
||||
FMPSMBUS_Trials++;
|
||||
}
|
||||
while (FMPSMBUS_Trials < Trials);
|
||||
} while (FMPSMBUS_Trials < Trials);
|
||||
|
||||
hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY;
|
||||
|
||||
|
@ -1550,8 +1560,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus,
|
|||
*/
|
||||
|
||||
/** @defgroup FMPSMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Handle FMPSMBUS event interrupt request.
|
||||
|
@ -1567,7 +1577,12 @@ void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus)
|
|||
uint32_t tmpcr1value = READ_REG(hfmpsmbus->Instance->CR1);
|
||||
|
||||
/* FMPSMBUS in mode Transmitter ---------------------------------------------------*/
|
||||
if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)) != RESET) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TXIS) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_STOPF) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_AF) != RESET)))
|
||||
if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)) != RESET) &&
|
||||
((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TXIS) != RESET) ||
|
||||
(FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) ||
|
||||
(FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) ||
|
||||
(FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_STOPF) != RESET) ||
|
||||
(FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_AF) != RESET)))
|
||||
{
|
||||
/* Slave mode selected */
|
||||
if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX) == HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX)
|
||||
|
@ -1586,7 +1601,12 @@ void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus)
|
|||
}
|
||||
|
||||
/* FMPSMBUS in mode Receiver ----------------------------------------------------*/
|
||||
if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)) != RESET) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_RXNE) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_STOPF) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_AF) != RESET)))
|
||||
if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)) != RESET) &&
|
||||
((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_RXNE) != RESET) ||
|
||||
(FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) ||
|
||||
(FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) ||
|
||||
(FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_STOPF) != RESET) ||
|
||||
(FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_AF) != RESET)))
|
||||
{
|
||||
/* Slave mode selected */
|
||||
if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX) == HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX)
|
||||
|
@ -1605,7 +1625,12 @@ void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus)
|
|||
}
|
||||
|
||||
/* FMPSMBUS in mode Listener Only --------------------------------------------------*/
|
||||
if (((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, FMPSMBUS_IT_ADDRI) != RESET) || (FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, FMPSMBUS_IT_STOPI) != RESET) || (FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, FMPSMBUS_IT_NACKI) != RESET)) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_ADDR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_STOPF) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_AF) != RESET)))
|
||||
if (((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, FMPSMBUS_IT_ADDRI) != RESET) ||
|
||||
(FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, FMPSMBUS_IT_STOPI) != RESET) ||
|
||||
(FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, FMPSMBUS_IT_NACKI) != RESET)) &&
|
||||
((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_ADDR) != RESET) ||
|
||||
(FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_STOPF) != RESET) ||
|
||||
(FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_AF) != RESET)))
|
||||
{
|
||||
if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_LISTEN) == HAL_FMPSMBUS_STATE_LISTEN)
|
||||
{
|
||||
|
@ -1745,8 +1770,8 @@ __weak void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus)
|
|||
*/
|
||||
|
||||
/** @defgroup FMPSMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @brief Peripheral State and Errors functions
|
||||
*
|
||||
* @brief Peripheral State and Errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State and Errors functions #####
|
||||
|
@ -1772,11 +1797,11 @@ uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Return the FMPSMBUS error code.
|
||||
* @brief Return the FMPSMBUS error code.
|
||||
* @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified FMPSMBUS.
|
||||
* @retval FMPSMBUS Error Code
|
||||
*/
|
||||
* @retval FMPSMBUS Error Code
|
||||
*/
|
||||
uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus)
|
||||
{
|
||||
return hfmpsmbus->ErrorCode;
|
||||
|
@ -1791,7 +1816,7 @@ uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus)
|
|||
*/
|
||||
|
||||
/** @addtogroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions
|
||||
* @brief Data transfers Private functions
|
||||
* @brief Data transfers Private functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
@ -1855,7 +1880,7 @@ static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus,
|
|||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hfmpsmbus);
|
||||
|
||||
/* REenable the selected FMPSMBUS peripheral */
|
||||
/* Re-enable the selected FMPSMBUS peripheral */
|
||||
__HAL_FMPSMBUS_ENABLE(hfmpsmbus);
|
||||
|
||||
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
||||
|
@ -1942,7 +1967,8 @@ static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus,
|
|||
|
||||
if (hfmpsmbus->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, MAX_NBYTE_SIZE, (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), FMPSMBUS_NO_STARTSTOP);
|
||||
FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, MAX_NBYTE_SIZE,
|
||||
(FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), FMPSMBUS_NO_STARTSTOP);
|
||||
hfmpsmbus->XferSize = MAX_NBYTE_SIZE;
|
||||
}
|
||||
else
|
||||
|
@ -2156,7 +2182,8 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u
|
|||
HAL_FMPSMBUS_AddrCallback(hfmpsmbus, TransferDirection, SlaveAddrCode);
|
||||
#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
|
||||
}
|
||||
else if ((FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_RXNE) != RESET) || (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_TCR) != RESET))
|
||||
else if ((FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_RXNE) != RESET) ||
|
||||
(FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_TCR) != RESET))
|
||||
{
|
||||
if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX) == HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX)
|
||||
{
|
||||
|
@ -2211,7 +2238,8 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u
|
|||
{
|
||||
if (hfmpsmbus->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
FMPSMBUS_TransferConfig(hfmpsmbus, 0, MAX_NBYTE_SIZE, (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), FMPSMBUS_NO_STARTSTOP);
|
||||
FMPSMBUS_TransferConfig(hfmpsmbus, 0, MAX_NBYTE_SIZE, (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)),
|
||||
FMPSMBUS_NO_STARTSTOP);
|
||||
hfmpsmbus->XferSize = MAX_NBYTE_SIZE;
|
||||
}
|
||||
else
|
||||
|
@ -2555,7 +2583,8 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus)
|
|||
* @param Timeout Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
|
||||
static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, FlagStatus Status,
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
|
@ -2604,7 +2633,8 @@ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef
|
|||
* @arg @ref FMPSMBUS_GENERATE_START_WRITE Generate Restart for write request.
|
||||
* @retval None
|
||||
*/
|
||||
static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
|
||||
static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
|
||||
uint32_t Request)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance));
|
||||
|
@ -2612,12 +2642,16 @@ static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t
|
|||
assert_param(IS_FMPSMBUS_TRANSFER_REQUEST(Request));
|
||||
|
||||
/* update CR2 register */
|
||||
MODIFY_REG(hfmpsmbus->Instance->CR2, ((FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - FMPI2C_CR2_RD_WRN_Pos))) | FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_PECBYTE)), \
|
||||
(uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
|
||||
MODIFY_REG(hfmpsmbus->Instance->CR2,
|
||||
((FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | \
|
||||
(FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - FMPI2C_CR2_RD_WRN_Pos))) | \
|
||||
FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_PECBYTE)), \
|
||||
(uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | \
|
||||
(((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Convert FMPSMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
|
||||
* @brief Convert FMPSMBUSx OTHER_xxx XferOptions to functional XferOptions.
|
||||
* @param hfmpsmbus FMPSMBUS handle.
|
||||
* @retval None
|
||||
*/
|
||||
|
|
|
@ -0,0 +1,146 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_fmpsmbus_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief FMPSMBUS Extended HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of FMPSMBUS Extended peripheral:
|
||||
* + Extended features functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### FMPSMBUS peripheral Extended features #####
|
||||
==============================================================================
|
||||
|
||||
[..] Comparing to other previous devices, the FMPSMBUS interface for STM32F4xx
|
||||
devices contains the following additional features
|
||||
|
||||
(+) Disable or enable Fast Mode Plus
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
|
||||
(++) HAL_FMPSMBUSEx_EnableFastModePlus()
|
||||
(++) HAL_FMPSMBUSEx_DisableFastModePlus()
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FMPSMBUSEx FMPSMBUSEx
|
||||
* @brief FMPSMBUS Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_FMPSMBUS_MODULE_ENABLED
|
||||
#if defined(FMPI2C_CR1_PE)
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FMPSMBUSEx_Exported_Functions FMPSMBUS Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FMPSMBUSEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
|
||||
(+) Configure Fast Mode Plus
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the FMPSMBUS fast mode plus driving capability.
|
||||
* @param ConfigFastModePlus Selects the pin.
|
||||
* This parameter can be one of the @ref FMPSMBUSEx_FastModePlus values
|
||||
* @note For FMPI2C1, fast mode plus driving capability can be enabled on all selected
|
||||
* FMPI2C1 pins using FMPI2C_FASTMODEPLUS_FMPI2C1 parameter or independently
|
||||
* on each one of the following pins PB6, PB7, PB8 and PB9.
|
||||
* @note For remaining FMPI2C1 pins (PA14, PA15...) fast mode plus driving capability
|
||||
* can be enabled only by using FMPI2C_FASTMODEPLUS_FMPI2C1 parameter.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FMPSMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_FMPSMBUS_FASTMODEPLUS(ConfigFastModePlus));
|
||||
|
||||
/* Enable SYSCFG clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* Enable fast mode plus driving capability for selected pin */
|
||||
SET_BIT(SYSCFG->CFGR, (uint32_t)ConfigFastModePlus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the FMPSMBUS fast mode plus driving capability.
|
||||
* @param ConfigFastModePlus Selects the pin.
|
||||
* This parameter can be one of the @ref FMPSMBUSEx_FastModePlus values
|
||||
* @note For FMPI2C1, fast mode plus driving capability can be disabled on all selected
|
||||
* FMPI2C1 pins using FMPI2C_FASTMODEPLUS_FMPI2C1 parameter or independently
|
||||
* on each one of the following pins PB6, PB7, PB8 and PB9.
|
||||
* @note For remaining FMPI2C1 pins (PA14, PA15...) fast mode plus driving capability
|
||||
* can be disabled only by using FMPI2C_FASTMODEPLUS_FMPI2C1 parameter.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_FMPSMBUS_FASTMODEPLUS(ConfigFastModePlus));
|
||||
|
||||
/* Enable SYSCFG clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* Disable fast mode plus driving capability for selected pin */
|
||||
CLEAR_BIT(SYSCFG->CFGR, (uint32_t)ConfigFastModePlus);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FMPI2C_CR1_PE */
|
||||
#endif /* HAL_FMPSMBUS_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
@ -123,13 +123,6 @@
|
|||
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE 0x00000003U
|
||||
#define EXTI_MODE 0x10000000U
|
||||
#define GPIO_MODE_IT 0x00010000U
|
||||
#define GPIO_MODE_EVT 0x00020000U
|
||||
#define RISING_EDGE 0x00100000U
|
||||
#define FALLING_EDGE 0x00200000U
|
||||
#define GPIO_OUTPUT_TYPE 0x00000010U
|
||||
|
||||
#define GPIO_NUMBER 16U
|
||||
/**
|
||||
|
@ -193,8 +186,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
{
|
||||
/*--------------------- GPIO Mode Configuration ------------------------*/
|
||||
/* In case of Output or Alternate function mode selection */
|
||||
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
||||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
|
||||
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
||||
{
|
||||
/* Check the Speed parameter */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
||||
|
@ -211,14 +204,17 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
GPIOx->OTYPER = temp;
|
||||
}
|
||||
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||
temp = GPIOx->PUPDR;
|
||||
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
|
||||
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
||||
GPIOx->PUPDR = temp;
|
||||
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
||||
{
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||
temp = GPIOx->PUPDR;
|
||||
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
|
||||
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
||||
GPIOx->PUPDR = temp;
|
||||
}
|
||||
|
||||
/* In case of Alternate function mode selection */
|
||||
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
||||
{
|
||||
/* Check the Alternate function parameter */
|
||||
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
||||
|
@ -434,17 +430,16 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
|
|||
*/
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint32_t odr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)
|
||||
{
|
||||
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BSRR = GPIO_Pin;
|
||||
}
|
||||
/* get current Ouput Data Register value */
|
||||
odr = GPIOx->ODR;
|
||||
|
||||
/* Set selected pins that were at low level, and reset ones that were high */
|
||||
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -5,7 +5,7 @@
|
|||
* @brief Extended HASH HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the HASH peripheral for SHA-224 and SHA-256
|
||||
* alogrithms:
|
||||
* algorithms:
|
||||
* + HASH or HMAC processing in polling mode
|
||||
* + HASH or HMAC processing in interrupt mode
|
||||
* + HASH or HMAC processing in DMA mode
|
||||
|
@ -46,10 +46,11 @@
|
|||
|
||||
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
|
||||
|
||||
(+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
|
||||
From that point, each buffer can be fed to the Peripheral thru HAL_HASHEx_xxx_Start_DMA() API.
|
||||
(+++) HASH processing: once initialization is done, MDMAT bit must be set through
|
||||
__HAL_HASH_SET_MDMAT() macro.
|
||||
From that point, each buffer can be fed to the Peripheral through HAL_HASHEx_xxx_Start_DMA() API.
|
||||
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
|
||||
macro then wrap-up the HASH processing in feeding the last input buffer thru the
|
||||
macro then wrap-up the HASH processing in feeding the last input buffer through the
|
||||
same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
|
||||
API HAL_HASHEx_xxx_Finish().
|
||||
|
||||
|
@ -107,8 +108,8 @@
|
|||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
|
||||
* @brief HASH extended processing functions using polling mode.
|
||||
*
|
||||
* @brief HASH extended processing functions using polling mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Polling mode HASH extended processing functions #####
|
||||
|
@ -147,7 +148,8 @@
|
|||
* @param Timeout Timeout value
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
@ -174,7 +176,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
{
|
||||
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
|
||||
return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -187,7 +189,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p
|
|||
* @param Timeout Timeout value
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
@ -203,7 +206,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
|
|||
* @param Timeout Timeout value
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
@ -230,7 +234,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
{
|
||||
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
|
||||
return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -243,7 +247,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p
|
|||
* @param Timeout Timeout value
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
@ -253,8 +258,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
|
|||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
|
||||
* @brief HASH extended processing functions using interrupt mode.
|
||||
*
|
||||
* @brief HASH extended processing functions using interrupt mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Interruption mode HASH extended processing functions #####
|
||||
|
@ -285,9 +290,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -310,7 +316,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
{
|
||||
return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
|
||||
return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -322,9 +328,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -337,9 +344,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -362,7 +370,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
{
|
||||
return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
|
||||
return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -374,9 +382,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -384,11 +393,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
|
|||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
|
||||
* @brief HASH extended processing functions using DMA mode.
|
||||
*
|
||||
* @brief HASH extended processing functions using DMA mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### DMA mode HASH extended processing functionss #####
|
||||
##### DMA mode HASH extended processing functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to calculate in DMA mode
|
||||
the hash value using one of the following algorithms:
|
||||
|
@ -440,9 +449,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param Timeout Timeout value.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Finish(hhash, pOutBuffer, Timeout);
|
||||
return HASH_Finish(hhash, pOutBuffer, Timeout);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -470,9 +479,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param Timeout Timeout value.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Finish(hhash, pOutBuffer, Timeout);
|
||||
return HASH_Finish(hhash, pOutBuffer, Timeout);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -480,8 +489,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
|
|||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
|
||||
* @brief HMAC extended processing functions using polling mode.
|
||||
*
|
||||
* @brief HMAC extended processing functions using polling mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Polling mode HMAC extended processing functions #####
|
||||
|
@ -512,7 +521,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
|
|||
* @param Timeout Timeout value.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
@ -530,7 +540,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
* @param Timeout Timeout value.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
@ -541,8 +552,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
|
||||
* @brief HMAC extended processing functions using interruption mode.
|
||||
*
|
||||
* @brief HMAC extended processing functions using interruption mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Interrupt mode HMAC extended processing functions #####
|
||||
|
@ -572,7 +583,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
@ -589,7 +601,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
@ -603,8 +616,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
|
||||
* @brief HMAC extended processing functions using DMA mode.
|
||||
*
|
||||
* @brief HMAC extended processing functions using DMA mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### DMA mode HMAC extended processing functions #####
|
||||
|
@ -681,8 +694,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
|
||||
* @brief HMAC extended processing functions in multi-buffer DMA mode.
|
||||
*
|
||||
* @brief HMAC extended processing functions in multi-buffer DMA mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Multi-buffer DMA mode HMAC extended processing functions #####
|
||||
|
|
|
@ -185,9 +185,9 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
|
|||
* This parameter can be a value from 0 to 255
|
||||
* @param speed Current device speed.
|
||||
* This parameter can be one of these values:
|
||||
* HCD_SPEED_HIGH: High speed mode,
|
||||
* HCD_SPEED_FULL: Full speed mode,
|
||||
* HCD_SPEED_LOW: Low speed mode
|
||||
* HCD_DEVICE_SPEED_HIGH: High speed mode,
|
||||
* HCD_DEVICE_SPEED_FULL: Full speed mode,
|
||||
* HCD_DEVICE_SPEED_LOW: Low speed mode
|
||||
* @param ep_type Endpoint Type.
|
||||
* This parameter can be one of these values:
|
||||
* EP_TYPE_CTRL: Control type,
|
||||
|
@ -566,6 +566,16 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|||
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
|
||||
}
|
||||
|
||||
/* Handle Rx Queue Level Interrupts */
|
||||
if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
|
||||
{
|
||||
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
||||
|
||||
HCD_RXQLVL_IRQHandler(hhcd);
|
||||
|
||||
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
||||
}
|
||||
|
||||
/* Handle Host channel Interrupt */
|
||||
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
|
||||
{
|
||||
|
@ -586,16 +596,6 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|||
}
|
||||
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
|
||||
}
|
||||
|
||||
/* Handle Rx Queue Level Interrupts */
|
||||
if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
|
||||
{
|
||||
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
||||
|
||||
HCD_RXQLVL_IRQHandler(hhcd);
|
||||
|
||||
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1207,10 +1207,17 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
|
||||
{
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
|
||||
hhcd->hc[ch_num].state = HC_DATATGLERR;
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
|
||||
{
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
hhcd->hc[ch_num].state = HC_XACTERR;
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -1227,7 +1234,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
{
|
||||
if (hhcd->Init.dma_enable != 0U)
|
||||
{
|
||||
hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \
|
||||
hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].XferSize - \
|
||||
(USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
|
||||
}
|
||||
|
||||
|
@ -1268,8 +1275,18 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
{
|
||||
/* ... */
|
||||
}
|
||||
hhcd->hc[ch_num].toggle_in ^= 1U;
|
||||
|
||||
if (hhcd->Init.dma_enable == 1U)
|
||||
{
|
||||
if (((hhcd->hc[ch_num].XferSize / hhcd->hc[ch_num].max_packet) & 1U) != 0U)
|
||||
{
|
||||
hhcd->hc[ch_num].toggle_in ^= 1U;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
hhcd->hc[ch_num].toggle_in ^= 1U;
|
||||
}
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
|
||||
{
|
||||
|
@ -1277,17 +1294,17 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
|
||||
if (hhcd->hc[ch_num].state == HC_XFRC)
|
||||
{
|
||||
hhcd->hc[ch_num].urb_state = URB_DONE;
|
||||
hhcd->hc[ch_num].urb_state = URB_DONE;
|
||||
}
|
||||
else if (hhcd->hc[ch_num].state == HC_STALL)
|
||||
{
|
||||
hhcd->hc[ch_num].urb_state = URB_STALL;
|
||||
hhcd->hc[ch_num].urb_state = URB_STALL;
|
||||
}
|
||||
else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
|
||||
(hhcd->hc[ch_num].state == HC_DATATGLERR))
|
||||
{
|
||||
hhcd->hc[ch_num].ErrCnt++;
|
||||
if (hhcd->hc[ch_num].ErrCnt > 3U)
|
||||
if (hhcd->hc[ch_num].ErrCnt > 2U)
|
||||
{
|
||||
hhcd->hc[ch_num].ErrCnt = 0U;
|
||||
hhcd->hc[ch_num].urb_state = URB_ERROR;
|
||||
|
@ -1295,18 +1312,19 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
else
|
||||
{
|
||||
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
|
||||
}
|
||||
|
||||
/* re-activate the channel */
|
||||
tmpreg = USBx_HC(ch_num)->HCCHAR;
|
||||
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
||||
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
||||
USBx_HC(ch_num)->HCCHAR = tmpreg;
|
||||
/* re-activate the channel */
|
||||
tmpreg = USBx_HC(ch_num)->HCCHAR;
|
||||
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
||||
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
||||
USBx_HC(ch_num)->HCCHAR = tmpreg;
|
||||
}
|
||||
}
|
||||
else if (hhcd->hc[ch_num].state == HC_NAK)
|
||||
{
|
||||
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
|
||||
/* re-activate the channel */
|
||||
|
||||
/* re-activate the channel */
|
||||
tmpreg = USBx_HC(ch_num)->HCCHAR;
|
||||
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
||||
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
||||
|
@ -1324,14 +1342,6 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
|
||||
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
|
||||
{
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
hhcd->hc[ch_num].ErrCnt++;
|
||||
hhcd->hc[ch_num].state = HC_XACTERR;
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
|
||||
{
|
||||
if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
|
||||
|
@ -1377,6 +1387,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
uint32_t USBx_BASE = (uint32_t)USBx;
|
||||
uint32_t ch_num = (uint32_t)chnum;
|
||||
uint32_t tmpreg;
|
||||
uint32_t num_packets;
|
||||
|
||||
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
|
||||
{
|
||||
|
@ -1395,15 +1406,6 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
}
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
|
||||
{
|
||||
hhcd->hc[ch_num].state = HC_NYET;
|
||||
hhcd->hc[ch_num].do_ping = 1U;
|
||||
hhcd->hc[ch_num].ErrCnt = 0U;
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
|
||||
{
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
|
@ -1413,11 +1415,27 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
|
||||
{
|
||||
hhcd->hc[ch_num].ErrCnt = 0U;
|
||||
|
||||
/* transaction completed with NYET state, update do ping state */
|
||||
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
|
||||
{
|
||||
hhcd->hc[ch_num].do_ping = 1U;
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
|
||||
}
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
|
||||
hhcd->hc[ch_num].state = HC_XFRC;
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
|
||||
{
|
||||
hhcd->hc[ch_num].state = HC_NYET;
|
||||
hhcd->hc[ch_num].do_ping = 1U;
|
||||
hhcd->hc[ch_num].ErrCnt = 0U;
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
|
||||
{
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
|
||||
|
@ -1432,7 +1450,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
|
||||
if (hhcd->hc[ch_num].do_ping == 0U)
|
||||
{
|
||||
if (hhcd->hc[ch_num].speed == HCD_SPEED_HIGH)
|
||||
if (hhcd->hc[ch_num].speed == HCD_DEVICE_SPEED_HIGH)
|
||||
{
|
||||
hhcd->hc[ch_num].do_ping = 1U;
|
||||
}
|
||||
|
@ -1444,9 +1462,26 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
|
||||
{
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
hhcd->hc[ch_num].state = HC_XACTERR;
|
||||
if (hhcd->Init.dma_enable == 0U)
|
||||
{
|
||||
hhcd->hc[ch_num].state = HC_XACTERR;
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
}
|
||||
else
|
||||
{
|
||||
hhcd->hc[ch_num].ErrCnt++;
|
||||
if (hhcd->hc[ch_num].ErrCnt > 2U)
|
||||
{
|
||||
hhcd->hc[ch_num].ErrCnt = 0U;
|
||||
hhcd->hc[ch_num].urb_state = URB_ERROR;
|
||||
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
|
||||
}
|
||||
else
|
||||
{
|
||||
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
|
||||
}
|
||||
}
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
|
||||
|
@ -1467,7 +1502,22 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) ||
|
||||
(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR))
|
||||
{
|
||||
hhcd->hc[ch_num].toggle_out ^= 1U;
|
||||
if (hhcd->Init.dma_enable == 1U)
|
||||
{
|
||||
if (hhcd->hc[ch_num].xfer_len > 0U)
|
||||
{
|
||||
num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet;
|
||||
|
||||
if ((num_packets & 1U) != 0U)
|
||||
{
|
||||
hhcd->hc[ch_num].toggle_out ^= 1U;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
hhcd->hc[ch_num].toggle_out ^= 1U;
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (hhcd->hc[ch_num].state == HC_NAK)
|
||||
|
@ -1486,7 +1536,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
(hhcd->hc[ch_num].state == HC_DATATGLERR))
|
||||
{
|
||||
hhcd->hc[ch_num].ErrCnt++;
|
||||
if (hhcd->hc[ch_num].ErrCnt > 3U)
|
||||
if (hhcd->hc[ch_num].ErrCnt > 2U)
|
||||
{
|
||||
hhcd->hc[ch_num].ErrCnt = 0U;
|
||||
hhcd->hc[ch_num].urb_state = URB_ERROR;
|
||||
|
@ -1494,13 +1544,13 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
else
|
||||
{
|
||||
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
|
||||
}
|
||||
|
||||
/* re-activate the channel */
|
||||
tmpreg = USBx_HC(ch_num)->HCCHAR;
|
||||
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
||||
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
||||
USBx_HC(ch_num)->HCCHAR = tmpreg;
|
||||
/* re-activate the channel */
|
||||
tmpreg = USBx_HC(ch_num)->HCCHAR;
|
||||
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
||||
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
||||
USBx_HC(ch_num)->HCCHAR = tmpreg;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -1527,14 +1577,15 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|||
uint32_t USBx_BASE = (uint32_t)USBx;
|
||||
uint32_t pktsts;
|
||||
uint32_t pktcnt;
|
||||
uint32_t temp;
|
||||
uint32_t GrxstspReg;
|
||||
uint32_t xferSizePktCnt;
|
||||
uint32_t tmpreg;
|
||||
uint32_t ch_num;
|
||||
|
||||
temp = hhcd->Instance->GRXSTSP;
|
||||
ch_num = temp & USB_OTG_GRXSTSP_EPNUM;
|
||||
pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17;
|
||||
pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
|
||||
GrxstspReg = hhcd->Instance->GRXSTSP;
|
||||
ch_num = GrxstspReg & USB_OTG_GRXSTSP_EPNUM;
|
||||
pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17;
|
||||
pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4;
|
||||
|
||||
switch (pktsts)
|
||||
{
|
||||
|
@ -1542,20 +1593,31 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|||
/* Read the data into the host buffer. */
|
||||
if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0))
|
||||
{
|
||||
(void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);
|
||||
|
||||
/*manage multiple Xfer */
|
||||
hhcd->hc[ch_num].xfer_buff += pktcnt;
|
||||
hhcd->hc[ch_num].xfer_count += pktcnt;
|
||||
|
||||
if ((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U)
|
||||
if ((hhcd->hc[ch_num].xfer_count + pktcnt) <= hhcd->hc[ch_num].xfer_len)
|
||||
{
|
||||
/* re-activate the channel when more packets are expected */
|
||||
tmpreg = USBx_HC(ch_num)->HCCHAR;
|
||||
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
||||
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
||||
USBx_HC(ch_num)->HCCHAR = tmpreg;
|
||||
hhcd->hc[ch_num].toggle_in ^= 1U;
|
||||
(void)USB_ReadPacket(hhcd->Instance,
|
||||
hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);
|
||||
|
||||
/* manage multiple Xfer */
|
||||
hhcd->hc[ch_num].xfer_buff += pktcnt;
|
||||
hhcd->hc[ch_num].xfer_count += pktcnt;
|
||||
|
||||
/* get transfer size packet count */
|
||||
xferSizePktCnt = (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19;
|
||||
|
||||
if ((hhcd->hc[ch_num].max_packet == pktcnt) && (xferSizePktCnt > 0U))
|
||||
{
|
||||
/* re-activate the channel when more packets are expected */
|
||||
tmpreg = USBx_HC(ch_num)->HCCHAR;
|
||||
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
||||
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
||||
USBx_HC(ch_num)->HCCHAR = tmpreg;
|
||||
hhcd->hc[ch_num].toggle_in ^= 1U;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
hhcd->hc[ch_num].urb_state = URB_ERROR;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
|
|
@ -90,7 +90,7 @@
|
|||
[..]
|
||||
(+) A specific option field manage the different steps of a sequential transfer
|
||||
(+) Option field values are defined through @ref I2C_XferOptions_definition and are listed below:
|
||||
(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
|
||||
(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
|
||||
(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
|
||||
and data to transfer without a final stop condition
|
||||
(++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
|
||||
|
@ -109,7 +109,7 @@
|
|||
or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
|
||||
or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
|
||||
or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
|
||||
Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
|
||||
Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
|
||||
without stopping the communication and so generate a restart condition.
|
||||
(++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
|
||||
interface.
|
||||
|
@ -119,7 +119,7 @@
|
|||
or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
|
||||
Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
|
||||
|
||||
(+) Differents sequential I2C interfaces are listed below:
|
||||
(+) Different sequential I2C interfaces are listed below:
|
||||
(++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
|
||||
or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
|
||||
(+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
|
||||
|
@ -1986,20 +1986,37 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
|
|||
|
||||
if (hi2c->XferSize > 0U)
|
||||
{
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
if (hi2c->hdmatx != NULL)
|
||||
{
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
|
||||
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmatx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmatx->XferM1CpltCallback = NULL;
|
||||
hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmatx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmatx->XferM1CpltCallback = NULL;
|
||||
hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update I2C state */
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
|
||||
/* Update I2C error code */
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (dmaxferstatus == HAL_OK)
|
||||
{
|
||||
|
@ -2127,20 +2144,37 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
|
|||
|
||||
if (hi2c->XferSize > 0U)
|
||||
{
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
if (hi2c->hdmarx != NULL)
|
||||
{
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
|
||||
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmarx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferM1CpltCallback = NULL;
|
||||
hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferAbortCallback = NULL;
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmarx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferM1CpltCallback = NULL;
|
||||
hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferAbortCallback = NULL;
|
||||
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update I2C state */
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
|
||||
/* Update I2C error code */
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (dmaxferstatus == HAL_OK)
|
||||
{
|
||||
|
@ -2247,20 +2281,37 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
|
|||
hi2c->XferSize = hi2c->XferCount;
|
||||
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
|
||||
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
if (hi2c->hdmatx != NULL)
|
||||
{
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
|
||||
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmatx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmatx->XferM1CpltCallback = NULL;
|
||||
hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmatx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmatx->XferM1CpltCallback = NULL;
|
||||
hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update I2C state */
|
||||
hi2c->State = HAL_I2C_STATE_LISTEN;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
|
||||
/* Update I2C error code */
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (dmaxferstatus == HAL_OK)
|
||||
{
|
||||
|
@ -2344,20 +2395,37 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
|
|||
hi2c->XferSize = hi2c->XferCount;
|
||||
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
|
||||
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
if (hi2c->hdmarx != NULL)
|
||||
{
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
|
||||
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmarx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferM1CpltCallback = NULL;
|
||||
hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferAbortCallback = NULL;
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmarx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferM1CpltCallback = NULL;
|
||||
hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferAbortCallback = NULL;
|
||||
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update I2C state */
|
||||
hi2c->State = HAL_I2C_STATE_LISTEN;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
|
||||
/* Update I2C error code */
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (dmaxferstatus == HAL_OK)
|
||||
{
|
||||
|
@ -3022,20 +3090,37 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
|
|||
|
||||
if (hi2c->XferSize > 0U)
|
||||
{
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
if (hi2c->hdmatx != NULL)
|
||||
{
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
|
||||
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmatx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmatx->XferM1CpltCallback = NULL;
|
||||
hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmatx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmatx->XferM1CpltCallback = NULL;
|
||||
hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update I2C state */
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
|
||||
/* Update I2C error code */
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (dmaxferstatus == HAL_OK)
|
||||
{
|
||||
|
@ -3048,11 +3133,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
|
|||
/* Prevent unused argument(s) compilation and MISRA warning */
|
||||
UNUSED(dmaxferstatus);
|
||||
|
||||
/* Clear directly Complete callback as no XferAbortCallback is used to finalize Abort treatment */
|
||||
if (hi2c->hdmatx != NULL)
|
||||
{
|
||||
hi2c->hdmatx->XferCpltCallback = NULL;
|
||||
}
|
||||
/* Set the unused I2C DMA transfer complete callback to NULL */
|
||||
hi2c->hdmatx->XferCpltCallback = NULL;
|
||||
|
||||
/* Disable Acknowledge */
|
||||
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
|
||||
|
@ -3188,20 +3270,37 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
|
|||
|
||||
if (hi2c->XferSize > 0U)
|
||||
{
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
if (hi2c->hdmarx != NULL)
|
||||
{
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
|
||||
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmarx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferM1CpltCallback = NULL;
|
||||
hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferAbortCallback = NULL;
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmarx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferM1CpltCallback = NULL;
|
||||
hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferAbortCallback = NULL;
|
||||
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update I2C state */
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
|
||||
/* Update I2C error code */
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (dmaxferstatus == HAL_OK)
|
||||
{
|
||||
|
@ -3214,11 +3313,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
|
|||
/* Prevent unused argument(s) compilation and MISRA warning */
|
||||
UNUSED(dmaxferstatus);
|
||||
|
||||
/* Clear directly Complete callback as no XferAbortCallback is used to finalize Abort treatment */
|
||||
if (hi2c->hdmarx != NULL)
|
||||
{
|
||||
hi2c->hdmarx->XferCpltCallback = NULL;
|
||||
}
|
||||
/* Set the unused I2C DMA transfer complete callback to NULL */
|
||||
hi2c->hdmarx->XferCpltCallback = NULL;
|
||||
|
||||
/* Disable Acknowledge */
|
||||
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
|
||||
|
@ -3609,18 +3705,35 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
|||
|
||||
if (hi2c->XferSize > 0U)
|
||||
{
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
if (hi2c->hdmatx != NULL)
|
||||
{
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
|
||||
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmatx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmatx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update I2C state */
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
|
||||
/* Update I2C error code */
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (dmaxferstatus == HAL_OK)
|
||||
{
|
||||
|
@ -3933,20 +4046,35 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
|
|||
SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
|
||||
}
|
||||
}
|
||||
if (hi2c->hdmarx != NULL)
|
||||
{
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmarx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferAbortCallback = NULL;
|
||||
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmarx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferAbortCallback = NULL;
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update I2C state */
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
|
||||
/* Update I2C error code */
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
if (dmaxferstatus == HAL_OK)
|
||||
{
|
||||
/* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
|
||||
|
@ -4196,18 +4324,35 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_
|
|||
hi2c->XferSize = hi2c->XferCount;
|
||||
hi2c->XferOptions = XferOptions;
|
||||
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
if (hi2c->hdmatx != NULL)
|
||||
{
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
|
||||
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmatx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmatx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update I2C state */
|
||||
hi2c->State = HAL_I2C_STATE_LISTEN;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
|
||||
/* Update I2C error code */
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (dmaxferstatus == HAL_OK)
|
||||
{
|
||||
|
@ -4419,18 +4564,35 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t
|
|||
hi2c->XferSize = hi2c->XferCount;
|
||||
hi2c->XferOptions = XferOptions;
|
||||
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
if (hi2c->hdmarx != NULL)
|
||||
{
|
||||
/* Set the I2C DMA transfer complete callback */
|
||||
hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
|
||||
/* Set the DMA error callback */
|
||||
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
|
||||
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmarx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferAbortCallback = NULL;
|
||||
/* Set the unused DMA callbacks to NULL */
|
||||
hi2c->hdmarx->XferHalfCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferAbortCallback = NULL;
|
||||
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
|
||||
/* Enable the DMA stream */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update I2C state */
|
||||
hi2c->State = HAL_I2C_STATE_LISTEN;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
|
||||
/* Update I2C error code */
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (dmaxferstatus == HAL_OK)
|
||||
{
|
||||
|
@ -5627,13 +5789,11 @@ static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
|
|||
/* Send slave address */
|
||||
hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
|
||||
|
||||
if ((hi2c->hdmatx != NULL) || (hi2c->hdmarx != NULL))
|
||||
if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
|
||||
|| ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
|
||||
{
|
||||
if ((hi2c->hdmatx->XferCpltCallback != NULL) || (hi2c->hdmarx->XferCpltCallback != NULL))
|
||||
{
|
||||
/* Enable DMA Request */
|
||||
SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
|
||||
}
|
||||
/* Enable DMA Request */
|
||||
SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -7295,7 +7455,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
|
||||
* @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
|
||||
* @param hi2c I2C handle.
|
||||
* @retval None
|
||||
*/
|
||||
|
|
|
@ -103,8 +103,8 @@
|
|||
(+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
|
||||
(+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
|
||||
(+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
|
||||
|
||||
(+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data
|
||||
|
||||
[..]
|
||||
(@) You can refer to the I2S HAL driver header file for more useful macros
|
||||
|
||||
|
@ -352,7 +352,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
|
|||
/* I2S standard */
|
||||
if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
|
||||
{
|
||||
/* In I2S standard packet lenght is multiplied by 2 */
|
||||
/* In I2S standard packet length is multiplied by 2 */
|
||||
packetlength = packetlength * 2U;
|
||||
}
|
||||
|
||||
|
@ -469,9 +469,11 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
|
|||
}
|
||||
|
||||
/* Configure the I2S Slave with the I2S Master parameter values */
|
||||
tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
|
||||
(uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
|
||||
(uint16_t)hi2s->Init.CPOL))));
|
||||
tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | \
|
||||
(uint16_t)tmp | \
|
||||
(uint16_t)hi2s->Init.Standard | \
|
||||
(uint16_t)hi2s->Init.DataFormat | \
|
||||
(uint16_t)hi2s->Init.CPOL);
|
||||
|
||||
/* Write to SPIx I2SCFGR */
|
||||
WRITE_REG(I2SxEXT(hi2s->Instance)->I2SCFGR, tmpreg);
|
||||
|
@ -831,7 +833,7 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @param Timeout Timeout duration
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
|
@ -948,7 +950,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @param Timeout Timeout duration
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
|
@ -1049,7 +1051,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
* @retval HAL status
|
||||
|
@ -1113,7 +1115,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
* @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
|
||||
|
@ -1179,7 +1181,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
* @retval HAL status
|
||||
|
@ -1270,7 +1272,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
* @retval HAL status
|
||||
|
|
|
@ -129,8 +129,11 @@ static void I2SEx_RxISR_I2S(I2S_HandleTypeDef *hi2s);
|
|||
static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s);
|
||||
static void I2SEx_TxISR_I2S(I2S_HandleTypeDef *hi2s);
|
||||
static void I2SEx_TxISR_I2SExt(I2S_HandleTypeDef *hi2s);
|
||||
static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
|
||||
uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed);
|
||||
static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
|
||||
uint32_t Flag,
|
||||
uint32_t State,
|
||||
uint32_t Timeout,
|
||||
I2S_UseTypeDef i2sUsed);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -202,8 +205,11 @@ static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTyp
|
|||
* between Master and Slave(example: audio streaming).
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
|
||||
uint16_t Size, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s,
|
||||
uint16_t *pTxData,
|
||||
uint16_t *pRxData,
|
||||
uint16_t Size,
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint32_t tmp1 = 0U;
|
||||
HAL_StatusTypeDef errorcode = HAL_OK;
|
||||
|
@ -420,7 +426,9 @@ error :
|
|||
* between Master and Slave(example: audio streaming).
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s,
|
||||
uint16_t *pTxData,
|
||||
uint16_t *pRxData,
|
||||
uint16_t Size)
|
||||
{
|
||||
uint32_t tmp1 = 0U;
|
||||
|
@ -530,7 +538,9 @@ error :
|
|||
* between Master and Slave(example: audio streaming).
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s,
|
||||
uint16_t *pTxData,
|
||||
uint16_t *pRxData,
|
||||
uint16_t Size)
|
||||
{
|
||||
uint32_t *tmp = NULL;
|
||||
|
@ -586,11 +596,11 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
|
|||
/* Set the I2S Rx DMA error callback */
|
||||
hi2s->hdmarx->XferErrorCallback = I2SEx_TxRxDMAError;
|
||||
|
||||
/* Set the I2S Tx DMA Half transfer complete callback */
|
||||
hi2s->hdmatx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt;
|
||||
/* Set the I2S Tx DMA Half transfer complete callback as NULL */
|
||||
hi2s->hdmatx->XferHalfCpltCallback = NULL;
|
||||
|
||||
/* Set the I2S Tx DMA transfer complete callback */
|
||||
hi2s->hdmatx->XferCpltCallback = I2SEx_TxRxDMACplt;
|
||||
/* Set the I2S Tx DMA transfer complete callback as NULL */
|
||||
hi2s->hdmatx->XferCpltCallback = NULL;
|
||||
|
||||
/* Set the I2S Tx DMA error callback */
|
||||
hi2s->hdmatx->XferErrorCallback = I2SEx_TxRxDMAError;
|
||||
|
@ -877,65 +887,34 @@ static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma)
|
|||
{
|
||||
I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
||||
|
||||
/* if DMA is configured in DMA_NORMAL mode */
|
||||
/* If DMA is configured in DMA_NORMAL mode */
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
if (hi2s->hdmarx == hdma)
|
||||
if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || \
|
||||
((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
|
||||
/* Disable Tx & Rx DMA Requests */
|
||||
{
|
||||
/* Disable Rx DMA Request */
|
||||
if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || \
|
||||
((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
|
||||
{
|
||||
CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
|
||||
}
|
||||
|
||||
hi2s->RxXferCount = 0U;
|
||||
|
||||
if (hi2s->TxXferCount == 0U)
|
||||
{
|
||||
hi2s->State = HAL_I2S_STATE_READY;
|
||||
|
||||
/* Call user TxRx complete callback */
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
hi2s->TxRxCpltCallback(hi2s);
|
||||
#else
|
||||
HAL_I2SEx_TxRxCpltCallback(hi2s);
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
}
|
||||
CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
|
||||
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
|
||||
CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
|
||||
}
|
||||
|
||||
if (hi2s->hdmatx == hdma)
|
||||
{
|
||||
/* Disable Tx DMA Request */
|
||||
if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || \
|
||||
((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
|
||||
{
|
||||
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
|
||||
}
|
||||
hi2s->RxXferCount = 0U;
|
||||
hi2s->TxXferCount = 0U;
|
||||
|
||||
hi2s->TxXferCount = 0U;
|
||||
|
||||
if (hi2s->RxXferCount == 0U)
|
||||
{
|
||||
hi2s->State = HAL_I2S_STATE_READY;
|
||||
|
||||
/* Call user TxRx complete callback */
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
hi2s->TxRxCpltCallback(hi2s);
|
||||
#else
|
||||
HAL_I2SEx_TxRxCpltCallback(hi2s);
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
hi2s->State = HAL_I2S_STATE_READY;
|
||||
}
|
||||
|
||||
/* Call user TxRx complete callback */
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
hi2s->TxRxCpltCallback(hi2s);
|
||||
#else
|
||||
HAL_I2SEx_TxRxCpltCallback(hi2s);
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1091,8 +1070,11 @@ static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s)
|
|||
* @param i2sUsed I2S instance reference
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
|
||||
uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed)
|
||||
static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
|
||||
uint32_t Flag,
|
||||
uint32_t State,
|
||||
uint32_t Timeout,
|
||||
I2S_UseTypeDef i2sUsed)
|
||||
{
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
|
|
|
@ -16,33 +16,43 @@
|
|||
(+) The IWDG can be started by either software or hardware (configurable
|
||||
through option byte).
|
||||
|
||||
(+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
|
||||
if the main clock fails.
|
||||
(+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
|
||||
active even if the main clock fails.
|
||||
|
||||
(+) Once the IWDG is started, the LSI is forced ON and both can not be
|
||||
(+) Once the IWDG is started, the LSI is forced ON and both cannot be
|
||||
disabled. The counter starts counting down from the reset value (0xFFF).
|
||||
When it reaches the end of count value (0x000) a reset signal is
|
||||
generated (IWDG reset).
|
||||
|
||||
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
|
||||
the IWDG_RLR value is reloaded in the counter and the watchdog reset is
|
||||
prevented.
|
||||
the IWDG_RLR value is reloaded into the counter and the watchdog reset
|
||||
is prevented.
|
||||
|
||||
(+) The IWDG is implemented in the VDD voltage domain that is still functional
|
||||
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
|
||||
in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
|
||||
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
|
||||
reset occurs.
|
||||
|
||||
(+) Debug mode : When the microcontroller enters debug mode (core halted),
|
||||
(+) Debug mode: When the microcontroller enters debug mode (core halted),
|
||||
the IWDG counter either continues to work normally or stops, depending
|
||||
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
|
||||
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
|
||||
|
||||
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
|
||||
The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
|
||||
devices provide the capability to measure the LSI frequency (LSI clock
|
||||
connected internally to TIM5 CH4 input capture). The measured value
|
||||
can be used to have an IWDG timeout with an acceptable accuracy.
|
||||
The IWDG timeout may vary due to LSI clock frequency dispersion.
|
||||
STM32F4xx devices provide the capability to measure the LSI clock
|
||||
frequency (LSI clock is internally connected to TIM5 CH4 input capture).
|
||||
The measured value can be used to have an IWDG timeout with an
|
||||
acceptable accuracy.
|
||||
|
||||
[..] Default timeout value (necessary for IWDG_SR status register update):
|
||||
Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
|
||||
This frequency being subject to variations as mentioned above, the
|
||||
default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
|
||||
below) may become too short or too long.
|
||||
In such cases, this default timeout value can be tuned by redefining
|
||||
the constant LSI_VALUE at user-application level (based, for instance,
|
||||
on the measured LSI clock frequency as explained above).
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
|
@ -102,10 +112,15 @@
|
|||
/** @defgroup IWDG_Private_Defines IWDG Private Defines
|
||||
* @{
|
||||
*/
|
||||
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
|
||||
higher prescaler (256), and according to LSI variation, we need to wait at
|
||||
least 6 cycles so 48 ms. */
|
||||
#define HAL_IWDG_DEFAULT_TIMEOUT 48u
|
||||
/* Status register needs up to 5 LSI clock periods divided by the clock
|
||||
prescaler to be updated. The number of LSI clock periods is upper-rounded to
|
||||
6 for the timeout value calculation.
|
||||
The timeout value is also calculated using the highest prescaler (256) and
|
||||
the LSI_VALUE constant. The value of this constant can be changed by the user
|
||||
to take into account possible LSI clock period variations.
|
||||
The timeout value is multiplied by 1000 to be converted in milliseconds. */
|
||||
#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
|
||||
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_RVU | IWDG_SR_PVU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -174,11 +189,14 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
|||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for register to be updated */
|
||||
while (hiwdg->Instance->SR != 0x00u)
|
||||
while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -189,6 +207,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -208,7 +227,6 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
|||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Refresh the IWDG.
|
||||
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
|
||||
|
@ -224,6 +242,7 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -194,8 +194,8 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t
|
|||
*/
|
||||
|
||||
/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
|
@ -232,16 +232,17 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
|
|||
|
||||
assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
|
||||
assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
|
||||
if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
|| (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
{
|
||||
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
|
||||
assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
|
||||
}
|
||||
assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
|
||||
if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
|
||||
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
|
||||
{
|
||||
assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
|
||||
assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
|
||||
assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
|
||||
}
|
||||
assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
|
||||
assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
|
||||
|
@ -275,17 +276,18 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
|
|||
/* Get the LPTIMx CFGR value */
|
||||
tmpcfgr = hlptim->Instance->CFGR;
|
||||
|
||||
if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
|| (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
{
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
|
||||
}
|
||||
if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
|
||||
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
|
||||
{
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
|
||||
}
|
||||
|
||||
/* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
|
||||
/* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
|
||||
LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
|
||||
|
||||
/* Set initialization parameters */
|
||||
|
@ -295,13 +297,25 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
|
|||
hlptim->Init.UpdateMode |
|
||||
hlptim->Init.CounterSource);
|
||||
|
||||
if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
/* Glitch filters for internal triggers and external inputs are configured
|
||||
* only if an internal clock source is provided to the LPTIM
|
||||
*/
|
||||
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
|
||||
{
|
||||
tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
|
||||
hlptim->Init.UltraLowPowerClock.SampleTime);
|
||||
}
|
||||
|
||||
/* Configure LPTIM external clock polarity and digital filter */
|
||||
if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
|| (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
{
|
||||
tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
|
||||
hlptim->Init.UltraLowPowerClock.SampleTime);
|
||||
}
|
||||
|
||||
if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
|
||||
/* Configure LPTIM external trigger */
|
||||
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
|
||||
{
|
||||
/* Enable External trigger and set the trigger source */
|
||||
tmpcfgr |= (hlptim->Init.Trigger.Source |
|
||||
|
@ -401,8 +415,8 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
|
|||
*/
|
||||
|
||||
/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
|
||||
* @brief Start-Stop operation functions.
|
||||
*
|
||||
* @brief Start-Stop operation functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### LPTIM Start Stop operation functions #####
|
||||
|
@ -1535,7 +1549,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
|
|||
hlptim->State = HAL_LPTIM_STATE_BUSY;
|
||||
|
||||
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
|
||||
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
&& (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
{
|
||||
/* Check if clock is prescaled */
|
||||
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
|
||||
|
@ -1620,7 +1635,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
|
|||
#endif /* EXTI_IMR_MR23 */
|
||||
|
||||
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
|
||||
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
&& (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
{
|
||||
/* Check if clock is prescaled */
|
||||
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
|
||||
|
@ -1715,8 +1731,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
|
|||
*/
|
||||
|
||||
/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
|
||||
* @brief Read operation functions.
|
||||
*
|
||||
* @brief Read operation functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### LPTIM Read operation functions #####
|
||||
|
@ -1773,8 +1789,8 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
|
|||
*/
|
||||
|
||||
/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
|
||||
* @brief LPTIM IRQ handler.
|
||||
*
|
||||
* @brief LPTIM IRQ handler.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### LPTIM IRQ handler and callbacks #####
|
||||
|
@ -2244,8 +2260,8 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti
|
|||
*/
|
||||
|
||||
/** @defgroup LPTIM_Group5 Peripheral State functions
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral State functions #####
|
||||
|
@ -2320,8 +2336,7 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t
|
|||
{
|
||||
result = HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
|
||||
} while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
|
@ -287,6 +287,7 @@
|
|||
static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc);
|
||||
static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc);
|
||||
static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus);
|
||||
static uint32_t MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout);
|
||||
static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc);
|
||||
static void MMC_Write_IT(MMC_HandleTypeDef *hmmc);
|
||||
static void MMC_Read_IT(MMC_HandleTypeDef *hmmc);
|
||||
|
@ -444,6 +445,17 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
|
|||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= errorstate;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
@ -584,17 +596,6 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= errorstate;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure the MMC DPSM (Data Path State Machine) */
|
||||
config.DataTimeOut = SDMMC_DATATIMEOUT;
|
||||
config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
|
||||
|
@ -800,17 +801,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= errorstate;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write Blocks in Polling mode */
|
||||
if(NumberOfBlocks > 1U)
|
||||
{
|
||||
|
@ -996,17 +986,6 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= errorstate;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure the MMC DPSM (Data Path State Machine) */
|
||||
config.DataTimeOut = SDMMC_DATATIMEOUT;
|
||||
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
|
||||
|
@ -1104,17 +1083,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= errorstate;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write Blocks in Polling mode */
|
||||
if(NumberOfBlocks > 1U)
|
||||
{
|
||||
|
@ -1216,16 +1184,9 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
|
||||
hmmc->ErrorCode = errorstate;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Force DMA Direction */
|
||||
hmmc->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||
MODIFY_REG(hmmc->hdmarx->Instance->CR, DMA_SxCR_DIR, hmmc->hdmarx->Init.Direction);
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
if(HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK)
|
||||
|
@ -1345,16 +1306,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= errorstate;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write Blocks in Polling mode */
|
||||
if(NumberOfBlocks > 1U)
|
||||
|
@ -1384,6 +1335,10 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat
|
|||
/* Enable SDIO DMA transfer */
|
||||
__HAL_MMC_DMA_ENABLE(hmmc);
|
||||
|
||||
/* Force DMA Direction */
|
||||
hmmc->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH;
|
||||
MODIFY_REG(hmmc->hdmatx->Instance->CR, DMA_SxCR_DIR, hmmc->hdmatx->Init.Direction);
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
if(HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK)
|
||||
{
|
||||
|
@ -2045,6 +2000,8 @@ HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTyp
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
|
||||
{
|
||||
uint32_t block_nbr = 0;
|
||||
|
||||
pCSD->CSDStruct = (uint8_t)((hmmc->CSD[0] & 0xC0000000U) >> 30U);
|
||||
|
||||
pCSD->SysSpecVersion = (uint8_t)((hmmc->CSD[0] & 0x3C000000U) >> 26U);
|
||||
|
@ -2083,12 +2040,34 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp
|
|||
|
||||
pCSD->DeviceSizeMul = (uint8_t)((hmmc->CSD[2] & 0x00038000U) >> 15U);
|
||||
|
||||
hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
|
||||
hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
|
||||
hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
|
||||
if(MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
|
||||
hmmc->MmcCard.LogBlockSize = 512U;
|
||||
if(hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD)
|
||||
{
|
||||
hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
|
||||
hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
|
||||
hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
|
||||
hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
|
||||
hmmc->MmcCard.LogBlockSize = 512U;
|
||||
}
|
||||
else if(hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD)
|
||||
{
|
||||
hmmc->MmcCard.BlockNbr = block_nbr;
|
||||
hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr;
|
||||
hmmc->MmcCard.BlockSize = 512U;
|
||||
hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
pCSD->EraseGrSize = (uint8_t)((hmmc->CSD[2] & 0x00004000U) >> 14U);
|
||||
|
||||
|
@ -2170,7 +2149,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32
|
|||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_BUS_WIDE(WideMode));
|
||||
|
||||
/* Chnage Satte */
|
||||
/* Change State */
|
||||
hmmc->State = HAL_MMC_STATE_BUSY;
|
||||
|
||||
/* Update Clock for Bus mode update */
|
||||
|
@ -2810,6 +2789,93 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
|
|||
return HAL_MMC_ERROR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads extended CSD register to get the sectors number of the device
|
||||
* @param hmmc: Pointer to MMC handle
|
||||
* @param pFieldData: Pointer to the read buffer
|
||||
* @param FieldIndex: Index of the field to be read
|
||||
* @param Timeout: Specify timeout value
|
||||
* @retval HAL status
|
||||
*/
|
||||
static uint32_t MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout)
|
||||
{
|
||||
SDIO_DataInitTypeDef config;
|
||||
uint32_t errorstate;
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
uint32_t count;
|
||||
uint32_t i = 0;
|
||||
uint32_t tmp_data;
|
||||
|
||||
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
|
||||
|
||||
/* Initialize data control register */
|
||||
hmmc->Instance->DCTRL = 0;
|
||||
|
||||
/* Configure the MMC DPSM (Data Path State Machine) */
|
||||
config.DataTimeOut = SDMMC_DATATIMEOUT;
|
||||
config.DataLength = 512;
|
||||
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
|
||||
config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
|
||||
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
|
||||
config.DPSM = SDIO_DPSM_ENABLE;
|
||||
(void)SDIO_ConfigData(hmmc->Instance, &config);
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= errorstate;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Poll on SDMMC flags */
|
||||
while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
|
||||
{
|
||||
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF))
|
||||
{
|
||||
/* Read data from SDMMC Rx FIFO */
|
||||
for(count = 0U; count < 8U; count++)
|
||||
{
|
||||
tmp_data = SDIO_ReadFIFO(hmmc->Instance);
|
||||
/* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */
|
||||
/* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */
|
||||
if ((i + count) == ((uint32_t)FieldIndex/4U))
|
||||
{
|
||||
*pFieldData = tmp_data;
|
||||
}
|
||||
}
|
||||
i += 8U;
|
||||
}
|
||||
|
||||
if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
|
||||
hmmc->State= HAL_MMC_STATE_READY;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
|
||||
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
hmmc->ErrorCode |= errorstate;
|
||||
}
|
||||
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS);
|
||||
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Wrap up reading in non-blocking mode.
|
||||
* @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
|
||||
|
|
|
@ -761,6 +761,21 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address
|
|||
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
|
||||
}
|
||||
|
||||
/* Calculate PageSize */
|
||||
#ifdef FSMC_PCR2_PWID
|
||||
if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
|
||||
#else /* FMC_PCR2_PWID is defined */
|
||||
if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
|
||||
#endif
|
||||
{
|
||||
size = size / 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
/* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
|
||||
}
|
||||
|
||||
/* Get Data into Buffer */
|
||||
for(; index < size; index++)
|
||||
{
|
||||
|
@ -1003,6 +1018,21 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres
|
|||
}
|
||||
}
|
||||
|
||||
/* Calculate PageSize */
|
||||
#ifdef FSMC_PCR2_PWID
|
||||
if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
|
||||
#else /* FMC_PCR2_PWID is defined */
|
||||
if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
|
||||
#endif
|
||||
{
|
||||
size = size / 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
/* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
|
||||
}
|
||||
|
||||
/* Write data to memory */
|
||||
for(; index < size; index++)
|
||||
{
|
||||
|
@ -1219,7 +1249,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad
|
|||
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
|
||||
|
||||
/* Column in page address */
|
||||
columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
|
||||
columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
|
||||
|
||||
/* Spare area(s) read loop */
|
||||
while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
|
||||
|
@ -1487,7 +1517,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A
|
|||
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
|
||||
|
||||
/* Column in page address */
|
||||
columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
|
||||
columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
|
||||
|
||||
/* Spare area(s) write loop */
|
||||
while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
|
||||
|
|
|
@ -100,11 +100,19 @@ void HAL_PWR_DeInit(void)
|
|||
* backup data registers and backup SRAM).
|
||||
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @note The following sequence is required to bypass the delay between
|
||||
* DBP bit programming and the effective enabling of the backup domain.
|
||||
* Please check the Errata Sheet for more details under "Possible delay
|
||||
* in backup domain protection disabling/enabling after programming the
|
||||
* DBP bit" section.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableBkUpAccess(void)
|
||||
{
|
||||
__IO uint32_t dummyread;
|
||||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
|
||||
dummyread = PWR->CR;
|
||||
UNUSED(dummyread);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -112,11 +120,19 @@ void HAL_PWR_EnableBkUpAccess(void)
|
|||
* backup data registers and backup SRAM).
|
||||
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @note The following sequence is required to bypass the delay between
|
||||
* DBP bit programming and the effective disabling of the backup domain.
|
||||
* Please check the Errata Sheet for more details under "Possible delay
|
||||
* in backup domain protection disabling/enabling after programming the
|
||||
* DBP bit" section.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableBkUpAccess(void)
|
||||
{
|
||||
__IO uint32_t dummyread;
|
||||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
|
||||
dummyread = PWR->CR;
|
||||
UNUSED(dummyread);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -540,11 +540,22 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
|
|||
{
|
||||
/* Do not return HAL_ERROR if request repeats the current configuration */
|
||||
pll_config = RCC->PLLCFGR;
|
||||
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ))
|
||||
#if defined (RCC_PLLCFGR_PLLR)
|
||||
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
|
||||
#else
|
||||
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
|
||||
#endif
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
|
|
@ -3334,7 +3334,13 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
||||
{
|
||||
uint32_t tickstart = 0U;
|
||||
uint32_t tickstart, pll_config;
|
||||
|
||||
/* Check Null pointer */
|
||||
if(RCC_OscInitStruct == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
||||
|
@ -3612,13 +3618,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|||
}
|
||||
|
||||
/* Configure the main PLL clock source, multiplication and division factors. */
|
||||
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
||||
RCC_OscInitStruct->PLL.PLLM,
|
||||
RCC_OscInitStruct->PLL.PLLN,
|
||||
RCC_OscInitStruct->PLL.PLLP,
|
||||
RCC_OscInitStruct->PLL.PLLQ,
|
||||
RCC_OscInitStruct->PLL.PLLR);
|
||||
|
||||
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
|
||||
RCC_OscInitStruct->PLL.PLLM | \
|
||||
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
|
||||
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
|
||||
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \
|
||||
(RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)));
|
||||
/* Enable the main PLL. */
|
||||
__HAL_RCC_PLL_ENABLE();
|
||||
|
||||
|
@ -3654,7 +3659,35 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
/* Check if there is a request to disable the PLL used as System clock source */
|
||||
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do not return HAL_ERROR if request repeats the current configuration */
|
||||
pll_config = RCC->PLLCFGR;
|
||||
#if defined (RCC_PLLCFGR_PLLR)
|
||||
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
|
||||
#else
|
||||
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
|
||||
#endif
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return HAL_OK;
|
||||
|
|
|
@ -798,10 +798,10 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
|
|||
/* Set the RTC_TR register */
|
||||
hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
|
||||
|
||||
/* Clear the bits to be configured */
|
||||
/* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
|
||||
hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;
|
||||
|
||||
/* Configure the RTC_CR register */
|
||||
/* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
|
||||
hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
|
||||
|
||||
/* Exit Initialization mode */
|
||||
|
@ -1757,6 +1757,72 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
|
|||
return hrtc->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Daylight Saving Time, Add one hour to the calendar in one single operation
|
||||
* without going through the initialization procedure.
|
||||
* @param hrtc RTC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
UNUSED(hrtc);
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
SET_BIT(RTC->CR, RTC_CR_ADD1H);
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Daylight Saving Time, Substract one hour from the calendar in one
|
||||
* single operation without going through the initialization procedure.
|
||||
* @param hrtc RTC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
UNUSED(hrtc);
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
SET_BIT(RTC->CR, RTC_CR_SUB1H);
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Daylight Saving Time, Set the store operation bit.
|
||||
* @note It can be used by the software in order to memorize the DST status.
|
||||
* @param hrtc RTC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
UNUSED(hrtc);
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
SET_BIT(RTC->CR, RTC_CR_BKP);
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Daylight Saving Time, Clear the store operation bit.
|
||||
* @param hrtc RTC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
UNUSED(hrtc);
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
CLEAR_BIT(RTC->CR, RTC_CR_BKP);
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Daylight Saving Time, Read the store operation bit.
|
||||
* @param hrtc RTC handle
|
||||
* @retval operation see RTC_StoreOperation_Definitions
|
||||
*/
|
||||
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
UNUSED(hrtc);
|
||||
return READ_BIT(RTC->CR, RTC_CR_BKP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -65,9 +65,9 @@
|
|||
/** @defgroup SAI_Private_Functions SAI Private Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup SAIEx_Exported_Functions SAI Extended Exported Functions
|
||||
|
@ -101,28 +101,28 @@ void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
|
|||
|
||||
#if defined(STM32F446xx)
|
||||
/* This setting must be done with both audio block (A & B) disabled */
|
||||
switch(hsai->Init.SynchroExt)
|
||||
switch (hsai->Init.SynchroExt)
|
||||
{
|
||||
case SAI_SYNCEXT_DISABLE :
|
||||
tmpregisterGCR = 0U;
|
||||
break;
|
||||
case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
|
||||
tmpregisterGCR = SAI_GCR_SYNCOUT_0;
|
||||
break;
|
||||
case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
|
||||
tmpregisterGCR = SAI_GCR_SYNCOUT_1;
|
||||
break;
|
||||
default:
|
||||
tmpregisterGCR = 0U;
|
||||
break;
|
||||
case SAI_SYNCEXT_DISABLE :
|
||||
tmpregisterGCR = 0U;
|
||||
break;
|
||||
case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
|
||||
tmpregisterGCR = SAI_GCR_SYNCOUT_0;
|
||||
break;
|
||||
case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
|
||||
tmpregisterGCR = SAI_GCR_SYNCOUT_1;
|
||||
break;
|
||||
default:
|
||||
tmpregisterGCR = 0U;
|
||||
break;
|
||||
}
|
||||
|
||||
if((hsai->Init.Synchro) == SAI_SYNCHRONOUS_EXT_SAI2)
|
||||
if ((hsai->Init.Synchro) == SAI_SYNCHRONOUS_EXT_SAI2)
|
||||
{
|
||||
tmpregisterGCR |= SAI_GCR_SYNCIN_0;
|
||||
}
|
||||
|
||||
if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
|
||||
if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
|
||||
{
|
||||
SAI1->GCR = tmpregisterGCR;
|
||||
}
|
||||
|
@ -134,30 +134,30 @@ void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
|
|||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
|
||||
defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||
/* This setting must be done with both audio block (A & B) disabled */
|
||||
switch(hsai->Init.SynchroExt)
|
||||
switch (hsai->Init.SynchroExt)
|
||||
{
|
||||
case SAI_SYNCEXT_DISABLE :
|
||||
tmpregisterGCR = 0U;
|
||||
break;
|
||||
case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
|
||||
tmpregisterGCR = SAI_GCR_SYNCOUT_0;
|
||||
break;
|
||||
case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
|
||||
tmpregisterGCR = SAI_GCR_SYNCOUT_1;
|
||||
break;
|
||||
default:
|
||||
tmpregisterGCR = 0U;
|
||||
break;
|
||||
case SAI_SYNCEXT_DISABLE :
|
||||
tmpregisterGCR = 0U;
|
||||
break;
|
||||
case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
|
||||
tmpregisterGCR = SAI_GCR_SYNCOUT_0;
|
||||
break;
|
||||
case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
|
||||
tmpregisterGCR = SAI_GCR_SYNCOUT_1;
|
||||
break;
|
||||
default:
|
||||
tmpregisterGCR = 0U;
|
||||
break;
|
||||
}
|
||||
SAI1->GCR = tmpregisterGCR;
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
|
||||
}
|
||||
/**
|
||||
* @brief Get SAI Input Clock based on SAI source clock selection
|
||||
* @param hsai pointer to a SAI_HandleTypeDef structure that contains
|
||||
* the configuration information for SAI module.
|
||||
* @retval SAI Clock Input
|
||||
*/
|
||||
/**
|
||||
* @brief Get SAI Input Clock based on SAI source clock selection
|
||||
* @param hsai pointer to a SAI_HandleTypeDef structure that contains
|
||||
* the configuration information for SAI module.
|
||||
* @retval SAI Clock Input
|
||||
*/
|
||||
uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai)
|
||||
{
|
||||
/* This variable used to store the SAI_CK_x (value in Hz) */
|
||||
|
@ -181,7 +181,7 @@ uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai)
|
|||
assert_param(IS_SAI_CLK_SOURCE(hsai->Init.ClockSource));
|
||||
|
||||
/* SAI Block clock source selection */
|
||||
if(hsai->Instance == SAI1_Block_A)
|
||||
if (hsai->Instance == SAI1_Block_A)
|
||||
{
|
||||
__HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(hsai->Init.ClockSource);
|
||||
}
|
||||
|
@ -191,7 +191,7 @@ uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai)
|
|||
}
|
||||
|
||||
/* VCO Input Clock value calculation */
|
||||
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
|
||||
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
|
||||
{
|
||||
/* In Case the PLL Source is HSI (Internal Clock) */
|
||||
vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
|
||||
|
@ -202,38 +202,38 @@ uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai)
|
|||
vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
|
||||
}
|
||||
#if defined(STM32F413xx) || defined(STM32F423xx)
|
||||
/* SAI_CLK_x : SAI Block Clock configuration for different clock sources selected */
|
||||
if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLR)
|
||||
/* SAI_CLK_x : SAI Block Clock configuration for different clock sources selected */
|
||||
if (hsai->Init.ClockSource == SAI_CLKSOURCE_PLLR)
|
||||
{
|
||||
/* Configure the PLLI2S division factor */
|
||||
/* PLL_VCO Input = PLL_SOURCE/PLLM */
|
||||
/* PLL_VCO Output = PLL_VCO Input * PLLN */
|
||||
/* SAI_CLK(first level) = PLL_VCO Output/PLLR */
|
||||
tmpreg = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U;
|
||||
saiclocksource = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg);
|
||||
saiclocksource = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U)) / (tmpreg);
|
||||
|
||||
/* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
|
||||
tmpreg = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> 8U) + 1U);
|
||||
|
||||
saiclocksource = saiclocksource/(tmpreg);
|
||||
saiclocksource = saiclocksource / (tmpreg);
|
||||
|
||||
}
|
||||
else if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLI2S)
|
||||
else if (hsai->Init.ClockSource == SAI_CLKSOURCE_PLLI2S)
|
||||
{
|
||||
/* Configure the PLLI2S division factor */
|
||||
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
|
||||
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
|
||||
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SR */
|
||||
tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U;
|
||||
saiclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg);
|
||||
saiclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U)) / (tmpreg);
|
||||
|
||||
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */
|
||||
tmpreg = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) + 1U);
|
||||
saiclocksource = saiclocksource/(tmpreg);
|
||||
saiclocksource = saiclocksource / (tmpreg);
|
||||
}
|
||||
else if(hsai->Init.ClockSource == SAI_CLKSOURCE_HS)
|
||||
else if (hsai->Init.ClockSource == SAI_CLKSOURCE_HS)
|
||||
{
|
||||
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
|
||||
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
|
||||
{
|
||||
/* Get the I2S source clock value */
|
||||
saiclocksource = (uint32_t)(HSE_VALUE);
|
||||
|
@ -250,32 +250,32 @@ uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai)
|
|||
}
|
||||
#else
|
||||
/* SAI_CLK_x : SAI Block Clock configuration for different clock sources selected */
|
||||
if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLSAI)
|
||||
if (hsai->Init.ClockSource == SAI_CLKSOURCE_PLLSAI)
|
||||
{
|
||||
/* Configure the PLLI2S division factor */
|
||||
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
||||
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
||||
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
|
||||
tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U;
|
||||
saiclocksource = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg);
|
||||
saiclocksource = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U)) / (tmpreg);
|
||||
|
||||
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
|
||||
tmpreg = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U);
|
||||
saiclocksource = saiclocksource/(tmpreg);
|
||||
saiclocksource = saiclocksource / (tmpreg);
|
||||
|
||||
}
|
||||
else if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLI2S)
|
||||
else if (hsai->Init.ClockSource == SAI_CLKSOURCE_PLLI2S)
|
||||
{
|
||||
/* Configure the PLLI2S division factor */
|
||||
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
|
||||
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
|
||||
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
|
||||
tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U;
|
||||
saiclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg);
|
||||
saiclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U)) / (tmpreg);
|
||||
|
||||
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
|
||||
tmpreg = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U);
|
||||
saiclocksource = saiclocksource/(tmpreg);
|
||||
saiclocksource = saiclocksource / (tmpreg);
|
||||
}
|
||||
else /* sConfig->ClockSource == SAI_CLKSource_Ext */
|
||||
{
|
||||
|
@ -286,7 +286,7 @@ uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai)
|
|||
}
|
||||
#endif /* STM32F413xx || STM32F423xx */
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
|
||||
/* the return result is the value of SAI clock */
|
||||
/* the return result is the value of SAI clock */
|
||||
return saiclocksource;
|
||||
}
|
||||
|
||||
|
|
|
@ -448,6 +448,17 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
|
|||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
@ -588,17 +599,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure the SD DPSM (Data Path State Machine) */
|
||||
config.DataTimeOut = SDMMC_DATATIMEOUT;
|
||||
config.DataLength = NumberOfBlocks * BLOCKSIZE;
|
||||
|
@ -814,17 +814,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure the SD DPSM (Data Path State Machine) */
|
||||
config.DataTimeOut = SDMMC_DATATIMEOUT;
|
||||
config.DataLength = NumberOfBlocks * BLOCKSIZE;
|
||||
|
@ -1019,17 +1008,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure the SD DPSM (Data Path State Machine) */
|
||||
config.DataTimeOut = SDMMC_DATATIMEOUT;
|
||||
config.DataLength = BLOCKSIZE * NumberOfBlocks;
|
||||
|
@ -1127,17 +1105,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write Blocks in Polling mode */
|
||||
if(NumberOfBlocks > 1U)
|
||||
{
|
||||
|
@ -1235,6 +1202,10 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
|
|||
/* Set the DMA Abort callback */
|
||||
hsd->hdmarx->XferAbortCallback = NULL;
|
||||
|
||||
/* Force DMA Direction */
|
||||
hsd->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||
MODIFY_REG(hsd->hdmarx->Instance->CR, DMA_SxCR_DIR, hsd->hdmarx->Init.Direction);
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
|
||||
{
|
||||
|
@ -1254,17 +1225,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure the SD DPSM (Data Path State Machine) */
|
||||
config.DataTimeOut = SDMMC_DATATIMEOUT;
|
||||
config.DataLength = BLOCKSIZE * NumberOfBlocks;
|
||||
|
@ -1369,17 +1329,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write Blocks in Polling mode */
|
||||
if(NumberOfBlocks > 1U)
|
||||
{
|
||||
|
@ -1408,6 +1357,10 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
|
|||
/* Enable SDIO DMA transfer */
|
||||
__HAL_SD_DMA_ENABLE(hsd);
|
||||
|
||||
/* Force DMA Direction */
|
||||
hsd->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH;
|
||||
MODIFY_REG(hsd->hdmatx->Instance->CR, DMA_SxCR_DIR, hsd->hdmatx->Init.Direction);
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
|
||||
{
|
||||
|
@ -2197,6 +2150,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT
|
|||
{
|
||||
uint32_t sd_status[16];
|
||||
uint32_t errorstate;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
errorstate = SD_SendSDStatus(hsd, sd_status);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
|
@ -2205,7 +2159,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT
|
|||
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -2231,7 +2185,18 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT
|
|||
pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
|
||||
hsd->ErrorCode = errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -2270,6 +2235,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
|
|||
{
|
||||
SDIO_InitTypeDef Init;
|
||||
uint32_t errorstate;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_BUS_WIDE(WideMode));
|
||||
|
@ -2312,7 +2278,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
|
|||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -2326,10 +2292,20 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
|
|||
(void)SDIO_Init(hsd->Instance, Init);
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Change State */
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -3150,13 +3126,17 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
|
|||
return errorstate;
|
||||
}
|
||||
|
||||
while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
|
||||
while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT))
|
||||
{
|
||||
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
|
||||
{
|
||||
*(tempscr + index) = SDIO_ReadFIFO(hsd->Instance);
|
||||
index++;
|
||||
}
|
||||
else if(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXACT))
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
|
||||
{
|
||||
|
|
|
@ -740,7 +740,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc,
|
|||
and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
|
||||
If user wants to abort it, Abort services should be called by user.
|
||||
(+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
|
||||
This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
|
||||
This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
|
||||
Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
|
||||
|
||||
@endverbatim
|
||||
|
@ -758,7 +758,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc,
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
{
|
||||
uint16_t* tmp;
|
||||
uint8_t *tmp = pData;
|
||||
uint32_t tickstart = 0U;
|
||||
|
||||
if(hsc->gState == HAL_SMARTCARD_STATE_READY)
|
||||
|
@ -774,7 +774,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
|
|||
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
|
||||
hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
|
||||
|
||||
/* Init tickstart for timeout managment */
|
||||
/* Init tickstart for timeout management */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
hsc->TxXferSize = Size;
|
||||
|
@ -786,9 +786,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
|
|||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
tmp = (uint16_t*) pData;
|
||||
hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
|
||||
pData +=1U;
|
||||
hsc->Instance->DR = (uint8_t)(*tmp & 0xFFU);
|
||||
tmp++;
|
||||
}
|
||||
|
||||
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
|
||||
|
@ -821,7 +820,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
{
|
||||
uint16_t* tmp;
|
||||
uint8_t *tmp = pData;
|
||||
uint32_t tickstart = 0U;
|
||||
|
||||
if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
|
||||
|
@ -837,7 +836,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
|
|||
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
|
||||
hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
|
||||
|
||||
/* Init tickstart for timeout managment */
|
||||
/* Init tickstart for timeout management */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
hsc->RxXferSize = Size;
|
||||
|
@ -851,9 +850,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
|
|||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
tmp = (uint16_t*) pData;
|
||||
*tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
|
||||
pData +=1U;
|
||||
*tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFFU);
|
||||
tmp++;
|
||||
}
|
||||
|
||||
/* At end of Rx process, restore hsc->RxState to Ready */
|
||||
|
@ -1999,14 +1997,12 @@ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc)
|
|||
*/
|
||||
static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
|
||||
{
|
||||
uint16_t* tmp;
|
||||
|
||||
/* Check that a Tx process is ongoing */
|
||||
if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)
|
||||
{
|
||||
tmp = (uint16_t*) hsc->pTxBuffPtr;
|
||||
hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
|
||||
hsc->pTxBuffPtr += 1U;
|
||||
hsc->Instance->DR = (uint8_t)(*hsc->pTxBuffPtr & 0xFFU);
|
||||
hsc->pTxBuffPtr++;
|
||||
|
||||
if(--hsc->TxXferCount == 0U)
|
||||
{
|
||||
|
@ -2061,14 +2057,12 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
|
|||
*/
|
||||
static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
|
||||
{
|
||||
uint16_t* tmp;
|
||||
|
||||
/* Check that a Rx process is ongoing */
|
||||
if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
|
||||
{
|
||||
tmp = (uint16_t*) hsc->pRxBuffPtr;
|
||||
*tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
|
||||
hsc->pRxBuffPtr += 1U;
|
||||
*hsc->pRxBuffPtr = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFFU);
|
||||
hsc->pRxBuffPtr++;
|
||||
|
||||
if(--hsc->RxXferCount == 0U)
|
||||
{
|
||||
|
|
|
@ -1925,14 +1925,12 @@ static HAL_StatusTypeDef SMBUS_MasterTransmit_TXE(SMBUS_HandleTypeDef *hsmbus)
|
|||
{
|
||||
/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
|
||||
uint32_t CurrentState = hsmbus->State;
|
||||
uint32_t CurrentMode = hsmbus->Mode;
|
||||
uint32_t CurrentXferOptions = hsmbus->XferOptions;
|
||||
|
||||
if ((hsmbus->XferSize == 0U) && (CurrentState == HAL_SMBUS_STATE_BUSY_TX))
|
||||
{
|
||||
/* Call TxCpltCallback() directly if no stop mode is set */
|
||||
if (((CurrentXferOptions != SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || (CurrentXferOptions != SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)) && \
|
||||
((CurrentXferOptions != SMBUS_LAST_FRAME_NO_PEC) || (CurrentXferOptions != SMBUS_LAST_FRAME_WITH_PEC)) && (CurrentXferOptions != SMBUS_NO_OPTION_FRAME))
|
||||
if (((CurrentXferOptions == SMBUS_FIRST_FRAME) || (CurrentXferOptions == SMBUS_NEXT_FRAME)) && (CurrentXferOptions != SMBUS_NO_OPTION_FRAME))
|
||||
{
|
||||
__HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR);
|
||||
|
||||
|
@ -2017,7 +2015,7 @@ static HAL_StatusTypeDef SMBUS_MasterTransmit_BTF(SMBUS_HandleTypeDef *hsmbus)
|
|||
else
|
||||
{
|
||||
/* Call TxCpltCallback() directly if no stop mode is set */
|
||||
if (((CurrentXferOptions != SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || (CurrentXferOptions != SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)) && ((CurrentXferOptions != SMBUS_LAST_FRAME_NO_PEC) || (CurrentXferOptions != SMBUS_LAST_FRAME_WITH_PEC)) && (CurrentXferOptions != SMBUS_NO_OPTION_FRAME))
|
||||
if (((CurrentXferOptions == SMBUS_FIRST_FRAME) || (CurrentXferOptions == SMBUS_NEXT_FRAME)) && (CurrentXferOptions != SMBUS_NO_OPTION_FRAME))
|
||||
{
|
||||
__HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR);
|
||||
|
||||
|
@ -2166,7 +2164,7 @@ static HAL_StatusTypeDef SMBUS_MasterReceive_BTF(SMBUS_HandleTypeDef *hsmbus)
|
|||
else if (hsmbus->XferCount == 2U)
|
||||
{
|
||||
/* Prepare next transfer or stop current transfer */
|
||||
if ((CurrentXferOptions == SMBUS_NEXT_FRAME) || (CurrentXferOptions == SMBUS_FIRST_FRAME) || (CurrentXferOptions == SMBUS_LAST_FRAME_NO_PEC))
|
||||
if ((CurrentXferOptions == SMBUS_NEXT_FRAME) || (CurrentXferOptions == SMBUS_FIRST_FRAME))
|
||||
{
|
||||
/* Disable Acknowledge */
|
||||
CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
|
||||
|
@ -2268,8 +2266,6 @@ static HAL_StatusTypeDef SMBUS_Master_ADD10(SMBUS_HandleTypeDef *hsmbus)
|
|||
static HAL_StatusTypeDef SMBUS_Master_ADDR(SMBUS_HandleTypeDef *hsmbus)
|
||||
{
|
||||
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
|
||||
uint32_t CurrentMode = hsmbus->Mode;
|
||||
uint32_t CurrentXferOptions = hsmbus->XferOptions;
|
||||
uint32_t Prev_State = hsmbus->PreviousState;
|
||||
|
||||
if (hsmbus->State == HAL_SMBUS_STATE_BUSY_RX)
|
||||
|
@ -2711,7 +2707,6 @@ static void SMBUS_ITError(SMBUS_HandleTypeDef *hsmbus)
|
|||
}
|
||||
|
||||
/* Call user error callback */
|
||||
HAL_SMBUS_ErrorCallback(hsmbus);
|
||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
||||
hsmbus->ErrorCallback(hsmbus);
|
||||
#else
|
||||
|
|
|
@ -93,7 +93,7 @@
|
|||
|
||||
The compilation define USE_HAL_SPDIFRX_REGISTER_CALLBACKS when set to 1
|
||||
allows the user to configure dynamically the driver callbacks.
|
||||
Use HAL_SPDIFRX_RegisterCallback() funtion to register an interrupt callback.
|
||||
Use HAL_SPDIFRX_RegisterCallback() function to register an interrupt callback.
|
||||
|
||||
The HAL_SPDIFRX_RegisterCallback() function allows to register the following callbacks:
|
||||
(+) RxHalfCpltCallback : SPDIFRX Data flow half completed callback.
|
||||
|
@ -841,7 +841,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif,
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
|
||||
{
|
||||
register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
|
||||
uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
|
||||
|
||||
const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
|
||||
|
||||
|
@ -926,7 +926,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
|
||||
{
|
||||
register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
|
||||
uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
|
||||
|
||||
const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
|
||||
|
||||
|
@ -1011,7 +1011,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
|
||||
{
|
||||
register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
|
||||
uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
|
||||
|
||||
const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
|
||||
|
||||
|
@ -1112,7 +1112,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
|
||||
{
|
||||
register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
|
||||
uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
|
||||
|
||||
const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
|
||||
|
||||
|
|
|
@ -131,7 +131,7 @@
|
|||
DataSize = SPI_DATASIZE_8BIT:
|
||||
+----------------------------------------------------------------------------------------------+
|
||||
| | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
|
||||
| Process | Tranfert mode |---------------------|----------------------|----------------------|
|
||||
| Process | Transfer mode |---------------------|----------------------|----------------------|
|
||||
| | | Master | Slave | Master | Slave | Master | Slave |
|
||||
|==============================================================================================|
|
||||
| T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
|
||||
|
@ -156,7 +156,7 @@
|
|||
DataSize = SPI_DATASIZE_16BIT:
|
||||
+----------------------------------------------------------------------------------------------+
|
||||
| | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
|
||||
| Process | Tranfert mode |---------------------|----------------------|----------------------|
|
||||
| Process | Transfer mode |---------------------|----------------------|----------------------|
|
||||
| | | Master | Slave | Master | Slave | Master | Slave |
|
||||
|==============================================================================================|
|
||||
| T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
|
||||
|
@ -331,6 +331,24 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
|||
{
|
||||
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
|
||||
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
|
||||
|
||||
if (hspi->Init.Mode == SPI_MODE_MASTER)
|
||||
{
|
||||
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
|
||||
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
||||
|
||||
/* Force polarity and phase to TI protocaol requirements */
|
||||
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
|
||||
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
|
||||
}
|
||||
#if (USE_SPI_CRC != 0U)
|
||||
assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
|
||||
|
@ -379,19 +397,25 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
|||
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
|
||||
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
|
||||
Communication speed, First bit and CRC calculation state */
|
||||
WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
|
||||
hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
|
||||
hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
|
||||
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
|
||||
(hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
|
||||
(hspi->Init.DataSize & SPI_CR1_DFF) |
|
||||
(hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
|
||||
(hspi->Init.CLKPhase & SPI_CR1_CPHA) |
|
||||
(hspi->Init.NSS & SPI_CR1_SSM) |
|
||||
(hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
|
||||
(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
|
||||
(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
|
||||
|
||||
/* Configure : NSS management, TI Mode */
|
||||
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
|
||||
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
|
||||
|
||||
#if (USE_SPI_CRC != 0U)
|
||||
/*---------------------------- SPIx CRCPOLY Configuration ------------------*/
|
||||
/* Configure : CRC Polynomial */
|
||||
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
|
||||
{
|
||||
WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
|
||||
WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
|
||||
}
|
||||
#endif /* USE_SPI_CRC */
|
||||
|
||||
|
@ -789,6 +813,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
|
|||
/* Configure communication direction : 1Line */
|
||||
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
||||
{
|
||||
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
||||
__HAL_SPI_DISABLE(hspi);
|
||||
SPI_1LINE_TX(hspi);
|
||||
}
|
||||
|
||||
|
@ -909,6 +935,9 @@ error:
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
{
|
||||
#if (USE_SPI_CRC != 0U)
|
||||
__IO uint32_t tmpreg = 0U;
|
||||
#endif /* USE_SPI_CRC */
|
||||
uint32_t tickstart;
|
||||
HAL_StatusTypeDef errorcode = HAL_OK;
|
||||
|
||||
|
@ -964,6 +993,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
|
|||
/* Configure communication direction: 1Line */
|
||||
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
||||
{
|
||||
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
||||
__HAL_SPI_DISABLE(hspi);
|
||||
SPI_1LINE_RX(hspi);
|
||||
}
|
||||
|
||||
|
@ -1058,7 +1089,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
|
|||
}
|
||||
|
||||
/* Read CRC to Flush DR and RXNE flag */
|
||||
READ_REG(hspi->Instance->DR);
|
||||
tmpreg = READ_REG(hspi->Instance->DR);
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg);
|
||||
}
|
||||
#endif /* USE_SPI_CRC */
|
||||
|
||||
|
@ -1101,6 +1134,9 @@ error :
|
|||
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
|
||||
uint32_t Timeout)
|
||||
{
|
||||
#if (USE_SPI_CRC != 0U)
|
||||
__IO uint32_t tmpreg = 0U;
|
||||
#endif /* USE_SPI_CRC */
|
||||
uint16_t initial_TxXferCount;
|
||||
uint32_t tmp_mode;
|
||||
HAL_SPI_StateTypeDef tmp_state;
|
||||
|
@ -1275,7 +1311,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
|
|||
goto error;
|
||||
}
|
||||
/* Read CRC */
|
||||
READ_REG(hspi->Instance->DR);
|
||||
tmpreg = READ_REG(hspi->Instance->DR);
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg);
|
||||
}
|
||||
|
||||
/* Check if CRC error occurred */
|
||||
|
@ -1365,6 +1403,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
|
|||
/* Configure communication direction : 1Line */
|
||||
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
||||
{
|
||||
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
||||
__HAL_SPI_DISABLE(hspi);
|
||||
SPI_1LINE_TX(hspi);
|
||||
}
|
||||
|
||||
|
@ -1452,6 +1492,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
|
|||
/* Configure communication direction : 1Line */
|
||||
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
||||
{
|
||||
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
||||
__HAL_SPI_DISABLE(hspi);
|
||||
SPI_1LINE_RX(hspi);
|
||||
}
|
||||
|
||||
|
@ -1622,6 +1664,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
|
|||
/* Configure communication direction : 1Line */
|
||||
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
||||
{
|
||||
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
||||
__HAL_SPI_DISABLE(hspi);
|
||||
SPI_1LINE_TX(hspi);
|
||||
}
|
||||
|
||||
|
@ -1735,6 +1779,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
|
|||
/* Configure communication direction : 1Line */
|
||||
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
||||
{
|
||||
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
||||
__HAL_SPI_DISABLE(hspi);
|
||||
SPI_1LINE_RX(hspi);
|
||||
}
|
||||
|
||||
|
@ -2685,6 +2731,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
|
|||
{
|
||||
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
|
||||
uint32_t tickstart;
|
||||
#if (USE_SPI_CRC != 0U)
|
||||
__IO uint32_t tmpreg = 0U;
|
||||
#endif /* USE_SPI_CRC */
|
||||
|
||||
/* Init tickstart for timeout management*/
|
||||
tickstart = HAL_GetTick();
|
||||
|
@ -2706,7 +2755,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
|
|||
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
|
||||
}
|
||||
/* Read CRC */
|
||||
READ_REG(hspi->Instance->DR);
|
||||
tmpreg = READ_REG(hspi->Instance->DR);
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg);
|
||||
}
|
||||
#endif /* USE_SPI_CRC */
|
||||
|
||||
|
@ -2769,6 +2820,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
|
|||
{
|
||||
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
|
||||
uint32_t tickstart;
|
||||
#if (USE_SPI_CRC != 0U)
|
||||
__IO uint32_t tmpreg = 0U;
|
||||
#endif /* USE_SPI_CRC */
|
||||
|
||||
/* Init tickstart for timeout management*/
|
||||
tickstart = HAL_GetTick();
|
||||
|
@ -2789,7 +2843,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
|
|||
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
|
||||
}
|
||||
/* Read CRC to Flush DR and RXNE flag */
|
||||
READ_REG(hspi->Instance->DR);
|
||||
tmpreg = READ_REG(hspi->Instance->DR);
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg);
|
||||
}
|
||||
#endif /* USE_SPI_CRC */
|
||||
|
||||
|
@ -3100,8 +3156,12 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
|
|||
*/
|
||||
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
|
||||
{
|
||||
/* Read 8bit CRC to flush Data Regsiter */
|
||||
READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
|
||||
__IO uint32_t tmpreg = 0U;
|
||||
|
||||
/* Read 8bit CRC to flush Data Register */
|
||||
tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg);
|
||||
|
||||
/* Disable RXNE and ERR interrupt */
|
||||
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
|
||||
|
@ -3191,8 +3251,12 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
|
|||
*/
|
||||
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
|
||||
{
|
||||
/* Read 16bit CRC to flush Data Regsiter */
|
||||
READ_REG(hspi->Instance->DR);
|
||||
__IO uint32_t tmpreg = 0U;
|
||||
|
||||
/* Read 16bit CRC to flush Data Register */
|
||||
tmpreg = READ_REG(hspi->Instance->DR);
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg);
|
||||
|
||||
/* Disable RXNE interrupt */
|
||||
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
|
||||
|
@ -3247,8 +3311,12 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
|
|||
*/
|
||||
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
|
||||
{
|
||||
__IO uint32_t tmpreg = 0U;
|
||||
|
||||
/* Read 8bit CRC to flush Data Register */
|
||||
READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
|
||||
tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg);
|
||||
|
||||
SPI_CloseRx_ISR(hspi);
|
||||
}
|
||||
|
@ -3296,8 +3364,12 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
|
|||
*/
|
||||
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
|
||||
{
|
||||
__IO uint32_t tmpreg = 0U;
|
||||
|
||||
/* Read 16bit CRC to flush Data Register */
|
||||
READ_REG(hspi->Instance->DR);
|
||||
tmpreg = READ_REG(hspi->Instance->DR);
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg);
|
||||
|
||||
/* Disable RXNE and ERR interrupt */
|
||||
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
|
||||
|
@ -3403,15 +3475,26 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
|
|||
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
|
||||
uint32_t Timeout, uint32_t Tickstart)
|
||||
{
|
||||
__IO uint32_t count;
|
||||
uint32_t tmp_timeout;
|
||||
uint32_t tmp_tickstart;
|
||||
|
||||
/* Adjust Timeout value in case of end of transfer */
|
||||
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
|
||||
tmp_tickstart = HAL_GetTick();
|
||||
|
||||
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
|
||||
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
|
||||
|
||||
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
|
||||
{
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
|
||||
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
|
||||
{
|
||||
/* Disable the SPI and reset the CRC: the CRC value should be cleared
|
||||
on both master and slave sides in order to resynchronize the master
|
||||
and slave for their respective CRC calculation */
|
||||
on both master and slave sides in order to resynchronize the master
|
||||
and slave for their respective CRC calculation */
|
||||
|
||||
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
|
||||
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
|
||||
|
@ -3436,6 +3519,12 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi,
|
|||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
|
||||
if(count == 0U)
|
||||
{
|
||||
tmp_timeout = 0U;
|
||||
}
|
||||
count--;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -3545,7 +3634,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
|
|||
uint32_t tickstart;
|
||||
__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
|
||||
|
||||
/* Init tickstart for timeout managment*/
|
||||
/* Init tickstart for timeout management */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Disable ERR interrupt */
|
||||
|
@ -3761,6 +3850,7 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
|
|||
*/
|
||||
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
|
||||
{
|
||||
__IO uint32_t tmpreg = 0U;
|
||||
__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
|
||||
|
||||
/* Wait until TXE flag is set */
|
||||
|
@ -3780,8 +3870,10 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
|
|||
/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
|
||||
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
|
||||
|
||||
/* Read CRC to flush Data Register */
|
||||
READ_REG(hspi->Instance->DR);
|
||||
/* Flush Data Register by a blank read */
|
||||
tmpreg = READ_REG(hspi->Instance->DR);
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg);
|
||||
|
||||
hspi->State = HAL_SPI_STATE_ABORT;
|
||||
}
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue