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stm32cube: update stm32f3 to version V1.11.2 

Update Cube version for STM32F3xx series
on https://github.com/STMicroelectronics
from version v1.11.1
to version v1.11.2

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2021-02-17 15:48:11 +01:00 committed by Kumar Gala
parent 06382a9968
commit 8f287a5788
75 changed files with 6124 additions and 3081 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
stm32cube/stm32f3xx/README
View File

@ -6,7 +6,7 @@ Origin:
http://www.st.com/en/embedded-software/stm32cubef3.html
Status:
version v1.11.1
version v1.11.2
Purpose:
ST Microelectronics official MCU package for STM32F3 series.
@ -23,7 +23,7 @@ URL:
https://github.com/STMicroelectronics/STM32CubeF3
Commit:
8fc490e8e4a09996fe4acf75d94411fcf6b1b9d7
86346f63f25b859f93f9603837dcd5be28e8e7bf
Maintained-by:
External
@ -40,12 +40,4 @@ Patch List:
-dos2unix applied
-trailing white spaces removed
*Extend public SetFlashLatency API to all families
The LL_SetFlashLatency public API is now defined for families
beyond G4, L4 and L5. The private function has been made public.
Impacted files:
drivers/include/stm32f3xx_ll_utils.h
drivers/src/stm32f3xx_ll_utils.c
ST Bug tracker ID: 76120
See release_note.html from STM32Cube

187
stm32cube/stm32f3xx/drivers/include/Legacy/stm32_hal_legacy.h
View File

@ -38,7 +38,6 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
/**
* @}
*/
@ -236,12 +235,12 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
#if defined(STM32G4)
#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH)
#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH)
#if defined(STM32G4) || defined(STM32H7)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0)
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@ -306,8 +305,22 @@
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
#endif
#endif /* STM32L4 */
#if defined(STM32G0)
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
#endif
#if defined(STM32H7)
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
@ -365,6 +378,9 @@
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */
/**
@ -566,7 +582,14 @@
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
#endif
#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
@ -624,6 +647,10 @@
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
#endif /* STM32G4 */
#if defined(STM32H7)
@ -737,6 +764,66 @@
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
#endif /* STM32H7 */
#if defined(STM32F3)
/** @brief Constants defining available sources associated to external events.
*/
#define HRTIM_EVENTSRC_1 (0x00000000U)
#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
/** @brief Constants defining the events that can be selected to configure the
* set/reset crossbar of a timer output
*/
#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
/** @brief Constants defining the event filtering applied to external events
* by a timer
*/
#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
/** @brief Constants defining the DLL calibration periods (in micro seconds)
*/
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
#endif /* STM32F3 */
/**
* @}
*/
@ -876,7 +963,7 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
#if defined(STM32L1) || defined(STM32L4)
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@ -967,6 +1054,16 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
#if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
#endif /* STM32H7 */
/**
* @}
*/
@ -1360,6 +1457,30 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@ -1382,6 +1503,12 @@
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
/**
* @}
@ -1412,16 +1539,18 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@ -1440,6 +1569,13 @@
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{
*/
#if defined(STM32G0)
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
#endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
@ -1512,14 +1648,14 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
/**
* @}
*/
@ -3115,9 +3251,8 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32L4)
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@ -3245,7 +3380,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4)
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@ -3353,9 +3488,9 @@
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
/* alias CMSIS for compatibilities */
#define SDIO_IRQn SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler
@ -3368,7 +3503,7 @@
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
#if defined(STM32H7)
#if defined(STM32H7) || defined(STM32L5)
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
@ -3609,12 +3744,12 @@
* @{
*/
#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
#endif
/**
* @}
@ -3623,9 +3758,9 @@
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32L4)
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
#endif
#endif /* STM32L4 || STM32F4 || STM32F7 */
/**
* @}
*/

8
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_adc_ex.h
View File

@ -88,8 +88,9 @@ typedef struct
New conversion starts only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
This parameter can be set to ENABLE or DISABLE.
Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
after the selected trigger occurred (software start or external trigger).
@ -765,6 +766,7 @@ typedef struct
#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_EXTERNALTRIG_T1_CC1
#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_EXTERNALTRIG_T1_CC2
#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_EXTERNALTRIG_T1_CC3
#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_EXTERNALTRIG_T2_CC2
#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_EXTERNALTRIG_EXT_IT11
#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_EXTERNALTRIG_T1_TRGO
#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_EXTERNALTRIG_T1_TRGO2
@ -1633,6 +1635,7 @@ typedef struct
#define ADC1_EXTERNALTRIG_T1_CC1 (0x00000000U)
#define ADC1_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
#define ADC1_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
#define ADC1_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define ADC1_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
#define ADC1_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
#define ADC1_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
@ -3203,6 +3206,7 @@ typedef struct
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \

4
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_cec.h
View File

@ -121,7 +121,7 @@ typedef struct
* b6 Error information
* 0 : No Error
* 1 : Error
* b5 IP initilisation status
* b5 IP initialization status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized. HAL CEC Init function already called)
* b4-b3 (not used)
@ -138,7 +138,7 @@ typedef struct
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 IP initilisation status
* b5 IP initialization status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized)
* b4-b2 (not used)

28
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_def.h
View File

@ -28,9 +28,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx.h"
#if defined USE_LEGACY
#include "Legacy/stm32_hal_legacy.h"
#endif
#include <stddef.h>
/* Exported types ------------------------------------------------------------*/
@ -108,7 +106,14 @@ typedef enum
}while (0U)
#endif /* USE_RTOS */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __weak
#define __weak __attribute__((weak))
#endif
#ifndef __packed
#define __packed __attribute__((packed))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
@ -119,7 +124,14 @@ typedef enum
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
@ -131,7 +143,7 @@ typedef enum
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#if defined (__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
@ -142,9 +154,9 @@ typedef enum
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
/* ARM V4/V5 and V6 & GNU Compiler
-------------------------------
*/
#define __NOINLINE __attribute__ ( (noinline) )

22
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_exti.h
View File

@ -302,21 +302,21 @@ typedef struct
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
#if defined(GPIOH)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \

139
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_hrtim.h
View File

@ -1017,15 +1017,15 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
@ -1137,9 +1137,6 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
/**
* @}
*/
/**
* @}
*/
/** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
* @{
@ -1147,21 +1144,21 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
* by a timer
*/
#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
/**
* @}
*/
@ -2229,18 +2226,18 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
#define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU)
#define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
(((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
(((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \
@ -2250,31 +2247,31 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
#define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
(((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
(((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \
@ -2284,16 +2281,16 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
#define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\

14
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2s.h
View File

@ -182,6 +182,7 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */
/**
* @}
*/
@ -405,6 +406,15 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
tmpreg_udr = ((__HANDLE__)->Instance->SR);\
UNUSED(tmpreg_udr); \
}while(0U)
/** @brief Flush the I2S DR Register.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\
__IO uint32_t tmpreg_dr = 0x00U;\
tmpreg_dr = ((__HANDLE__)->Instance->DR);\
UNUSED(tmpreg_dr); \
}while(0U)
/**
* @}
*/
@ -490,7 +500,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
*/
/** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of I2S SR regsiter.
* @param __SR__ copy of I2S SR register.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
@ -505,7 +515,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
& ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __CR2__ copy of I2S CR2 regsiter.
* @param __CR2__ copy of I2S CR2 register.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable

10
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2s_ex.h
View File

@ -111,6 +111,16 @@ extern "C" {
tmpreg_udr = I2SxEXT((__HANDLE__)->Instance)->SR;\
UNUSED(tmpreg_udr); \
}while(0U)
/** @brief Flush the I2S and I2SExt DR Registers.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2SEXT_FLUSH_RX_DR(__HANDLE__) do{ \
__IO uint32_t tmpreg_dr = 0x00U; \
tmpreg_dr = I2SxEXT((__HANDLE__)->Instance)->DR; \
tmpreg_dr = ((__HANDLE__)->Instance->DR); \
UNUSED(tmpreg_dr); \
}while(0U)
/**
* @}
*/

60
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_irda.h
View File

@ -75,7 +75,8 @@ typedef struct
/**
* @brief HAL IRDA State definition
* @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition).
* @note HAL IRDA State value is a combination of 2 different substates:
* gState and RxState (see @ref IRDA_State_Definition).
* - gState contains IRDA state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@ -86,7 +87,7 @@ typedef struct
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral not initialized. HAL IRDA Init function already called)
* 1 : Init done (Peripheral initialized. HAL IRDA Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@ -103,7 +104,7 @@ typedef struct
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral not initialized)
* 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@ -245,7 +246,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
Value is allowed for RxState only */
#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
Value is result of combination (Or) between gState and RxState values */
Value is result of combination (Or) between
gState and RxState values */
#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
Value is allowed for gState only */
#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error
@ -257,15 +259,15 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
* @{
*/
#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */
#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */
#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
@ -549,9 +551,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
((__HANDLE__)->Instance->CR1 |= (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))):\
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
((__HANDLE__)->Instance->CR2 |= (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))):\
((__HANDLE__)->Instance->CR3 |= (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Disable the specified IRDA interrupt.
* @param __HANDLE__ specifies the IRDA Handle.
@ -565,10 +572,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
((__HANDLE__)->Instance->CR1 &= ~ (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))): \
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
((__HANDLE__)->Instance->CR2 &= ~ (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Check whether the specified IRDA interrupt has occurred or not.
* @param __HANDLE__ specifies the IRDA Handle.
@ -584,8 +595,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \
((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
* @param __HANDLE__ specifies the IRDA Handle.
@ -599,9 +610,10 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \
& IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \
& (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the IRDA Handle.

2
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_irda_ex.h
View File

@ -52,7 +52,7 @@ extern "C" {
#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */
#elif defined(USART_CR1_M)
#define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long frame */
#define IRDA_WORDLENGTH_9B USART_CR1_M /*!< 9-bit long frame */
#endif
/**
* @}

94
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_nand.h
View File

@ -90,10 +90,10 @@ typedef struct
typedef struct
{
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
for 8 bits adressing or words for 16 bits addressing */
for 8 bits addressing or words for 16 bits addressing */
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
for 8 bits adressing or words for 16 bits addressing */
for 8 bits addressing or words for 16 bits addressing */
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
@ -131,9 +131,9 @@ typedef struct
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
void (* MspInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp Init callback */
void (* MspDeInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp DeInit callback */
void (* ItCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND IT callback */
void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */
void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */
#endif
} NAND_HandleTypeDef;
@ -146,7 +146,7 @@ typedef enum
HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */
HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */
HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */
}HAL_NAND_CallbackIDTypeDef;
} HAL_NAND_CallbackIDTypeDef;
/**
* @brief HAL NAND Callback pointer definition
@ -161,8 +161,8 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup NAND_Exported_Macros NAND Exported Macros
* @{
*/
* @{
*/
/** @brief Reset NAND handle state
* @param __HANDLE__ specifies the NAND handle.
@ -192,7 +192,8 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
@ -215,15 +216,23 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
/* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
@ -231,7 +240,8 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressT
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/* NAND callback registering/unregistering */
HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
pNAND_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
#endif
@ -272,34 +282,34 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
/** @defgroup NAND_Private_Constants NAND Private Constants
* @{
*/
#define NAND_DEVICE1 ((uint32_t)0x70000000U)
#define NAND_DEVICE2 ((uint32_t)0x80000000U)
#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
#define NAND_DEVICE1 0x70000000UL
#define NAND_DEVICE2 0x80000000UL
#define NAND_WRITE_TIMEOUT 0x01000000UL
#define CMD_AREA ((uint32_t)(1UL<<16U)) /* A16 = CLE high */
#define ADDR_AREA ((uint32_t)(1UL<<17U)) /* A17 = ALE high */
#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
#define NAND_CMD_AREA_A ((uint8_t)0x00U)
#define NAND_CMD_AREA_B ((uint8_t)0x01U)
#define NAND_CMD_AREA_C ((uint8_t)0x50U)
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
#define NAND_CMD_AREA_A ((uint8_t)0x00)
#define NAND_CMD_AREA_B ((uint8_t)0x01)
#define NAND_CMD_AREA_C ((uint8_t)0x50)
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
#define NAND_CMD_WRITE0 ((uint8_t)0x80U)
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
#define NAND_CMD_ERASE0 ((uint8_t)0x60U)
#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
#define NAND_CMD_READID ((uint8_t)0x90U)
#define NAND_CMD_STATUS ((uint8_t)0x70U)
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
#define NAND_CMD_RESET ((uint8_t)0xFFU)
#define NAND_CMD_WRITE0 ((uint8_t)0x80)
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
#define NAND_CMD_ERASE0 ((uint8_t)0x60)
#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
#define NAND_CMD_READID ((uint8_t)0x90)
#define NAND_CMD_STATUS ((uint8_t)0x70)
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
#define NAND_CMD_RESET ((uint8_t)0xFF)
/* NAND memory status */
#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
#define NAND_BUSY ((uint32_t)0x00000000U)
#define NAND_ERROR ((uint32_t)0x00000001U)
#define NAND_READY ((uint32_t)0x00000040U)
#define NAND_VALID_ADDRESS 0x00000100UL
#define NAND_INVALID_ADDRESS 0x00000200UL
#define NAND_TIMEOUT_ERROR 0x00000400UL
#define NAND_BUSY 0x00000000UL
#define NAND_ERROR 0x00000001UL
#define NAND_READY 0x00000040UL
/**
* @}
*/
@ -316,7 +326,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
* @retval NAND Raw address value
*/
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
(((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
(((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
/**
* @brief NAND memory Column address computation.

52
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_nor.h
View File

@ -121,9 +121,11 @@ typedef struct
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
uint32_t CommandSet; /*!< NOR algorithm command set and control */
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
void (* MspInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp Init callback */
void (* MspDeInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp DeInit callback */
void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */
void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */
#endif
} NOR_HandleTypeDef;
@ -135,7 +137,7 @@ typedef enum
{
HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */
HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */
}HAL_NOR_CallbackIDTypeDef;
} HAL_NOR_CallbackIDTypeDef;
/**
* @brief HAL NOR Callback pointer definition
@ -178,7 +180,8 @@ typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
@ -197,8 +200,10 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
uint32_t uwBufferSize);
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
uint32_t uwBufferSize);
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
@ -206,7 +211,8 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
/* NOR callback registering/unregistering */
HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
pNOR_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
#endif
/**
@ -246,29 +252,29 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
* @{
*/
/* NOR device IDs addresses */
#define MC_ADDRESS ((uint16_t)0x0000U)
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
#define MC_ADDRESS ((uint16_t)0x0000)
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
/* NOR CFI IDs addresses */
#define CFI1_ADDRESS ((uint16_t)0x61U)
#define CFI2_ADDRESS ((uint16_t)0x62U)
#define CFI3_ADDRESS ((uint16_t)0x63U)
#define CFI4_ADDRESS ((uint16_t)0x64U)
#define CFI1_ADDRESS ((uint16_t)0x61)
#define CFI2_ADDRESS ((uint16_t)0x62)
#define CFI3_ADDRESS ((uint16_t)0x63)
#define CFI4_ADDRESS ((uint16_t)0x64)
/* NOR operation wait timeout */
#define NOR_TMEOUT ((uint16_t)0xFFFFU)
#define NOR_TMEOUT ((uint16_t)0xFFFF)
/* NOR memory data width */
#define NOR_MEMORY_8B ((uint8_t)0x0U)
#define NOR_MEMORY_16B ((uint8_t)0x1U)
#define NOR_MEMORY_8B ((uint8_t)0x0)
#define NOR_MEMORY_16B ((uint8_t)0x1)
/* NOR memory device read/write start address */
#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
#define NOR_MEMORY_ADRESS1 (0x60000000U)
#define NOR_MEMORY_ADRESS2 (0x64000000U)
#define NOR_MEMORY_ADRESS3 (0x68000000U)
#define NOR_MEMORY_ADRESS4 (0x6C000000U)
/**
* @}
*/
@ -285,7 +291,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
* @retval NOR shifted address value
*/
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))

23
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pccard.h
View File

@ -80,9 +80,9 @@ typedef struct
HAL_LockTypeDef Lock; /*!< PCCARD Lock */
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
void (* MspInitCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD Msp Init callback */
void (* MspDeInitCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD Msp DeInit callback */
void (* ItCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD IT callback */
void (* MspInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp Init callback */
void (* MspDeInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp DeInit callback */
void (* ItCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD IT callback */
#endif
} PCCARD_HandleTypeDef;
@ -95,7 +95,7 @@ typedef enum
HAL_PCCARD_MSP_INIT_CB_ID = 0x00U, /*!< PCCARD MspInit Callback ID */
HAL_PCCARD_MSP_DEINIT_CB_ID = 0x01U, /*!< PCCARD MspDeInit Callback ID */
HAL_PCCARD_IT_CB_ID = 0x02U /*!< PCCARD IT Callback ID */
}HAL_PCCARD_CallbackIDTypeDef;
} HAL_PCCARD_CallbackIDTypeDef;
/**
* @brief HAL PCCARD Callback pointer definition
@ -137,7 +137,8 @@ typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming,
FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
@ -150,8 +151,10 @@ void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
@ -159,8 +162,10 @@ void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
/* PCCARD callback registering/unregistering */
HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, pPCCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId);
HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId,
pPCCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard,
HAL_PCCARD_CallbackIDTypeDef CallbackId);
#endif
/**
* @}

16
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_rtc.h
View File

@ -106,12 +106,11 @@ typedef struct
with [1 Sec / SecondFraction +1] granularity.
This field will be used only by HAL_RTC_GetTime function */
uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight
Saving Time, please use HAL_RTC_DST_xxx functions */
uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
in CR register to store the operation.
This parameter can be a value of @ref RTC_StoreOperation_Definitions */
uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight
Saving Time, please use HAL_RTC_DST_xxx functions */
} RTC_TimeTypeDef;
/**
@ -705,6 +704,13 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
/* RTC Daylight Saving Time functions *****************************************/
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
/**
* @}
*/

126
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_smartcard.h
View File

@ -52,7 +52,8 @@ typedef struct
where usart_ker_ckpres is the USART input clock divided by a prescaler */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
This parameter @ref SMARTCARD_Word_Length can only be
set to 9 (8 data + 1 parity bits). */
uint32_t StopBits; /*!< Specifies the number of stop bits.
This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
@ -76,13 +77,14 @@ typedef struct
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref SMARTCARD_Last_Bit */
uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
Selecting the single sample method increases the receiver tolerance to clock
deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote
is selected. Selecting the single sample method increases
the receiver tolerance to clock deviations. This parameter can be a value
of @ref SMARTCARD_OneBit_Sampling. */
uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler.
This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied
by 2 to give the division factor of the source clock frequency */
This parameter can be any value from 0x01 to 0x1F. Prescaler value is
multiplied by 2 to give the division factor of the source clock frequency */
uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */
@ -108,7 +110,7 @@ typedef struct
} SMARTCARD_InitTypeDef;
/**
* @brief SMARTCARD advanced features initalization structure definition
* @brief SMARTCARD advanced features initialization structure definition
*/
typedef struct
{
@ -138,14 +140,16 @@ typedef struct
uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
This parameter can be a value of @ref SMARTCARD_MSB_First */
uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
relevant flag is available) or once guard time period has elapsed.
This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */
uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
relevant flag is available) or once guard time period has elapsed.
This parameter can be a value
of @ref SMARTCARDEx_Transmission_Completion_Indication. */
} SMARTCARD_AdvFeatureInitTypeDef;
/**
* @brief HAL SMARTCARD State definition
* @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition).
* @note HAL SMARTCARD State value is a combination of 2 different substates:
* gState and RxState (see @ref SMARTCARD_State_Definition).
* - gState contains SMARTCARD state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@ -156,7 +160,7 @@ typedef struct
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called)
* 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@ -173,7 +177,7 @@ typedef struct
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral not initialized)
* 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@ -218,12 +222,14 @@ typedef struct __SMARTCARD_HandleTypeDef
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
__IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global
Handle management and also related to Tx operations.
This parameter can be a value
of @ref HAL_SMARTCARD_StateTypeDef */
__IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
This parameter can be a value
of @ref HAL_SMARTCARD_StateTypeDef */
__IO uint32_t ErrorCode; /*!< SmartCard Error code */
@ -297,23 +303,26 @@ typedef enum
/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
* @{
*/
#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
Value is allowed for gState and RxState */
#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value
is allowed for gState and RxState */
#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for
use. Value is allowed for gState
and RxState */
#define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing
Value is allowed for gState only */
Value is allowed for gState only */
#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
Value is allowed for gState only */
Value is allowed for gState only */
#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
Value is allowed for RxState only */
#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
Value is result of combination (Or) between gState and RxState values */
#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception
process is ongoing Not to be used for
neither gState nor RxState.
Value is result of combination (Or)
between gState and RxState values */
#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
Value is allowed for gState only */
Value is allowed for gState only */
#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error
Value is allowed for gState only */
Value is allowed for gState only */
/**
* @}
*/
@ -321,15 +330,15 @@ typedef enum
/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
* @{
*/
#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */
#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */
#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */
#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */
#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */
#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @}
@ -631,9 +640,16 @@ typedef enum
* @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
SMARTCARD_CR_POS) == 1U)?\
((__HANDLE__)->Instance->CR1 |= (1UL <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))):\
((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
SMARTCARD_CR_POS) == 2U)?\
((__HANDLE__)->Instance->CR2 |= (1UL <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1UL <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Disable the specified SmartCard interrupt.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@ -649,9 +665,16 @@ typedef enum
* @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
SMARTCARD_CR_POS) == 1U)?\
((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
SMARTCARD_CR_POS) == 2U)?\
((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Check whether the specified SmartCard interrupt has occurred or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@ -668,7 +691,9 @@ typedef enum
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
& (0x01UL << (((__INTERRUPT__)\
& SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U)\
? SET : RESET)
/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@ -684,9 +709,15 @@ typedef enum
* @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
SMARTCARD_CR_POS) == 0x01U)?\
(__HANDLE__)->Instance->CR1 : \
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
SMARTCARD_CR_POS) == 0x02U)?\
(__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) &\
(0x01UL << (((uint16_t)(__INTERRUPT__))\
& SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@ -940,7 +971,8 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
pSMARTCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */

48
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_spi.h
View File

@ -582,7 +582,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
/** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of SPI SR regsiter.
* @param __SR__ copy of SPI SR register.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
@ -596,10 +596,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @arg SPI_FLAG_FRLVL: SPI fifo reception level
* @retval SET or RESET.
*/
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __CR2__ copy of SPI CR2 regsiter.
* @param __CR2__ copy of SPI CR2 register.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
@ -607,15 +608,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @arg SPI_IT_ERR: Error interrupt enable
* @retval SET or RESET.
*/
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
(__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if SPI Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Mode.
* This parameter can be a value of @ref SPI_Mode
* @retval None
*/
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
((__MODE__) == SPI_MODE_MASTER))
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
((__MODE__) == SPI_MODE_MASTER))
/** @brief Checks if SPI Direction Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Direction Mode.
@ -663,33 +665,33 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* This parameter can be a value of @ref SPI_Clock_Polarity
* @retval None
*/
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
((__CPOL__) == SPI_POLARITY_HIGH))
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
((__CPOL__) == SPI_POLARITY_HIGH))
/** @brief Checks if SPI Clock Phase parameter is in allowed range.
* @param __CPHA__ specifies the SPI Clock Phase.
* This parameter can be a value of @ref SPI_Clock_Phase
* @retval None
*/
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
((__CPHA__) == SPI_PHASE_2EDGE))
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
((__CPHA__) == SPI_PHASE_2EDGE))
/** @brief Checks if SPI Slave Select parameter is in allowed range.
* @param __NSS__ specifies the SPI Slave Select management parameter.
* This parameter can be a value of @ref SPI_Slave_Select_management
* @retval None
*/
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
((__NSS__) == SPI_NSS_HARD_INPUT) || \
((__NSS__) == SPI_NSS_HARD_OUTPUT))
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
((__NSS__) == SPI_NSS_HARD_INPUT) || \
((__NSS__) == SPI_NSS_HARD_OUTPUT))
/** @brief Checks if SPI NSS Pulse parameter is in allowed range.
* @param __NSSP__ specifies the SPI NSS Pulse Mode parameter.
* This parameter can be a value of @ref SPI_NSSP_Mode
* @retval None
*/
#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
((__NSSP__) == SPI_NSS_PULSE_DISABLE))
#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
((__NSSP__) == SPI_NSS_PULSE_DISABLE))
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
* @param __PRESCALER__ specifies the SPI Baudrate prescaler.
@ -710,16 +712,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* This parameter can be a value of @ref SPI_MSB_LSB_transmission
* @retval None
*/
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
((__BIT__) == SPI_FIRSTBIT_LSB))
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
((__BIT__) == SPI_FIRSTBIT_LSB))
/** @brief Checks if SPI TI mode parameter is in allowed range.
* @param __MODE__ specifies the SPI TI mode.
* This parameter can be a value of @ref SPI_TI_mode
* @retval None
*/
#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
((__MODE__) == SPI_TIMODE_ENABLE))
#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
((__MODE__) == SPI_TIMODE_ENABLE))
/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
* @param __CALCULATION__ specifies the SPI CRC calculation enable state.
@ -734,8 +736,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* This parameter can be a value of @ref SPI_CRC_length
* @retval None
*/
#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\
((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \
#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \
((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \
((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
@ -743,7 +745,9 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535
* @retval None
*/
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
((__POLYNOMIAL__) <= 0xFFFFU) && \
(((__POLYNOMIAL__)&0x1U) != 0U))
/** @brief Checks if DMA handle is valid.
* @param __HANDLE__ specifies a DMA Handle.

63
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_sram.h
View File

@ -77,10 +77,10 @@ typedef struct
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
void (* MspInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp Init callback */
void (* MspDeInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp DeInit callback */
void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Complete callback */
void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Error callback */
void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */
void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */
void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */
void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */
#endif
} SRAM_HandleTypeDef;
@ -94,7 +94,7 @@ typedef enum
HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */
HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */
HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */
}HAL_SRAM_CallbackIDTypeDef;
} HAL_SRAM_CallbackIDTypeDef;
/**
* @brief HAL SRAM Callback pointer definition
@ -110,8 +110,8 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
* @{
*/
* @{
*/
/** @brief Reset SRAM handle state
* @param __HANDLE__ SRAM handle
@ -137,11 +137,12 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
*/
/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
@ -151,27 +152,37 @@ void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
*/
/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
* @{
*/
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
uint32_t BufferSize);
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
/* SRAM callback registering/unregistering */
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
pSRAM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
pSRAM_DmaCallbackTypeDef pCallback);
#endif
/**
@ -179,8 +190,8 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR
*/
/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
* @{
*/
* @{
*/
/* SRAM Control functions ****************************************************/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
@ -191,8 +202,8 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
*/
/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
* @{
*/
* @{
*/
/* SRAM State functions ******************************************************/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);

285
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_tim.h
View File

@ -308,6 +308,26 @@ typedef enum
HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
} HAL_TIM_StateTypeDef;
/**
* @brief TIM Channel States definition
*/
typedef enum
{
HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
} HAL_TIM_ChannelStateTypeDef;
/**
* @brief DMA Burst States definition
*/
typedef enum
{
HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
} HAL_TIM_DMABurstStateTypeDef;
/**
* @brief HAL Active channel structures definition
*/
@ -335,13 +355,16 @@ typedef struct __TIM_HandleTypeDef
typedef struct
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
{
TIM_TypeDef *Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
This array is accessed by a @ref DMA_Handle_index */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
TIM_TypeDef *Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
This array is accessed by a @ref DMA_Handle_index */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
__IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */
__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
__IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
@ -383,36 +406,36 @@ typedef struct
*/
typedef enum
{
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
, HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
#if defined(TIM_BDTR_BK2E)
,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
, HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
#endif /* TIM_BDTR_BK2E */
} HAL_TIM_CallbackIDTypeDef;
@ -538,6 +561,17 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @}
*/
#if defined(TIM_CR1_UIFREMAP)
/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
* @{
*/
#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */
#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */
/**
* @}
*/
#endif /* TIM_CR1_UIFREMAP */
/** @defgroup TIM_ClockDivision TIM Clock Division
* @{
*/
@ -1115,25 +1149,49 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @retval None
*/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
(__HANDLE__)->Base_MspInitCallback = NULL; \
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
(__HANDLE__)->IC_MspInitCallback = NULL; \
(__HANDLE__)->IC_MspDeInitCallback = NULL; \
(__HANDLE__)->OC_MspInitCallback = NULL; \
(__HANDLE__)->OC_MspDeInitCallback = NULL; \
(__HANDLE__)->PWM_MspInitCallback = NULL; \
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
(__HANDLE__)->Encoder_MspInitCallback = NULL; \
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
(__HANDLE__)->Base_MspInitCallback = NULL; \
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
(__HANDLE__)->IC_MspInitCallback = NULL; \
(__HANDLE__)->IC_MspDeInitCallback = NULL; \
(__HANDLE__)->OC_MspInitCallback = NULL; \
(__HANDLE__)->OC_MspDeInitCallback = NULL; \
(__HANDLE__)->PWM_MspInitCallback = NULL; \
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
(__HANDLE__)->Encoder_MspInitCallback = NULL; \
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
} while(0)
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
@ -1334,6 +1392,33 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @retval None
*/
#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
#if defined(TIM_CR1_UIFREMAP)
/**
* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
* @param __HANDLE__ TIM handle.
* @retval None
mode.
*/
#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
/**
* @brief Disable update interrupt flag (UIF) remapping.
* @param __HANDLE__ TIM handle.
* @retval None
mode.
*/
#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
/**
* @brief Get update interrupt flag (UIF) copy status.
* @param __COUNTER__ Counter value.
* @retval The state of UIFCPY (TRUE or FALSE).
mode.
*/
#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
#endif /* TIM_CR1_UIFREMAP */
/**
* @brief Indicates whether or not the TIM Counter is used as downcounter.
@ -1354,6 +1439,8 @@ mode.
/**
* @brief Set the TIM Counter Register value on runtime.
* Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.
* Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
* @param __HANDLE__ TIM handle.
* @param __COUNTER__ specifies the Counter register new value.
* @retval None
@ -1778,6 +1865,11 @@ mode.
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
#if defined(TIM_CR1_UIFREMAP)
#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
((__MODE__) == TIM_UIFREMAP_ENALE))
#endif /* TIM_CR1_UIFREMAP */
#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV4))
@ -2025,15 +2117,15 @@ mode.
#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
@ -2081,6 +2173,71 @@ mode.
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E)
#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
(__HANDLE__)->ChannelState[5])
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
(__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \
} while(0)
#else
#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
(__HANDLE__)->ChannelState[3])
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
(__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
} while(0)
#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
(__HANDLE__)->ChannelNState[3])
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
(__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
} while(0)
/**
* @}
*/
@ -2306,6 +2463,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
/* Peripheral Channel state functions ************************************************/
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
/**
* @}
*/
@ -2325,7 +2487,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_DMAError(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);

29
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_tim_ex.h
View File

@ -152,23 +152,23 @@ typedef struct
* @{
*/
#if defined(TIM1) && defined(TIM8) && defined(TIM20) && defined(TIM16)
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM8) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM20) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM8) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM20) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
#elif defined(TIM1) && defined(TIM8) && defined(TIM16)
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM8) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM8) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
#elif defined(TIM1) && defined(TIM16)
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
#elif defined(TIM14)
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
(((__INSTANCE__) == TIM14) && (((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
(((__INSTANCE__) == TIM14) && (((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))
#endif /* TIM1 && TIM8 && TIM20 && TIM16 */
/**
@ -304,6 +304,7 @@ void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
*/
/* Extended Peripheral State functions ***************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
/**
* @}
*/

4
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_tsc.h
View File

@ -634,6 +634,10 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to
((__VALUE__) == TSC_PG_PRESC_DIV64) || \
((__VALUE__) == TSC_PG_PRESC_DIV128))
#define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && ((__CTPL__) > TSC_CTPL_2CYCLES)) || \
(((__PGPSC__) == TSC_PG_PRESC_DIV2) && ((__CTPL__) > TSC_CTPL_1CYCLE)) || \
(((__PGPSC__) > TSC_PG_PRESC_DIV2) && (((__CTPL__) == TSC_CTPL_1CYCLE) || ((__CTPL__) > TSC_CTPL_1CYCLE))))
#define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \
((__VALUE__) == TSC_MCV_511) || \
((__VALUE__) == TSC_MCV_1023) || \

198
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_uart.h
View File

@ -76,7 +76,8 @@ typedef struct
or disabled.
This parameter can be a value of @ref UART_Hardware_Flow_Control. */
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled,
to achieve higher speed (up to f_PCLK/8).
This parameter can be a value of @ref UART_Over_Sampling. */
uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
@ -93,7 +94,8 @@ typedef struct
{
uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
Advanced Features may be initialized at the same time .
This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
This parameter can be a value of
@ref UART_Advanced_Features_Initialization_Type. */
uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
This parameter can be a value of @ref UART_Tx_Inv. */
@ -127,7 +129,8 @@ typedef struct
/**
* @brief HAL UART State definition
* @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).
* @note HAL UART State value is a combination of 2 different substates:
* gState and RxState (see @ref UART_State_Definition).
* - gState contains UART state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@ -138,7 +141,7 @@ typedef struct
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral not initialized. HAL UART Init function already called)
* 1 : Init done (Peripheral initialized. HAL UART Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@ -155,7 +158,7 @@ typedef struct
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral not initialized)
* 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@ -179,6 +182,17 @@ typedef enum
UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
} UART_ClockSourceTypeDef;
/**
* @brief HAL UART Reception type definition
* @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
* It is expected to admit following values :
* HAL_UART_RECEPTION_STANDARD = 0x00U,
* HAL_UART_RECEPTION_TOIDLE = 0x01U,
* HAL_UART_RECEPTION_TORTO = 0x02U,
* HAL_UART_RECEPTION_TOCHARMATCH = 0x03U,
*/
typedef uint32_t HAL_UART_RxTypeTypeDef;
/**
* @brief UART handle Structure definition
*/
@ -204,6 +218,8 @@ typedef struct __UART_HandleTypeDef
uint16_t Mask; /*!< UART Rx RDR register mask */
__IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
@ -215,11 +231,11 @@ typedef struct __UART_HandleTypeDef
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_UART_StateTypeDef */
and also related to Tx operations. This parameter
can be a value of @ref HAL_UART_StateTypeDef */
__IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
This parameter can be a value of @ref HAL_UART_StateTypeDef */
__IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This
parameter can be a value of @ref HAL_UART_StateTypeDef */
__IO uint32_t ErrorCode; /*!< UART Error code */
@ -233,6 +249,7 @@ typedef struct __UART_HandleTypeDef
void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */
void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */
void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
@ -265,6 +282,7 @@ typedef enum
* @brief HAL UART Callback pointer definition
*/
typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@ -291,8 +309,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
Value is allowed for RxState only */
#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
Value is result of combination (Or) between gState and RxState values */
Not to be used for neither gState nor RxState.Value is result
of combination (Or) between gState and RxState values */
#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
Value is allowed for gState only */
#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error
@ -304,16 +322,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
/** @defgroup UART_Error_Definition UART Error Definition
* @{
*/
#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */
#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */
#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */
#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */
#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */
#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
@ -391,10 +409,14 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
* @{
*/
#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */
#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */
#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */
#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */
#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection
on start bit */
#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection
on falling edge */
#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection
on 0x7F frame detection */
#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection
on 0x55 frame detection */
/**
* @}
*/
@ -556,8 +578,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
/** @defgroup UART_MSB_First UART Advanced Feature MSB First
* @{
*/
#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */
#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */
#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received
first disable */
#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received
first enable */
/**
* @}
*/
@ -583,7 +607,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
* @{
*/
#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */
#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */
/**
* @}
*/
@ -591,9 +615,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
* @{
*/
#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */
#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */
#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */
#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */
#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */
#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register
not empty or RXFIFO is not empty */
/**
* @}
*/
@ -610,7 +635,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
* @{
*/
#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */
#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB
position in CR1 register */
/**
* @}
*/
@ -618,7 +644,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
* @{
*/
#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB
position in CR1 register */
/**
* @}
*/
@ -687,22 +714,22 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* - ZZZZ : Flag position in the ISR register(4bits)
* @{
*/
#define UART_IT_PE 0x0028U /*!< UART parity error interruption */
#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */
#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */
#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */
#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */
#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */
#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */
#define UART_IT_CM 0x112EU /*!< UART character match interruption */
#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */
#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */
#define UART_IT_PE 0x0028U /*!< UART parity error interruption */
#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */
#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */
#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */
#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */
#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */
#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */
#define UART_IT_CM 0x112EU /*!< UART character match interruption */
#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */
#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */
#define UART_IT_ERR 0x0060U /*!< UART error interruption */
#define UART_IT_ERR 0x0060U /*!< UART error interruption */
#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */
#define UART_IT_NE 0x0200U /*!< UART noise error interruption */
#define UART_IT_FE 0x0100U /*!< UART frame error interruption */
#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */
#define UART_IT_NE 0x0200U /*!< UART noise error interruption */
#define UART_IT_FE 0x0100U /*!< UART frame error interruption */
/**
* @}
*/
@ -725,6 +752,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @}
*/
/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
* @{
*/
#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */
#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */
#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */
/**
* @}
*/
/**
* @}
@ -858,10 +895,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\
((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
((__HANDLE__)->Instance->CR1 |= (1U <<\
((__INTERRUPT__) & UART_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
((__HANDLE__)->Instance->CR2 |= (1U <<\
((__INTERRUPT__) & UART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U <<\
((__INTERRUPT__) & UART_IT_MASK))))
/** @brief Disable the specified UART interrupt.
* @param __HANDLE__ specifies the UART Handle.
@ -880,9 +922,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\
((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
((__INTERRUPT__) & UART_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
((__INTERRUPT__) & UART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
((__INTERRUPT__) & UART_IT_MASK))))
/** @brief Check whether the specified UART interrupt has occurred or not.
* @param __HANDLE__ specifies the UART Handle.
@ -921,9 +969,13 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\
(__HANDLE__)->Instance->CR1 : \
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\
(__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (1U <<\
(((uint16_t)(__INTERRUPT__)) &\
UART_IT_MASK))) != RESET) ? SET : RESET)
/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the UART Handle.
@ -989,8 +1041,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* - macro could only be called when corresponding UART instance is disabled
* (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
* macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
@ -1007,8 +1060,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* - macro could only be called when corresponding UART instance is disabled
* (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
* macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
@ -1025,8 +1079,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* - macro could only be called when corresponding UART instance is disabled
* (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
* macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
@ -1043,8 +1098,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* - macro could only be called when corresponding UART instance is disabled
* (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
* macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
@ -1304,8 +1360,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __AUTOBAUDRATE__ UART auto Baud rate state.
* @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
*/
#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \
UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
/**
* @brief Ensure that UART DMA enabling or disabling on error setting is valid.
@ -1388,6 +1445,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
@ -1426,6 +1486,8 @@ void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
/**
* @}
*/
@ -1471,13 +1533,15 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
* @{
*/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
/**
* @}

6
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_uart_ex.h
View File

@ -119,7 +119,6 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
/**
* @}
*/
@ -136,6 +135,11 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
/**
* @}
*/

79
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_usart.h
View File

@ -48,11 +48,14 @@ typedef struct
{
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
The baud rate is computed using the following formula:
Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4]
Baud Rate Register[15:4] = ((2 * fclk_pres) /
((huart->Init.BaudRate)))[15:4]
Baud Rate Register[3] = 0
Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1
Baud Rate Register[2:0] = (((2 * fclk_pres) /
((huart->Init.BaudRate)))[3:0]) >> 1
where fclk_pres is the USART input clock frequency
@note Oversampling by 8 is systematically applied to achieve high baud rates. */
@note Oversampling by 8 is systematically applied to
achieve high baud rates. */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USARTEx_Word_Length. */
@ -200,15 +203,16 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
/** @defgroup USART_Error_Definition USART Error Definition
* @{
*/
#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */
#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */
/**
* @}
*/
@ -244,15 +248,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @}
*/
/** @defgroup USART_Over_Sampling USART Over Sampling
* @{
*/
#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
/**
* @}
*/
/** @defgroup USART_Clock USART Clock
* @{
*/
@ -311,6 +306,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
#define USART_FLAG_CTSIF USART_ISR_CTSIF /*!< USART clear to send interrupt flag */
#define USART_FLAG_LBDF USART_ISR_LBDF /*!< USART LIN break detection flag */
#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */
#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */
#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */
#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */
@ -357,6 +353,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */
/**
* @}
*/
@ -416,6 +413,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @arg @ref USART_FLAG_TXE Transmit data register empty flag
* @arg @ref USART_FLAG_TC Transmission Complete flag
* @arg @ref USART_FLAG_RXNE Receive data register not empty flag
* @arg @ref USART_FLAG_RTOF Receiver Timeout flag
* @arg @ref USART_FLAG_IDLE Idle Line detection flag
* @arg @ref USART_FLAG_ORE OverRun Error flag
* @arg @ref USART_FLAG_NE Noise Error flag
@ -435,6 +433,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag
* @arg @ref USART_CLEAR_CTSF
* @retval None
*/
@ -484,9 +483,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Disable the specified USART interrupt.
* @param __HANDLE__ specifies the USART Handle.
@ -500,10 +502,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Check whether the specified USART interrupt has occurred or not.
* @param __HANDLE__ specifies the USART Handle.
@ -520,7 +524,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
& (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
USART_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified USART interrupt source is enabled or not.
* @param __HANDLE__ specifies the USART Handle.
@ -536,10 +541,13 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \
(((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET)
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
(__HANDLE__)->Instance->CR1 : \
(((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
(__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (0x01U <<\
(((uint16_t)(__INTERRUPT__)) &\
USART_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the USART Handle.
@ -551,6 +559,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @arg @ref USART_CLEAR_CTSF CTS Interrupt Clear Flag
* @retval None
@ -641,14 +650,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
*/
#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
/**
* @brief Ensure that USART oversampling is valid.
* @param __SAMPLING__ USART oversampling.
* @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
*/
#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
((__SAMPLING__) == USART_OVERSAMPLING_8))
/**
* @brief Ensure that USART clock state is valid.
* @param __CLOCK__ USART clock state.

6
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_usart_ex.h
View File

@ -46,12 +46,12 @@ extern "C" {
* @{
*/
#if defined(USART_CR1_M0)&& defined(USART_CR1_M1)
#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */
#elif defined(USART_CR1_M)
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long USART frame */
#define USART_WORDLENGTH_9B (USART_CR1_M) /*!< 9-bit long USART frame */
#endif
/**
* @}

21
stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_wwdg.h
View File

@ -56,7 +56,7 @@ typedef struct
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
This parameter can be a value of @ref WWDG_EWI_Mode */
} WWDG_InitTypeDef;
@ -68,17 +68,17 @@ typedef struct
typedef struct __WWDG_HandleTypeDef
#else
typedef struct
#endif
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
{
WWDG_TypeDef *Instance; /*!< Register base address */
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
#endif
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
} WWDG_HandleTypeDef;
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
@ -87,8 +87,8 @@ typedef struct
*/
typedef enum
{
HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */
HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */
} HAL_WWDG_CallbackIDTypeDef;
/**
@ -96,7 +96,7 @@ typedef enum
*/
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
#endif
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
*/
@ -260,9 +260,10 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
pWWDG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
#endif
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}

113
stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_adc.h
View File

@ -934,6 +934,7 @@ typedef struct
#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
@ -2491,7 +2492,7 @@ typedef struct
#if defined(ADC_MULTIMODE_SUPPORT)
__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
{
register uint32_t data_reg_addr = 0U;
uint32_t data_reg_addr = 0U;
if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
{
@ -2791,9 +2792,12 @@ __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
* Moreover, this avoids risk of overrun for low frequency
* applications.
* How to use this low power mode:
* - Do not use with interruption or DMA since these modes
* have to clear immediately the EOC flag to free the
* IRQ vector sequencer.
* - It is not recommended to use with interruption or DMA
* since these modes have to clear immediately the EOC flag
* (by CPU to free the IRQ pending event or by DMA).
* Auto wait will work but fort a very short time, discarding
* its intended benefit (except specific case of high load of CPU
* or DMA transfers which can justify usage of auto wait).
* - Do use with polling: 1. Start conversion,
* 2. Later on, when conversion data is needed: poll for end of
* conversion to ensure that conversion is completed and
@ -2844,9 +2848,12 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower
* Moreover, this avoids risk of overrun for low frequency
* applications.
* How to use this low power mode:
* - Do not use with interruption or DMA since these modes
* have to clear immediately the EOC flag to free the
* IRQ vector sequencer.
* - It is not recommended to use with interruption or DMA
* since these modes have to clear immediately the EOC flag
* (by CPU to free the IRQ pending event or by DMA).
* Auto wait will work but fort a very short time, discarding
* its intended benefit (except specific case of high load of CPU
* or DMA transfers which can justify usage of auto wait).
* - Do use with polling: 1. Start conversion,
* 2. Later on, when conversion data is needed: poll for end of
* conversion to ensure that conversion is completed and
@ -2951,7 +2958,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
MODIFY_REG(*preg,
ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
@ -3024,7 +3031,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
}
@ -3050,7 +3057,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
}
@ -3083,7 +3090,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offse
*/
__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
{
register __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)
__IO uint32_t *preg = (__IO uint32_t *)((uint32_t)
((uint32_t)(&ADCx->OFR1) + (Offsety*4U)));
MODIFY_REG(*preg,
@ -3110,7 +3117,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety,
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
}
@ -3283,11 +3290,11 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
{
register uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
/* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
/* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
/* to match with triggers literals definition. */
@ -3613,11 +3620,11 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
MODIFY_REG(*preg,
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
(Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK)));
((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
}
/**
@ -3714,11 +3721,11 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
return (uint32_t) (READ_BIT(*preg,
return (uint32_t) ((READ_BIT(*preg,
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
<< (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK))
>> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
);
}
@ -4038,11 +4045,11 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
{
register uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
/* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
/* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
/* to match with triggers literals definition. */
@ -4263,8 +4270,8 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
MODIFY_REG(ADCx->JSQR,
ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)),
(Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)));
(ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
}
/**
@ -4333,9 +4340,9 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
return (uint32_t)(READ_BIT(ADCx->JSQR,
ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)))
<< (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
return (uint32_t)((READ_BIT(ADCx->JSQR,
(ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
>> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
);
}
@ -4817,7 +4824,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
MODIFY_REG(*preg,
ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
@ -4901,7 +4908,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C
*/
__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
return (uint32_t)(READ_BIT(*preg,
ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
@ -5173,7 +5180,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t
/* in register and register position depending on parameter "AWDy". */
/* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
/* containing other bits reserved for other purpose. */
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
+ ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
MODIFY_REG(*preg,
@ -5305,12 +5312,12 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
+ ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
/* Variable "AWDy" used to retrieve appropriate bitfield corresponding to */
/* ADC_AWD_CR1_CHANNEL_MASK or ADC_AWD_CR23_CHANNEL_MASK. */
register uint32_t AWD123ChannelGroup = READ_BIT(*preg, (AWDy | ADC_AWD_CR_ALL_CHANNEL_MASK));
uint32_t AWD123ChannelGroup = READ_BIT(*preg, (AWDy | ADC_AWD_CR_ALL_CHANNEL_MASK));
/* Set variable of AWD1 monitored channel according to AWD1 features */
/* and ADC channel definition: */
@ -5319,9 +5326,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint
/* - AWD1 single or all channels */
/* - AWD1 enable or disable (also used to discard AWD1 bitfield in case of */
/* AWD2 or AWD3 selected). */
register uint32_t AWD1ChannelSingle = ((AWD123ChannelGroup & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS);
uint32_t AWD1ChannelSingle = ((AWD123ChannelGroup & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS);
register uint32_t AWD1ChannelGroup = ( ( AWD123ChannelGroup
uint32_t AWD1ChannelGroup = ( ( AWD123ChannelGroup
| ((ADC_CHANNEL_0_BITFIELD << ((AWD123ChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)) * AWD1ChannelSingle)
| (ADC_CHANNEL_ID_BITFIELD_MASK * (~AWD1ChannelSingle & ((uint32_t)0x00000001U)))
)
@ -5340,9 +5347,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint
/* is activated, therefore the channel monitoring value channel "3" */
/* is not not supported by this function, there is no risk of */
/* conflict. */
register uint32_t AWD23Enabled = ((((uint32_t)0x00000001U) >> (AWD123ChannelGroup % 3U)) << 6U); /* Value "0" if AWD2-3 is enabled, value "32" if AWD2-3 is disabled */
uint32_t AWD23Enabled = ((((uint32_t)0x00000001U) >> (AWD123ChannelGroup % 3U)) << 6U); /* Value "0" if AWD2-3 is enabled, value "32" if AWD2-3 is disabled */
register uint32_t AWD23ChannelGroup = ((( AWD123ChannelGroup
uint32_t AWD23ChannelGroup = ((( AWD123ChannelGroup
| ((uint32_t)POSITION_VAL(AWD123ChannelGroup) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
| ((ADC_CFGR_AWD1SGL) >> ((((uint32_t)0x00000001U) >> (ADC_AWD_CR23_CHANNEL_MASK - AWD123ChannelGroup)) << 5U))
| (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)
@ -5407,7 +5414,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t
/* "AWDy". */
/* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
/* containing other bits reserved for other purpose. */
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
MODIFY_REG(*preg,
ADC_TR1_HT1 | ADC_TR1_LT1,
@ -5471,7 +5478,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW
/* "AWDThresholdsHighLow" and "AWDy". */
/* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
/* containing other bits reserved for other purpose. */
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
MODIFY_REG(*preg,
AWDThresholdsHighLow,
@ -5508,7 +5515,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
return (uint32_t)(READ_BIT(*preg,
(AWDThresholdsHighLow | ADC_TR1_LT1))
@ -6202,7 +6209,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint32_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@ -6229,7 +6236,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@ -6256,7 +6263,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@ -6283,7 +6290,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint
*/
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint8_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@ -6310,7 +6317,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32
*/
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint8_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@ -9278,7 +9285,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
MODIFY_REG(*preg,
ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
@ -9368,7 +9375,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
return (uint32_t) (READ_BIT(*preg,
ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
@ -9834,7 +9841,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
MODIFY_REG(*preg,
ADC_JOFR1_JOFFSET1,
@ -9861,7 +9868,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
return (uint32_t)(READ_BIT(*preg,
ADC_JOFR1_JOFFSET1)
@ -9954,7 +9961,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
MODIFY_REG(*preg,
ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
@ -10023,7 +10030,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C
*/
__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
return (uint32_t)(READ_BIT(*preg,
ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
@ -10247,7 +10254,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
MODIFY_REG(*preg,
ADC_HTR_HT,
@ -10270,7 +10277,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
}
@ -10493,7 +10500,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint32_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@ -10520,7 +10527,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
{
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)

6
stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_comp.h
View File

@ -283,7 +283,7 @@ typedef struct
#define LL_COMP_OUTPUT_TIM2_IC4_COMP2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM1 input capture 4 (specific to COMP instance: COMP2) */
#define LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */
#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */
#define LL_COMP_OUTPUT_TIM3_IC1_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
#define LL_COMP_OUTPUT_TIM3_IC1_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
/* Note: Output redirection specific to COMP instance: COMP4 */
#define LL_COMP_OUTPUT_TIM3_IC3_COMP4 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */
#define LL_COMP_OUTPUT_TIM15_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */
@ -325,7 +325,7 @@ typedef struct
#define LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 input capture 4 (specific to COMP instance: COMP2) */
#define LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */
#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */
#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
/* Note: Output redirection specific to COMP instance: COMP4 */
#define LL_COMP_OUTPUT_TIM3_IC3_COMP4 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */
#define LL_COMP_OUTPUT_TIM4_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 2 (specific to COMP instance: COMP4) */
@ -384,7 +384,7 @@ typedef struct
/* Note: Output redirection specific to COMP instance: COMP1, COMP2 */
#define LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */
#define LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 input capture 4 (specific to COMP instance: COMP2) */
#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
#if defined(STM32F303xE) || defined(STM32F398xx)
#define LL_COMP_OUTPUT_TIM20_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM20 OCREF clear (specific to COMP instance: COMP2) */
#endif

2
stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_exti.h
View File

@ -1139,7 +1139,7 @@ __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
#if defined(EXTI_32_63_SUPPORT)
/**
* @brief Generate a software Interrupt Event for Lines in range 32 to 63
* @note If the interrupt is enabled on this line inthe EXTI_IMR2, writing a 1 to
* @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to
* this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
* resulting in an interrupt request generation.
* This bit is cleared by clearing the corresponding bit in the EXTI_PR2

186
stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_fmc.h
View File

@ -62,7 +62,7 @@ extern "C" {
#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
((__MODE__) == FMC_WRAP_MODE_ENABLE))
((__MODE__) == FMC_WRAP_MODE_ENABLE))
#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
@ -92,9 +92,9 @@ extern "C" {
#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
((__STATE__) == FMC_NAND_ECC_ENABLE))
@ -208,7 +208,7 @@ typedef struct
This parameter is only enabled through the FMC_BCR1 register, and don't care
through FMC_BCR2..4 registers.
This parameter can be a value of @ref FMC_Continous_Clock */
}FMC_NORSRAM_InitTypeDef;
} FMC_NORSRAM_InitTypeDef;
/**
* @brief FMC NORSRAM Timing parameters structure definition
@ -251,7 +251,7 @@ typedef struct
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FMC_Access_Mode */
}FMC_NORSRAM_TimingTypeDef;
} FMC_NORSRAM_TimingTypeDef;
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
@ -282,7 +282,7 @@ typedef struct
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
}FMC_NAND_InitTypeDef;
} FMC_NAND_InitTypeDef;
#endif
#if defined(FMC_BANK3)||defined(FMC_BANK4)
@ -315,7 +315,7 @@ typedef struct
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
}FMC_NAND_PCC_TimingTypeDef;
} FMC_NAND_PCC_TimingTypeDef;
#endif /* FMC_BANK3 */
#if defined(FMC_BANK4)
@ -354,10 +354,10 @@ typedef struct
/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
* @{
*/
#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
#define FMC_NORSRAM_BANK1 (0x00000000U)
#define FMC_NORSRAM_BANK2 (0x00000002U)
#define FMC_NORSRAM_BANK3 (0x00000004U)
#define FMC_NORSRAM_BANK4 (0x00000006U)
/**
* @}
*/
@ -365,8 +365,8 @@ typedef struct
/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
* @{
*/
#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
/**
* @}
*/
@ -374,9 +374,9 @@ typedef struct
/** @defgroup FMC_Memory_Type FMC Memory Type
* @{
*/
#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
#define FMC_MEMORY_TYPE_SRAM (0x00000000U)
#define FMC_MEMORY_TYPE_PSRAM (0x00000004U)
#define FMC_MEMORY_TYPE_NOR (0x00000008U)
/**
* @}
*/
@ -384,9 +384,9 @@ typedef struct
/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
* @{
*/
#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
/**
* @}
*/
@ -394,8 +394,8 @@ typedef struct
/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
* @{
*/
#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
/**
* @}
*/
@ -403,8 +403,8 @@ typedef struct
/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
* @{
*/
#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
/**
* @}
*/
@ -412,8 +412,8 @@ typedef struct
/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
* @{
*/
#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
/**
* @}
*/
@ -421,8 +421,8 @@ typedef struct
/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
* @{
*/
#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U)
#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U)
#define FMC_WRAP_MODE_DISABLE (0x00000000U)
#define FMC_WRAP_MODE_ENABLE (0x00000400U)
/**
* @}
*/
@ -430,8 +430,8 @@ typedef struct
/** @defgroup FMC_Wait_Timing FMC Wait Timing
* @{
*/
#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
#define FMC_WAIT_TIMING_DURING_WS (0x00000800U)
/**
* @}
*/
@ -439,8 +439,8 @@ typedef struct
/** @defgroup FMC_Write_Operation FMC Write Operation
* @{
*/
#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
#define FMC_WRITE_OPERATION_DISABLE (0x00000000U)
#define FMC_WRITE_OPERATION_ENABLE (0x00001000U)
/**
* @}
*/
@ -448,8 +448,8 @@ typedef struct
/** @defgroup FMC_Wait_Signal FMC Wait Signal
* @{
*/
#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U)
#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U)
/**
* @}
*/
@ -457,8 +457,8 @@ typedef struct
/** @defgroup FMC_Extended_Mode FMC Extended Mode
* @{
*/
#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
#define FMC_EXTENDED_MODE_DISABLE (0x00000000U)
#define FMC_EXTENDED_MODE_ENABLE (0x00004000U)
/**
* @}
*/
@ -466,8 +466,8 @@ typedef struct
/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
* @{
*/
#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
/**
* @}
*/
@ -475,8 +475,8 @@ typedef struct
/** @defgroup FMC_Write_Burst FMC Write Burst
* @{
*/
#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
#define FMC_WRITE_BURST_DISABLE (0x00000000U)
#define FMC_WRITE_BURST_ENABLE (0x00080000U)
/**
* @}
*/
@ -484,19 +484,19 @@ typedef struct
/** @defgroup FMC_Continous_Clock FMC Continuous Clock
* @{
*/
#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
/**
* @}
*/
/** @defgroup FMC_Access_Mode FMC Access Mode
/** @defgroup FMC_Access_Mode FMC Access Mode
* @{
*/
#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
#define FMC_ACCESS_MODE_A (0x00000000U)
#define FMC_ACCESS_MODE_B (0x10000000U)
#define FMC_ACCESS_MODE_C (0x20000000U)
#define FMC_ACCESS_MODE_D (0x30000000U)
/**
* @}
*/
@ -514,8 +514,8 @@ typedef struct
/** @defgroup FMC_NAND_Bank FMC NAND Bank
* @{
*/
#define FMC_NAND_BANK2 ((uint32_t)0x00000010U)
#define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
#define FMC_NAND_BANK2 (0x00000010U)
#define FMC_NAND_BANK3 (0x00000100U)
/**
* @}
*/
@ -523,8 +523,8 @@ typedef struct
/** @defgroup FMC_Wait_feature FMC Wait feature
* @{
*/
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U)
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U)
/**
* @}
*/
@ -533,9 +533,9 @@ typedef struct
* @{
*/
#if defined(FMC_BANK4)
#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U)
#define FMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U)
#endif
#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
/**
* @}
*/
@ -543,8 +543,8 @@ typedef struct
/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
* @{
*/
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U)
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U)
/**
* @}
*/
@ -552,8 +552,8 @@ typedef struct
/** @defgroup FMC_ECC FMC ECC
* @{
*/
#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
#define FMC_NAND_ECC_DISABLE (0x00000000U)
#define FMC_NAND_ECC_ENABLE (0x00000040U)
/**
* @}
*/
@ -561,12 +561,12 @@ typedef struct
/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
* @{
*/
#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
/**
* @}
*/
@ -581,9 +581,9 @@ typedef struct
* @{
*/
#if defined(FMC_BANK3)||defined(FMC_BANK4)
#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
#define FMC_IT_LEVEL ((uint32_t)0x00000010U)
#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
#define FMC_IT_RISING_EDGE (0x00000008U)
#define FMC_IT_LEVEL (0x00000010U)
#define FMC_IT_FALLING_EDGE (0x00000020U)
#endif /* FMC_BANK3 */
/**
* @}
@ -593,10 +593,10 @@ typedef struct
* @{
*/
#if defined(FMC_BANK3)||defined(FMC_BANK4)
#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
#define FMC_FLAG_LEVEL ((uint32_t)0x00000002U)
#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
#define FMC_FLAG_FEMPT ((uint32_t)0x00000040U)
#define FMC_FLAG_RISING_EDGE (0x00000001U)
#define FMC_FLAG_LEVEL (0x00000002U)
#define FMC_FLAG_FALLING_EDGE (0x00000004U)
#define FMC_FLAG_FEMPT (0x00000040U)
#endif /* FMC_BANK3 */
/**
* @}
@ -626,7 +626,8 @@ typedef struct
* @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCRx_MBKEN)
#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
|= FMC_BCRx_MBKEN)
/**
* @brief Disable the NORSRAM device access.
@ -634,7 +635,8 @@ typedef struct
* @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCRx_MBKEN)
#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
&= ~FMC_BCRx_MBKEN)
/**
* @}
@ -643,9 +645,9 @@ typedef struct
#if defined(FMC_BANK3)
/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
* @brief macros to handle NAND device enable/disable
* @{
*/
* @brief macros to handle NAND device enable/disable
* @{
*/
/**
* @brief Enable the NAND device access.
@ -672,9 +674,9 @@ typedef struct
#if defined(FMC_BANK4)
/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
* @brief macros to handle PCCARD read/write operations
* @{
*/
* @brief macros to handle PCCARD read/write operations
* @{
*/
/**
* @brief Enable the PCCARD device access.
* @param __INSTANCE__ FMC_PCCARD Instance
@ -843,10 +845,14 @@ typedef struct
/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
* @{
*/
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
FMC_NORSRAM_InitTypeDef *Init);
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
/**
* @}
*/
@ -872,8 +878,10 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic
* @{
*/
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
/**
* @}
@ -884,7 +892,8 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
*/
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
uint32_t Timeout);
/**
* @}
*/
@ -901,9 +910,12 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u
* @{
*/
HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
/**
* @}

992
stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_hrtim.h
View File

File diff suppressed because it is too large Load Diff

8
stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_opamp.h
View File

@ -160,8 +160,8 @@ typedef struct
*/
#define LL_OPAMP_INPUT_NONINVERT_IO0 (OPAMP_CSR_VPSEL) /*!< OPAMP non inverting input connected to GPIO pin (pin PA1 for OPAMP1, pin PA7 for OPAMP2, pin PB0 for OPAMP3, pin PB13 for OPAMP4) */
#define LL_OPAMP_INPUT_NONINVERT_IO1 (0x00000000) /*!< OPAMP non inverting input connected to GPIO pin (pin PA7 for OPAMP1, pin PD14 for OPAMP2, pin PB13 for OPAMP3, pin PD11 for OPAMP4) */
#define LL_OPAMP_INPUT_NONINVERT_IO2 (OPAMP_CSR_VPSEL_1) /*!< OPAMP non inverting input connected to GPIO pin (pin PA3 for OPAMP1, pin PB0 for OPAMP2, pin PA1 for OPAMP3, pin PB11 for OPAMP4) */
#define LL_OPAMP_INPUT_NONINVERT_IO3 (OPAMP_CSR_VPSEL_0) /*!< OPAMP non inverting input connected to GPIO pin (pin PA5 for OPAMP1, pin PB14 for OPAMP2, pin PA5 for OPAMP3, pin PA4 for OPAMP4) */
#define LL_OPAMP_INPUT_NONINVERT_IO2 (OPAMP_CSR_VPSEL_1) /*!< OPAMP non inverting input connected to GPIO pin (pin PA3 for OPAMP1, pin PB0 for OPAMP2, pin PA1 for OPAMP3, pin PA4 for OPAMP4) */
#define LL_OPAMP_INPUT_NONINVERT_IO3 (OPAMP_CSR_VPSEL_0) /*!< OPAMP non inverting input connected to GPIO pin (pin PA5 for OPAMP1, pin PB14 for OPAMP2, pin PA5 for OPAMP3, pin PB11 for OPAMP4) */
#define LL_OPAMP_INPUT_NONINV_DAC1_CH1 (LL_OPAMP_INPUT_NONINVERT_IO3) /*!< OPAMP non inverting input connected to DAC1 channel1 output (specific to OPAMP instances: OPAMP4) */
#define LL_OPAMP_INPUT_NONINV_DAC1_CH2 (LL_OPAMP_INPUT_NONINVERT_IO3) /*!< OPAMP non inverting input connected to DAC1 channel2 output (specific to OPAMP instances: OPAMP1, OPAMP3) */
/**
@ -504,7 +504,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx)
{
register uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL);
uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL);
/* Manage cases 0x10 and 0x11 to return the same value: OPAMP inverting */
/* input not connected. */
@ -689,7 +689,7 @@ __STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uin
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)
{
register uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
return (CalibrationSelection |
(((CalibrationSelection & OPAMP_CSR_CALSEL) == 0UL) ? OPAMP_CSR_TRIMOFFSETN : OPAMP_CSR_TRIMOFFSETP));

4
stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_rcc.h
View File

@ -132,6 +132,10 @@ typedef struct
#if !defined (LSI_VALUE)
#define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */
#endif /* LSI_VALUE */
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
#endif /* EXTERNAL_CLOCK_VALUE */
/**
* @}
*/

16
stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_rtc.h
View File

@ -1296,7 +1296,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
*/
__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
{
register uint32_t temp = 0U;
uint32_t temp = 0U;
temp = Format12_24 | \
(((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
@ -1324,7 +1324,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24,
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
{
register uint32_t temp = 0U;
uint32_t temp = 0U;
temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \
@ -1626,7 +1626,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
*/
__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
{
register uint32_t temp = 0U;
uint32_t temp = 0U;
temp = (WeekDay << RTC_DR_WDU_Pos) | \
(((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
@ -1654,7 +1654,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
{
register uint32_t temp = 0U;
uint32_t temp = 0U;
temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
@ -1954,7 +1954,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
*/
__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
{
register uint32_t temp = 0U;
uint32_t temp = 0U;
temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
@ -2320,7 +2320,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
*/
__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
{
register uint32_t temp = 0U;
uint32_t temp = 0U;
temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
@ -3010,7 +3010,7 @@ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
*/
__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
{
register uint32_t tmp = 0U;
uint32_t tmp = 0U;
tmp = (uint32_t)(&(RTCx->BKP0R));
tmp += (BackupRegister * 4U);
@ -3062,7 +3062,7 @@ __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRe
*/
__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
{
register uint32_t tmp = 0U;
uint32_t tmp = 0U;
tmp = (uint32_t)(&(RTCx->BKP0R));
tmp += (BackupRegister * 4U);

22
stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_spi.h
View File

@ -266,8 +266,8 @@ typedef struct
/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
* @{
*/
#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */
#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */
#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */
#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */
/**
* @}
*/
@ -848,8 +848,8 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
*/
__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
{
register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
return (Ssm | Ssoe);
}
@ -1501,10 +1501,10 @@ typedef struct
/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
* @{
*/
#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */
#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */
#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */
#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */
/**
* @}
*/
@ -1839,7 +1839,7 @@ __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
}
/**
* @brief Enable the master clock ouput (Pin MCK)
* @brief Enable the master clock output (Pin MCK)
* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
* @param SPIx SPI Instance
* @retval None
@ -1850,7 +1850,7 @@ __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
}
/**
* @brief Disable the master clock ouput (Pin MCK)
* @brief Disable the master clock output (Pin MCK)
* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
* @param SPIx SPI Instance
* @retval None
@ -1861,7 +1861,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
}
/**
* @brief Check if the master clock ouput (Pin MCK) is enabled
* @brief Check if the master clock output (Pin MCK) is enabled
* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).

126
stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_tim.h
View File

@ -240,13 +240,14 @@ typedef struct
This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
This parameter must be a number between 0x00 and 0xFF.
GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
} LL_TIM_InitTypeDef;
@ -602,8 +603,8 @@ typedef struct
*/
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
/**
* @}
@ -1511,7 +1512,16 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo
*/
__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
uint32_t counter_mode;
counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
if (counter_mode == 0U)
{
counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
}
return counter_mode;
}
/**
@ -1685,7 +1695,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
* @param TIMx Timer instance
* @param RepetitionCounter between Min_Data=0 and Max_Data=255
* @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
@ -1730,6 +1740,16 @@ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
}
/**
* @brief Indicate whether update interrupt flag (UIF) copy is set.
* @param Counter Counter value
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
{
return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
}
#endif /* TIM_CR1_UIFREMAP */
/**
* @}
@ -1970,8 +1990,8 @@ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t
*/
__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
@ -2031,8 +2051,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel,
*/
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
}
@ -2086,8 +2106,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
}
@ -2121,7 +2141,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
*/
__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
}
@ -2154,7 +2174,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
}
@ -2192,7 +2212,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann
*/
__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
}
@ -2225,7 +2245,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel,
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
}
@ -2260,8 +2280,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan
*/
__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@ -2296,8 +2316,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
*/
__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@ -2332,9 +2352,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@ -2368,8 +2388,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha
*/
__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@ -2403,8 +2423,8 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel
*/
__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@ -2438,9 +2458,9 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@ -2477,8 +2497,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t
*/
__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@ -2514,8 +2534,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
*/
__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@ -2553,9 +2573,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@ -2873,8 +2893,8 @@ __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t G
*/
__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
@ -2901,8 +2921,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3
*/
__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@ -2925,8 +2945,8 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@ -2951,8 +2971,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch
*/
__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@ -2976,8 +2996,8 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel,
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@ -3014,8 +3034,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan
*/
__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@ -3051,8 +3071,8 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@ -3080,7 +3100,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel
*/
__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
ICPolarity << SHIFT_TAB_CCxP[iChannel]);
}
@ -3108,7 +3128,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
SHIFT_TAB_CCxP[iChannel]);
}

222
stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_usart.h
View File

@ -66,37 +66,44 @@ typedef struct
uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
This feature can be modified afterwards using unitary
function @ref LL_USART_SetBaudRate().*/
uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
This feature can be modified afterwards using unitary
function @ref LL_USART_SetDataWidth().*/
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_LL_EC_STOPBITS.
This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
This feature can be modified afterwards using unitary
function @ref LL_USART_SetStopBitsLength().*/
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_LL_EC_PARITY.
This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
This feature can be modified afterwards using unitary
function @ref LL_USART_SetParity().*/
uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_LL_EC_DIRECTION.
This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
This feature can be modified afterwards using unitary
function @ref LL_USART_SetTransferDirection().*/
uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
This feature can be modified afterwards using unitary
function @ref LL_USART_SetHWFlowCtrl().*/
uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
This feature can be modified afterwards using unitary
function @ref LL_USART_SetOverSampling().*/
} LL_USART_InitTypeDef;
@ -115,20 +122,23 @@ typedef struct
uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
This parameter can be a value of @ref USART_LL_EC_POLARITY.
USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
USART HW configuration can be modified afterwards using unitary
functions @ref LL_USART_SetClockPolarity().
For more details, refer to description of this function. */
uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_LL_EC_PHASE.
USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
USART HW configuration can be modified afterwards using unitary
functions @ref LL_USART_SetClockPhase().
For more details, refer to description of this function. */
uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
USART HW configuration can be modified afterwards using unitary
functions @ref LL_USART_SetLastClkPulseOutput().
For more details, refer to description of this function. */
} LL_USART_ClockInitTypeDef;
@ -553,7 +563,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
* @brief USART enabled in STOP Mode.
* @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
* USART clock selection is HSI or LSE in RCC.
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_EnableInStopMode
* @param USARTx USART Instance
@ -567,7 +577,7 @@ __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
/**
* @brief USART disabled in STOP Mode.
* @note When this function is disabled, USART is not able to wake up the MCU from Stop mode
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_DisableInStopMode
* @param USARTx USART Instance
@ -580,7 +590,7 @@ __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
/**
* @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode
* @param USARTx USART Instance
@ -827,7 +837,7 @@ __STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
/**
* @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
* @param USARTx USART Instance
@ -844,7 +854,7 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3
/**
* @brief Retrieve Clock pulse of the last data bit output configuration
* (Last bit Clock pulse output to the SCLK pin or not)
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
* @param USARTx USART Instance
@ -859,7 +869,7 @@ __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
/**
* @brief Select the phase of the clock output on the SCLK pin in synchronous mode
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPHA LL_USART_SetClockPhase
* @param USARTx USART Instance
@ -875,7 +885,7 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc
/**
* @brief Return phase of the clock output on the SCLK pin in synchronous mode
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPHA LL_USART_GetClockPhase
* @param USARTx USART Instance
@ -890,7 +900,7 @@ __STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
/**
* @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPOL LL_USART_SetClockPolarity
* @param USARTx USART Instance
@ -906,7 +916,7 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C
/**
* @brief Return polarity of the clock output on the SCLK pin in synchronous mode
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPOL LL_USART_GetClockPolarity
* @param USARTx USART Instance
@ -921,7 +931,7 @@ __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
/**
* @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
@ -949,7 +959,7 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase,
/**
* @brief Enable Clock output on SCLK pin
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
* @param USARTx USART Instance
@ -962,7 +972,7 @@ __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
/**
* @brief Disable Clock output on SCLK pin
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
* @param USARTx USART Instance
@ -975,7 +985,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
/**
* @brief Indicate if Clock output on SCLK pin is enabled
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
* @param USARTx USART Instance
@ -1196,7 +1206,7 @@ __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
/**
* @brief Enable Auto Baud-Rate Detection
* @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate
* @param USARTx USART Instance
@ -1209,7 +1219,7 @@ __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
/**
* @brief Disable Auto Baud-Rate Detection
* @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate
* @param USARTx USART Instance
@ -1222,7 +1232,7 @@ __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
/**
* @brief Indicate if Auto Baud-Rate Detection mechanism is enabled
* @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud
* @param USARTx USART Instance
@ -1235,7 +1245,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
/**
* @brief Set Auto Baud-Rate mode bits
* @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode
* @param USARTx USART Instance
@ -1253,7 +1263,7 @@ __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_
/**
* @brief Return Auto Baud-Rate mode
* @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode
* @param USARTx USART Instance
@ -1360,7 +1370,7 @@ __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
/**
* @brief Enable RTS HW Flow Control
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
* @param USARTx USART Instance
@ -1373,7 +1383,7 @@ __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
/**
* @brief Disable RTS HW Flow Control
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
* @param USARTx USART Instance
@ -1386,7 +1396,7 @@ __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
/**
* @brief Enable CTS HW Flow Control
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
* @param USARTx USART Instance
@ -1399,7 +1409,7 @@ __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
/**
* @brief Disable CTS HW Flow Control
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
* @param USARTx USART Instance
@ -1412,7 +1422,7 @@ __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
/**
* @brief Configure HW Flow Control mode (both CTS and RTS)
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
* CR3 CTSE LL_USART_SetHWFlowCtrl
@ -1431,7 +1441,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard
/**
* @brief Return HW Flow Control configuration (both CTS and RTS)
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
* CR3 CTSE LL_USART_GetHWFlowCtrl
@ -1515,7 +1525,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
/**
* @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUS LL_USART_SetWKUPType
* @param USARTx USART Instance
@ -1532,7 +1542,7 @@ __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
/**
* @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUS LL_USART_GetWKUPType
* @param USARTx USART Instance
@ -1566,7 +1576,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph
uint32_t BaudRate)
{
uint32_t usartdiv;
register uint32_t brrtemp;
uint32_t brrtemp;
if (OverSampling == LL_USART_OVERSAMPLING_8)
{
@ -1596,8 +1606,8 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph
*/
__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
{
register uint32_t usartdiv;
register uint32_t brrresult = 0x0U;
uint32_t usartdiv;
uint32_t brrresult = 0x0U;
usartdiv = USARTx->BRR;
@ -1679,7 +1689,7 @@ __STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
/**
* @brief Enable IrDA mode
* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_EnableIrda
* @param USARTx USART Instance
@ -1692,7 +1702,7 @@ __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
/**
* @brief Disable IrDA mode
* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_DisableIrda
* @param USARTx USART Instance
@ -1705,7 +1715,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
/**
* @brief Indicate if IrDA mode is enabled
* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_IsEnabledIrda
* @param USARTx USART Instance
@ -1718,7 +1728,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
/**
* @brief Configure IrDA Power Mode (Normal or Low Power)
* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
* @param USARTx USART Instance
@ -1734,7 +1744,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P
/**
* @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
* @param USARTx USART Instance
@ -1750,7 +1760,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
/**
* @brief Set Irda prescaler value, used for dividing the USART clock source
* to achieve the Irda Low Power frequency (8 bits value)
* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
* @param USARTx USART Instance
@ -1765,7 +1775,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t P
/**
* @brief Return Irda prescaler value, used for dividing the USART clock source
* to achieve the Irda Low Power frequency (8 bits value)
* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
* @param USARTx USART Instance
@ -1786,7 +1796,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
/**
* @brief Enable Smartcard NACK transmission
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
* @param USARTx USART Instance
@ -1799,7 +1809,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
/**
* @brief Disable Smartcard NACK transmission
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
* @param USARTx USART Instance
@ -1812,7 +1822,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
/**
* @brief Indicate if Smartcard NACK transmission is enabled
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
* @param USARTx USART Instance
@ -1825,7 +1835,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
/**
* @brief Enable Smartcard mode
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_EnableSmartcard
* @param USARTx USART Instance
@ -1838,7 +1848,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
/**
* @brief Disable Smartcard mode
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_DisableSmartcard
* @param USARTx USART Instance
@ -1851,7 +1861,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
/**
* @brief Indicate if Smartcard mode is enabled
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
* @param USARTx USART Instance
@ -1864,7 +1874,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
/**
* @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
* In transmission mode, it specifies the number of automatic retransmission retries, before
@ -1883,7 +1893,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx,
/**
* @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
* @param USARTx USART Instance
@ -1897,7 +1907,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USAR
/**
* @brief Set Smartcard prescaler value, used for dividing the USART clock
* source to provide the SMARTCARD Clock (5 bits value)
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
* @param USARTx USART Instance
@ -1912,7 +1922,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint3
/**
* @brief Return Smartcard prescaler value, used for dividing the USART clock
* source to provide the SMARTCARD Clock (5 bits value)
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
* @param USARTx USART Instance
@ -1926,7 +1936,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
/**
* @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
* (GT[7:0] bits : Guard time value)
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
* @param USARTx USART Instance
@ -1941,7 +1951,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3
/**
* @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
* (GT[7:0] bits : Guard time value)
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
* @param USARTx USART Instance
@ -1962,7 +1972,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
/**
* @brief Enable Single Wire Half-Duplex mode
* @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
* @param USARTx USART Instance
@ -1975,7 +1985,7 @@ __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
/**
* @brief Disable Single Wire Half-Duplex mode
* @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
* @param USARTx USART Instance
@ -1988,7 +1998,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
/**
* @brief Indicate if Single Wire Half-Duplex mode is enabled
* @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
* @param USARTx USART Instance
@ -2009,7 +2019,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
/**
* @brief Set LIN Break Detection Length
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
* @param USARTx USART Instance
@ -2025,7 +2035,7 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3
/**
* @brief Return LIN Break Detection Length
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
* @param USARTx USART Instance
@ -2040,7 +2050,7 @@ __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
/**
* @brief Enable LIN mode
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_EnableLIN
* @param USARTx USART Instance
@ -2053,7 +2063,7 @@ __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
/**
* @brief Disable LIN mode
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_DisableLIN
* @param USARTx USART Instance
@ -2066,7 +2076,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
/**
* @brief Indicate if LIN mode is enabled
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
* @param USARTx USART Instance
@ -2087,7 +2097,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
/**
* @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime
* @param USARTx USART Instance
@ -2101,7 +2111,7 @@ __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32
/**
* @brief Return DEDT (Driver Enable De-Assertion Time)
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime
* @param USARTx USART Instance
@ -2114,7 +2124,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
/**
* @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime
* @param USARTx USART Instance
@ -2128,7 +2138,7 @@ __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t
/**
* @brief Return DEAT (Driver Enable Assertion Time)
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime
* @param USARTx USART Instance
@ -2141,7 +2151,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
/**
* @brief Enable Driver Enable (DE) Mode
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_EnableDEMode
* @param USARTx USART Instance
@ -2154,7 +2164,7 @@ __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
/**
* @brief Disable Driver Enable (DE) Mode
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_DisableDEMode
* @param USARTx USART Instance
@ -2167,7 +2177,7 @@ __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
/**
* @brief Indicate if Driver Enable (DE) Mode is enabled
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_IsEnabledDEMode
* @param USARTx USART Instance
@ -2180,7 +2190,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
/**
* @brief Select Driver Enable Polarity
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEP LL_USART_SetDESignalPolarity
* @param USARTx USART Instance
@ -2196,7 +2206,7 @@ __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_
/**
* @brief Return Driver Enable Polarity
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEP LL_USART_GetDESignalPolarity
* @param USARTx USART Instance
@ -2260,7 +2270,7 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also sets the USART in Synchronous mode.
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@ -2299,7 +2309,7 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also set the UART/USART in LIN mode.
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
@ -2340,7 +2350,7 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
* - SCEN bit in the USART_CR3 register,
* - IREN bit in the USART_CR3 register,
* This function also sets the UART/USART in Half Duplex mode.
* @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@ -2380,7 +2390,7 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
* This function also configures Stop bits to 1.5 bits and
* sets the USART in Smartcard mode (SCEN bit).
* Clock Output is also enabled (CLKEN).
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@ -2423,7 +2433,7 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
* - SCEN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also sets the UART/USART in IRDA mode (IREN bit).
* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@ -2591,7 +2601,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
/**
* @brief Check if the USART LIN Break Detection Flag is set or not
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD
* @param USARTx USART Instance
@ -2604,7 +2614,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
/**
* @brief Check if the USART CTS interrupt Flag is set or not
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS
* @param USARTx USART Instance
@ -2617,7 +2627,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
/**
* @brief Check if the USART CTS Flag is set or not
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS
* @param USARTx USART Instance
@ -2641,7 +2651,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
/**
* @brief Check if the USART End Of Block Flag is set or not
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB
* @param USARTx USART Instance
@ -2654,7 +2664,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
/**
* @brief Check if the USART Auto-Baud Rate Error Flag is set or not
* @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE
* @param USARTx USART Instance
@ -2667,7 +2677,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
/**
* @brief Check if the USART Auto-Baud Rate Flag is set or not
* @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR
* @param USARTx USART Instance
@ -2724,7 +2734,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
/**
* @brief Check if the USART Wake Up from stop mode Flag is set or not
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP
* @param USARTx USART Instance
@ -2826,7 +2836,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
/**
* @brief Clear LIN Break Detection Flag
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD
* @param USARTx USART Instance
@ -2839,7 +2849,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
/**
* @brief Clear CTS Interrupt Flag
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS
* @param USARTx USART Instance
@ -2863,7 +2873,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
/**
* @brief Clear End Of Block Flag
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB
* @param USARTx USART Instance
@ -2887,7 +2897,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
/**
* @brief Clear Wake Up from stop mode Flag
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP
* @param USARTx USART Instance
@ -2985,7 +2995,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
/**
* @brief Enable End Of Block Interrupt
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB
* @param USARTx USART Instance
@ -2998,7 +3008,7 @@ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
/**
* @brief Enable LIN Break Detection Interrupt
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
* @param USARTx USART Instance
@ -3026,7 +3036,7 @@ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
/**
* @brief Enable CTS Interrupt
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
* @param USARTx USART Instance
@ -3039,7 +3049,7 @@ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
/**
* @brief Enable Wake Up from Stop Mode Interrupt
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP
* @param USARTx USART Instance
@ -3130,7 +3140,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
/**
* @brief Disable End Of Block Interrupt
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB
* @param USARTx USART Instance
@ -3143,7 +3153,7 @@ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
/**
* @brief Disable LIN Break Detection Interrupt
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
* @param USARTx USART Instance
@ -3171,7 +3181,7 @@ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
/**
* @brief Disable CTS Interrupt
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
* @param USARTx USART Instance
@ -3184,7 +3194,7 @@ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
/**
* @brief Disable Wake Up from Stop Mode Interrupt
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP
* @param USARTx USART Instance
@ -3275,7 +3285,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
/**
* @brief Check if the USART End Of Block Interrupt is enabled or disabled.
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB
* @param USARTx USART Instance
@ -3288,7 +3298,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
/**
* @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
* @param USARTx USART Instance
@ -3312,7 +3322,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
/**
* @brief Check if the USART CTS Interrupt is enabled or disabled.
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
* @param USARTx USART Instance
@ -3325,7 +3335,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
/**
* @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP
* @param USARTx USART Instance
@ -3456,7 +3466,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx
*/
__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
{
register uint32_t data_reg_addr;
uint32_t data_reg_addr;
if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
{
@ -3536,7 +3546,7 @@ __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Valu
/**
* @brief Request an Automatic Baud Rate measurement on next received data frame
* @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate
* @param USARTx USART Instance
@ -3584,7 +3594,7 @@ __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
/**
* @brief Request a Transmit data flush
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush
* @param USARTx USART Instance

3
stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_utils.h
View File

@ -249,6 +249,9 @@ void LL_mDelay(uint32_t Delay);
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
#if defined(FLASH_ACR_LATENCY)
ErrorStatus LL_SetFlashLatency(uint32_t Frequency);
#endif /* FLASH_ACR_LATENCY */
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,

4
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal.c
View File

@ -52,11 +52,11 @@
* @{
*/
/**
* @brief STM32F3xx HAL Driver version number V1.5.3
* @brief STM32F3xx HAL Driver version number V1.5.5
*/
#define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F3xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F3xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
#define __STM32F3xx_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */
#define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\

103
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_adc_ex.c
View File

@ -2666,13 +2666,16 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
/* while DMA transfer is on going) */
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
/* Check if DMA channel effectively disabled */
if (tmp_hal_status != HAL_OK)
if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
/* Check if DMA channel effectively disabled */
if (tmp_hal_status != HAL_OK)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
}
}
/* Disable ADC overrun interrupt */
@ -2971,57 +2974,59 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/* group having no further conversion upcoming (same conditions as */
/* regular group interruption disabling above), */
/* and if injected scan sequence is completed. */
if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) &&
(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
(READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) )
if(ADC_IS_SOFTWARE_START_INJECTED(hadc))
{
/* If End of Sequence is reached, disable interrupts */
if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
if((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) ||
(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
(READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) )
{
/* If End of Sequence is reached, disable interrupts */
if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
{
/* Get relevant register CFGR in ADC instance of ADC master or slave */
/* in function of multimode state (for devices with multimode */
/* available). */
if (ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc))
{
tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR);
}
else
{
tmp_cfgr_jqm = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
}
/* Particular case if injected contexts queue is enabled: */
/* when the last context has been fully processed, JSQR is reset */
/* by the hardware. Even if no injected conversion is planned to come */
/* (queue empty, triggers are ignored), it can start again */
/* immediately after setting a new context (JADSTART is still set). */
/* Therefore, state of HAL ADC injected group is kept to busy. */
if(READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) == RESET)
{
/* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
/* JADSTART==0 (no conversion on going) */
if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
/* Get relevant register CFGR in ADC instance of ADC master or slave */
/* in function of multimode state (for devices with multimode */
/* available). */
if (ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc))
{
/* Disable ADC end of sequence conversion interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR);
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
tmp_cfgr_jqm = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
}
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
/* Particular case if injected contexts queue is enabled: */
/* when the last context has been fully processed, JSQR is reset */
/* by the hardware. Even if no injected conversion is planned to come */
/* (queue empty, triggers are ignored), it can start again */
/* immediately after setting a new context (JADSTART is still set). */
/* Therefore, state of HAL ADC injected group is kept to busy. */
if(READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) == RESET)
{
/* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
/* JADSTART==0 (no conversion on going) */
if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
{
/* Disable ADC end of sequence conversion interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
}
}
}

12
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_cec.c
View File

@ -822,19 +822,15 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
/* CEC TX byte request interrupt ------------------------------------------------*/
if ((reg & CEC_FLAG_TXBR) != 0U)
{
--hcec->TxXferCount;
if (hcec->TxXferCount == 0U)
{
/* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
hcec->Instance->TXDR = *hcec->pTxBuffPtr;
hcec->pTxBuffPtr++;
}
else
{
hcec->Instance->TXDR = *hcec->pTxBuffPtr;
hcec->pTxBuffPtr++;
hcec->TxXferCount--;
}
/* In all cases transmit the byte */
hcec->Instance->TXDR = *hcec->pTxBuffPtr;
hcec->pTxBuffPtr++;
/* clear Tx-Byte request flag */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
}

8
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_hrtim.c
View File

@ -779,6 +779,9 @@ HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim,
SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
}
/* Set HRTIM state */
hhrtim->State = HAL_HRTIM_STATE_READY;
return HAL_OK;
}
@ -829,6 +832,9 @@ HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim,
SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
}
/* Set HRTIM state */
hhrtim->State = HAL_HRTIM_STATE_READY;
return HAL_OK;
}
@ -3793,8 +3799,8 @@ HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
HRTIM_EventCfgTypeDef* pEventCfg)
{
/* Check parameters */
assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
assert_param(IS_HRTIM_EVENT(Event));
assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));

227
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2s.c
View File

@ -88,6 +88,10 @@
(+) Pause the DMA Transfer using HAL_I2S_DMAPause()
(+) Resume the DMA Transfer using HAL_I2S_DMAResume()
(+) Stop the DMA Transfer using HAL_I2S_DMAStop()
In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error
HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data
inside DR register and avoid using DeInit/Init process for the next transfer.
*** I2S HAL driver macros list ***
===================================
@ -99,6 +103,7 @@
(+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
(+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
(+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
(+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data
[..]
(@) You can refer to the I2S HAL driver header file for more useful macros
@ -195,6 +200,7 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define I2S_TIMEOUT_FLAG 100U /*!< Timeout 100 ms */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@ -263,7 +269,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
uint32_t i2sodd;
uint32_t packetlength;
uint32_t tmp;
uint32_t i2sclk = 0U;
uint32_t i2sclk;
#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
uint16_t tmpreg;
#endif
@ -350,7 +356,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
/* I2S standard */
if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
{
/* In I2S standard packet lenght is multiplied by 2 */
/* In I2S standard packet length is multiplied by 2 */
packetlength = packetlength * 2U;
}
@ -384,7 +390,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
{
i2sclk = HAL_RCC_GetPCLK2Freq();
}
else if ((hi2s->Instance == SPI2) || (hi2s->Instance == SPI3))
else /* SPI2 or SPI3 */
{
i2sclk = HAL_RCC_GetPCLK1Freq();
}
@ -489,9 +495,11 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
}
/* Configure the I2S Slave with the I2S Master parameter values */
tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
(uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
(uint16_t)hi2s->Init.CPOL))));
tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | \
(uint16_t)tmp | \
(uint16_t)hi2s->Init.Standard | \
(uint16_t)hi2s->Init.DataFormat | \
(uint16_t)hi2s->Init.CPOL);
/* Write to SPIx I2SCFGR */
WRITE_REG(I2SxEXT(hi2s->Instance)->I2SCFGR, tmpreg);
@ -851,7 +859,7 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
* the Size parameter means the number of 24-bit or 32-bit data length.
* @param Timeout Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
@ -968,7 +976,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
* the Size parameter means the number of 24-bit or 32-bit data length.
* @param Timeout Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
@ -1069,7 +1077,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
* the Size parameter means the number of 24-bit or 32-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
@ -1133,7 +1141,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
* the Size parameter means the number of 24-bit or 32-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
@ -1199,7 +1207,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
* the Size parameter means the number of 24-bit or 32-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
@ -1290,7 +1298,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
* the Size parameter means the number of 24-bit or 32-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
@ -1480,6 +1488,9 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
*/
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
{
#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
uint32_t tickstart;
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
HAL_StatusTypeDef errorcode = HAL_OK;
/* The Lock is not implemented on this API to allow the user application
to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
@ -1487,46 +1498,180 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
*/
/* Disable the I2S Tx/Rx DMA requests */
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
/* Abort the I2S DMA tx Stream/Channel */
if (hi2s->hdmatx != NULL)
if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
{
/* Disable the I2S DMA tx Stream/Channel */
if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
/* Abort the I2S DMA tx Stream/Channel */
if (hi2s->hdmatx != NULL)
{
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
errorcode = HAL_ERROR;
/* Disable the I2S DMA tx Stream/Channel */
if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
{
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
errorcode = HAL_ERROR;
}
}
}
/* Abort the I2S DMA rx Stream/Channel */
if (hi2s->hdmarx != NULL)
{
/* Disable the I2S DMA rx Stream/Channel */
if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
/* Wait until TXE flag is set */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK)
{
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
errorcode = HAL_ERROR;
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
hi2s->State = HAL_I2S_STATE_READY;
errorcode = HAL_ERROR;
}
}
/* Wait until BSY flag is Reset */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK)
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
hi2s->State = HAL_I2S_STATE_READY;
errorcode = HAL_ERROR;
}
/* Disable I2S peripheral */
__HAL_I2S_DISABLE(hi2s);
/* Clear UDR flag */
__HAL_I2S_CLEAR_UDRFLAG(hi2s);
/* Disable the I2S Tx DMA requests */
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
/* In case of Full-Duplex, disable the I2SxEXT Tx/Rx DMA requests*/
if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
{
/* Disable the I2SxEXT DMA requests */
CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
/* Disable I2Sext peripheral */
__HAL_I2SEXT_DISABLE(hi2s);
if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
{
/* Abort the I2S DMA rx Stream/Channel */
if (hi2s->hdmarx != NULL)
{
/* Disable the I2S DMA rx Stream/Channel */
if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
{
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
errorcode = HAL_ERROR;
}
}
/* Disable I2Sext peripheral */
__HAL_I2SEXT_DISABLE(hi2s);
/* Clear OVR flag */
__HAL_I2SEXT_CLEAR_OVRFLAG(hi2s);
/* Disable the I2SxEXT DMA request */
CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
if (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
/* Set the I2S State ready */
hi2s->State = HAL_I2S_STATE_READY;
errorcode = HAL_ERROR;
}
else
{
/* Read DR to Flush RX Data */
READ_REG(I2SxEXT(hi2s->Instance)->DR);
}
}
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
}
else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
{
/* Abort the I2S DMA rx Stream/Channel */
if (hi2s->hdmarx != NULL)
{
/* Disable the I2S DMA rx Stream/Channel */
if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
{
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
errorcode = HAL_ERROR;
}
}
#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
{
/* Abort the I2S DMA tx Stream/Channel */
if (hi2s->hdmatx != NULL)
{
/* Disable the I2S DMA tx Stream/Channel */
if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
{
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
errorcode = HAL_ERROR;
}
}
tickstart = HAL_GetTick();
/* Wait until TXE flag is set */
while (__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_TXE) != SET)
{
if (((HAL_GetTick() - tickstart) > I2S_TIMEOUT_FLAG))
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
/* Set the I2S State ready */
hi2s->State = HAL_I2S_STATE_READY;
errorcode = HAL_ERROR;
}
}
/* Wait until BSY flag is Reset */
while (__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_BSY) != RESET)
{
if (((HAL_GetTick() - tickstart) > I2S_TIMEOUT_FLAG))
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
/* Set the I2S State ready */
hi2s->State = HAL_I2S_STATE_READY;
errorcode = HAL_ERROR;
}
}
/* Disable I2Sext peripheral */
__HAL_I2SEXT_DISABLE(hi2s);
/* Clear UDR flag */
__HAL_I2SEXT_CLEAR_UDRFLAG(hi2s);
/* Disable the I2SxEXT DMA request */
CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
}
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
/* Disable I2S peripheral */
__HAL_I2S_DISABLE(hi2s);
/* Disable I2S peripheral */
__HAL_I2S_DISABLE(hi2s);
/* Clear OVR flag */
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
/* Disable the I2S Rx DMA request */
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
/* Set the I2S State ready */
hi2s->State = HAL_I2S_STATE_READY;
errorcode = HAL_ERROR;
}
else
{
/* Read DR to Flush RX Data */
READ_REG((hi2s->Instance)->DR);
}
}
hi2s->State = HAL_I2S_STATE_READY;

33
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2s_ex.c
View File

@ -52,6 +52,10 @@
add his own code by customization of function pointer HAL_I2S_TxRxCpltCallback
(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2S_ErrorCallback
(+) __HAL_I2SEXT_FLUSH_RX_DR: In Full-Duplex Slave mode, if HAL_I2S_DMAStop is used to stop the
communication, an error HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
In this case __HAL_I2SEXT_FLUSH_RX_DR macro must be used to flush the remaining data
inside I2Sx and I2Sx_ext DR registers and avoid using DeInit/Init process for the next transfer.
@endverbatim
Additional Figure: The Extended block uses the same clock sources as its master.
@ -125,8 +129,11 @@ static void I2SEx_RxISR_I2S(I2S_HandleTypeDef *hi2s);
static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s);
static void I2SEx_TxISR_I2S(I2S_HandleTypeDef *hi2s);
static void I2SEx_TxISR_I2SExt(I2S_HandleTypeDef *hi2s);
static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed);
static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
uint32_t Flag,
uint32_t State,
uint32_t Timeout,
I2S_UseTypeDef i2sUsed);
/**
* @}
*/
@ -198,8 +205,11 @@ static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTyp
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
uint16_t Size, uint32_t Timeout)
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s,
uint16_t *pTxData,
uint16_t *pRxData,
uint16_t Size,
uint32_t Timeout)
{
uint32_t tmp1 = 0U;
HAL_StatusTypeDef errorcode = HAL_OK;
@ -416,7 +426,9 @@ error :
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s,
uint16_t *pTxData,
uint16_t *pRxData,
uint16_t Size)
{
uint32_t tmp1 = 0U;
@ -526,7 +538,9 @@ error :
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s,
uint16_t *pTxData,
uint16_t *pRxData,
uint16_t Size)
{
uint32_t *tmp = NULL;
@ -1087,8 +1101,11 @@ static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s)
* @param i2sUsed I2S instance reference
* @retval HAL status
*/
static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed)
static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
uint32_t Flag,
uint32_t State,
uint32_t Timeout,
I2S_UseTypeDef i2sUsed)
{
uint32_t tickstart = HAL_GetTick();

53
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_irda.c
View File

@ -40,7 +40,8 @@
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
(+++) Configure the priority and enable the NVIC for the transfer
complete interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
the normal or low power mode and the clock prescaler in the hirda handle Init structure.
@ -620,43 +621,45 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
switch (CallbackID)
{
case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
break;
case HAL_IRDA_TX_COMPLETE_CB_ID :
hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
break;
case HAL_IRDA_RX_COMPLETE_CB_ID :
hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_IRDA_ERROR_CB_ID :
hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_IRDA_ABORT_COMPLETE_CB_ID :
hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak
AbortTransmitCpltCallback */
break;
case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak
AbortReceiveCpltCallback */
break;
case HAL_IRDA_MSPINIT_CB_ID :
hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_IRDA_MSPDEINIT_CB_ID :
hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
@ -779,13 +782,16 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
Transfer is kept ongoing on IRDA side.
If user wants to abort it, Abort services should be called by user.
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
Error code is set to allow user to identify error type, and
HAL_IRDA_ErrorCallback() user callback is executed.
@endverbatim
* @{
@ -823,7 +829,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
/* Init tickstart for timeout managment*/
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
hirda->TxXferSize = Size;
@ -913,7 +919,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
/* Init tickstart for timeout managment*/
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
hirda->RxXferSize = Size;
@ -1081,9 +1087,6 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
/* Check if USART/UART instance associated to the IRDA handle supports continuous communication using DMA */
assert_param(IS_UART_DMA_INSTANCE(hirda->Instance));
/* Check that a Tx process is not already ongoing */
if (hirda->gState == HAL_IRDA_STATE_READY)
{
@ -1164,9 +1167,6 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
*/
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
/* Check if USART/UART instance associated to the IRDA handle supports continuous communication using DMA */
assert_param(IS_UART_DMA_INSTANCE(hirda->Instance));
/* Check that a Rx process is not already ongoing */
if (hirda->RxState == HAL_IRDA_STATE_READY)
{
@ -1294,7 +1294,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_IRDA_CLEAR_OREFLAG(hirda);
/* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@ -2330,7 +2330,7 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
/* Initialize the IRDA ErrorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
/* Init tickstart for timeout managment*/
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Check if the Transmitter is enabled */
@ -2385,7 +2385,8 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);

44
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_iwdg.c
View File

@ -16,33 +16,43 @@
(+) The IWDG can be started by either software or hardware (configurable
through option byte).
(+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
if the main clock fails.
(+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
active even if the main clock fails.
(+) Once the IWDG is started, the LSI is forced ON and both can not be
(+) Once the IWDG is started, the LSI is forced ON and both cannot be
disabled. The counter starts counting down from the reset value (0xFFF).
When it reaches the end of count value (0x000) a reset signal is
generated (IWDG reset).
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
the IWDG_RLR value is reloaded in the counter and the watchdog reset is
prevented.
the IWDG_RLR value is reloaded into the counter and the watchdog reset
is prevented.
(+) The IWDG is implemented in the VDD voltage domain that is still functional
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
reset occurs.
(+) Debug mode : When the microcontroller enters debug mode (core halted),
(+) Debug mode: When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
[..] Min-max timeout value @40KHz (LSI): ~100us / ~26.2s
The IWDG timeout may vary due to LSI frequency dispersion. STM32F3xx
devices provide the capability to measure the LSI frequency (LSI clock
connected internally to TIM16 CH1 input capture). The measured value
can be used to have an IWDG timeout with an acceptable accuracy.
The IWDG timeout may vary due to LSI clock frequency dispersion.
STM32F3xx devices provide the capability to measure the LSI clock
frequency (LSI clock is internally connected to TIM16 CH1 input capture).
The measured value can be used to have an IWDG timeout with an
acceptable accuracy.
[..] Default timeout value (necessary for IWDG_SR status register update):
Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
This frequency being subject to variations as mentioned above, the
default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
below) may become too short or too long.
In such cases, this default timeout value can be tuned by redefining
the constant LSI_VALUE at user-application level (based, for instance,
on the measured LSI clock frequency as explained above).
##### How to use this driver #####
==============================================================================
@ -108,10 +118,14 @@
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
higher prescaler (256), and according to LSI variation, we need to wait at
least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48u
/* Status register needs up to 5 LSI clock periods divided by the clock
prescaler to be updated. The number of LSI clock periods is upper-rounded to
6 for the timeout value calculation.
The timeout value is also calculated using the highest prescaler (256) and
the LSI_VALUE constant. The value of this constant can be changed by the user
to take into account possible LSI clock period variations.
The timeout value is multiplied by 1000 to be converted in milliseconds. */
#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
/**
* @}
*/

732
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_nand.c
View File

File diff suppressed because it is too large Load Diff

495
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_nor.c
View File

@ -151,9 +151,35 @@
#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF
#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040
#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8
#define NOR_CMD_CONFIRM (uint16_t)0x00D0
#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020
#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060
#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070
#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050
/* Mask on NOR STATUS REGISTER */
#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010
#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080
/* Address of the primary command set */
#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013
/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */
#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */
#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */
#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */
#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */
#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */
#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */
#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */
#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */
#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */
#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */
/**
* @}
@ -200,8 +226,11 @@ static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
* @param ExtTiming pointer to NOR extended mode timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
FMC_NORSRAM_TimingTypeDef *ExtTiming)
{
uint32_t deviceaddress;
/* Check the NOR handle parameter */
if (hnor == NULL)
{
@ -214,7 +243,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
hnor->Lock = HAL_UNLOCKED;
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
if(hnor->MspInitCallback == NULL)
if (hnor->MspInitCallback == NULL)
{
hnor->MspInitCallback = HAL_NOR_MspInit;
}
@ -252,7 +281,29 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
/* Initialize the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
return HAL_OK;
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Get the value of the command set */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
return HAL_NOR_ReturnToReadMode(hnor);
}
/**
@ -264,7 +315,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
{
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
if(hnor->MspDeInitCallback == NULL)
if (hnor->MspDeInitCallback == NULL)
{
hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
}
@ -367,6 +418,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
@ -401,15 +453,30 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
}
/* Send read ID command */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
/* Read the NOR IDs */
pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
if (status != HAL_ERROR)
{
/* Read the NOR IDs */
pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
}
/* Check the NOR controller state */
hnor->State = state;
@ -422,7 +489,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
return HAL_ERROR;
}
return HAL_OK;
return status;
}
/**
@ -435,6 +502,7 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
@ -468,7 +536,19 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
deviceaddress = NOR_MEMORY_ADRESS4;
}
NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
/* Check the NOR controller state */
hnor->State = state;
@ -481,7 +561,7 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
return HAL_ERROR;
}
return HAL_OK;
return status;
}
/**
@ -496,6 +576,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
@ -530,12 +611,27 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
}
/* Send read data command */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
/* Read the data */
*pData = (uint16_t)(*(__IO uint32_t *)pAddress);
if (status != HAL_ERROR)
{
/* Read the data */
*pData = (uint16_t)(*(__IO uint32_t *)pAddress);
}
/* Check the NOR controller state */
hnor->State = state;
@ -548,7 +644,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
return HAL_ERROR;
}
return HAL_OK;
return status;
}
/**
@ -562,6 +658,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
uint32_t deviceaddress;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
@ -595,12 +692,27 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
}
/* Send program data command */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
/* Write the data */
NOR_WRITE(pAddress, *pData);
if (status != HAL_ERROR)
{
/* Write the data */
NOR_WRITE(pAddress, *pData);
}
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@ -613,7 +725,7 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
return HAL_ERROR;
}
return HAL_OK;
return status;
}
/**
@ -625,11 +737,15 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
* @param uwBufferSize number of Half word to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
uint32_t uwBufferSize)
{
uint32_t deviceaddress, size = uwBufferSize, address = uwAddress;
uint32_t deviceaddress;
uint32_t size = uwBufferSize;
uint32_t address = uwAddress;
uint16_t *data = pData;
HAL_NOR_StateTypeDef state;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
@ -664,17 +780,32 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
}
/* Send read data command */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
/* Read buffer */
while (size > 0U)
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
*data = *(__IO uint16_t *)address;
data++;
address += 2U;
size--;
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
if (status != HAL_ERROR)
{
/* Read buffer */
while (size > 0U)
{
*data = *(__IO uint16_t *)address;
data++;
address += 2U;
size--;
}
}
/* Check the NOR controller state */
@ -688,7 +819,7 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
return HAL_ERROR;
}
return HAL_OK;
return status;
}
/**
@ -700,12 +831,14 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
* @param uwBufferSize Size of the buffer to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
uint32_t uwBufferSize)
{
uint16_t *p_currentaddress;
const uint16_t *p_endaddress;
uint16_t *data = pData;
uint32_t lastloadedaddress, deviceaddress;
uint32_t deviceaddress;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
@ -739,31 +872,51 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
}
/* Initialize variables */
p_currentaddress = (uint16_t *)(uwAddress);
p_endaddress = (const uint16_t *)(uwAddress + (uwBufferSize - 1U));
lastloadedaddress = uwAddress;
p_currentaddress = (uint16_t *)(deviceaddress + uwAddress);
p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U)));
/* Issue unlock command sequence */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
/* Write Buffer Load Command */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uint16_t)(uwBufferSize - 1U));
/* Load Data into NOR Buffer */
while (p_currentaddress <= p_endaddress)
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
/* Store last loaded address & data value (for polling) */
lastloadedaddress = (uint32_t)p_currentaddress;
/* Issue unlock command sequence */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(p_currentaddress, *data);
data++;
p_currentaddress ++;
/* Write Buffer Load Command */
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
/* Write Buffer Load Command */
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM);
NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
if (status != HAL_ERROR)
{
/* Load Data into NOR Buffer */
while (p_currentaddress <= p_endaddress)
{
NOR_WRITE(p_currentaddress, *data);
data++;
p_currentaddress ++;
}
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
}
else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */
{
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM);
}
}
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@ -776,7 +929,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
return HAL_ERROR;
}
return HAL_OK;
return status;
}
@ -791,6 +944,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
{
uint32_t deviceaddress;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
@ -824,12 +978,30 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
}
/* Send block erase command sequence */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK);
NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE);
NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
@ -842,7 +1014,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
return HAL_ERROR;
}
return HAL_OK;
return status;
}
@ -856,6 +1028,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
{
uint32_t deviceaddress;
HAL_StatusTypeDef status = HAL_OK;
UNUSED(Address);
/* Check the NOR controller state */
@ -890,12 +1063,23 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
}
/* Send NOR chip erase command sequence */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
@ -908,7 +1092,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
return HAL_ERROR;
}
return HAL_OK;
return status;
}
/**
@ -990,12 +1174,13 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
* @param pCallback : pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
pNOR_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_NOR_StateTypeDef state;
if(pCallback == NULL)
if (pCallback == NULL)
{
return HAL_ERROR;
}
@ -1004,20 +1189,20 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_Cal
__HAL_LOCK(hnor);
state = hnor->State;
if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
switch (CallbackId)
{
case HAL_NOR_MSP_INIT_CB_ID :
hnor->MspInitCallback = pCallback;
break;
case HAL_NOR_MSP_DEINIT_CB_ID :
hnor->MspDeInitCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
case HAL_NOR_MSP_INIT_CB_ID :
hnor->MspInitCallback = pCallback;
break;
case HAL_NOR_MSP_DEINIT_CB_ID :
hnor->MspDeInitCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
@ -1041,7 +1226,7 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_Cal
* @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_NOR_StateTypeDef state;
@ -1050,20 +1235,20 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C
__HAL_LOCK(hnor);
state = hnor->State;
if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
switch (CallbackId)
{
case HAL_NOR_MSP_INIT_CB_ID :
hnor->MspInitCallback = HAL_NOR_MspInit;
break;
case HAL_NOR_MSP_DEINIT_CB_ID :
hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
case HAL_NOR_MSP_INIT_CB_ID :
hnor->MspInitCallback = HAL_NOR_MspInit;
break;
case HAL_NOR_MSP_DEINIT_CB_ID :
hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
@ -1083,8 +1268,8 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C
*/
/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
* @brief management functions
*
* @brief management functions
*
@verbatim
==============================================================================
##### NOR Control functions #####
@ -1106,7 +1291,7 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
{
/* Check the NOR controller state */
if(hnor->State == HAL_NOR_STATE_PROTECTED)
if (hnor->State == HAL_NOR_STATE_PROTECTED)
{
/* Process Locked */
__HAL_LOCK(hnor);
@ -1140,7 +1325,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
{
/* Check the NOR controller state */
if(hnor->State == HAL_NOR_STATE_READY)
if (hnor->State == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@ -1170,8 +1355,8 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
*/
/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
* @brief Peripheral State functions
*
* @brief Peripheral State functions
*
@verbatim
==============================================================================
##### NOR State functions #####
@ -1207,7 +1392,8 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
{
HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
uint16_t tmpSR1, tmpSR2;
uint16_t tmpsr1;
uint16_t tmpsr2;
uint32_t tickstart;
/* Poll on NOR memory Ready/Busy signal ------------------------------------*/
@ -1217,45 +1403,84 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
/* Get tick */
tickstart = HAL_GetTick();
while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
status = HAL_NOR_STATUS_TIMEOUT;
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
status = HAL_NOR_STATUS_TIMEOUT;
}
}
/* Read NOR status register (DQ6 and DQ5) */
tmpsr1 = *(__IO uint16_t *)Address;
tmpsr2 = *(__IO uint16_t *)Address;
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
{
return HAL_NOR_STATUS_SUCCESS ;
}
if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
{
status = HAL_NOR_STATUS_ONGOING;
}
tmpsr1 = *(__IO uint16_t *)Address;
tmpsr2 = *(__IO uint16_t *)Address;
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
{
return HAL_NOR_STATUS_SUCCESS;
}
if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
{
return HAL_NOR_STATUS_ERROR;
}
}
/* Read NOR status register (DQ6 and DQ5) */
tmpSR1 = *(__IO uint16_t *)Address;
tmpSR2 = *(__IO uint16_t *)Address;
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
do
{
return HAL_NOR_STATUS_SUCCESS ;
}
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
tmpsr2 = *(__IO uint16_t *)(Address);
if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
{
status = HAL_NOR_STATUS_ONGOING;
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
return HAL_NOR_STATUS_TIMEOUT;
}
}
} while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U);
tmpSR1 = *(__IO uint16_t *)Address;
tmpSR2 = *(__IO uint16_t *)Address;
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
tmpsr1 = *(__IO uint16_t *)(Address);
if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U)
{
return HAL_NOR_STATUS_SUCCESS;
/* Clear the Status Register */
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
status = HAL_NOR_STATUS_ERROR;
}
if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
else
{
return HAL_NOR_STATUS_ERROR;
status = HAL_NOR_STATUS_SUCCESS;
}
}
else
{
/* Primary command set not supported by the driver */
status = HAL_NOR_STATUS_ERROR;
}
/* Return the operation status */
return status;

4
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_opamp.c
View File

@ -273,15 +273,15 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
if (hopamp->State == HAL_OPAMP_STATE_RESET)
{
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
if (hopamp->MspInitCallback == NULL)
{
hopamp->MspInitCallback = HAL_OPAMP_MspInit;
}
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
}
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
{

141
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pccard.c
View File

@ -162,7 +162,8 @@
* @param IOSpaceTiming IO space timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming,
FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
{
/* Check the PCCARD controller state */
if (hpccard == NULL)
@ -175,7 +176,7 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti
/* Allocate lock resource and initialize it */
hpccard->Lock = HAL_UNLOCKED;
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
if(hpccard->MspInitCallback == NULL)
if (hpccard->MspInitCallback == NULL)
{
hpccard->MspInitCallback = HAL_PCCARD_MspInit;
}
@ -223,7 +224,7 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
{
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
if(hpccard->MspDeInitCallback == NULL)
if (hpccard->MspDeInitCallback == NULL)
{
hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
}
@ -334,8 +335,7 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}
while ((status != PCCARD_STATUS_OK) && timeout);
} while ((status != PCCARD_STATUS_OK) && timeout);
if (timeout == 0U)
{
@ -368,7 +368,8 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp
* @param pStatus pointer to PCCARD status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus)
{
uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
uint8_t status = 0;
@ -398,8 +399,7 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
/* wait till the Status = 0x80 */
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}
while ((status == 0x80U) && timeout);
} while ((status == 0x80U) && timeout);
if (timeout == 0U)
{
@ -413,8 +413,7 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
/* wait till the Status = PCCARD_STATUS_OK */
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}
while ((status != PCCARD_STATUS_OK) && timeout);
} while ((status != PCCARD_STATUS_OK) && timeout);
if (timeout == 0U)
{
@ -446,7 +445,8 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
* @param pStatus pointer to PCCARD status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus)
{
uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
uint8_t status = 0;
@ -476,8 +476,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_
/* Wait till the Status = PCCARD_STATUS_OK */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}
while ((status != PCCARD_STATUS_OK) && timeout);
} while ((status != PCCARD_STATUS_OK) && timeout);
if (timeout == 0U)
{
@ -495,8 +494,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_
/* Wait till the Status = PCCARD_STATUS_WRITE_OK */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}
while ((status != PCCARD_STATUS_WRITE_OK) && timeout);
} while ((status != PCCARD_STATUS_WRITE_OK) && timeout);
if (timeout == 0U)
{
@ -615,7 +613,7 @@ HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval HAL status
*/
*/
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
{
/* Check PCCARD interrupt Rising edge flag */
@ -703,11 +701,12 @@ __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
* @param pCallback : pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_PCCARD_RegisterCallback (PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, pPCCARD_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId,
pPCCARD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if(pCallback == NULL)
if (pCallback == NULL)
{
return HAL_ERROR;
}
@ -715,39 +714,39 @@ HAL_StatusTypeDef HAL_PCCARD_RegisterCallback (PCCARD_HandleTypeDef *hpccard, HA
/* Process locked */
__HAL_LOCK(hpccard);
if(hpccard->State == HAL_PCCARD_STATE_READY)
if (hpccard->State == HAL_PCCARD_STATE_READY)
{
switch (CallbackId)
{
case HAL_PCCARD_MSP_INIT_CB_ID :
hpccard->MspInitCallback = pCallback;
break;
case HAL_PCCARD_MSP_DEINIT_CB_ID :
hpccard->MspDeInitCallback = pCallback;
break;
case HAL_PCCARD_IT_CB_ID :
hpccard->ItCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
case HAL_PCCARD_MSP_INIT_CB_ID :
hpccard->MspInitCallback = pCallback;
break;
case HAL_PCCARD_MSP_DEINIT_CB_ID :
hpccard->MspDeInitCallback = pCallback;
break;
case HAL_PCCARD_IT_CB_ID :
hpccard->ItCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else if(hpccard->State == HAL_PCCARD_STATE_RESET)
else if (hpccard->State == HAL_PCCARD_STATE_RESET)
{
switch (CallbackId)
{
case HAL_PCCARD_MSP_INIT_CB_ID :
hpccard->MspInitCallback = pCallback;
break;
case HAL_PCCARD_MSP_DEINIT_CB_ID :
hpccard->MspDeInitCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
case HAL_PCCARD_MSP_INIT_CB_ID :
hpccard->MspInitCallback = pCallback;
break;
case HAL_PCCARD_MSP_DEINIT_CB_ID :
hpccard->MspDeInitCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
@ -772,46 +771,46 @@ HAL_StatusTypeDef HAL_PCCARD_RegisterCallback (PCCARD_HandleTypeDef *hpccard, HA
* @arg @ref HAL_PCCARD_IT_CB_ID PCCARD IT callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback (PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId)
HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hpccard);
if(hpccard->State == HAL_PCCARD_STATE_READY)
if (hpccard->State == HAL_PCCARD_STATE_READY)
{
switch (CallbackId)
{
case HAL_PCCARD_MSP_INIT_CB_ID :
hpccard->MspInitCallback = HAL_PCCARD_MspInit;
break;
case HAL_PCCARD_MSP_DEINIT_CB_ID :
hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
break;
case HAL_PCCARD_IT_CB_ID :
hpccard->ItCallback = HAL_PCCARD_ITCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
case HAL_PCCARD_MSP_INIT_CB_ID :
hpccard->MspInitCallback = HAL_PCCARD_MspInit;
break;
case HAL_PCCARD_MSP_DEINIT_CB_ID :
hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
break;
case HAL_PCCARD_IT_CB_ID :
hpccard->ItCallback = HAL_PCCARD_ITCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else if(hpccard->State == HAL_PCCARD_STATE_RESET)
else if (hpccard->State == HAL_PCCARD_STATE_RESET)
{
switch (CallbackId)
{
case HAL_PCCARD_MSP_INIT_CB_ID :
hpccard->MspInitCallback = HAL_PCCARD_MspInit;
break;
case HAL_PCCARD_MSP_DEINIT_CB_ID :
hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
case HAL_PCCARD_MSP_INIT_CB_ID :
hpccard->MspInitCallback = HAL_PCCARD_MspInit;
break;
case HAL_PCCARD_MSP_DEINIT_CB_ID :
hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
@ -831,8 +830,8 @@ HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback (PCCARD_HandleTypeDef *hpccard,
*/
/** @defgroup PCCARD_Exported_Functions_Group3 State functions
* @brief Peripheral State functions
*
* @brief Peripheral State functions
*
@verbatim
==============================================================================
##### PCCARD State functions #####

2
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rcc_ex.c
View File

@ -108,6 +108,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
{
uint32_t tickstart = 0U;
uint32_t temp_reg = 0U;
FlagStatus pwrclkchanged = RESET;
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
@ -118,7 +119,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
FlagStatus pwrclkchanged = RESET;
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */

78
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rtc.c
View File

@ -766,6 +766,8 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc)
/**
* @brief Set RTC current time.
* @param hrtc RTC handle
* @note DayLightSaving and StoreOperation interfaces are deprecated.
* To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions.
* @param sTime Pointer to Time structure
* @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
@ -779,8 +781,6 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
/* Process Locked */
__HAL_LOCK(hrtc);
@ -849,10 +849,10 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
/* Set the RTC_TR register */
hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
/* Clear the bits to be configured */
/* Clear the bits to be configured (Deprecated. Use HAL_RTC_DST_xxx functions instead) */
hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK);
/* Configure the RTC_CR register */
/* Configure the RTC_CR register (Deprecated. Use HAL_RTC_DST_xxx functions instead) */
hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
/* Exit Initialization mode */
@ -1079,6 +1079,76 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
return HAL_OK;
}
/**
* @brief Daylight Saving Time, adda one hour to the calendar in one
* single operation without going through the initialization procedure.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc)
{
UNUSED(hrtc);
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
SET_BIT(RTC->CR, RTC_CR_ADD1H);
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
/**
* @brief Daylight Saving Time, subtracts one hour from the calendar in one
* single operation without going through the initialization procedure.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc)
{
UNUSED(hrtc);
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
SET_BIT(RTC->CR, RTC_CR_SUB1H);
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
/**
* @brief Daylight Saving Time, sets the store operation bit.
* @note It can be used by the software in order to memorize the DST status.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc)
{
UNUSED(hrtc);
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
SET_BIT(RTC->CR, RTC_CR_BKP);
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
/**
* @brief Daylight Saving Time, clears the store operation bit.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc)
{
UNUSED(hrtc);
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
CLEAR_BIT(RTC->CR, RTC_CR_BKP);
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
/**
* @brief Daylight Saving Time, reads the store operation bit.
* @param hrtc RTC handle
* @retval operation see RTC_StoreOperation_Definitions
*/
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc)
{
UNUSED(hrtc);
return READ_BIT(RTC->CR, RTC_CR_BKP);
}
/**
* @}
*/

277
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_smartcard.c
View File

@ -35,7 +35,8 @@
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
(+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
@ -107,8 +108,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback.
Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback.
Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
(+) TxCpltCallback : Tx Complete Callback.
(+) RxCpltCallback : Rx Complete Callback.
(+) ErrorCallback : Error Callback.
@ -121,9 +122,9 @@
and a pointer to the user callback function.
[..]
Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
@ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxCpltCallback : Tx Complete Callback.
@ -136,13 +137,13 @@
(+) MspDeInitCallback : SMARTCARD MspDeInit.
[..]
By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback().
examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init()
and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit()
reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init()
and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@ -151,8 +152,8 @@
in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit()
or @ref HAL_SMARTCARD_Init() function.
using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit()
or HAL_SMARTCARD_Init() function.
[..]
When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
@ -473,7 +474,8 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
pSMARTCARD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@ -599,36 +601,38 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
switch (CallbackID)
{
case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_SMARTCARD_ERROR_CB_ID :
hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
AbortTransmitCpltCallback*/
break;
case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
AbortReceiveCpltCallback */
break;
case HAL_SMARTCARD_MSPINIT_CB_ID :
hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_SMARTCARD_MSPDEINIT_CB_ID :
hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
@ -699,62 +703,67 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
(+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
[..]
(+) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
(#) There are two modes of transfer:
(##) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
(++) Non-Blocking mode: The communication is performed using Interrupts
(##) Non-Blocking mode: The communication is performed using Interrupts
or DMA, the relevant API's return the HAL status.
The end of the data processing will be indicated through the
dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
(++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
(##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
will be executed respectively at the end of the Transmit or Receive process
The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
error is detected.
(+) Blocking mode APIs are :
(++) HAL_SMARTCARD_Transmit()
(++) HAL_SMARTCARD_Receive()
(#) Blocking mode APIs are :
(##) HAL_SMARTCARD_Transmit()
(##) HAL_SMARTCARD_Receive()
(+) Non Blocking mode APIs with Interrupt are :
(++) HAL_SMARTCARD_Transmit_IT()
(++) HAL_SMARTCARD_Receive_IT()
(++) HAL_SMARTCARD_IRQHandler()
(#) Non Blocking mode APIs with Interrupt are :
(##) HAL_SMARTCARD_Transmit_IT()
(##) HAL_SMARTCARD_Receive_IT()
(##) HAL_SMARTCARD_IRQHandler()
(+) Non Blocking mode functions with DMA are :
(++) HAL_SMARTCARD_Transmit_DMA()
(++) HAL_SMARTCARD_Receive_DMA()
(#) Non Blocking mode functions with DMA are :
(##) HAL_SMARTCARD_Transmit_DMA()
(##) HAL_SMARTCARD_Receive_DMA()
(+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_SMARTCARD_TxCpltCallback()
(++) HAL_SMARTCARD_RxCpltCallback()
(++) HAL_SMARTCARD_ErrorCallback()
(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(##) HAL_SMARTCARD_TxCpltCallback()
(##) HAL_SMARTCARD_RxCpltCallback()
(##) HAL_SMARTCARD_ErrorCallback()
[..]
(#) Non-Blocking mode transfers could be aborted using Abort API's :
(++) HAL_SMARTCARD_Abort()
(++) HAL_SMARTCARD_AbortTransmit()
(++) HAL_SMARTCARD_AbortReceive()
(++) HAL_SMARTCARD_Abort_IT()
(++) HAL_SMARTCARD_AbortTransmit_IT()
(++) HAL_SMARTCARD_AbortReceive_IT()
(##) HAL_SMARTCARD_Abort()
(##) HAL_SMARTCARD_AbortTransmit()
(##) HAL_SMARTCARD_AbortReceive()
(##) HAL_SMARTCARD_Abort_IT()
(##) HAL_SMARTCARD_AbortTransmit_IT()
(##) HAL_SMARTCARD_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
(++) HAL_SMARTCARD_AbortCpltCallback()
(++) HAL_SMARTCARD_AbortTransmitCpltCallback()
(++) HAL_SMARTCARD_AbortReceiveCpltCallback()
(#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT),
a set of Abort Complete Callbacks are provided:
(##) HAL_SMARTCARD_AbortCpltCallback()
(##) HAL_SMARTCARD_AbortTransmitCpltCallback()
(##) HAL_SMARTCARD_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
If user wants to abort it, Abort services should be called by user.
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
(##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
to be evaluated by user : this concerns Frame Error,
Parity Error or Noise Error in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer,
Error code is set to allow user to identify error type,
and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
If user wants to abort it, Abort services should be called by user.
(##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt
mode reception and all errors in DMA mode.
Error code is set to allow user to identify error type,
and HAL_SMARTCARD_ErrorCallback() user callback is executed.
@endverbatim
* @{
@ -794,14 +803,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
/* Disable the Peripheral first to update mode for TX master */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* Disable Rx, enable Tx */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
/* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
the bidirectional line to detect a NACK signal in case of parity error.
Therefore, the receiver block must be enabled as well (RE bit must be set). */
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
/* Enable Tx */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
/* Enable the Peripheral */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* Perform a TX/RX FIFO Flush */
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsmartcard->TxXferSize = Size;
hsmartcard->TxXferCount = Size;
@ -816,20 +834,28 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
ptmpdata++;
}
if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart,
Timeout) != HAL_OK)
if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET,
tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
/* Disable the Peripheral first to update mode */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
/* Disable the Peripheral first to update modes */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
/* Enable the Peripheral */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* In case of TX only mode, if NACK is enabled, receiver block has been enabled
for Transmit phase. Disable this receiver block. */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
|| (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
/* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
}
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* At end of Tx process, restore hsmartcard->gState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@ -939,14 +965,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard,
/* Disable the Peripheral first to update mode for TX master */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* Disable Rx, enable Tx */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
/* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
the bidirectional line to detect a NACK signal in case of parity error.
Therefore, the receiver block must be enabled as well (RE bit must be set). */
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
/* Enable Tx */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
/* Enable the Peripheral */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* Perform a TX/RX FIFO Flush */
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
/* Configure Tx interrupt processing */
/* Set the Tx ISR function pointer */
hsmartcard->TxISR = SMARTCARD_TxISR;
@ -1048,14 +1083,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard
/* Disable the Peripheral first to update mode for TX master */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* Disable Rx, enable Tx */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
/* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
the bidirectional line to detect a NACK signal in case of parity error.
Therefore, the receiver block must be enabled as well (RE bit must be set). */
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
/* Enable Tx */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
/* Enable the Peripheral */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* Perform a TX/RX FIFO Flush */
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
/* Set the SMARTCARD DMA transfer complete callback */
hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
@ -1198,7 +1242,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1,
(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE |
USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
/* Disable the SMARTCARD DMA Tx request if enabled */
@ -1257,8 +1302,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@ -1388,8 +1433,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@ -1418,11 +1463,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1,
(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE |
USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
/* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle,
DMA Abort complete callbacks should be initialised before any call
to DMA Abort functions */
/* DMA Tx Handle is valid */
if (hsmartcard->hdmatx != NULL)
{
@ -1516,8 +1563,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@ -1687,8 +1734,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@ -1713,8 +1760,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@ -2156,12 +2203,14 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Init the SMARTCARD Callback settings */
hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
AbortTransmitCpltCallback */
hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
AbortReceiveCpltCallback */
}
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
@ -2200,7 +2249,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
* Configure the Parity and Mode:
* set PS bit according to hsmartcard->Init.Parity value
* set TE and RE bits according to hsmartcard->Init.Mode value */
tmpreg = (uint32_t)(hsmartcard->Init.Parity | hsmartcard->Init.Mode | hsmartcard->Init.WordLength);
tmpreg = ((uint32_t)(hsmartcard->Init.Parity)) | ((uint32_t)(hsmartcard->Init.Mode)) | ((uint32_t)(hsmartcard->Init.WordLength));
MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/
@ -2416,7 +2465,8 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
@ -2610,8 +2660,8 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@ -2659,8 +2709,8 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@ -2721,8 +2771,8 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@ -2784,15 +2834,22 @@ static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
}
/* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
/* Disable the Peripheral first to update mode */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
/* Disable the Peripheral first to update modes */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
/* Enable the Peripheral */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* In case of TX only mode, if NACK is enabled, receiver block has been enabled
for Transmit phase. Disable this receiver block. */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
|| (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
/* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
}
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* Tx process is ended, restore hsmartcard->gState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;

6
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_smartcard_ex.c
View File

@ -165,12 +165,6 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef
/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions
* @brief SMARTCARD Transmit and Receive functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..]
@endverbatim
* @{
*/

263
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_spi.c
View File

@ -131,7 +131,7 @@
DataSize = SPI_DATASIZE_8BIT:
+----------------------------------------------------------------------------------------------+
| | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
| Process | Tranfert mode |---------------------|----------------------|----------------------|
| Process | Transfer mode |---------------------|----------------------|----------------------|
| | | Master | Slave | Master | Slave | Master | Slave |
|==============================================================================================|
| T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
@ -156,7 +156,7 @@
DataSize = SPI_DATASIZE_16BIT:
+----------------------------------------------------------------------------------------------+
| | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
| Process | Tranfert mode |---------------------|----------------------|----------------------|
| Process | Transfer mode |---------------------|----------------------|----------------------|
| | | Master | Slave | Master | Slave | Master | Slave |
|==============================================================================================|
| T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
@ -337,6 +337,24 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
}
}
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
}
#if (USE_SPI_CRC != 0U)
assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
@ -400,44 +418,56 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
}
/* Align the CRC Length on the data size */
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
{
/* CRC Length aligned on the data size : value set by default */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
}
else
{
hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
}
}
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
(hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
(hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
(hspi->Init.CLKPhase & SPI_CR1_CPHA) |
(hspi->Init.NSS & SPI_CR1_SSM) |
(hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
#if (USE_SPI_CRC != 0U)
/* Configure : CRC Length */
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
/*---------------------------- SPIx CRCL Configuration -------------------*/
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCL;
/* Align the CRC Length on the data size */
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
{
/* CRC Length aligned on the data size : value set by default */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
}
else
{
hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
}
}
/* Configure : CRC Length */
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL);
}
}
#endif /* USE_SPI_CRC */
/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
(hspi->Init.TIMode & SPI_CR2_FRF) |
(hspi->Init.NSSPMode & SPI_CR2_NSSP) |
(hspi->Init.DataSize & SPI_CR2_DS_Msk) |
(frxth & SPI_CR2_FRXTH)));
#if (USE_SPI_CRC != 0U)
/*---------------------------- SPIx CRCPOLY Configuration ------------------*/
/* Configure : CRC Polynomial */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
}
#endif /* USE_SPI_CRC */
@ -835,6 +865,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_TX(hspi);
}
@ -1042,6 +1074,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Configure communication direction: 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_RX(hspi);
}
@ -1544,6 +1578,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_TX(hspi);
}
@ -1635,6 +1671,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_RX(hspi);
}
@ -1835,6 +1873,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_TX(hspi);
}
@ -1965,6 +2005,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_RX(hspi);
}
@ -3070,8 +3112,17 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
}
#endif /* USE_SPI_CRC */
/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
/* Check if we are in Master RX 2 line mode */
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
}
else
{
/* Normal case */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
}
/* Check the end of the transaction */
if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
@ -3488,7 +3539,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
/* Read 8bit CRC to flush Data Regsiter */
/* Read 8bit CRC to flush Data Register */
READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
hspi->CRCSize--;
@ -3596,7 +3647,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
/* Read 16bit CRC to flush Data Regsiter */
/* Read 16bit CRC to flush Data Register */
READ_REG(hspi->Instance->DR);
/* Disable RXNE interrupt */
@ -3813,69 +3864,22 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart)
{
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
tmp_tickstart = HAL_GetTick();
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
{
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
/**
* @brief Handle SPI FIFO Communication Timeout.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param Fifo Fifo to check
* @param State Fifo state to check
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
uint32_t Timeout, uint32_t Tickstart)
{
while ((hspi->Instance->SR & Fifo) != State)
{
if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
{
/* Read 8bit CRC to flush Data Register */
READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
}
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
@ -3904,6 +3908,87 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi,
return HAL_TIMEOUT;
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
if(count == 0U)
{
tmp_timeout = 0U;
}
count--;
}
}
return HAL_OK;
}
/**
* @brief Handle SPI FIFO Communication Timeout.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param Fifo Fifo to check
* @param State Fifo state to check
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
uint32_t Timeout, uint32_t Tickstart)
{
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
tmp_tickstart = HAL_GetTick();
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
while ((hspi->Instance->SR & Fifo) != State)
{
if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
{
/* Read 8bit CRC to flush Data Register */
READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
}
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return HAL_TIMEOUT;
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
if(count == 0U)
{
tmp_timeout = 0U;
}
count--;
}
}
@ -3990,7 +4075,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
{
uint32_t tickstart;
/* Init tickstart for timeout managment*/
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Disable ERR interrupt */

194
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_sram.c
View File

@ -136,9 +136,9 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void SRAM_DMACplt (DMA_HandleTypeDef *hdma);
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
static void SRAM_DMAError (DMA_HandleTypeDef *hdma);
static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
/**
@endcond
*/
@ -171,7 +171,8 @@ static void SRAM_DMAError (DMA_HandleTypeDef *hdma);
* @param ExtTiming Pointer to SRAM extended mode timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
FMC_NORSRAM_TimingTypeDef *ExtTiming)
{
/* Check the SRAM handle parameter */
if (hsram == NULL)
@ -185,7 +186,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp
hsram->Lock = HAL_UNLOCKED;
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
if(hsram->MspInitCallback == NULL)
if (hsram->MspInitCallback == NULL)
{
hsram->MspInitCallback = HAL_SRAM_MspInit;
}
@ -207,7 +208,8 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp
(void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
/* Initialize SRAM extended mode timing Interface */
(void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
(void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
hsram->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
@ -227,7 +229,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
{
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
if(hsram->MspDeInitCallback == NULL)
if (hsram->MspDeInitCallback == NULL)
{
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
}
@ -342,11 +344,12 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
uint32_t BufferSize)
{
uint32_t size;
__IO uint8_t *psramaddress = (uint8_t *)pAddress;
uint8_t * pdestbuff = pDstBuffer;
uint8_t *pdestbuff = pDstBuffer;
HAL_SRAM_StateTypeDef state = hsram->State;
/* Check the SRAM controller state */
@ -389,11 +392,12 @@ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
uint32_t BufferSize)
{
uint32_t size;
__IO uint8_t *psramaddress = (uint8_t *)pAddress;
uint8_t * psrcbuff = pSrcBuffer;
uint8_t *psrcbuff = pSrcBuffer;
/* Check the SRAM controller state */
if (hsram->State == HAL_SRAM_STATE_READY)
@ -435,7 +439,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t *psramaddress = pAddress;
@ -452,11 +457,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Check if the size is a 32-bits mulitple */
/* Check if the size is a 32-bits multiple */
limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
/* Read data from memory */
for (size = BufferSize; size != limit; size-=2U)
for (size = BufferSize; size != limit; size -= 2U)
{
*pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
pdestbuff++;
@ -494,11 +499,12 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t *psramaddress = pAddress;
uint16_t * psrcbuff = pSrcBuffer;
uint16_t *psrcbuff = pSrcBuffer;
uint8_t limit;
/* Check the SRAM controller state */
@ -510,11 +516,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Check if the size is a 32-bits mulitple */
/* Check if the size is a 32-bits multiple */
limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
/* Write data to memory */
for (size = BufferSize; size != limit; size-=2U)
for (size = BufferSize; size != limit; size -= 2U)
{
*psramaddress = (uint32_t)(*psrcbuff);
psrcbuff++;
@ -552,11 +558,12 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t * psramaddress = pAddress;
uint32_t * pdestbuff = pDstBuffer;
__IO uint32_t *psramaddress = pAddress;
uint32_t *pdestbuff = pDstBuffer;
HAL_SRAM_StateTypeDef state = hsram->State;
/* Check the SRAM controller state */
@ -599,11 +606,12 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t * psramaddress = pAddress;
uint32_t * psrcbuff = pSrcBuffer;
__IO uint32_t *psramaddress = pAddress;
uint32_t *psrcbuff = pSrcBuffer;
/* Check the SRAM controller state */
if (hsram->State == HAL_SRAM_STATE_READY)
@ -645,7 +653,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
uint32_t BufferSize)
{
HAL_StatusTypeDef status;
HAL_SRAM_StateTypeDef state = hsram->State;
@ -678,7 +687,7 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
}
else
{
return HAL_ERROR;
status = HAL_ERROR;
}
return status;
@ -693,7 +702,8 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
uint32_t BufferSize)
{
HAL_StatusTypeDef status;
@ -718,7 +728,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
}
else
{
return HAL_ERROR;
status = HAL_ERROR;
}
return status;
@ -736,12 +746,13 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
* @param pCallback : pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
pSRAM_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
if(pCallback == NULL)
if (pCallback == NULL)
{
return HAL_ERROR;
}
@ -750,20 +761,20 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM
__HAL_LOCK(hsram);
state = hsram->State;
if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
{
switch (CallbackId)
{
case HAL_SRAM_MSP_INIT_CB_ID :
hsram->MspInitCallback = pCallback;
break;
case HAL_SRAM_MSP_DEINIT_CB_ID :
hsram->MspDeInitCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
case HAL_SRAM_MSP_INIT_CB_ID :
hsram->MspInitCallback = pCallback;
break;
case HAL_SRAM_MSP_DEINIT_CB_ID :
hsram->MspDeInitCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
@ -789,7 +800,7 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM
* @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
@ -798,42 +809,42 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SR
__HAL_LOCK(hsram);
state = hsram->State;
if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
{
switch (CallbackId)
{
case HAL_SRAM_MSP_INIT_CB_ID :
hsram->MspInitCallback = HAL_SRAM_MspInit;
break;
case HAL_SRAM_MSP_DEINIT_CB_ID :
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
break;
case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
break;
case HAL_SRAM_DMA_XFER_ERR_CB_ID :
hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
case HAL_SRAM_MSP_INIT_CB_ID :
hsram->MspInitCallback = HAL_SRAM_MspInit;
break;
case HAL_SRAM_MSP_DEINIT_CB_ID :
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
break;
case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
break;
case HAL_SRAM_DMA_XFER_ERR_CB_ID :
hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else if(state == HAL_SRAM_STATE_RESET)
else if (state == HAL_SRAM_STATE_RESET)
{
switch (CallbackId)
{
case HAL_SRAM_MSP_INIT_CB_ID :
hsram->MspInitCallback = HAL_SRAM_MspInit;
break;
case HAL_SRAM_MSP_DEINIT_CB_ID :
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
case HAL_SRAM_MSP_INIT_CB_ID :
hsram->MspInitCallback = HAL_SRAM_MspInit;
break;
case HAL_SRAM_MSP_DEINIT_CB_ID :
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
@ -858,12 +869,13 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SR
* @param pCallback : pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
pSRAM_DmaCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
if(pCallback == NULL)
if (pCallback == NULL)
{
return HAL_ERROR;
}
@ -872,20 +884,20 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR
__HAL_LOCK(hsram);
state = hsram->State;
if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
{
switch (CallbackId)
{
case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
hsram->DmaXferCpltCallback = pCallback;
break;
case HAL_SRAM_DMA_XFER_ERR_CB_ID :
hsram->DmaXferErrorCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
hsram->DmaXferCpltCallback = pCallback;
break;
case HAL_SRAM_DMA_XFER_ERR_CB_ID :
hsram->DmaXferErrorCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
@ -905,8 +917,8 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR
*/
/** @defgroup SRAM_Exported_Functions_Group3 Control functions
* @brief Control functions
*
* @brief Control functions
*
@verbatim
==============================================================================
##### SRAM Control functions #####
@ -928,7 +940,7 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
{
/* Check the SRAM controller state */
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
if (hsram->State == HAL_SRAM_STATE_PROTECTED)
{
/* Process Locked */
__HAL_LOCK(hsram);
@ -962,7 +974,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
{
/* Check the SRAM controller state */
if(hsram->State == HAL_SRAM_STATE_READY)
if (hsram->State == HAL_SRAM_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsram);
@ -992,8 +1004,8 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
*/
/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
* @brief Peripheral State functions
*
@verbatim
==============================================================================
##### SRAM State functions #####
@ -1035,7 +1047,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
*/
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
{
SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hdma);
@ -1057,7 +1069,7 @@ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
*/
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
{
SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hdma);
@ -1079,7 +1091,7 @@ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
*/
static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
{
SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hdma);

1018
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_tim.c
View File

File diff suppressed because it is too large Load Diff

481
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_tim_ex.c
View File

@ -56,7 +56,7 @@
the commutation event).
(#) Activate the TIM peripheral using one of the start functions:
(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
(++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
(++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
@ -92,9 +92,11 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
/* Exported functions --------------------------------------------------------*/
@ -125,6 +127,9 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha
*/
/**
* @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
* @note When the timer instance is initialized in Hall Sensor Interface mode,
* timer channels 1 and channel 2 are reserved and cannot be used for
* other purpose.
* @param htim TIM Hall Sensor Interface handle
* @param sConfig TIM Hall Sensor configuration structure
* @retval HAL status
@ -210,6 +215,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
htim->Instance->CR2 &= ~TIM_CR2_MMS;
htim->Instance->CR2 |= TIM_TRGO_OC2REF;
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@ -243,6 +257,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
HAL_TIMEx_HallSensor_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
/* Change the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@ -290,17 +313,43 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
{
uint32_t tmpsmcr;
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
@ -326,6 +375,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -338,10 +393,29 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
{
uint32_t tmpsmcr;
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the capture compare Interrupts 1 event */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
@ -350,8 +424,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
@ -380,6 +461,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -394,29 +481,36 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
{
uint32_t tmpsmcr;
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
if (htim->State == HAL_TIM_STATE_BUSY)
/* Set the TIM channel state */
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
|| (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if (htim->State == HAL_TIM_STATE_READY)
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
if (((uint32_t)pData == 0U) && (Length > 0U))
if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
/* nothing to do */
return HAL_ERROR;
}
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
@ -430,14 +524,22 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
/* Enable the DMA channel for Capture 1*/
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the capture compare 1 Interrupt */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
@ -465,9 +567,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -514,6 +621,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
/* Check the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
@ -521,8 +637,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
@ -556,6 +679,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -578,6 +704,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
/* Check the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
switch (Channel)
{
case TIM_CHANNEL_1:
@ -616,8 +751,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
@ -686,6 +828,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -710,24 +855,25 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
if (htim->State == HAL_TIM_STATE_BUSY)
/* Set the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
else if (htim->State == HAL_TIM_STATE_READY)
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
if (((uint32_t)pData == 0U) && (Length > 0U))
if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
/* nothing to do */
return HAL_ERROR;
}
switch (Channel)
@ -735,15 +881,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
case TIM_CHANNEL_1:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@ -754,15 +901,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
case TIM_CHANNEL_2:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@ -773,15 +921,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
case TIM_CHANNEL_3:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@ -800,8 +949,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
@ -865,8 +1021,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@ -923,6 +1079,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
/* Check the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
@ -930,8 +1095,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
@ -964,6 +1136,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -986,6 +1161,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
/* Check the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
switch (Channel)
{
case TIM_CHANNEL_1:
@ -1023,8 +1207,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
@ -1094,6 +1285,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -1118,39 +1312,42 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
if (htim->State == HAL_TIM_STATE_BUSY)
/* Set the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
else if (htim->State == HAL_TIM_STATE_READY)
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
if (((uint32_t)pData == 0U) && (Length > 0U))
if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
/* nothing to do */
return HAL_ERROR;
}
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 1 DMA request */
@ -1161,15 +1358,16 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
case TIM_CHANNEL_2:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@ -1180,15 +1378,16 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
case TIM_CHANNEL_3:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@ -1207,8 +1406,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
@ -1272,8 +1478,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@ -1313,11 +1519,27 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Enable the complementary One Pulse output */
/* Check the TIM channels state */
if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
|| (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
@ -1338,12 +1560,14 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Disable the complementary One Pulse output */
/* Disable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@ -1351,6 +1575,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -1367,17 +1595,33 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Check the TIM channels state */
if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
|| (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
/* Enable the complementary One Pulse output */
/* Enable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
@ -1398,6 +1642,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
@ -1407,8 +1653,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
/* Disable the complementary One Pulse output */
/* Disable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@ -1416,6 +1663,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -2011,6 +2262,27 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
return htim->State;
}
/**
* @brief Return actual state of the TIM complementary channel.
* @param htim TIM handle
* @param ChannelN TIM Complementary channel
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1
* @arg TIM_CHANNEL_2: TIM Channel 2
* @arg TIM_CHANNEL_3: TIM Channel 3
* @retval TIM Complementary channel state
*/
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
{
HAL_TIM_ChannelStateTypeDef channel_state;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
return channel_state;
}
/**
* @}
*/
@ -2063,6 +2335,103 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
}
/**
* @brief TIM DMA Delay Pulse complete callback (complementary channel).
* @param hdma pointer to DMA handle.
* @retval None
*/
static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
}
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
}
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
}
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
}
}
else
{
/* nothing to do */
}
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
* @brief TIM DMA error callback (complementary channel)
* @param hdma pointer to DMA handle.
* @retval None
*/
static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
}
else
{
/* nothing to do */
}
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->ErrorCallback(htim);
#else
HAL_TIM_ErrorCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
* @param TIMx to select the TIM peripheral

181
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_timebase_rtc_alarm_template.c
View File

@ -93,12 +93,13 @@ void RTC_Alarm_IRQHandler(void);
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
__IO uint32_t counter = 0U;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
HAL_StatusTypeDef status;
#ifdef RTC_CLOCK_SOURCE_LSE
/* Configue LSE as RTC clock soucre */
@ -122,92 +123,112 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
#error Please select the RTC Clock source
#endif /* RTC_CLOCK_SOURCE_LSE */
if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
status = HAL_RCC_OscConfig(&RCC_OscInitStruct);
if (status == HAL_OK)
{
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
}
if (status == HAL_OK)
{
/* Enable RTC Clock */
__HAL_RCC_RTC_ENABLE();
/* The time base should be 1ms
Time base = ((RTC_ASYNCH_PREDIV + 1U) * (RTC_SYNCH_PREDIV + 1U)) / RTC_CLOCK
HSE/32 as RTC clock and HSE 8MHz
Time base = ((49U + 1U) * (4U + 1U)) / 250kHz
= 1ms
LSE as RTC clock
Time base = ((31U + 1U) * (0U + 1U)) / 32.768KHz
= ~1ms
LSI as RTC clock
Time base = ((39U + 1U) * (0U + 1U)) / 40KHz
= 1ms
*/
hRTC_Handle.Instance = RTC;
hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
status = HAL_RTC_Init(&hRTC_Handle);
}
if (status == HAL_OK)
{
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
/* Disable the Alarm A interrupt */
__HAL_RTC_ALARMA_DISABLE(&hRTC_Handle);
/* Clear flag alarm A */
__HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF);
counter = 0U;
/* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAWF) == RESET)
{
/* Enable RTC Clock */
__HAL_RCC_RTC_ENABLE();
/* The time base should be 1ms
Time base = ((RTC_ASYNCH_PREDIV + 1U) * (RTC_SYNCH_PREDIV + 1U)) / RTC_CLOCK
HSE/32 as RTC clock and HSE 8MHz
Time base = ((49U + 1U) * (4U + 1U)) / 250kHz
= 1ms
LSE as RTC clock
Time base = ((31U + 1U) * (0U + 1U)) / 32.768KHz
= ~1ms
LSI as RTC clock
Time base = ((39U + 1U) * (0U + 1U)) / 40KHz
= 1ms
*/
hRTC_Handle.Instance = RTC;
hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
HAL_RTC_Init(&hRTC_Handle);
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
/* Disable the Alarm A interrupt */
__HAL_RTC_ALARMA_DISABLE(&hRTC_Handle);
/* Clear flag alarm A */
__HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF);
counter = 0U;
/* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAWF) == RESET)
if(counter++ == (SystemCoreClock / 48U)) /* Timeout = ~ 1s */
{
if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
{
return HAL_ERROR;
}
status = HAL_ERROR;
}
hRTC_Handle.Instance->ALRMAR = 0x01U;
/* Configure the Alarm state: Enable Alarm */
__HAL_RTC_ALARMA_ENABLE(&hRTC_Handle);
/* Configure the Alarm interrupt */
__HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
/* RTC Alarm Interrupt Configuration: EXTI configuration */
__HAL_RTC_ALARM_EXTI_ENABLE_IT();
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
/* Check if the Initialization mode is set */
if((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
{
/* Set the Initialization mode */
hRTC_Handle.Instance->ISR = (uint32_t)RTC_INIT_MASK;
counter = 0U;
while((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
{
if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
{
return HAL_ERROR;
}
}
}
hRTC_Handle.Instance->DR = 0U;
hRTC_Handle.Instance->TR = 0U;
hRTC_Handle.Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U);
HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
return HAL_OK;
}
}
return HAL_ERROR;
if (status == HAL_OK)
{
hRTC_Handle.Instance->ALRMAR = 0x01U;
/* Configure the Alarm state: Enable Alarm */
__HAL_RTC_ALARMA_ENABLE(&hRTC_Handle);
/* Configure the Alarm interrupt */
__HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
/* RTC Alarm Interrupt Configuration: EXTI configuration */
__HAL_RTC_ALARM_EXTI_ENABLE_IT();
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
/* Check if the Initialization mode is set */
if ((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
{
/* Set the Initialization mode */
hRTC_Handle.Instance->ISR = (uint32_t)RTC_INIT_MASK;
counter = 0U;
while((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
{
if(counter++ == (SystemCoreClock / 48U)) /* Timeout = ~ 1s */
{
status = HAL_ERROR;
}
}
}
}
if (status == HAL_OK)
{
hRTC_Handle.Instance->DR = 0U;
hRTC_Handle.Instance->TR = 0U;
hRTC_Handle.Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
/* Enable the RTC Alarm Interrupt */
HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
{
HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U);
uwTickPrio = TickPriority;
}
else
{
status = HAL_ERROR;
}
}
return status;
}
/**

151
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_timebase_rtc_wakeup_template.c
View File

@ -100,12 +100,13 @@ void RTC_WKUP_IRQHandler(void);
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
__IO uint32_t counter = 0U;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
HAL_StatusTypeDef status;
#ifdef RTC_CLOCK_SOURCE_LSE
/* Configue LSE as RTC clock soucre */
@ -129,25 +130,29 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
#error Please select the RTC Clock source
#endif /* RTC_CLOCK_SOURCE_LSE */
if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
status = HAL_RCC_OscConfig(&RCC_OscInitStruct);
if (status == HAL_OK)
{
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
{
/* Enable RTC Clock */
__HAL_RCC_RTC_ENABLE();
/* The time base should be 1ms
Time base = ((RTC_ASYNCH_PREDIV + 1U) * (RTC_SYNCH_PREDIV + 1U)) / RTC_CLOCK
HSE/32 as RTC clock and HSE 8MHz
Time base = ((49U + 1U) * (4U + 1U)) / 250kHz
= 1ms
LSE as RTC clock
Time base = ((31U + 1U) * (0U + 1U)) / 32.768Khz
= ~1ms
LSI as RTC clock
Time base = ((39U + 1U) * (0U + 1U)) / 40Khz
= 1ms
*/
status = (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct));
}
if (status == HAL_OK)
{
/* Enable RTC Clock */
__HAL_RCC_RTC_ENABLE();
/* The time base should be 1ms
Time base = ((RTC_ASYNCH_PREDIV + 1U) * (RTC_SYNCH_PREDIV + 1U)) / RTC_CLOCK
HSE/32 as RTC clock and HSE 8MHz
Time base = ((49U + 1U) * (4U + 1U)) / 250kHz
= 1ms
LSE as RTC clock
Time base = ((31U + 1U) * (0U + 1U)) / 32.768Khz
= ~1ms
LSI as RTC clock
Time base = ((39U + 1U) * (0U + 1U)) / 40Khz
= 1ms
*/
hRTC_Handle.Instance = RTC;
hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
@ -155,61 +160,75 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
HAL_RTC_Init(&hRTC_Handle);
status = HAL_RTC_Init(&hRTC_Handle);
}
if (status == HAL_OK)
{
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
/* Disable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(&hRTC_Handle);
/* Disable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(&hRTC_Handle);
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT);
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle,RTC_IT_WUT);
/* Wait till RTC WUTWF flag is set */
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == RESET)
/* Wait till RTC WUTWF flag is set */
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == RESET)
{
if(counter++ == (SystemCoreClock / 48U))
{
if(counter++ == (SystemCoreClock /48U))
{
return HAL_ERROR;
}
status = HAL_ERROR;
}
/* Clear PWR wake up Flag */
__HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU);
/* Clear RTC Wake Up timer Flag */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_WUTF);
/* Configure the Wake-up Timer counter */
hRTC_Handle.Instance->WUTR = 0U;
/* Clear the Wake-up Timer clock source bits in CR register */
hRTC_Handle.Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
/* Configure the clock source */
hRTC_Handle.Instance->CR |= (uint32_t)RTC_WAKEUPCLOCK_CK_SPRE_16BITS;
/* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
/* Configure the Interrupt in the RTC_CR register */
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle,RTC_IT_WUT);
/* Enable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_ENABLE(&hRTC_Handle);
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
HAL_NVIC_SetPriority(RTC_WKUP_IRQn, TickPriority, 0U);
HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
return HAL_OK;
}
}
return HAL_ERROR;
if (status == HAL_OK)
{
/* Clear PWR wake up Flag */
__HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU);
/* Clear RTC Wake Up timer Flag */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_WUTF);
/* Configure the Wake-up Timer counter */
hRTC_Handle.Instance->WUTR = 0U;
/* Clear the Wake-up Timer clock source bits in CR register */
hRTC_Handle.Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
/* Configure the clock source */
hRTC_Handle.Instance->CR |= (uint32_t)RTC_WAKEUPCLOCK_CK_SPRE_16BITS;
/* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
/* Configure the Interrupt in the RTC_CR register */
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle,RTC_IT_WUT);
/* Enable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_ENABLE(&hRTC_Handle);
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
/* Enable the RTC global Interrupt */
HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
{
HAL_NVIC_SetPriority(RTC_WKUP_IRQn, TickPriority, 0U);
uwTickPrio = TickPriority;
}
else
{
status = HAL_ERROR;
}
}
return status;
}
/**

33
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_timebase_tim_template.c
View File

@ -57,12 +57,7 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
uint32_t uwTimclock, uwAPB1Prescaler = 0U;
uint32_t uwPrescalerValue = 0U;
uint32_t pFLatency;
/*Configure the TIM6 IRQ priority */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U);
/* Enable the TIM6 global Interrupt */
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
HAL_StatusTypeDef status;
/* Enable TIM6 clock */
__HAL_RCC_TIM6_CLK_ENABLE();
@ -80,7 +75,7 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
}
else
{
uwTimclock = 2U*HAL_RCC_GetPCLK1Freq();
uwTimclock = 2U * HAL_RCC_GetPCLK1Freq();
}
/* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
@ -100,14 +95,30 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
TimHandle.Init.ClockDivision = 0U;
TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if(HAL_TIM_Base_Init(&TimHandle) == HAL_OK)
status = HAL_TIM_Base_Init(&TimHandle);
if (status == HAL_OK)
{
/* Start the TIM time Base generation in interrupt mode */
return HAL_TIM_Base_Start_IT(&TimHandle);
}
status = HAL_TIM_Base_Start_IT(&TimHandle);
if (status == HAL_OK)
{
/* Enable the TIM6 global Interrupt */
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
{
/* Enable the TIM6 global Interrupt */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0);
uwTickPrio = TickPriority;
}
else
{
status = HAL_ERROR;
}
}
}
/* Return function status */
return HAL_ERROR;
return status;
}
/**

4
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_tsc.c
View File

@ -257,6 +257,7 @@ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc)
assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation));
assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler));
assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler));
assert_param(IS_TSC_PG_PRESC_VS_CTPL(htsc->Init.PulseGeneratorPrescaler, htsc->Init.CTPulseLowLength));
assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue));
assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode));
assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
@ -430,7 +431,8 @@ __weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc)
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID,
pTSC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;

656
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_uart.c
View File

File diff suppressed because it is too large Load Diff

281
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_uart_ex.c
View File

@ -277,6 +277,41 @@ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
(+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
(+) HAL_UARTEx_DisableStopMode() API disables the above functionality
[..] This subsection also provides a set of additional functions providing enhanced reception
services to user. (For example, these functions allow application to handle use cases
where number of data to be received is unknown).
(#) Compared to standard reception services which only consider number of received
data elements as reception completion criteria, these functions also consider additional events
as triggers for updating reception status to caller :
(+) Detection of inactivity period (RX line has not been active for a given period).
(++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
for 1 frame time, after last received byte.
(++) RX inactivity detected by RTO, i.e. line has been in idle state
for a programmable time, after last received byte.
(+) Detection that a specific character has been received.
(#) There are two mode of transfer:
(+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
or till IDLE event occurs. Reception is handled only during function execution.
When function exits, no data reception could occur. HAL status and number of actually received data elements,
are returned by function after finishing transfer.
(+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
These API's return the HAL status.
The end of the data processing will be indicated through the
dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
(#) Blocking mode API:
(+) HAL_UARTEx_ReceiveToIdle()
(#) Non-Blocking mode API with Interrupt:
(+) HAL_UARTEx_ReceiveToIdle_IT()
(#) Non-Blocking mode API with DMA:
(+) HAL_UARTEx_ReceiveToIdle_DMA()
@endverbatim
* @{
*/
@ -361,7 +396,7 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* Init tickstart for timeout managment*/
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Wait until REACK flag is set */
@ -420,6 +455,250 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
return HAL_OK;
}
/**
* @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.
* @note HAL_OK is returned if reception is completed (expected number of data has been received)
* or if reception is stopped after IDLE event (less than the expected number of data has been received)
* In this case, RxLen output parameter indicates number of data available in reception buffer.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
* of uint16_t available through pData.
* @param huart UART handle.
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
* @param RxLen Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event)
* @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout)
{
uint8_t *pdata8bits;
uint16_t *pdata16bits;
uint16_t uhMask;
uint32_t tickstart;
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
__HAL_LOCK(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
huart->RxXferSize = Size;
huart->RxXferCount = Size;
/* Computation of UART mask to apply to RDR register */
UART_MASK_COMPUTATION(huart);
uhMask = huart->Mask;
/* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
pdata8bits = NULL;
pdata16bits = (uint16_t *) pData;
}
else
{
pdata8bits = pData;
pdata16bits = NULL;
}
__HAL_UNLOCK(huart);
/* Initialize output number of received elements */
*RxLen = 0U;
/* as long as data have to be received */
while (huart->RxXferCount > 0U)
{
/* Check if IDLE flag is set */
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
{
/* Clear IDLE flag in ISR */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
/* If Set, but no data ever received, clear flag without exiting loop */
/* If Set, and data has already been received, this means Idle Event is valid : End reception */
if (*RxLen > 0U)
{
huart->RxState = HAL_UART_STATE_READY;
return HAL_OK;
}
}
/* Check if RXNE flag is set */
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
{
if (pdata8bits == NULL)
{
*pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
pdata16bits++;
}
else
{
*pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
pdata8bits++;
}
/* Increment number of received elements */
*RxLen += 1U;
huart->RxXferCount--;
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
huart->RxState = HAL_UART_STATE_READY;
return HAL_TIMEOUT;
}
}
}
/* Set number of received elements in output parameter : RxLen */
*RxLen = huart->RxXferSize - huart->RxXferCount;
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.
* @note Reception is initiated by this function call. Further progress of reception is achieved thanks
* to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
* number of received data elements.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
* of uint16_t available through pData.
* @param huart UART handle.
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef status;
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
__HAL_LOCK(huart);
/* Set Reception type to reception till IDLE Event*/
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
status = UART_Start_Receive_IT(huart, pData, Size);
/* Check Rx process has been successfully started */
if (status == HAL_OK)
{
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
}
else
{
/* In case of errors already pending when reception is started,
Interrupts may have already been raised and lead to reception abortion.
(Overrun error for instance).
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
status = HAL_ERROR;
}
}
return status;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.
* @note Reception is initiated by this function call. Further progress of reception is achieved thanks
* to DMA services, transferring automatically received data elements in user reception buffer and
* calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
* reception phase as ended. In all cases, callback execution will indicate number of received data elements.
* @note When the UART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
* of uint16_t available through pData.
* @param huart UART handle.
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef status;
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
__HAL_LOCK(huart);
/* Set Reception type to reception till IDLE Event*/
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
status = UART_Start_Receive_DMA(huart, pData, Size);
/* Check Rx process has been successfully started */
if (status == HAL_OK)
{
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
}
else
{
/* In case of errors already pending when reception is started,
Interrupts may have already been raised and lead to reception abortion.
(Overrun error for instance).
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
status = HAL_ERROR;
}
}
return status;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/

76
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_usart.c
View File

@ -39,7 +39,8 @@
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
(+++) Configure the priority and enable the NVIC for the transfer
complete interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
(Receiver/Transmitter) in the husart handle Init structure.
@ -521,9 +522,9 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US
}
/**
* @brief Unregister an UART Callback
* UART callaback is redirected to the weak predefined callback
* @param husart uart handle
* @brief Unregister an USART Callback
* USART callaback is redirected to the weak predefined callback
* @param husart usart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
@ -549,40 +550,40 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
switch (CallbackID)
{
case HAL_USART_TX_HALFCOMPLETE_CB_ID :
husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
break;
case HAL_USART_TX_COMPLETE_CB_ID :
husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_USART_RX_HALFCOMPLETE_CB_ID :
husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
break;
case HAL_USART_RX_COMPLETE_CB_ID :
husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_USART_TX_RX_COMPLETE_CB_ID :
husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
break;
case HAL_USART_ERROR_CB_ID :
husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_USART_ABORT_COMPLETE_CB_ID :
husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_USART_MSPINIT_CB_ID :
husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */
husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_USART_MSPDEINIT_CB_ID :
husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */
husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
@ -701,13 +702,16 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
to be evaluated by user : this concerns Frame Error,
Parity Error or Noise Error in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify
error type, and HAL_USART_ErrorCallback() user callback is executed.
Transfer is kept ongoing on USART side.
If user wants to abort it, Abort services should be called by user.
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
Error code is set to allow user to identify error type,
and HAL_USART_ErrorCallback() user callback is executed.
@endverbatim
* @{
@ -715,7 +719,7 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
/**
* @brief Simplex send an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@ -743,7 +747,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX;
/* Init tickstart for timeout managment*/
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
husart->TxXferSize = Size;
@ -812,7 +816,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
/**
* @brief Receive an amount of data in blocking mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@ -841,7 +845,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
/* Init tickstart for timeout managment*/
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
husart->RxXferSize = Size;
@ -916,7 +920,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
/**
* @brief Full-Duplex Send and Receive an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
@ -950,7 +954,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
/* Init tickstart for timeout managment*/
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
husart->RxXferSize = Size;
@ -1065,7 +1069,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
/**
* @brief Send an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@ -1128,7 +1132,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
/**
* @brief Receive an amount of data in interrupt mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@ -1198,7 +1202,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
/**
* @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
@ -1269,7 +1273,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
/**
* @brief Send an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@ -1354,7 +1358,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
* @note When the USART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
* @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@ -1468,7 +1472,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
@ -1659,7 +1663,7 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
/* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
@ -1968,7 +1972,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
if (errorflags == 0U)
{
/* USART in mode Receiver ---------------------------------------------------*/
@ -2022,6 +2026,14 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
husart->ErrorCode |= HAL_USART_ERROR_ORE;
}
/* USART Receiver Timeout interrupt occurred ---------------------------------*/
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF);
husart->ErrorCode |= HAL_USART_ERROR_RTO;
}
/* Call USART Error Call back function if need be --------------------------*/
if (husart->ErrorCode != HAL_USART_ERROR_NONE)
@ -2766,7 +2778,7 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
/* Initialize the USART ErrorCode */
husart->ErrorCode = HAL_USART_ERROR_NONE;
/* Init tickstart for timeout managment*/
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Check if the Transmitter is enabled */

58
stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_wwdg.c
View File

@ -21,6 +21,13 @@
before the counter has reached the refresh window value. This
implies that the counter must be refreshed in a limited window.
(+) Once enabled the WWDG cannot be disabled except by a system reset.
(+) If required by application, an Early Wakeup Interrupt can be triggered
in order to be warned before WWDG expiration. The Early Wakeup Interrupt
(EWI) can be used if specific safety operations or data logging must
be performed before the actual reset is generated. When the downcounter
reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
disabled except by a system reset.
(+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
reset occurs.
(+) The WWDG counter input clock is derived from the APB clock divided
@ -32,12 +39,12 @@
(++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Typical values:
(++) Counter min (T[5;0] = 0x00) @36MHz (PCLK1) with zero prescaler:
(++) Counter min (T[5;0] = 0x00) at 36MHz (PCLK1) with zero prescaler:
max timeout before reset: approximately 113.78µs
(++) Counter max (T[5;0] = 0x3F) @36MHz (PCLK1) with prescaler dividing by 8:
(++) Counter max (T[5;0] = 0x3F) at 36MHz (PCLK1) with prescaler
dividing by 8:
max timeout before reset: approximately 58.25ms
==============================================================================
##### How to use this driver #####
==============================================================================
@ -46,16 +53,16 @@
[..]
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
(+) Set the WWDG prescaler, refresh window and counter value
using HAL_WWDG_Init() function.
(+) Start the WWDG using HAL_WWDG_Start() function.
When the WWDG is enabled the counter value should be configured to
a value greater than 0x40 to prevent generating an immediate reset.
(+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
generated when the counter reaches 0x40, and then start the WWDG using
HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
add his own code by customization of callback HAL_WWDG_WakeupCallback.
Once enabled, EWI interrupt cannot be disabled except by a system reset.
(+) Configure the WWDG prescaler, refresh window value, counter value and early
interrupt status using HAL_WWDG_Init() function. This will automatically
enable WWDG and start its downcounter. Time reference can be taken from
function exit. Care must be taken to provide a counter value
greater than 0x40 to prevent generation of immediate reset.
(+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
triggered by the interrupt service routine, flag will be automatically
cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
can add his own code by customization of callback HAL_WWDG_WakeupCallback.
(+) Then the application program must refresh the WWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_WWDG_Refresh() function. This operation must occur only when
@ -65,28 +72,28 @@
=============================
[..]
The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
the user to configure dynamically the driver callbacks. Use Functions
@ref HAL_WWDG_RegisterCallback() to register a user callback.
HAL_WWDG_RegisterCallback() to register a user callback.
(+) Function @ref HAL_WWDG_RegisterCallback() allows to register following
(+) Function HAL_WWDG_RegisterCallback() allows to register following
callbacks:
(++) EwiCallback : callback for Early WakeUp Interrupt.
(++) MspInitCallback : WWDG MspInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
(+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to
the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback()
(+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to
the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback()
takes as parameters the HAL peripheral handle and the Callback ID.
This function allows to reset following callbacks:
(++) EwiCallback : callback for Early WakeUp Interrupt.
(++) MspInitCallback : WWDG MspInit.
[..]
When calling @ref HAL_WWDG_Init function, callbacks are reset to the
When calling HAL_WWDG_Init function, callbacks are reset to the
corresponding legacy weak (surcharged) functions:
@ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
not been registered before.
[..]
@ -97,7 +104,7 @@
*** WWDG HAL driver macros list ***
===================================
[..]
Below the list of most used macros in WWDG HAL driver.
Below the list of available macros in WWDG HAL driver.
(+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
(+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
(+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
@ -198,7 +205,7 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
#else
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
#endif
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/* Set WWDG Counter */
WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
@ -243,7 +250,8 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
* @param pCallback pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
pWWDG_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@ -304,7 +312,7 @@ HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWD
return status;
}
#endif
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
@ -372,7 +380,7 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
#else
/* Early Wakeup callback */
HAL_WWDG_EarlyWakeupCallback(hwwdg);
#endif
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
}
}
}

7
stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_adc.c
View File

@ -270,6 +270,7 @@
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
@ -1762,6 +1763,12 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
{
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
}
/* ADC group regular continuous mode and discontinuous mode */
/* can not be enabled simultenaeously */
assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
|| (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));

131
stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_fmc.c
View File

@ -203,9 +203,12 @@
* @param Init Pointer to NORSRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
FMC_NORSRAM_InitTypeDef *Init)
{
uint32_t flashaccess;
uint32_t btcr_reg;
uint32_t mask;
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
@ -237,38 +240,40 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini
flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
}
MODIFY_REG(Device->BTCR[Init->NSBank],
(FMC_BCRx_MBKEN |
FMC_BCRx_MUXEN |
FMC_BCRx_MTYP |
FMC_BCRx_MWID |
FMC_BCRx_FACCEN |
FMC_BCRx_BURSTEN |
FMC_BCRx_WAITPOL |
FMC_BCRx_WRAPMOD |
FMC_BCRx_WAITCFG |
FMC_BCRx_WREN |
FMC_BCRx_WAITEN |
FMC_BCRx_EXTMOD |
FMC_BCRx_ASYNCWAIT |
FMC_BCRx_CBURSTRW |
FMC_BCR1_CCLKEN |
0),
(flashaccess |
Init->DataAddressMux |
Init->MemoryType |
Init->MemoryDataWidth |
Init->BurstAccessMode |
Init->WaitSignalPolarity |
Init->WrapMode |
Init->WaitSignalActive |
Init->WriteOperation |
Init->WaitSignal |
Init->ExtendedMode |
Init->AsynchronousWait |
Init->WriteBurst |
Init->ContinuousClock |
0));
btcr_reg = (flashaccess | \
Init->DataAddressMux | \
Init->MemoryType | \
Init->MemoryDataWidth | \
Init->BurstAccessMode | \
Init->WaitSignalPolarity | \
Init->WaitSignalActive | \
Init->WriteOperation | \
Init->WaitSignal | \
Init->ExtendedMode | \
Init->AsynchronousWait | \
Init->WriteBurst);
btcr_reg |= Init->WrapMode;
btcr_reg |= Init->ContinuousClock;
mask = (FMC_BCRx_MBKEN |
FMC_BCRx_MUXEN |
FMC_BCRx_MTYP |
FMC_BCRx_MWID |
FMC_BCRx_FACCEN |
FMC_BCRx_BURSTEN |
FMC_BCRx_WAITPOL |
FMC_BCRx_WAITCFG |
FMC_BCRx_WREN |
FMC_BCRx_WAITEN |
FMC_BCRx_EXTMOD |
FMC_BCRx_ASYNCWAIT |
FMC_BCRx_CBURSTRW);
mask |= FMC_BCRx_WRAPMOD;
mask |= FMC_BCR1_CCLKEN;
MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
/* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
@ -286,7 +291,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini
* @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
@ -322,7 +328,8 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EX
* @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
{
uint32_t tmpr;
@ -339,17 +346,17 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR
/* Set FMC_NORSRAM device timing parameters */
MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) |
(((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) |
(Timing->AccessMode)));
((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) |
(((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) |
(Timing->AccessMode)));
/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
{
tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0F) << FMC_BTRx_CLKDIV_Pos));
tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos));
tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos);
MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);
}
@ -369,7 +376,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR
* @arg FMC_EXTENDED_MODE_ENABLE
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
{
/* Check the parameters */
assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
@ -411,8 +419,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef
*/
/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
* @brief management functions
*
* @brief management functions
*
@verbatim
==============================================================================
##### FMC_NORSRAM Control functions #####
@ -498,8 +506,8 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device
*/
/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
@ -568,7 +576,8 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *
* @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
@ -607,7 +616,8 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC
* @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
@ -754,7 +764,8 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
* @param Timeout Timeout wait value
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
uint32_t Timeout)
{
uint32_t tickstart;
@ -850,9 +861,11 @@ HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTyp
{
/* Check the parameters */
assert_param(IS_FMC_PCCARD_DEVICE(Device));
#if defined(FMC_BANK3)
assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
#endif /* FMC_BANK3 */
/* Set FMC_PCCARD device control parameters */
MODIFY_REG(Device->PCR4,
@ -877,14 +890,17 @@ HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTyp
* @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing)
{
/* Check the parameters */
assert_param(IS_FMC_PCCARD_DEVICE(Device));
#if defined(FMC_BANK3)
assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
#endif /* FMC_BANK3 */
/* Set PCCARD timing parameters */
MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK,
@ -903,14 +919,17 @@ HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
* @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing)
{
/* Check the parameters */
assert_param(IS_FMC_PCCARD_DEVICE(Device));
#if defined(FMC_BANK3)
assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
#endif /* FMC_BANK3 */
/* Set PCCARD timing parameters */
MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK,
@ -929,14 +948,17 @@ HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Devi
* @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing)
{
/* Check the parameters */
assert_param(IS_FMC_PCCARD_DEVICE(Device));
#if defined(FMC_BANK3)
assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
#endif /* FMC_BANK3 */
/* Set FMC_PCCARD device timing parameters */
MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,
@ -989,5 +1011,8 @@ HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

6
stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_rcc.c
View File

@ -622,7 +622,7 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
return i2c_frequency;
}
#if defined(RCC_CFGR_I2SSRC)
#if defined(RCC_CFGR_I2SSRC)
/**
* @brief Return I2Sx clock frequency
* @param I2SxSource This parameter can be one of the following values:
@ -643,7 +643,11 @@ uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
i2s_frequency = RCC_GetSystemClockFreq();
break;
/* If an external I2S clock has to be used, LL_RCC_SetI2SClockSource(LL_RCC_I2S_CLKSOURCE_PIN)
have to be called in the main after calling SystemClock_Config() */
case LL_RCC_I2S_CLKSOURCE_PIN: /*!< External clock selected as I2S clock source */
i2s_frequency = EXTERNAL_CLOCK_VALUE;
break;
default:
i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
break;

19
stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_spi.c
View File

@ -395,7 +395,9 @@ ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
uint32_t i2sodd = 0U;
uint32_t packetlength = 1U;
uint32_t tmp;
#if !defined (SPI_I2S_FULLDUPLEX_SUPPORT)
LL_RCC_ClocksTypeDef rcc_clocks;
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
uint32_t sourceclock;
ErrorStatus status = ERROR;
@ -445,11 +447,24 @@ ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
packetlength = 2U;
}
#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
/* If an external I2S clock has to be used, the specific define should be set
in the project configuration or in the stm32f3xx_ll_rcc.h file */
/* Get the I2S source clock value */
sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S_CLKSOURCE);
#else /* Case for STM32F373xC and STM32F378xx series */
/* I2S Clock source is System clock: Get System Clock frequency */
LL_RCC_GetSystemClocksFreq(&rcc_clocks);
if (SPIx == SPI1)
{
sourceclock = rcc_clocks.PCLK2_Frequency;
}
else /* SPI2 or SPI3 */
{
sourceclock = rcc_clocks.PCLK1_Frequency;
}
/* Get the source clock value: based on System Clock value */
sourceclock = rcc_clocks.SYSCLK_Frequency;
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
/* Compute the Real divider depending on the MCLK output state with a floating point */
if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)

2
stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_tim.c
View File

@ -380,7 +380,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
TIM_InitStruct->RepetitionCounter = 0x00000000U;
}
/**

27
stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_usart.c
View File

@ -71,7 +71,7 @@
|| ((__VALUE__) == LL_USART_DATAWIDTH_9B))
#else
#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
|| ((__VALUE__) == LL_USART_DATAWIDTH_9B))
|| ((__VALUE__) == LL_USART_DATAWIDTH_9B))
#endif /* USART_7BITS_SUPPORT */
#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
@ -183,8 +183,9 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
/**
* @brief Initialize USART registers according to the specified
* parameters in USART_InitStruct.
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
* USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @note As some bits in USART configuration registers can only be written when
* the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
* this function. Otherwise, ERROR result will be returned.
* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
* @param USARTx USART Instance
* @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
@ -237,7 +238,8 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
/*---------------------------- USART CR3 Configuration ---------------------
* Configure USARTx CR3 (Hardware Flow Control) with parameters:
* - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
* - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
* USART_InitStruct->HardwareFlowControl value.
*/
LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
@ -332,13 +334,15 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
/**
* @brief Initialize USART Clock related settings according to the
* specified parameters in the USART_ClockInitStruct.
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
* USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @note As some bits in USART configuration registers can only be written when
* the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
* this function. Otherwise, ERROR result will be returned.
* @param USARTx USART Instance
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
* that contains the Clock configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
* - SUCCESS: USART registers related to Clock settings are initialized according
* to USART_ClockInitStruct content
* - ERROR: Problem occurred during USART Registers initialization
*/
ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
@ -404,9 +408,12 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
{
/* Set LL_USART_ClockInitStruct fields with default values */
USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput =
LL_USART_CLOCK_DISABLE */
USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput =
LL_USART_CLOCK_DISABLE */
USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput =
LL_USART_CLOCK_DISABLE */
}
/**

121
stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_utils.c
View File

@ -225,6 +225,77 @@ void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
SystemCoreClock = HCLKFrequency;
}
/**
* @brief Update number of Flash wait states in line with new frequency and current
voltage range.
* @param Frequency SYSCLK frequency
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Latency has been modified
* - ERROR: Latency cannot be modified
*/
#if defined(FLASH_ACR_LATENCY)
ErrorStatus LL_SetFlashLatency(uint32_t Frequency)
{
uint32_t timeout;
uint32_t getlatency;
uint32_t latency;
ErrorStatus status = SUCCESS;
/* Frequency cannot be equal to 0 */
if (Frequency == 0U)
{
status = ERROR;
}
else
{
if (Frequency > UTILS_LATENCY2_FREQ)
{
/* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
latency = LL_FLASH_LATENCY_2;
}
else
{
if (Frequency > UTILS_LATENCY1_FREQ)
{
/* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
latency = LL_FLASH_LATENCY_1;
}
else
{
/* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
latency = LL_FLASH_LATENCY_0;
}
}
if (status != ERROR)
{
LL_FLASH_SetLatency(latency);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
timeout = 2;
do
{
/* Wait for Flash latency to be updated */
getlatency = LL_FLASH_GetLatency();
timeout--;
} while ((getlatency != latency) && (timeout > 0));
if(getlatency != latency)
{
status = ERROR;
}
else
{
status = SUCCESS;
}
}
}
return status;
}
#endif /* FLASH_ACR_LATENCY */
/**
* @brief This function configures system clock with HSI as clock source of the PLL
* @note The application need to ensure that PLL is disabled.
@ -374,56 +445,6 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa
return status;
}
/**
* @brief Update number of Flash wait states in line with new frequency and current
voltage range.
* @param Frequency SYSCLK frequency
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Latency has been modified
* - ERROR: Latency cannot be modified
*/
#if defined(FLASH_ACR_LATENCY)
ErrorStatus LL_SetFlashLatency(uint32_t Frequency)
{
ErrorStatus status = SUCCESS;
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
/* Frequency cannot be equal to 0 */
if (Frequency == 0U)
{
status = ERROR;
}
else
{
if (Frequency > UTILS_LATENCY2_FREQ)
{
/* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
latency = LL_FLASH_LATENCY_2;
}
else
{
if (Frequency > UTILS_LATENCY1_FREQ)
{
/* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
latency = LL_FLASH_LATENCY_1;
}
/* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
}
LL_FLASH_SetLatency(latency);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (LL_FLASH_GetLatency() != latency)
{
status = ERROR;
}
}
return status;
}
#endif /* FLASH_ACR_LATENCY */
/**
* @}
*/

4
stm32cube/stm32f3xx/soc/stm32f3xx.h
View File

@ -103,11 +103,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.4
* @brief CMSIS Device version number V2.3.5
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x05) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\

37
stm32cube/stm32f3xx/soc/system_stm32f3xx.c
View File

@ -94,11 +94,31 @@
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* Note: Following vector table addresses must be defined in line with linker
configuration. */
/*!< Uncomment the following line if you need to relocate the vector table
anywhere in Flash or Sram, else the vector table is kept at the automatic
remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */
#if defined(USER_VECT_TAB_ADDRESS)
/*!< Uncomment the following line if you need to relocate your vector Table
in Sram else user remap will be done in Flash. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
/**
* @}
*/
@ -155,11 +175,10 @@ void SystemInit(void)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
/**