zephyr
/
hal_stm32
mirror of https://github.com/zephyrproject-rtos/hal_stm32.git
1
0
Fork 0
Code Issues Releases Wiki Activity

stm32cube: update stm32f7 to version V1.16.0 

Update Cube version for STM32F7xx series
   on https://github.com/STMicroelectronics
   from version v1.15.0
   to version v1.16.0

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2020-03-04 16:30:40 +01:00 committed by Kumar Gala
parent 5687b77796
commit 4fa9c62e00
107 changed files with 24416 additions and 11325 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
stm32cube/stm32f7xx/CMakeLists.txt
View File

@ -1,4 +1,5 @@
# Copyright (c) 2017 Erwin Rol <erwin@erwinrol.com>
# Copyright (c) 2020 STMicroelectronics
#
# SPDX-License-Identifier: Apache-2.0
@ -24,6 +25,7 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DMA2D drivers/src/stm32f7xx_ha
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DMA_EX drivers/src/stm32f7xx_hal_dma_ex.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DSI drivers/src/stm32f7xx_hal_dsi.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_ETH drivers/src/stm32f7xx_hal_eth.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_EXTI drivers/src/stm32f7xx_hal_exti.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_FLASH drivers/src/stm32f7xx_hal_flash.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_FLASH_EX drivers/src/stm32f7xx_hal_flash_ex.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_GPIO drivers/src/stm32f7xx_hal_gpio.c)
@ -48,6 +50,7 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PCD_EX drivers/src/stm32f7xx_h
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PWR drivers/src/stm32f7xx_hal_pwr.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PWR_EX drivers/src/stm32f7xx_hal_pwr_ex.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_QSPI drivers/src/stm32f7xx_hal_qspi.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RCC drivers/src/stm32f7xx_hal_rcc.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RCC_EX drivers/src/stm32f7xx_hal_rcc_ex.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RNG drivers/src/stm32f7xx_hal_rng.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RTC drivers/src/stm32f7xx_hal_rtc.c)
@ -61,10 +64,12 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMARTCARD_EX drivers/src/stm32
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMBUS drivers/src/stm32f7xx_hal_smbus.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SPDIFRX drivers/src/stm32f7xx_hal_spdifrx.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SPI drivers/src/stm32f7xx_hal_spi.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SPI_EX drivers/src/stm32f7xx_hal_spi_ex.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SRAM drivers/src/stm32f7xx_hal_sram.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_TIM drivers/src/stm32f7xx_hal_tim.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_TIM_EX drivers/src/stm32f7xx_hal_tim_ex.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_UART drivers/src/stm32f7xx_hal_uart.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_UART_EX drivers/src/stm32f7xx_hal_uart_ex.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_USART drivers/src/stm32f7xx_hal_usart.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_WWDG drivers/src/stm32f7xx_hal_wwdg.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_ADC drivers/src/stm32f7xx_ll_adc.c)

17
stm32cube/stm32f7xx/README
View File

@ -35,6 +35,7 @@ License Link:
https://opensource.org/licenses/BSD-3-Clause
Patch List:
See release_note.html from STM32Cube
*Fix LL_EXTI_LINE_18 and LL_EXTI_LINE_20 declarations
LL_EXTI_LINE_18 and LL_EXTI_LINE_20 are declared in stm32f7xx_hal_pcd.h
@ -43,19 +44,3 @@ Patch List:
Impacted files:
drivers/include/stm32f7xx_ll_exti.h
ST Bug tracker ID: 55274
*Use of (__packed uint32_t *) produces warning
Using GNU 8.2.0, (__packed uint32_t *) generates warning.
Replace with CMSIS macros __UNALIGNED_UINT32_READ and
__UNALIGNED_UINT32_WRITE.
Impacted files:
drivers/include/stm32f7xx_ll_usb.c
ST Bug tracker ID: 61327
*Fix warnings for extraneous parentheses
Using clang 7.0.1, if ((htim->State == HAL_TIM_STATE_BUSY))
generates warnings. Remove the extra parentheses
Impacted files:
drivers/src/stm32f7xx_hal_tim.c
drivers/src/stm32f7xx_hal_tim_ex.c
ST Bug tracker ID: 63618

369
stm32cube/stm32f7xx/drivers/include/Legacy/stm32_hal_legacy.h
View File

@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@ -236,6 +236,16 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
#if defined(STM32G4) || defined(STM32H7)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
/**
* @}
*/
@ -296,8 +306,17 @@
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
#endif
#endif /* STM32L4 */
#if defined(STM32G0)
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
#endif
#if defined(STM32H7)
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
@ -355,6 +374,9 @@
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */
/**
@ -450,7 +472,9 @@
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
#endif
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
#endif /* STM32H7 */
/**
* @}
@ -486,6 +510,13 @@
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
#if defined(STM32G4)
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
/**
* @}
*/
@ -494,7 +525,7 @@
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{
*/
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
@ -547,18 +578,25 @@
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
#endif
#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7)
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
#if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@ -599,6 +637,185 @@
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
#if defined(STM32G4)
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
#endif /* STM32G4 */
#if defined(STM32H7)
#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
#endif /* STM32H7 */
#if defined(STM32F3)
/** @brief Constants defining available sources associated to external events.
*/
#define HRTIM_EVENTSRC_1 (0x00000000U)
#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
/** @brief Constants defining the events that can be selected to configure the
* set/reset crossbar of a timer output
*/
#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
/** @brief Constants defining the event filtering applied to external events
* by a timer
*/
#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
/** @brief Constants defining the DLL calibration periods (in micro seconds)
*/
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
#endif /* STM32F3 */
/**
* @}
*/
@ -738,6 +955,12 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
/**
* @}
*/
@ -753,7 +976,6 @@
#define I2S_FLAG_TXE I2S_FLAG_TXP
#define I2S_FLAG_RXNE I2S_FLAG_RXP
#define I2S_FLAG_FRE I2S_FLAG_TIFRE
#endif
#if defined(STM32F7)
@ -824,6 +1046,16 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
#if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
#endif /* STM32H7 */
/**
* @}
*/
@ -971,6 +1203,24 @@
#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
#endif
#if defined(STM32H7)
#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
#endif
/**
* @}
*/
@ -1199,6 +1449,30 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
#endif /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@ -1221,6 +1495,13 @@
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
/**
* @}
*/
@ -1250,16 +1531,18 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7)
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 */
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@ -1278,6 +1561,13 @@
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{
*/
#if defined(STM32G0)
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
#endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
@ -1350,14 +1640,14 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0)
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
/**
* @}
*/
@ -2476,12 +2766,28 @@
#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
#if defined(STM32H7)
#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
#endif
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
@ -2814,6 +3120,15 @@
#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
#if defined(STM32L1)
#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
#endif /* STM32L1 */
#if defined(STM32F4)
#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
@ -2930,7 +3245,7 @@
#if defined(STM32L4)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#elif defined(STM32WB) || defined(STM32G0)
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@ -3058,7 +3373,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@ -3174,14 +3489,14 @@
#define SDIO_IRQHandler SDMMC1_IRQHandler
#endif
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
#if defined(STM32H7)
#if defined(STM32H7) || defined(STM32L5)
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
@ -3421,18 +3736,28 @@
/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
* @{
*/
#if defined (STM32H7) || defined (STM32F3)
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
#endif
/**
* @}
*/
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7)
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
#endif /* STM32L4 || STM32F4 || STM32F7 */
/**
* @}
*/
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{
*/

28
stm32cube/stm32f7xx/drivers/include/Legacy/stm32f7xx_hal_can_legacy.h
View File

@ -6,13 +6,29 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/

12
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_adc.h
View File

@ -18,8 +18,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_ADC_H
#define __STM32F7xx_ADC_H
#ifndef STM32F7xx_ADC_H
#define STM32F7xx_ADC_H
#ifdef __cplusplus
extern "C" {
@ -416,8 +416,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
#define ADC_INTERNAL_NONE 0x80000000U
#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)(ADC_CHANNEL_18 | 0x10000000U))
/**
* @}
*/
@ -732,6 +734,10 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
*/
#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \
((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
((CHANNEL) == ADC_INTERNAL_NONE))
#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
@ -947,7 +953,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
}
#endif
#endif /*__STM32F7xx_ADC_H */
#endif /* STM32F7xx_ADC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

10
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_adc_ex.h
View File

@ -18,8 +18,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_ADC_EX_H
#define __STM32F7xx_ADC_EX_H
#ifndef STM32F7xx_ADC_EX_H
#define STM32F7xx_ADC_EX_H
#ifdef __cplusplus
extern "C" {
@ -210,7 +210,7 @@ typedef struct
/** @defgroup ADCEx_channels ADC Specific Channels
* @{
*/
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | 0x10000000U)
/**
* @}
*/
@ -274,8 +274,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
/** @defgroup ADCEx_Private_Macros ADC Private Macros
* @{
*/
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \
((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))
#define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \
((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
@ -352,7 +350,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
}
#endif
#endif /*__STM32F7xx_ADC_EX_H */
#endif /* STM32F7xx_ADC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

132
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cryp.h
View File

@ -22,7 +22,7 @@
#define __STM32F7xx_HAL_CRYP_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
@ -53,20 +53,23 @@ typedef struct
This parameter can be a value of @ref CRYP_Data_Type */
uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
uint32_t* pKey; /*!< The key used for encryption/decryption */
uint32_t* pInitVect; /*!< The initialization vector used also as initialization
uint32_t *pKey; /*!< The key used for encryption/decryption */
uint32_t *pInitVect; /*!< The initialization vector used also as initialization
counter in CTR mode */
uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
AES Algorithm ECB/CBC/CTR/GCM or CCM
This parameter can be a value of @ref CRYP_Algorithm_Mode */
uint32_t* Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
GCM : also known as Additional Authentication Data
CCM : named B1 composed of the associated data length and Associated Data. */
uint32_t HeaderSize; /*!< The size of header buffer in word */
uint32_t* B0; /*!< B0 is first authentication block used only in AES CCM mode */
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
Vector only once and to skip configuration for consecutive processings.
This parameter can be a value of @ref CRYP_Configuration_Skip */
}CRYP_ConfigTypeDef;
} CRYP_ConfigTypeDef;
/**
@ -78,7 +81,7 @@ typedef enum
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
HAL_CRYP_STATE_BUSY = 0x02U /*!< CRYP BUSY, internal processing is ongoing */
}HAL_CRYP_STATETypeDef;
} HAL_CRYP_STATETypeDef;
/**
@ -88,50 +91,57 @@ typedef enum
typedef struct __CRYP_HandleTypeDef
{
#if defined (CRYP)
CRYP_TypeDef *Instance; /*!< CRYP registers base address */
CRYP_TypeDef *Instance; /*!< CRYP registers base address */
#else /* AES*/
AES_TypeDef *Instance; /*!< AES Register base address */
AES_TypeDef *Instance; /*!< AES Register base address */
#endif /* End AES or CRYP */
CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption.
FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption.
This parameter can be a value of ENABLE/DISABLE */
uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
__IO uint16_t CrypHeaderCount; /*!< Counter of header data */
__IO uint16_t CrypHeaderCount; /*!< Counter of header data */
__IO uint16_t CrypInCount; /*!< Counter of input data */
__IO uint16_t CrypInCount; /*!< Counter of input data */
__IO uint16_t CrypOutCount; /*!< Counter of output data */
__IO uint16_t CrypOutCount; /*!< Counter of output data */
uint16_t Size; /*!< length of input data in word */
uint16_t Size; /*!< length of input data in word */
uint32_t Phase; /*!< CRYP peripheral phase */
uint32_t Phase; /*!< CRYP peripheral phase */
DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
HAL_LockTypeDef Lock; /*!< CRYP locking object */
HAL_LockTypeDef Lock; /*!< CRYP locking object */
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
configuration can be skipped */
uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
for a single signature computation after several
messages processing */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
void (*InCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Input FIFO transfer completed callback */
void (*OutCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Output FIFO transfer completed callback */
void (*ErrorCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Error callback */
void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */
void (* MspInitCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp Init callback */
void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp DeInit callback */
void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */
void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
}CRYP_HandleTypeDef;
} CRYP_HandleTypeDef;
/**
@ -152,7 +162,7 @@ typedef enum
HAL_CRYP_MSPINIT_CB_ID = 0x04U, /*!< CRYP MspInit callback ID */
HAL_CRYP_MSPDEINIT_CB_ID = 0x05U /*!< CRYP MspDeInit callback ID */
}HAL_CRYP_CallbackIDTypeDef;
} HAL_CRYP_CallbackIDTypeDef;
/**
* @}
*/
@ -162,7 +172,7 @@ typedef enum
* @{
*/
typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< pointer to a common CRYP callback function */
typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */
/**
* @}
@ -309,6 +319,17 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
#define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */
#endif /* End AES or CRYP */
/**
* @}
*/
/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
* @{
*/
#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
/**
* @}
*/
@ -366,12 +387,12 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
* @arg CRYP_FLAG_OFNE: Output FIFO is not empty
* @arg CRYP_FLAG_OFFU: Output FIFO is full
* @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
* @retval The state of __FLAG__ (TRUE or FALSE).
* @retval The state of __FLAG__ (TRUE or FALSE).
*/
#define CRYP_FLAG_MASK 0x0000001FU
#if defined(CRYP)
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
#else /* AES*/
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
#endif /* End AES or CRYP */
@ -398,7 +419,8 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
* @retval State of interruption (TRUE or FALSE).
*/
#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
& (__INTERRUPT__)) == (__INTERRUPT__))
#endif /* AES */
@ -415,7 +437,8 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
*/
#if defined(CRYP)
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR\
& (__INTERRUPT__)) == (__INTERRUPT__))
#else /* AES*/
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
#endif /* End AES or CRYP */
@ -473,10 +496,11 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
pCRYP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/**
@ -488,8 +512,10 @@ HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRY
*/
/* encryption/decryption ***********************************/
HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
@ -529,23 +555,23 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
*/
#if defined(CRYP)
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \
((ALGORITHM) == CRYP_DES_CBC) || \
((ALGORITHM) == CRYP_TDES_ECB) || \
((ALGORITHM) == CRYP_TDES_CBC) || \
((ALGORITHM) == CRYP_AES_ECB) || \
((ALGORITHM) == CRYP_AES_CBC) || \
((ALGORITHM) == CRYP_AES_CTR) || \
((ALGORITHM) == CRYP_AES_GCM) || \
((ALGORITHM) == CRYP_AES_CCM))
((ALGORITHM) == CRYP_DES_CBC) || \
((ALGORITHM) == CRYP_TDES_ECB) || \
((ALGORITHM) == CRYP_TDES_CBC) || \
((ALGORITHM) == CRYP_AES_ECB) || \
((ALGORITHM) == CRYP_AES_CBC) || \
((ALGORITHM) == CRYP_AES_CTR) || \
((ALGORITHM) == CRYP_AES_GCM) || \
((ALGORITHM) == CRYP_AES_CCM))
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
((KEYSIZE) == CRYP_KEYSIZE_192B) || \
((KEYSIZE) == CRYP_KEYSIZE_256B))
#else /* AES*/
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \
((ALGORITHM) == CRYP_AES_CBC) || \
((ALGORITHM) == CRYP_AES_CTR) || \
((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
((ALGORITHM) == CRYP_AES_CCM))
((ALGORITHM) == CRYP_AES_CBC) || \
((ALGORITHM) == CRYP_AES_CTR) || \
((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
((ALGORITHM) == CRYP_AES_CCM))
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
@ -557,6 +583,8 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
((DATATYPE) == CRYP_DATATYPE_8B) || \
((DATATYPE) == CRYP_DATATYPE_1B))
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
/**
* @}
*/

6
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cryp_ex.h
View File

@ -22,7 +22,7 @@
#define __STM32F7xx_HAL_CRYP_EX_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@ -84,9 +84,9 @@
* @{
*/
/**
/**
* @}
*/
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions

71
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dcmi.h
View File

@ -18,11 +18,11 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_DCMI_H
#define __STM32F7xx_HAL_DCMI_H
#ifndef STM32F7xx_HAL_DCMI_H
#define STM32F7xx_HAL_DCMI_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@ -54,7 +54,7 @@ typedef enum
HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */
HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */
HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */
}HAL_DCMI_StateTypeDef;
} HAL_DCMI_StateTypeDef;
/**
* @brief DCMIEx Embedded Synchronisation CODE Init structure definition
@ -65,8 +65,18 @@ typedef struct
uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
}DCMI_CodesInitTypeDef;
} DCMI_CodesInitTypeDef;
/**
* @brief DCMI Embedded Synchronisation CODE Init structure definition
*/
typedef struct
{
uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
uint8_t LineStartUnmask; /*!< Specifies the line start delimiter unmask. */
uint8_t LineEndUnmask; /*!< Specifies the line end delimiter unmask. */
uint8_t FrameEndUnmask; /*!< Specifies the frame end delimiter unmask. */
} DCMI_SyncUnmaskTypeDef;
/**
* @brief DCMI Init structure definition
*/
@ -96,6 +106,7 @@ typedef struct
uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
This parameter can be a value of @ref DCMI_MODE_JPEG */
#ifdef DCMI_CR_BSM
uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface
This parameter can be a value of @ref DCMI_Byte_Select_Mode */
@ -107,7 +118,8 @@ typedef struct
uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd
This parameter can be a value of @ref DCMI_Line_Select_Start */
}DCMI_InitTypeDef;
#endif
} DCMI_InitTypeDef;
/**
* @brief DCMI handle Structure definition
@ -134,14 +146,14 @@ typedef struct __DCMI_HandleTypeDef
__IO uint32_t ErrorCode; /*!< DCMI Error code */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
void (* FrameEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */
void (* VsyncEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */
void (* LineEventCallback ) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */
void (* ErrorCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */
void (* MspInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */
void (* MspDeInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */
void (* FrameEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */
void (* VsyncEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */
void (* LineEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */
void (* ErrorCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */
void (* MspInitCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */
void (* MspDeInitCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}DCMI_HandleTypeDef;
} DCMI_HandleTypeDef;
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
typedef enum
@ -153,7 +165,7 @@ typedef enum
HAL_DCMI_MSPINIT_CB_ID = 0x04U, /*!< DCMI MspInit callback ID */
HAL_DCMI_MSPDEINIT_CB_ID = 0x05U /*!< DCMI MspDeInit callback ID */
}HAL_DCMI_CallbackIDTypeDef;
} HAL_DCMI_CallbackIDTypeDef;
typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
@ -500,8 +512,8 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
void HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
@ -516,10 +528,10 @@ HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCM
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
@ -536,6 +548,7 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
/**
* @}
@ -572,31 +585,31 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
*/
#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
((MODE) == DCMI_MODE_SNAPSHOT))
#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
((MODE) == DCMI_SYNCHRO_EMBEDDED))
#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
((POLARITY) == DCMI_PCKPOLARITY_RISING))
#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
((POLARITY) == DCMI_VSPOLARITY_HIGH))
#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
((POLARITY) == DCMI_HSPOLARITY_HIGH))
#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
((JPEG_MODE) == DCMI_JPEG_ENABLE))
#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
((DATA) == DCMI_EXTEND_DATA_10B) || \
((DATA) == DCMI_EXTEND_DATA_12B) || \
((DATA) == DCMI_EXTEND_DATA_14B))
#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
@ -640,6 +653,6 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
}
#endif
#endif /* __STM32F7xx_HAL_DCMI_H */
#endif /* STM32F7xx_HAL_DCMI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

161
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_exti.h
View File

@ -18,8 +18,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_EXTI_H
#define __STM32F7xx_HAL_EXTI_H
#ifndef STM32F7xx_HAL_EXTI_H
#define STM32F7xx_HAL_EXTI_H
#ifdef __cplusplus
extern "C" {
@ -38,14 +38,13 @@ extern "C" {
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Types EXTI Exported Types
* @{
*/
typedef enum
{
HAL_EXTI_COMMON_CB_ID = 0x00U,
HAL_EXTI_RISING_CB_ID = 0x01U,
HAL_EXTI_FALLING_CB_ID = 0x02U,
HAL_EXTI_COMMON_CB_ID = 0x00U
} EXTI_CallbackIDTypeDef;
/**
@ -68,6 +67,9 @@ typedef struct
This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
can be a value of @ref EXTI_Trigger */
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
This parameter is only possible for line 0 to 15. It
can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef;
/**
@ -82,48 +84,36 @@ typedef struct
/** @defgroup EXTI_Line EXTI Line
* @{
*/
#define EXTI_LINE_0 EXTI_IMR_IM0 /*!< External interrupt line 0 */
#define EXTI_LINE_1 EXTI_IMR_IM1 /*!< External interrupt line 1 */
#define EXTI_LINE_2 EXTI_IMR_IM2 /*!< External interrupt line 2 */
#define EXTI_LINE_3 EXTI_IMR_IM3 /*!< External interrupt line 3 */
#define EXTI_LINE_4 EXTI_IMR_IM4 /*!< External interrupt line 4 */
#define EXTI_LINE_5 EXTI_IMR_IM5 /*!< External interrupt line 5 */
#define EXTI_LINE_6 EXTI_IMR_IM6 /*!< External interrupt line 6 */
#define EXTI_LINE_7 EXTI_IMR_IM7 /*!< External interrupt line 7 */
#define EXTI_LINE_8 EXTI_IMR_IM8 /*!< External interrupt line 8 */
#define EXTI_LINE_9 EXTI_IMR_IM9 /*!< External interrupt line 9 */
#define EXTI_LINE_10 EXTI_IMR_IM10 /*!< External interrupt line 10 */
#define EXTI_LINE_11 EXTI_IMR_IM11 /*!< External interrupt line 11 */
#define EXTI_LINE_12 EXTI_IMR_IM12 /*!< External interrupt line 12 */
#define EXTI_LINE_13 EXTI_IMR_IM13 /*!< External interrupt line 13 */
#define EXTI_LINE_14 EXTI_IMR_IM14 /*!< External interrupt line 14 */
#define EXTI_LINE_15 EXTI_IMR_IM15 /*!< External interrupt line 15 */
#if defined(EXTI_IMR_IM16)
#define EXTI_LINE_16 EXTI_IMR_IM16 /*!< External interrupt line 16 Connected to the PVD Output */
#endif /* EXTI_IMR_IM16 */
#if defined(EXTI_IMR_IM17)
#define EXTI_LINE_17 EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
#endif /* EXTI_IMR_IM17 */
#if defined(EXTI_IMR_IM18)
#define EXTI_LINE_18 EXTI_IMR_IM18 /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
#endif /* EXTI_IMR_IM18 */
#if defined(EXTI_IMR_IM19)
#define EXTI_LINE_19 EXTI_IMR_IM19 /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
#endif /* EXTI_IMR_IM19 */
#if defined(EXTI_IMR_IM20)
#define EXTI_LINE_20 EXTI_IMR_IM20 /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
#endif /* EXTI_IMR_IM20 */
#if defined(EXTI_IMR_IM21)
#define EXTI_LINE_21 EXTI_IMR_IM21 /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
#endif /* EXTI_IMR_IM21 */
#if defined(EXTI_IMR_IM22)
#define EXTI_LINE_22 EXTI_IMR_IM22 /*!< External interrupt line 22 Connected to the RTC Wakeup event */
#endif /* EXTI_IMR_IM22 */
#if defined(EXTI_IMR_IM23)
#define EXTI_LINE_23 EXTI_IMR_IM23 /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */
#endif /* EXTI_IMR_IM23 */
#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
#if defined(ETH)
#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
#else
#define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */
#endif /* ETH */
#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */
#if defined(EXTI_IMR_IM24)
#define EXTI_LINE_24 EXTI_IMR_IM24 /*!< External interrupt line 24 Connected to the MDIO Slave global Interrupt Wakeup event */
#define EXTI_LINE_24 (EXTI_CONFIG | 0x18u) /*!< External interrupt line 24 Connected to the MDIO Slave global Interrupt Wakeup event */
#endif /* EXTI_IMR_IM24 */
/**
* @}
@ -142,6 +132,7 @@ typedef struct
/** @defgroup EXTI_Trigger EXTI Trigger
* @{
*/
#define EXTI_TRIGGER_NONE 0x00000000u
#define EXTI_TRIGGER_RISING 0x00000001u
#define EXTI_TRIGGER_FALLING 0x00000002u
@ -150,6 +141,24 @@ typedef struct
* @}
*/
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
* @brief
* @{
*/
#define EXTI_GPIOA 0x00000000u
#define EXTI_GPIOB 0x00000001u
#define EXTI_GPIOC 0x00000002u
#define EXTI_GPIOD 0x00000003u
#define EXTI_GPIOE 0x00000004u
#define EXTI_GPIOF 0x00000005u
#define EXTI_GPIOG 0x00000006u
#define EXTI_GPIOH 0x00000007u
#define EXTI_GPIOI 0x00000008u
#define EXTI_GPIOJ 0x00000009u
#if defined (GPIOK)
#define EXTI_GPIOK 0x0000000Au
#endif /* GPIOK */
/**
* @}
*/
@ -167,6 +176,20 @@ typedef struct
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
/**
* @brief EXTI Line property definition
*/
#define EXTI_PROPERTY_SHIFT 24u
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
/**
* @brief EXTI bit usage
*/
#define EXTI_PIN_MASK 0x0000001Fu
/**
* @brief EXTI Mask for interrupt & event mode
*/
@ -175,12 +198,17 @@ typedef struct
/**
* @brief EXTI Mask for trigger possibilities
*/
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING | EXTI_TRIGGER_RISING_FALLING)
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @brief EXTI Line number
*/
#if defined(EXTI_IMR_IM24)
#define EXTI_LINE_NB 25u
#else
#define EXTI_LINE_NB 24u
#endif /* EXTI_IMR_IM24 */
/**
* @}
@ -190,16 +218,47 @@ typedef struct
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~EXTI_IMR_IM) == 0x00U) && (__LINE__))
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & ~EXTI_MODE_MASK) == 0x00U))
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \
((__LINE__) == EXTI_TRIGGER_RISING) || \
((__LINE__) == EXTI_TRIGGER_RISING_FALLING))
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
#if defined (GPIOK)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH) || \
((__PORT__) == EXTI_GPIOI) || \
((__PORT__) == EXTI_GPIOJ) || \
((__PORT__) == EXTI_GPIOK))
#else
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH) || \
((__PORT__) == EXTI_GPIOI) || \
((__PORT__) == EXTI_GPIOJ))
#endif /* GPIOK */
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
/**
* @}
@ -255,6 +314,6 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
}
#endif
#endif /* __STM32F7xx_HAL_EXTI_H */
#endif /* STM32F7xx_HAL_EXTI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

2
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_gpio.h
View File

@ -262,7 +262,7 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00))
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
((MODE) == GPIO_MODE_OUTPUT_OD) ||\

60
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_hash.h
View File

@ -152,6 +152,8 @@ typedef struct
__IO uint32_t ErrorCode; /*!< HASH Error code */
__IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */
@ -226,11 +228,11 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/** @defgroup HASH_flags_definition HASH flags definitions
* @{
*/
#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the Peripheral */
#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
/**
* @}
@ -276,7 +278,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
*/
/** @brief Check whether or not the specified HASH flag is set.
* @param __FLAG__: specifies the flag to check.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
* @arg @ref HASH_FLAG_DCIS Digest calculation complete.
@ -291,7 +293,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/** @brief Clear the specified HASH flag.
* @param __FLAG__: specifies the flag to clear.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
* @arg @ref HASH_FLAG_DCIS Digest calculation complete
@ -301,7 +303,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/** @brief Enable the specified HASH interrupt.
* @param __INTERRUPT__: specifies the HASH interrupt source to enable.
* @param __INTERRUPT__ specifies the HASH interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
* @arg @ref HASH_IT_DCI Digest calculation complete
@ -310,7 +312,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
#define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
/** @brief Disable the specified HASH interrupt.
* @param __INTERRUPT__: specifies the HASH interrupt source to disable.
* @param __INTERRUPT__ specifies the HASH interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
* @arg @ref HASH_IT_DCI Digest calculation complete
@ -319,7 +321,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
#define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
/** @brief Reset HASH handle state.
* @param __HANDLE__: HASH handle.
* @param __HANDLE__ HASH handle.
* @retval None
*/
@ -335,7 +337,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/** @brief Reset HASH handle status.
* @param __HANDLE__: HASH handle.
* @param __HANDLE__ HASH handle.
* @retval None
*/
#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
@ -362,7 +364,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/**
* @brief Set the number of valid bits in the last word written in data register DIN.
* @param __SIZE__: size in bytes of last data written in Data register.
* @param __SIZE__ size in bytes of last data written in Data register.
* @retval None
*/
#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
@ -397,7 +399,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/**
* @brief Ensure that HASH input data type is valid.
* @param __DATATYPE__: HASH input data type.
* @param __DATATYPE__ HASH input data type.
* @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
*/
#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
@ -405,21 +407,11 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
((__DATATYPE__) == HASH_DATATYPE_8B) || \
((__DATATYPE__) == HASH_DATATYPE_1B))
/**
* @brief Ensure that input data buffer size is valid for multi-buffer HASH
* processing in polling mode.
* @note This check is valid only for multi-buffer HASH processing in polling mode.
* @param __SIZE__: input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4U) == 0U)
/**
* @brief Ensure that input data buffer size is valid for multi-buffer HASH
* processing in DMA mode.
* @note This check is valid only for multi-buffer HASH processing in DMA mode.
* @param __SIZE__: input data buffer size.
* @param __SIZE__ input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U))
@ -428,21 +420,21 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
* @brief Ensure that input data buffer size is valid for multi-buffer HMAC
* processing in DMA mode.
* @note This check is valid only for multi-buffer HMAC processing in DMA mode.
* @param __HANDLE__: HASH handle.
* @param __SIZE__: input data buffer size.
* @param __HANDLE__ HASH handle.
* @param __SIZE__ input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
/**
* @brief Ensure that handle phase is set to HASH processing.
* @param __HANDLE__: HASH handle.
* @param __HANDLE__ HASH handle.
* @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
*/
#define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
/**
* @brief Ensure that handle phase is set to HMAC processing.
* @param __HANDLE__: HASH handle.
* @param __HANDLE__ HASH handle.
* @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
*/
#define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
@ -492,8 +484,11 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS
/* HASH processing using polling *********************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
/**
* @}
@ -505,7 +500,11 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p
/* HASH processing using IT **************************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
/**
* @}
@ -591,6 +590,7 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
/* Private functions */
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);

10
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_hash_ex.h
View File

@ -52,9 +52,11 @@
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
/**
* @}
@ -65,7 +67,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
/**
* @}

78
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_hcd.h
View File

@ -108,9 +108,10 @@ typedef struct
/** @defgroup HCD_Speed HCD Speed
* @{
*/
#define HCD_SPEED_HIGH 0U
#define HCD_SPEED_LOW 2U
#define HCD_SPEED_FULL 3U
#define HCD_SPEED_HIGH USBH_HS_SPEED
#define HCD_SPEED_FULL USBH_FSLS_SPEED
#define HCD_SPEED_LOW USBH_FSLS_SPEED
/**
* @}
*/
@ -169,19 +170,15 @@ typedef struct
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
uint8_t ch_num,
uint8_t epnum,
uint8_t dev_address,
uint8_t speed,
uint8_t ep_type,
uint16_t mps);
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
uint8_t epnum, uint8_t dev_address,
uint8_t speed, uint8_t ep_type, uint16_t mps);
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
@ -190,14 +187,14 @@ void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
*/
typedef enum
{
HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
} HAL_HCD_CallbackIDTypeDef;
/**
@ -231,25 +228,20 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef
/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
uint8_t ch_num,
uint8_t direction,
uint8_t ep_type,
uint8_t token,
uint8_t *pbuff,
uint16_t length,
uint8_t do_ping);
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
uint8_t direction, uint8_t ep_type,
uint8_t token, uint8_t *pbuff,
uint16_t length, uint8_t do_ping);
/* Non-Blocking mode: Interrupt */
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
uint8_t chnum,
HCD_URBStateTypeDef urb_state);
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
HCD_URBStateTypeDef urb_state);
/**
* @}
*/
@ -258,9 +250,9 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
@ -271,8 +263,8 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/**

3
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_i2c_ex.h
View File

@ -167,6 +167,9 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */
/**
* @}
*/

32
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_irda.h
View File

@ -434,8 +434,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
*/
/**
* @}
*/
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
@ -465,10 +465,10 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @retval None
*/
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
} while(0U)
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
} while(0U)
/** @brief Clear the specified IRDA pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
@ -582,7 +582,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
* @param __HANDLE__ specifies the IRDA Handle.
@ -597,8 +598,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the IRDA Handle.
@ -636,7 +637,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
&= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable UART/USART associated to IRDA Handle.
* @param __HANDLE__ specifies the IRDA Handle.
@ -683,7 +685,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @param __MODE__ IRDA communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
& (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
/** @brief Ensure that IRDA power mode is valid.
* @param __MODE__ IRDA power mode.
@ -735,8 +738,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
/**
* @}
*/
* @}
*/
/* Include IRDA HAL Extended module */
#include "stm32f7xx_hal_irda_ex.h"
@ -758,7 +761,8 @@ void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
pIRDA_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */

115
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_irda_ex.h
View File

@ -32,7 +32,8 @@ extern "C" {
* @{
*/
/** @addtogroup IRDAEx
/** @defgroup IRDAEx IRDAEx
* @brief IRDA Extended HAL module driver
* @{
*/
@ -73,8 +74,8 @@ extern "C" {
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
break; \
@ -90,12 +91,12 @@ extern "C" {
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@ -111,12 +112,12 @@ extern "C" {
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@ -132,12 +133,12 @@ extern "C" {
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@ -153,12 +154,12 @@ extern "C" {
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if ((__HANDLE__)->Instance == UART5) \
{ \
switch(__HAL_RCC_GET_UART5_SOURCE()) \
{ \
switch(__HAL_RCC_GET_UART5_SOURCE()) \
{ \
case RCC_UART5CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@ -174,12 +175,12 @@ extern "C" {
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
switch(__HAL_RCC_GET_USART6_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART6_SOURCE()) \
{ \
case RCC_USART6CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
break; \
@ -195,12 +196,12 @@ extern "C" {
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if ((__HANDLE__)->Instance == UART7) \
{ \
switch(__HAL_RCC_GET_UART7_SOURCE()) \
{ \
switch(__HAL_RCC_GET_UART7_SOURCE()) \
{ \
case RCC_UART7CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@ -216,12 +217,12 @@ extern "C" {
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if ((__HANDLE__)->Instance == UART8) \
{ \
switch(__HAL_RCC_GET_UART8_SOURCE()) \
{ \
switch(__HAL_RCC_GET_UART8_SOURCE()) \
{ \
case RCC_UART8CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@ -237,7 +238,7 @@ extern "C" {
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else \
{ \
@ -252,44 +253,44 @@ extern "C" {
*/
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU ; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
/** @brief Ensure that IRDA frame length is valid.
* @param __LENGTH__ IRDA frame length.

371
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_lptim.h
View File

@ -18,11 +18,11 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_LPTIM_H
#define __STM32F7xx_HAL_LPTIM_H
#ifndef STM32F7xx_HAL_LPTIM_H
#define STM32F7xx_HAL_LPTIM_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@ -32,8 +32,9 @@
* @{
*/
/** @defgroup LPTIM LPTIM
* @brief LPTIM HAL module driver
#if defined (LPTIM1)
/** @addtogroup LPTIM
* @{
*/
@ -41,14 +42,7 @@
/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
* @{
*/
/** @defgroup LPTIM_WAKEUPTIMER_EXTILINE LPTIM WAKEUP Timer EXTI Line
* @{
*/
#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR23) /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */
/**
* @}
*/
#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR23 /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */
/**
* @brief LPTIM Clock configuration definition
@ -61,7 +55,7 @@ typedef struct
uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.
This parameter can be a value of @ref LPTIM_Clock_Prescaler */
}LPTIM_ClockConfigTypeDef;
} LPTIM_ClockConfigTypeDef;
/**
* @brief LPTIM Clock configuration definition
@ -79,7 +73,7 @@ typedef struct
Note: This parameter is used only when Ultra low power clock source is used.
This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
}LPTIM_ULPClockConfigTypeDef;
} LPTIM_ULPClockConfigTypeDef;
/**
* @brief LPTIM Trigger configuration definition
@ -96,7 +90,7 @@ typedef struct
uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.
Note: This parameter is used only when an external trigger is used.
This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */
}LPTIM_TriggerConfigTypeDef;
} LPTIM_TriggerConfigTypeDef;
/**
* @brief LPTIM Initialization Structure definition
@ -112,53 +106,58 @@ typedef struct
uint32_t OutputPolarity; /*!< Specifies the Output polarity.
This parameter can be a value of @ref LPTIM_Output_Polarity */
uint32_t UpdateMode; /*!< Specifies whether the update of the autorelaod and the compare
uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
values is done immediately or after the end of current period.
This parameter can be a value of @ref LPTIM_Updating_Mode */
uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
or each external event.
This parameter can be a value of @ref LPTIM_Counter_Source */
}LPTIM_InitTypeDef;
} LPTIM_InitTypeDef;
/**
* @brief HAL LPTIM State structure definition
*/
typedef enum __HAL_LPTIM_StateTypeDef
typedef enum
{
HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
}HAL_LPTIM_StateTypeDef;
HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
} HAL_LPTIM_StateTypeDef;
/**
* @brief LPTIM handle Structure definition
*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
typedef struct __LPTIM_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
{
LPTIM_TypeDef *Instance; /*!< Register base address */
LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
HAL_LockTypeDef Lock; /*!< LPTIM locking object */
__IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
LPTIM_TypeDef *Instance; /*!< Register base address */
LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
HAL_LockTypeDef Lock; /*!< LPTIM locking object */
__IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
void (* MspInitCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Msp Init Callback */
void (* MspDeInitCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Msp DeInit Callback */
void (* CompareMatchCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Compare Match Callback */
void (* AutoReloadMatchCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Auto Reload Match Callback */
void (* TriggerCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Trigger Callback */
void (* CompareWriteCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Compare Write Callback */
void (* AutoReloadWriteCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Auto Reload Write Callback */
void (* DirectionUpCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Direction Up Callback */
void (* DirectionDownCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Direction Down Callback */
void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */
void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */
void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */
void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */
void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */
void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */
void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */
void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */
void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}LPTIM_HandleTypeDef;
} LPTIM_HandleTypeDef;
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
/**
@ -166,25 +165,23 @@ typedef struct __LPTIM_HandleTypeDef
*/
typedef enum
{
HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM MspInit Callback ID */
HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM MspDeInit Callback ID */
HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< LPTIM Compare Match Callback ID */
HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID = 0x03U, /*!< LPTIM Auto Reload Match Callback ID */
HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< LPTIM Trigger Callback ID */
HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< LPTIM Compare Write Callback ID */
HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID = 0x06U, /*!< LPTIM Auto Reload Write Callback ID */
HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< LPTIM Direction Up Callback ID */
HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< LPTIM Direction Down Callback ID */
}HAL_LPTIM_CallbackIDTypeDef;
HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */
HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */
HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */
HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */
HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */
HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */
HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */
HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */
HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */
} HAL_LPTIM_CallbackIDTypeDef;
/**
* @brief HAL LPTIM Callback pointer definition
* @brief HAL TIM Callback pointer definition
*/
typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< pointer to the LPTIM callback function */
typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
* @}
*/
@ -197,7 +194,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin
/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
* @{
*/
#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U)
#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
/**
* @}
@ -206,14 +203,14 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin
/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
* @{
*/
#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U)
#define LPTIM_PRESCALER_DIV1 0x00000000U
#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
#define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)
#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
/**
* @}
*/
@ -222,8 +219,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin
* @{
*/
#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)
#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)
#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL
/**
* @}
*/
@ -231,10 +228,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin
/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
* @{
*/
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
/**
* @}
*/
@ -242,10 +239,9 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin
/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
* @{
*/
#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U)
#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U
#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
/**
* @}
*/
@ -253,13 +249,13 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin
/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
* @{
*/
#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU)
#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U)
#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
#define LPTIM_TRIGSOURCE_0 0x00000000U
#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
/**
* @}
*/
@ -277,7 +273,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin
/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
* @{
*/
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
@ -289,7 +285,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin
* @{
*/
#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U)
#define LPTIM_UPDATE_IMMEDIATE 0x00000000U
#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
/**
* @}
@ -299,13 +295,13 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin
* @{
*/
#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U)
#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
/**
* @}
*/
/** @defgroup LPTIM_Flag_Definition LPTIM Flag Definition
/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
* @{
*/
@ -323,7 +319,6 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin
/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
* @{
*/
#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define LPTIM_IT_UP LPTIM_IER_UPIE
#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE
@ -339,54 +334,79 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
* @{
*/
/** @brief Reset LPTIM handle state
/** @brief Reset LPTIM handle state.
* @param __HANDLE__ LPTIM handle
* @retval None
*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
* @brief Enable/Disable the LPTIM peripheral.
* @brief Enable the LPTIM peripheral.
* @param __HANDLE__ LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
#define __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))
#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
/**
* @brief Starts the LPTIM peripheral in Continuous or in single mode.
* @param __HANDLE__ DMA handle
* @brief Disable the LPTIM peripheral.
* @param __HANDLE__ LPTIM handle
* @note The following sequence is required to solve LPTIM disable HW limitation.
* Please check Errata Sheet ES0335 for more details under "MCU may remain
* stuck in LPTIM interrupt when entering Stop mode" section.
* @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
* check for TIMEOUT.
* @retval None
*/
#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
/**
* @brief Start the LPTIM peripheral in Continuous mode.
* @param __HANDLE__ LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
/**
* @brief Start the LPTIM peripheral in single mode.
* @param __HANDLE__ LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
/**
* @brief Writes the passed parameter in the Autoreload register.
* @brief Write the passed parameter in the Autoreload register.
* @param __HANDLE__ LPTIM handle
* @param __VALUE__ Autoreload value
* @param __VALUE__ Autoreload value
* @retval None
* @note The ARR register can only be modified when the LPTIM instance is enabled.
*/
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
/**
* @brief Writes the passed parameter in the Compare register.
* @brief Write the passed parameter in the Compare register.
* @param __HANDLE__ LPTIM handle
* @param __VALUE__ Compare value
* @param __VALUE__ Compare value
* @retval None
* @note The CMP register can only be modified when the LPTIM instance is enabled.
*/
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
/**
* @brief Checks whether the specified LPTIM flag is set or not.
* @brief Check whether the specified LPTIM flag is set or not.
* @param __HANDLE__ LPTIM handle
* @param __FLAG__ LPTIM flag to check
* @param __FLAG__ LPTIM flag to check
* This parameter can be a value of:
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
@ -400,9 +420,9 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin
#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
/**
* @brief Clears the specified LPTIM flag.
* @brief Clear the specified LPTIM flag.
* @param __HANDLE__ LPTIM handle.
* @param __FLAG__ LPTIM flag to clear.
* @param __FLAG__ LPTIM flag to clear.
* This parameter can be a value of:
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
@ -413,12 +433,12 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
* @retval None.
*/
#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/**
* @brief Enable the specified LPTIM interrupt.
* @param __HANDLE__ LPTIM handle.
* @param __INTERRUPT__ LPTIM interrupt to set.
* @param __HANDLE__ LPTIM handle.
* @param __INTERRUPT__ LPTIM interrupt to set.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
@ -428,13 +448,14 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
* @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
*/
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/**
/**
* @brief Disable the specified LPTIM interrupt.
* @param __HANDLE__ LPTIM handle.
* @param __INTERRUPT__ LPTIM interrupt to set.
* @param __HANDLE__ LPTIM handle.
* @param __INTERRUPT__ LPTIM interrupt to set.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
@ -444,13 +465,14 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
* @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
*/
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
/**
* @brief Checks whether the specified LPTIM interrupt is set or not.
* @param __HANDLE__ LPTIM handle.
* @param __INTERRUPT__ LPTIM interrupt to check.
/**
* @brief Check whether the specified LPTIM interrupt source is enabled or not.
* @param __HANDLE__ LPTIM handle.
* @param __INTERRUPT__ LPTIM interrupt to check.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
@ -522,7 +544,6 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin
/**
* @brief Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
* This parameter can be:
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
@ -556,6 +577,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin
* @{
*/
/** @addtogroup LPTIM_Exported_Functions_Group1
* @brief Initialization and Configuration functions.
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
@ -563,7 +588,14 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
/* MSP functions *************************************************************/
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
/** @addtogroup LPTIM_Exported_Functions_Group2
* @brief Start-Stop operation functions.
* @{
*/
/* Start/Stop operation functions *********************************************/
/* ################################# PWM Mode ################################*/
/* Blocking mode: Polling */
@ -612,12 +644,26 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
/** @addtogroup LPTIM_Exported_Functions_Group3
* @brief Read operation functions.
* @{
*/
/* Reading operation functions ************************************************/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
/** @addtogroup LPTIM_Exported_Functions_Group4
* @brief LPTIM IRQ handler and callback functions.
* @{
*/
/* LPTIM IRQ functions *******************************************************/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
@ -632,12 +678,22 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup LPTIM_Group5
* @brief Peripheral State functions.
* @{
*/
/* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
/**
* @}
@ -675,61 +731,63 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
* @{
*/
#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
((__TRIG__) == LPTIM_TRIGSOURCE_5))
#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__) (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING ) || \
((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING ) || \
((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
((__TRIG__) == LPTIM_TRIGSOURCE_5))
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFU)
#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFU)
#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
#define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFFU)
#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
#define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFFU)
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL)
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL)
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
/**
* @}
@ -739,7 +797,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
* @{
*/
void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
@ -748,6 +806,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
* @}
*/
#endif /* LPTIM1 */
/**
* @}
*/
@ -756,6 +815,6 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
}
#endif
#endif /* __STM32F7xx_HAL_LPTIM_H */
#endif /* STM32F7xx_HAL_LPTIM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

145
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_mmc.h
View File

@ -12,14 +12,16 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_MMC_H
#define __STM32F7xx_HAL_MMC_H
#ifndef STM32F7xx_HAL_MMC_H
#define STM32F7xx_HAL_MMC_H
#if defined(SDMMC1)
#ifdef __cplusplus
extern "C" {
@ -46,14 +48,14 @@
*/
typedef enum
{
HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), /*!< MMC not yet initialized or disabled */
HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), /*!< MMC initialized and ready for use */
HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< MMC Timeout state */
HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */
HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */
HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */
HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfert State */
HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */
HAL_MMC_STATE_RESET = 0x00000000U, /*!< MMC not yet initialized or disabled */
HAL_MMC_STATE_READY = 0x00000001U, /*!< MMC initialized and ready for use */
HAL_MMC_STATE_TIMEOUT = 0x00000002U, /*!< MMC Timeout state */
HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */
HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */
HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */
HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfert State */
HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */
}HAL_MMC_StateTypeDef;
/**
* @}
@ -62,18 +64,17 @@ typedef enum
/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
* @{
*/
typedef enum
{
HAL_MMC_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */
HAL_MMC_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */
HAL_MMC_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */
HAL_MMC_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
HAL_MMC_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */
HAL_MMC_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */
HAL_MMC_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */
HAL_MMC_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */
HAL_MMC_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */
}HAL_MMC_CardStateTypeDef;
typedef uint32_t HAL_MMC_CardStateTypeDef;
#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */
#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */
/**
* @}
*/
@ -114,23 +115,23 @@ typedef struct __MMC_HandleTypeDef
typedef struct
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
{
MMC_TypeDef *Instance; /*!< MMC registers base address */
MMC_TypeDef *Instance; /*!< MMC registers base address */
MMC_InitTypeDef Init; /*!< MMC required parameters */
MMC_InitTypeDef Init; /*!< MMC required parameters */
HAL_LockTypeDef Lock; /*!< MMC locking object */
uint32_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
uint32_t TxXferSize; /*!< MMC Tx Transfer size */
uint32_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
uint32_t RxXferSize; /*!< MMC Rx Transfer size */
__IO uint32_t Context; /*!< MMC transfer context */
__IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
__IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
__IO uint32_t ErrorCode; /*!< MMC Card Error codes */
@ -138,13 +139,13 @@ typedef struct
DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
uint32_t CSD[4]; /*!< MMC card specific data table */
uint32_t CSD[4U]; /*!< MMC card specific data table */
uint32_t CID[4]; /*!< MMC card identification number table */
uint32_t CID[4U]; /*!< MMC card identification number table */
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc);
@ -193,7 +194,7 @@ typedef struct
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
__IO uint8_t Reserved3; /*!< Reserved */
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
__IO uint8_t FileFormatGrouop; /*!< File format group */
__IO uint8_t FileFormatGroup; /*!< File format group */
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
@ -227,6 +228,7 @@ typedef struct
/**
* @}
*/
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
* @{
@ -262,8 +264,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @{
*/
#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */
#define CAPACITY ((uint32_t)0x80000000U) /*!< 2 G bytes constant */
#define MMC_BLOCKSIZE 512U /*!< Block size is 512 bytes */
/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
* @{
@ -304,6 +305,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
#endif
@ -314,13 +316,13 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
* @{
*/
#define MMC_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */
#define MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */
#define MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */
#define MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */
#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */
#define MMC_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */
#define MMC_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
#define MMC_CONTEXT_NONE 0x00000000U /*!< None */
#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
/**
* @}
@ -344,8 +346,9 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
* @{
*/
#define MMC_HIGH_VOLTAGE_CARD ((uint32_t)0x00000000U)
#define MMC_DUAL_VOLTAGE_CARD ((uint32_t)0x00000001U)
#define MMC_LOW_CAPACITY_CARD 0x00000000U /*!< MMC Card Capacity <=2Gbytes */
#define MMC_HIGH_CAPACITY_CARD 0x00000001U /*!< MMC Card Capacity >2Gbytes and <2Tbytes */
/**
* @}
*/
@ -399,8 +402,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @brief Enable the MMC device interrupt.
* @param __HANDLE__ MMC Handle
* @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
* @param __HANDLE__: MMC Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@ -410,7 +413,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@ -430,8 +433,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @brief Disable the MMC device interrupt.
* @param __HANDLE__ MMC Handle
* @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
* @param __HANDLE__: MMC Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@ -441,7 +444,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@ -461,8 +464,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @brief Check whether the specified MMC flag is set or not.
* @param __HANDLE__ MMC Handle
* @param __FLAG__ specifies the flag to check.
* @param __HANDLE__: MMC Handle
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@ -472,7 +475,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
* @arg SDMMC_FLAG_TXACT: Data transmit in progress
@ -492,8 +495,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @brief Clear the MMC's pending flags.
* @param __HANDLE__ MMC Handle
* @param __FLAG__ specifies the flag to clear.
* @param __HANDLE__: MMC Handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@ -503,7 +506,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
* @retval None
@ -512,8 +515,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @brief Check whether the specified MMC interrupt has occurred or not.
* @param __HANDLE__ MMC Handle
* @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
* @param __HANDLE__: MMC Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@ -523,7 +526,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@ -537,14 +540,14 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval The new state of SD IT (SET or RESET).
* @retval The new state of MMC IT (SET or RESET).
*/
#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Clear the MMC's interrupt pending bits.
* @param __HANDLE__ MMC Handle
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* @param __HANDLE__: MMC Handle
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@ -554,7 +557,12 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval None
*/
@ -577,6 +585,7 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
@ -624,9 +633,9 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32
* @{
*/
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
/**
* @}
*/
@ -725,12 +734,12 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* SDMMC1 */
#endif /* __STM32F7xx_HAL_MMC_H */
#endif /* STM32F7xx_HAL_MMC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

48
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_pcd.h
View File

@ -96,16 +96,16 @@ typedef struct __PCD_HandleTypeDef
typedef struct
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
__IO uint8_t USB_Address; /*!< USB Address */
PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
__IO uint32_t ErrorCode; /*!< PCD Error code */
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
__IO uint8_t USB_Address; /*!< USB Address */
PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
__IO uint32_t ErrorCode; /*!< PCD Error code */
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
@ -148,9 +148,9 @@ typedef struct
/** @defgroup PCD_Speed PCD Speed
* @{
*/
#define PCD_SPEED_HIGH 0U
#define PCD_SPEED_HIGH_IN_FULL 1U
#define PCD_SPEED_FULL 2U
#define PCD_SPEED_HIGH USBD_HS_SPEED
#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED
#define PCD_SPEED_FULL USBD_FS_SPEED
/**
* @}
*/
@ -207,20 +207,20 @@ typedef struct
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
do { \
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
do { \
EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
} while(0U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
do { \
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
do { \
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
} while(0U)
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
@ -256,7 +256,7 @@ typedef enum
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
@ -371,14 +371,6 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U
#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */

437
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_qspi.h
View File

@ -12,14 +12,14 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_QSPI_H
#define __STM32F7xx_HAL_QSPI_H
#ifndef STM32F7xx_HAL_QSPI_H
#define STM32F7xx_HAL_QSPI_H
#ifdef __cplusplus
extern "C" {
@ -28,6 +28,8 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
#if defined(QUADSPI)
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
@ -44,35 +46,27 @@
/**
* @brief QSPI Init structure definition
*/
typedef struct
{
uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
This parameter can be a number between 0 and 255 */
uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
This parameter can be a value between 1 and 32 */
uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
This parameter can be a value of @ref QSPI_SampleShifting */
uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
required to address the flash memory. The flash capacity can be up to 4GB
(addressed using 32 bits) in indirect mode, but the addressable space in
memory-mapped mode is limited to 256MB
This parameter can be a number between 0 and 31 */
uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
of clock cycles which the chip select must remain high between commands.
This parameter can be a value of @ref QSPI_ChipSelectHighTime */
uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
This parameter can be a value of @ref QSPI_ClockMode */
uint32_t FlashID; /* Specifies the Flash which will be used,
This parameter can be a value of @ref QSPI_Flash_Select */
uint32_t DualFlash; /* Specifies the Dual Flash Mode State
This parameter can be a value of @ref QSPI_DualFlash_Mode */
}QSPI_InitTypeDef;
@ -157,15 +151,15 @@ typedef struct
This parameter can be a value of @ref QSPI_AlternateBytesMode */
uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
This parameter can be a value of @ref QSPI_DataMode */
uint32_t NbData; /* Specifies the number of data to transfer.
uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
until end of memory)*/
uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
This parameter can be a value of @ref QSPI_DdrMode */
uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
system clock in DDR mode.
uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data
output by one half of system clock in DDR mode.
This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
uint32_t SIOOMode; /* Specifies the send instruction only once mode
uint32_t SIOOMode; /* Specifies the send instruction only once mode
This parameter can be a value of @ref QSPI_SIOOMode */
}QSPI_CommandTypeDef;
@ -195,7 +189,7 @@ typedef struct
{
uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
This parameter can be any value between 0 and 0xFFFF */
uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
This parameter can be a value of @ref QSPI_TimeOutActivation */
}QSPI_MemoryMappedTypeDef;
@ -233,14 +227,15 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
* @{
*/
/** @defgroup QSPI_ErrorCode QSPI Error Code
* @{
*/
#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */
#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */
#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
#endif
@ -251,23 +246,23 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
* @{
*/
#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!<No clock cycle shift to sample data*/
#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/
#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
/**
* @}
*/
/** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
* @{
*/
#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U) /*!<nCS stay high for at least 1 clock cycle between commands*/
#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/
#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
/**
* @}
*/
@ -275,8 +270,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_ClockMode QSPI Clock Mode
* @{
*/
#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!<Clk stays low while nCS is released*/
#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
#define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/
#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
/**
* @}
*/
@ -284,17 +279,17 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_Flash_Select QSPI Flash Select
* @{
*/
#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000U)
#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
#define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/
#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
/**
* @}
*/
/** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
/** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
* @{
*/
#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000U)
#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
#define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/
/**
* @}
*/
@ -302,7 +297,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_AddressSize QSPI Address Size
* @{
*/
#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!<8-bit address*/
#define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/
#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
@ -313,7 +308,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
* @{
*/
#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!<8-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
@ -324,7 +319,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
* @{
*/
#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!<No instruction*/
#define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/
#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
@ -335,7 +330,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_AddressMode QSPI Address Mode
* @{
*/
#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!<No address*/
#define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/
#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
@ -343,10 +338,10 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
* @}
*/
/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
* @{
*/
#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!<No alternate bytes*/
#define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/
#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
@ -357,7 +352,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_DataMode QSPI Data Mode
* @{
*/
#define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
#define QSPI_DATA_NONE 0x00000000U /*!<No data*/
#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
@ -365,28 +360,28 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
* @}
*/
/** @defgroup QSPI_DdrMode QSPI Ddr Mode
/** @defgroup QSPI_DdrMode QSPI DDR Mode
* @{
*/
#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000U) /*!<Double data rate mode disabled*/
#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
#define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/
#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
/**
* @}
*/
/** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
* @{
*/
#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000U) /*!<Delay the data output using analog delay in DDR mode*/
#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
#define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/
#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/
/**
* @}
*/
/** @defgroup QSPI_SIOOMode QSPI SIOO Mode
/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
* @{
*/
#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!<Send instruction on every transaction*/
#define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/
#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
/**
* @}
@ -395,8 +390,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_MatchMode QSPI Match Mode
* @{
*/
#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!<AND match mode between unmasked bits*/
#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
#define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/
#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
/**
* @}
*/
@ -404,22 +399,22 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
* @{
*/
#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!<AutoPolling stops only with abort or QSPI disabling*/
#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/
#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
/**
* @}
*/
/** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
* @{
*/
#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!<Timeout counter disabled, nCS remains active*/
#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/
#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
/**
* @}
*/
/** @defgroup QSPI_Flags QSPI Flags
/** @defgroup QSPI_Flags QSPI Flags
* @{
*/
#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
@ -432,22 +427,23 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
* @}
*/
/** @defgroup QSPI_Interrupts QSPI Interrupts
/** @defgroup QSPI_Interrupts QSPI Interrupts
* @{
*/
#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
/**
* @}
*/
/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
* @brief QSPI Timeout definition
* @{
*/
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
/**
* @}
*/
@ -460,9 +456,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
* @{
*/
/** @brief Reset QSPI handle state
* @param __HANDLE__ QSPI handle.
/** @brief Reset QSPI handle state.
* @param __HANDLE__ : QSPI handle.
* @retval None
*/
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
@ -475,23 +470,23 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
#endif
/** @brief Enable QSPI
* @param __HANDLE__ specifies the QSPI Handle.
/** @brief Enable the QSPI peripheral.
* @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Disable QSPI
* @param __HANDLE__ specifies the QSPI Handle.
/** @brief Disable the QSPI peripheral.
* @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Enables the specified QSPI interrupt.
* @param __HANDLE__ specifies the QSPI Handle.
* @param __INTERRUPT__ specifies the QSPI interrupt source to enable.
/** @brief Enable the specified QSPI interrupt.
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __INTERRUPT__ : specifies the QSPI interrupt source to enable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Time out interrupt
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
@ -501,9 +496,9 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Disables the specified QSPI interrupt.
* @param __HANDLE__ specifies the QSPI Handle.
* @param __INTERRUPT__ specifies the QSPI interrupt source to disable.
/** @brief Disable the specified QSPI interrupt.
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __INTERRUPT__ : specifies the QSPI interrupt source to disable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@ -514,11 +509,11 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
*/
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Checks whether the specified QSPI interrupt source is enabled.
* @param __HANDLE__ specifies the QSPI Handle.
* @param __INTERRUPT__ specifies the QSPI interrupt source to check.
/** @brief Check whether the specified QSPI interrupt source is enabled or not.
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __INTERRUPT__ : specifies the QSPI interrupt source to check.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Time out interrupt
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
@ -528,25 +523,25 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Get the selected QSPI's flag status.
* @param __HANDLE__ specifies the QSPI Handle.
* @param __FLAG__ specifies the QSPI flag to check.
* @brief Check whether the selected QSPI flag is set or not.
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __FLAG__ : specifies the QSPI flag to check.
* This parameter can be one of the following values:
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
* @arg QSPI_FLAG_TO: QSPI Time out flag
* @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
* @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
* @retval None
*/
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
/** @brief Clears the specified QSPI's flag status.
* @param __HANDLE__ specifies the QSPI Handle.
* @param __FLAG__ specifies the QSPI clear register flag that needs to be set
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __FLAG__ : specifies the QSPI clear register flag that needs to be set
* This parameter can be one of the following values:
* @arg QSPI_FLAG_TO: QSPI Time out flag
* @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
@ -597,13 +592,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Co
/* QSPI memory-mapped mode */
HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
/**
* @}
*/
/** @addtogroup QSPI_Exported_Functions_Group3
* @{
*/
/* Callback functions in non-blocking modes ***********************************/
void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
@ -631,7 +620,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi,
* @}
*/
/** @addtogroup QSPI_Exported_Functions_Group4
/** @addtogroup QSPI_Exported_Functions_Group3
* @{
*/
/* Peripheral Control and State functions ************************************/
@ -642,6 +631,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
/**
* @}
*/
@ -649,161 +639,100 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup QSPI_Private_Macros QSPI Private Macros
* @{
*/
/** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
* @{
*/
#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
((CLKMODE) == QSPI_CLOCK_MODE_3))
#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \
((FLASH_ID) == QSPI_FLASH_ID_2))
#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
((MODE) == QSPI_DUALFLASH_DISABLE))
#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
((MODE) == QSPI_INSTRUCTION_1_LINE) || \
((MODE) == QSPI_INSTRUCTION_2_LINES) || \
((MODE) == QSPI_INSTRUCTION_4_LINES))
#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
((MODE) == QSPI_ADDRESS_1_LINE) || \
((MODE) == QSPI_ADDRESS_2_LINES) || \
((MODE) == QSPI_ADDRESS_4_LINES))
#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
((MODE) == QSPI_DATA_1_LINE) || \
((MODE) == QSPI_DATA_2_LINES) || \
((MODE) == QSPI_DATA_4_LINES))
#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
((MODE) == QSPI_MATCH_MODE_OR))
#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
/**
* @}
*/
/** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold
* @{
*/
#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32))
/**
* @}
*/
#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
/** @defgroup QSPI_FlashSize QSPI Flash Size
* @{
*/
#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
/**
* @}
*/
#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
((CLKMODE) == QSPI_CLOCK_MODE_3))
#define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \
((FLA) == QSPI_FLASH_ID_2))
#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
((MODE) == QSPI_DUALFLASH_DISABLE))
/** @defgroup QSPI_Instruction QSPI Instruction
* @{
*/
#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
/**
* @}
*/
#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
/** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
* @{
*/
#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
/**
* @}
*/
#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
((MODE) == QSPI_INSTRUCTION_1_LINE) || \
((MODE) == QSPI_INSTRUCTION_2_LINES) || \
((MODE) == QSPI_INSTRUCTION_4_LINES))
#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
((MODE) == QSPI_ADDRESS_1_LINE) || \
((MODE) == QSPI_ADDRESS_2_LINES) || \
((MODE) == QSPI_ADDRESS_4_LINES))
#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
((MODE) == QSPI_DATA_1_LINE) || \
((MODE) == QSPI_DATA_2_LINES) || \
((MODE) == QSPI_DATA_4_LINES))
#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
/** @defgroup QSPI_Interval QSPI Interval
* @{
*/
#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
/**
* @}
*/
/** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
* @{
*/
#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
/**
* @}
*/
#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
((MODE) == QSPI_MATCH_MODE_OR))
#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
/** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period
* @{
*/
#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)
/**
* @}
*/
#define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \
((FLAG) == QSPI_FLAG_TO) || \
((FLAG) == QSPI_FLAG_SM) || \
((FLAG) == QSPI_FLAG_FT) || \
((FLAG) == QSPI_FLAG_TC) || \
((FLAG) == QSPI_FLAG_TE))
#define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup QSPI_Private_Functions QSPI Private Functions
* @{
*/
* @}
*/
/* End of private macros -----------------------------------------------------*/
/**
* @}
@ -813,14 +742,12 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
* @}
*/
/**
* @}
*/
#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F7xx_HAL_QSPI_H */
#endif /* STM32F7xx_HAL_QSPI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

8
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rcc.h
View File

@ -413,7 +413,7 @@ typedef struct
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
@ -443,14 +443,14 @@ typedef struct
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_PWR_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
UNUSED(tmpreg); \
} while(0)
} while(0)
#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
@ -472,7 +472,7 @@ typedef struct
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
/**

9
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sai.h
View File

@ -97,9 +97,10 @@ typedef struct
uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
This parameter can be a value of @ref SAI_Audio_Frequency */
uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for
AudioFrequency the user choice
This parameter must be a number between Min_Data = 0 and Max_Data = 15 */
uint32_t Mckdiv; /*!< Specifies the master clock divider.
This parameter must be a number between Min_Data = 0 and Max_Data = 15.
@note This parameter is used only if AudioFrequency is set to
SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */
uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected.
This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
@ -841,7 +842,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15U)
#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))

161
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sd.h
View File

@ -12,19 +12,21 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_SD_H
#define __STM32F7xx_HAL_SD_H
#ifndef STM32F7xx_HAL_SD_H
#define STM32F7xx_HAL_SD_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(SDMMC1)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_sdmmc.h"
@ -47,14 +49,14 @@
*/
typedef enum
{
HAL_SD_STATE_RESET = ((uint32_t)0x00000000U), /*!< SD not yet initialized or disabled */
HAL_SD_STATE_READY = ((uint32_t)0x00000001U), /*!< SD initialized and ready for use */
HAL_SD_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< SD Timeout state */
HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U), /*!< SD process ongoing */
HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< SD Programming State */
HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< SD Receinving State */
HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfert State */
HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */
HAL_SD_STATE_RESET = 0x00000000U, /*!< SD not yet initialized or disabled */
HAL_SD_STATE_READY = 0x00000001U, /*!< SD initialized and ready for use */
HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */
HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */
HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */
HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receiving State */
HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfert State */
HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */
}HAL_SD_StateTypeDef;
/**
* @}
@ -63,18 +65,17 @@ typedef enum
/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
* @{
*/
typedef enum
{
HAL_SD_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */
HAL_SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */
HAL_SD_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */
HAL_SD_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
HAL_SD_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */
HAL_SD_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */
HAL_SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */
HAL_SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */
HAL_SD_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */
}HAL_SD_CardStateTypeDef;
typedef uint32_t HAL_SD_CardStateTypeDef;
#define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */
#define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
#define HAL_SD_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
#define HAL_SD_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
#define HAL_SD_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
#define HAL_SD_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
#define HAL_SD_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
#define HAL_SD_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
#define HAL_SD_CARD_ERROR 0x000000FFU /*!< Card response Error */
/**
* @}
*/
@ -111,7 +112,11 @@ typedef struct
/**
* @brief SD handle Structure definition
*/
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
typedef struct __SD_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
{
SD_TypeDef *Instance; /*!< SD registers base address */
@ -119,11 +124,11 @@ typedef struct __SD_HandleTypeDef
HAL_LockTypeDef Lock; /*!< SD locking object */
uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
uint32_t TxXferSize; /*!< SD Tx Transfer size */
uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
uint32_t RxXferSize; /*!< SD Rx Transfer size */
@ -133,17 +138,17 @@ typedef struct __SD_HandleTypeDef
__IO uint32_t ErrorCode; /*!< SD Card Error codes */
DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
uint32_t CSD[4]; /*!< SD card specific data table */
uint32_t CID[4]; /*!< SD card identification number table */
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd);
@ -151,7 +156,7 @@ typedef struct __SD_HandleTypeDef
void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd);
void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd);
#endif
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}SD_HandleTypeDef;
/**
@ -192,7 +197,7 @@ typedef struct
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
__IO uint8_t Reserved3; /*!< Reserved */
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
__IO uint8_t FileFormatGrouop; /*!< File format group */
__IO uint8_t FileFormatGroup; /*!< File format group */
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
@ -200,7 +205,6 @@ typedef struct
__IO uint8_t ECC; /*!< ECC code */
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< Always 1 */
}HAL_SD_CardCSDTypeDef;
/**
* @}
@ -248,7 +252,7 @@ typedef struct
* @}
*/
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
* @{
*/
@ -273,7 +277,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
/**
* @}
*/
#endif
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @}
*/
@ -283,7 +287,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @{
*/
#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */
#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
* @{
@ -325,10 +329,9 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
#endif
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @}
*/
@ -336,13 +339,13 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
* @{
*/
#define SD_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */
#define SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */
#define SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */
#define SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */
#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */
#define SD_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */
#define SD_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
#define SD_CONTEXT_NONE 0x00000000U /*!< None */
#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
/**
* @}
@ -351,9 +354,9 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
* @{
*/
#define CARD_SDSC ((uint32_t)0x00000000U)
#define CARD_SDHC_SDXC ((uint32_t)0x00000001U)
#define CARD_SECURED ((uint32_t)0x00000003U)
#define CARD_SDSC 0x00000000U /*!< SD Standard Capacity <2Go */
#define CARD_SDHC_SDXC 0x00000001U /*!< SD High Capacity <32Go, SD Extended Capacity <2To */
#define CARD_SECURED 0x00000003U
/**
* @}
@ -362,8 +365,8 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
* @{
*/
#define CARD_V1_X ((uint32_t)0x00000000U)
#define CARD_V2_X ((uint32_t)0x00000001U)
#define CARD_V1_X 0x00000000U
#define CARD_V2_X 0x00000001U
/**
* @}
*/
@ -381,7 +384,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @param __HANDLE__ : SD handle.
* @retval None
*/
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_SD_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
@ -389,7 +392,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
} while(0)
#else
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET)
#endif
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @brief Enable the SD device.
@ -417,8 +420,8 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
/**
* @brief Enable the SD device interrupt.
* @param __HANDLE__ SD Handle
* @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
* @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@ -428,7 +431,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@ -441,15 +444,15 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Disable the SD device interrupt.
* @param __HANDLE__ SD Handle
* @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
* @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@ -459,7 +462,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@ -472,15 +475,15 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Check whether the specified SD flag is set or not.
* @param __HANDLE__ SD Handle
* @param __FLAG__ specifies the flag to check.
* @param __HANDLE__: SD Handle
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@ -490,7 +493,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
* @arg SDMMC_FLAG_TXACT: Data transmit in progress
@ -503,15 +506,15 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
* @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
* @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
* @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
* @retval The new state of SD FLAG (SET or RESET).
*/
#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Clear the SD's pending flags.
* @param __HANDLE__ SD Handle
* @param __FLAG__ specifies the flag to clear.
* @param __HANDLE__: SD Handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@ -521,17 +524,17 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
* @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
* @retval None
*/
#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Check whether the specified SD interrupt has occurred or not.
* @param __HANDLE__ SD Handle
* @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
* @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@ -541,7 +544,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@ -554,15 +557,15 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @retval The new state of SD IT (SET or RESET).
*/
#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Clear the SD's interrupt pending bits.
* @param __HANDLE__ SD Handle
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@ -572,8 +575,8 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
@ -621,11 +624,12 @@ void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/* SD callback registering/unregistering */
HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId);
#endif
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @}
*/
@ -745,12 +749,13 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
* @}
*/
#endif /* SDMMC1 */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F7xx_HAL_SD_H */
#endif /* STM32F7xx_HAL_SD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

2
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sdram.h
View File

@ -41,7 +41,7 @@
/** @defgroup SDRAM_Exported_Types SDRAM Exported Types
* @{
*/
/**
* @brief HAL SDRAM State structure definition
*/

71
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_smartcard.h
View File

@ -524,15 +524,15 @@ typedef enum
*/
#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
} while(0U)
#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
@ -540,11 +540,11 @@ typedef enum
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
} while(0U)
#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
} while(0U)
/** @brief Clear the specified SMARTCARD pending flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@ -667,7 +667,8 @@ typedef enum
* @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@ -685,8 +686,8 @@ typedef enum
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@ -726,7 +727,8 @@ typedef enum
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
&= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable the USART associated to the SMARTCARD Handle.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@ -758,8 +760,8 @@ typedef enum
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
break; \
@ -775,12 +777,12 @@ typedef enum
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
@ -796,12 +798,12 @@ typedef enum
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
@ -817,12 +819,12 @@ typedef enum
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
switch(__HAL_RCC_GET_USART6_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART6_SOURCE()) \
{ \
case RCC_USART6CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
break; \
@ -838,7 +840,7 @@ typedef enum
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else \
{ \
@ -905,7 +907,8 @@ typedef enum
* @param __CPOL__ SMARTCARD frame polarity.
* @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
*/
#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\
|| ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
/** @brief Ensure that SMARTCARD frame phase is valid.
* @param __CPHA__ SMARTCARD frame phase.
@ -1034,8 +1037,10 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
@ -1047,8 +1052,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
* @{
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);

11
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_smartcard_ex.h
View File

@ -166,7 +166,7 @@ extern "C" {
do { \
if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \
{ \
(__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
(__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
} \
else \
{ \
@ -243,15 +243,6 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef
* @}
*/
/** @addtogroup SMARTCARDEx_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ***********************************************/
/**
* @}
*/
/**
* @}

354
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_tim.h
View File

@ -167,7 +167,7 @@ typedef struct
This parameter can be a value of @ref TIM_Encoder_Mode */
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC1Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@ -179,7 +179,7 @@ typedef struct
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC2Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@ -235,7 +235,12 @@ typedef struct
uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
uint32_t MasterSlaveMode; /*!< Master/slave mode selection
This parameter can be a value of @ref TIM_Master_Slave_Mode */
This parameter can be a value of @ref TIM_Master_Slave_Mode
@note When the Master/slave mode is enabled, the effect of
an event on the trigger input (TRGI) is delayed to allow a
perfect synchronization between the current timer and its
slaves (through TRGO). It is not mandatory in case of timer
synchronization mode. */
} TIM_MasterConfigTypeDef;
/**
@ -518,6 +523,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @}
*/
/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
* @{
*/
#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */
#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */
/**
* @}
*/
/** @defgroup TIM_ClockDivision TIM Clock Division
* @{
*/
@ -611,6 +625,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @}
*/
/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
* @{
*/
#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
/**
* @}
*/
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
@ -1119,15 +1142,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @retval None
*/
#define __HAL_TIM_DISABLE(__HANDLE__) \
do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \
(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
} \
} \
} while(0)
do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \
(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
} \
} \
} while(0)
/**
* @brief Disable the TIM main Output.
@ -1136,15 +1159,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
} \
} \
} while(0)
do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
} \
} \
} while(0)
/**
* @brief Disable the TIM main Output.
@ -1279,7 +1302,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @arg TIM_IT_BREAK: Break interrupt
* @retval The state of TIM_IT (SET or RESET).
*/
#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
== (__INTERRUPT__)) ? SET : RESET)
/** @brief Clear the TIM interrupt pending bits.
* @param __HANDLE__ TIM handle
@ -1297,6 +1321,31 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
*/
#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
/**
* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
* @param __HANDLE__ TIM handle.
* @retval None
mode.
*/
#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
/**
* @brief Disable update interrupt flag (UIF) remapping.
* @param __HANDLE__ TIM handle.
* @retval None
mode.
*/
#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
/**
* @brief Get update interrupt flag (UIF) copy status.
* @param __COUNTER__ Counter value.
* @retval The state of UIFCPY (TRUE or FALSE).
mode.
*/
#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
/**
* @brief Indicates whether or not the TIM Counter is used as downcounter.
* @param __HANDLE__ TIM handle.
@ -1316,6 +1365,8 @@ mode.
/**
* @brief Set the TIM Counter Register value on runtime.
* Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.
* Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
* @param __HANDLE__ TIM handle.
* @param __COUNTER__ specifies the Counter register new value.
* @retval None
@ -1327,8 +1378,7 @@ mode.
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
*/
#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
((__HANDLE__)->Instance->CNT)
#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
/**
* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
@ -1337,18 +1387,17 @@ mode.
* @retval None
*/
#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
do{ \
(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
} while(0)
do{ \
(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
} while(0)
/**
* @brief Get the TIM Autoreload Register value on runtime.
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
*/
#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
((__HANDLE__)->Instance->ARR)
#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
/**
* @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
@ -1361,11 +1410,11 @@ mode.
* @retval None
*/
#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
do{ \
(__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
(__HANDLE__)->Instance->CR1 |= (__CKD__); \
(__HANDLE__)->Init.ClockDivision = (__CKD__); \
} while(0)
do{ \
(__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
(__HANDLE__)->Instance->CR1 |= (__CKD__); \
(__HANDLE__)->Init.ClockDivision = (__CKD__); \
} while(0)
/**
* @brief Get the TIM Clock Division value on runtime.
@ -1375,8 +1424,7 @@ mode.
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
*/
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/**
* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
@ -1396,10 +1444,10 @@ mode.
* @retval None
*/
#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
do{ \
TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
} while(0)
do{ \
TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
} while(0)
/**
* @brief Get the TIM Input Capture prescaler on runtime.
@ -1437,12 +1485,12 @@ mode.
* @retval None
*/
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
/**
* @brief Get the TIM Capture Compare Register value on runtime.
@ -1458,12 +1506,12 @@ mode.
* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
*/
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
((__HANDLE__)->Instance->CCR6))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
((__HANDLE__)->Instance->CCR6))
/**
* @brief Set the TIM Output compare preload.
@ -1479,12 +1527,12 @@ mode.
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
/**
* @brief Reset the TIM Output compare preload.
@ -1500,12 +1548,62 @@ mode.
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
/**
* @brief Enable fast mode for a given channel.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @note When fast mode is enabled an active edge on the trigger input acts
* like a compare match on CCx output. Delay to sample the trigger
* input and to activate CCx output is reduced to 3 clock cycles.
* @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
/**
* @brief Disable fast mode for a given channel.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @note When fast mode is disabled CCx output behaves normally depending
* on counter and CCRx values even when the trigger is ON. The minimum
* delay to activate CCx output when an active edge occurs on the
* trigger input is 5 clock cycles.
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
/**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
@ -1515,8 +1613,7 @@ mode.
* enabled)
* @retval None
*/
#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
/**
* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
@ -1529,8 +1626,7 @@ mode.
* _ Update generation through the slave mode controller
* @retval None
*/
#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
/**
* @brief Set the TIM Capture x input polarity on runtime.
@ -1548,10 +1644,10 @@ mode.
* @retval None
*/
#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
do{ \
TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
}while(0)
do{ \
TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
}while(0)
/**
* @}
@ -1579,29 +1675,29 @@ mode.
((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
#if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE)
#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
((__BASE__) == TIM_DMABASE_CR2) || \
((__BASE__) == TIM_DMABASE_SMCR) || \
((__BASE__) == TIM_DMABASE_DIER) || \
((__BASE__) == TIM_DMABASE_SR) || \
((__BASE__) == TIM_DMABASE_EGR) || \
((__BASE__) == TIM_DMABASE_CCMR1) || \
((__BASE__) == TIM_DMABASE_CCMR2) || \
((__BASE__) == TIM_DMABASE_CCER) || \
((__BASE__) == TIM_DMABASE_CNT) || \
((__BASE__) == TIM_DMABASE_PSC) || \
((__BASE__) == TIM_DMABASE_ARR) || \
((__BASE__) == TIM_DMABASE_RCR) || \
((__BASE__) == TIM_DMABASE_CCR1) || \
((__BASE__) == TIM_DMABASE_CCR2) || \
((__BASE__) == TIM_DMABASE_CCR3) || \
((__BASE__) == TIM_DMABASE_CCR4) || \
((__BASE__) == TIM_DMABASE_BDTR) || \
((__BASE__) == TIM_DMABASE_OR) || \
((__BASE__) == TIM_DMABASE_CCMR3) || \
((__BASE__) == TIM_DMABASE_CCR5) || \
((__BASE__) == TIM_DMABASE_CCR6) || \
((__BASE__) == TIM_DMABASE_AF1) || \
#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
((__BASE__) == TIM_DMABASE_CR2) || \
((__BASE__) == TIM_DMABASE_SMCR) || \
((__BASE__) == TIM_DMABASE_DIER) || \
((__BASE__) == TIM_DMABASE_SR) || \
((__BASE__) == TIM_DMABASE_EGR) || \
((__BASE__) == TIM_DMABASE_CCMR1) || \
((__BASE__) == TIM_DMABASE_CCMR2) || \
((__BASE__) == TIM_DMABASE_CCER) || \
((__BASE__) == TIM_DMABASE_CNT) || \
((__BASE__) == TIM_DMABASE_PSC) || \
((__BASE__) == TIM_DMABASE_ARR) || \
((__BASE__) == TIM_DMABASE_RCR) || \
((__BASE__) == TIM_DMABASE_CCR1) || \
((__BASE__) == TIM_DMABASE_CCR2) || \
((__BASE__) == TIM_DMABASE_CCR3) || \
((__BASE__) == TIM_DMABASE_CCR4) || \
((__BASE__) == TIM_DMABASE_BDTR) || \
((__BASE__) == TIM_DMABASE_OR) || \
((__BASE__) == TIM_DMABASE_CCMR3) || \
((__BASE__) == TIM_DMABASE_CCR5) || \
((__BASE__) == TIM_DMABASE_CCR6) || \
((__BASE__) == TIM_DMABASE_AF1) || \
((__BASE__) == TIM_DMABASE_AF2))
#else
#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
@ -1636,6 +1732,9 @@ mode.
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
((__MODE__) == TIM_UIFREMAP_ENALE))
#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV4))
@ -1658,6 +1757,9 @@ mode.
#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
((__STATE__) == TIM_OCNIDLESTATE_RESET))
#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
@ -1876,28 +1978,28 @@ mode.
((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
/**
* @}
@ -2035,7 +2137,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
@ -2059,17 +2162,19 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel);
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
uint32_t OutputChannel, uint32_t InputChannel);
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
@ -2095,7 +2200,8 @@ void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
pTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
@ -2125,8 +2231,8 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
/* Private functions----------------------------------------------------------*/
/** @defgroup TIM_Private_Functions TIM Private Functions
* @{
*/
* @{
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
@ -2145,8 +2251,8 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
* @}
*/
* @}
*/
/* End of private functions --------------------------------------------------*/
/**

50
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_tim_ex.h
View File

@ -201,9 +201,9 @@ TIMEx_BreakInputConfigTypeDef;
*/
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
* @brief Timer Hall Sensor functions
* @{
*/
* @brief Timer Hall Sensor functions
* @{
*/
/* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
@ -225,9 +225,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
*/
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
* @brief Timer Complementary Output Compare functions
* @{
*/
* @brief Timer Complementary Output Compare functions
* @{
*/
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
@ -245,9 +245,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
*/
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
* @brief Timer Complementary PWM functions
* @{
*/
* @brief Timer Complementary PWM functions
* @{
*/
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
@ -264,9 +264,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
*/
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
* @brief Timer Complementary One Pulse functions
* @{
*/
* @brief Timer Complementary One Pulse functions
* @{
*/
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
@ -280,17 +280,23 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
*/
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
* @brief Peripheral Control functions
* @{
*/
/* Extended Control functions ************************************************/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
#if defined(TIM_BREAK_INPUT_SUPPORT)
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
#endif /* TIM_BREAK_INPUT_SUPPORT */
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
@ -327,7 +333,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);

151
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_uart.h
View File

@ -125,8 +125,6 @@ typedef struct
This parameter can be a value of @ref UART_MSB_First. */
} UART_AdvFeatureInitTypeDef;
/**
* @brief HAL UART State definition
* @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).
@ -206,10 +204,9 @@ typedef struct __UART_HandleTypeDef
uint16_t Mask; /*!< UART Rx RDR register mask */
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
@ -313,8 +310,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */
#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
@ -400,11 +399,11 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @}
*/
/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
/** @defgroup UART_Receiver_Timeout UART Receiver Timeout
* @{
*/
#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART receiver timeout disable */
#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART receiver timeout enable */
#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */
#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */
/**
* @}
*/
@ -562,6 +561,17 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
/**
* @}
*/
#if defined(USART_CR1_UESM)
/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable
* @{
*/
#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */
#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */
/**
* @}
*/
#endif /* USART_CR1_UESM */
/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
* @{
@ -579,6 +589,18 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
/**
* @}
*/
#if defined(USART_CR1_UESM)
/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
* @{
*/
#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */
#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */
#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */
/**
* @}
*/
#endif /* USART_CR1_UESM */
/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
* @{
@ -626,13 +648,20 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
#if defined(USART_ISR_REACK)
#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */
#endif /* USART_ISR_REACK */
#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */
#if defined(USART_CR1_UESM)
#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */
#endif /* USART_CR1_UESM */
#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */
#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */
#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */
#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */
#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */
#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */
#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */
#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */
#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */
#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */
@ -674,6 +703,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */
#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */
#define UART_IT_CM 0x112EU /*!< UART character match interruption */
#if defined(USART_CR1_UESM)
#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */
#endif /* USART_CR1_UESM */
#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */
#define UART_IT_ERR 0x0060U /*!< UART error interruption */
@ -689,13 +722,17 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
*/
#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */
#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */
#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
#if defined(USART_CR1_UESM)
#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */
#endif /* USART_CR1_UESM */
#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */
/**
* @}
*/
@ -734,9 +771,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
*/
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
} while(0U)
SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
} while(0U)
/** @brief Clear the specified UART pending flag.
* @param __HANDLE__ specifies the UART Handle.
@ -748,9 +785,13 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
* @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag
* @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
* @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
* @arg @ref UART_CLEAR_CMF Character Match Clear Flag
#if defined(USART_CR1_UESM)
* @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
#endif
* @retval None
*/
#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
@ -790,7 +831,13 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __HANDLE__ specifies the UART Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
#if defined(USART_ISR_REACK)
* @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
#endif
* @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
#if defined(USART_CR1_UESM)
* @arg @ref UART_FLAG_WUF Wake up from stop mode flag
#endif
* @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode)
* @arg @ref UART_FLAG_SBKF Send Break flag
* @arg @ref UART_FLAG_CMF Character match flag
@ -802,6 +849,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_FLAG_TXE Transmit data register empty flag
* @arg @ref UART_FLAG_TC Transmission Complete flag
* @arg @ref UART_FLAG_RXNE Receive data register not empty flag
* @arg @ref UART_FLAG_RTOF Receiver Timeout flag
* @arg @ref UART_FLAG_IDLE Idle Line detection flag
* @arg @ref UART_FLAG_ORE Overrun Error flag
* @arg @ref UART_FLAG_NE Noise Error flag
@ -815,12 +863,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __HANDLE__ specifies the UART Handle.
* @param __INTERRUPT__ specifies the UART interrupt source to enable.
* This parameter can be one of the following values:
#if defined(USART_CR1_UESM)
* @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
#endif
* @arg @ref UART_IT_CM Character match interrupt
* @arg @ref UART_IT_CTS CTS change interrupt
* @arg @ref UART_IT_LBD LIN Break detection interrupt
* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref UART_IT_TC Transmission complete interrupt
* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref UART_IT_RTO Receive Timeout interrupt
* @arg @ref UART_IT_IDLE Idle line detection interrupt
* @arg @ref UART_IT_PE Parity Error interrupt
* @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error)
@ -835,12 +887,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __HANDLE__ specifies the UART Handle.
* @param __INTERRUPT__ specifies the UART interrupt source to disable.
* This parameter can be one of the following values:
#if defined(USART_CR1_UESM)
* @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
#endif
* @arg @ref UART_IT_CM Character match interrupt
* @arg @ref UART_IT_CTS CTS change interrupt
* @arg @ref UART_IT_LBD LIN Break detection interrupt
* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref UART_IT_TC Transmission complete interrupt
* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref UART_IT_RTO Receive Timeout interrupt
* @arg @ref UART_IT_IDLE Idle line detection interrupt
* @arg @ref UART_IT_PE Parity Error interrupt
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
@ -854,37 +910,46 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __HANDLE__ specifies the UART Handle.
* @param __INTERRUPT__ specifies the UART interrupt to check.
* This parameter can be one of the following values:
#if defined(USART_CR1_UESM)
* @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
#endif
* @arg @ref UART_IT_CM Character match interrupt
* @arg @ref UART_IT_CTS CTS change interrupt
* @arg @ref UART_IT_LBD LIN Break detection interrupt
* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref UART_IT_TC Transmission complete interrupt
* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref UART_IT_RTO Receive Timeout interrupt
* @arg @ref UART_IT_IDLE Idle line detection interrupt
* @arg @ref UART_IT_PE Parity Error interrupt
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
/** @brief Check whether the specified UART interrupt source is enabled or not.
* @param __HANDLE__ specifies the UART Handle.
* @param __INTERRUPT__ specifies the UART interrupt source to check.
* This parameter can be one of the following values:
#if defined(USART_CR1_UESM)
* @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
#endif
* @arg @ref UART_IT_CM Character match interrupt
* @arg @ref UART_IT_CTS CTS change interrupt
* @arg @ref UART_IT_LBD LIN Break detection interrupt
* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref UART_IT_TC Transmission complete interrupt
* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref UART_IT_RTO Receive Timeout interrupt
* @arg @ref UART_IT_IDLE Idle line detection interrupt
* @arg @ref UART_IT_PE Parity Error interrupt
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)
/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the UART Handle.
@ -896,10 +961,14 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
* @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
* @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
* @arg @ref UART_CLEAR_CMF Character Match Clear Flag
#if defined(USART_CR1_UESM)
* @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
#endif
* @retval None
*/
#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
@ -1083,10 +1152,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
*/
#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
(((__CONTROL__) == UART_HWCONTROL_NONE) || \
((__CONTROL__) == UART_HWCONTROL_RTS) || \
((__CONTROL__) == UART_HWCONTROL_CTS) || \
((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
(((__CONTROL__) == UART_HWCONTROL_NONE) || \
((__CONTROL__) == UART_HWCONTROL_RTS) || \
((__CONTROL__) == UART_HWCONTROL_CTS) || \
((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
/**
* @brief Ensure that UART communication mode is valid.
@ -1134,8 +1203,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __TIMEOUT__ UART receiver timeout setting.
* @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
*/
#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
/** @brief Check the receiver timeout value.
* @note The maximum UART receiver timeout value is 0xFFFFFF.
* @param __TIMEOUTVALUE__ receiver timeout value.
* @retval Test result (TRUE or FALSE)
*/
#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
/**
* @brief Ensure that UART LIN state is valid.
@ -1275,6 +1351,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
#if defined(USART_CR1_UESM)
/**
* @brief Ensure that UART stop mode state is valid.
* @param __STOPMODE__ UART stop mode state.
* @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
*/
#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
#endif /* USART_CR1_UESM */
/**
* @brief Ensure that UART mute mode state is valid.
* @param __MUTE__ UART mute mode state.
@ -1282,6 +1368,17 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
*/
#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
#if defined(USART_CR1_UESM)
/**
* @brief Ensure that UART wake-up selection is valid.
* @param __WAKE__ UART wake-up selection.
* @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
*/
#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
#endif /* USART_CR1_UESM */
/**
* @brief Ensure that UART driver enable polarity is valid.
@ -1320,7 +1417,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@ -1369,6 +1467,10 @@ void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
*/
/* Peripheral Control functions ************************************************/
void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
@ -1405,7 +1507,8 @@ void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
/**

162
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_uart_ex.h
View File

@ -41,7 +41,24 @@ extern "C" {
* @{
*/
#if defined(USART_CR1_UESM)
/**
* @brief UART wake up from stop mode parameters
*/
typedef struct
{
uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
be filled up. */
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
uint8_t Address; /*!< UART/USART node address (7-bit long max). */
} UART_WakeUpTypeDef;
#endif /* USART_CR1_UESM */
/**
* @}
*/
@ -54,9 +71,9 @@ extern "C" {
/** @defgroup UARTEx_Word_Length UARTEx Word Length
* @{
*/
#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
/**
* @}
*/
@ -64,13 +81,12 @@ extern "C" {
/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
* @{
*/
#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
/**
* @}
*/
/**
* @}
*/
@ -86,7 +102,8 @@ extern "C" {
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
uint32_t DeassertionTime);
/**
* @}
@ -96,6 +113,10 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
* @{
*/
#if defined(USART_CR1_UESM)
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
#endif /* USART_CR1_UESM */
/**
* @}
@ -106,8 +127,20 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
*/
/* Peripheral Control functions **********************************************/
#if defined(USART_CR1_UESM)
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
#endif/* USART_CR1_UESM */
#if defined(USART_CR3_UCESM)
HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart);
#endif /* USART_CR3_UCESM */
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
/**
* @}
*/
@ -126,12 +159,12 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua
* @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
@ -147,12 +180,12 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@ -168,12 +201,12 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@ -189,12 +222,12 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@ -210,12 +243,12 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if ((__HANDLE__)->Instance == UART5) \
{ \
switch(__HAL_RCC_GET_UART5_SOURCE()) \
{ \
switch(__HAL_RCC_GET_UART5_SOURCE()) \
{ \
case RCC_UART5CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@ -231,12 +264,12 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
switch(__HAL_RCC_GET_USART6_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART6_SOURCE()) \
{ \
case RCC_USART6CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
@ -252,12 +285,12 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if ((__HANDLE__)->Instance == UART7) \
{ \
switch(__HAL_RCC_GET_UART7_SOURCE()) \
{ \
switch(__HAL_RCC_GET_UART7_SOURCE()) \
{ \
case RCC_UART7CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@ -273,12 +306,12 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if ((__HANDLE__)->Instance == UART8) \
{ \
switch(__HAL_RCC_GET_UART8_SOURCE()) \
{ \
switch(__HAL_RCC_GET_UART8_SOURCE()) \
{ \
case RCC_UART8CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@ -294,7 +327,7 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else \
{ \
@ -313,44 +346,44 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua
*/
#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU ; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
/**
* @brief Ensure that UART frame length is valid.
@ -369,7 +402,6 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
/**
* @}
*/

61
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_usart.h
View File

@ -209,6 +209,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
#define HAL_USART_ERROR_RTO ((uint32_t)0x00000080U) /*!< Receiver Timeout error */
/**
* @}
*/
@ -304,9 +305,11 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */
#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */
#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */
#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */
#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */
#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */
#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */
@ -348,10 +351,11 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
*/
#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */
/**
* @}
*/
@ -383,10 +387,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
*/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_USART_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
(__HANDLE__)->State = HAL_USART_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
@ -395,11 +399,13 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @param __HANDLE__ specifies the USART Handle
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
* @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
* @arg @ref USART_FLAG_BUSY Busy flag
* @arg @ref USART_FLAG_TXE Transmit data register empty flag
* @arg @ref USART_FLAG_TC Transmission Complete flag
* @arg @ref USART_FLAG_RXNE Receive data register not empty flag
* @arg @ref USART_FLAG_RTOF Receiver Timeout flag
* @arg @ref USART_FLAG_IDLE Idle Line detection flag
* @arg @ref USART_FLAG_ORE OverRun Error flag
* @arg @ref USART_FLAG_NE Noise Error flag
@ -419,6 +425,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag
* @retval None
*/
#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
@ -502,7 +509,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified USART interrupt source is enabled or not.
* @param __HANDLE__ specifies the USART Handle.
@ -519,8 +527,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \
(((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET)
(((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
@ -533,6 +541,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @retval None
*/
@ -598,8 +607,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
break; \
@ -615,12 +624,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
@ -636,12 +645,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
@ -657,12 +666,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
switch(__HAL_RCC_GET_USART6_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART6_SOURCE()) \
{ \
case RCC_USART6CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
break; \
@ -678,7 +687,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else \
{ \
@ -789,7 +798,8 @@ void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
pUSART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
@ -804,13 +814,16 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);

68
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_usart_ex.h
View File

@ -46,14 +46,13 @@ extern "C" {
* @{
*/
#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
/**
* @}
*/
/**
* @}
*/
@ -74,45 +73,44 @@ extern "C" {
*/
#define USART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
/**
* @brief Ensure that USART frame length is valid.

11
stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_wwdg.h
View File

@ -22,7 +22,7 @@
#define STM32F7xx_HAL_WWDG_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@ -89,12 +89,12 @@ typedef enum
{
HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
}HAL_WWDG_CallbackIDTypeDef;
} HAL_WWDG_CallbackIDTypeDef;
/**
* @brief HAL WWDG Callback pointer definition
*/
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer to a WWDG common callback functions */
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
#endif
/**
@ -239,7 +239,8 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer t
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
* @retval state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
& (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @}
@ -294,6 +295,6 @@ void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
}
#endif
#endif /* __STM32F7xx_HAL_WWDG_H */
#endif /* STM32F7xx_HAL_WWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

6
stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_adc.h
View File

@ -255,11 +255,11 @@ extern "C" {
#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
/* ADC internal channels related definitions */
/* Internal voltage reference VrefInt */
#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF0F44A)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define VREFINT_CAL_ADDR VREFINT_CAL_ADDR_CMSIS /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
/* Temperature sensor */
#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF0F44C)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF0F44E)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_ADDR TEMPSENSOR_CAL1_ADDR_CMSIS /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR TEMPSENSOR_CAL2_ADDR_CMSIS /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */

12
stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_fmc.h
View File

@ -77,21 +77,21 @@
((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \
((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \
((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \
((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \
((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \
((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
@ -106,8 +106,8 @@
#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \
((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \
((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
/** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time
* @{
*/

177
stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_lptim.h
View File

@ -18,8 +18,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_LL_LPTIM_H
#define __STM32F7xx_LL_LPTIM_H
#ifndef STM32F7xx_LL_LPTIM_H
#define STM32F7xx_LL_LPTIM_H
#ifdef __cplusplus
extern "C" {
@ -31,8 +31,9 @@ extern "C" {
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
#if defined (LPTIM1)
/** @defgroup LPTIM_LL LPTIM
* @{
*/
@ -127,8 +128,8 @@ typedef struct
/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
* @{
*/
#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
#define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
#define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
/**
* @}
*/
@ -136,8 +137,8 @@ typedef struct
/** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
* @{
*/
#define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
#define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
/**
* @}
*/
@ -145,8 +146,8 @@ typedef struct
/** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
* @{
*/
#define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
#define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
#define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
#define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
/**
* @}
*/
@ -154,8 +155,8 @@ typedef struct
/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
* @{
*/
#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
/**
* @}
*/
@ -163,8 +164,8 @@ typedef struct
/** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
* @{
*/
#define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
#define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
#define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
#define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
/**
* @}
*/
@ -187,14 +188,14 @@ typedef struct
/** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
* @{
*/
#define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
#define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
#define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
#define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
#define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
#define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
#define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
#define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
#define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
#define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
/**
* @}
*/
@ -202,10 +203,10 @@ typedef struct
/** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
* @{
*/
#define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
#define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
#define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
#define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
#define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
#define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
#define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
#define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
/**
* @}
*/
@ -213,9 +214,9 @@ typedef struct
/** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
* @{
*/
#define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
#define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
#define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
#define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
/**
* @}
*/
@ -223,8 +224,8 @@ typedef struct
/** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
* @{
*/
#define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
#define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
#define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
#define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
/**
* @}
*/
@ -232,10 +233,10 @@ typedef struct
/** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
* @{
*/
#define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
#define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
#define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
#define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
#define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
#define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
/**
* @}
*/
@ -243,9 +244,9 @@ typedef struct
/** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
* @{
*/
#define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
#define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
#define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
#define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
#define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
#define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
/**
* @}
*/
@ -253,14 +254,13 @@ typedef struct
/** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
* @{
*/
#define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
#define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
#define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
#define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
#define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
#define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
/**
* @}
*/
/**
* @}
*/
@ -281,7 +281,7 @@ typedef struct
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in LPTIM register
@ -289,7 +289,7 @@ typedef struct
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
@ -298,12 +298,25 @@ typedef struct
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
* @{
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
* @{
*/
ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
* @{
*/
@ -321,17 +334,6 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
}
/**
* @brief Disable the LPTIM instance
* @rmtoll CR ENABLE LL_LPTIM_Disable
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
}
/**
* @brief Indicates whether the LPTIM instance is enabled.
* @rmtoll CR ENABLE LL_LPTIM_IsEnabled
@ -340,7 +342,7 @@ __STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
{
return (READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == (LPTIM_CR_ENABLE));
return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
}
/**
@ -361,7 +363,6 @@ __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t Opera
MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
}
/**
* @brief Set the LPTIM registers update mode (enable/disable register preload)
* @note This function must be called when the LPTIM instance is disabled.
@ -395,7 +396,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
* @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
* @note After a write to the LPTIMx_ARR register a new write operation to the
* same register can only be performed when the previous write operation
* is completed. Any successive write before the ARROK flag be set, will
* is completed. Any successive write before the ARROK flag is set, will
* lead to unpredictable results.
* @note autoreload value be strictly greater than the compare value.
* @rmtoll ARR ARR LL_LPTIM_SetAutoReload
@ -423,7 +424,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
* @brief Set the compare value
* @note After a write to the LPTIMx_CMP register a new write operation to the
* same register can only be performed when the previous write operation
* is completed. Any successive write before the CMPOK flag be set, will
* is completed. Any successive write before the CMPOK flag is set, will
* lead to unpredictable results.
* @rmtoll CMP CMP LL_LPTIM_SetCompare
* @param LPTIMx Low-Power Timer instance
@ -609,7 +610,6 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
}
/**
* @}
*/
@ -657,7 +657,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
{
return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == (LPTIM_CFGR_TIMOUT));
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
}
/**
@ -920,7 +920,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
{
return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == (LPTIM_CFGR_ENC));
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
}
/**
@ -950,7 +950,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
{
return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == (LPTIM_ISR_CMPM));
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
}
/**
@ -972,7 +972,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
{
return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == (LPTIM_ISR_ARRM));
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
}
/**
@ -994,7 +994,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == (LPTIM_ISR_EXTTRIG));
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
}
/**
@ -1009,14 +1009,14 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
}
/**
* @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed; If so, a new one can be initiated.
* @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.
* @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
{
return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == (LPTIM_ISR_CMPOK));
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
}
/**
@ -1031,14 +1031,14 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
}
/**
* @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed; If so, a new one can be initiated.
* @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.
* @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
{
return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == (LPTIM_ISR_ARROK));
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
}
/**
@ -1060,7 +1060,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
{
return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == (LPTIM_ISR_UP));
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
}
/**
@ -1082,7 +1082,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
{
return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == (LPTIM_ISR_DOWN));
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
}
/**
@ -1123,7 +1123,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
{
return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == (LPTIM_IER_CMPMIE));
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
}
/**
@ -1156,7 +1156,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
{
return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == (LPTIM_IER_ARRMIE));
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
}
/**
@ -1189,7 +1189,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
return (READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == (LPTIM_IER_EXTTRIGIE));
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
}
/**
@ -1222,7 +1222,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
{
return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == (LPTIM_IER_CMPOKIE));
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
}
/**
@ -1251,11 +1251,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
* @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
* @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
{
return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == (LPTIM_IER_ARROKIE));
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
}
/**
@ -1284,11 +1284,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
* @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
* @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
{
return (READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == (LPTIM_IER_UPIE));
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
}
/**
@ -1317,30 +1317,17 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
* @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
* @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
{
return (READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == (LPTIM_IER_DOWNIE));
return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
* @{
*/
ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
@ -1359,6 +1346,6 @@ ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_Ini
}
#endif
#endif /* __STM32F7xx_LL_LPTIM_H */
#endif /* STM32F7xx_LL_LPTIM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

531
stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_sdmmc.h
View File

@ -12,19 +12,21 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_LL_SDMMC_H
#define __STM32F7xx_LL_SDMMC_H
#ifndef STM32F7xx_LL_SDMMC_H
#define STM32F7xx_LL_SDMMC_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(SDMMC1)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
@ -127,205 +129,206 @@ typedef struct
/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
* @{
*/
#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */
#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */
#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */
#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */
#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */
#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */
#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */
#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
#define SDMMC_ERROR_NONE 0x00000000U /*!< No error */
#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */
#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */
#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */
#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */
#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */
#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */
#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */
#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
number of transferred bytes does not match the block length */
#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */
#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */
#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */
#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */
#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */
#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */
#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
command or if there was an attempt to access a locked card */
#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */
#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */
#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */
#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */
#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */
#define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */
#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */
#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */
#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */
#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */
#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */
#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */
#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */
#define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */
#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */
#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */
#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */
#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */
#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */
#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */
#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
of erase sequence command was received */
#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */
#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */
#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */
#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */
#define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */
#define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */
#define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */
#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */
#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */
#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */
#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */
#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */
#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */
#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */
#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */
#define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */
#define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */
#define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */
/**
* @brief SDMMC Commands Index
*/
#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */
#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */
#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
operating condition register (OCR) content in the response on the CMD line. */
#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
and asks the card whether card supports voltage. */
#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */
#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */
#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */
#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */
#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */
#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */
#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */
#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
operating condition register (OCR) content in the response on the CMD line. */
#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */
#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
and asks the card whether card supports voltage. */
#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */
#define SDMMC_CMD_READ_DAT_UNTIL_STOP 11U /*!< SD card doesn't support it. */
#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */
#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */
#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */
#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */
#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands
(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
for SDHS and SDXC. */
#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
fixed 512 bytes in case of SDHC and SDXC. */
#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by
STOP_TRANSMISSION command. */
#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */
#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */
#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
fixed 512 bytes in case of SDHC and SDXC. */
#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */
#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */
#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */
#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */
#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */
#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */
#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */
#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */
#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */
#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command
system set by switch function command (CMD6). */
#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased.
Reserved for each command system set by switch function command (CMD6). */
#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */
#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */
#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */
#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
the SET_BLOCK_LEN command. */
#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather
than a standard command. */
#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card
for general purpose/application specific commands. */
#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */
#define SDMMC_CMD_NO_CMD 64U /*!< No command */
/**
* @brief Following commands are SD Card Specific commands.
* SDMMC_APP_CMD should be sent before sending these commands.
*/
#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
widths are given in SCR register. */
#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */
#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
32bit+CRC data block. */
#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
send its operating condition register (OCR) content in the response on the CMD line. */
#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */
#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */
#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */
/**
* @brief Following commands are SD Card Specific security commands.
* SDMMC_CMD_APP_CMD should be sent before sending these commands.
*/
#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
#define SDMMC_CMD_SD_APP_GET_MKB 43U
#define SDMMC_CMD_SD_APP_GET_MID 44U
#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U
#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U
#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U
#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U
#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U
#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U
#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U
#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U
#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U
/**
* @brief Masks for errors Card Status R1 (OCR Register)
*/
#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
#define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
#define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
#define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
#define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
#define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
#define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
#define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
#define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
#define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
#define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
#define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
#define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
#define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
#define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
#define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
#define SDMMC_OCR_CC_ERROR 0x00100000U
#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
#define SDMMC_OCR_ERASE_RESET 0x00002000U
#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
#define SDMMC_OCR_ERRORBITS 0xFDFFE008U
/**
* @brief Masks for R6 Response
*/
#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
#define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
#define SDMMC_R6_ILLEGAL_CMD 0x00004000U
#define SDMMC_R6_COM_CRC_FAILED 0x00008000U
#define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
#define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
#define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
#define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
#define SDMMC_HIGH_CAPACITY 0x40000000U
#define SDMMC_STD_CAPACITY 0x00000000U
#define SDMMC_CHECK_PATTERN 0x000001AAU
#define SD_SWITCH_1_8V_CAPACITY 0x01000000U
#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
#define SDMMC_MAX_TRIAL 0x0000FFFFU
#define SDMMC_ALLZERO ((uint32_t)0x00000000U)
#define SDMMC_ALLZERO 0x00000000U
#define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
#define SDMMC_CARD_LOCKED 0x02000000U
#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
#define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
#define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
#define SDMMC_0TO7BITS 0x000000FFU
#define SDMMC_8TO15BITS 0x0000FF00U
#define SDMMC_16TO23BITS 0x00FF0000U
#define SDMMC_24TO31BITS 0xFF000000U
#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
#define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
#define SDMMC_HALFFIFO 0x00000008U
#define SDMMC_HALFFIFOBYTES 0x00000020U
/**
* @brief Command Class supported
*/
#define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
#define SDMMC_CCCC_ERASE 0x00000020U
#define SDMMC_CMDTIMEOUT 5000U /* Command send and response timeout */
#define SDMMC_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
#define SDMMC_STOPTRANSFERTIMEOUT 100000000U /* Timeout for STOP TRANSMISSION command */
/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
* @{
*/
#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
#define SDMMC_CLOCK_EDGE_RISING 0x00000000U
#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
/**
* @}
*/
@ -333,11 +336,11 @@ typedef struct
/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
* @{
*/
#define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U)
#define SDMMC_CLOCK_BYPASS_DISABLE 0x00000000U
#define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \
((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
/**
* @}
*/
@ -345,11 +348,11 @@ typedef struct
/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
* @{
*/
#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
#define SDMMC_CLOCK_POWER_SAVE_DISABLE 0x00000000U
#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
/**
* @}
*/
@ -357,13 +360,13 @@ typedef struct
/** @defgroup SDMMC_LL_Bus_Wide Bus Width
* @{
*/
#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U)
#define SDMMC_BUS_WIDE_1B 0x00000000U
#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
((WIDE) == SDMMC_BUS_WIDE_4B) || \
((WIDE) == SDMMC_BUS_WIDE_8B))
((WIDE) == SDMMC_BUS_WIDE_4B) || \
((WIDE) == SDMMC_BUS_WIDE_8B))
/**
* @}
*/
@ -371,11 +374,11 @@ typedef struct
/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
* @{
*/
#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U
#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
/**
* @}
*/
@ -383,7 +386,7 @@ typedef struct
/** @defgroup SDMMC_LL_Clock_Division Clock Division
* @{
*/
#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF)
#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFFU)
/**
* @}
*/
@ -391,7 +394,7 @@ typedef struct
/** @defgroup SDMMC_LL_Command_Index Command Index
* @{
*/
#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40)
#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
/**
* @}
*/
@ -399,13 +402,13 @@ typedef struct
/** @defgroup SDMMC_LL_Response_Type Response Type
* @{
*/
#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U)
#define SDMMC_RESPONSE_NO 0x00000000U
#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \
((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
((RESPONSE) == SDMMC_RESPONSE_LONG))
((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
((RESPONSE) == SDMMC_RESPONSE_LONG))
/**
* @}
*/
@ -413,13 +416,13 @@ typedef struct
/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
* @{
*/
#define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
#define SDMMC_WAIT_NO 0x00000000U
#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
((WAIT) == SDMMC_WAIT_IT) || \
((WAIT) == SDMMC_WAIT_PEND))
((WAIT) == SDMMC_WAIT_IT) || \
((WAIT) == SDMMC_WAIT_PEND))
/**
* @}
*/
@ -427,11 +430,11 @@ typedef struct
/** @defgroup SDMMC_LL_CPSM_State CPSM State
* @{
*/
#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U)
#define SDMMC_CPSM_DISABLE 0x00000000U
#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
((CPSM) == SDMMC_CPSM_ENABLE))
((CPSM) == SDMMC_CPSM_ENABLE))
/**
* @}
*/
@ -439,15 +442,15 @@ typedef struct
/** @defgroup SDMMC_LL_Response_Registers Response Register
* @{
*/
#define SDMMC_RESP1 ((uint32_t)0x00000000U)
#define SDMMC_RESP2 ((uint32_t)0x00000004U)
#define SDMMC_RESP3 ((uint32_t)0x00000008U)
#define SDMMC_RESP4 ((uint32_t)0x0000000C)
#define SDMMC_RESP1 0x00000000U
#define SDMMC_RESP2 0x00000004U
#define SDMMC_RESP3 0x00000008U
#define SDMMC_RESP4 0x0000000CU
#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
((RESP) == SDMMC_RESP2) || \
((RESP) == SDMMC_RESP3) || \
((RESP) == SDMMC_RESP4))
((RESP) == SDMMC_RESP2) || \
((RESP) == SDMMC_RESP3) || \
((RESP) == SDMMC_RESP4))
/**
* @}
*/
@ -455,7 +458,7 @@ typedef struct
/** @defgroup SDMMC_LL_Data_Length Data Lenght
* @{
*/
#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
/**
* @}
*/
@ -463,7 +466,7 @@ typedef struct
/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
* @{
*/
#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
#define SDMMC_DATABLOCK_SIZE_1B 0x00000000U
#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
@ -480,20 +483,20 @@ typedef struct
#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
/**
* @}
*/
@ -501,11 +504,11 @@ typedef struct
/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
* @{
*/
#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
#define SDMMC_TRANSFER_DIR_TO_CARD 0x00000000U
#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
/**
* @}
*/
@ -513,11 +516,11 @@ typedef struct
/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
* @{
*/
#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
#define SDMMC_TRANSFER_MODE_BLOCK 0x00000000U
#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
((MODE) == SDMMC_TRANSFER_MODE_STREAM))
((MODE) == SDMMC_TRANSFER_MODE_STREAM))
/**
* @}
*/
@ -525,11 +528,11 @@ typedef struct
/** @defgroup SDMMC_LL_DPSM_State DPSM State
* @{
*/
#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U)
#define SDMMC_DPSM_DISABLE 0x00000000U
#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
((DPSM) == SDMMC_DPSM_ENABLE))
((DPSM) == SDMMC_DPSM_ENABLE))
/**
* @}
*/
@ -537,11 +540,11 @@ typedef struct
/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
* @{
*/
#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
#define SDMMC_READ_WAIT_MODE_DATA2 0x00000000U
#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
/**
* @}
*/
@ -549,28 +552,28 @@ typedef struct
/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
* @{
*/
#define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL
#define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL
#define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT
#define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT
#define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR
#define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR
#define SDMMC_IT_CMDREND SDMMC_STA_CMDREND
#define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT
#define SDMMC_IT_DATAEND SDMMC_STA_DATAEND
#define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND
#define SDMMC_IT_CMDACT SDMMC_STA_CMDACT
#define SDMMC_IT_TXACT SDMMC_STA_TXACT
#define SDMMC_IT_RXACT SDMMC_STA_RXACT
#define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE
#define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF
#define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF
#define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF
#define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE
#define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE
#define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL
#define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL
#define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT
#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE
#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE
#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE
#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE
#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE
#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE
#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE
#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE
#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE
#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE
#define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE
#define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE
#define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE
#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE
#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE
#define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE
#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE
#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE
#define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE
#define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE
#define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE
#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE
/**
* @}
*/
@ -603,7 +606,13 @@ typedef struct
#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
SDMMC_FLAG_DBCKEND))
SDMMC_FLAG_DBCKEND | SDMMC_FLAG_SDIOIT))
#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\
SDMMC_FLAG_CMDSENT))
#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\
SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DBCKEND))
/**
* @}
*/
@ -640,11 +649,10 @@ typedef struct
SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND))
/* SDMMC Initialization Frequency (400KHz max) */
#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
/* SDMMC Data Transfer Frequency (25MHz max) */
#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */
/**
* @}
*/
@ -656,35 +664,36 @@ typedef struct
/**
* @brief Enable the SDMMC device.
* @param __INSTANCE__ SDMMC Instance
* @param __INSTANCE__: SDMMC Instance
* @retval None
*/
#define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)
/**
* @brief Disable the SDMMC device.
* @param __INSTANCE__ SDMMC Instance
* @param __INSTANCE__: SDMMC Instance
* @retval None
*/
#define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
/**
* @brief Enable the SDMMC DMA transfer.
* @param __INSTANCE__ SDMMC Instance
* @param __INSTANCE__: SDMMC Instance
* @retval None
*/
#define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)
/**
* @brief Disable the SDMMC DMA transfer.
* @param __INSTANCE__ SDMMC Instance
* @param __INSTANCE__: SDMMC Instance
* @retval None
*/
#define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
/**
* @brief Enable the SDMMC device interrupt.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
* @param __INSTANCE__ : Pointer to SDMMC register base
* @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@ -694,7 +703,7 @@ typedef struct
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@ -707,15 +716,15 @@ typedef struct
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
/**
* @brief Disable the SDMMC device interrupt.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
* @param __INSTANCE__ : Pointer to SDMMC register base
* @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@ -725,7 +734,7 @@ typedef struct
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@ -738,15 +747,15 @@ typedef struct
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified SDMMC flag is set or not.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __FLAG__ specifies the flag to check.
* @param __INSTANCE__ : Pointer to SDMMC register base
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@ -756,7 +765,7 @@ typedef struct
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
* @arg SDMMC_FLAG_TXACT: Data transmit in progress
@ -769,16 +778,16 @@ typedef struct
* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
* @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
* @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
* @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
* @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
* @retval The new state of SDMMC_FLAG (SET or RESET).
*/
#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
/**
* @brief Clears the SDMMC pending flags.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __FLAG__ specifies the flag to clear.
* @param __INSTANCE__ : Pointer to SDMMC register base
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@ -788,17 +797,17 @@ typedef struct
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
* @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
* @retval None
*/
#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
/**
* @brief Checks whether the specified SDMMC interrupt has occurred or not.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
* @param __INSTANCE__ : Pointer to SDMMC register base
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@ -808,7 +817,7 @@ typedef struct
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@ -821,15 +830,15 @@ typedef struct
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @retval The new state of SDMMC_IT (SET or RESET).
*/
#define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Clears the SDMMC's interrupt pending bits.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* @param __INSTANCE__ : Pointer to SDMMC register base
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@ -839,64 +848,64 @@ typedef struct
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
/**
* @brief Enable Start the SD I/O Read Wait operation.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
/**
* @brief Disable Start the SD I/O Read Wait operations.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
/**
* @brief Enable Start the SD I/O Read Wait operation.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
/**
* @brief Disable Stop the SD I/O Read Wait operations.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
/**
* @brief Enable the SD I/O Mode Operation.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
/**
* @brief Disable the SD I/O Mode Operation.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
/**
* @brief Enable the SD I/O Suspend command sending.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND)
/**
* @brief Disable the SD I/O Suspend command sending.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
@ -970,7 +979,7 @@ uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType);
uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
@ -997,10 +1006,12 @@ uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
* @}
*/
#endif /* SDMMC1 */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F7xx_LL_SDMMC_H */
#endif /* STM32F7xx_LL_SDMMC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

246
stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_tim.h
View File

@ -121,17 +121,7 @@ static const uint8_t SHIFT_TAB_OISx[] =
#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
/* Generic bit definitions for TIMx_AF1 register */
#define TIMx_AF1_BKINE TIM1_AF1_BKINE /*!< BRK BKINE input enable */
#if defined(DFSDM1_Channel0)
#define TIMx_AF1_BKDFBKE TIM1_AF1_BKDFBKE /*!< BRK DFSDM1_BREAK[0] enable */
#endif /* DFSDM1_Channel0 */
#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
/* Generic bit definitions for TIMx_AF2 register */
#define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /*!< BRK B2KINE input enable */
#if defined(DFSDM1_Channel0)
#define TIMx_AF2_BK2DFBKE TIM1_AF2_BK2DFBKE /*!< BRK DFSDM_BREAK[0] enable */
#endif /* DFSDM1_Channel0 */
#define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /*!< BRK BK2IN input polarity */
#endif /* TIM_BREAK_INPUT_SUPPORT */
/* Remap mask definitions */
@ -176,14 +166,14 @@ static const uint8_t SHIFT_TAB_OISx[] =
* @retval none
*/
#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
/** @brief Calculate the deadtime sampling period(in ps).
* @param __TIMCLK__ timer input clock frequency (in Hz).
@ -194,9 +184,9 @@ static const uint8_t SHIFT_TAB_OISx[] =
* @retval none
*/
#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
/**
* @}
*/
@ -235,13 +225,14 @@ typedef struct
This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
This parameter must be a number between 0x00 and 0xFF.
GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
} LL_TIM_InitTypeDef;
@ -1157,7 +1148,7 @@ typedef struct
* @retval UIF status bit
*/
#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
(READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
(READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
/**
* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
@ -1171,11 +1162,11 @@ typedef struct
* @retval DTG[0:7]
*/
#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
(((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
(((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
(((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
0U)
( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
(((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
(((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
(((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
0U)
/**
* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
@ -1185,7 +1176,7 @@ typedef struct
* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
(((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
(((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
@ -1196,7 +1187,7 @@ typedef struct
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
/**
* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
@ -1207,8 +1198,8 @@ typedef struct
* @retval Compare value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
@ -1220,8 +1211,8 @@ typedef struct
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
/**
* @brief HELPER macro retrieving the ratio of the input capture prescaler
@ -1234,7 +1225,7 @@ typedef struct
* @retval Input capture prescaler ratio (1, 2, 4 or 8)
*/
#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
/**
@ -1383,7 +1374,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
/**
* @brief Set the timer counter counting mode.
* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
@ -1407,7 +1398,7 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo
/**
* @brief Get actual counter mode.
* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
@ -1444,7 +1435,7 @@ __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->CR1,TIM_CR1_ARPE);
CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
}
/**
@ -1460,7 +1451,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
/**
* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_SetClockDivision
@ -1478,7 +1469,7 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi
/**
* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_GetClockDivision
@ -1495,7 +1486,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
/**
* @brief Set the counter value.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @rmtoll CNT CNT LL_TIM_SetCounter
* @param TIMx Timer instance
@ -1509,7 +1500,7 @@ __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
/**
* @brief Get the counter value.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @rmtoll CNT CNT LL_TIM_GetCounter
* @param TIMx Timer instance
@ -1563,7 +1554,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
/**
* @brief Set the auto-reload value.
* @note The counter is blocked while the auto-reload value is null.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
* @rmtoll ARR ARR LL_TIM_SetAutoReload
@ -1579,7 +1570,7 @@ __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload
/**
* @brief Get the auto-reload value.
* @rmtoll ARR ARR LL_TIM_GetAutoReload
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @param TIMx Timer instance
* @retval Auto-reload value
@ -1592,11 +1583,11 @@ __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
/**
* @brief Set the repetition counter value.
* @note For advanced timer instances RepetitionCounter can be up to 65535.
* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
* @param TIMx Timer instance
* @param RepetitionCounter between Min_Data=0 and Max_Data=255
* @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
@ -1606,7 +1597,7 @@ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t Rep
/**
* @brief Get the repetition counter value.
* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
* @param TIMx Timer instance
@ -1640,6 +1631,16 @@ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
}
/**
* @brief Indicate whether update interrupt flag (UIF) copy is set.
* @param Counter Counter value
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
{
return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
}
/**
* @}
*/
@ -1652,7 +1653,7 @@ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
* they are updated only when a commutation event (COM) occurs.
* @note Only on channels that have a complementary output.
* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
* @param TIMx Timer instance
@ -1665,7 +1666,7 @@ __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
/**
* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
* @param TIMx Timer instance
@ -1678,7 +1679,7 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
/**
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
* @param TIMx Timer instance
@ -1722,7 +1723,7 @@ __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
/**
* @brief Set the lock level to freeze the
* configuration of several capture/compare parameters.
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* the lock mechanism is supported by a timer instance.
* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
* @param TIMx Timer instance
@ -2024,7 +2025,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann
/**
* @brief Set the IDLE state of an output channel
* @note This function is significant only for the timer instances
* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
* supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
* can be used to check whether or not a timer instance provides
* a break input.
* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
@ -2248,7 +2249,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t
/**
* @brief Enable clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
@ -2275,7 +2276,7 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
/**
* @brief Disable clearing the output channel on an external event.
* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
@ -2304,7 +2305,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
* @note This function enables clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
@ -2332,7 +2333,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Ch
/**
* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* dead-time insertion feature is supported by a timer instance.
* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
@ -2348,9 +2349,9 @@ __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
/**
* @brief Set compare value for output channel 1 (TIMx_CCR1).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
* @param TIMx Timer instance
@ -2365,9 +2366,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t Compare
/**
* @brief Set compare value for output channel 2 (TIMx_CCR2).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
* @param TIMx Timer instance
@ -2382,9 +2383,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t Compare
/**
* @brief Set compare value for output channel 3 (TIMx_CCR3).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
* @param TIMx Timer instance
@ -2399,9 +2400,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t Compare
/**
* @brief Set compare value for output channel 4 (TIMx_CCR4).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
* @param TIMx Timer instance
@ -2415,7 +2416,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t Compare
/**
* @brief Set compare value for output channel 5 (TIMx_CCR5).
* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
* output channel 5 is supported by a timer instance.
* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
* @param TIMx Timer instance
@ -2429,7 +2430,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t Compare
/**
* @brief Set compare value for output channel 6 (TIMx_CCR6).
* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
* output channel 6 is supported by a timer instance.
* @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
* @param TIMx Timer instance
@ -2444,9 +2445,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t Compare
/**
* @brief Get compare value (TIMx_CCR1) set for output channel 1.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
* @param TIMx Timer instance
@ -2460,9 +2461,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
/**
* @brief Get compare value (TIMx_CCR2) set for output channel 2.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
* @param TIMx Timer instance
@ -2476,9 +2477,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
/**
* @brief Get compare value (TIMx_CCR3) set for output channel 3.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel 3 is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
* @param TIMx Timer instance
@ -2492,9 +2493,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
/**
* @brief Get compare value (TIMx_CCR4) set for output channel 4.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
* @param TIMx Timer instance
@ -2507,7 +2508,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
/**
* @brief Get compare value (TIMx_CCR5) set for output channel 5.
* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
* output channel 5 is supported by a timer instance.
* @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
* @param TIMx Timer instance
@ -2520,7 +2521,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
/**
* @brief Get compare value (TIMx_CCR6) set for output channel 6.
* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
* output channel 6 is supported by a timer instance.
* @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
* @param TIMx Timer instance
@ -2533,7 +2534,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
/**
* @brief Select on which reference signal the OC5REF is combined to.
* @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the combined 3-phase PWM mode.
* @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
@ -2837,7 +2838,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann
/**
* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
* @param TIMx Timer instance
@ -2850,7 +2851,7 @@ __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
/**
* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
* @param TIMx Timer instance
@ -2863,7 +2864,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
/**
* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
* @param TIMx Timer instance
@ -2877,9 +2878,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
/**
* @brief Get captured value for input channel 1.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* input channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
* @param TIMx Timer instance
@ -2893,9 +2894,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
/**
* @brief Get captured value for input channel 2.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* input channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
* @param TIMx Timer instance
@ -2909,9 +2910,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
/**
* @brief Get captured value for input channel 3.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* input channel 3 is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
* @param TIMx Timer instance
@ -2925,9 +2926,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
/**
* @brief Get captured value for input channel 4.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* input channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
* @param TIMx Timer instance
@ -2948,7 +2949,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
/**
* @brief Enable external clock mode 2.
* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
* @param TIMx Timer instance
@ -2961,7 +2962,7 @@ __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
/**
* @brief Disable external clock mode 2.
* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
* @param TIMx Timer instance
@ -2974,7 +2975,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
/**
* @brief Indicate whether external clock mode 2 is enabled.
* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
* @param TIMx Timer instance
@ -2991,9 +2992,9 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
* function. This timer input must be configured by calling
* the @ref LL_TIM_IC_Config() function.
* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode1.
* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
* SMCR ECE LL_TIM_SetClockSource
@ -3011,7 +3012,7 @@ __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSour
/**
* @brief Set the encoder interface mode.
* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the encoder mode.
* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
* @param TIMx Timer instance
@ -3035,7 +3036,7 @@ __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMo
*/
/**
* @brief Set the trigger output (TRGO) used for timer synchronization .
* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance can operate as a master timer.
* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
* @param TIMx Timer instance
@ -3057,7 +3058,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSy
/**
* @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
* @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance can be used for ADC synchronization.
* @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
* @param TIMx Timer Instance
@ -3087,7 +3088,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSyn
/**
* @brief Set the synchronization mode of a slave timer.
* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
* @param TIMx Timer instance
@ -3106,7 +3107,7 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
/**
* @brief Set the selects the trigger input to be used to synchronize the counter.
* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR TS LL_TIM_SetTriggerInput
* @param TIMx Timer instance
@ -3128,7 +3129,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerI
/**
* @brief Enable the Master/Slave mode.
* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
* @param TIMx Timer instance
@ -3141,7 +3142,7 @@ __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
/**
* @brief Disable the Master/Slave mode.
* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
* @param TIMx Timer instance
@ -3154,7 +3155,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
/**
* @brief Indicates whether the Master/Slave mode is enabled.
* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
* @param TIMx Timer instance
@ -3167,7 +3168,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
/**
* @brief Configure the external trigger (ETR) input.
* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an external trigger input.
* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
* SMCR ETPS LL_TIM_ConfigETR\n
@ -3215,7 +3216,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u
*/
/**
* @brief Enable the break function.
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR BKE LL_TIM_EnableBRK
* @param TIMx Timer instance
@ -3230,7 +3231,7 @@ __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
* @brief Disable the break function.
* @rmtoll BDTR BKE LL_TIM_DisableBRK
* @param TIMx Timer instance
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @retval None
*/
@ -3241,7 +3242,7 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
/**
* @brief Configure the break input.
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
* BDTR BKF LL_TIM_ConfigBRK
@ -3268,14 +3269,15 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
* @retval None
*/
__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
uint32_t BreakFilter)
{
MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
}
/**
* @brief Enable the break 2 function.
* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @rmtoll BDTR BK2E LL_TIM_EnableBRK2
* @param TIMx Timer instance
@ -3288,7 +3290,7 @@ __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
/**
* @brief Disable the break 2 function.
* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @rmtoll BDTR BK2E LL_TIM_DisableBRK2
* @param TIMx Timer instance
@ -3301,7 +3303,7 @@ __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
/**
* @brief Configure the break 2 input.
* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
* BDTR BK2F LL_TIM_ConfigBRK2
@ -3335,7 +3337,7 @@ __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarit
/**
* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
* BDTR OSSR LL_TIM_SetOffStates
@ -3355,7 +3357,7 @@ __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdl
/**
* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
* @param TIMx Timer instance
@ -3368,7 +3370,7 @@ __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
/**
* @brief Disable automatic output (MOE can be set only by software).
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
* @param TIMx Timer instance
@ -3381,7 +3383,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
/**
* @brief Indicate whether automatic output is enabled.
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
* @param TIMx Timer instance
@ -3396,7 +3398,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
* @param TIMx Timer instance
@ -3411,7 +3413,7 @@ __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event.
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
* @param TIMx Timer instance
@ -3424,7 +3426,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
/**
* @brief Indicates whether outputs are enabled.
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
* @param TIMx Timer instance
@ -3438,7 +3440,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
#if defined(TIM_BREAK_INPUT_SUPPORT)
/**
* @brief Enable the signals connected to the designated timer break input.
* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
* AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n
@ -3461,7 +3463,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B
/**
* @brief Disable the signals connected to the designated timer break input.
* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
* AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n
@ -3484,7 +3486,7 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t
/**
* @brief Set the polarity of the break signal for the timer break input.
* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINE LL_TIM_SetBreakInputSourcePolarity\n
* AF1 BKDFBKE LL_TIM_SetBreakInputSourcePolarity\n
@ -3518,7 +3520,7 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3
*/
/**
* @brief Configures the timer DMA burst feature.
* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
* @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
* not a timer instance supports the DMA burst mode.
* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
* DCR DBA LL_TIM_ConfigDMABurst
@ -3584,7 +3586,7 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB
*/
/**
* @brief Remap TIM inputs (input channel, internal/external triggers).
* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
* a some timer inputs can be remapped.
* @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
* TIM5_OR TI4_RMP LL_TIM_SetRemap\n

285
stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_usart.h
View File

@ -42,13 +42,6 @@ extern "C" {
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup USART_LL_Private_Constants USART Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_Private_Macros USART Private Macros
@ -156,18 +149,21 @@ typedef struct
*/
#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error detected flag */
#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error detected flag */
#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
#if defined(USART_TCBGT_SUPPORT)
#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time flag */
#endif
#endif /* USART_TCBGT_SUPPORT */
#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */
#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */
#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */
#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */
#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */
#if defined(USART_CR1_UESM)
#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */
#endif /* USART_CR1_UESM */
/**
* @}
*/
@ -195,10 +191,16 @@ typedef struct
#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
#if defined(USART_CR1_UESM)
#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
#endif /* USART_CR1_UESM */
#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
#if defined(USART_ISR_REACK)
#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
#endif /* USART_ISR_REACK */
#if defined(USART_TCBGT_SUPPORT)
#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */
#endif
#endif /* USART_TCBGT_SUPPORT */
/**
* @}
*/
@ -218,9 +220,12 @@ typedef struct
#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */
#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
#if defined(USART_CR1_UESM)
#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
#endif /* USART_CR1_UESM */
#if defined(USART_TCBGT_SUPPORT)
#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */
#endif
#endif /* USART_TCBGT_SUPPORT */
/**
* @}
*/
@ -400,6 +405,18 @@ typedef struct
* @}
*/
#if defined(USART_CR1_UESM)
/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
* @{
*/
#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
/**
* @}
*/
#endif /* USART_CR1_UESM */
/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
* @{
*/
@ -480,7 +497,8 @@ typedef struct
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
*/
#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\
+ ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @brief Compute USARTDIV value according to Peripheral Clock and
@ -545,6 +563,87 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
}
#if defined(USART_CR1_UESM)
/**
* @brief USART enabled in STOP Mode.
* @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
* USART clock selection is HSI or LSE in RCC.
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_EnableInStopMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR1, USART_CR1_UESM);
}
/**
* @brief USART disabled in STOP Mode.
* @note When this function is disabled, USART is not able to wake up the MCU from Stop mode
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_DisableInStopMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
}
/**
* @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
}
#if defined(USART_CR3_UCESM)
/**
* @brief USART Clock enabled in STOP Mode
* @note When this function is called, USART Clock is enabled while in STOP mode
* @rmtoll CR3 UCESM LL_USART_EnableClockInStopMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_UCESM);
}
/**
* @brief USART clock disabled in STOP Mode
* @note When this function is called, USART Clock is disabled while in STOP mode
* @rmtoll CR3 UCESM LL_USART_DisableClockInStopMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM);
}
/**
* @brief Indicate if USART clock is enabled in STOP Mode
* @rmtoll CR3 UCESM LL_USART_IsClockEnabledInStopMode
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(USART_TypeDef *USARTx)
{
return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM));
}
#endif /* USART_CR3_UCESM */
#endif /* USART_CR1_UESM*/
/**
* @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
* @rmtoll CR1 RE LL_USART_EnableDirectionRx
@ -1461,6 +1560,41 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
}
#if defined(USART_CR1_UESM)
/**
* @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUS LL_USART_SetWKUPType
* @param USARTx USART Instance
* @param Type This parameter can be one of the following values:
* @arg @ref LL_USART_WAKEUP_ON_ADDRESS
* @arg @ref LL_USART_WAKEUP_ON_STARTBIT
* @arg @ref LL_USART_WAKEUP_ON_RXNE
* @retval None
*/
__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
{
MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
}
/**
* @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUS LL_USART_GetWKUPType
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_WAKEUP_ON_ADDRESS
* @arg @ref LL_USART_WAKEUP_ON_STARTBIT
* @arg @ref LL_USART_WAKEUP_ON_RXNE
*/
__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
}
#endif /* USART_CR1_UESM */
/**
* @brief Configure USART BRR register for achieving expected Baud Rate value.
* @note Compute and set USARTDIV value in BRR Register (full BRR content)
@ -1480,7 +1614,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
uint32_t BaudRate)
{
register uint32_t usartdiv;
uint32_t usartdiv;
register uint32_t brrtemp;
if (OverSampling == LL_USART_OVERSAMPLING_8)
@ -2161,7 +2295,8 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
{
/* In Asynchronous mode, the following bits must be kept cleared:
- LINEN, CLKEN bits in the USART_CR2 register,
- SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
- SCEN, IREN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
}
@ -2197,7 +2332,8 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
{
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
- SCEN, IREN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
/* set the UART/USART in Synchronous mode */
@ -2237,7 +2373,8 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
{
/* In LIN mode, the following bits must be kept cleared:
- STOP and CLKEN bits in the USART_CR2 register,
- IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
- IREN, SCEN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
/* Set the UART/USART in LIN mode */
@ -2275,7 +2412,8 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
{
/* In Half Duplex mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.*/
- SCEN and IREN bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
/* set the UART/USART in Half Duplex mode */
@ -2315,7 +2453,8 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
{
/* In Smartcard mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- IREN and HDSEL bits in the USART_CR3 register.*/
- IREN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
/* Configure Stop bits to 1.5 bits */
@ -2358,7 +2497,8 @@ __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
{
/* In IRDA mode, the following bits must be kept cleared:
- LINEN, STOP and CLKEN bits in the USART_CR2 register,
- SCEN and HDSEL bits in the USART_CR3 register.*/
- SCEN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
/* set the UART/USART in IRDA mode */
@ -2396,7 +2536,8 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
{
/* In Multi Processor mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
- IREN, SCEN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
}
@ -2630,6 +2771,21 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
}
#if defined(USART_CR1_UESM)
/**
* @brief Check if the USART Wake Up from stop mode Flag is set or not
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
}
#endif /* USART_CR1_UESM */
/**
* @brief Check if the USART Transmit Enable Acknowledge Flag is set or not
* @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK
@ -2641,6 +2797,19 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
}
#if defined(USART_ISR_REACK)
/**
* @brief Check if the USART Receive Enable Acknowledge Flag is set or not
* @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
}
#endif/* USART_ISR_REACK */
#if defined(USART_TCBGT_SUPPORT)
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
/**
@ -2653,8 +2822,8 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
}
#endif
#endif /* USART_TCBGT_SUPPORT */
/**
* @brief Clear Parity Error Flag
* @rmtoll ICR PECF LL_USART_ClearFlag_PE
@ -2733,7 +2902,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
}
#endif
#endif /* USART_TCBGT_SUPPORT */
/**
* @brief Clear LIN Break Detection Flag
@ -2796,6 +2965,21 @@ __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
}
#if defined(USART_CR1_UESM)
/**
* @brief Clear Wake Up from stop mode Flag
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
}
#endif /* USART_CR1_UESM */
/**
* @}
*/
@ -2935,6 +3119,21 @@ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
}
#if defined(USART_CR1_UESM)
/**
* @brief Enable Wake Up from Stop Mode Interrupt
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
}
#endif /* USART_CR1_UESM */
#if defined(USART_TCBGT_SUPPORT)
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
/**
@ -2949,7 +3148,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
}
#endif
#endif /* USART_TCBGT_SUPPORT */
/**
* @brief Disable IDLE Interrupt
@ -3082,6 +3281,21 @@ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
}
#if defined(USART_CR1_UESM)
/**
* @brief Disable Wake Up from Stop Mode Interrupt
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
}
#endif /* USART_CR1_UESM */
#if defined(USART_TCBGT_SUPPORT)
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
/**
@ -3096,7 +3310,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
}
#endif
#endif /* USART_TCBGT_SUPPORT */
/**
* @brief Check if the USART IDLE Interrupt source is enabled or disabled.
@ -3225,6 +3439,21 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
}
#if defined(USART_CR1_UESM)
/**
* @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
}
#endif /* USART_CR1_UESM */
#if defined(USART_TCBGT_SUPPORT)
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
/**
@ -3239,7 +3468,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
}
#endif
#endif /* USART_TCBGT_SUPPORT */
/**
* @}
@ -3365,12 +3594,12 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t
if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
{
/* return address of TDR register */
data_reg_addr = (uint32_t) & (USARTx->TDR);
data_reg_addr = (uint32_t) &(USARTx->TDR);
}
else
{
/* return address of RDR register */
data_reg_addr = (uint32_t) & (USARTx->RDR);
data_reg_addr = (uint32_t) &(USARTx->RDR);
}
return data_reg_addr;
@ -3392,7 +3621,7 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t
*/
__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
{
return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
}
/**

45
stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_usb.h
View File

@ -155,7 +155,7 @@ typedef struct
typedef struct
{
uint8_t dev_addr ; /*!< USB device address.
uint8_t dev_addr; /*!< USB device address.
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
uint8_t ch_num; /*!< Host channel number.
@ -199,10 +199,10 @@ typedef struct
uint32_t ErrCnt; /*!< Host channel error count.*/
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
} USB_OTG_HCTypeDef;
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
@ -234,6 +234,18 @@ typedef struct
* @}
*/
/** @defgroup USB_LL Device Speed
* @{
*/
#define USBD_HS_SPEED 0U
#define USBD_HSINFS_SPEED 1U
#define USBH_HS_SPEED 0U
#define USBD_FS_SPEED 2U
#define USBH_FSLS_SPEED 1U
/**
* @}
*/
/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
* @{
*/
@ -252,7 +264,7 @@ typedef struct
#define USB_OTG_HS_EMBEDDED_PHY 3U
#if !defined (USB_HS_PHYC_TUNE_VALUE)
#define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */
#define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */
#endif /* USB_HS_PHYC_TUNE_VALUE */
/**
* @}
@ -262,11 +274,11 @@ typedef struct
* @{
*/
#ifndef USBD_HS_TRDT_VALUE
#define USBD_HS_TRDT_VALUE 9U
#define USBD_HS_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
#ifndef USBD_FS_TRDT_VALUE
#define USBD_FS_TRDT_VALUE 5U
#define USBD_DEFAULT_TRDT_VALUE 9U
#define USBD_FS_TRDT_VALUE 5U
#define USBD_DEFAULT_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
/**
* @}
@ -275,9 +287,9 @@ typedef struct
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
* @{
*/
#define USB_OTG_HS_MAX_PACKET_SIZE 512U
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
#define USB_OTG_MAX_EP0_SIZE 64U
#define USB_OTG_HS_MAX_PACKET_SIZE 512U
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
#define USB_OTG_MAX_EP0_SIZE 64U
/**
* @}
*/
@ -287,7 +299,6 @@ typedef struct
*/
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1)
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
/**
* @}
@ -397,7 +408,7 @@ typedef struct
#define USBPHYC ((USBPHYC_GlobalTypeDef *)((uint32_t )USB_PHY_HS_CONTROLLER_BASE))
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#define EP_ADDR_MSK 0xFU
#define EP_ADDR_MSK 0xFU
/**
* @}
*/
@ -462,13 +473,9 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
uint8_t ch_num,
uint8_t epnum,
uint8_t dev_address,
uint8_t speed,
uint8_t ep_type,
uint16_t mps);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
uint8_t epnum, uint8_t dev_address, uint8_t speed,
uint8_t ep_type, uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);

8
stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_wwdg.h
View File

@ -58,8 +58,8 @@ extern "C" {
*/
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
* @{
*/
* @{
*/
#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
@ -175,7 +175,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
* @arg @ref LL_WWDG_PRESCALER_2
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
* @retval None
* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
{
@ -314,6 +314,6 @@ __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
}
#endif
#endif /* __STM32F7xx_LL_WWDG_H */
#endif /* STM32F7xx_LL_WWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

28
stm32cube/stm32f7xx/drivers/src/Legacy/stm32f7xx_hal_can.c
View File

@ -83,13 +83,29 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/

16
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal.c
View File

@ -50,11 +50,11 @@
* @{
*/
/**
* @brief STM32F7xx HAL Driver version number V1.2.7
* @brief STM32F7xx HAL Driver version number V1.2.8
*/
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F7xx_HAL_VERSION_SUB2 (0x07) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_SUB2 (0x08) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
@ -319,14 +319,26 @@ uint32_t HAL_GetTickPrio(void)
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_TickFreqTypeDef prevTickFreq;
assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq)
{
/* Back up uwTickFreq frequency */
prevTickFreq = uwTickFreq;
/* Update uwTickFreq global variable used by HAL_InitTick() */
uwTickFreq = Freq;
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
if (status != HAL_OK)
{
/* Restore previous tick frequency */
uwTickFreq = prevTickFreq;
}
}
return status;

42
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_adc.c
View File

@ -131,6 +131,7 @@
*** Callback functions ***
==============================
[..]
(@) Callback functions must be implemented in user program:
(+@) HAL_ADC_ErrorCallback()
(+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
@ -1631,23 +1632,23 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
/* Process locked */
__HAL_LOCK(hadc);
/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
if (sConfig->Channel > ADC_CHANNEL_9)
{
/* Clear the old sample time */
hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
{
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);
}
else
{
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
}
/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
if ((sConfig->Channel > ADC_CHANNEL_9) && (sConfig->Channel != ADC_INTERNAL_NONE))
{
/* Clear the old sample time */
hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
{
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);
}
else
{
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
}
}
else /* ADC_Channel include in ADC_Channel_[0..9] */
{
@ -1686,6 +1687,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
}
/* if no internal channel selected */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_INTERNAL_NONE))
{
/* Disable the VBAT & TSVREFE channel*/
ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE);
}
/* if ADC1 Channel_18 is selected enable VBAT Channel */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
{
@ -1732,7 +1740,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
* the configuration information for the specified ADC.
* @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure
* that contains the configuration information of ADC analog watchdog.
* @retval HAL status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
{

12
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_adc_ex.c
View File

@ -58,18 +58,6 @@
add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
(+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()
*** DMA mode IO operation ***
==============================
[..]
(+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length
of data to be transferred at each end of conversion
(+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
(+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
(+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA()
*** Multi mode ADCs Regular channels configuration ***
======================================================
[..]

2
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_can.c
View File

@ -1556,7 +1556,7 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
{
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
}
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos;
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;

5008
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cryp.c
View File

File diff suppressed because it is too large Load Diff

288
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cryp_ex.c
View File

@ -79,7 +79,7 @@
#define CRYPEx_PHASE_PROCESS 0x02U /*!< CRYP peripheral is in processing phase */
#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
/* CTR0 information to use in CCM algorithm */
/* CTR0 information to use in CCM algorithm */
#define CRYP_CCM_CTR0_0 0x07FFFFFFU
#define CRYP_CCM_CTR0_3 0xFFFFFF00U
@ -100,8 +100,8 @@
*/
/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
* @brief Extended processing functions.
*
* @brief Extended processing functions.
*
@verbatim
==============================================================================
##### Extended AES processing functions #####
@ -129,10 +129,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
{
uint32_t tickstart;
uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */
uint64_t inputlength = (uint64_t)(hcryp->Size) * 8U; /* input length in bits */
uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */
uint32_t tagaddr = (uint32_t)AuthTag;
if(hcryp->State == HAL_CRYP_STATE_READY)
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Process locked */
__HAL_LOCK(hcryp);
@ -141,7 +141,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
hcryp->State = HAL_CRYP_STATE_BUSY;
/* Check if initialization phase has already been performed */
if(hcryp->Phase == CRYPEx_PHASE_PROCESS)
if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
{
/* Change the CRYP phase */
hcryp->Phase = CRYPEx_PHASE_FINAL;
@ -178,28 +178,28 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
/* Write the number of bits in header (64 bits) followed by the number of bits
in the payload */
if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __RBIT((uint32_t)(headerlength));
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __RBIT((uint32_t)(inputlength));
}
else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
else if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __REV((uint32_t)(headerlength));
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __REV((uint32_t)(inputlength));
}
else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __ROR((uint32_t)headerlength, 16U);
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __ROR((uint32_t)inputlength, 16U);
}
else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
else if (hcryp->Init.DataType == CRYP_DATATYPE_32B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = (uint32_t)(headerlength);
@ -213,12 +213,12 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
/* Wait for OFNE flag to be raised */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
if (Timeout != HAL_MAX_DELAY)
{
if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP Peripheral Clock */
__HAL_CRYP_DISABLE(hcryp);
@ -235,13 +235,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
}
/* Read the authentication TAG in the output FIFO */
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
tagaddr+=4U;
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
tagaddr+=4U;
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
tagaddr+=4U;
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
#else /* AES*/
@ -250,28 +250,28 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
/* Write the number of bits in header (64 bits) followed by the number of bits
in the payload */
if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = __RBIT((uint32_t)(headerlength));
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = __RBIT((uint32_t)(inputlength));
}
else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
else if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = __REV((uint32_t)(headerlength));
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = __REV((uint32_t)(inputlength));
}
else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = __ROR((uint32_t)headerlength, 16U);
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = __ROR((uint32_t)inputlength, 16U);
}
else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
else if (hcryp->Init.DataType == CRYP_DATATYPE_32B)
{
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = (uint32_t)(headerlength);
@ -284,12 +284,12 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
}
/* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
if (Timeout != HAL_MAX_DELAY)
{
if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
@ -306,13 +306,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
}
/* Read the authentication TAG in the output FIFO */
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
tagaddr+=4U;
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
tagaddr+=4U;
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
tagaddr+=4U;
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
@ -349,11 +349,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
{
uint32_t tagaddr = (uint32_t)AuthTag;
uint32_t ctr0 [4]={0};
uint32_t ctr0 [4] = {0};
uint32_t ctr0addr = (uint32_t)ctr0;
uint32_t tickstart;
if(hcryp->State == HAL_CRYP_STATE_READY)
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Process locked */
__HAL_LOCK(hcryp);
@ -362,7 +362,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
hcryp->State = HAL_CRYP_STATE_BUSY;
/* Check if initialization phase has already been performed */
if(hcryp->Phase == CRYPEx_PHASE_PROCESS)
if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
{
/* Change the CRYP phase */
hcryp->Phase = CRYPEx_PHASE_FINAL;
@ -389,66 +389,66 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
__HAL_CRYP_DISABLE(hcryp);
/* Select final phase & ALGODIR bit must be set to ‘0’. */
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH|CRYP_CR_ALGODIR, CRYP_PHASE_FINAL|CRYP_OPERATINGMODE_ENCRYPT);
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH | CRYP_CR_ALGODIR, CRYP_PHASE_FINAL | CRYP_OPERATINGMODE_ENCRYPT);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
/* Write the counter block in the IN FIFO, CTR0 information from B0
data has to be swapped according to the DATATYPE*/
ctr0[0]=(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
ctr0[1]=hcryp->Init.B0[1];
ctr0[2]=hcryp->Init.B0[2];
ctr0[3]=hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
ctr0[0] = (hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
ctr0[1] = hcryp->Init.B0[1];
ctr0[2] = hcryp->Init.B0[2];
ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
ctr0addr+=4U;
hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
ctr0addr+=4U;
hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
ctr0addr+=4U;
hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
}
else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
ctr0addr+=4U;
hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
ctr0addr+=4U;
hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
ctr0addr+=4U;
hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
ctr0addr += 4U;
hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
ctr0addr += 4U;
hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
ctr0addr += 4U;
hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
}
else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
ctr0addr+=4U;
hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
ctr0addr+=4U;
hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
ctr0addr+=4U;
hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
}
else
{
hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
ctr0addr+=4U;
hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
ctr0addr+=4U;
hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
ctr0addr+=4U;
hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
}
/* Wait for OFNE flag to be raised */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
if (Timeout != HAL_MAX_DELAY)
{
if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral Clock */
__HAL_CRYP_DISABLE(hcryp);
@ -465,13 +465,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
}
/* Read the Auth TAG in the IN FIFO */
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
tagaddr+=4U;
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
tagaddr+=4U;
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
tagaddr+=4U;
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
#else /* AES */
@ -480,75 +480,75 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
/* Write the counter block in the IN FIFO, CTR0 information from B0
data has to be swapped according to the DATATYPE*/
if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
ctr0[0]=(__REV(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0);
ctr0[1]=__REV(hcryp->Init.B0[1]);
ctr0[2]=__REV(hcryp->Init.B0[2]);
ctr0[3]=(__REV(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3);
ctr0[0] = (__REV(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0);
ctr0[1] = __REV(hcryp->Init.B0[1]);
ctr0[2] = __REV(hcryp->Init.B0[2]);
ctr0[3] = (__REV(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3);
hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
ctr0addr+=4U;
hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
ctr0addr+=4U;
hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
ctr0addr+=4U;
hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr));
}
else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
ctr0[0]= ( __ROR((hcryp->Init.B0[0]), 16U)& CRYP_CCM_CTR0_0);
ctr0[1]= __ROR((hcryp->Init.B0[1]), 16U);
ctr0[2]= __ROR((hcryp->Init.B0[2]), 16U);
ctr0[3]= ( __ROR((hcryp->Init.B0[3]), 16U)& CRYP_CCM_CTR0_3);
ctr0[0] = (__ROR((hcryp->Init.B0[0]), 16U)& CRYP_CCM_CTR0_0);
ctr0[1] = __ROR((hcryp->Init.B0[1]), 16U);
ctr0[2] = __ROR((hcryp->Init.B0[2]), 16U);
ctr0[3] = (__ROR((hcryp->Init.B0[3]), 16U)& CRYP_CCM_CTR0_3);
hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
ctr0addr+=4U;
hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
ctr0addr+=4U;
hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
ctr0addr+=4U;
hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U);
ctr0addr += 4U;
hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U);
ctr0addr += 4U;
hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U);
ctr0addr += 4U;
hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U);
}
else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
ctr0[0]=(__RBIT(hcryp->Init.B0[0])& CRYP_CCM_CTR0_0);
ctr0[1]=__RBIT(hcryp->Init.B0[1]);
ctr0[2]=__RBIT(hcryp->Init.B0[2]);
ctr0[3]=(__RBIT(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3);
ctr0[0] = (__RBIT(hcryp->Init.B0[0])& CRYP_CCM_CTR0_0);
ctr0[1] = __RBIT(hcryp->Init.B0[1]);
ctr0[2] = __RBIT(hcryp->Init.B0[2]);
ctr0[3] = (__RBIT(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3);
hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
ctr0addr+=4U;
hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
ctr0addr+=4U;
hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
ctr0addr+=4U;
hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr));
}
else
{
ctr0[0]=(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
ctr0[1]=hcryp->Init.B0[1];
ctr0[2]=hcryp->Init.B0[2];
ctr0[3]=hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
ctr0[0] = (hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
ctr0[1] = hcryp->Init.B0[1];
ctr0[2] = hcryp->Init.B0[2];
ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
ctr0addr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
ctr0addr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
ctr0addr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
hcryp->Instance->DINR = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DINR = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DINR = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DINR = *(uint32_t *)(ctr0addr);
}
/* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
if (Timeout != HAL_MAX_DELAY)
{
if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral Clock */
__HAL_CRYP_DISABLE(hcryp);
@ -565,13 +565,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
}
/* Read the authentication TAG in the output FIFO */
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
tagaddr+=4U;
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
tagaddr+=4U;
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
tagaddr+=4U;
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
@ -603,8 +603,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
#if defined (AES)
/** @defgroup CRYPEx_Exported_Functions_Group2 Key Derivation functions
* @brief AutoKeyDerivation functions
*
* @brief AutoKeyDerivation functions
*
@verbatim
==============================================================================
##### Key Derivation functions #####
@ -624,7 +624,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
*/
void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
{
if(hcryp->State == HAL_CRYP_STATE_READY)
if (hcryp->State == HAL_CRYP_STATE_READY)
{
hcryp->AutoKeyDerivation = ENABLE;
}
@ -641,7 +641,7 @@ void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
*/
void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
{
if(hcryp->State == HAL_CRYP_STATE_READY)
if (hcryp->State == HAL_CRYP_STATE_READY)
{
hcryp->AutoKeyDerivation = DISABLE;
}

2
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dac.c
View File

@ -110,7 +110,7 @@
(+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
(+) Stop the DAC peripheral using HAL_DAC_Stop()
*** DMA mode IO operation ***
==============================
[..]

373
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dcmi.c
View File

@ -56,7 +56,7 @@
[..]
(@) You can refer to the DCMI HAL driver header file for more useful macros
*** Callback registration ***
=============================
@ -106,7 +106,7 @@
When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
* @attention
@ -177,9 +177,9 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
{
/* Check the DCMI peripheral state */
if(hdcmi == NULL)
if (hdcmi == NULL)
{
return HAL_ERROR;
return HAL_ERROR;
}
/* Check function parameters */
@ -192,21 +192,23 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
#ifdef DCMI_CR_BSM
assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));
assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));
assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
#endif
if(hdcmi->State == HAL_DCMI_STATE_RESET)
if (hdcmi->State == HAL_DCMI_STATE_RESET)
{
/* Init the DCMI Callback settings */
/* Init the DCMI Callback settings */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
if(hdcmi->MspInitCallback == NULL)
if (hdcmi->MspInitCallback == NULL)
{
/* Legacy weak MspInit Callback */
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
@ -221,24 +223,43 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
/* Change the DCMI state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Configures the HS, VS, DE and PC polarity */
hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\
DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\
DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\
#ifdef DCMI_CR_BSM
if (hdcmi->Init.ExtendedDataMode != DCMI_EXTEND_DATA_8B)
{
/* Byte select mode must be programmed to the reset value if the extended mode
is not set to 8-bit data capture on every pixel clock */
hdcmi->Init.ByteSelectMode = DCMI_BSM_ALL;
}
#endif
/* Configures the HS, VS, DE and PC polarity */
#ifdef DCMI_CR_BSM
hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 | \
DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG | \
DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS | \
DCMI_CR_LSM | DCMI_CR_OELS);
hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\
hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity |\
hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\
hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\
hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\
hdcmi->Init.LineSelectStart);
hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \
hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \
hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \
hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode | \
hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode | \
hdcmi->Init.LineSelectStart);
#else
hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 | \
DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG);
if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \
hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \
hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \
hdcmi->Init.JPEGMode);
#endif
if (hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
{
hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |\
((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_ESCR_LSC_Pos)|\
((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_ESCR_LEC_Pos) |\
hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) | \
((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_ESCR_LSC_Pos) | \
((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_ESCR_LEC_Pos) | \
((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_ESCR_FEC_Pos));
}
@ -266,7 +287,7 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
{
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
if(hdcmi->MspDeInitCallback == NULL)
if (hdcmi->MspDeInitCallback == NULL)
{
hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
}
@ -295,7 +316,7 @@ HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
@ -311,7 +332,7 @@ __weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
@ -350,7 +371,7 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
* @param Length The length of capture to be transferred.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
{
/* Initialize the second memory address */
uint32_t SecondMemAddress = 0;
@ -369,7 +390,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
/* Configure the DCMI Mode */
hdcmi->Instance->CR &= ~(DCMI_CR_CM);
hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);
hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);
/* Set the DMA memory0 conversion complete callback */
hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;
@ -383,11 +404,16 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
/* Reset transfer counters value */
hdcmi->XferCount = 0;
hdcmi->XferTransferNumber = 0;
hdcmi->XferSize = 0;
hdcmi->pBuffPtr = 0;
if(Length <= 0xFFFF)
if (Length <= 0xFFFFU)
{
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);
if (HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length) != HAL_OK)
{
return HAL_ERROR;
}
}
else /* DCMI_DOUBLE_BUFFER Mode */
{
@ -400,21 +426,24 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
hdcmi->pBuffPtr = pData;
/* Get the number of buffer */
while(hdcmi->XferSize > 0xFFFF)
while (hdcmi->XferSize > 0xFFFFU)
{
hdcmi->XferSize = (hdcmi->XferSize/2);
hdcmi->XferCount = hdcmi->XferCount*2;
hdcmi->XferSize = (hdcmi->XferSize / 2U);
hdcmi->XferCount = hdcmi->XferCount * 2U;
}
/* Update DCMI counter and transfer number*/
hdcmi->XferCount = (hdcmi->XferCount - 2);
hdcmi->XferCount = (hdcmi->XferCount - 2U);
hdcmi->XferTransferNumber = hdcmi->XferCount;
/* Update second memory address */
SecondMemAddress = (uint32_t)(pData + (4*hdcmi->XferSize));
SecondMemAddress = (uint32_t)(pData + (4 * hdcmi->XferSize));
/* Start DMA multi buffer transfer */
HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);
if (HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize) != HAL_OK)
{
return HAL_ERROR;
}
}
/* Enable Capture */
@ -433,9 +462,9 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi)
{
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000);
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
@ -450,7 +479,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
/* Check if the DCMI capture effectively disabled */
do
{
if (count-- == 0)
if (count-- == 0U)
{
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
@ -459,13 +488,13 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
break;
}
}
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
/* Disable the DCMI */
__HAL_DCMI_DISABLE(hdcmi);
/* Disable the DMA */
HAL_DMA_Abort(hdcmi->DMA_Handle);
(void)HAL_DMA_Abort(hdcmi->DMA_Handle);
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;
@ -486,15 +515,15 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi)
{
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000);
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdcmi);
if(hdcmi->State == HAL_DCMI_STATE_BUSY)
if (hdcmi->State == HAL_DCMI_STATE_BUSY)
{
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_SUSPENDED;
@ -505,7 +534,7 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
/* Check if the DCMI capture effectively disabled */
do
{
if (count-- == 0)
if (count-- == 0U)
{
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
@ -517,7 +546,7 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
break;
}
}
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
}
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
@ -532,12 +561,12 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi)
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi)
{
/* Process locked */
__HAL_LOCK(hdcmi);
if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
if (hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
{
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
@ -563,7 +592,7 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
uint32_t isr_value = READ_REG(hdcmi->Instance->MISR);
/* Synchronization error interrupt management *******************************/
if((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
if ((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
{
/* Clear the Synchronization error flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
@ -578,10 +607,10 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
/* Abort the DMA Transfer */
HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
(void)HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
}
/* Overflow interrupt management ********************************************/
if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
if ((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
{
/* Clear the Overflow flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);
@ -596,10 +625,13 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
/* Abort the DMA Transfer */
HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK)
{
DCMI_DMAError(hdcmi->DMA_Handle);
}
}
/* Line Interrupt management ************************************************/
if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
if ((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
{
/* Clear the Line interrupt flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
@ -613,7 +645,7 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
/* VSYNC interrupt management ***********************************************/
if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
if ((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
{
/* Clear the VSYNC flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
@ -627,10 +659,10 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
/* FRAME interrupt management ***********************************************/
if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
if ((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
{
/* When snapshot mode, disable Vsync, Error and Overrun interrupts */
if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
{
/* Disable the Line, Vsync, Error and Overrun interrupts */
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
@ -756,7 +788,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui
assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
/* Configure CROP */
hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_CWSIZE_VLINE_Pos));
hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_CWSTRT_VST_Pos));
@ -822,6 +854,37 @@ HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
return HAL_OK;
}
/**
* @brief Set embedded synchronization delimiters unmasks.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @param SyncUnmask pointer to a DCMI_SyncUnmaskTypeDef structure that contains
* the embedded synchronization delimiters unmasks.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask)
{
/* Process Locked */
__HAL_LOCK(hdcmi);
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Write DCMI embedded synchronization unmask register */
hdcmi->Instance->ESUR = (((uint32_t)SyncUnmask->FrameStartUnmask) | \
((uint32_t)SyncUnmask->LineStartUnmask << DCMI_ESUR_LSU_Pos) | \
((uint32_t)SyncUnmask->LineEndUnmask << DCMI_ESUR_LEU_Pos) | \
((uint32_t)SyncUnmask->FrameEndUnmask << DCMI_ESUR_FEU_Pos));
/* Change the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
return HAL_OK;
}
/**
* @}
*/
@ -877,7 +940,7 @@ HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_
{
HAL_StatusTypeDef status = HAL_OK;
if(pCallback == NULL)
if (pCallback == NULL)
{
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
@ -886,59 +949,59 @@ HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_
}
else
{
if(hdcmi->State == HAL_DCMI_STATE_READY)
if (hdcmi->State == HAL_DCMI_STATE_READY)
{
switch (CallbackID)
{
case HAL_DCMI_FRAME_EVENT_CB_ID :
hdcmi->FrameEventCallback = pCallback;
break;
case HAL_DCMI_FRAME_EVENT_CB_ID :
hdcmi->FrameEventCallback = pCallback;
break;
case HAL_DCMI_VSYNC_EVENT_CB_ID :
hdcmi->VsyncEventCallback = pCallback;
break;
case HAL_DCMI_VSYNC_EVENT_CB_ID :
hdcmi->VsyncEventCallback = pCallback;
break;
case HAL_DCMI_LINE_EVENT_CB_ID :
hdcmi->LineEventCallback = pCallback;
break;
case HAL_DCMI_LINE_EVENT_CB_ID :
hdcmi->LineEventCallback = pCallback;
break;
case HAL_DCMI_ERROR_CB_ID :
hdcmi->ErrorCallback = pCallback;
break;
case HAL_DCMI_ERROR_CB_ID :
hdcmi->ErrorCallback = pCallback;
break;
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = pCallback;
break;
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = pCallback;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = pCallback;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = pCallback;
break;
default :
/* Return error status */
status = HAL_ERROR;
break;
default :
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if(hdcmi->State == HAL_DCMI_STATE_RESET)
else if (hdcmi->State == HAL_DCMI_STATE_RESET)
{
switch (CallbackID)
{
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = pCallback;
break;
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = pCallback;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = pCallback;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = pCallback;
break;
default :
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
default :
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
@ -962,61 +1025,61 @@ HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCM
{
HAL_StatusTypeDef status = HAL_OK;
if(hdcmi->State == HAL_DCMI_STATE_READY)
if (hdcmi->State == HAL_DCMI_STATE_READY)
{
switch (CallbackID)
{
case HAL_DCMI_FRAME_EVENT_CB_ID :
hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
break;
case HAL_DCMI_FRAME_EVENT_CB_ID :
hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
break;
case HAL_DCMI_VSYNC_EVENT_CB_ID :
hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
break;
case HAL_DCMI_VSYNC_EVENT_CB_ID :
hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
break;
case HAL_DCMI_LINE_EVENT_CB_ID :
hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
break;
case HAL_DCMI_LINE_EVENT_CB_ID :
hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
break;
case HAL_DCMI_ERROR_CB_ID :
hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_DCMI_ERROR_CB_ID :
hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
break;
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
break;
default :
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
default :
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if(hdcmi->State == HAL_DCMI_STATE_RESET)
else if (hdcmi->State == HAL_DCMI_STATE_RESET)
{
switch (CallbackID)
{
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
break;
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
break;
default :
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
default :
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
@ -1037,59 +1100,59 @@ HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCM
/** @defgroup DCMI_Private_Functions DCMI Private Functions
* @{
*/
/**
* @brief DMA conversion complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
/**
* @brief DMA conversion complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
{
uint32_t tmp = 0;
DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if(hdcmi->XferCount != 0)
if (hdcmi->XferCount != 0)
{
/* Update memory 0 address location */
tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT);
if(((hdcmi->XferCount % 2) == 0) && (tmp != 0))
if (((hdcmi->XferCount % 2) == 0) && (tmp != 0))
{
tmp = hdcmi->DMA_Handle->Instance->M0AR;
HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY0);
HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8 * hdcmi->XferSize)), MEMORY0);
hdcmi->XferCount--;
}
/* Update memory 1 address location */
else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
{
tmp = hdcmi->DMA_Handle->Instance->M1AR;
HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY1);
HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8 * hdcmi->XferSize)), MEMORY1);
hdcmi->XferCount--;
}
}
/* Update memory 0 address location */
else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0)
else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0)
{
hdcmi->DMA_Handle->Instance->M0AR = hdcmi->pBuffPtr;
}
/* Update memory 1 address location */
else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
{
tmp = hdcmi->pBuffPtr;
hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4*hdcmi->XferSize));
hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4 * hdcmi->XferSize));
hdcmi->XferCount = hdcmi->XferTransferNumber;
}
/* Check if the frame is transferred */
if(hdcmi->XferCount == hdcmi->XferTransferNumber)
if (hdcmi->XferCount == hdcmi->XferTransferNumber)
{
/* Enable the Frame interrupt */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
/* When snapshot mode, set dcmi state to ready */
if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
{
hdcmi->State= HAL_DCMI_STATE_READY;
hdcmi->State = HAL_DCMI_STATE_READY;
}
}
}
@ -1102,9 +1165,9 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
*/
static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
{
DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if(hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE)
if (hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE)
{
/* Initialize the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
@ -1115,10 +1178,10 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
/* DCMI error Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI error callback*/
hdcmi->ErrorCallback(hdcmi);
/*Call registered DCMI error callback*/
hdcmi->ErrorCallback(hdcmi);
#else
HAL_DCMI_ErrorCallback(hdcmi);
HAL_DCMI_ErrorCallback(hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}

4
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dcmi_ex.c
View File

@ -4,8 +4,8 @@
* @author MCD Application Team
* @brief Empty file; This file is no longer used to handle the Black&White
* feature. Its content is now moved to common files
* (stm32f7xx_hal_dcmi.c/.h) as there's no device's dependency within F7
* family. It's just kept for compatibility reasons.
* (stm32f7xx_hal_dcmi.c/.h) as there's no device's dependency within
* this family. It's just kept for compatibility reasons.
*
******************************************************************************
* @attention

45
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dfsdm.c
View File

@ -157,23 +157,26 @@
*** Callback registration ***
=============================
[..]
The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use functions @ref HAL_DFSDM_Channel_RegisterCallback(),
@ref HAL_DFSDM_Filter_RegisterCallback() or
@ref HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.
Use functions HAL_DFSDM_Channel_RegisterCallback(),
HAL_DFSDM_Filter_RegisterCallback() or
HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.
Function @ref HAL_DFSDM_Channel_RegisterCallback() allows to register
[..]
Function HAL_DFSDM_Channel_RegisterCallback() allows to register
following callbacks:
(+) CkabCallback : DFSDM channel clock absence detection callback.
(+) ScdCallback : DFSDM channel short circuit detection callback.
(+) MspInitCallback : DFSDM channel MSP init callback.
(+) MspDeInitCallback : DFSDM channel MSP de-init callback.
[..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Function @ref HAL_DFSDM_Filter_RegisterCallback() allows to register
[..]
Function HAL_DFSDM_Filter_RegisterCallback() allows to register
following callbacks:
(+) RegConvCpltCallback : DFSDM filter regular conversion complete callback.
(+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
@ -182,26 +185,33 @@
(+) ErrorCallback : DFSDM filter error callback.
(+) MspInitCallback : DFSDM filter MSP init callback.
(+) MspDeInitCallback : DFSDM filter MSP de-init callback.
[..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
For specific DFSDM filter analog watchdog callback use dedicated register callback:
@ref HAL_DFSDM_Filter_RegisterAwdCallback().
HAL_DFSDM_Filter_RegisterAwdCallback().
Use functions @ref HAL_DFSDM_Channel_UnRegisterCallback() or
@ref HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default
[..]
Use functions HAL_DFSDM_Channel_UnRegisterCallback() or
HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,
[..]
HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
[..]
This function allows to reset following callbacks:
(+) CkabCallback : DFSDM channel clock absence detection callback.
(+) ScdCallback : DFSDM channel short circuit detection callback.
(+) MspInitCallback : DFSDM channel MSP init callback.
(+) MspDeInitCallback : DFSDM channel MSP de-init callback.
@ref HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,
[..]
HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
[..]
This function allows to reset following callbacks:
(+) RegConvCpltCallback : DFSDM filter regular conversion complete callback.
(+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
@ -211,29 +221,34 @@
(+) MspInitCallback : DFSDM filter MSP init callback.
(+) MspDeInitCallback : DFSDM filter MSP de-init callback.
[..]
For specific DFSDM filter analog watchdog callback use dedicated unregister callback:
@ref HAL_DFSDM_Filter_UnRegisterAwdCallback().
HAL_DFSDM_Filter_UnRegisterAwdCallback().
[..]
By default, after the call of init function and if the state is RESET
all callbacks are reset to the corresponding legacy weak functions:
examples @ref HAL_DFSDM_ChannelScdCallback(), @ref HAL_DFSDM_FilterErrorCallback().
examples HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FilterErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak functions in the init and de-init only when these
callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the init and de-init keep and use
the user MspInit/MspDeInit callbacks (registered beforehand)
[..]
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the init/de-init.
In that case first register the MspInit/MspDeInit user callbacks using
@ref HAL_DFSDM_Channel_RegisterCallback() or
@ref HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.
HAL_DFSDM_Channel_RegisterCallback() or
HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.
[..]
When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak callbacks are used.
@endverbatim
******************************************************************************
* @attention

2
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dma.c
View File

@ -492,7 +492,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
else
{
/* Process unlocked */
__HAL_UNLOCK(hdma);
__HAL_UNLOCK(hdma);
/* Return error status */
status = HAL_BUSY;

2
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dma_ex.c
View File

@ -210,7 +210,7 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_
else
{
/* Process unlocked */
__HAL_UNLOCK(hdma);
__HAL_UNLOCK(hdma);
/* Return error status */
status = HAL_BUSY;

228
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_exti.c
View File

@ -85,7 +85,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
#include "stm32f7xx_hal_exti.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
@ -105,7 +104,7 @@
#ifdef HAL_EXTI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines ------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
@ -144,6 +143,8 @@
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
@ -154,37 +155,77 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
/* Check parameters */
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
/* Assign line number to handle */
hexti->Line = pExtiConfig->Line;
/* Clear EXTI line configuration */
EXTI->IMR &= ~pExtiConfig->Line;
EXTI->EMR &= ~pExtiConfig->Line;
/* Compute line mask */
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* Select the Mode for the selected external interrupts */
regval = (uint32_t)EXTI_BASE;
regval += pExtiConfig->Mode;
*(__IO uint32_t *) regval |= pExtiConfig->Line;
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~pExtiConfig->Line;
EXTI->FTSR &= ~pExtiConfig->Line;
/* Select the trigger for the selected external interrupts */
if (pExtiConfig->Trigger == EXTI_TRIGGER_RISING_FALLING)
/* Configure triggers for configurable lines */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
/* Rising Falling edge */
EXTI->RTSR |= pExtiConfig->Line;
EXTI->FTSR |= pExtiConfig->Line;
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
/* Configure rising trigger */
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
{
EXTI->RTSR |= maskline;
}
else
{
EXTI->RTSR &= ~maskline;
}
/* Configure falling trigger */
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
{
EXTI->FTSR |= maskline;
}
else
{
EXTI->FTSR &= ~maskline;
}
/* Configure gpio port selection in case of gpio exti line */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
SYSCFG->EXTICR[linepos >> 2u] = regval;
}
}
/* Configure interrupt mode : read current mode */
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
{
EXTI->IMR |= maskline;
}
else
{
regval = (uint32_t)EXTI_BASE;
regval += pExtiConfig->Trigger;
*(__IO uint32_t *) regval |= pExtiConfig->Line;
EXTI->IMR &= ~maskline;
}
/* Configure event mode : read current mode */
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
{
EXTI->EMR |= maskline;
}
else
{
EXTI->EMR &= ~maskline;
}
return HAL_OK;
}
@ -196,6 +237,10 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
@ -208,41 +253,67 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
/* Store handle line number to configuration structure */
pExtiConfig->Line = hexti->Line;
/* Get EXTI mode to configiguration structure */
if ((EXTI->IMR & hexti->Line) == hexti->Line)
/* Compute line mask */
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Get core mode : interrupt */
/* Check if selected line is enable */
if ((EXTI->IMR & maskline) != 0x00u)
{
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
}
else if ((EXTI->EMR & hexti->Line) == hexti->Line)
{
pExtiConfig->Mode = EXTI_MODE_EVENT;
}
else
{
/* No MODE selected */
pExtiConfig->Mode = 0x0Bu;
pExtiConfig->Mode = EXTI_MODE_NONE;
}
/* Get EXTI Trigger to configiguration structure */
if ((EXTI->RTSR & hexti->Line) == hexti->Line)
/* Get event mode */
/* Check if selected line is enable */
if ((EXTI->EMR & maskline) != 0x00u)
{
if ((EXTI->FTSR & hexti->Line) == hexti->Line)
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING_FALLING;
}
else
pExtiConfig->Mode |= EXTI_MODE_EVENT;
}
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
/* Check if configuration of selected line is enable */
if ((EXTI->RTSR & maskline) != 0x00u)
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
}
else if ((EXTI->FTSR & hexti->Line) == hexti->Line)
{
pExtiConfig->Trigger = EXTI_TRIGGER_FALLING;
else
{
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
}
/* Get falling configuration */
/* Check if configuration of selected line is enable */
if ((EXTI->FTSR & maskline) != 0x00u)
{
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
}
/* Get Gpio port selection for gpio lines */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
}
else
{
pExtiConfig->GPIOSel = 0x00u;
}
}
else
{
/* No Trigger selected */
pExtiConfig->Trigger = 0x00u;
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0x00u;
}
return HAL_OK;
@ -255,6 +326,10 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
*/
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
{
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
/* Check null pointer */
if (hexti == NULL)
{
@ -264,15 +339,32 @@ HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* compute line mask */
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Clear interrupt mode */
EXTI->IMR = (EXTI->IMR & ~hexti->Line);
EXTI->IMR = (EXTI->IMR & ~maskline);
/* 2] Clear event mode */
EXTI->EMR = (EXTI->EMR & ~hexti->Line);
EXTI->EMR = (EXTI->EMR & ~maskline);
/* 3] Clear triggers */
EXTI->RTSR = (EXTI->RTSR & ~hexti->Line);
EXTI->FTSR = (EXTI->FTSR & ~hexti->Line);
/* 3] Clear triggers in case of configurable lines */
if ((hexti->Line & EXTI_CONFIG) != 0x00u)
{
EXTI->RTSR = (EXTI->RTSR & ~maskline);
EXTI->FTSR = (EXTI->FTSR & ~maskline);
/* Get Gpio port selection for gpio lines */
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
SYSCFG->EXTICR[linepos >> 2u] = regval;
}
}
return HAL_OK;
}
@ -352,17 +444,18 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin
*/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t maskline;
/* Compute line mask */
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Get pending bit */
regaddr = (&EXTI->PR);
regval = (*regaddr & hexti->Line);
regval = (EXTI->PR & maskline);
if (regval != 0x00u)
{
/* Clear pending bit */
*regaddr = hexti->Line;
EXTI->PR = maskline;
/* Call callback */
if (hexti->PendingCallback != NULL)
@ -383,19 +476,21 @@ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
*/
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* Get pending bit */
regaddr = &EXTI->PR;
/* Compute line mask */
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* return 1 if bit is set else 0 */
regval = ((*regaddr & hexti->Line) >> POSITION_VAL(hexti->Line));
regval = ((EXTI->PR & maskline) >> linepos);
return regval;
}
@ -410,12 +505,18 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
*/
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
uint32_t maskline;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* Compute line mask */
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Clear Pending bit */
EXTI->PR = hexti->Line;
EXTI->PR = maskline;
}
/**
@ -425,10 +526,17 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
*/
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
{
uint32_t maskline;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
EXTI->SWIER = hexti->Line;
/* Compute line mask */
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Generate Software interrupt */
EXTI->SWIER = maskline;
}
/**

2
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_flash.c
View File

@ -56,7 +56,7 @@
(+) Reset the Instruction cache and the Data cache
(+) Enable/Disable the FLASH interrupts
(+) Monitor the FLASH flags status
[..]
[..]
(@) For any Flash memory program operation (erase or program), the CPU clock frequency
(HCLK) must be at least 1MHz.
(@) The contents of the Flash memory are not guaranteed if a device reset occurs during

63
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_gpio.c
View File

@ -190,25 +190,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
if(iocurrent == ioposition)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
GPIOx->AFR[position >> 3] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
GPIOx->MODER = temp;
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
@ -234,6 +215,25 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
temp |= ((GPIO_Init->Pull) << (position * 2));
GPIOx->PUPDR = temp;
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
GPIOx->AFR[position >> 3] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
GPIOx->MODER = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
@ -316,10 +316,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
{
/* Configure the External Interrupt or event for the current IO */
tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
SYSCFG->EXTICR[position >> 2] &= ~tmp;
/* Clear EXTI line configuration */
EXTI->IMR &= ~((uint32_t)iocurrent);
EXTI->EMR &= ~((uint32_t)iocurrent);
@ -327,6 +323,10 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~((uint32_t)iocurrent);
EXTI->FTSR &= ~((uint32_t)iocurrent);
/* Configure the External Interrupt or event for the current IO */
tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
SYSCFG->EXTICR[position >> 2] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO Direction in Input Floating Mode */
@ -335,14 +335,14 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
}
}
}
@ -431,13 +431,13 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)
if ((GPIOx->ODR & GPIO_Pin) != 0X00u)
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
}
else
{
GPIOx->BSRR = GPIO_Pin;
GPIOx->BSRR = (uint32_t)GPIO_Pin;
}
}
@ -467,10 +467,11 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Read LCKK bit*/
/* Read LCKR register. This read is mandatory to complete key lock sequence */
tmp = GPIOx->LCKR;
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
/* Read again in order to confirm lock is active */
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
{
return HAL_OK;
}

836
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_hash.c
View File

File diff suppressed because it is too large Load Diff

402
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_hash_ex.c
View File

@ -33,16 +33,21 @@
e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to
HAL_HASHEx_xxx_Finish() is then required to retrieve the digest.
(#)Multi-buffer processing is possible in polling and DMA mode.
(#)Multi-buffer processing is possible in polling, interrupt and DMA modes.
(##) In polling mode, only multi-buffer HASH processing is possible.
API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one.
User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as
User must resort to HAL_HASHEx_xxx_Accumulate_End() to enter the last one and retrieve as
well the computed digest.
(##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer,
except for the last one.
User must resort to HAL_HASHEx_xxx_Accumulate_End_IT() to enter the last one and retrieve as
well the computed digest.
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
(+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
From that point, each buffer can be fed to the IP thru HAL_HASHEx_xxx_Start_DMA() API.
From that point, each buffer can be fed to the Peripheral thru HAL_HASHEx_xxx_Start_DMA() API.
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
macro then wrap-up the HASH processing in feeding the last input buffer thru the
same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
@ -50,7 +55,7 @@
(+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to
extended functions): after initialization, the key and the first input buffer are entered
in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
in the Peripheral with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
starts step 2.
The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this
point, the HMAC processing is still carrying out step 2.
@ -112,17 +117,19 @@
the hash value using one of the following algorithms:
(+) SHA224
(++) HAL_HASHEx_SHA224_Start()
(++) HAL_HASHEx_SHA224_Accumulate()
(++) HAL_HASHEx_SHA224_Accmlt()
(++) HAL_HASHEx_SHA224_Accmlt_End()
(+) SHA256
(++) HAL_HASHEx_SHA256_Start()
(++) HAL_HASHEx_SHA256_Accumulate()
(++) HAL_HASHEx_SHA256_Accmlt()
(++) HAL_HASHEx_SHA256_Accmlt_End()
[..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
[..] In case of multi-buffer HASH processing (a single digest is computed while
several buffers are fed to the IP), the user can resort to successive calls
several buffers are fed to the Peripheral), the user can resort to successive calls
to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call
to HAL_HASHEx_xxx_Start().
to HAL_HASHEx_xxx_Accumulate_End().
@endverbatim
* @{
@ -133,11 +140,11 @@
* @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout: Timeout value
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@ -148,37 +155,52 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
/**
* @brief If not already done, initialize the HASH peripheral in SHA224 mode then
* processes pInBuffer.
* @note Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed
* several input buffers back-to-back to the IP that will yield a single
* @note Consecutive calls to HAL_HASHEx_SHA224_Accmlt() can be used to feed
* several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASHEx_SHA224_Start().
* HAL_HASHEx_SHA224_Accmlt_End().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the IP has already been initialized.
* @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Start()
* to read it, feeding at the same time the last input buffer to the IP.
* the Peripheral has already been initialized.
* @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Accmlt_End()
* to read it, feeding at the same time the last input buffer to the Peripheral.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Start() is able
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Accmlt_End() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes, must be a multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
}
/**
* @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA224_Accmlt() API.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout: Timeout value
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@ -189,28 +211,42 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
/**
* @brief If not already done, initialize the HASH peripheral in SHA256 mode then
* processes pInBuffer.
* @note Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed
* several input buffers back-to-back to the IP that will yield a single
* @note Consecutive calls to HAL_HASHEx_SHA256_Accmlt() can be used to feed
* several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASHEx_SHA256_Start().
* HAL_HASHEx_SHA256_Accmlt_End().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the IP has already been initialized.
* @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Start()
* to read it, feeding at the same time the last input buffer to the IP.
* the Peripheral has already been initialized.
* @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Accmlt_End()
* to read it, feeding at the same time the last input buffer to the Peripheral.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Start() is able
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Accmlt_End() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes, must be a multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
}
/**
* @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA256_Accmlt() API.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
}
/**
* @}
@ -227,8 +263,12 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_
the hash value using one of the following algorithms:
(+) SHA224
(++) HAL_HASHEx_SHA224_Start_IT()
(++) HAL_HASHEx_SHA224_Accmlt_IT()
(++) HAL_HASHEx_SHA224_Accmlt_End_IT()
(+) SHA256
(++) HAL_HASHEx_SHA256_Start_IT()
(++) HAL_HASHEx_SHA256_Accmlt_IT()
(++) HAL_HASHEx_SHA256_Accmlt_End_IT()
@endverbatim
* @{
@ -239,10 +279,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_
* @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@ -250,14 +290,51 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
}
/**
* @brief If not already done, initialize the HASH peripheral in SHA224 mode then
* processes pInBuffer in interruption mode.
* @note Consecutive calls to HAL_HASHEx_SHA224_Accmlt_IT() can be used to feed
* several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASHEx_SHA224_Accmlt_End_IT().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the Peripheral has already been initialized.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Accmlt_End_IT() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
}
/**
* @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA224_Accmlt_IT() API.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
}
/**
* @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@ -265,6 +342,43 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
}
/**
* @brief If not already done, initialize the HASH peripheral in SHA256 mode then
* processes pInBuffer in interruption mode.
* @note Consecutive calls to HAL_HASHEx_SHA256_Accmlt_IT() can be used to feed
* several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASHEx_SHA256_Accmlt_End_IT().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the Peripheral has already been initialized.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Accmlt_End_IT() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
}
/**
* @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA256_Accmlt_IT() API.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
@ -285,7 +399,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
(++) HAL_HASHEx_SHA256_Start_DMA()
(++) HAL_HASHEx_SHA256_Finish()
[..] When resorting to DMA mode to enter the data in the IP, user must resort
[..] When resorting to DMA mode to enter the data in the Peripheral, user must resort
to HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with
HAL_HASHEx_xxx_Finish().
@ -303,12 +417,12 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer
* to feed the input buffer to the IP.
* to feed the input buffer to the Peripheral.
* @note Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must
* be called to retrieve the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -321,9 +435,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in
* HMAC SHA224 mode.
* @param hhash: HASH handle.
* @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout: Timeout value.
* @param hhash HASH handle.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@ -333,12 +447,12 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
/**
* @brief Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer
* to feed the input buffer to the IP.
* to feed the input buffer to the Peripheral.
* @note Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must
* be called to retrieve the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -351,9 +465,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in
* HMAC SHA256 mode.
* @param hhash: HASH handle.
* @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout: Timeout value.
* @param hhash HASH handle.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@ -391,11 +505,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout: Timeout value.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@ -409,11 +523,11 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout: Timeout value.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@ -452,10 +566,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@ -469,10 +583,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@ -502,7 +616,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
(+) SHA256
(++) HAL_HMACEx_SHA256_Start_DMA()
[..] When resorting to DMA mode to enter the data in the IP for HMAC processing,
[..] When resorting to DMA mode to enter the data in the Peripheral for HMAC processing,
user must resort to HAL_HMACEx_xxx_Start_DMA() then read the resulting digest
with HAL_HASHEx_xxx_Finish().
@ -515,7 +629,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
* DMA transfers to feed the key and the input buffer to the IP.
* DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve
* the computed digest.
@ -527,9 +641,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -539,7 +653,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
* DMA transfers to feed the key and the input buffer to the IP.
* DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
@ -551,9 +665,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -597,13 +711,13 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
intiates step 2 with the first input buffer.
[..] The following buffers are next fed to the IP with a call to the API
[..] The following buffers are next fed to the Peripheral with a call to the API
HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls
to this API.
[..] Multi-buffer DMA-based HMAC computation is wrapped up by a call to
HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input
buffer to the IP then carries out step 3.
buffer to the Peripheral then carries out step 3.
[..] Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or
SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256.
@ -618,18 +732,18 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
* @note Step 1 consists in writing the inner hash function key in the IP,
* @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
* the first buffer entered to the IP. DCAL bit is not automatically set after
* the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -640,7 +754,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief MD5 HMAC step 2 in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP.
* @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
@ -648,9 +762,9 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -664,7 +778,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p
/**
* @brief MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP,
* @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
@ -674,9 +788,9 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -688,18 +802,18 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
* @note Step 1 consists in writing the inner hash function key in the IP,
* @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
* the first buffer entered to the IP. DCAL bit is not automatically set after
* the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -710,7 +824,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief SHA1 HMAC step 2 in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP.
* @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
@ -718,9 +832,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -734,7 +848,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *
/**
* @brief SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP,
* @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
@ -744,9 +858,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -757,18 +871,18 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
* @note Step 1 consists in writing the inner hash function key in the IP,
* @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
* the first buffer entered to the IP. DCAL bit is not automatically set after
* the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -779,7 +893,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8
/**
* @brief SHA224 HMAC step 2 in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP.
* @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
@ -787,9 +901,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -803,7 +917,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP,
* @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
@ -813,9 +927,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -826,18 +940,18 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8
/**
* @brief SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
* @note Step 1 consists in writing the inner hash function key in the IP,
* @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
* the first buffer entered to the IP. DCAL bit is not automatically set after
* the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -848,7 +962,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8
/**
* @brief SHA256 HMAC step 2 in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP.
* @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
@ -856,9 +970,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -872,7 +986,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP,
* @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
@ -882,9 +996,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)

72
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_hcd.c
View File

@ -42,11 +42,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* @attention
*
* <h2><center>&copy; Copyright (c) YYYY STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@ -114,6 +110,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx;
/* Check the HCD handle allocation */
if (hhcd == NULL)
{
@ -123,6 +121,8 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
/* Check the parameters */
assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
USBx = hhcd->Instance;
if (hhcd->State == HAL_HCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@ -151,6 +151,12 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
hhcd->State = HAL_HCD_STATE_BUSY;
/* Disable DMA mode for FS instance */
if ((USBx->CID & (0x1U << 8)) == 0U)
{
hhcd->Init.dma_enable = 0U;
}
/* Disable the Interrupts */
__HAL_HCD_DISABLE(hhcd);
@ -367,14 +373,13 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
uint16_t length,
uint8_t do_ping)
{
UNUSED(do_ping);
hhcd->hc[ch_num].ep_is_in = direction;
hhcd->hc[ch_num].ep_type = ep_type;
if (token == 0U)
{
hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
hhcd->hc[ch_num].do_ping = do_ping;
}
else
{
@ -528,20 +533,19 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
/* Handle Host Disconnect Interrupts */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
{
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
/* Cleanup HPRT */
USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
/* Handle Host Port Disconnect Interrupt */
if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U)
{
/* Handle Host Port Disconnect Interrupt */
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->DisconnectCallback(hhcd);
hhcd->DisconnectCallback(hhcd);
#else
HAL_HCD_Disconnect_Callback(hhcd);
HAL_HCD_Disconnect_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
}
}
/* Handle Host Port Interrupts */
@ -1003,6 +1007,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
__HAL_HCD_ENABLE(hhcd);
(void)USB_DriveVbus(hhcd->Instance, 1U);
__HAL_UNLOCK(hhcd);
return HAL_OK;
}
@ -1017,6 +1022,7 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
__HAL_LOCK(hhcd);
(void)USB_StopHost(hhcd->Instance);
__HAL_UNLOCK(hhcd);
return HAL_OK;
}
@ -1164,6 +1170,13 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR);
hhcd->hc[ch_num].state = HC_BBLERR;
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
@ -1219,6 +1232,17 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
hhcd->hc[ch_num].urb_state = URB_DONE;
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC)
{
hhcd->hc[ch_num].urb_state = URB_DONE;
hhcd->hc[ch_num].toggle_in ^= 1U;
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
#else
@ -1273,6 +1297,11 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(ch_num)->HCCHAR = tmpreg;
}
else if (hhcd->hc[ch_num].state == HC_BBLERR)
{
hhcd->hc[ch_num].ErrCnt++;
hhcd->hc[ch_num].urb_state = URB_ERROR;
}
else
{
/* ... */
@ -1300,6 +1329,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
(hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
{
hhcd->hc[ch_num].ErrCnt = 0U;
if (hhcd->Init.dma_enable == 0U)
{
hhcd->hc[ch_num].state = HC_NAK;
@ -1548,8 +1578,6 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
{
if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
{
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->ConnectCallback(hhcd);
#else
@ -1586,10 +1614,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
}
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->PortEnabledCallback(hhcd);
hhcd->ConnectCallback(hhcd);
#else
HAL_HCD_PortEnabled_Callback(hhcd);
HAL_HCD_Connect_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
@ -1600,12 +1626,6 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
#else
HAL_HCD_PortDisabled_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
/* Cleanup HPRT */
USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
}
}

45
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_i2c.c
View File

@ -223,12 +223,12 @@
*** Callback registration ***
=============================================
[..]
The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
to register an interrupt callback.
[..]
Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
@ -243,9 +243,9 @@
(+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
[..]
Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
weak function.
@ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
@ -262,9 +262,9 @@
(+) AbortCpltCallback : callback for abort completion process.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
[..]
By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
@ -273,7 +273,7 @@
these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
@ -281,7 +281,7 @@
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
or @ref HAL_I2C_Init() function.
[..]
When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@ -4737,6 +4737,13 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
/* Process locked */
__HAL_LOCK(hi2c);
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, tmpITFlags);
}
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
@ -4788,9 +4795,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
{
if (hi2c->XferCount > 0U)
{
/* Remove RXNE flag on temporary variable as read done */
tmpITFlags &= ~I2C_FLAG_RXNE;
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
@ -4844,13 +4848,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
/* Nothing to do */
}
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, tmpITFlags);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -5008,6 +5005,13 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
/* Process locked */
__HAL_LOCK(hi2c);
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
}
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
@ -5092,11 +5096,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
{
I2C_ITAddrCplt(hi2c, ITFlags);
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
}
else
{
/* Nothing to do */

115
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_irda.c
View File

@ -206,7 +206,7 @@
#define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */
#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
| USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
| USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
@ -239,7 +239,8 @@ void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
@ -475,7 +476,8 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
pIRDA_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@ -714,6 +716,7 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
While receiving data, transmission should be avoided as the data to be transmitted
could be corrupted.
[..]
(#) There are two modes of transfer:
(++) Blocking mode: the communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
@ -751,28 +754,28 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
(++) HAL_IRDA_ErrorCallback()
(#) Non-Blocking mode transfers could be aborted using Abort API's :
(+) HAL_IRDA_Abort()
(+) HAL_IRDA_AbortTransmit()
(+) HAL_IRDA_AbortReceive()
(+) HAL_IRDA_Abort_IT()
(+) HAL_IRDA_AbortTransmit_IT()
(+) HAL_IRDA_AbortReceive_IT()
(++) HAL_IRDA_Abort()
(++) HAL_IRDA_AbortTransmit()
(++) HAL_IRDA_AbortReceive()
(++) HAL_IRDA_Abort_IT()
(++) HAL_IRDA_AbortTransmit_IT()
(++) HAL_IRDA_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
(+) HAL_IRDA_AbortCpltCallback()
(+) HAL_IRDA_AbortTransmitCpltCallback()
(+) HAL_IRDA_AbortReceiveCpltCallback()
(++) HAL_IRDA_AbortCpltCallback()
(++) HAL_IRDA_AbortTransmitCpltCallback()
(++) HAL_IRDA_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
If user wants to abort it, Abort services should be called by user.
(+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
If user wants to abort it, Abort services should be called by user.
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
@endverbatim
* @{
@ -780,10 +783,13 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
/**
* @brief Send an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be sent.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Specify timeout value.
* @retval HAL status
*/
@ -866,10 +872,13 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
/**
* @brief Receive an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be received.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Specify timeout value.
* @retval HAL status
*/
@ -954,10 +963,13 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
/**
* @brief Send an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be sent.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@ -996,10 +1008,13 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData
/**
* @brief Receive an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be received.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@ -1045,10 +1060,13 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
/**
* @brief Send an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData pointer to data buffer.
* @param Size amount of data to be sent.
* @param pData pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@ -1120,12 +1138,15 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
/**
* @brief Receive an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @note When the IRDA parity is enabled (PCE = 1), the received data contains
* the parity bit (MSB position).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be received.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@ -1353,7 +1374,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
*/
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@ -1439,7 +1460,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
*/
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE and TCIE interrupts */
@ -1491,7 +1512,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
*/
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@ -1549,7 +1570,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
*/
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
{
uint32_t abortcplt = 1U;
@ -1681,7 +1702,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
*/
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE and TCIE interrupts */
@ -1759,7 +1780,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
*/
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@ -2150,7 +2171,8 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
{
/* Return IRDA handle state */
uint32_t temp1, temp2;
uint32_t temp1;
uint32_t temp2;
temp1 = (uint32_t)hirda->gState;
temp2 = (uint32_t)hirda->RxState;
@ -2212,6 +2234,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
uint32_t tmpreg;
IRDA_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK;
uint32_t pclk;
/* Check the communication parameters */
assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
@ -2235,7 +2258,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
/*-------------------------- USART GTPR Configuration ----------------------*/
MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, hirda->Init.Prescaler);
MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler);
/*-------------------------- USART BRR Configuration -----------------------*/
IRDA_GETCLOCKSOURCE(hirda, clocksource);
@ -2243,16 +2266,19 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
switch (clocksource)
{
case IRDA_CLOCKSOURCE_PCLK1:
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate));
pclk = HAL_RCC_GetPCLK1Freq();
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate));
break;
case IRDA_CLOCKSOURCE_PCLK2:
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate));
pclk = HAL_RCC_GetPCLK2Freq();
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate));
break;
case IRDA_CLOCKSOURCE_HSI:
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate));
break;
case IRDA_CLOCKSOURCE_SYSCLK:
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), hirda->Init.BaudRate));
pclk = HAL_RCC_GetSysClockFreq();
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate));
break;
case IRDA_CLOCKSOURCE_LSE:
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate));
@ -2322,7 +2348,8 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)

1458
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_lptim.c
View File

File diff suppressed because it is too large Load Diff

1156
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_mmc.c
View File

File diff suppressed because it is too large Load Diff

6
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_nand.c
View File

@ -672,7 +672,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address
/* Page(s) read loop */
while((NumPageToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
{
/* update the buffer size */
size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
@ -1026,7 +1026,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{
@ -1618,7 +1618,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{

161
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_pcd.c
View File

@ -122,6 +122,7 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx;
uint8_t i;
/* Check the PCD handle allocation */
@ -133,6 +134,8 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
USBx = hpcd->Instance;
if (hpcd->State == HAL_PCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@ -166,6 +169,12 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->State = HAL_PCD_STATE_BUSY;
/* Disable DMA mode for FS instance */
if ((USBx->CID & (0x1U << 8)) == 0U)
{
hpcd->Init.dma_enable = 0U;
}
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
@ -943,7 +952,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t i, ep_intr, epint, epnum = 0U;
uint32_t i, ep_intr, epint, epnum;
uint32_t fifoemptymsk, temp;
USB_OTG_EPTypeDef *ep;
@ -962,6 +971,38 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
}
/* Handle RxQLevel Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
{
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
temp = USBx->GRXSTSP;
ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
{
if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
{
(void)USB_ReadPacket(USBx, ep->xfer_buff,
(uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
}
}
else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
{
(void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
}
else
{
/* ... */
}
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
{
epnum = 0U;
@ -983,9 +1024,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
/* Class B setup phase done for previous decoded setup */
(void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
}
if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
@ -996,10 +1037,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/* Clear Status Phase Received interrupt */
if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
{
if (hpcd->Init.dma_enable == 1U)
{
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
}
@ -1037,16 +1074,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if (hpcd->Init.dma_enable == 1U)
{
hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if (hpcd->Init.dma_enable == 1U)
{
/* this is ZLP, so prepare EP0 for next setup */
if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
{
@ -1054,6 +1082,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
{
@ -1159,8 +1193,10 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
USBx_INEP(i)->DIEPINT = 0xFB7FU;
USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
}
USBx_DEVICE->DAINTMSK |= 0x10001U;
@ -1201,15 +1237,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
{
(void)USB_ActivateSetup(hpcd->Instance);
if (USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)
{
hpcd->Init.speed = USB_OTG_SPEED_HIGH;
}
else
{
hpcd->Init.speed = USB_OTG_SPEED_FULL;
}
hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
/* Set USB Turnaround time */
(void)USB_SetTurnaroundTime(hpcd->Instance,
@ -1225,38 +1253,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
}
/* Handle RxQLevel Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
{
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
temp = USBx->GRXSTSP;
ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
{
if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
{
(void)USB_ReadPacket(USBx, ep->xfer_buff,
(uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
}
}
else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
{
(void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
}
else
{
/* ... */
}
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
/* Handle SOF Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
{
@ -1272,6 +1268,10 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/* Handle Incomplete ISO IN Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
{
/* Keep application checking the corresponding Iso IN endpoint
causing the incomplete Interrupt */
epnum = 0U;
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
#else
@ -1284,6 +1284,10 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/* Handle Incomplete ISO OUT Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
/* Keep application checking the corresponding Iso OUT endpoint
causing the incomplete Interrupt */
epnum = 0U;
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
#else
@ -1963,16 +1967,6 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
/* Inform the upper layer that a setup packet is available */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SetupStageCallback(hpcd);
#else
HAL_PCD_SetupStageCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
}
else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
{
@ -1995,17 +1989,16 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint
hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
{
/* this is ZLP, so prepare EP0 for next setup */
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
else
@ -2038,6 +2031,12 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint
}
else
{
if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
{
/* this is ZLP, so prepare EP0 for next setup */
(void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup);
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
@ -2063,22 +2062,10 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint
uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if (hpcd->Init.dma_enable == 1U)
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
{
/* StupPktRcvd = 1 pending setup packet int */
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
}
else
{
if ((gSNPSiD == USB_OTG_CORE_ID_310A) &&
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
/* Inform the upper layer that a setup packet is available */

710
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_qspi.c
View File

File diff suppressed because it is too large Load Diff

183
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rcc.c
View File

@ -317,7 +317,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
SystemCoreClock = HSI_VALUE;
/* Adapt Systick interrupt period */
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
if (HAL_InitTick(uwTickPrio) != HAL_OK)
{
return HAL_ERROR;
}
@ -344,10 +344,11 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
uint32_t tickstart;
uint32_t pll_config;
FlagStatus pwrclkchanged = RESET;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
if (RCC_OscInitStruct == NULL)
{
return HAL_ERROR;
}
@ -356,15 +357,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
{
return HAL_ERROR;
}
@ -375,15 +376,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@ -395,9 +396,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@ -406,18 +407,18 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
{
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
{
return HAL_ERROR;
}
@ -431,7 +432,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
@ -440,9 +441,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@ -460,9 +461,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@ -471,13 +472,13 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
@ -486,9 +487,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@ -503,9 +504,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@ -513,21 +514,21 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
{
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
{
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
pwrclkchanged = SET;
}
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
{
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
@ -535,9 +536,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@ -547,15 +548,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@ -567,9 +568,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@ -577,7 +578,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
if (pwrclkchanged == SET)
{
__HAL_RCC_PWR_CLK_DISABLE();
}
@ -588,9 +589,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
{
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
@ -609,9 +610,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@ -640,9 +641,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@ -657,9 +658,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@ -668,7 +669,27 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
else
{
return HAL_ERROR;
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
#if defined (RCC_PLLCFGR_PLLR)
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
#endif
{
return HAL_ERROR;
}
}
}
return HAL_OK;
@ -705,7 +726,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
uint32_t tickstart = 0;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
if (RCC_ClkInitStruct == NULL)
{
return HAL_ERROR;
}
@ -719,30 +740,30 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
(HCLK) and the supply voltage of the device. */
/* Increasing the CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
if (FLatency > __HAL_FLASH_GET_LATENCY())
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
if (__HAL_FLASH_GET_LATENCY() != FLatency)
{
return HAL_ERROR;
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
}
@ -753,24 +774,24 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
return HAL_ERROR;
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
return HAL_ERROR;
}
@ -779,7 +800,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
return HAL_ERROR;
}
@ -800,38 +821,38 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
if (FLatency < __HAL_FLASH_GET_LATENCY())
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
if (__HAL_FLASH_GET_LATENCY() != FLatency)
{
return HAL_ERROR;
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
HAL_InitTick(uwTickPrio);
return HAL_OK;
}
@ -888,7 +909,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
assert_param(IS_RCC_MCO(RCC_MCOx));
assert_param(IS_RCC_MCODIV(RCC_MCODiv));
/* RCC_MCO1 */
if(RCC_MCOx == RCC_MCO1)
if (RCC_MCOx == RCC_MCO1)
{
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
@ -990,7 +1011,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
break;
break;
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
{
@ -1005,16 +1026,16 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2);
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
sysclockfreq = pllvco/pllp;
sysclockfreq = pllvco / pllp;
break;
}
default:
@ -1047,7 +1068,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void)
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
}
/**
@ -1059,7 +1080,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
}
/**
@ -1075,11 +1096,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
/* Get the HSE configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
{
RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
}
else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
{
RCC_OscInitStruct->HSEState = RCC_HSE_ON;
}
@ -1089,7 +1110,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Get the HSI configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
{
RCC_OscInitStruct->HSIState = RCC_HSI_ON;
}
@ -1098,14 +1119,14 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
}
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
/* Get the LSE configuration -----------------------------------------------*/
if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
{
RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
}
else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
{
RCC_OscInitStruct->LSEState = RCC_LSE_ON;
}
@ -1115,7 +1136,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Get the LSI configuration -----------------------------------------------*/
if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
{
RCC_OscInitStruct->LSIState = RCC_LSI_ON;
}
@ -1125,7 +1146,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Get the PLL configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
{
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
}
@ -1180,7 +1201,7 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF
void HAL_RCC_NMI_IRQHandler(void)
{
/* Check RCC CSSF flag */
if(__HAL_RCC_GET_IT(RCC_IT_CSS))
if (__HAL_RCC_GET_IT(RCC_IT_CSS))
{
/* RCC Clock Security System interrupt user callback */
HAL_RCC_CSSCallback();

21
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rng.c
View File

@ -532,8 +532,16 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
/**
* @brief Generates a 32-bit random number.
* @note Each time the random number data is read the RNG_FLAG_DRDY flag
* is automatically cleared.
* @note This function checks value of RNG_FLAG_DRDY flag to know if valid
* random number is available in the DR register (RNG_FLAG_DRDY flag set
* whenever a random number is available through the RNG_DR register).
* After transitioning from 0 to 1 (random number available),
* RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading
* four words from the RNG_DR register, i.e. further function calls
* will immediately return a new u32 random number (additional words are
* available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
* @note When no more random number data is available in DR register, RNG_FLAG_DRDY
* flag is automatically cleared.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @param random32bit pointer to generated random number variable if successful.
@ -697,13 +705,13 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_SEED;
hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
rngclockerror = 1U;
}
else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
hrng->ErrorCode = HAL_RNG_ERROR_SEED;
rngclockerror = 1U;
}
else
@ -768,6 +776,11 @@ uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
/**
* @brief Data Ready callback in non-blocking mode.
* @note When RNG_FLAG_DRDY flag value is set, first random number has been read
* from DR register in IRQ Handler and is provided as callback parameter.
* Depending on valid data available in the conditioning output buffer,
* additional words can be read by the application from DR register till
* DRDY bit remains high.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @param random32bit generated random number.

18
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rtc.c
View File

@ -1586,10 +1586,11 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
*/
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
{
if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))
/* Get the AlarmA interrupt source enable status */
if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != (uint32_t)RESET)
{
/* Get the status of the Interrupt */
if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)
/* Get the pending status of the AlarmA Interrupt */
if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != (uint32_t)RESET)
{
/* AlarmA callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@ -1598,15 +1599,16 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
HAL_RTC_AlarmAEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Alarm interrupt pending bit */
/* Clear the AlarmA interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
}
}
if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB))
/* Get the AlarmB interrupt source enable status */
if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != (uint32_t)RESET)
{
/* Get the status of the Interrupt */
if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)
/* Get the pending status of the AlarmB Interrupt */
if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != (uint32_t)RESET)
{
/* AlarmB callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@ -1615,7 +1617,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
HAL_RTCEx_AlarmBEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Alarm interrupt pending bit */
/* Clear the AlarmB interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
}
}

56
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rtc_ex.c
View File

@ -656,10 +656,11 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T
*/
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
{
if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))
/* Get the TimeStamp interrupt source enable status */
if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != (uint32_t)RESET)
{
/* Get the status of the Interrupt */
if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)
/* Get the pending status of the TIMESTAMP Interrupt */
if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != (uint32_t)RESET)
{
/* TIMESTAMP callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@ -673,12 +674,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
}
}
/* Get the status of the Interrupt */
if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== SET)
/* Get the Tamper1 interrupt source enable status */
if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != (uint32_t)RESET)
{
/* Get the TAMPER Interrupt enable bit and pending bit */
if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \
(((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP1IE)) != (uint32_t)RESET))
/* Get the pending status of the Tamper1 Interrupt */
if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != (uint32_t)RESET)
{
/* Tamper callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@ -692,12 +692,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
}
}
/* Get the status of the Interrupt */
if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F)== SET)
/* Get the Tamper2 interrupt source enable status */
if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != (uint32_t)RESET)
{
/* Get the TAMPER Interrupt enable bit and pending bit */
if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \
(((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP2IE)) != (uint32_t)RESET))
/* Get the pending status of the Tamper2 Interrupt */
if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != (uint32_t)RESET)
{
/* Tamper callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@ -711,12 +710,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
}
}
/* Get the status of the Interrupt */
if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F)== SET)
/* Get the Tamper3 interrupt source enable status */
if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != (uint32_t)RESET)
{
/* Get the TAMPER Interrupt enable bit and pending bit */
if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \
(((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP3IE)) != (uint32_t)RESET))
/* Get the pending status of the Tamper3 Interrupt */
if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != (uint32_t)RESET)
{
/* Tamper callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@ -1211,27 +1209,29 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
/**
* @brief This function handles Wake Up Timer interrupt request.
* @note Unlike alarm interrupt line (shared by AlarmA and AlarmB) and tamper
* interrupt line (shared by timestamp and tampers) wakeup timer
* interrupt line is exclusive to the wakeup timer.
* There is no need in this case to check on the interrupt enable
* status via __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE().
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
{
if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))
/* Get the pending status of the WAKEUPTIMER Interrupt */
if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != (uint32_t)RESET)
{
/* Get the status of the Interrupt */
if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)
{
/* WAKEUPTIMER callback */
/* WAKEUPTIMER callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->WakeUpTimerEventCallback(hrtc);
hrtc->WakeUpTimerEventCallback(hrtc);
#else
HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the WAKEUPTIMER interrupt pending bit */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
}
/* Clear the WAKEUPTIMER interrupt pending bit */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
}
/* Clear the EXTI's line Flag for RTC WakeUpTimer */

38
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sai.c
View File

@ -132,12 +132,13 @@
*** Callback registration ***
=============================
[..]
The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use functions @ref HAL_SAI_RegisterCallback() to register a user callback.
Use functions HAL_SAI_RegisterCallback() to register a user callback.
Function @ref HAL_SAI_RegisterCallback() allows to register following callbacks:
[..]
Function HAL_SAI_RegisterCallback() allows to register following callbacks:
(+) RxCpltCallback : SAI receive complete.
(+) RxHalfCpltCallback : SAI receive half complete.
(+) TxCpltCallback : SAI transmit complete.
@ -145,13 +146,16 @@
(+) ErrorCallback : SAI error.
(+) MspInitCallback : SAI MspInit.
(+) MspDeInitCallback : SAI MspDeInit.
[..]
This function takes as parameters the HAL peripheral handle, the callback ID
and a pointer to the user callback function.
Use function @ref HAL_SAI_UnRegisterCallback() to reset a callback to the default
[..]
Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
@ref HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
[..]
This function allows to reset following callbacks:
(+) RxCpltCallback : SAI receive complete.
(+) RxHalfCpltCallback : SAI receive half complete.
@ -161,23 +165,26 @@
(+) MspInitCallback : SAI MspInit.
(+) MspDeInitCallback : SAI MspDeInit.
By default, after the @ref HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
[..]
By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
examples @ref HAL_SAI_RxCpltCallback(), @ref HAL_SAI_ErrorCallback().
examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_SAI_Init
and @ref HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_SAI_Init and @ref HAL_SAI_DeInit
reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_SAI_RegisterCallback before calling @ref HAL_SAI_DeInit
or @ref HAL_SAI_Init function.
using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit
or HAL_SAI_Init function.
[..]
When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@ -228,7 +235,6 @@ typedef enum {
/** @defgroup SAI_Private_Constants SAI Private Constants
* @{
*/
#define SAI_FIFO_SIZE 8
#define SAI_DEFAULT_TIMEOUT 4 /* 4ms */
/**
* @}
@ -507,6 +513,8 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
hsai->Init.Mckdiv+= 1;
}
}
/* Check the SAI Block master clock divider parameter */
assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv));
/* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */
if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
@ -2344,7 +2352,7 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
{
SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
if (hdma->Init.Mode != DMA_CIRCULAR)
{
hsai->XferCount = 0;
@ -2390,7 +2398,7 @@ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
{
SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
if (hdma->Init.Mode != DMA_CIRCULAR)
{
/* Disable Rx DMA Request */
hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);

1577
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sd.c
View File

File diff suppressed because it is too large Load Diff

134
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_smartcard.c
View File

@ -192,8 +192,8 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
* @{
*/
* @{
*/
#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
@ -225,7 +225,8 @@ void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
@ -471,7 +472,8 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@ -584,7 +586,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart
* @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
@ -728,29 +731,30 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
(++) HAL_SMARTCARD_RxCpltCallback()
(++) HAL_SMARTCARD_ErrorCallback()
[..]
(#) Non-Blocking mode transfers could be aborted using Abort API's :
(+) HAL_SMARTCARD_Abort()
(+) HAL_SMARTCARD_AbortTransmit()
(+) HAL_SMARTCARD_AbortReceive()
(+) HAL_SMARTCARD_Abort_IT()
(+) HAL_SMARTCARD_AbortTransmit_IT()
(+) HAL_SMARTCARD_AbortReceive_IT()
(++) HAL_SMARTCARD_Abort()
(++) HAL_SMARTCARD_AbortTransmit()
(++) HAL_SMARTCARD_AbortReceive()
(++) HAL_SMARTCARD_Abort_IT()
(++) HAL_SMARTCARD_AbortTransmit_IT()
(++) HAL_SMARTCARD_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
(+) HAL_SMARTCARD_AbortCpltCallback()
(+) HAL_SMARTCARD_AbortTransmitCpltCallback()
(+) HAL_SMARTCARD_AbortReceiveCpltCallback()
(++) HAL_SMARTCARD_AbortCpltCallback()
(++) HAL_SMARTCARD_AbortTransmitCpltCallback()
(++) HAL_SMARTCARD_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
If user wants to abort it, Abort services should be called by user.
(+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
If user wants to abort it, Abort services should be called by user.
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
@endverbatim
* @{
@ -765,7 +769,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
uint32_t Timeout)
{
uint32_t tickstart;
uint8_t *ptmpdata = pData;
@ -811,7 +816,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
ptmpdata++;
}
if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK)
if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart,
Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@ -848,7 +854,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
uint32_t Timeout)
{
uint32_t tickstart;
uint8_t *ptmpdata = pData;
@ -1059,7 +1066,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard
hsmartcard->hdmatx->XferAbortCallback = NULL;
/* Enable the SMARTCARD transmit DMA channel */
if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size) == HAL_OK)
if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR,
Size) == HAL_OK)
{
/* Clear the TC flag in the ICR register */
CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
@ -1135,7 +1143,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard,
hsmartcard->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size) == HAL_OK)
if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr,
Size) == HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
@ -1188,7 +1197,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR1,
(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
/* Disable the SMARTCARD DMA Tx request if enabled */
@ -1246,7 +1256,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
hsmartcard->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@ -1375,7 +1387,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard
hsmartcard->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@ -1403,7 +1417,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
uint32_t abortcplt = 1U;
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR1,
(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
/* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
@ -1500,7 +1515,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@ -1627,7 +1644,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
*/
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@ -1669,7 +1686,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc
hsmartcard->RxISR = NULL;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@ -1693,7 +1712,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc
hsmartcard->RxISR = NULL;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@ -1731,7 +1752,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* SMARTCARD in mode Receiver ---------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE) != 0U)
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
{
if (hsmartcard->RxISR != NULL)
{
@ -1793,7 +1814,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* SMARTCARD in mode Receiver ---------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE) != 0U)
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
{
if (hsmartcard->RxISR != NULL)
{
@ -1946,7 +1967,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
/* SMARTCARD in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_ISR_TXE) != 0U)
&& ((cr1its & USART_CR1_TXEIE) != 0U))
&& ((cr1its & USART_CR1_TXEIE) != 0U))
{
if (hsmartcard->TxISR != NULL)
{
@ -1958,7 +1979,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
/* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
{
if(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
{
SMARTCARD_EndTransmit_IT(hsmartcard);
return;
@ -2095,7 +2116,8 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsma
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Return SMARTCARD handle state */
uint32_t temp1, temp2;
uint32_t temp1;
uint32_t temp2;
temp1 = (uint32_t)hsmartcard->gState;
temp2 = (uint32_t)hsmartcard->RxState;
@ -2155,6 +2177,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
uint32_t tmpreg;
SMARTCARD_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK;
uint32_t pclk;
/* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
@ -2177,7 +2200,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
* Configure the Parity and Mode:
* set PS bit according to hsmartcard->Init.Parity value
* set TE and RE bits according to hsmartcard->Init.Mode value */
tmpreg = (uint32_t) (hsmartcard->Init.Parity | hsmartcard->Init.Mode | hsmartcard->Init.WordLength);
tmpreg = (uint32_t)(hsmartcard->Init.Parity | hsmartcard->Init.Mode | hsmartcard->Init.WordLength);
MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/
@ -2220,16 +2243,19 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
switch (clocksource)
{
case SMARTCARD_CLOCKSOURCE_PCLK1:
tmpreg = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
pclk = HAL_RCC_GetPCLK1Freq();
tmpreg = (uint16_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_PCLK2:
tmpreg = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
pclk = HAL_RCC_GetPCLK2Freq();
tmpreg = (uint16_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_HSI:
tmpreg = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_SYSCLK:
tmpreg = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
pclk = HAL_RCC_GetSysClockFreq();
tmpreg = (uint16_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_LSE:
tmpreg = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
@ -2340,7 +2366,8 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar
if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
/* Wait until TEACK flag is set */
if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart,
SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
{
/* Timeout occurred */
return HAL_TIMEOUT;
@ -2367,7 +2394,8 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar
* @param Timeout Timeout duration.
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
@ -2491,7 +2519,7 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
/* Stop SMARTCARD DMA Tx request if ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
{
if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
{
hsmartcard->TxXferCount = 0U;
SMARTCARD_EndTxTransfer(hsmartcard);
@ -2570,7 +2598,9 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@ -2617,7 +2647,9 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@ -2677,7 +2709,9 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
hsmartcard->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;

24
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_smartcard_ex.c
View File

@ -165,12 +165,6 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef
/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions
* @brief SMARTCARD Transmit and Receive functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..]
@endverbatim
* @{
*/
@ -178,28 +172,12 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef
* @}
*/
/** @defgroup SMARTCARD_Exported_Functions_Group3 Extended Peripheral Peripheral Control functions
* @brief SMARTCARD control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
@endverbatim
* @{
*/
/**
* @}
*/
/**
* @}
*/
/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended private Functions
/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended Private Functions
* @{
*/

16
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_smbus.c
View File

@ -89,12 +89,12 @@
*** Callback registration ***
=============================================
[..]
The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback()
to register an interrupt callback.
[..]
Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
@ -106,9 +106,9 @@
(+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback.
[..]
Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
weak function.
@ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
@ -122,9 +122,9 @@
(+) ErrorCallback : callback for error detection.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback.
[..]
By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
@ -133,7 +133,7 @@
these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
@ -141,7 +141,7 @@
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
or @ref HAL_SMBUS_Init() function.
[..]
When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.

119
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_tim.c
View File

@ -98,18 +98,22 @@
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
[..]
Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
@ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
the Callback ID and a pointer to the user callback function.
[..]
Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
[..]
These functions allow to register/unregister following callbacks:
(+) Base_MspInitCallback : TIM Base Msp Init Callback.
(+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
@ -140,15 +144,18 @@
(+) BreakCallback : TIM Break Callback.
(+) Break2Callback : TIM Break2 Callback.
[..]
By default, after the Init and when the state is HAL_TIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
[..]
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
functionalities in the Init / DeInit only when these callbacks are null
(not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
[..]
Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
Exception done MspInit / MspDeInit that can be registered / unregistered
in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
@ -156,6 +163,7 @@ all interrupt callbacks are set to the corresponding weak functions:
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
[..]
When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@ -216,7 +224,7 @@ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig);
TIM_SlaveConfigTypeDef *sSlaveConfig);
/**
* @}
*/
@ -227,8 +235,8 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
*/
/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
* @brief Time Base functions
*
* @brief Time Base functions
*
@verbatim
==============================================================================
##### Time Base functions #####
@ -559,8 +567,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
*/
/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
* @brief TIM Output Compare functions
*
* @brief TIM Output Compare functions
*
@verbatim
==============================================================================
##### TIM Output Compare functions #####
@ -929,7 +937,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
uint32_t tmpsmcr;
uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@ -1136,8 +1144,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
* @brief TIM PWM functions
*
* @brief TIM PWM functions
*
@verbatim
==============================================================================
##### TIM PWM functions #####
@ -1714,8 +1722,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
*/
/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
* @brief TIM Input Capture functions
*
* @brief TIM Input Capture functions
*
@verbatim
==============================================================================
##### TIM Input Capture functions #####
@ -2249,8 +2257,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
* @brief TIM One Pulse functions
*
* @brief TIM One Pulse functions
*
@verbatim
==============================================================================
##### TIM One Pulse functions #####
@ -2563,8 +2571,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
*/
/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
* @brief TIM Encoder functions
*
* @brief TIM Encoder functions
*
@verbatim
==============================================================================
##### TIM Encoder functions #####
@ -2609,15 +2617,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
}
/* Check the parameters */
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
@ -2775,7 +2783,7 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Enable the encoder interface channels */
switch (Channel)
@ -2819,7 +2827,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@ -2865,7 +2873,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Enable the encoder interface channels */
/* Enable the capture compare Interrupts 1 and/or 2 */
@ -2915,7 +2923,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@ -2966,10 +2974,11 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
* @param Length The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
uint32_t *pData2, uint16_t Length)
{
/* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
if (htim->State == HAL_TIM_STATE_BUSY)
{
@ -3103,7 +3112,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@ -3149,8 +3158,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
* @}
*/
/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
* @brief TIM IRQ handler management
*
* @brief TIM IRQ handler management
*
@verbatim
==============================================================================
##### IRQ handler management #####
@ -3363,8 +3372,8 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
*/
/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
* @brief TIM Peripheral Control functions
*
* @brief TIM Peripheral Control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
@ -3738,9 +3747,14 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @note To output a waveform with a minimum delay user can enable the fast
* mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
* output is forced in response to the edge detection on TIx input,
* without taking in account the comparison.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
uint32_t OutputChannel, uint32_t InputChannel)
{
TIM_OC_InitTypeDef temp1;
@ -3941,7 +3955,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@ -3957,7 +3972,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@ -3973,7 +3989,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@ -3989,7 +4006,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@ -4005,7 +4023,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@ -4021,7 +4040,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@ -4151,8 +4171,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
* @note This function should be used only when BurstLength is equal to DMA data transfer length.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
uint32_t *BurstBuffer, uint32_t BurstLength)
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
@ -4465,7 +4485,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
/* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
{
htim->State = HAL_TIM_STATE_READY;
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_ERROR;
}
@ -4780,9 +4800,9 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC
htim->State = HAL_TIM_STATE_BUSY;
if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
{
htim->State = HAL_TIM_STATE_READY;
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_ERROR;
}
@ -4810,7 +4830,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig)
TIM_SlaveConfigTypeDef *sSlaveConfig)
{
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
@ -4821,9 +4841,9 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
htim->State = HAL_TIM_STATE_BUSY;
if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
{
htim->State = HAL_TIM_STATE_READY;
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_ERROR;
}
@ -4913,8 +4933,8 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
* @brief TIM Callbacks functions
*
* @brief TIM Callbacks functions
*
@verbatim
==============================================================================
##### TIM Callbacks functions #####
@ -5118,7 +5138,8 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
* @param pCallback pointer to the callback function
* @retval status
*/
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
pTIM_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@ -5578,8 +5599,8 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
*/
/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
* @brief TIM Peripheral State functions
*
* @brief TIM Peripheral State functions
*
@verbatim
==============================================================================
##### Peripheral State functions #####
@ -6365,7 +6386,7 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
* @retval None
*/
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig)
TIM_SlaveConfigTypeDef *sSlaveConfig)
{
uint32_t tmpsmcr;
uint32_t tmpccmr1;

51
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_tim_ex.c
View File

@ -73,7 +73,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
@ -1466,7 +1466,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@ -1521,7 +1522,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@ -1577,7 +1579,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@ -1632,7 +1635,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
@ -1665,16 +1668,19 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
@ -1690,6 +1696,9 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
* @param htim TIM handle
* @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
* contains the BDTR Register configuration information for the TIM peripheral.
* @note Interrupts can be generated when an active level is detected on the
* break input, the break 2 input or the system break input. Break
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
@ -1763,10 +1772,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
{
uint32_t tmporx;
uint32_t bkin_enable_mask = 0U;
uint32_t bkin_polarity_mask = 0U;
uint32_t bkin_enable_bitpos = 0U;
uint32_t bkin_polarity_bitpos = 0U;
uint32_t bkin_enable_mask;
uint32_t bkin_polarity_mask;
uint32_t bkin_enable_bitpos;
uint32_t bkin_polarity_bitpos;
/* Check the parameters */
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
@ -1800,11 +1809,19 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
{
bkin_enable_mask = TIM1_AF1_BKDF1BKE;
bkin_enable_bitpos = 8;
bkin_polarity_mask = 0U;
bkin_polarity_bitpos = 0U;
break;
}
default:
{
bkin_enable_mask = 0U;
bkin_polarity_mask = 0U;
bkin_enable_bitpos = 0U;
bkin_polarity_bitpos = 0U;
break;
}
}
switch (BreakInput)
@ -2054,7 +2071,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/

345
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_uart.c
View File

@ -326,7 +326,6 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the UART Communication parameters */
@ -346,7 +345,6 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
@ -393,7 +391,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the UART Communication parameters */
@ -416,7 +413,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
/* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
@ -481,7 +477,6 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the UART Communication parameters */
@ -507,7 +502,6 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
/* Set the USART LIN Break detection length. */
MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
@ -567,7 +561,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the UART Communication parameters */
@ -596,7 +589,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
/* Set the wake up method by setting the WAKE bit in the CR1 register */
MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
@ -622,7 +614,6 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
huart->Instance->CR1 = 0x0U;
@ -645,7 +636,6 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_RESET;
huart->RxState = HAL_UART_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(huart);
return HAL_OK;
@ -704,18 +694,18 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
pUART_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(huart);
if (huart->gState == HAL_UART_STATE_READY)
@ -768,10 +758,8 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_
break;
default :
/* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
@ -789,24 +777,19 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_
break;
default :
/* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(huart);
return status;
@ -837,7 +820,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(huart);
if (HAL_UART_STATE_READY == huart->gState)
@ -876,6 +858,12 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR
huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
break;
#if defined(USART_CR1_UESM)
case HAL_UART_WAKEUP_CB_ID :
huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
break;
#endif /* USART_CR1_UESM */
case HAL_UART_MSPINIT_CB_ID :
huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */
break;
@ -885,10 +873,8 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR
break;
default :
/* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
@ -906,24 +892,19 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR
break;
default :
/* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(huart);
return status;
@ -992,6 +973,11 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR
(+) HAL_UART_AbortCpltCallback()
(+) HAL_UART_AbortTransmitCpltCallback()
(+) HAL_UART_AbortReceiveCpltCallback()
#if defined(USART_CR1_UESM)
(#) Wakeup from Stop mode Callback:
(+) HAL_UARTEx_WakeupCallback()
#endif
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
@ -1013,9 +999,12 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR
/**
* @brief Send an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pData.
* @param huart UART handle.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be sent.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@ -1033,7 +1022,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
@ -1045,7 +1033,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
huart->TxXferSize = Size;
huart->TxXferCount = Size;
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
pdata8bits = NULL;
@ -1057,6 +1045,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
pdata16bits = NULL;
}
__HAL_UNLOCK(huart);
while (huart->TxXferCount > 0U)
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
@ -1084,9 +1074,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
else
@ -1097,9 +1084,12 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
/**
* @brief Receive an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pData.
* @param huart UART handle.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be received.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@ -1118,7 +1108,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
@ -1146,6 +1135,8 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
pdata16bits = NULL;
}
__HAL_UNLOCK(huart);
/* as long as data have to be received */
while (huart->RxXferCount > 0U)
{
@ -1169,9 +1160,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
else
@ -1182,9 +1170,12 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
/**
* @brief Send an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pData.
* @param huart UART handle.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be sent.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@ -1197,7 +1188,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(huart);
huart->pTxBuffPtr = pData;
@ -1218,7 +1208,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
huart->TxISR = UART_TxISR_8BIT;
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the Transmit Data Register Empty interrupt */
@ -1234,9 +1223,12 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
/**
* @brief Receive an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pData.
* @param huart UART handle.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be received.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@ -1249,7 +1241,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(huart);
huart->pRxBuffPtr = pData;
@ -1276,7 +1267,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
huart->RxISR = UART_RxISR_8BIT;
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
@ -1292,9 +1282,12 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
/**
* @brief Send an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pData.
* @param huart UART handle.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be sent.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@ -1307,7 +1300,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(huart);
huart->pTxBuffPtr = pData;
@ -1337,7 +1329,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Restore huart->gState to ready */
@ -1349,7 +1340,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
/* Clear the TC flag in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
@ -1368,9 +1358,12 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
* @brief Receive an amount of data in DMA mode.
* @note When the UART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pData.
* @param huart UART handle.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be received.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@ -1383,7 +1376,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(huart);
huart->pRxBuffPtr = pData;
@ -1412,7 +1404,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Restore huart->gState to ready */
@ -1421,7 +1412,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
return HAL_ERROR;
}
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error Interrupt */
@ -1452,7 +1442,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
const HAL_UART_StateTypeDef gstate = huart->gState;
const HAL_UART_StateTypeDef rxstate = huart->RxState;
/* Process Locked */
__HAL_LOCK(huart);
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
@ -1472,7 +1461,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@ -1485,7 +1473,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
*/
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
if (huart->gState == HAL_UART_STATE_BUSY_TX)
@ -1506,7 +1493,6 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@ -1591,7 +1577,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
*/
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
{
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@ -1663,7 +1649,6 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
/* Reset Handle ErrorCode to No Error */
huart->ErrorCode = HAL_UART_ERROR_NONE;
return HAL_OK;
@ -1680,7 +1665,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
*/
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
{
/* Disable TXEIE and TCIE interrupts */
@ -1732,7 +1717,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
*/
HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@ -1792,7 +1777,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
*/
HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
{
uint32_t abortcplt = 1U;
@ -1931,7 +1916,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
*/
HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
{
/* Disable interrupts */
@ -2015,7 +2000,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
*/
HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@ -2110,7 +2095,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
if (errorflags == 0U)
{
/* UART in mode Receiver ---------------------------------------------------*/
@ -2164,10 +2149,18 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
huart->ErrorCode |= HAL_UART_ERROR_ORE;
}
/* Call UART Error Call back function if need be --------------------------*/
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
huart->ErrorCode |= HAL_UART_ERROR_RTO;
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
{
/* UART in mode Receiver ---------------------------------------------------*/
/* UART in mode Receiver --------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE) != 0U)
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
{
@ -2177,11 +2170,14 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
}
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
/* If Error is to be considered as blocking :
- Receiver Timeout error in Reception
- Overrun error in Reception
- any error occurs in DMA mode reception
*/
errorcode = huart->ErrorCode;
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
((errorcode & HAL_UART_ERROR_ORE) != 0U))
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
@ -2249,6 +2245,26 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
return;
} /* End if some error occurs */
#if defined(USART_CR1_UESM)
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
/* UART Rx state is not reset as a reception process might be ongoing.
If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Wakeup Callback */
huart->WakeupCallback(huart);
#else
/* Call legacy weak Wakeup Callback */
HAL_UARTEx_WakeupCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
}
#endif /* USART_CR1_UESM */
/* UART in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_ISR_TXE) != 0U)
@ -2390,6 +2406,23 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
*/
}
#if defined(USART_CR1_UESM)
/**
* @brief UART wakeup from Stop mode callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
*/
}
#endif /* USART_CR1_UESM */
/**
* @}
*/
@ -2403,6 +2436,9 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
===============================================================================
[..]
This subsection provides a set of functions allowing to control the UART.
(+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
(+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
(+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
(+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
(+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
(+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
@ -2416,6 +2452,82 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
* @{
*/
/**
* @brief Update on the fly the receiver timeout value in RTOR register.
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param TimeoutValue receiver timeout value in number of baud blocks. The timeout
* value must be less or equal to 0x0FFFFFFFF.
* @retval None
*/
void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
{
assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
}
/**
* @brief Enable the UART receiver timeout feature.
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
{
if (huart->gState == HAL_UART_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
/* Set the USART RTOEN bit */
SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Disable the UART receiver timeout feature.
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
{
if (huart->gState == HAL_UART_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
/* Clear the USART RTOEN bit */
CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Enable UART in mute mode (does not mean UART enters mute mode;
* to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
@ -2424,7 +2536,6 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
*/
HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
@ -2445,7 +2556,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
*/
HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
@ -2476,7 +2586,6 @@ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
@ -2488,7 +2597,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@ -2501,7 +2609,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
@ -2513,7 +2620,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@ -2530,7 +2636,6 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
/* Check the parameters */
assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
@ -2540,7 +2645,6 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@ -2551,8 +2655,8 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
*/
/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
* @brief UART Peripheral State functions
*
* @brief UART Peripheral State functions
*
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
@ -2574,7 +2678,8 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
*/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
{
uint32_t temp1, temp2;
uint32_t temp1;
uint32_t temp2;
temp1 = huart->gState;
temp2 = huart->RxState;
@ -2586,7 +2691,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART.
* @retval UART Error Code
*/
*/
uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
{
return huart->ErrorCode;
@ -2620,6 +2725,9 @@ void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
#if defined(USART_CR1_UESM)
huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
#endif /* USART_CR1_UESM */
}
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@ -2636,6 +2744,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv = 0x00000000U;
HAL_StatusTypeDef ret = HAL_OK;
uint32_t pclk;
/* Check the parameters */
assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
@ -2683,21 +2792,23 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
switch (clocksource)
{
case UART_CLOCKSOURCE_PCLK1:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
pclk = HAL_RCC_GetPCLK1Freq();
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_PCLK2:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
pclk = HAL_RCC_GetPCLK2Freq();
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_HSI:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_SYSCLK:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
pclk = HAL_RCC_GetSysClockFreq();
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
@ -2720,21 +2831,23 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
switch (clocksource)
{
case UART_CLOCKSOURCE_PCLK1:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
pclk = HAL_RCC_GetPCLK1Freq();
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_PCLK2:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
pclk = HAL_RCC_GetPCLK2Freq();
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_HSI:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_SYSCLK:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
pclk = HAL_RCC_GetSysClockFreq();
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
@ -2858,12 +2971,24 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
return HAL_TIMEOUT;
}
}
#if defined(USART_ISR_REACK)
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
{
/* Timeout occurred */
return HAL_TIMEOUT;
}
}
#endif
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@ -2878,7 +3003,8 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
@ -2895,11 +3021,32 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_TIMEOUT;
}
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
huart->ErrorCode = HAL_UART_ERROR_RTO;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_TIMEOUT;
}
}
}
}
return HAL_OK;

193
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_uart_ex.c
View File

@ -57,6 +57,9 @@
/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
* @{
*/
#if defined(USART_CR1_UESM)
static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
#endif /* USART_CR1_UESM */
/**
* @}
*/
@ -144,7 +147,8 @@
* oversampling rate).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
uint32_t DeassertionTime)
{
uint32_t temp;
@ -224,42 +228,74 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
* @}
*/
/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
* @brief Extended functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
This subsection provides a set of Wakeup and FIFO mode related callback functions.
@endverbatim
* @{
*/
/**
* @}
*/
/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
* @brief Extended Peripheral Control functions
*
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides the following functions:
(+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode
(+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality
(+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
detection length to more than 4 bits for multiprocessor address mark wake up.
#if defined(USART_CR1_UESM)
(+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
trigger: address match, Start Bit detection or RXNE bit status.
(+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
(+) HAL_UARTEx_DisableStopMode() API disables the above functionality
#endif
@endverbatim
* @{
*/
#if defined(USART_CR3_UCESM)
/**
* @brief Keep UART Clock enabled when in Stop Mode.
* @note When the USART clock source is configured to be LSE or HSI, it is possible to keep enabled
* this clock during STOP mode by setting the UCESM bit in USART_CR3 control register.
* @note When LPUART is used to wakeup from stop with LSE is selected as LPUART clock source,
* and desired baud rate is 9600 baud, the bit UCESM bit in LPUART_CR3 control register must be set.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
/* Set UCESM bit */
SET_BIT(huart->Instance->CR3, USART_CR3_UCESM);
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
/**
* @brief Disable UART Clock when in Stop Mode.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
/* Clear UCESM bit */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM);
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
#endif /* USART_CR3_UCESM */
/**
* @brief By default in multiprocessor mode, when the wake up method is set
* to address mark, the UART handles only 4-bit long addresses detection;
@ -299,8 +335,108 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua
return (UART_CheckIdleState(huart));
}
#if defined(USART_CR1_UESM)
/**
* @brief Set Wakeup from Stop mode interrupt flag selection.
* @note It is the application responsibility to enable the interrupt used as
* usart_wkup interrupt source before entering low-power mode.
* @param huart UART handle.
* @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
* This parameter can be one of the following values:
* @arg @ref UART_WAKEUP_ON_ADDRESS
* @arg @ref UART_WAKEUP_ON_STARTBIT
* @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart;
/* check the wake-up from stop mode UART instance */
assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
/* check the wake-up selection parameter */
assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the wake-up selection scheme */
MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
{
UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
}
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
{
status = HAL_TIMEOUT;
}
else
{
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
return status;
}
/**
* @brief Enable UART Stop Mode.
* @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
/* Set UESM bit */
SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
/**
* @brief Disable UART Stop Mode.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
/* Clear UESM bit */
CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
#endif /* USART_CR1_UESM */
/**
* @}
*/
@ -312,6 +448,25 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua
/** @addtogroup UARTEx_Private_Functions
* @{
*/
#if defined(USART_CR1_UESM)
/**
* @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
* @param huart UART handle.
* @param WakeUpSelection UART wake up from stop mode parameters.
* @retval None
*/
static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
{
assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
/* Set the USART address length */
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
/* Set the USART address node */
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
}
#endif /* USART_CR1_UESM */
/**
* @}

142
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_usart.c
View File

@ -181,7 +181,8 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma);
static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
static void USART_TxISR_8BIT(USART_HandleTypeDef *husart);
@ -303,14 +304,15 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
- HDSEL, SCEN and IREN bits in the USART_CR3 register.
*/
husart->Instance->CR2 &= ~USART_CR2_LINEN;
husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
/* Enable the Peripheral */
__HAL_USART_ENABLE(husart);
/* TEACK to check before moving husart->State to Ready */
/* TEACK and/or REACK to check before moving husart->State to Ready */
return (USART_CheckIdleState(husart));
}
@ -406,7 +408,8 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
* @param pCallback pointer to the Callback function
* @retval HAL status
+ */
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
pUSART_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@ -701,9 +704,12 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
/**
* @brief Simplex send an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
* @param pTxData Pointer to data buffer.
* @param Size Amount of data to be sent.
* @param pTxData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@ -794,10 +800,13 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
/**
* @brief Receive an amount of data in blocking mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
* @param pRxData Pointer to data buffer.
* @param Size Amount of data to be received.
* @param pRxData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@ -896,14 +905,18 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
/**
* @brief Full-Duplex Send and Receive an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
* @param pTxData pointer to TX data buffer.
* @param pRxData pointer to RX data buffer.
* @param Size amount of data to be sent (same amount to be received).
* @param pTxData pointer to TX data buffer (u8 or u16 data elements).
* @param pRxData pointer to RX data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout)
{
uint8_t *prxdata8bits;
uint16_t *prxdata16bits;
@ -1041,9 +1054,12 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
/**
* @brief Send an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
* @param pTxData pointer to data buffer.
* @param Size amount of data to be sent.
* @param pTxData pointer to data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
@ -1100,10 +1116,13 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
/**
* @brief Receive an amount of data in interrupt mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
* @param pRxData pointer to data buffer.
* @param Size amount of data to be received.
* @param pRxData pointer to data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
@ -1168,13 +1187,17 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
/**
* @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
* @param pTxData pointer to TX data buffer.
* @param pRxData pointer to RX data buffer.
* @param Size amount of data to be sent (same amount to be received).
* @param pTxData pointer to TX data buffer (u8 or u16 data elements).
* @param pRxData pointer to RX data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
if (husart->State == HAL_USART_STATE_READY)
@ -1235,9 +1258,12 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
/**
* @brief Send an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
* @param pTxData pointer to data buffer.
* @param Size amount of data to be sent.
* @param pTxData pointer to data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
@ -1316,10 +1342,13 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
* @brief Receive an amount of data in DMA mode.
* @note When the USART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
* @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
* @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
* @param pRxData pointer to data buffer.
* @param Size amount of data to be received.
* @param pRxData pointer to data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
@ -1428,13 +1457,17 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
* @param pTxData pointer to TX data buffer.
* @param pRxData pointer to RX data buffer.
* @param Size amount of data to be received/sent.
* @param pTxData pointer to TX data buffer (u8 or u16 data elements).
* @param pRxData pointer to RX data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be received/sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
HAL_StatusTypeDef status;
uint32_t *tmp;
@ -1700,7 +1733,7 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
*/
HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
{
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
@ -1789,7 +1822,7 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
*/
HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
{
uint32_t abortcplt = 1U;
@ -1924,7 +1957,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
if (errorflags == 0U)
{
/* USART in mode Receiver ---------------------------------------------------*/
@ -1978,6 +2011,14 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
husart->ErrorCode |= HAL_USART_ERROR_ORE;
}
/* USART Receiver Timeout interrupt occurred ---------------------------------*/
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF);
husart->ErrorCode |= HAL_USART_ERROR_RTO;
}
/* Call USART Error Call back function if need be --------------------------*/
if (husart->ErrorCode != HAL_USART_ERROR_NONE)
@ -2206,8 +2247,8 @@ __weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart)
*/
/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
* @brief USART Peripheral State and Error functions
*
* @brief USART Peripheral State and Error functions
*
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
@ -2253,8 +2294,8 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
*/
/** @defgroup USART_Private_Functions USART Private Functions
* @{
*/
* @{
*/
/**
* @brief Initialize the callbacks to their default values.
@ -2591,7 +2632,8 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
* @param Timeout timeout duration.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
@ -2625,6 +2667,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
HAL_StatusTypeDef ret = HAL_OK;
uint16_t brrtemp;
uint32_t usartdiv = 0x00000000;
uint32_t pclk;
/* Check the parameters */
assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
@ -2666,16 +2709,19 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
switch (clocksource)
{
case USART_CLOCKSOURCE_PCLK1:
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate));
pclk = HAL_RCC_GetPCLK1Freq();
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate));
break;
case USART_CLOCKSOURCE_PCLK2:
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate));
pclk = HAL_RCC_GetPCLK2Freq();
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate));
break;
case USART_CLOCKSOURCE_HSI:
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate));
break;
case USART_CLOCKSOURCE_SYSCLK:
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate));
pclk = HAL_RCC_GetSysClockFreq();
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate));
break;
case USART_CLOCKSOURCE_LSE:
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate));
@ -2730,6 +2776,18 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
return HAL_TIMEOUT;
}
}
#if defined(USART_ISR_REACK)
/* Check if the Receiver is enabled */
if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
{
/* Wait until REACK flag is set */
if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
{
/* Timeout occurred */
return HAL_TIMEOUT;
}
}
#endif
/* Initialize the USART state*/
husart->State = HAL_USART_STATE_READY;

35
stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_wwdg.c
View File

@ -32,17 +32,19 @@
(++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Typical values:
(++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler:
max timeout before reset: ~73.14µs
(++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 128:
max timeout before reset: ~599.18ms
(++) Counter min (T[5;0] = 0x00) @54MHz (PCLK1) with zero prescaler:
max timeout before reset: approximately 75.85µs
(++) Counter max (T[5;0] = 0x3F) @54MHz (PCLK1) with prescaler dividing by 8:
max timeout before reset: approximately 38.83ms
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** Common driver usage ***
===========================
[..]
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
(+) Set the WWDG prescaler, refresh window and counter value
using HAL_WWDG_Init() function.
@ -59,9 +61,10 @@
HAL_WWDG_Refresh() function. This operation must occur only when
the counter is lower than the refresh window value already programmed.
[..]
*** Callback registration ***
=============================
[..]
The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
the user to configure dynamically the driver callbacks. Use Functions
@ref HAL_WWDG_RegisterCallback() to register a user callback.
@ -80,11 +83,13 @@
(++) EwiCallback : callback for Early WakeUp Interrupt.
(++) MspInitCallback : WWDG MspInit.
[..]
When calling @ref HAL_WWDG_Init function, callbacks are reset to the
corresponding legacy weak (surcharged) functions:
@ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
not been registered before.
[..]
When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@ -138,8 +143,8 @@
*/
/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions.
*
* @brief Initialization and Configuration functions.
*
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
@ -178,12 +183,12 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
/* Reset Callback pointers */
if(hwwdg->EwiCallback == NULL)
if (hwwdg->EwiCallback == NULL)
{
hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
}
if(hwwdg->MspInitCallback == NULL)
if (hwwdg->MspInitCallback == NULL)
{
hwwdg->MspInitCallback = HAL_WWDG_MspInit;
}
@ -242,13 +247,13 @@ HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_
{
HAL_StatusTypeDef status = HAL_OK;
if(pCallback == NULL)
if (pCallback == NULL)
{
status = HAL_ERROR;
}
else
{
switch(CallbackID)
switch (CallbackID)
{
case HAL_WWDG_EWI_CB_ID:
hwwdg->EwiCallback = pCallback;
@ -282,7 +287,7 @@ HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWD
{
HAL_StatusTypeDef status = HAL_OK;
switch(CallbackID)
switch (CallbackID)
{
case HAL_WWDG_EWI_CB_ID:
hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
@ -306,8 +311,8 @@ HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWD
*/
/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
* @brief IO operation functions
*
@verbatim
==============================================================================
##### IO operation functions #####

21
stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_gpio.c
View File

@ -220,9 +220,6 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
if (currentpin)
{
/* Pin Mode configuration */
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
/* Check Speed mode parameters */
@ -230,6 +227,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
/* Speed mode configuration */
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
/* Check Output mode parameters */
assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
/* Output mode configuration*/
LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
}
/* Pull-up Pull down resistor configuration*/
@ -250,19 +253,11 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
}
}
/* Pin Mode configuration */
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
}
pinpos++;
}
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
/* Check Output mode parameters */
assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
/* Output mode configuration*/
LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
}
return (SUCCESS);
}

192
stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_lptim.c
View File

@ -21,18 +21,20 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_lptim.h"
#include "stm32f7xx_ll_bus.h"
#include "stm32f7xx_ll_rcc.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
#if defined (LPTIM1) || defined (LPTIM2)
#if defined (LPTIM1)
/** @addtogroup LPTIM_LL
* @{
@ -46,28 +48,35 @@
* @{
*/
#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
|| ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
|| ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
|| ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
|| ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
#define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
|| ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
|| ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup LPTIM_LL_Exported_Functions
* @{
@ -84,7 +93,7 @@
* - SUCCESS: LPTIMx registers are de-initialized
* - ERROR: invalid LPTIMx instance
*/
ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx)
ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx)
{
ErrorStatus result = SUCCESS;
@ -96,13 +105,6 @@ ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx)
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
}
#if defined(LPTIM2)
else if (LPTIMx == LPTIM2)
{
LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2);
LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2);
}
#endif
else
{
result = ERROR;
@ -117,7 +119,7 @@ ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx)
* @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
* @retval None
*/
void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
{
/* Set the default configuration */
LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL;
@ -136,19 +138,9 @@ void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
* - SUCCESS: LPTIMx instance has been initialized
* - ERROR: LPTIMx instance hasn't been initialized
*/
ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
{
ErrorStatus result = SUCCESS;
/* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled
(ENABLE bit is reset to 0).
*/
if (LL_LPTIM_IsEnabled(LPTIMx))
{
result = ERROR;
}
else
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(LPTIMx));
assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
@ -156,21 +148,133 @@ ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_In
assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
/* Set CKSEL bitfield according to ClockSource value */
/* Set PRESC bitfield according to Prescaler value */
/* Set WAVE bitfield according to Waveform value */
/* Set WAVEPOL bitfield according to Polarity value */
MODIFY_REG(LPTIMx->CFGR,
(LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE| LPTIM_CFGR_WAVPOL),
LPTIM_InitStruct->ClockSource | \
LPTIM_InitStruct->Prescaler | \
LPTIM_InitStruct->Waveform | \
LPTIM_InitStruct->Polarity);
/* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled
(ENABLE bit is reset to 0).
*/
if (LL_LPTIM_IsEnabled(LPTIMx) == 1UL)
{
result = ERROR;
}
else
{
/* Set CKSEL bitfield according to ClockSource value */
/* Set PRESC bitfield according to Prescaler value */
/* Set WAVE bitfield according to Waveform value */
/* Set WAVEPOL bitfield according to Polarity value */
MODIFY_REG(LPTIMx->CFGR,
(LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL),
LPTIM_InitStruct->ClockSource | \
LPTIM_InitStruct->Prescaler | \
LPTIM_InitStruct->Waveform | \
LPTIM_InitStruct->Polarity);
}
return result;
}
/**
* @brief Disable the LPTIM instance
* @rmtoll CR ENABLE LL_LPTIM_Disable
* @param LPTIMx Low-Power Timer instance
* @note The following sequence is required to solve LPTIM disable HW limitation.
* Please check Errata Sheet ES0335 for more details under "MCU may remain
* stuck in LPTIM interrupt when entering Stop mode" section.
* @retval None
*/
void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
{
LL_RCC_ClocksTypeDef rcc_clock;
uint32_t tmpclksource = 0;
uint32_t tmpIER;
uint32_t tmpCFGR;
uint32_t tmpCMP;
uint32_t tmpARR;
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(LPTIMx));
__disable_irq();
/********** Save LPTIM Config *********/
/* Save LPTIM source clock */
switch ((uint32_t)LPTIMx)
{
case LPTIM1_BASE:
tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
break;
default:
break;
}
/* Save LPTIM configuration registers */
tmpIER = LPTIMx->IER;
tmpCFGR = LPTIMx->CFGR;
tmpCMP = LPTIMx->CMP;
tmpARR = LPTIMx->ARR;
/************* Reset LPTIM ************/
(void)LL_LPTIM_DeInit(LPTIMx);
/********* Restore LPTIM Config *******/
LL_RCC_GetSystemClocksFreq(&rcc_clock);
if ((tmpCMP != 0UL) || (tmpARR != 0UL))
{
/* Force LPTIM source kernel clock from APB */
switch ((uint32_t)LPTIMx)
{
case LPTIM1_BASE:
LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
break;
default:
break;
}
if (tmpCMP != 0UL)
{
/* Restore CMP and ARR registers (LPTIM should be enabled first) */
LPTIMx->CR |= LPTIM_CR_ENABLE;
LPTIMx->CMP = tmpCMP;
/* Polling on CMP write ok status after above restore operation */
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
}
while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
}
if (tmpARR != 0UL)
{
LPTIMx->CR |= LPTIM_CR_ENABLE;
LPTIMx->ARR = tmpARR;
LL_RCC_GetSystemClocksFreq(&rcc_clock);
/* Polling on ARR write ok status after above restore operation */
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
}
while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_ARROK(LPTIMx);
}
/* Restore LPTIM source kernel clock */
LL_RCC_SetLPTIMClockSource(tmpclksource);
}
/* Restore configuration registers (LPTIM should be disabled first) */
LPTIMx->CR &= ~(LPTIM_CR_ENABLE);
LPTIMx->IER = tmpIER;
LPTIMx->CFGR = tmpCFGR;
__enable_irq();
}
/**
* @}
*/
@ -183,7 +287,7 @@ ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_In
* @}
*/
#endif /* defined (LPTIM1) || defined (LPTIM2) */
#endif /* LPTIM1 */
/**
* @}

7
stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_rcc.c
View File

@ -163,7 +163,7 @@ uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
*/
ErrorStatus LL_RCC_DeInit(void)
{
uint32_t vl_mask = 0xFFFFFFFFU;
__IO uint32_t vl_mask;
/* Set HSION bit */
LL_RCC_HSI_Enable();
@ -175,10 +175,13 @@ ErrorStatus LL_RCC_DeInit(void)
/* Reset CFGR register */
LL_RCC_WriteReg(CFGR, 0x00000000U);
/* Read CR register */
vl_mask = LL_RCC_ReadReg(CR);
/* Reset HSEON, HSEBYP, PLLON, CSSON, PLLI2SON and PLLSAION bits */
CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_PLLSAION | RCC_CR_PLLI2SON));
/* Write new mask in CR register */
/* Write new value in CR register */
LL_RCC_WriteReg(CR, vl_mask);
/* Set HSITRIM bits to the reset value*/

379
stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_sdmmc.c
View File

File diff suppressed because it is too large Load Diff

184
stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_tim.c
View File

@ -26,7 +26,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32F7xx_LL_Driver
* @{
@ -46,135 +46,135 @@
* @{
*/
#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
|| ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
|| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
|| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
|| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
|| ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
|| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
|| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
|| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
|| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
|| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
|| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
|| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
|| ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
|| ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
|| ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
|| ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
|| ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
|| ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
|| ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
|| ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
|| ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
|| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
|| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
|| ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
|| ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
|| ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
|| ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
|| ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
|| ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
|| ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
|| ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
|| ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
|| ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
|| ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
|| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
|| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
|| ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
|| ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
|| ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
|| ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
|| ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
|| ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
|| ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
|| ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
|| ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
|| ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
|| ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
|| ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
|| ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
|| ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
|| ((__VALUE__) == LL_TIM_ICPSC_DIV8))
|| ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
|| ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
|| ((__VALUE__) == LL_TIM_ICPSC_DIV8))
#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
|| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
|| ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
|| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
|| ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
|| ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
|| ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
|| ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
|| ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
|| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
|| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
|| ((__VALUE__) == LL_TIM_OSSR_ENABLE))
|| ((__VALUE__) == LL_TIM_OSSR_ENABLE))
#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
|| ((__VALUE__) == LL_TIM_OSSI_ENABLE))
|| ((__VALUE__) == LL_TIM_OSSI_ENABLE))
#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
|| ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
|| ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
|| ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
|| ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
|| ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
|| ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
|| ((__VALUE__) == LL_TIM_BREAK_ENABLE))
|| ((__VALUE__) == LL_TIM_BREAK_ENABLE))
#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
|| ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
|| ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
|| ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
|| ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
|| ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
|| ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
|| ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
|| ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
/**
* @}
*/
@ -336,7 +336,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
TIM_InitStruct->RepetitionCounter = 0x00000000U;
}
/**
@ -728,9 +728,9 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
* and DTG[7:0] can be write-locked depending on the LOCK configuration, it
* can be necessary to configure all of them during the first write access to
* the TIMx_BDTR register.
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @param TIMx Timer Instance
* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
@ -795,7 +795,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT
*/
/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
* @brief Private functions
* @brief Private functions
* @{
*/
/**

48
stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_usart.c
View File

@ -22,11 +22,11 @@
#include "stm32f7xx_ll_usart.h"
#include "stm32f7xx_ll_rcc.h"
#include "stm32f7xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32F7xx_LL_Driver
* @{
@ -41,14 +41,6 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Macros
* @{
@ -65,42 +57,42 @@
#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \
|| ((__VALUE__) == LL_USART_DIRECTION_TX) \
|| ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \
|| ((__VALUE__) == LL_USART_DIRECTION_TX) \
|| ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
|| ((__VALUE__) == LL_USART_PARITY_EVEN) \
|| ((__VALUE__) == LL_USART_PARITY_ODD))
|| ((__VALUE__) == LL_USART_PARITY_EVEN) \
|| ((__VALUE__) == LL_USART_PARITY_ODD))
#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
|| ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
|| ((__VALUE__) == LL_USART_DATAWIDTH_9B))
|| ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
|| ((__VALUE__) == LL_USART_DATAWIDTH_9B))
#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
|| ((__VALUE__) == LL_USART_OVERSAMPLING_8))
|| ((__VALUE__) == LL_USART_OVERSAMPLING_8))
#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
|| ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
|| ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
|| ((__VALUE__) == LL_USART_PHASE_2EDGE))
|| ((__VALUE__) == LL_USART_PHASE_2EDGE))
#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
|| ((__VALUE__) == LL_USART_POLARITY_HIGH))
|| ((__VALUE__) == LL_USART_POLARITY_HIGH))
#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
|| ((__VALUE__) == LL_USART_CLOCK_ENABLE))
|| ((__VALUE__) == LL_USART_CLOCK_ENABLE))
#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
|| ((__VALUE__) == LL_USART_STOPBITS_1) \
|| ((__VALUE__) == LL_USART_STOPBITS_1_5) \
|| ((__VALUE__) == LL_USART_STOPBITS_2))
|| ((__VALUE__) == LL_USART_STOPBITS_1) \
|| ((__VALUE__) == LL_USART_STOPBITS_1_5) \
|| ((__VALUE__) == LL_USART_STOPBITS_2))
#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
|| ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
|| ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
/**
* @}

151
stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_usb.c
View File

@ -94,6 +94,11 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
/* Init The ULPI Interface */
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx)
/* Select ULPI Interface */
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
#endif /* defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx) */
/* Select vbus source */
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
if (cfg.use_external_vbus == 1U)
@ -115,7 +120,7 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
/* Select UTMI Interace */
USBx->GUSBCFG &= ~ USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN;
/* Enables control of a High Speed USB PHY */
@ -169,7 +174,7 @@ HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
used by application. In the low AHB frequency range it is used to stretch enough the USB response
time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
latency to the Data FIFO */
if (speed == USB_OTG_SPEED_FULL)
if (speed == USBD_FS_SPEED)
{
if ((hclk >= 14200000U) && (hclk < 15000000U))
{
@ -222,7 +227,7 @@ HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
UsbTrd = 0x6U;
}
}
else if (speed == USB_OTG_SPEED_HIGH)
else if (speed == USBD_HS_SPEED)
{
UsbTrd = USBD_HS_TRDT_VALUE;
}
@ -314,6 +319,8 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf
/* VBUS Sensing setup */
if (cfg.vbus_sensing_enable == 0U)
{
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
/* Deactivate VBUS Sensing B */
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
@ -335,33 +342,33 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
{
if (cfg.speed == USB_OTG_SPEED_HIGH)
if (cfg.speed == USBD_HS_SPEED)
{
/* Set High speed phy */
/* Set Core speed to High speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
}
else
{
/* set High speed phy in Full speed mode */
/* Set Core speed to Full speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
}
}
else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY)
{
if (cfg.speed == USB_OTG_SPEED_HIGH)
if (cfg.speed == USBD_HS_SPEED)
{
/* Set High speed phy */
/* Set Core speed to High speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
}
else
{
/* set High speed phy in Full speed mode */
/* Set Core speed to Full speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
}
}
else
{
/* Set Full speed phy */
/* Set Core speed to Full speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
}
@ -427,17 +434,6 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
if (cfg.dma_enable == 1U)
{
/*Set threshold parameters */
USBx_DEVICE->DTHRCTL = USB_OTG_DTHRCTL_TXTHRLEN_6 |
USB_OTG_DTHRCTL_RXTHRLEN_6;
USBx_DEVICE->DTHRCTL |= USB_OTG_DTHRCTL_RXTHREN |
USB_OTG_DTHRCTL_ISOTHREN |
USB_OTG_DTHRCTL_NONISOTHREN;
}
/* Disable all interrupts. */
USBx->GINTMSK = 0U;
@ -542,8 +538,8 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
* @param USBx Selected device
* @retval speed device speed
* This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @arg PCD_SPEED_HIGH: High speed mode
* @arg PCD_SPEED_FULL: Full speed mode
*/
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
{
@ -553,16 +549,16 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
{
speed = USB_OTG_SPEED_HIGH;
speed = USBD_HS_SPEED;
}
else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
(DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
{
speed = USB_OTG_SPEED_FULL;
speed = USBD_FS_SPEED;
}
else
{
speed = 0U;
speed = 0xFU;
}
return speed;
@ -659,6 +655,12 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
/* Read DEPCTLn register */
if (ep->is_in == 1U)
{
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
}
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
@ -669,6 +671,12 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
}
else
{
if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
{
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
}
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
@ -694,11 +702,23 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U
/* Read DEPCTLn register */
if (ep->is_in == 1U)
{
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
}
USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
}
else
{
if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
{
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
}
USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
}
@ -757,9 +777,27 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
{
USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
}
if (ep->type == EP_TYPE_ISOC)
{
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
}
else
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
}
}
/* EP enable, IN data in FIFO */
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
else
{
/* EP enable, IN data in FIFO */
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
if (ep->type != EP_TYPE_ISOC)
{
/* Enable the Tx FIFO Empty Interrupt for this EP */
@ -768,27 +806,20 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
}
}
}
if (ep->type == EP_TYPE_ISOC)
{
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
}
else
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
}
else
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
}
(void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
}
}
/* EP enable, IN data in FIFO */
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
if (ep->type == EP_TYPE_ISOC)
{
(void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
}
}
else /* OUT endpoint */
{
@ -886,18 +917,21 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe
{
USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
}
/* EP enable, IN data in FIFO */
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
else
{
/* EP enable, IN data in FIFO */
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0U)
{
USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
}
}
/* EP enable, IN data in FIFO */
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
else /* OUT endpoint */
{
@ -964,15 +998,10 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin
}
/**
* @brief USB_ReadPacket : read a packet from the Tx FIFO associated
* with the EP/channel
* @brief USB_ReadPacket : read a packet from the RX FIFO
* @param USBx Selected device
* @param dest source pointer
* @param len Number of bytes to read
* @param dma USB dma enabled or disabled
* This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @retval pointer to destination buffer
*/
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
@ -1256,13 +1285,9 @@ HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
/* Set the MPS of the IN EP based on the enumeration speed */
/* Set the MPS of the IN EP0 to 64 bytes */
USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
{
USBx_INEP(0U)->DIEPCTL |= 3U;
}
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
return HAL_OK;
@ -1429,7 +1454,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
if ((USBx->CID & (0x1U << 8)) != 0U)
{
if (cfg.speed == USB_OTG_SPEED_FULL)
if (cfg.speed == USBH_FSLS_SPEED)
{
/* Force Device Enumeration to FS/LS mode only */
USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
@ -1590,9 +1615,9 @@ HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
* @param USBx Selected device
* @retval speed : Host speed
* This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @arg USB_OTG_SPEED_LOW: Low speed mode
* @arg HCD_SPEED_HIGH: High speed mode
* @arg HCD_SPEED_FULL: Full speed mode
* @arg HCD_SPEED_LOW: Low speed mode
*/
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)
{
@ -1770,7 +1795,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
uint16_t num_packets;
uint16_t max_hc_pkt_count = 256U;
if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USB_OTG_SPEED_HIGH))
if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED))
{
if ((dma == 0U) && (hc->do_ping == 1U))
{
@ -1998,7 +2023,6 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
uint32_t value;
uint32_t i;
(void)USB_DisableGlobalInt(USBx);
/* Flush FIFO */
@ -2037,6 +2061,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
/* Clear any pending Host interrupts */
USBx_HOST->HAINT = 0xFFFFFFFFU;
USBx->GINTSTS = 0xFFFFFFFFU;
(void)USB_EnableGlobalInt(USBx);
return HAL_OK;

5587
stm32cube/stm32f7xx/release_note.html Normal file
View File

File diff suppressed because it is too large Load Diff

744
stm32cube/stm32f7xx/soc/stm32f722xx.h
View File

@ -12,29 +12,13 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@ -1196,6 +1180,10 @@ typedef struct
/* Analog to Digital Converter */
/* */
/******************************************************************************/
#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF07A2A)) /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_ADDR_CMSIS ((uint16_t*) (0x1FF07A2C)) /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR_CMSIS ((uint16_t*) (0x1FF07A2E)) /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD_Pos (0U)
#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
@ -7603,104 +7591,236 @@ typedef struct
#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT_0 0x00000001U
#define GPIO_OTYPER_OT_1 0x00000002U
#define GPIO_OTYPER_OT_2 0x00000004U
#define GPIO_OTYPER_OT_3 0x00000008U
#define GPIO_OTYPER_OT_4 0x00000010U
#define GPIO_OTYPER_OT_5 0x00000020U
#define GPIO_OTYPER_OT_6 0x00000040U
#define GPIO_OTYPER_OT_7 0x00000080U
#define GPIO_OTYPER_OT_8 0x00000100U
#define GPIO_OTYPER_OT_9 0x00000200U
#define GPIO_OTYPER_OT_10 0x00000400U
#define GPIO_OTYPER_OT_11 0x00000800U
#define GPIO_OTYPER_OT_12 0x00001000U
#define GPIO_OTYPER_OT_13 0x00002000U
#define GPIO_OTYPER_OT_14 0x00004000U
#define GPIO_OTYPER_OT_15 0x00008000U
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
/* legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0_Pos GPIO_OSPEEDR_OSPEEDR0_Pos
#define GPIO_OSPEEDER_OSPEEDR0_Msk GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
#define GPIO_OSPEEDER_OSPEEDR1_Pos GPIO_OSPEEDR_OSPEEDR1_Pos
#define GPIO_OSPEEDER_OSPEEDR1_Msk GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
#define GPIO_OSPEEDER_OSPEEDR2_Pos GPIO_OSPEEDR_OSPEEDR2_Pos
#define GPIO_OSPEEDER_OSPEEDR2_Msk GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
#define GPIO_OSPEEDER_OSPEEDR3_Pos GPIO_OSPEEDR_OSPEEDR3_Pos
#define GPIO_OSPEEDER_OSPEEDR3_Msk GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
#define GPIO_OSPEEDER_OSPEEDR4_Pos GPIO_OSPEEDR_OSPEEDR4_Pos
#define GPIO_OSPEEDER_OSPEEDR4_Msk GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
#define GPIO_OSPEEDER_OSPEEDR5_Pos GPIO_OSPEEDR_OSPEEDR5_Pos
#define GPIO_OSPEEDER_OSPEEDR5_Msk GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
#define GPIO_OSPEEDER_OSPEEDR6_Pos GPIO_OSPEEDR_OSPEEDR6_Pos
#define GPIO_OSPEEDER_OSPEEDR6_Msk GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
#define GPIO_OSPEEDER_OSPEEDR7_Pos GPIO_OSPEEDR_OSPEEDR7_Pos
#define GPIO_OSPEEDER_OSPEEDR7_Msk GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
#define GPIO_OSPEEDER_OSPEEDR8_Pos GPIO_OSPEEDR_OSPEEDR8_Pos
#define GPIO_OSPEEDER_OSPEEDR8_Msk GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
#define GPIO_OSPEEDER_OSPEEDR9_Pos GPIO_OSPEEDR_OSPEEDR9_Pos
#define GPIO_OSPEEDER_OSPEEDR9_Msk GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
#define GPIO_OSPEEDER_OSPEEDR10_Pos GPIO_OSPEEDR_OSPEEDR10_Pos
#define GPIO_OSPEEDER_OSPEEDR10_Msk GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
#define GPIO_OSPEEDER_OSPEEDR11_Pos GPIO_OSPEEDR_OSPEEDR11_Pos
#define GPIO_OSPEEDER_OSPEEDR11_Msk GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
#define GPIO_OSPEEDER_OSPEEDR12_Pos GPIO_OSPEEDR_OSPEEDR12_Pos
#define GPIO_OSPEEDER_OSPEEDR12_Msk GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
#define GPIO_OSPEEDER_OSPEEDR13_Pos GPIO_OSPEEDR_OSPEEDR13_Pos
#define GPIO_OSPEEDER_OSPEEDR13_Msk GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
#define GPIO_OSPEEDER_OSPEEDR14_Pos GPIO_OSPEEDR_OSPEEDR14_Pos
#define GPIO_OSPEEDER_OSPEEDR14_Msk GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
#define GPIO_OSPEEDER_OSPEEDR15_Pos GPIO_OSPEEDR_OSPEEDR15_Pos
#define GPIO_OSPEEDER_OSPEEDR15_Msk GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPDR0_Pos (0U)
@ -7785,74 +7905,272 @@ typedef struct
#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_IDR_0 0x00000001U
#define GPIO_IDR_IDR_1 0x00000002U
#define GPIO_IDR_IDR_2 0x00000004U
#define GPIO_IDR_IDR_3 0x00000008U
#define GPIO_IDR_IDR_4 0x00000010U
#define GPIO_IDR_IDR_5 0x00000020U
#define GPIO_IDR_IDR_6 0x00000040U
#define GPIO_IDR_IDR_7 0x00000080U
#define GPIO_IDR_IDR_8 0x00000100U
#define GPIO_IDR_IDR_9 0x00000200U
#define GPIO_IDR_IDR_10 0x00000400U
#define GPIO_IDR_IDR_11 0x00000800U
#define GPIO_IDR_IDR_12 0x00001000U
#define GPIO_IDR_IDR_13 0x00002000U
#define GPIO_IDR_IDR_14 0x00004000U
#define GPIO_IDR_IDR_15 0x00008000U
#define GPIO_IDR_ID0_Pos (0U)
#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos (1U)
#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos (2U)
#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos (3U)
#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos (4U)
#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos (5U)
#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos (6U)
#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos (7U)
#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos (8U)
#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos (9U)
#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos (10U)
#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos (11U)
#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos (12U)
#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos (13U)
#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos (14U)
#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos (15U)
#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
/* Legacy defines */
#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_ODR_0 0x00000001U
#define GPIO_ODR_ODR_1 0x00000002U
#define GPIO_ODR_ODR_2 0x00000004U
#define GPIO_ODR_ODR_3 0x00000008U
#define GPIO_ODR_ODR_4 0x00000010U
#define GPIO_ODR_ODR_5 0x00000020U
#define GPIO_ODR_ODR_6 0x00000040U
#define GPIO_ODR_ODR_7 0x00000080U
#define GPIO_ODR_ODR_8 0x00000100U
#define GPIO_ODR_ODR_9 0x00000200U
#define GPIO_ODR_ODR_10 0x00000400U
#define GPIO_ODR_ODR_11 0x00000800U
#define GPIO_ODR_ODR_12 0x00001000U
#define GPIO_ODR_ODR_13 0x00002000U
#define GPIO_ODR_ODR_14 0x00004000U
#define GPIO_ODR_ODR_15 0x00008000U
#define GPIO_ODR_OD0_Pos (0U)
#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos (1U)
#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos (2U)
#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos (3U)
#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos (4U)
#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos (5U)
#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos (6U)
#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos (7U)
#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos (8U)
#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos (9U)
#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos (10U)
#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos (11U)
#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos (12U)
#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos (13U)
#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos (14U)
#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos (15U)
#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
/* Legacy defines */
#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS_0 0x00000001U
#define GPIO_BSRR_BS_1 0x00000002U
#define GPIO_BSRR_BS_2 0x00000004U
#define GPIO_BSRR_BS_3 0x00000008U
#define GPIO_BSRR_BS_4 0x00000010U
#define GPIO_BSRR_BS_5 0x00000020U
#define GPIO_BSRR_BS_6 0x00000040U
#define GPIO_BSRR_BS_7 0x00000080U
#define GPIO_BSRR_BS_8 0x00000100U
#define GPIO_BSRR_BS_9 0x00000200U
#define GPIO_BSRR_BS_10 0x00000400U
#define GPIO_BSRR_BS_11 0x00000800U
#define GPIO_BSRR_BS_12 0x00001000U
#define GPIO_BSRR_BS_13 0x00002000U
#define GPIO_BSRR_BS_14 0x00004000U
#define GPIO_BSRR_BS_15 0x00008000U
#define GPIO_BSRR_BR_0 0x00010000U
#define GPIO_BSRR_BR_1 0x00020000U
#define GPIO_BSRR_BR_2 0x00040000U
#define GPIO_BSRR_BR_3 0x00080000U
#define GPIO_BSRR_BR_4 0x00100000U
#define GPIO_BSRR_BR_5 0x00200000U
#define GPIO_BSRR_BR_6 0x00400000U
#define GPIO_BSRR_BR_7 0x00800000U
#define GPIO_BSRR_BR_8 0x01000000U
#define GPIO_BSRR_BR_9 0x02000000U
#define GPIO_BSRR_BR_10 0x04000000U
#define GPIO_BSRR_BR_11 0x08000000U
#define GPIO_BSRR_BR_12 0x10000000U
#define GPIO_BSRR_BR_13 0x20000000U
#define GPIO_BSRR_BR_14 0x40000000U
#define GPIO_BSRR_BR_15 0x80000000U
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/* Legacy defines */
#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
@ -13422,6 +13740,12 @@ typedef struct
#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
#define USB_OTG_GUSBCFG_PHYIF_Pos (3U)
#define USB_OTG_GUSBCFG_PHYIF_Msk (0x1UL << USB_OTG_GUSBCFG_PHYIF_Pos) /*!< 0x00000008 */
#define USB_OTG_GUSBCFG_PHYIF USB_OTG_GUSBCFG_PHYIF_Msk /*!< PHY Interface (PHYIf) */
#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos (4U)
#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk (0x1UL << USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos) /*!< 0x00000010 */
#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk /*!< ULPI or UTMI+ Select (ULPI_UTMI_Sel) */
#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
@ -13856,49 +14180,6 @@ typedef struct
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_CHNUM_Pos (0U)
#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos (4U)
#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
#define USB_OTG_DPID_Pos (15U)
#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_PKTSTS_Pos (17U)
#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
#define USB_OTG_EPNUM_Pos (0U)
#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_FRMNUM_Pos (21U)
#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
@ -15005,17 +15286,6 @@ typedef struct
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8) )
/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
((__INSTANCE__) == TIM3) || \
((__INSTANCE__) == TIM4) || \
((__INSTANCE__) == TIM5) || \
((__INSTANCE__) == TIM6) || \
((__INSTANCE__) == TIM7) || \
((__INSTANCE__) == TIM8))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
@ -15062,7 +15332,7 @@ typedef struct
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8))
((__INSTANCE__) == TIM8))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \

738
stm32cube/stm32f7xx/soc/stm32f723xx.h
View File

@ -12,29 +12,13 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@ -1212,6 +1196,10 @@ typedef struct
/* Analog to Digital Converter */
/* */
/******************************************************************************/
#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF07A2A)) /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_ADDR_CMSIS ((uint16_t*) (0x1FF07A2C)) /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR_CMSIS ((uint16_t*) (0x1FF07A2E)) /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD_Pos (0U)
#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
@ -7619,104 +7607,236 @@ typedef struct
#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT_0 0x00000001U
#define GPIO_OTYPER_OT_1 0x00000002U
#define GPIO_OTYPER_OT_2 0x00000004U
#define GPIO_OTYPER_OT_3 0x00000008U
#define GPIO_OTYPER_OT_4 0x00000010U
#define GPIO_OTYPER_OT_5 0x00000020U
#define GPIO_OTYPER_OT_6 0x00000040U
#define GPIO_OTYPER_OT_7 0x00000080U
#define GPIO_OTYPER_OT_8 0x00000100U
#define GPIO_OTYPER_OT_9 0x00000200U
#define GPIO_OTYPER_OT_10 0x00000400U
#define GPIO_OTYPER_OT_11 0x00000800U
#define GPIO_OTYPER_OT_12 0x00001000U
#define GPIO_OTYPER_OT_13 0x00002000U
#define GPIO_OTYPER_OT_14 0x00004000U
#define GPIO_OTYPER_OT_15 0x00008000U
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
/* legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0_Pos GPIO_OSPEEDR_OSPEEDR0_Pos
#define GPIO_OSPEEDER_OSPEEDR0_Msk GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
#define GPIO_OSPEEDER_OSPEEDR1_Pos GPIO_OSPEEDR_OSPEEDR1_Pos
#define GPIO_OSPEEDER_OSPEEDR1_Msk GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
#define GPIO_OSPEEDER_OSPEEDR2_Pos GPIO_OSPEEDR_OSPEEDR2_Pos
#define GPIO_OSPEEDER_OSPEEDR2_Msk GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
#define GPIO_OSPEEDER_OSPEEDR3_Pos GPIO_OSPEEDR_OSPEEDR3_Pos
#define GPIO_OSPEEDER_OSPEEDR3_Msk GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
#define GPIO_OSPEEDER_OSPEEDR4_Pos GPIO_OSPEEDR_OSPEEDR4_Pos
#define GPIO_OSPEEDER_OSPEEDR4_Msk GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
#define GPIO_OSPEEDER_OSPEEDR5_Pos GPIO_OSPEEDR_OSPEEDR5_Pos
#define GPIO_OSPEEDER_OSPEEDR5_Msk GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
#define GPIO_OSPEEDER_OSPEEDR6_Pos GPIO_OSPEEDR_OSPEEDR6_Pos
#define GPIO_OSPEEDER_OSPEEDR6_Msk GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
#define GPIO_OSPEEDER_OSPEEDR7_Pos GPIO_OSPEEDR_OSPEEDR7_Pos
#define GPIO_OSPEEDER_OSPEEDR7_Msk GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
#define GPIO_OSPEEDER_OSPEEDR8_Pos GPIO_OSPEEDR_OSPEEDR8_Pos
#define GPIO_OSPEEDER_OSPEEDR8_Msk GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
#define GPIO_OSPEEDER_OSPEEDR9_Pos GPIO_OSPEEDR_OSPEEDR9_Pos
#define GPIO_OSPEEDER_OSPEEDR9_Msk GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
#define GPIO_OSPEEDER_OSPEEDR10_Pos GPIO_OSPEEDR_OSPEEDR10_Pos
#define GPIO_OSPEEDER_OSPEEDR10_Msk GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
#define GPIO_OSPEEDER_OSPEEDR11_Pos GPIO_OSPEEDR_OSPEEDR11_Pos
#define GPIO_OSPEEDER_OSPEEDR11_Msk GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
#define GPIO_OSPEEDER_OSPEEDR12_Pos GPIO_OSPEEDR_OSPEEDR12_Pos
#define GPIO_OSPEEDER_OSPEEDR12_Msk GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
#define GPIO_OSPEEDER_OSPEEDR13_Pos GPIO_OSPEEDR_OSPEEDR13_Pos
#define GPIO_OSPEEDER_OSPEEDR13_Msk GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
#define GPIO_OSPEEDER_OSPEEDR14_Pos GPIO_OSPEEDR_OSPEEDR14_Pos
#define GPIO_OSPEEDER_OSPEEDR14_Msk GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
#define GPIO_OSPEEDER_OSPEEDR15_Pos GPIO_OSPEEDR_OSPEEDR15_Pos
#define GPIO_OSPEEDER_OSPEEDR15_Msk GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPDR0_Pos (0U)
@ -7801,74 +7921,272 @@ typedef struct
#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_IDR_0 0x00000001U
#define GPIO_IDR_IDR_1 0x00000002U
#define GPIO_IDR_IDR_2 0x00000004U
#define GPIO_IDR_IDR_3 0x00000008U
#define GPIO_IDR_IDR_4 0x00000010U
#define GPIO_IDR_IDR_5 0x00000020U
#define GPIO_IDR_IDR_6 0x00000040U
#define GPIO_IDR_IDR_7 0x00000080U
#define GPIO_IDR_IDR_8 0x00000100U
#define GPIO_IDR_IDR_9 0x00000200U
#define GPIO_IDR_IDR_10 0x00000400U
#define GPIO_IDR_IDR_11 0x00000800U
#define GPIO_IDR_IDR_12 0x00001000U
#define GPIO_IDR_IDR_13 0x00002000U
#define GPIO_IDR_IDR_14 0x00004000U
#define GPIO_IDR_IDR_15 0x00008000U
#define GPIO_IDR_ID0_Pos (0U)
#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos (1U)
#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos (2U)
#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos (3U)
#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos (4U)
#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos (5U)
#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos (6U)
#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos (7U)
#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos (8U)
#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos (9U)
#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos (10U)
#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos (11U)
#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos (12U)
#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos (13U)
#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos (14U)
#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos (15U)
#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
/* Legacy defines */
#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_ODR_0 0x00000001U
#define GPIO_ODR_ODR_1 0x00000002U
#define GPIO_ODR_ODR_2 0x00000004U
#define GPIO_ODR_ODR_3 0x00000008U
#define GPIO_ODR_ODR_4 0x00000010U
#define GPIO_ODR_ODR_5 0x00000020U
#define GPIO_ODR_ODR_6 0x00000040U
#define GPIO_ODR_ODR_7 0x00000080U
#define GPIO_ODR_ODR_8 0x00000100U
#define GPIO_ODR_ODR_9 0x00000200U
#define GPIO_ODR_ODR_10 0x00000400U
#define GPIO_ODR_ODR_11 0x00000800U
#define GPIO_ODR_ODR_12 0x00001000U
#define GPIO_ODR_ODR_13 0x00002000U
#define GPIO_ODR_ODR_14 0x00004000U
#define GPIO_ODR_ODR_15 0x00008000U
#define GPIO_ODR_OD0_Pos (0U)
#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos (1U)
#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos (2U)
#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos (3U)
#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos (4U)
#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos (5U)
#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos (6U)
#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos (7U)
#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos (8U)
#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos (9U)
#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos (10U)
#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos (11U)
#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos (12U)
#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos (13U)
#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos (14U)
#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos (15U)
#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
/* Legacy defines */
#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS_0 0x00000001U
#define GPIO_BSRR_BS_1 0x00000002U
#define GPIO_BSRR_BS_2 0x00000004U
#define GPIO_BSRR_BS_3 0x00000008U
#define GPIO_BSRR_BS_4 0x00000010U
#define GPIO_BSRR_BS_5 0x00000020U
#define GPIO_BSRR_BS_6 0x00000040U
#define GPIO_BSRR_BS_7 0x00000080U
#define GPIO_BSRR_BS_8 0x00000100U
#define GPIO_BSRR_BS_9 0x00000200U
#define GPIO_BSRR_BS_10 0x00000400U
#define GPIO_BSRR_BS_11 0x00000800U
#define GPIO_BSRR_BS_12 0x00001000U
#define GPIO_BSRR_BS_13 0x00002000U
#define GPIO_BSRR_BS_14 0x00004000U
#define GPIO_BSRR_BS_15 0x00008000U
#define GPIO_BSRR_BR_0 0x00010000U
#define GPIO_BSRR_BR_1 0x00020000U
#define GPIO_BSRR_BR_2 0x00040000U
#define GPIO_BSRR_BR_3 0x00080000U
#define GPIO_BSRR_BR_4 0x00100000U
#define GPIO_BSRR_BR_5 0x00200000U
#define GPIO_BSRR_BR_6 0x00400000U
#define GPIO_BSRR_BR_7 0x00800000U
#define GPIO_BSRR_BR_8 0x01000000U
#define GPIO_BSRR_BR_9 0x02000000U
#define GPIO_BSRR_BR_10 0x04000000U
#define GPIO_BSRR_BR_11 0x08000000U
#define GPIO_BSRR_BR_12 0x10000000U
#define GPIO_BSRR_BR_13 0x20000000U
#define GPIO_BSRR_BR_14 0x40000000U
#define GPIO_BSRR_BR_15 0x80000000U
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/* Legacy defines */
#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
@ -13884,49 +14202,6 @@ typedef struct
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_CHNUM_Pos (0U)
#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos (4U)
#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
#define USB_OTG_DPID_Pos (15U)
#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_PKTSTS_Pos (17U)
#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
#define USB_OTG_EPNUM_Pos (0U)
#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_FRMNUM_Pos (21U)
#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
@ -15105,17 +15380,6 @@ typedef struct
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8) )
/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
((__INSTANCE__) == TIM3) || \
((__INSTANCE__) == TIM4) || \
((__INSTANCE__) == TIM5) || \
((__INSTANCE__) == TIM6) || \
((__INSTANCE__) == TIM7) || \
((__INSTANCE__) == TIM8))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
@ -15162,7 +15426,7 @@ typedef struct
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8))
((__INSTANCE__) == TIM8))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \

738
stm32cube/stm32f7xx/soc/stm32f730xx.h
View File

@ -12,29 +12,13 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@ -1246,6 +1230,10 @@ typedef struct
/* Analog to Digital Converter */
/* */
/******************************************************************************/
#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF07A2A)) /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_ADDR_CMSIS ((uint16_t*) (0x1FF07A2C)) /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR_CMSIS ((uint16_t*) (0x1FF07A2E)) /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD_Pos (0U)
#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
@ -7833,104 +7821,236 @@ typedef struct
#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT_0 0x00000001U
#define GPIO_OTYPER_OT_1 0x00000002U
#define GPIO_OTYPER_OT_2 0x00000004U
#define GPIO_OTYPER_OT_3 0x00000008U
#define GPIO_OTYPER_OT_4 0x00000010U
#define GPIO_OTYPER_OT_5 0x00000020U
#define GPIO_OTYPER_OT_6 0x00000040U
#define GPIO_OTYPER_OT_7 0x00000080U
#define GPIO_OTYPER_OT_8 0x00000100U
#define GPIO_OTYPER_OT_9 0x00000200U
#define GPIO_OTYPER_OT_10 0x00000400U
#define GPIO_OTYPER_OT_11 0x00000800U
#define GPIO_OTYPER_OT_12 0x00001000U
#define GPIO_OTYPER_OT_13 0x00002000U
#define GPIO_OTYPER_OT_14 0x00004000U
#define GPIO_OTYPER_OT_15 0x00008000U
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
/* legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0_Pos GPIO_OSPEEDR_OSPEEDR0_Pos
#define GPIO_OSPEEDER_OSPEEDR0_Msk GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
#define GPIO_OSPEEDER_OSPEEDR1_Pos GPIO_OSPEEDR_OSPEEDR1_Pos
#define GPIO_OSPEEDER_OSPEEDR1_Msk GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
#define GPIO_OSPEEDER_OSPEEDR2_Pos GPIO_OSPEEDR_OSPEEDR2_Pos
#define GPIO_OSPEEDER_OSPEEDR2_Msk GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
#define GPIO_OSPEEDER_OSPEEDR3_Pos GPIO_OSPEEDR_OSPEEDR3_Pos
#define GPIO_OSPEEDER_OSPEEDR3_Msk GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
#define GPIO_OSPEEDER_OSPEEDR4_Pos GPIO_OSPEEDR_OSPEEDR4_Pos
#define GPIO_OSPEEDER_OSPEEDR4_Msk GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
#define GPIO_OSPEEDER_OSPEEDR5_Pos GPIO_OSPEEDR_OSPEEDR5_Pos
#define GPIO_OSPEEDER_OSPEEDR5_Msk GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
#define GPIO_OSPEEDER_OSPEEDR6_Pos GPIO_OSPEEDR_OSPEEDR6_Pos
#define GPIO_OSPEEDER_OSPEEDR6_Msk GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
#define GPIO_OSPEEDER_OSPEEDR7_Pos GPIO_OSPEEDR_OSPEEDR7_Pos
#define GPIO_OSPEEDER_OSPEEDR7_Msk GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
#define GPIO_OSPEEDER_OSPEEDR8_Pos GPIO_OSPEEDR_OSPEEDR8_Pos
#define GPIO_OSPEEDER_OSPEEDR8_Msk GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
#define GPIO_OSPEEDER_OSPEEDR9_Pos GPIO_OSPEEDR_OSPEEDR9_Pos
#define GPIO_OSPEEDER_OSPEEDR9_Msk GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
#define GPIO_OSPEEDER_OSPEEDR10_Pos GPIO_OSPEEDR_OSPEEDR10_Pos
#define GPIO_OSPEEDER_OSPEEDR10_Msk GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
#define GPIO_OSPEEDER_OSPEEDR11_Pos GPIO_OSPEEDR_OSPEEDR11_Pos
#define GPIO_OSPEEDER_OSPEEDR11_Msk GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
#define GPIO_OSPEEDER_OSPEEDR12_Pos GPIO_OSPEEDR_OSPEEDR12_Pos
#define GPIO_OSPEEDER_OSPEEDR12_Msk GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
#define GPIO_OSPEEDER_OSPEEDR13_Pos GPIO_OSPEEDR_OSPEEDR13_Pos
#define GPIO_OSPEEDER_OSPEEDR13_Msk GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
#define GPIO_OSPEEDER_OSPEEDR14_Pos GPIO_OSPEEDR_OSPEEDR14_Pos
#define GPIO_OSPEEDER_OSPEEDR14_Msk GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
#define GPIO_OSPEEDER_OSPEEDR15_Pos GPIO_OSPEEDR_OSPEEDR15_Pos
#define GPIO_OSPEEDER_OSPEEDR15_Msk GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPDR0_Pos (0U)
@ -8015,74 +8135,272 @@ typedef struct
#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_IDR_0 0x00000001U
#define GPIO_IDR_IDR_1 0x00000002U
#define GPIO_IDR_IDR_2 0x00000004U
#define GPIO_IDR_IDR_3 0x00000008U
#define GPIO_IDR_IDR_4 0x00000010U
#define GPIO_IDR_IDR_5 0x00000020U
#define GPIO_IDR_IDR_6 0x00000040U
#define GPIO_IDR_IDR_7 0x00000080U
#define GPIO_IDR_IDR_8 0x00000100U
#define GPIO_IDR_IDR_9 0x00000200U
#define GPIO_IDR_IDR_10 0x00000400U
#define GPIO_IDR_IDR_11 0x00000800U
#define GPIO_IDR_IDR_12 0x00001000U
#define GPIO_IDR_IDR_13 0x00002000U
#define GPIO_IDR_IDR_14 0x00004000U
#define GPIO_IDR_IDR_15 0x00008000U
#define GPIO_IDR_ID0_Pos (0U)
#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos (1U)
#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos (2U)
#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos (3U)
#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos (4U)
#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos (5U)
#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos (6U)
#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos (7U)
#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos (8U)
#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos (9U)
#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos (10U)
#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos (11U)
#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos (12U)
#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos (13U)
#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos (14U)
#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos (15U)
#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
/* Legacy defines */
#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_ODR_0 0x00000001U
#define GPIO_ODR_ODR_1 0x00000002U
#define GPIO_ODR_ODR_2 0x00000004U
#define GPIO_ODR_ODR_3 0x00000008U
#define GPIO_ODR_ODR_4 0x00000010U
#define GPIO_ODR_ODR_5 0x00000020U
#define GPIO_ODR_ODR_6 0x00000040U
#define GPIO_ODR_ODR_7 0x00000080U
#define GPIO_ODR_ODR_8 0x00000100U
#define GPIO_ODR_ODR_9 0x00000200U
#define GPIO_ODR_ODR_10 0x00000400U
#define GPIO_ODR_ODR_11 0x00000800U
#define GPIO_ODR_ODR_12 0x00001000U
#define GPIO_ODR_ODR_13 0x00002000U
#define GPIO_ODR_ODR_14 0x00004000U
#define GPIO_ODR_ODR_15 0x00008000U
#define GPIO_ODR_OD0_Pos (0U)
#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos (1U)
#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos (2U)
#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos (3U)
#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos (4U)
#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos (5U)
#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos (6U)
#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos (7U)
#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos (8U)
#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos (9U)
#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos (10U)
#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos (11U)
#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos (12U)
#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos (13U)
#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos (14U)
#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos (15U)
#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
/* Legacy defines */
#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS_0 0x00000001U
#define GPIO_BSRR_BS_1 0x00000002U
#define GPIO_BSRR_BS_2 0x00000004U
#define GPIO_BSRR_BS_3 0x00000008U
#define GPIO_BSRR_BS_4 0x00000010U
#define GPIO_BSRR_BS_5 0x00000020U
#define GPIO_BSRR_BS_6 0x00000040U
#define GPIO_BSRR_BS_7 0x00000080U
#define GPIO_BSRR_BS_8 0x00000100U
#define GPIO_BSRR_BS_9 0x00000200U
#define GPIO_BSRR_BS_10 0x00000400U
#define GPIO_BSRR_BS_11 0x00000800U
#define GPIO_BSRR_BS_12 0x00001000U
#define GPIO_BSRR_BS_13 0x00002000U
#define GPIO_BSRR_BS_14 0x00004000U
#define GPIO_BSRR_BS_15 0x00008000U
#define GPIO_BSRR_BR_0 0x00010000U
#define GPIO_BSRR_BR_1 0x00020000U
#define GPIO_BSRR_BR_2 0x00040000U
#define GPIO_BSRR_BR_3 0x00080000U
#define GPIO_BSRR_BR_4 0x00100000U
#define GPIO_BSRR_BR_5 0x00200000U
#define GPIO_BSRR_BR_6 0x00400000U
#define GPIO_BSRR_BR_7 0x00800000U
#define GPIO_BSRR_BR_8 0x01000000U
#define GPIO_BSRR_BR_9 0x02000000U
#define GPIO_BSRR_BR_10 0x04000000U
#define GPIO_BSRR_BR_11 0x08000000U
#define GPIO_BSRR_BR_12 0x10000000U
#define GPIO_BSRR_BR_13 0x20000000U
#define GPIO_BSRR_BR_14 0x40000000U
#define GPIO_BSRR_BR_15 0x80000000U
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/* Legacy defines */
#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
@ -14107,49 +14425,6 @@ typedef struct
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_CHNUM_Pos (0U)
#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos (4U)
#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
#define USB_OTG_DPID_Pos (15U)
#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_PKTSTS_Pos (17U)
#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
#define USB_OTG_EPNUM_Pos (0U)
#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_FRMNUM_Pos (21U)
#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
@ -15330,17 +15605,6 @@ typedef struct
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8) )
/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
((__INSTANCE__) == TIM3) || \
((__INSTANCE__) == TIM4) || \
((__INSTANCE__) == TIM5) || \
((__INSTANCE__) == TIM6) || \
((__INSTANCE__) == TIM7) || \
((__INSTANCE__) == TIM8))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
@ -15387,7 +15651,7 @@ typedef struct
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8))
((__INSTANCE__) == TIM8))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \

744
stm32cube/stm32f7xx/soc/stm32f732xx.h
View File

@ -12,29 +12,13 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@ -1230,6 +1214,10 @@ typedef struct
/* Analog to Digital Converter */
/* */
/******************************************************************************/
#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF07A2A)) /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_ADDR_CMSIS ((uint16_t*) (0x1FF07A2C)) /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR_CMSIS ((uint16_t*) (0x1FF07A2E)) /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD_Pos (0U)
#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
@ -7817,104 +7805,236 @@ typedef struct
#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT_0 0x00000001U
#define GPIO_OTYPER_OT_1 0x00000002U
#define GPIO_OTYPER_OT_2 0x00000004U
#define GPIO_OTYPER_OT_3 0x00000008U
#define GPIO_OTYPER_OT_4 0x00000010U
#define GPIO_OTYPER_OT_5 0x00000020U
#define GPIO_OTYPER_OT_6 0x00000040U
#define GPIO_OTYPER_OT_7 0x00000080U
#define GPIO_OTYPER_OT_8 0x00000100U
#define GPIO_OTYPER_OT_9 0x00000200U
#define GPIO_OTYPER_OT_10 0x00000400U
#define GPIO_OTYPER_OT_11 0x00000800U
#define GPIO_OTYPER_OT_12 0x00001000U
#define GPIO_OTYPER_OT_13 0x00002000U
#define GPIO_OTYPER_OT_14 0x00004000U
#define GPIO_OTYPER_OT_15 0x00008000U
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
/* legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0_Pos GPIO_OSPEEDR_OSPEEDR0_Pos
#define GPIO_OSPEEDER_OSPEEDR0_Msk GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
#define GPIO_OSPEEDER_OSPEEDR1_Pos GPIO_OSPEEDR_OSPEEDR1_Pos
#define GPIO_OSPEEDER_OSPEEDR1_Msk GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
#define GPIO_OSPEEDER_OSPEEDR2_Pos GPIO_OSPEEDR_OSPEEDR2_Pos
#define GPIO_OSPEEDER_OSPEEDR2_Msk GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
#define GPIO_OSPEEDER_OSPEEDR3_Pos GPIO_OSPEEDR_OSPEEDR3_Pos
#define GPIO_OSPEEDER_OSPEEDR3_Msk GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
#define GPIO_OSPEEDER_OSPEEDR4_Pos GPIO_OSPEEDR_OSPEEDR4_Pos
#define GPIO_OSPEEDER_OSPEEDR4_Msk GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
#define GPIO_OSPEEDER_OSPEEDR5_Pos GPIO_OSPEEDR_OSPEEDR5_Pos
#define GPIO_OSPEEDER_OSPEEDR5_Msk GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
#define GPIO_OSPEEDER_OSPEEDR6_Pos GPIO_OSPEEDR_OSPEEDR6_Pos
#define GPIO_OSPEEDER_OSPEEDR6_Msk GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
#define GPIO_OSPEEDER_OSPEEDR7_Pos GPIO_OSPEEDR_OSPEEDR7_Pos
#define GPIO_OSPEEDER_OSPEEDR7_Msk GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
#define GPIO_OSPEEDER_OSPEEDR8_Pos GPIO_OSPEEDR_OSPEEDR8_Pos
#define GPIO_OSPEEDER_OSPEEDR8_Msk GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
#define GPIO_OSPEEDER_OSPEEDR9_Pos GPIO_OSPEEDR_OSPEEDR9_Pos
#define GPIO_OSPEEDER_OSPEEDR9_Msk GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
#define GPIO_OSPEEDER_OSPEEDR10_Pos GPIO_OSPEEDR_OSPEEDR10_Pos
#define GPIO_OSPEEDER_OSPEEDR10_Msk GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
#define GPIO_OSPEEDER_OSPEEDR11_Pos GPIO_OSPEEDR_OSPEEDR11_Pos
#define GPIO_OSPEEDER_OSPEEDR11_Msk GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
#define GPIO_OSPEEDER_OSPEEDR12_Pos GPIO_OSPEEDR_OSPEEDR12_Pos
#define GPIO_OSPEEDER_OSPEEDR12_Msk GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
#define GPIO_OSPEEDER_OSPEEDR13_Pos GPIO_OSPEEDR_OSPEEDR13_Pos
#define GPIO_OSPEEDER_OSPEEDR13_Msk GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
#define GPIO_OSPEEDER_OSPEEDR14_Pos GPIO_OSPEEDR_OSPEEDR14_Pos
#define GPIO_OSPEEDER_OSPEEDR14_Msk GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
#define GPIO_OSPEEDER_OSPEEDR15_Pos GPIO_OSPEEDR_OSPEEDR15_Pos
#define GPIO_OSPEEDER_OSPEEDR15_Msk GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPDR0_Pos (0U)
@ -7999,74 +8119,272 @@ typedef struct
#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_IDR_0 0x00000001U
#define GPIO_IDR_IDR_1 0x00000002U
#define GPIO_IDR_IDR_2 0x00000004U
#define GPIO_IDR_IDR_3 0x00000008U
#define GPIO_IDR_IDR_4 0x00000010U
#define GPIO_IDR_IDR_5 0x00000020U
#define GPIO_IDR_IDR_6 0x00000040U
#define GPIO_IDR_IDR_7 0x00000080U
#define GPIO_IDR_IDR_8 0x00000100U
#define GPIO_IDR_IDR_9 0x00000200U
#define GPIO_IDR_IDR_10 0x00000400U
#define GPIO_IDR_IDR_11 0x00000800U
#define GPIO_IDR_IDR_12 0x00001000U
#define GPIO_IDR_IDR_13 0x00002000U
#define GPIO_IDR_IDR_14 0x00004000U
#define GPIO_IDR_IDR_15 0x00008000U
#define GPIO_IDR_ID0_Pos (0U)
#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos (1U)
#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos (2U)
#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos (3U)
#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos (4U)
#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos (5U)
#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos (6U)
#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos (7U)
#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos (8U)
#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos (9U)
#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos (10U)
#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos (11U)
#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos (12U)
#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos (13U)
#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos (14U)
#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos (15U)
#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
/* Legacy defines */
#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_ODR_0 0x00000001U
#define GPIO_ODR_ODR_1 0x00000002U
#define GPIO_ODR_ODR_2 0x00000004U
#define GPIO_ODR_ODR_3 0x00000008U
#define GPIO_ODR_ODR_4 0x00000010U
#define GPIO_ODR_ODR_5 0x00000020U
#define GPIO_ODR_ODR_6 0x00000040U
#define GPIO_ODR_ODR_7 0x00000080U
#define GPIO_ODR_ODR_8 0x00000100U
#define GPIO_ODR_ODR_9 0x00000200U
#define GPIO_ODR_ODR_10 0x00000400U
#define GPIO_ODR_ODR_11 0x00000800U
#define GPIO_ODR_ODR_12 0x00001000U
#define GPIO_ODR_ODR_13 0x00002000U
#define GPIO_ODR_ODR_14 0x00004000U
#define GPIO_ODR_ODR_15 0x00008000U
#define GPIO_ODR_OD0_Pos (0U)
#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos (1U)
#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos (2U)
#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos (3U)
#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos (4U)
#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos (5U)
#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos (6U)
#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos (7U)
#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos (8U)
#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos (9U)
#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos (10U)
#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos (11U)
#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos (12U)
#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos (13U)
#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos (14U)
#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos (15U)
#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
/* Legacy defines */
#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS_0 0x00000001U
#define GPIO_BSRR_BS_1 0x00000002U
#define GPIO_BSRR_BS_2 0x00000004U
#define GPIO_BSRR_BS_3 0x00000008U
#define GPIO_BSRR_BS_4 0x00000010U
#define GPIO_BSRR_BS_5 0x00000020U
#define GPIO_BSRR_BS_6 0x00000040U
#define GPIO_BSRR_BS_7 0x00000080U
#define GPIO_BSRR_BS_8 0x00000100U
#define GPIO_BSRR_BS_9 0x00000200U
#define GPIO_BSRR_BS_10 0x00000400U
#define GPIO_BSRR_BS_11 0x00000800U
#define GPIO_BSRR_BS_12 0x00001000U
#define GPIO_BSRR_BS_13 0x00002000U
#define GPIO_BSRR_BS_14 0x00004000U
#define GPIO_BSRR_BS_15 0x00008000U
#define GPIO_BSRR_BR_0 0x00010000U
#define GPIO_BSRR_BR_1 0x00020000U
#define GPIO_BSRR_BR_2 0x00040000U
#define GPIO_BSRR_BR_3 0x00080000U
#define GPIO_BSRR_BR_4 0x00100000U
#define GPIO_BSRR_BR_5 0x00200000U
#define GPIO_BSRR_BR_6 0x00400000U
#define GPIO_BSRR_BR_7 0x00800000U
#define GPIO_BSRR_BR_8 0x01000000U
#define GPIO_BSRR_BR_9 0x02000000U
#define GPIO_BSRR_BR_10 0x04000000U
#define GPIO_BSRR_BR_11 0x08000000U
#define GPIO_BSRR_BR_12 0x10000000U
#define GPIO_BSRR_BR_13 0x20000000U
#define GPIO_BSRR_BR_14 0x40000000U
#define GPIO_BSRR_BR_15 0x80000000U
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/* Legacy defines */
#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
@ -13645,6 +13963,12 @@ typedef struct
#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
#define USB_OTG_GUSBCFG_PHYIF_Pos (3U)
#define USB_OTG_GUSBCFG_PHYIF_Msk (0x1UL << USB_OTG_GUSBCFG_PHYIF_Pos) /*!< 0x00000008 */
#define USB_OTG_GUSBCFG_PHYIF USB_OTG_GUSBCFG_PHYIF_Msk /*!< PHY Interface (PHYIf) */
#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos (4U)
#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk (0x1UL << USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos) /*!< 0x00000010 */
#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk /*!< ULPI or UTMI+ Select (ULPI_UTMI_Sel) */
#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
@ -14079,49 +14403,6 @@ typedef struct
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_CHNUM_Pos (0U)
#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos (4U)
#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
#define USB_OTG_DPID_Pos (15U)
#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_PKTSTS_Pos (17U)
#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
#define USB_OTG_EPNUM_Pos (0U)
#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_FRMNUM_Pos (21U)
#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
@ -15230,17 +15511,6 @@ typedef struct
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8) )
/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
((__INSTANCE__) == TIM3) || \
((__INSTANCE__) == TIM4) || \
((__INSTANCE__) == TIM5) || \
((__INSTANCE__) == TIM6) || \
((__INSTANCE__) == TIM7) || \
((__INSTANCE__) == TIM8))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
@ -15287,7 +15557,7 @@ typedef struct
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8))
((__INSTANCE__) == TIM8))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \

738
stm32cube/stm32f7xx/soc/stm32f733xx.h
View File

@ -12,29 +12,13 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@ -1246,6 +1230,10 @@ typedef struct
/* Analog to Digital Converter */
/* */
/******************************************************************************/
#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF07A2A)) /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_ADDR_CMSIS ((uint16_t*) (0x1FF07A2C)) /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR_CMSIS ((uint16_t*) (0x1FF07A2E)) /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD_Pos (0U)
#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
@ -7833,104 +7821,236 @@ typedef struct
#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT_0 0x00000001U
#define GPIO_OTYPER_OT_1 0x00000002U
#define GPIO_OTYPER_OT_2 0x00000004U
#define GPIO_OTYPER_OT_3 0x00000008U
#define GPIO_OTYPER_OT_4 0x00000010U
#define GPIO_OTYPER_OT_5 0x00000020U
#define GPIO_OTYPER_OT_6 0x00000040U
#define GPIO_OTYPER_OT_7 0x00000080U
#define GPIO_OTYPER_OT_8 0x00000100U
#define GPIO_OTYPER_OT_9 0x00000200U
#define GPIO_OTYPER_OT_10 0x00000400U
#define GPIO_OTYPER_OT_11 0x00000800U
#define GPIO_OTYPER_OT_12 0x00001000U
#define GPIO_OTYPER_OT_13 0x00002000U
#define GPIO_OTYPER_OT_14 0x00004000U
#define GPIO_OTYPER_OT_15 0x00008000U
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
/* legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0_Pos GPIO_OSPEEDR_OSPEEDR0_Pos
#define GPIO_OSPEEDER_OSPEEDR0_Msk GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
#define GPIO_OSPEEDER_OSPEEDR1_Pos GPIO_OSPEEDR_OSPEEDR1_Pos
#define GPIO_OSPEEDER_OSPEEDR1_Msk GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
#define GPIO_OSPEEDER_OSPEEDR2_Pos GPIO_OSPEEDR_OSPEEDR2_Pos
#define GPIO_OSPEEDER_OSPEEDR2_Msk GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
#define GPIO_OSPEEDER_OSPEEDR3_Pos GPIO_OSPEEDR_OSPEEDR3_Pos
#define GPIO_OSPEEDER_OSPEEDR3_Msk GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
#define GPIO_OSPEEDER_OSPEEDR4_Pos GPIO_OSPEEDR_OSPEEDR4_Pos
#define GPIO_OSPEEDER_OSPEEDR4_Msk GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
#define GPIO_OSPEEDER_OSPEEDR5_Pos GPIO_OSPEEDR_OSPEEDR5_Pos
#define GPIO_OSPEEDER_OSPEEDR5_Msk GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
#define GPIO_OSPEEDER_OSPEEDR6_Pos GPIO_OSPEEDR_OSPEEDR6_Pos
#define GPIO_OSPEEDER_OSPEEDR6_Msk GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
#define GPIO_OSPEEDER_OSPEEDR7_Pos GPIO_OSPEEDR_OSPEEDR7_Pos
#define GPIO_OSPEEDER_OSPEEDR7_Msk GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
#define GPIO_OSPEEDER_OSPEEDR8_Pos GPIO_OSPEEDR_OSPEEDR8_Pos
#define GPIO_OSPEEDER_OSPEEDR8_Msk GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
#define GPIO_OSPEEDER_OSPEEDR9_Pos GPIO_OSPEEDR_OSPEEDR9_Pos
#define GPIO_OSPEEDER_OSPEEDR9_Msk GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
#define GPIO_OSPEEDER_OSPEEDR10_Pos GPIO_OSPEEDR_OSPEEDR10_Pos
#define GPIO_OSPEEDER_OSPEEDR10_Msk GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
#define GPIO_OSPEEDER_OSPEEDR11_Pos GPIO_OSPEEDR_OSPEEDR11_Pos
#define GPIO_OSPEEDER_OSPEEDR11_Msk GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
#define GPIO_OSPEEDER_OSPEEDR12_Pos GPIO_OSPEEDR_OSPEEDR12_Pos
#define GPIO_OSPEEDER_OSPEEDR12_Msk GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
#define GPIO_OSPEEDER_OSPEEDR13_Pos GPIO_OSPEEDR_OSPEEDR13_Pos
#define GPIO_OSPEEDER_OSPEEDR13_Msk GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
#define GPIO_OSPEEDER_OSPEEDR14_Pos GPIO_OSPEEDR_OSPEEDR14_Pos
#define GPIO_OSPEEDER_OSPEEDR14_Msk GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
#define GPIO_OSPEEDER_OSPEEDR15_Pos GPIO_OSPEEDR_OSPEEDR15_Pos
#define GPIO_OSPEEDER_OSPEEDR15_Msk GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPDR0_Pos (0U)
@ -8015,74 +8135,272 @@ typedef struct
#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_IDR_0 0x00000001U
#define GPIO_IDR_IDR_1 0x00000002U
#define GPIO_IDR_IDR_2 0x00000004U
#define GPIO_IDR_IDR_3 0x00000008U
#define GPIO_IDR_IDR_4 0x00000010U
#define GPIO_IDR_IDR_5 0x00000020U
#define GPIO_IDR_IDR_6 0x00000040U
#define GPIO_IDR_IDR_7 0x00000080U
#define GPIO_IDR_IDR_8 0x00000100U
#define GPIO_IDR_IDR_9 0x00000200U
#define GPIO_IDR_IDR_10 0x00000400U
#define GPIO_IDR_IDR_11 0x00000800U
#define GPIO_IDR_IDR_12 0x00001000U
#define GPIO_IDR_IDR_13 0x00002000U
#define GPIO_IDR_IDR_14 0x00004000U
#define GPIO_IDR_IDR_15 0x00008000U
#define GPIO_IDR_ID0_Pos (0U)
#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos (1U)
#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos (2U)
#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos (3U)
#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos (4U)
#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos (5U)
#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos (6U)
#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos (7U)
#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos (8U)
#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos (9U)
#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos (10U)
#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos (11U)
#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos (12U)
#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos (13U)
#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos (14U)
#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos (15U)
#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
/* Legacy defines */
#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_ODR_0 0x00000001U
#define GPIO_ODR_ODR_1 0x00000002U
#define GPIO_ODR_ODR_2 0x00000004U
#define GPIO_ODR_ODR_3 0x00000008U
#define GPIO_ODR_ODR_4 0x00000010U
#define GPIO_ODR_ODR_5 0x00000020U
#define GPIO_ODR_ODR_6 0x00000040U
#define GPIO_ODR_ODR_7 0x00000080U
#define GPIO_ODR_ODR_8 0x00000100U
#define GPIO_ODR_ODR_9 0x00000200U
#define GPIO_ODR_ODR_10 0x00000400U
#define GPIO_ODR_ODR_11 0x00000800U
#define GPIO_ODR_ODR_12 0x00001000U
#define GPIO_ODR_ODR_13 0x00002000U
#define GPIO_ODR_ODR_14 0x00004000U
#define GPIO_ODR_ODR_15 0x00008000U
#define GPIO_ODR_OD0_Pos (0U)
#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos (1U)
#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos (2U)
#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos (3U)
#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos (4U)
#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos (5U)
#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos (6U)
#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos (7U)
#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos (8U)
#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos (9U)
#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos (10U)
#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos (11U)
#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos (12U)
#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos (13U)
#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos (14U)
#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos (15U)
#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
/* Legacy defines */
#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS_0 0x00000001U
#define GPIO_BSRR_BS_1 0x00000002U
#define GPIO_BSRR_BS_2 0x00000004U
#define GPIO_BSRR_BS_3 0x00000008U
#define GPIO_BSRR_BS_4 0x00000010U
#define GPIO_BSRR_BS_5 0x00000020U
#define GPIO_BSRR_BS_6 0x00000040U
#define GPIO_BSRR_BS_7 0x00000080U
#define GPIO_BSRR_BS_8 0x00000100U
#define GPIO_BSRR_BS_9 0x00000200U
#define GPIO_BSRR_BS_10 0x00000400U
#define GPIO_BSRR_BS_11 0x00000800U
#define GPIO_BSRR_BS_12 0x00001000U
#define GPIO_BSRR_BS_13 0x00002000U
#define GPIO_BSRR_BS_14 0x00004000U
#define GPIO_BSRR_BS_15 0x00008000U
#define GPIO_BSRR_BR_0 0x00010000U
#define GPIO_BSRR_BR_1 0x00020000U
#define GPIO_BSRR_BR_2 0x00040000U
#define GPIO_BSRR_BR_3 0x00080000U
#define GPIO_BSRR_BR_4 0x00100000U
#define GPIO_BSRR_BR_5 0x00200000U
#define GPIO_BSRR_BR_6 0x00400000U
#define GPIO_BSRR_BR_7 0x00800000U
#define GPIO_BSRR_BR_8 0x01000000U
#define GPIO_BSRR_BR_9 0x02000000U
#define GPIO_BSRR_BR_10 0x04000000U
#define GPIO_BSRR_BR_11 0x08000000U
#define GPIO_BSRR_BR_12 0x10000000U
#define GPIO_BSRR_BR_13 0x20000000U
#define GPIO_BSRR_BR_14 0x40000000U
#define GPIO_BSRR_BR_15 0x80000000U
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/* Legacy defines */
#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
@ -14107,49 +14425,6 @@ typedef struct
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_CHNUM_Pos (0U)
#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos (4U)
#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
#define USB_OTG_DPID_Pos (15U)
#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_PKTSTS_Pos (17U)
#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
#define USB_OTG_EPNUM_Pos (0U)
#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_FRMNUM_Pos (21U)
#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
@ -15330,17 +15605,6 @@ typedef struct
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8) )
/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
((__INSTANCE__) == TIM3) || \
((__INSTANCE__) == TIM4) || \
((__INSTANCE__) == TIM5) || \
((__INSTANCE__) == TIM6) || \
((__INSTANCE__) == TIM7) || \
((__INSTANCE__) == TIM8))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
@ -15387,7 +15651,7 @@ typedef struct
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8))
((__INSTANCE__) == TIM8))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \

738
stm32cube/stm32f7xx/soc/stm32f745xx.h
View File

@ -12,29 +12,13 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@ -1378,6 +1362,10 @@ typedef struct
/* Analog to Digital Converter */
/* */
/******************************************************************************/
#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A)) /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_ADDR_CMSIS ((uint16_t*) (0x1FF0F44C)) /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR_CMSIS ((uint16_t*) (0x1FF0F44E)) /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD_Pos (0U)
#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
@ -8393,104 +8381,236 @@ typedef struct
#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT_0 0x00000001U
#define GPIO_OTYPER_OT_1 0x00000002U
#define GPIO_OTYPER_OT_2 0x00000004U
#define GPIO_OTYPER_OT_3 0x00000008U
#define GPIO_OTYPER_OT_4 0x00000010U
#define GPIO_OTYPER_OT_5 0x00000020U
#define GPIO_OTYPER_OT_6 0x00000040U
#define GPIO_OTYPER_OT_7 0x00000080U
#define GPIO_OTYPER_OT_8 0x00000100U
#define GPIO_OTYPER_OT_9 0x00000200U
#define GPIO_OTYPER_OT_10 0x00000400U
#define GPIO_OTYPER_OT_11 0x00000800U
#define GPIO_OTYPER_OT_12 0x00001000U
#define GPIO_OTYPER_OT_13 0x00002000U
#define GPIO_OTYPER_OT_14 0x00004000U
#define GPIO_OTYPER_OT_15 0x00008000U
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
/* legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0_Pos GPIO_OSPEEDR_OSPEEDR0_Pos
#define GPIO_OSPEEDER_OSPEEDR0_Msk GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
#define GPIO_OSPEEDER_OSPEEDR1_Pos GPIO_OSPEEDR_OSPEEDR1_Pos
#define GPIO_OSPEEDER_OSPEEDR1_Msk GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
#define GPIO_OSPEEDER_OSPEEDR2_Pos GPIO_OSPEEDR_OSPEEDR2_Pos
#define GPIO_OSPEEDER_OSPEEDR2_Msk GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
#define GPIO_OSPEEDER_OSPEEDR3_Pos GPIO_OSPEEDR_OSPEEDR3_Pos
#define GPIO_OSPEEDER_OSPEEDR3_Msk GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
#define GPIO_OSPEEDER_OSPEEDR4_Pos GPIO_OSPEEDR_OSPEEDR4_Pos
#define GPIO_OSPEEDER_OSPEEDR4_Msk GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
#define GPIO_OSPEEDER_OSPEEDR5_Pos GPIO_OSPEEDR_OSPEEDR5_Pos
#define GPIO_OSPEEDER_OSPEEDR5_Msk GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
#define GPIO_OSPEEDER_OSPEEDR6_Pos GPIO_OSPEEDR_OSPEEDR6_Pos
#define GPIO_OSPEEDER_OSPEEDR6_Msk GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
#define GPIO_OSPEEDER_OSPEEDR7_Pos GPIO_OSPEEDR_OSPEEDR7_Pos
#define GPIO_OSPEEDER_OSPEEDR7_Msk GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
#define GPIO_OSPEEDER_OSPEEDR8_Pos GPIO_OSPEEDR_OSPEEDR8_Pos
#define GPIO_OSPEEDER_OSPEEDR8_Msk GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
#define GPIO_OSPEEDER_OSPEEDR9_Pos GPIO_OSPEEDR_OSPEEDR9_Pos
#define GPIO_OSPEEDER_OSPEEDR9_Msk GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
#define GPIO_OSPEEDER_OSPEEDR10_Pos GPIO_OSPEEDR_OSPEEDR10_Pos
#define GPIO_OSPEEDER_OSPEEDR10_Msk GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
#define GPIO_OSPEEDER_OSPEEDR11_Pos GPIO_OSPEEDR_OSPEEDR11_Pos
#define GPIO_OSPEEDER_OSPEEDR11_Msk GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
#define GPIO_OSPEEDER_OSPEEDR12_Pos GPIO_OSPEEDR_OSPEEDR12_Pos
#define GPIO_OSPEEDER_OSPEEDR12_Msk GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
#define GPIO_OSPEEDER_OSPEEDR13_Pos GPIO_OSPEEDR_OSPEEDR13_Pos
#define GPIO_OSPEEDER_OSPEEDR13_Msk GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
#define GPIO_OSPEEDER_OSPEEDR14_Pos GPIO_OSPEEDR_OSPEEDR14_Pos
#define GPIO_OSPEEDER_OSPEEDR14_Msk GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
#define GPIO_OSPEEDER_OSPEEDR15_Pos GPIO_OSPEEDR_OSPEEDR15_Pos
#define GPIO_OSPEEDER_OSPEEDR15_Msk GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPDR0_Pos (0U)
@ -8575,74 +8695,272 @@ typedef struct
#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_IDR_0 0x00000001U
#define GPIO_IDR_IDR_1 0x00000002U
#define GPIO_IDR_IDR_2 0x00000004U
#define GPIO_IDR_IDR_3 0x00000008U
#define GPIO_IDR_IDR_4 0x00000010U
#define GPIO_IDR_IDR_5 0x00000020U
#define GPIO_IDR_IDR_6 0x00000040U
#define GPIO_IDR_IDR_7 0x00000080U
#define GPIO_IDR_IDR_8 0x00000100U
#define GPIO_IDR_IDR_9 0x00000200U
#define GPIO_IDR_IDR_10 0x00000400U
#define GPIO_IDR_IDR_11 0x00000800U
#define GPIO_IDR_IDR_12 0x00001000U
#define GPIO_IDR_IDR_13 0x00002000U
#define GPIO_IDR_IDR_14 0x00004000U
#define GPIO_IDR_IDR_15 0x00008000U
#define GPIO_IDR_ID0_Pos (0U)
#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos (1U)
#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos (2U)
#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos (3U)
#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos (4U)
#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos (5U)
#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos (6U)
#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos (7U)
#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos (8U)
#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos (9U)
#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos (10U)
#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos (11U)
#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos (12U)
#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos (13U)
#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos (14U)
#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos (15U)
#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
/* Legacy defines */
#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_ODR_0 0x00000001U
#define GPIO_ODR_ODR_1 0x00000002U
#define GPIO_ODR_ODR_2 0x00000004U
#define GPIO_ODR_ODR_3 0x00000008U
#define GPIO_ODR_ODR_4 0x00000010U
#define GPIO_ODR_ODR_5 0x00000020U
#define GPIO_ODR_ODR_6 0x00000040U
#define GPIO_ODR_ODR_7 0x00000080U
#define GPIO_ODR_ODR_8 0x00000100U
#define GPIO_ODR_ODR_9 0x00000200U
#define GPIO_ODR_ODR_10 0x00000400U
#define GPIO_ODR_ODR_11 0x00000800U
#define GPIO_ODR_ODR_12 0x00001000U
#define GPIO_ODR_ODR_13 0x00002000U
#define GPIO_ODR_ODR_14 0x00004000U
#define GPIO_ODR_ODR_15 0x00008000U
#define GPIO_ODR_OD0_Pos (0U)
#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos (1U)
#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos (2U)
#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos (3U)
#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos (4U)
#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos (5U)
#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos (6U)
#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos (7U)
#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos (8U)
#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos (9U)
#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos (10U)
#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos (11U)
#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos (12U)
#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos (13U)
#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos (14U)
#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos (15U)
#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
/* Legacy defines */
#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS_0 0x00000001U
#define GPIO_BSRR_BS_1 0x00000002U
#define GPIO_BSRR_BS_2 0x00000004U
#define GPIO_BSRR_BS_3 0x00000008U
#define GPIO_BSRR_BS_4 0x00000010U
#define GPIO_BSRR_BS_5 0x00000020U
#define GPIO_BSRR_BS_6 0x00000040U
#define GPIO_BSRR_BS_7 0x00000080U
#define GPIO_BSRR_BS_8 0x00000100U
#define GPIO_BSRR_BS_9 0x00000200U
#define GPIO_BSRR_BS_10 0x00000400U
#define GPIO_BSRR_BS_11 0x00000800U
#define GPIO_BSRR_BS_12 0x00001000U
#define GPIO_BSRR_BS_13 0x00002000U
#define GPIO_BSRR_BS_14 0x00004000U
#define GPIO_BSRR_BS_15 0x00008000U
#define GPIO_BSRR_BR_0 0x00010000U
#define GPIO_BSRR_BR_1 0x00020000U
#define GPIO_BSRR_BR_2 0x00040000U
#define GPIO_BSRR_BR_3 0x00080000U
#define GPIO_BSRR_BR_4 0x00100000U
#define GPIO_BSRR_BR_5 0x00200000U
#define GPIO_BSRR_BR_6 0x00400000U
#define GPIO_BSRR_BR_7 0x00800000U
#define GPIO_BSRR_BR_8 0x01000000U
#define GPIO_BSRR_BR_9 0x02000000U
#define GPIO_BSRR_BR_10 0x04000000U
#define GPIO_BSRR_BR_11 0x08000000U
#define GPIO_BSRR_BR_12 0x10000000U
#define GPIO_BSRR_BR_13 0x20000000U
#define GPIO_BSRR_BR_14 0x40000000U
#define GPIO_BSRR_BR_15 0x80000000U
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/* Legacy defines */
#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
@ -15895,49 +16213,6 @@ typedef struct
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_CHNUM_Pos (0U)
#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos (4U)
#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
#define USB_OTG_DPID_Pos (15U)
#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_PKTSTS_Pos (17U)
#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
#define USB_OTG_EPNUM_Pos (0U)
#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_FRMNUM_Pos (21U)
#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
@ -17059,17 +17334,6 @@ typedef struct
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8) )
/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
((__INSTANCE__) == TIM3) || \
((__INSTANCE__) == TIM4) || \
((__INSTANCE__) == TIM5) || \
((__INSTANCE__) == TIM6) || \
((__INSTANCE__) == TIM7) || \
((__INSTANCE__) == TIM8))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
@ -17116,7 +17380,7 @@ typedef struct
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8))
((__INSTANCE__) == TIM8))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \

738
stm32cube/stm32f7xx/soc/stm32f746xx.h
View File

@ -12,29 +12,13 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@ -1433,6 +1417,10 @@ typedef struct
/* Analog to Digital Converter */
/* */
/******************************************************************************/
#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A)) /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_ADDR_CMSIS ((uint16_t*) (0x1FF0F44C)) /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR_CMSIS ((uint16_t*) (0x1FF0F44E)) /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD_Pos (0U)
#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
@ -8448,104 +8436,236 @@ typedef struct
#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT_0 0x00000001U
#define GPIO_OTYPER_OT_1 0x00000002U
#define GPIO_OTYPER_OT_2 0x00000004U
#define GPIO_OTYPER_OT_3 0x00000008U
#define GPIO_OTYPER_OT_4 0x00000010U
#define GPIO_OTYPER_OT_5 0x00000020U
#define GPIO_OTYPER_OT_6 0x00000040U
#define GPIO_OTYPER_OT_7 0x00000080U
#define GPIO_OTYPER_OT_8 0x00000100U
#define GPIO_OTYPER_OT_9 0x00000200U
#define GPIO_OTYPER_OT_10 0x00000400U
#define GPIO_OTYPER_OT_11 0x00000800U
#define GPIO_OTYPER_OT_12 0x00001000U
#define GPIO_OTYPER_OT_13 0x00002000U
#define GPIO_OTYPER_OT_14 0x00004000U
#define GPIO_OTYPER_OT_15 0x00008000U
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
/* legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0_Pos GPIO_OSPEEDR_OSPEEDR0_Pos
#define GPIO_OSPEEDER_OSPEEDR0_Msk GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
#define GPIO_OSPEEDER_OSPEEDR1_Pos GPIO_OSPEEDR_OSPEEDR1_Pos
#define GPIO_OSPEEDER_OSPEEDR1_Msk GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
#define GPIO_OSPEEDER_OSPEEDR2_Pos GPIO_OSPEEDR_OSPEEDR2_Pos
#define GPIO_OSPEEDER_OSPEEDR2_Msk GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
#define GPIO_OSPEEDER_OSPEEDR3_Pos GPIO_OSPEEDR_OSPEEDR3_Pos
#define GPIO_OSPEEDER_OSPEEDR3_Msk GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
#define GPIO_OSPEEDER_OSPEEDR4_Pos GPIO_OSPEEDR_OSPEEDR4_Pos
#define GPIO_OSPEEDER_OSPEEDR4_Msk GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
#define GPIO_OSPEEDER_OSPEEDR5_Pos GPIO_OSPEEDR_OSPEEDR5_Pos
#define GPIO_OSPEEDER_OSPEEDR5_Msk GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
#define GPIO_OSPEEDER_OSPEEDR6_Pos GPIO_OSPEEDR_OSPEEDR6_Pos
#define GPIO_OSPEEDER_OSPEEDR6_Msk GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
#define GPIO_OSPEEDER_OSPEEDR7_Pos GPIO_OSPEEDR_OSPEEDR7_Pos
#define GPIO_OSPEEDER_OSPEEDR7_Msk GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
#define GPIO_OSPEEDER_OSPEEDR8_Pos GPIO_OSPEEDR_OSPEEDR8_Pos
#define GPIO_OSPEEDER_OSPEEDR8_Msk GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
#define GPIO_OSPEEDER_OSPEEDR9_Pos GPIO_OSPEEDR_OSPEEDR9_Pos
#define GPIO_OSPEEDER_OSPEEDR9_Msk GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
#define GPIO_OSPEEDER_OSPEEDR10_Pos GPIO_OSPEEDR_OSPEEDR10_Pos
#define GPIO_OSPEEDER_OSPEEDR10_Msk GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
#define GPIO_OSPEEDER_OSPEEDR11_Pos GPIO_OSPEEDR_OSPEEDR11_Pos
#define GPIO_OSPEEDER_OSPEEDR11_Msk GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
#define GPIO_OSPEEDER_OSPEEDR12_Pos GPIO_OSPEEDR_OSPEEDR12_Pos
#define GPIO_OSPEEDER_OSPEEDR12_Msk GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
#define GPIO_OSPEEDER_OSPEEDR13_Pos GPIO_OSPEEDR_OSPEEDR13_Pos
#define GPIO_OSPEEDER_OSPEEDR13_Msk GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
#define GPIO_OSPEEDER_OSPEEDR14_Pos GPIO_OSPEEDR_OSPEEDR14_Pos
#define GPIO_OSPEEDER_OSPEEDR14_Msk GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
#define GPIO_OSPEEDER_OSPEEDR15_Pos GPIO_OSPEEDR_OSPEEDR15_Pos
#define GPIO_OSPEEDER_OSPEEDR15_Msk GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPDR0_Pos (0U)
@ -8630,74 +8750,272 @@ typedef struct
#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_IDR_0 0x00000001U
#define GPIO_IDR_IDR_1 0x00000002U
#define GPIO_IDR_IDR_2 0x00000004U
#define GPIO_IDR_IDR_3 0x00000008U
#define GPIO_IDR_IDR_4 0x00000010U
#define GPIO_IDR_IDR_5 0x00000020U
#define GPIO_IDR_IDR_6 0x00000040U
#define GPIO_IDR_IDR_7 0x00000080U
#define GPIO_IDR_IDR_8 0x00000100U
#define GPIO_IDR_IDR_9 0x00000200U
#define GPIO_IDR_IDR_10 0x00000400U
#define GPIO_IDR_IDR_11 0x00000800U
#define GPIO_IDR_IDR_12 0x00001000U
#define GPIO_IDR_IDR_13 0x00002000U
#define GPIO_IDR_IDR_14 0x00004000U
#define GPIO_IDR_IDR_15 0x00008000U
#define GPIO_IDR_ID0_Pos (0U)
#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos (1U)
#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos (2U)
#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos (3U)
#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos (4U)
#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos (5U)
#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos (6U)
#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos (7U)
#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos (8U)
#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos (9U)
#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos (10U)
#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos (11U)
#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos (12U)
#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos (13U)
#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos (14U)
#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos (15U)
#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
/* Legacy defines */
#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_ODR_0 0x00000001U
#define GPIO_ODR_ODR_1 0x00000002U
#define GPIO_ODR_ODR_2 0x00000004U
#define GPIO_ODR_ODR_3 0x00000008U
#define GPIO_ODR_ODR_4 0x00000010U
#define GPIO_ODR_ODR_5 0x00000020U
#define GPIO_ODR_ODR_6 0x00000040U
#define GPIO_ODR_ODR_7 0x00000080U
#define GPIO_ODR_ODR_8 0x00000100U
#define GPIO_ODR_ODR_9 0x00000200U
#define GPIO_ODR_ODR_10 0x00000400U
#define GPIO_ODR_ODR_11 0x00000800U
#define GPIO_ODR_ODR_12 0x00001000U
#define GPIO_ODR_ODR_13 0x00002000U
#define GPIO_ODR_ODR_14 0x00004000U
#define GPIO_ODR_ODR_15 0x00008000U
#define GPIO_ODR_OD0_Pos (0U)
#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos (1U)
#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos (2U)
#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos (3U)
#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos (4U)
#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos (5U)
#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos (6U)
#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos (7U)
#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos (8U)
#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos (9U)
#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos (10U)
#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos (11U)
#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos (12U)
#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos (13U)
#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos (14U)
#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos (15U)
#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
/* Legacy defines */
#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS_0 0x00000001U
#define GPIO_BSRR_BS_1 0x00000002U
#define GPIO_BSRR_BS_2 0x00000004U
#define GPIO_BSRR_BS_3 0x00000008U
#define GPIO_BSRR_BS_4 0x00000010U
#define GPIO_BSRR_BS_5 0x00000020U
#define GPIO_BSRR_BS_6 0x00000040U
#define GPIO_BSRR_BS_7 0x00000080U
#define GPIO_BSRR_BS_8 0x00000100U
#define GPIO_BSRR_BS_9 0x00000200U
#define GPIO_BSRR_BS_10 0x00000400U
#define GPIO_BSRR_BS_11 0x00000800U
#define GPIO_BSRR_BS_12 0x00001000U
#define GPIO_BSRR_BS_13 0x00002000U
#define GPIO_BSRR_BS_14 0x00004000U
#define GPIO_BSRR_BS_15 0x00008000U
#define GPIO_BSRR_BR_0 0x00010000U
#define GPIO_BSRR_BR_1 0x00020000U
#define GPIO_BSRR_BR_2 0x00040000U
#define GPIO_BSRR_BR_3 0x00080000U
#define GPIO_BSRR_BR_4 0x00100000U
#define GPIO_BSRR_BR_5 0x00200000U
#define GPIO_BSRR_BR_6 0x00400000U
#define GPIO_BSRR_BR_7 0x00800000U
#define GPIO_BSRR_BR_8 0x01000000U
#define GPIO_BSRR_BR_9 0x02000000U
#define GPIO_BSRR_BR_10 0x04000000U
#define GPIO_BSRR_BR_11 0x08000000U
#define GPIO_BSRR_BR_12 0x10000000U
#define GPIO_BSRR_BR_13 0x20000000U
#define GPIO_BSRR_BR_14 0x40000000U
#define GPIO_BSRR_BR_15 0x80000000U
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/* Legacy defines */
#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
@ -16243,49 +16561,6 @@ typedef struct
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_CHNUM_Pos (0U)
#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos (4U)
#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
#define USB_OTG_DPID_Pos (15U)
#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_PKTSTS_Pos (17U)
#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
#define USB_OTG_EPNUM_Pos (0U)
#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_FRMNUM_Pos (21U)
#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
@ -17409,17 +17684,6 @@ typedef struct
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8) )
/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
((__INSTANCE__) == TIM3) || \
((__INSTANCE__) == TIM4) || \
((__INSTANCE__) == TIM5) || \
((__INSTANCE__) == TIM6) || \
((__INSTANCE__) == TIM7) || \
((__INSTANCE__) == TIM8))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
@ -17466,7 +17730,7 @@ typedef struct
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8))
((__INSTANCE__) == TIM8))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \

738
stm32cube/stm32f7xx/soc/stm32f750xx.h
View File

@ -12,29 +12,13 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@ -1508,6 +1492,10 @@ typedef struct
/* Analog to Digital Converter */
/* */
/******************************************************************************/
#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A)) /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_ADDR_CMSIS ((uint16_t*) (0x1FF0F44C)) /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR_CMSIS ((uint16_t*) (0x1FF0F44E)) /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD_Pos (0U)
#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
@ -8636,104 +8624,236 @@ typedef struct
#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT_0 0x00000001U
#define GPIO_OTYPER_OT_1 0x00000002U
#define GPIO_OTYPER_OT_2 0x00000004U
#define GPIO_OTYPER_OT_3 0x00000008U
#define GPIO_OTYPER_OT_4 0x00000010U
#define GPIO_OTYPER_OT_5 0x00000020U
#define GPIO_OTYPER_OT_6 0x00000040U
#define GPIO_OTYPER_OT_7 0x00000080U
#define GPIO_OTYPER_OT_8 0x00000100U
#define GPIO_OTYPER_OT_9 0x00000200U
#define GPIO_OTYPER_OT_10 0x00000400U
#define GPIO_OTYPER_OT_11 0x00000800U
#define GPIO_OTYPER_OT_12 0x00001000U
#define GPIO_OTYPER_OT_13 0x00002000U
#define GPIO_OTYPER_OT_14 0x00004000U
#define GPIO_OTYPER_OT_15 0x00008000U
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
/* legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0_Pos GPIO_OSPEEDR_OSPEEDR0_Pos
#define GPIO_OSPEEDER_OSPEEDR0_Msk GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
#define GPIO_OSPEEDER_OSPEEDR1_Pos GPIO_OSPEEDR_OSPEEDR1_Pos
#define GPIO_OSPEEDER_OSPEEDR1_Msk GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
#define GPIO_OSPEEDER_OSPEEDR2_Pos GPIO_OSPEEDR_OSPEEDR2_Pos
#define GPIO_OSPEEDER_OSPEEDR2_Msk GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
#define GPIO_OSPEEDER_OSPEEDR3_Pos GPIO_OSPEEDR_OSPEEDR3_Pos
#define GPIO_OSPEEDER_OSPEEDR3_Msk GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
#define GPIO_OSPEEDER_OSPEEDR4_Pos GPIO_OSPEEDR_OSPEEDR4_Pos
#define GPIO_OSPEEDER_OSPEEDR4_Msk GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
#define GPIO_OSPEEDER_OSPEEDR5_Pos GPIO_OSPEEDR_OSPEEDR5_Pos
#define GPIO_OSPEEDER_OSPEEDR5_Msk GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
#define GPIO_OSPEEDER_OSPEEDR6_Pos GPIO_OSPEEDR_OSPEEDR6_Pos
#define GPIO_OSPEEDER_OSPEEDR6_Msk GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
#define GPIO_OSPEEDER_OSPEEDR7_Pos GPIO_OSPEEDR_OSPEEDR7_Pos
#define GPIO_OSPEEDER_OSPEEDR7_Msk GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
#define GPIO_OSPEEDER_OSPEEDR8_Pos GPIO_OSPEEDR_OSPEEDR8_Pos
#define GPIO_OSPEEDER_OSPEEDR8_Msk GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
#define GPIO_OSPEEDER_OSPEEDR9_Pos GPIO_OSPEEDR_OSPEEDR9_Pos
#define GPIO_OSPEEDER_OSPEEDR9_Msk GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
#define GPIO_OSPEEDER_OSPEEDR10_Pos GPIO_OSPEEDR_OSPEEDR10_Pos
#define GPIO_OSPEEDER_OSPEEDR10_Msk GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
#define GPIO_OSPEEDER_OSPEEDR11_Pos GPIO_OSPEEDR_OSPEEDR11_Pos
#define GPIO_OSPEEDER_OSPEEDR11_Msk GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
#define GPIO_OSPEEDER_OSPEEDR12_Pos GPIO_OSPEEDR_OSPEEDR12_Pos
#define GPIO_OSPEEDER_OSPEEDR12_Msk GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
#define GPIO_OSPEEDER_OSPEEDR13_Pos GPIO_OSPEEDR_OSPEEDR13_Pos
#define GPIO_OSPEEDER_OSPEEDR13_Msk GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
#define GPIO_OSPEEDER_OSPEEDR14_Pos GPIO_OSPEEDR_OSPEEDR14_Pos
#define GPIO_OSPEEDER_OSPEEDR14_Msk GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
#define GPIO_OSPEEDER_OSPEEDR15_Pos GPIO_OSPEEDR_OSPEEDR15_Pos
#define GPIO_OSPEEDER_OSPEEDR15_Msk GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPDR0_Pos (0U)
@ -8818,74 +8938,272 @@ typedef struct
#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_IDR_0 0x00000001U
#define GPIO_IDR_IDR_1 0x00000002U
#define GPIO_IDR_IDR_2 0x00000004U
#define GPIO_IDR_IDR_3 0x00000008U
#define GPIO_IDR_IDR_4 0x00000010U
#define GPIO_IDR_IDR_5 0x00000020U
#define GPIO_IDR_IDR_6 0x00000040U
#define GPIO_IDR_IDR_7 0x00000080U
#define GPIO_IDR_IDR_8 0x00000100U
#define GPIO_IDR_IDR_9 0x00000200U
#define GPIO_IDR_IDR_10 0x00000400U
#define GPIO_IDR_IDR_11 0x00000800U
#define GPIO_IDR_IDR_12 0x00001000U
#define GPIO_IDR_IDR_13 0x00002000U
#define GPIO_IDR_IDR_14 0x00004000U
#define GPIO_IDR_IDR_15 0x00008000U
#define GPIO_IDR_ID0_Pos (0U)
#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos (1U)
#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos (2U)
#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos (3U)
#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos (4U)
#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos (5U)
#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos (6U)
#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos (7U)
#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos (8U)
#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos (9U)
#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos (10U)
#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos (11U)
#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos (12U)
#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos (13U)
#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos (14U)
#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos (15U)
#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
/* Legacy defines */
#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_ODR_0 0x00000001U
#define GPIO_ODR_ODR_1 0x00000002U
#define GPIO_ODR_ODR_2 0x00000004U
#define GPIO_ODR_ODR_3 0x00000008U
#define GPIO_ODR_ODR_4 0x00000010U
#define GPIO_ODR_ODR_5 0x00000020U
#define GPIO_ODR_ODR_6 0x00000040U
#define GPIO_ODR_ODR_7 0x00000080U
#define GPIO_ODR_ODR_8 0x00000100U
#define GPIO_ODR_ODR_9 0x00000200U
#define GPIO_ODR_ODR_10 0x00000400U
#define GPIO_ODR_ODR_11 0x00000800U
#define GPIO_ODR_ODR_12 0x00001000U
#define GPIO_ODR_ODR_13 0x00002000U
#define GPIO_ODR_ODR_14 0x00004000U
#define GPIO_ODR_ODR_15 0x00008000U
#define GPIO_ODR_OD0_Pos (0U)
#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos (1U)
#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos (2U)
#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos (3U)
#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos (4U)
#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos (5U)
#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos (6U)
#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos (7U)
#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos (8U)
#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos (9U)
#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos (10U)
#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos (11U)
#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos (12U)
#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos (13U)
#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos (14U)
#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos (15U)
#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
/* Legacy defines */
#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS_0 0x00000001U
#define GPIO_BSRR_BS_1 0x00000002U
#define GPIO_BSRR_BS_2 0x00000004U
#define GPIO_BSRR_BS_3 0x00000008U
#define GPIO_BSRR_BS_4 0x00000010U
#define GPIO_BSRR_BS_5 0x00000020U
#define GPIO_BSRR_BS_6 0x00000040U
#define GPIO_BSRR_BS_7 0x00000080U
#define GPIO_BSRR_BS_8 0x00000100U
#define GPIO_BSRR_BS_9 0x00000200U
#define GPIO_BSRR_BS_10 0x00000400U
#define GPIO_BSRR_BS_11 0x00000800U
#define GPIO_BSRR_BS_12 0x00001000U
#define GPIO_BSRR_BS_13 0x00002000U
#define GPIO_BSRR_BS_14 0x00004000U
#define GPIO_BSRR_BS_15 0x00008000U
#define GPIO_BSRR_BR_0 0x00010000U
#define GPIO_BSRR_BR_1 0x00020000U
#define GPIO_BSRR_BR_2 0x00040000U
#define GPIO_BSRR_BR_3 0x00080000U
#define GPIO_BSRR_BR_4 0x00100000U
#define GPIO_BSRR_BR_5 0x00200000U
#define GPIO_BSRR_BR_6 0x00400000U
#define GPIO_BSRR_BR_7 0x00800000U
#define GPIO_BSRR_BR_8 0x01000000U
#define GPIO_BSRR_BR_9 0x02000000U
#define GPIO_BSRR_BR_10 0x04000000U
#define GPIO_BSRR_BR_11 0x08000000U
#define GPIO_BSRR_BR_12 0x10000000U
#define GPIO_BSRR_BR_13 0x20000000U
#define GPIO_BSRR_BR_14 0x40000000U
#define GPIO_BSRR_BR_15 0x80000000U
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/* Legacy defines */
#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
@ -16536,49 +16854,6 @@ typedef struct
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_CHNUM_Pos (0U)
#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos (4U)
#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
#define USB_OTG_DPID_Pos (15U)
#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_PKTSTS_Pos (17U)
#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
#define USB_OTG_EPNUM_Pos (0U)
#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_FRMNUM_Pos (21U)
#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
@ -17702,17 +17977,6 @@ typedef struct
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8) )
/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
((__INSTANCE__) == TIM3) || \
((__INSTANCE__) == TIM4) || \
((__INSTANCE__) == TIM5) || \
((__INSTANCE__) == TIM6) || \
((__INSTANCE__) == TIM7) || \
((__INSTANCE__) == TIM8))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
@ -17759,7 +18023,7 @@ typedef struct
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8))
((__INSTANCE__) == TIM8))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \

738
stm32cube/stm32f7xx/soc/stm32f756xx.h
View File

@ -12,29 +12,13 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@ -1508,6 +1492,10 @@ typedef struct
/* Analog to Digital Converter */
/* */
/******************************************************************************/
#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A)) /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_ADDR_CMSIS ((uint16_t*) (0x1FF0F44C)) /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR_CMSIS ((uint16_t*) (0x1FF0F44E)) /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD_Pos (0U)
#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
@ -8636,104 +8624,236 @@ typedef struct
#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT_0 0x00000001U
#define GPIO_OTYPER_OT_1 0x00000002U
#define GPIO_OTYPER_OT_2 0x00000004U
#define GPIO_OTYPER_OT_3 0x00000008U
#define GPIO_OTYPER_OT_4 0x00000010U
#define GPIO_OTYPER_OT_5 0x00000020U
#define GPIO_OTYPER_OT_6 0x00000040U
#define GPIO_OTYPER_OT_7 0x00000080U
#define GPIO_OTYPER_OT_8 0x00000100U
#define GPIO_OTYPER_OT_9 0x00000200U
#define GPIO_OTYPER_OT_10 0x00000400U
#define GPIO_OTYPER_OT_11 0x00000800U
#define GPIO_OTYPER_OT_12 0x00001000U
#define GPIO_OTYPER_OT_13 0x00002000U
#define GPIO_OTYPER_OT_14 0x00004000U
#define GPIO_OTYPER_OT_15 0x00008000U
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
/* legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0_Pos GPIO_OSPEEDR_OSPEEDR0_Pos
#define GPIO_OSPEEDER_OSPEEDR0_Msk GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
#define GPIO_OSPEEDER_OSPEEDR1_Pos GPIO_OSPEEDR_OSPEEDR1_Pos
#define GPIO_OSPEEDER_OSPEEDR1_Msk GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
#define GPIO_OSPEEDER_OSPEEDR2_Pos GPIO_OSPEEDR_OSPEEDR2_Pos
#define GPIO_OSPEEDER_OSPEEDR2_Msk GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
#define GPIO_OSPEEDER_OSPEEDR3_Pos GPIO_OSPEEDR_OSPEEDR3_Pos
#define GPIO_OSPEEDER_OSPEEDR3_Msk GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
#define GPIO_OSPEEDER_OSPEEDR4_Pos GPIO_OSPEEDR_OSPEEDR4_Pos
#define GPIO_OSPEEDER_OSPEEDR4_Msk GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
#define GPIO_OSPEEDER_OSPEEDR5_Pos GPIO_OSPEEDR_OSPEEDR5_Pos
#define GPIO_OSPEEDER_OSPEEDR5_Msk GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
#define GPIO_OSPEEDER_OSPEEDR6_Pos GPIO_OSPEEDR_OSPEEDR6_Pos
#define GPIO_OSPEEDER_OSPEEDR6_Msk GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
#define GPIO_OSPEEDER_OSPEEDR7_Pos GPIO_OSPEEDR_OSPEEDR7_Pos
#define GPIO_OSPEEDER_OSPEEDR7_Msk GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
#define GPIO_OSPEEDER_OSPEEDR8_Pos GPIO_OSPEEDR_OSPEEDR8_Pos
#define GPIO_OSPEEDER_OSPEEDR8_Msk GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
#define GPIO_OSPEEDER_OSPEEDR9_Pos GPIO_OSPEEDR_OSPEEDR9_Pos
#define GPIO_OSPEEDER_OSPEEDR9_Msk GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
#define GPIO_OSPEEDER_OSPEEDR10_Pos GPIO_OSPEEDR_OSPEEDR10_Pos
#define GPIO_OSPEEDER_OSPEEDR10_Msk GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
#define GPIO_OSPEEDER_OSPEEDR11_Pos GPIO_OSPEEDR_OSPEEDR11_Pos
#define GPIO_OSPEEDER_OSPEEDR11_Msk GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
#define GPIO_OSPEEDER_OSPEEDR12_Pos GPIO_OSPEEDR_OSPEEDR12_Pos
#define GPIO_OSPEEDER_OSPEEDR12_Msk GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
#define GPIO_OSPEEDER_OSPEEDR13_Pos GPIO_OSPEEDR_OSPEEDR13_Pos
#define GPIO_OSPEEDER_OSPEEDR13_Msk GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
#define GPIO_OSPEEDER_OSPEEDR14_Pos GPIO_OSPEEDR_OSPEEDR14_Pos
#define GPIO_OSPEEDER_OSPEEDR14_Msk GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
#define GPIO_OSPEEDER_OSPEEDR15_Pos GPIO_OSPEEDR_OSPEEDR15_Pos
#define GPIO_OSPEEDER_OSPEEDR15_Msk GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPDR0_Pos (0U)
@ -8818,74 +8938,272 @@ typedef struct
#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_IDR_0 0x00000001U
#define GPIO_IDR_IDR_1 0x00000002U
#define GPIO_IDR_IDR_2 0x00000004U
#define GPIO_IDR_IDR_3 0x00000008U
#define GPIO_IDR_IDR_4 0x00000010U
#define GPIO_IDR_IDR_5 0x00000020U
#define GPIO_IDR_IDR_6 0x00000040U
#define GPIO_IDR_IDR_7 0x00000080U
#define GPIO_IDR_IDR_8 0x00000100U
#define GPIO_IDR_IDR_9 0x00000200U
#define GPIO_IDR_IDR_10 0x00000400U
#define GPIO_IDR_IDR_11 0x00000800U
#define GPIO_IDR_IDR_12 0x00001000U
#define GPIO_IDR_IDR_13 0x00002000U
#define GPIO_IDR_IDR_14 0x00004000U
#define GPIO_IDR_IDR_15 0x00008000U
#define GPIO_IDR_ID0_Pos (0U)
#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos (1U)
#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos (2U)
#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos (3U)
#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos (4U)
#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos (5U)
#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos (6U)
#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos (7U)
#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos (8U)
#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos (9U)
#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos (10U)
#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos (11U)
#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos (12U)
#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos (13U)
#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos (14U)
#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos (15U)
#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
/* Legacy defines */
#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_ODR_0 0x00000001U
#define GPIO_ODR_ODR_1 0x00000002U
#define GPIO_ODR_ODR_2 0x00000004U
#define GPIO_ODR_ODR_3 0x00000008U
#define GPIO_ODR_ODR_4 0x00000010U
#define GPIO_ODR_ODR_5 0x00000020U
#define GPIO_ODR_ODR_6 0x00000040U
#define GPIO_ODR_ODR_7 0x00000080U
#define GPIO_ODR_ODR_8 0x00000100U
#define GPIO_ODR_ODR_9 0x00000200U
#define GPIO_ODR_ODR_10 0x00000400U
#define GPIO_ODR_ODR_11 0x00000800U
#define GPIO_ODR_ODR_12 0x00001000U
#define GPIO_ODR_ODR_13 0x00002000U
#define GPIO_ODR_ODR_14 0x00004000U
#define GPIO_ODR_ODR_15 0x00008000U
#define GPIO_ODR_OD0_Pos (0U)
#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos (1U)
#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos (2U)
#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos (3U)
#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos (4U)
#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos (5U)
#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos (6U)
#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos (7U)
#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos (8U)
#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos (9U)
#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos (10U)
#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos (11U)
#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos (12U)
#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos (13U)
#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos (14U)
#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos (15U)
#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
/* Legacy defines */
#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS_0 0x00000001U
#define GPIO_BSRR_BS_1 0x00000002U
#define GPIO_BSRR_BS_2 0x00000004U
#define GPIO_BSRR_BS_3 0x00000008U
#define GPIO_BSRR_BS_4 0x00000010U
#define GPIO_BSRR_BS_5 0x00000020U
#define GPIO_BSRR_BS_6 0x00000040U
#define GPIO_BSRR_BS_7 0x00000080U
#define GPIO_BSRR_BS_8 0x00000100U
#define GPIO_BSRR_BS_9 0x00000200U
#define GPIO_BSRR_BS_10 0x00000400U
#define GPIO_BSRR_BS_11 0x00000800U
#define GPIO_BSRR_BS_12 0x00001000U
#define GPIO_BSRR_BS_13 0x00002000U
#define GPIO_BSRR_BS_14 0x00004000U
#define GPIO_BSRR_BS_15 0x00008000U
#define GPIO_BSRR_BR_0 0x00010000U
#define GPIO_BSRR_BR_1 0x00020000U
#define GPIO_BSRR_BR_2 0x00040000U
#define GPIO_BSRR_BR_3 0x00080000U
#define GPIO_BSRR_BR_4 0x00100000U
#define GPIO_BSRR_BR_5 0x00200000U
#define GPIO_BSRR_BR_6 0x00400000U
#define GPIO_BSRR_BR_7 0x00800000U
#define GPIO_BSRR_BR_8 0x01000000U
#define GPIO_BSRR_BR_9 0x02000000U
#define GPIO_BSRR_BR_10 0x04000000U
#define GPIO_BSRR_BR_11 0x08000000U
#define GPIO_BSRR_BR_12 0x10000000U
#define GPIO_BSRR_BR_13 0x20000000U
#define GPIO_BSRR_BR_14 0x40000000U
#define GPIO_BSRR_BR_15 0x80000000U
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/* Legacy defines */
#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
@ -16536,49 +16854,6 @@ typedef struct
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_CHNUM_Pos (0U)
#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos (4U)
#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
#define USB_OTG_DPID_Pos (15U)
#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_PKTSTS_Pos (17U)
#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
#define USB_OTG_EPNUM_Pos (0U)
#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_FRMNUM_Pos (21U)
#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
@ -17702,17 +17977,6 @@ typedef struct
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8) )
/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
(((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
((__INSTANCE__) == TIM3) || \
((__INSTANCE__) == TIM4) || \
((__INSTANCE__) == TIM5) || \
((__INSTANCE__) == TIM6) || \
((__INSTANCE__) == TIM7) || \
((__INSTANCE__) == TIM8))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
@ -17759,7 +18023,7 @@ typedef struct
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM8))
((__INSTANCE__) == TIM8))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \

Some files were not shown because too many files have changed in this diff Show More