stm32cube: update stm32f7 to version V1.16.1
Update Cube version for STM32F7xx series on https://github.com/STMicroelectronics from version v1.16.0 to version v1.16.1 Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
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8599539184
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2219f386e8
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@ -40,20 +40,4 @@ Patch List:
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-dos2unix applied
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-trailing white spaces removed
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*Extend public SetFlashLatency API to all families
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The LL_SetFlashLatency public API is now defined for families
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beyond G4, L4 and L5. The private function has been made public.
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Impacted files:
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drivers/include/stm32f7xx_ll_utils.h
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drivers/src/stm32f7xx_ll_utils.c
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ST Bug tracker ID: 76122
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*Fix LL_EXTI_LINE_18 and LL_EXTI_LINE_20 declarations
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LL_EXTI_LINE_18 and LL_EXTI_LINE_20 are declared in stm32f7xx_hal_pcd.h
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and in stm32f7xx_ll_exti.h which generates warnings. Set #ifndef
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in stm32f7xx_ll_exti.h around declarations.
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Impacted files:
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drivers/include/stm32f7xx_ll_exti.h
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ST Bug tracker ID: 55274
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See release_note.html from STM32Cube
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@ -23,7 +23,7 @@
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#define STM32_HAL_LEGACY
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#ifdef __cplusplus
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extern "C" {
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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@ -38,7 +38,6 @@
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#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
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#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
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#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
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/**
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* @}
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*/
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@ -241,7 +240,7 @@
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#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
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#endif
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#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4)
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#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
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#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
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#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
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#endif
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@ -313,8 +312,13 @@
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#endif /* STM32L4 */
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#if defined(STM32G0)
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#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
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#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
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#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
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#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
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#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
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#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
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#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
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#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
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#endif
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#if defined(STM32H7)
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@ -591,24 +595,24 @@
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#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
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#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
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#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
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#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
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#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
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#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
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#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
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#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
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#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
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#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
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#if defined(STM32L1)
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#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
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#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
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#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
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#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
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#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
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#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
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#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
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#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
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#endif /* STM32L1 */
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#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
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#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
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#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
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#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
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#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
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#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
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#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
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#endif /* STM32F0 || STM32F3 || STM32F1 */
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#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
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@ -643,6 +647,10 @@
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#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
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#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
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#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
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#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
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#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
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#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
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#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
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#endif /* STM32G4 */
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#if defined(STM32H7)
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@ -765,49 +773,6 @@
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#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
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#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
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/** @brief Constants defining the events that can be selected to configure the
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* set/reset crossbar of a timer output
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*/
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#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
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#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
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#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
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#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
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#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
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#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
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#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
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#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
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#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
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#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
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#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
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#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
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#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
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#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
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#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
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#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
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#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
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#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
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/** @brief Constants defining the event filtering applied to external events
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* by a timer
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*/
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#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
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#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
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#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
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#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
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#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
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/** @brief Constants defining the DLL calibration periods (in micro seconds)
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*/
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#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
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@ -955,11 +920,16 @@
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#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
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#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
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#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7)
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#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
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#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
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#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
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#endif
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#if defined(STM32L4) || defined(STM32L5)
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#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
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#elif defined(STM32G4)
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#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
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#endif
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/**
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* @}
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@ -971,15 +941,15 @@
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#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
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#if defined(STM32H7)
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#define I2S_IT_TXE I2S_IT_TXP
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#define I2S_IT_RXNE I2S_IT_RXP
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#define I2S_IT_TXE I2S_IT_TXP
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#define I2S_IT_RXNE I2S_IT_RXP
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#define I2S_FLAG_TXE I2S_FLAG_TXP
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#define I2S_FLAG_RXNE I2S_FLAG_RXP
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#define I2S_FLAG_TXE I2S_FLAG_TXP
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#define I2S_FLAG_RXNE I2S_FLAG_RXP
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#endif
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#if defined(STM32F7)
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#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
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#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
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#endif
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/**
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* @}
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#if defined(STM32H7)
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#define SPI_FLAG_TXE SPI_FLAG_TXP
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#define SPI_FLAG_RXNE SPI_FLAG_RXP
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#define SPI_FLAG_TXE SPI_FLAG_TXP
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#define SPI_FLAG_RXNE SPI_FLAG_RXP
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#define SPI_IT_TXE SPI_IT_TXP
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#define SPI_IT_RXNE SPI_IT_RXP
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#define SPI_IT_TXE SPI_IT_TXP
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#define SPI_IT_RXNE SPI_IT_RXP
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#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
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#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
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#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
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#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
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#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
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#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
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#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
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#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
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#endif /* STM32H7 */
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#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
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#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
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#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
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#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
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#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
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#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
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#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
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#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
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#endif /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */
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#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
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/**
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* @}
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*/
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#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
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#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
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#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
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#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
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#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
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)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
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#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
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#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
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#if defined(STM32L0)
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#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
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#endif
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#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
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#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
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#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
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)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
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#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
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#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
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#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
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#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
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#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
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/**
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/**
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* @}
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*/
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*/
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/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
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* @{
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#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
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#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
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#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
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#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
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)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
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#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
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#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
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#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
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#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
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#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
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#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
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#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
|
||||
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
|
||||
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
|
||||
#if defined(STM32F4)
|
||||
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
|
||||
|
@ -1554,19 +1527,19 @@
|
|||
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
|
||||
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
|
||||
#endif /* STM32F4 */
|
||||
/**
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32G0)
|
||||
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
|
||||
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
|
||||
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
|
||||
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
|
||||
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
|
||||
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
|
||||
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
|
||||
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
|
||||
#endif
|
||||
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
|
||||
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
|
||||
|
@ -1611,9 +1584,9 @@
|
|||
|
||||
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
|
||||
|
||||
/**
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
|
@ -1862,15 +1835,15 @@
|
|||
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
|
||||
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
|
||||
#else
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
|
||||
#endif /* STM32H7 */
|
||||
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
|
||||
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
|
||||
|
@ -2081,8 +2054,8 @@
|
|||
*/
|
||||
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
|
||||
((WAVE) == DAC_WAVE_NOISE)|| \
|
||||
((WAVE) == DAC_WAVE_TRIANGLE))
|
||||
((WAVE) == DAC_WAVE_NOISE)|| \
|
||||
((WAVE) == DAC_WAVE_TRIANGLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -2138,7 +2111,7 @@
|
|||
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
|
||||
#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -2275,7 +2248,8 @@
|
|||
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
|
||||
|
||||
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
|
||||
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
|
||||
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
|
||||
)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
|
||||
|
||||
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
|
||||
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
|
||||
|
@ -3243,9 +3217,8 @@
|
|||
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
|
||||
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
|
||||
|
||||
#if defined(STM32L4)
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
|
||||
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
|
||||
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
|
||||
#else
|
||||
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
|
||||
#endif
|
||||
|
@ -3373,7 +3346,7 @@
|
|||
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
|
||||
#else
|
||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||
#endif
|
||||
|
@ -3393,19 +3366,19 @@
|
|||
#else
|
||||
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
|
||||
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
|
||||
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
|
||||
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
|
||||
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
|
||||
#endif /* STM32F1 */
|
||||
|
||||
#define IS_ALARM IS_RTC_ALARM
|
||||
|
@ -3481,9 +3454,9 @@
|
|||
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
|
||||
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
|
||||
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
|
||||
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
|
||||
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
|
||||
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
|
||||
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
|
||||
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
|
||||
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
|
||||
/* alias CMSIS for compatibilities */
|
||||
#define SDIO_IRQn SDMMC1_IRQn
|
||||
#define SDIO_IRQHandler SDMMC1_IRQHandler
|
||||
|
@ -3589,6 +3562,13 @@
|
|||
#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
|
||||
#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
|
||||
|
||||
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
|
||||
#define USART_OVERSAMPLING_16 0x00000000U
|
||||
#define USART_OVERSAMPLING_8 USART_CR1_OVER8
|
||||
|
||||
#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
|
||||
((__SAMPLING__) == USART_OVERSAMPLING_8))
|
||||
#endif /* STM32F0 || STM32F3 || STM32F7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -3751,7 +3731,7 @@
|
|||
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7)
|
||||
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
|
||||
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
|
||||
#endif /* STM32L4 || STM32F4 || STM32F7 */
|
||||
/**
|
||||
|
|
|
@ -52,7 +52,7 @@
|
|||
* - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
|
||||
* - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
|
||||
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
|
||||
* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
|
||||
* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
@ -761,7 +761,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
|||
#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
|
||||
((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
|
||||
((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
|
||||
((__RESOLUTION__) == ADC_RESOLUTION_6B))
|
||||
((__RESOLUTION__) == ADC_RESOLUTION_6B))
|
||||
#define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
|
||||
|
@ -784,8 +784,8 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
|||
((__REGTRIG__) == ADC_SOFTWARE_START))
|
||||
#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
|
||||
((__ALIGN__) == ADC_DATAALIGN_LEFT))
|
||||
|
||||
|
||||
|
||||
|
||||
#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_15CYCLES) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_28CYCLES) || \
|
||||
|
@ -793,12 +793,12 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
|||
((__TIME__) == ADC_SAMPLETIME_84CYCLES) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_480CYCLES))
|
||||
((__TIME__) == ADC_SAMPLETIME_480CYCLES))
|
||||
#define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV) || \
|
||||
((__EOCSelection__) == ADC_EOC_SEQ_CONV) || \
|
||||
((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV))
|
||||
((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV))
|
||||
#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || \
|
||||
((__EVENT__) == ADC_OVR_EVENT))
|
||||
((__EVENT__) == ADC_OVR_EVENT))
|
||||
#define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
|
||||
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
|
||||
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
|
||||
|
@ -927,11 +927,11 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
|||
* @retval None
|
||||
*/
|
||||
#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup ADC_Private_Functions ADC Private Functions
|
||||
* @{
|
||||
|
@ -940,11 +940,11 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -255,7 +255,7 @@ typedef enum
|
|||
HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */
|
||||
HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */
|
||||
HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */
|
||||
HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up fropm Rx msg callback ID */
|
||||
HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up from Rx msg callback ID */
|
||||
HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */
|
||||
|
||||
HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */
|
||||
|
@ -295,11 +295,11 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to
|
|||
#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
|
||||
#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
|
||||
#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
|
||||
#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
|
||||
#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
|
||||
#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
|
||||
#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
|
||||
#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
|
||||
|
|
|
@ -121,7 +121,7 @@ typedef struct
|
|||
* b6 Error information
|
||||
* 0 : No Error
|
||||
* 1 : Error
|
||||
* b5 IP initilisation status
|
||||
* b5 IP initialization status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP initialized. HAL CEC Init function already called)
|
||||
* b4-b3 (not used)
|
||||
|
@ -138,7 +138,7 @@ typedef struct
|
|||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 IP initilisation status
|
||||
* b5 IP initialization status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP initialized)
|
||||
* b4-b2 (not used)
|
||||
|
|
|
@ -267,7 +267,6 @@ typedef struct
|
|||
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
|
||||
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
|
||||
|
||||
|
||||
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
|
||||
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
|
||||
|
||||
|
|
|
@ -65,6 +65,7 @@ typedef struct
|
|||
uint32_t HeaderSize; /*!< The size of header buffer in word */
|
||||
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
|
||||
uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
|
||||
uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
|
||||
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
|
||||
Vector only once and to skip configuration for consecutive processings.
|
||||
This parameter can be a value of @ref CRYP_Configuration_Skip */
|
||||
|
@ -210,6 +211,17 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
|
|||
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
|
||||
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */
|
||||
#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -18,31 +18,34 @@
|
|||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_DAC_H
|
||||
#define __STM32F7xx_HAL_DAC_H
|
||||
#ifndef STM32F7xx_HAL_DAC_H
|
||||
#define STM32F7xx_HAL_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
#if defined(DAC)
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Types DAC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
|
@ -51,16 +54,17 @@ typedef enum
|
|||
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
|
||||
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
|
||||
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
|
||||
}HAL_DAC_StateTypeDef;
|
||||
|
||||
} HAL_DAC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC handle Structure definition
|
||||
* @brief DAC handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __DAC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
{
|
||||
DAC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
|
@ -73,33 +77,37 @@ typedef struct
|
|||
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DAC Error code */
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
|
||||
void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
|
||||
void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
|
||||
void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
|
||||
|
||||
void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac);
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
|
||||
void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
|
||||
|
||||
void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
}DAC_HandleTypeDef;
|
||||
} DAC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC Configuration regular Channel structure definition
|
||||
* @brief DAC Configuration regular Channel structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
}DAC_ChannelConfTypeDef;
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
|
||||
} DAC_ChannelConfTypeDef;
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
|
@ -111,25 +119,29 @@ typedef enum
|
|||
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
|
||||
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
|
||||
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
|
||||
|
||||
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
|
||||
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
|
||||
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
|
||||
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
|
||||
HAL_DAC_MSP_INIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
|
||||
HAL_DAC_MSP_DEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
|
||||
|
||||
HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
|
||||
HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
|
||||
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
|
||||
}HAL_DAC_CallbackIDTypeDef;
|
||||
} HAL_DAC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DAC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Constants DAC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
@ -138,77 +150,87 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
|||
* @{
|
||||
*/
|
||||
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
|
||||
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
|
||||
#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_trigger_selection DAC Trigger Selection
|
||||
/** @defgroup DAC_trigger_selection DAC trigger selection
|
||||
* @{
|
||||
*/
|
||||
#define DAC_TRIGGER_NONE 0x00000000UL /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE (DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
|
||||
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer DAC Output Buffer
|
||||
/** @defgroup DAC_output_buffer DAC output buffer
|
||||
* @{
|
||||
*/
|
||||
#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U)
|
||||
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
|
||||
#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
|
||||
#define DAC_OUTPUTBUFFER_DISABLE (DAC_CR_BOFF1)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection DAC Channel Selection
|
||||
/** @defgroup DAC_Channel_selection DAC Channel selection
|
||||
* @{
|
||||
*/
|
||||
#define DAC_CHANNEL_1 ((uint32_t)0x00000000U)
|
||||
#define DAC_CHANNEL_2 ((uint32_t)0x00000010U)
|
||||
#define DAC_CHANNEL_1 0x00000000U
|
||||
|
||||
#define DAC_CHANNEL_2 0x00000010U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignment DAC Data Alignment
|
||||
/** @defgroup DAC_data_alignment DAC data alignment
|
||||
* @{
|
||||
*/
|
||||
#define DAC_ALIGN_12B_R ((uint32_t)0x00000000U)
|
||||
#define DAC_ALIGN_12B_L ((uint32_t)0x00000004U)
|
||||
#define DAC_ALIGN_8B_R ((uint32_t)0x00000008U)
|
||||
#define DAC_ALIGN_12B_R 0x00000000U
|
||||
#define DAC_ALIGN_12B_L 0x00000004U
|
||||
#define DAC_ALIGN_8B_R 0x00000008U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition DAC Flags Definition
|
||||
/** @defgroup DAC_flags_definition DAC flags definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
|
||||
#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
|
||||
#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
|
||||
|
||||
#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_IT_definition DAC IT Definition
|
||||
/** @defgroup DAC_IT_definition DAC IT definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
|
||||
#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
|
||||
#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
|
||||
|
||||
#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -218,92 +240,142 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
|||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Macros DAC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DAC handle state
|
||||
* @param __HANDLE__: specifies the DAC handle.
|
||||
/** @brief Reset DAC handle state.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_DAC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_DAC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the DAC channel
|
||||
* @param __HANDLE__: specifies the DAC handle.
|
||||
* @param __DAC_CHANNEL__: specifies the DAC channel
|
||||
/** @brief Enable the DAC channel.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __DAC_Channel__ specifies the DAC channel
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) \
|
||||
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_CHANNEL__)))
|
||||
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
|
||||
|
||||
/** @brief Disable the DAC channel
|
||||
* @param __HANDLE__: specifies the DAC handle
|
||||
* @param __DAC_CHANNEL__: specifies the DAC channel.
|
||||
/** @brief Disable the DAC channel.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __DAC_Channel__ specifies the DAC channel.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \
|
||||
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_CHANNEL__)))
|
||||
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
|
||||
|
||||
/** @brief Set DHR12R1 alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
|
||||
|
||||
|
||||
/** @brief Enable the DAC interrupt
|
||||
* @param __HANDLE__: specifies the DAC handle
|
||||
* @param __INTERRUPT__: specifies the DAC interrupt.
|
||||
/** @brief Set DHR12R2 alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
|
||||
|
||||
|
||||
/** @brief Set DHR12RD alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
|
||||
|
||||
/** @brief Enable the DAC interrupt.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __INTERRUPT__ specifies the DAC interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the DAC interrupt
|
||||
* @param __HANDLE__: specifies the DAC handle
|
||||
* @param __INTERRUPT__: specifies the DAC interrupt.
|
||||
/** @brief Disable the DAC interrupt.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __INTERRUPT__ specifies the DAC interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Checks if the specified DAC interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: DAC handle
|
||||
* @param __INTERRUPT__: DAC interrupt source to check
|
||||
/** @brief Check whether the specified DAC interrupt source is enabled or not.
|
||||
* @param __HANDLE__ DAC handle
|
||||
* @param __INTERRUPT__ DAC interrupt source to check
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
|
||||
* @retval State of interruption (SET or RESET)
|
||||
*/
|
||||
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/** @brief Get the selected DAC's flag status.
|
||||
* @param __HANDLE__: specifies the DAC handle.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
|
||||
* @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __FLAG__ specifies the DAC flag to get.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
|
||||
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the DAC's flag.
|
||||
* @param __HANDLE__: specifies the DAC handle.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
|
||||
* @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __FLAG__ specifies the DAC flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
|
||||
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include DAC HAL Extension module */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Private_Macros DAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
|
||||
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
|
||||
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2))
|
||||
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
|
||||
((ALIGN) == DAC_ALIGN_12B_L) || \
|
||||
((ALIGN) == DAC_ALIGN_8B_R))
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include DAC HAL Extended module */
|
||||
#include "stm32f7xx_hal_dac_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
@ -311,11 +383,12 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
|||
/** @addtogroup DAC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions *********************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -323,12 +396,27 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
|
|||
/** @addtogroup DAC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
|
||||
uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
|
||||
|
||||
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/* DAC callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
|
||||
pDAC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -337,8 +425,8 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
|||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -346,20 +434,10 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui
|
|||
/** @addtogroup DAC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
|
||||
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
|
||||
|
||||
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/* DAC callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -367,66 +445,13 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_D
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup DAC_Private_Constants DAC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DAC_Private_Macros DAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
|
||||
((ALIGN) == DAC_ALIGN_12B_L) || \
|
||||
((ALIGN) == DAC_ALIGN_8B_R))
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2))
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
|
||||
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
/** @brief Set DHR12R1 alignment
|
||||
* @param __ALIGNMENT__: specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__))
|
||||
|
||||
/** @brief Set DHR12R2 alignment
|
||||
* @param __ALIGNMENT__: specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))
|
||||
|
||||
/** @brief Set DHR12RD alignment
|
||||
* @param __ALIGNMENT__: specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DAC_Private_Functions DAC Private Functions
|
||||
* @{
|
||||
*/
|
||||
void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -435,6 +460,8 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_D
|
|||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DAC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -443,6 +470,7 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_D
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F7xx_HAL_DAC_H */
|
||||
|
||||
#endif /* STM32F7xx_HAL_DAC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
@ -1,8 +1,8 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dac.h
|
||||
* @file stm32f7xx_hal_dac_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DAC HAL Extension module.
|
||||
* @brief Header file of DAC HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
|
@ -18,57 +18,66 @@
|
|||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_DAC_EX_H
|
||||
#define __STM32F7xx_HAL_DAC_EX_H
|
||||
#ifndef STM32F7xx_HAL_DAC_EX_H
|
||||
#define STM32F7xx_HAL_DAC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
#if defined(DAC)
|
||||
|
||||
/** @addtogroup DACEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Exported_Constants DAC Exported Constants
|
||||
|
||||
/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
|
||||
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
|
||||
* @{
|
||||
*/
|
||||
#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000U) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
|
||||
#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -76,47 +85,25 @@
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DACEx_Exported_Functions
|
||||
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DACEx_Private_Macros DACEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Extension features functions ***********************************************/
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
|
||||
|
||||
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Private_Constants DAC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Private_Macros DAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
|
||||
|
@ -145,13 +132,32 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Private_Functions DAC Private Functions
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Extended features functions ***********************************************/
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
|
||||
|
||||
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -160,6 +166,30 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
|
||||
/* are called by HAL_DAC_Start_DMA */
|
||||
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DAC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -168,6 +198,6 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F7xx_HAL_DAC_EX_H */
|
||||
#endif /* STM32F7xx_HAL_DAC_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
@ -107,7 +107,14 @@ typedef enum
|
|||
}while (0U)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((packed))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
|
@ -118,7 +125,14 @@ typedef enum
|
|||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
|
@ -130,7 +144,7 @@ typedef enum
|
|||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler */
|
||||
#if defined (__CC_ARM) /* ARM Compiler V5*/
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
|
@ -150,9 +164,9 @@ typedef enum
|
|||
/**
|
||||
* @brief __RAM_FUNC definition
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
/* ARM Compiler
|
||||
------------
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
/* ARM Compiler V4/V5 and V6
|
||||
--------------------------
|
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
|
@ -182,9 +196,9 @@ typedef enum
|
|||
/**
|
||||
* @brief __NOINLINE definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
|
||||
/* ARM & GNUCompiler
|
||||
----------------
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
|
||||
/* ARM V4/V5 and V6 & GNU Compiler
|
||||
-------------------------------
|
||||
*/
|
||||
#define __NOINLINE __attribute__ ( (noinline) )
|
||||
|
||||
|
|
|
@ -301,8 +301,8 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
|
|||
/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */
|
||||
#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
|
||||
#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for output clock is system clock */
|
||||
#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for output clock is audio clock */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -22,11 +22,9 @@
|
|||
#define STM32F7xx_HAL_DMA2D_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (DMA2D)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
|
@ -34,6 +32,8 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
#if defined (DMA2D)
|
||||
|
||||
/** @addtogroup DMA2D DMA2D
|
||||
* @brief DMA2D HAL module driver
|
||||
* @{
|
||||
|
@ -71,9 +71,11 @@ typedef struct
|
|||
This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
|
||||
|
||||
uint32_t OutputOffset; /*!< Specifies the Offset value.
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x0000 and Max_Data = 0x3FFF. */
|
||||
#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
|
||||
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter.
|
||||
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value
|
||||
for the output pixel format converter.
|
||||
This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
|
||||
|
||||
uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
|
||||
|
@ -94,7 +96,8 @@ typedef struct
|
|||
typedef struct
|
||||
{
|
||||
uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x0000 and Max_Data = 0x3FFF. */
|
||||
|
||||
uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
|
||||
This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
|
||||
|
@ -102,9 +105,12 @@ typedef struct
|
|||
uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
|
||||
This parameter can be one value of @ref DMA2D_Alpha_Mode. */
|
||||
|
||||
uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
|
||||
@note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
|
||||
uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value
|
||||
in case of A8 or A4 color mode.
|
||||
This parameter must be a number between Min_Data = 0x00
|
||||
and Max_Data = 0xFF except for the color modes detailed below.
|
||||
@note In case of A8 or A4 color mode (ARGB),
|
||||
this parameter must be a number between
|
||||
Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
|
||||
- InputAlpha[24:31] is the alpha value ALPHA[0:7]
|
||||
- InputAlpha[16:23] is the red value RED[0:7]
|
||||
|
@ -132,46 +138,46 @@ typedef enum
|
|||
HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
|
||||
HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */
|
||||
HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */
|
||||
}HAL_DMA2D_StateTypeDef;
|
||||
} HAL_DMA2D_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA2D handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA2D_HandleTypeDef
|
||||
{
|
||||
DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
|
||||
DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
|
||||
|
||||
DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
|
||||
DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
|
||||
|
||||
void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */
|
||||
void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */
|
||||
|
||||
void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */
|
||||
void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */
|
||||
|
||||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
||||
void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */
|
||||
void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */
|
||||
|
||||
void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */
|
||||
void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */
|
||||
|
||||
void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */
|
||||
void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */
|
||||
|
||||
void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */
|
||||
void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */
|
||||
|
||||
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
|
||||
|
||||
DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
|
||||
DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA2D lock. */
|
||||
HAL_LockTypeDef Lock; /*!< DMA2D lock. */
|
||||
|
||||
__IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
|
||||
__IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA2D error code. */
|
||||
__IO uint32_t ErrorCode; /*!< DMA2D error code. */
|
||||
} DMA2D_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL DMA2D Callback pointer definition
|
||||
*/
|
||||
typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */
|
||||
typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */
|
||||
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
|
@ -242,10 +248,10 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Poin
|
|||
/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
|
||||
#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
|
||||
#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */
|
||||
#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value
|
||||
with original alpha channel value */
|
||||
with original alpha channel value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -312,7 +318,8 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Poin
|
|||
/** @defgroup DMA2D_Aliases DMA2D API Aliases
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
|
||||
#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
|
||||
for compatibility with legacy code */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -329,7 +336,7 @@ typedef enum
|
|||
HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */
|
||||
HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */
|
||||
HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */
|
||||
}HAL_DMA2D_CallbackIDTypeDef;
|
||||
} HAL_DMA2D_CallbackIDTypeDef;
|
||||
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
|
@ -346,10 +353,10 @@ typedef enum
|
|||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
}while(0)
|
||||
#else
|
||||
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
|
||||
|
@ -455,12 +462,13 @@ typedef enum
|
|||
|
||||
/* Initialization and de-initialization functions *******************************/
|
||||
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
|
||||
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
|
||||
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d);
|
||||
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d);
|
||||
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d);
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
|
||||
pDMA2D_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
|
||||
|
||||
|
@ -474,14 +482,22 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_
|
|||
*/
|
||||
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
|
||||
uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
|
||||
uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
|
||||
uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
|
||||
uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
|
||||
uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
|
||||
uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||||
|
@ -601,13 +617,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
|
|||
/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER))
|
||||
#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\
|
||||
|| ((LAYER) == DMA2D_FOREGROUND_LAYER))
|
||||
|
||||
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
|
||||
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
|
||||
|
||||
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
|
||||
((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
|
||||
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \
|
||||
((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
|
||||
((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \
|
||||
((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
|
||||
((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
|
||||
|
||||
#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
|
||||
|
@ -615,11 +634,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
|
|||
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
|
||||
#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
|
||||
|
||||
#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
|
||||
#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_RGB888) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_RGB565) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_L8) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_AL44) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_AL88) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_L4) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_A8) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_A4))
|
||||
|
||||
#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
|
||||
|
@ -641,15 +665,11 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
|
|||
#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
|
||||
#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
|
||||
#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
|
||||
((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
|
||||
((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
|
||||
((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
|
||||
((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
|
||||
#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
|
||||
((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
|
||||
((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
|
||||
((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -660,6 +680,10 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
|
|||
|
||||
#endif /* defined (DMA2D) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -25,10 +25,11 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(DSI)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
#if defined(DSI)
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
@ -347,6 +348,9 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
|||
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DSI_Exported_Constants DSI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup DSI_DCS_Command DSI DCS Command
|
||||
* @{
|
||||
*/
|
||||
|
@ -908,10 +912,18 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
|||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup DSI_Exported_Macros DSI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reset DSI handle state.
|
||||
* @param __HANDLE__: DSI handle
|
||||
* @param __HANDLE__ DSI handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
|
||||
|
@ -1101,6 +1113,10 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
|||
*/
|
||||
#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup DSI_Exported_Functions DSI Exported Functions
|
||||
* @{
|
||||
|
|
|
@ -591,7 +591,7 @@ typedef struct
|
|||
|
||||
|
||||
/**
|
||||
* @brief Received Frame Informations structure definition
|
||||
* @brief Received Frame Information structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
|
|
@ -218,21 +218,21 @@ typedef struct
|
|||
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
|
||||
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
||||
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
||||
(((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
|
||||
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
|
||||
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
||||
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
||||
(((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
|
||||
|
||||
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
|
||||
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
|
||||
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
|
||||
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
|
||||
|
||||
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
|
||||
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
|
||||
|
||||
#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \
|
||||
((__LINE__) == EXTI_TRIGGER_RISING) || \
|
||||
((__LINE__) == EXTI_TRIGGER_RISING_FALLING))
|
||||
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_FALLING) || \
|
||||
((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \
|
||||
((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING))
|
||||
|
||||
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
|
||||
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
|
||||
|
||||
#if defined (GPIOK)
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
|
|
|
@ -502,10 +502,10 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
|
||||
* @brief Calculate the FLASH Boot Base Address (BOOT_ADD0 or BOOT_ADD1)
|
||||
* @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
|
||||
* @param __ADDRESS__ FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
|
||||
* @retval The FLASH Boot Base Adress
|
||||
* @retval The FLASH Boot Base Address
|
||||
*/
|
||||
#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)
|
||||
/**
|
||||
|
|
|
@ -22,7 +22,7 @@
|
|||
#define STM32F7xx_HAL_HASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
@ -51,7 +51,7 @@ typedef struct
|
|||
|
||||
uint32_t KeySize; /*!< The key size is used only in HMAC operation. */
|
||||
|
||||
uint8_t* pKey; /*!< The key is used only in HMAC operation. */
|
||||
uint8_t *pKey; /*!< The key is used only in HMAC operation. */
|
||||
|
||||
} HASH_InitTypeDef;
|
||||
|
||||
|
@ -66,7 +66,7 @@ typedef enum
|
|||
HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
|
||||
HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */
|
||||
HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */
|
||||
}HAL_HASH_StateTypeDef;
|
||||
} HAL_HASH_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL phase structures definition
|
||||
|
@ -81,7 +81,7 @@ typedef enum
|
|||
(step 2 consists in entering the message text) */
|
||||
HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase
|
||||
(step 3 consists in entering the outer hash function key) */
|
||||
}HAL_HASH_PhaseTypeDef;
|
||||
} HAL_HASH_PhaseTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL HASH mode suspend definitions
|
||||
|
@ -90,7 +90,7 @@ typedef enum
|
|||
{
|
||||
HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */
|
||||
HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */
|
||||
}HAL_HASH_SuspendTypeDef;
|
||||
} HAL_HASH_SuspendTypeDef;
|
||||
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
|
||||
/**
|
||||
|
@ -103,7 +103,7 @@ typedef enum
|
|||
HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */
|
||||
HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */
|
||||
HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */
|
||||
}HAL_HASH_CallbackIDTypeDef;
|
||||
} HAL_HASH_CallbackIDTypeDef;
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
|
@ -155,15 +155,15 @@ typedef struct
|
|||
__IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */
|
||||
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */
|
||||
void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH input completion callback */
|
||||
|
||||
void (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH digest computation completion callback */
|
||||
void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH digest computation completion callback */
|
||||
|
||||
void (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH error callback */
|
||||
void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH error callback */
|
||||
|
||||
void (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp Init callback */
|
||||
void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */
|
||||
void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
|
||||
} HASH_HandleTypeDef;
|
||||
|
@ -172,7 +172,7 @@ typedef struct
|
|||
/**
|
||||
* @brief HAL HASH Callback pointer definition
|
||||
*/
|
||||
typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */
|
||||
typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer to a HASH common callback functions */
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
|
@ -250,7 +250,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
|
|||
/** @defgroup HASH_alias HASH API alias
|
||||
* @{
|
||||
*/
|
||||
#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
|
||||
#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -288,8 +288,8 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
|
|||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \
|
||||
((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
|
||||
((HASH->SR & (__FLAG__)) == (__FLAG__)) )
|
||||
((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
|
||||
((HASH->SR & (__FLAG__)) == (__FLAG__)) )
|
||||
|
||||
|
||||
/** @brief Clear the specified HASH flag.
|
||||
|
@ -366,7 +366,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
|
|||
* @brief Set the number of valid bits in the last word written in data register DIN.
|
||||
* @param __SIZE__ size in bytes of last data written in Data register.
|
||||
* @retval None
|
||||
*/
|
||||
*/
|
||||
#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
|
||||
|
||||
/**
|
||||
|
@ -389,8 +389,8 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
|
|||
* @retval Digest length
|
||||
*/
|
||||
#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \
|
||||
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
|
||||
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
|
||||
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
|
||||
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
|
||||
/**
|
||||
* @brief Return number of words already pushed in the FIFO.
|
||||
* @retval Number of words already pushed in the FIFO
|
||||
|
@ -424,7 +424,8 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
|
|||
* @param __SIZE__ input data buffer size.
|
||||
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
|
||||
*/
|
||||
#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
|
||||
#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET)\
|
||||
|| (((__SIZE__) % 4U) == 0U))
|
||||
/**
|
||||
* @brief Ensure that handle phase is set to HASH processing.
|
||||
* @param __HANDLE__ HASH handle.
|
||||
|
@ -467,7 +468,8 @@ void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
|
|||
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
|
||||
pHASH_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
|
@ -482,12 +484,16 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS
|
|||
|
||||
|
||||
/* HASH processing using polling *********************************************/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
|
||||
|
||||
/**
|
||||
|
@ -499,12 +505,16 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p
|
|||
*/
|
||||
|
||||
/* HASH processing using IT **************************************************/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
|
||||
/**
|
||||
* @}
|
||||
|
@ -516,9 +526,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
|
|||
|
||||
/* HASH processing using DMA *************************************************/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -529,8 +539,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu
|
|||
*/
|
||||
|
||||
/* HASH-MAC processing using polling *****************************************/
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -540,8 +552,10 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
|
|||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -567,8 +581,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
|
|||
/* Peripheral State methods **************************************************/
|
||||
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
|
||||
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
|
||||
void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
|
||||
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
|
||||
void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
|
||||
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
|
||||
|
@ -588,14 +602,18 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
|
|||
*/
|
||||
|
||||
/* Private functions */
|
||||
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
uint32_t Timeout, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
uint32_t Timeout, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
|
||||
/**
|
||||
|
|
|
@ -22,7 +22,7 @@
|
|||
#define STM32F7xx_HAL_HASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
@ -51,12 +51,16 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -66,12 +70,16 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
|
|||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -81,9 +89,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
|
|||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -92,8 +100,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
|
|||
/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -102,8 +112,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
@ -33,7 +33,7 @@ extern "C" {
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HCD
|
||||
/** @addtogroup HCD HCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
@ -112,6 +112,10 @@ typedef struct
|
|||
#define HCD_SPEED_FULL USBH_FSLS_SPEED
|
||||
#define HCD_SPEED_LOW USBH_FSLS_SPEED
|
||||
|
||||
#define HCD_DEVICE_SPEED_HIGH 0U
|
||||
#define HCD_DEVICE_SPEED_FULL 1U
|
||||
#define HCD_DEVICE_SPEED_LOW 2U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -143,9 +147,9 @@ typedef struct
|
|||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Exported_Macros HCD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
|
||||
|
@ -214,10 +218,16 @@ typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
|
|||
* @}
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID);
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
|
||||
HAL_HCD_CallbackIDTypeDef CallbackID,
|
||||
pHCD_CallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
|
||||
HAL_HCD_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
|
||||
pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
|
@ -235,6 +245,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_n
|
|||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
|
||||
|
@ -267,6 +278,7 @@ HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chn
|
|||
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
|
||||
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -277,36 +289,17 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
|
|||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Private_Macros HCD Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup HCD_Private_Functions HCD Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
|
|
@ -495,7 +495,8 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
|
|||
*
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
|
||||
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
|
@ -521,7 +522,8 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
|
|||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define I2C_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
|
||||
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
|
@ -541,7 +543,7 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
|
|||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
|
||||
: ((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
||||
: ((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
||||
|
||||
/** @brief Enable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
|
@ -583,7 +585,8 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
|||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
|
||||
pI2C_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
|
||||
|
@ -598,49 +601,70 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
|
|||
*/
|
||||
/* IO operation functions ****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
|
||||
uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
|
||||
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
|
@ -732,7 +756,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
|||
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
|
||||
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
|
||||
|
||||
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
|
||||
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
|
||||
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
|
||||
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
|
||||
|
@ -743,13 +768,15 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
|||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
||||
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
|
||||
(uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||
|
||||
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
|
||||
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
/**
|
||||
* @}
|
||||
|
|
|
@ -38,7 +38,6 @@ extern "C" {
|
|||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
@ -99,24 +98,51 @@ extern "C" {
|
|||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions
|
||||
* @{
|
||||
*/
|
||||
#if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP)
|
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
|
||||
|
@ -132,7 +158,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
|||
* @{
|
||||
*/
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == I2C_ANALOGFILTER_DISABLE))
|
||||
((FILTER) == I2C_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
|
||||
|
@ -167,9 +193,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
|||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
|
||||
#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -191,14 +214,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -89,7 +89,7 @@ typedef enum
|
|||
typedef struct __I2S_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
{
|
||||
SPI_TypeDef *Instance; /*!< I2S registers base address */
|
||||
|
||||
|
@ -176,6 +176,7 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
|
|||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -272,7 +273,8 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
|
|||
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
|
||||
#define I2S_FLAG_BSY SPI_SR_BSY
|
||||
|
||||
#define I2S_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
|
||||
#define I2S_FLAG_MASK (SPI_SR_RXNE\
|
||||
| SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -306,7 +308,7 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
|
|||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
|
||||
#endif
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified SPI peripheral (in I2S mode).
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
|
@ -352,7 +354,8 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
|
|||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified I2S flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
|
@ -374,19 +377,28 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
|
|||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
|
||||
__IO uint32_t tmpreg_ovr = 0x00U; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_ovr); \
|
||||
__IO uint32_t tmpreg_ovr = 0x00U; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_ovr); \
|
||||
}while(0U)
|
||||
/** @brief Clears the I2S UDR pending flag.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
|
||||
__IO uint32_t tmpreg_udr = 0x00U;\
|
||||
tmpreg_udr = ((__HANDLE__)->Instance->SR);\
|
||||
UNUSED(tmpreg_udr); \
|
||||
__IO uint32_t tmpreg_udr = 0x00U;\
|
||||
tmpreg_udr = ((__HANDLE__)->Instance->SR);\
|
||||
UNUSED(tmpreg_udr); \
|
||||
}while(0U)
|
||||
/** @brief Flush the I2S DR Register.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\
|
||||
__IO uint32_t tmpreg_dr = 0x00U;\
|
||||
tmpreg_dr = ((__HANDLE__)->Instance->DR);\
|
||||
UNUSED(tmpreg_dr); \
|
||||
}while(0U)
|
||||
/**
|
||||
* @}
|
||||
|
@ -408,7 +420,8 @@ void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
|
|||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
|
||||
pI2S_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
/**
|
||||
|
@ -463,21 +476,13 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
|||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2S_Private_Constants I2S Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2S_Private_Macros I2S Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __SR__ copy of I2S SR regsiter.
|
||||
* @param __SR__ copy of I2S SR register.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
||||
|
@ -488,10 +493,11 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
|||
* @arg I2S_FLAG_BSY: Busy flag
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
|
||||
#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
|
||||
& ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
||||
* @param __CR2__ copy of I2S CR2 regsiter.
|
||||
* @param __CR2__ copy of I2S CR2 register.
|
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
|
@ -499,7 +505,8 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
|||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks if I2S Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the I2S Mode.
|
||||
|
@ -527,7 +534,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
|||
|
||||
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
|
||||
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
|
||||
((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
|
||||
((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
|
||||
|
||||
/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
|
||||
* @param __CPOL__ specifies the I2S serial clock steady state.
|
||||
|
@ -535,7 +542,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
|||
* @retval None
|
||||
*/
|
||||
#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
|
||||
((__CPOL__) == I2S_CPOL_HIGH))
|
||||
((__CPOL__) == I2S_CPOL_HIGH))
|
||||
|
||||
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
|
||||
((CLOCK) == I2S_CLOCK_PLL))
|
||||
|
|
|
@ -75,7 +75,8 @@ typedef struct
|
|||
|
||||
/**
|
||||
* @brief HAL IRDA State definition
|
||||
* @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition).
|
||||
* @note HAL IRDA State value is a combination of 2 different substates:
|
||||
* gState and RxState (see @ref IRDA_State_Definition).
|
||||
* - gState contains IRDA state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
|
@ -86,7 +87,7 @@ typedef struct
|
|||
* 11 : Error
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral not initialized. HAL IRDA Init function already called)
|
||||
* 1 : Init done (Peripheral initialized. HAL IRDA Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
|
@ -103,7 +104,7 @@ typedef struct
|
|||
* xx : Should be set to 00
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
|
@ -245,7 +246,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
|
|||
Value is allowed for RxState only */
|
||||
#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState.
|
||||
Value is result of combination (Or) between gState and RxState values */
|
||||
Value is result of combination (Or) between
|
||||
gState and RxState values */
|
||||
#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
|
||||
Value is allowed for gState only */
|
||||
#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error
|
||||
|
@ -257,15 +259,15 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
|
|||
/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
|
||||
#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
|
||||
#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
|
||||
#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
|
||||
#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */
|
||||
#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */
|
||||
#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
|
||||
#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
|
||||
#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
|
||||
#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
|
||||
#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
|
@ -547,9 +549,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
|
|||
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
|
||||
((__HANDLE__)->Instance->CR1 |= (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))):\
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
|
||||
((__HANDLE__)->Instance->CR2 |= (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))):\
|
||||
((__HANDLE__)->Instance->CR3 |= (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
/** @brief Disable the specified IRDA interrupt.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
|
@ -563,10 +570,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
|
|||
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
|
||||
((__HANDLE__)->Instance->CR1 &= ~ (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
|
||||
((__HANDLE__)->Instance->CR2 &= ~ (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
/** @brief Check whether the specified IRDA interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
|
@ -582,8 +593,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
|
|||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
|
||||
& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
|
||||
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \
|
||||
((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
|
@ -597,9 +608,10 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
|
|||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
|
||||
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
|
||||
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
|
||||
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \
|
||||
& IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \
|
||||
& (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
|
|
|
@ -87,7 +87,6 @@ typedef struct
|
|||
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
|
||||
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
|
||||
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -100,7 +99,6 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -138,7 +136,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
/* Initialization/Start functions ********************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -147,7 +145,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
|||
* @{
|
||||
*/
|
||||
/* I/O operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -24,10 +24,12 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#if defined (JPEG)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
#if defined (JPEG)
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
@ -397,7 +399,7 @@ typedef void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8
|
|||
* @arg JPEG_IT_EOC : End of Conversion Interrupt
|
||||
* @arg JPEG_IT_HPD : Header Parsing Done Interrupt
|
||||
*
|
||||
* @retval No retrun
|
||||
* @retval No return
|
||||
*/
|
||||
#define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )
|
||||
|
||||
|
@ -415,7 +417,7 @@ typedef void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8
|
|||
*
|
||||
* @note To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits
|
||||
* located in the same IT enable register (CR register).
|
||||
* @retval No retrun
|
||||
* @retval No return
|
||||
*/
|
||||
#define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0UL)
|
||||
|
||||
|
@ -643,6 +645,7 @@ uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg);
|
|||
*/
|
||||
|
||||
#endif /* JPEG */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -345,10 +345,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
|||
*/
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
|
@ -484,55 +484,64 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
|||
* @retval Interrupt status.
|
||||
*/
|
||||
|
||||
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR\
|
||||
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR\
|
||||
&= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable event on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR\
|
||||
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable event on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR\
|
||||
&= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR\
|
||||
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR\
|
||||
&= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR\
|
||||
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR\
|
||||
&= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
|
||||
|
@ -547,26 +556,29 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
|||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
|
||||
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
|
||||
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.
|
||||
* @retval Line Status.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR\
|
||||
& LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Clear the LPTIM Wake-up Timer associated Exti line flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR\
|
||||
= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER\
|
||||
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -578,9 +590,9 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
|||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group1
|
||||
* @brief Initialization and Configuration functions.
|
||||
* @{
|
||||
*/
|
||||
* @brief Initialization and Configuration functions.
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
|
||||
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
|
||||
|
@ -593,9 +605,9 @@ void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
|
|||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group2
|
||||
* @brief Start-Stop operation functions.
|
||||
* @{
|
||||
*/
|
||||
* @brief Start-Stop operation functions.
|
||||
* @{
|
||||
*/
|
||||
/* Start/Stop operation functions *********************************************/
|
||||
/* ################################# PWM Mode ################################*/
|
||||
/* Blocking mode: Polling */
|
||||
|
@ -649,9 +661,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
|||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group3
|
||||
* @brief Read operation functions.
|
||||
* @{
|
||||
*/
|
||||
* @brief Read operation functions.
|
||||
* @{
|
||||
*/
|
||||
/* Reading operation functions ************************************************/
|
||||
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
|
||||
|
@ -661,9 +673,9 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
|
|||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group4
|
||||
* @brief LPTIM IRQ handler and callback functions.
|
||||
* @{
|
||||
*/
|
||||
* @brief LPTIM IRQ handler and callback functions.
|
||||
* @{
|
||||
*/
|
||||
/* LPTIM IRQ functions *******************************************************/
|
||||
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
|
@ -678,7 +690,8 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
|
|||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
|
||||
pLPTIM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
/**
|
||||
|
@ -686,9 +699,9 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_
|
|||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Group5
|
||||
* @brief Peripheral State functions.
|
||||
* @{
|
||||
*/
|
||||
* @brief Peripheral State functions.
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
|
|
|
@ -54,7 +54,7 @@ typedef enum
|
|||
HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */
|
||||
HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */
|
||||
HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */
|
||||
HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfert State */
|
||||
HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfer State */
|
||||
HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */
|
||||
}HAL_MMC_StateTypeDef;
|
||||
/**
|
||||
|
|
|
@ -88,10 +88,10 @@ typedef struct
|
|||
typedef struct
|
||||
{
|
||||
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
|
||||
for 8 bits adressing or words for 16 bits addressing */
|
||||
for 8 bits addressing or words for 16 bits addressing */
|
||||
|
||||
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
|
||||
for 8 bits adressing or words for 16 bits addressing */
|
||||
for 8 bits addressing or words for 16 bits addressing */
|
||||
|
||||
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
|
||||
|
||||
|
|
|
@ -183,9 +183,9 @@ typedef struct
|
|||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Macros PCD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
|
@ -195,12 +195,11 @@ typedef struct
|
|||
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
|
||||
|
||||
|
||||
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
|
||||
~(USB_OTG_PCGCCTL_STOPCLK)
|
||||
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
|
||||
|
||||
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
|
||||
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
|
||||
|
||||
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
|
||||
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
|
||||
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
|
@ -208,20 +207,20 @@ typedef struct
|
|||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
|
||||
do { \
|
||||
EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \
|
||||
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
|
||||
} while(0U)
|
||||
do { \
|
||||
EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \
|
||||
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
|
||||
} while(0U)
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
|
||||
do { \
|
||||
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
|
||||
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
|
||||
} while(0U)
|
||||
do { \
|
||||
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
|
||||
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
|
||||
} while(0U)
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
|
||||
|
@ -282,22 +281,36 @@ typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgType
|
|||
* @}
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
|
||||
HAL_PCD_CallbackIDTypeDef CallbackID,
|
||||
pPCD_CallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
|
||||
HAL_PCD_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_DataOutStageCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_DataInStageCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_IsoOutIncpltCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_IsoInIncpltCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_LpmCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
|
@ -312,6 +325,7 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
|
|||
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
@ -336,16 +350,24 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
|||
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint16_t ep_mps, uint8_t ep_type);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint8_t *pBuf, uint32_t len);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint8_t *pBuf, uint32_t len);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -411,8 +433,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup PCD_Private_Macros PCD Private Macros
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
@ -66,7 +66,7 @@
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
|
||||
* @{
|
||||
*/
|
||||
|
@ -85,7 +85,7 @@
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWREx_Wakeup_Pins_Flag PWREx Wake Up Pin Flags
|
||||
* @{
|
||||
*/
|
||||
|
@ -145,7 +145,7 @@
|
|||
|
||||
/** @brief Clear the Under-Drive Ready flag.
|
||||
*/
|
||||
#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY)
|
||||
#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= (PWR_FLAG_UDRDY | PWR_CSR1_EIWUP))
|
||||
|
||||
/** @brief Check Wake Up flag is set or not.
|
||||
* @param __WUFLAG__ specifies the Wake Up flag to check.
|
||||
|
|
|
@ -74,7 +74,7 @@ typedef struct
|
|||
}RCC_OscInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RCC System, AHB and APB busses clock configuration structure definition
|
||||
* @brief RCC System, AHB and APB buses clock configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
|
|
@ -106,12 +106,11 @@ typedef struct
|
|||
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
|
||||
This parameter can be a value of @ref RTC_AM_PM_Definitions */
|
||||
|
||||
uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
|
||||
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
|
||||
uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time,
|
||||
please use HAL_RTC_DST_xxx functions */
|
||||
|
||||
uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BKP bit
|
||||
in CR register to store the operation.
|
||||
This parameter can be a value of @ref RTC_StoreOperation_Definitions */
|
||||
uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time,
|
||||
please use HAL_RTC_DST_xxx functions */
|
||||
}RTC_TimeTypeDef;
|
||||
|
||||
/**
|
||||
|
@ -693,6 +692,11 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
|
|||
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -22,7 +22,7 @@
|
|||
#define __STM32F7xx_HAL_SAI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
|
@ -52,7 +52,7 @@ typedef enum
|
|||
HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */
|
||||
HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
|
||||
HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */
|
||||
}HAL_SAI_StateTypeDef;
|
||||
} HAL_SAI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SAI Callback prototype
|
||||
|
@ -125,13 +125,14 @@ typedef struct
|
|||
|
||||
uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
|
||||
This parameter can be a value of @ref SAI_Block_Clock_Strobing */
|
||||
}SAI_InitTypeDef;
|
||||
} SAI_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
|
||||
* @brief SAI Frame Init structure definition
|
||||
* @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware).
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
|
@ -157,13 +158,15 @@ typedef struct
|
|||
uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset.
|
||||
This parameter can be a value of @ref SAI_Block_FS_Offset */
|
||||
|
||||
}SAI_FrameInitTypeDef;
|
||||
} SAI_FrameInitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
|
||||
* @brief SAI Block Slot Init Structure definition
|
||||
* @note For SPDIF protocol, these parameters are not used (set by hardware).
|
||||
* @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware).
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
|
@ -179,7 +182,7 @@ typedef struct
|
|||
|
||||
uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated.
|
||||
This parameter can be a value of @ref SAI_Block_Slot_Active */
|
||||
}SAI_SlotInitTypeDef;
|
||||
} SAI_SlotInitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -227,7 +230,7 @@ typedef struct __SAI_HandleTypeDef
|
|||
void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */
|
||||
void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */
|
||||
#endif
|
||||
}SAI_HandleTypeDef;
|
||||
} SAI_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -657,9 +660,9 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
|
|||
#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
|
||||
#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SAI_Exported_Functions
|
||||
|
@ -672,7 +675,7 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
|
||||
HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
|
||||
HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
|
||||
HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
|
||||
|
||||
|
|
|
@ -55,7 +55,7 @@ typedef enum
|
|||
HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */
|
||||
HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */
|
||||
HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receiving State */
|
||||
HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfert State */
|
||||
HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfer State */
|
||||
HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */
|
||||
}HAL_SD_StateTypeDef;
|
||||
/**
|
||||
|
|
|
@ -52,7 +52,8 @@ typedef struct
|
|||
where usart_ker_ckpres is the USART input clock divided by a prescaler */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
|
||||
This parameter @ref SMARTCARD_Word_Length can only be
|
||||
set to 9 (8 data + 1 parity bits). */
|
||||
|
||||
uint32_t StopBits; /*!< Specifies the number of stop bits.
|
||||
This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
|
||||
|
@ -76,13 +77,14 @@ typedef struct
|
|||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref SMARTCARD_Last_Bit */
|
||||
|
||||
uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
|
||||
Selecting the single sample method increases the receiver tolerance to clock
|
||||
deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
|
||||
uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote
|
||||
is selected. Selecting the single sample method increases
|
||||
the receiver tolerance to clock deviations. This parameter can be a value
|
||||
of @ref SMARTCARD_OneBit_Sampling. */
|
||||
|
||||
uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler.
|
||||
This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied
|
||||
by 2 to give the division factor of the source clock frequency */
|
||||
This parameter can be any value from 0x01 to 0x1F. Prescaler value is
|
||||
multiplied by 2 to give the division factor of the source clock frequency */
|
||||
|
||||
uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */
|
||||
|
||||
|
@ -108,7 +110,7 @@ typedef struct
|
|||
} SMARTCARD_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SMARTCARD advanced features initalization structure definition
|
||||
* @brief SMARTCARD advanced features initialization structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
@ -138,14 +140,16 @@ typedef struct
|
|||
uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
|
||||
This parameter can be a value of @ref SMARTCARD_MSB_First */
|
||||
|
||||
uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
|
||||
relevant flag is available) or once guard time period has elapsed.
|
||||
This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */
|
||||
uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
|
||||
relevant flag is available) or once guard time period has elapsed.
|
||||
This parameter can be a value
|
||||
of @ref SMARTCARDEx_Transmission_Completion_Indication. */
|
||||
} SMARTCARD_AdvFeatureInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SMARTCARD State definition
|
||||
* @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition).
|
||||
* @note HAL SMARTCARD State value is a combination of 2 different substates:
|
||||
* gState and RxState (see @ref SMARTCARD_State_Definition).
|
||||
* - gState contains SMARTCARD state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
|
@ -156,7 +160,7 @@ typedef struct
|
|||
* 11 : Error
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called)
|
||||
* 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
|
@ -173,7 +177,7 @@ typedef struct
|
|||
* xx : Should be set to 00
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
|
@ -218,12 +222,14 @@ typedef struct __SMARTCARD_HandleTypeDef
|
|||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
|
||||
__IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global
|
||||
Handle management and also related to Tx operations.
|
||||
This parameter can be a value
|
||||
of @ref HAL_SMARTCARD_StateTypeDef */
|
||||
|
||||
__IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
|
||||
This parameter can be a value
|
||||
of @ref HAL_SMARTCARD_StateTypeDef */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< SmartCard Error code */
|
||||
|
||||
|
@ -297,23 +303,26 @@ typedef enum
|
|||
/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value
|
||||
is allowed for gState and RxState */
|
||||
#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for
|
||||
use. Value is allowed for gState
|
||||
and RxState */
|
||||
#define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
Value is allowed for gState only */
|
||||
#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
Value is allowed for gState only */
|
||||
#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState.
|
||||
Value is result of combination (Or) between gState and RxState values */
|
||||
#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception
|
||||
process is ongoing Not to be used for
|
||||
neither gState nor RxState.
|
||||
Value is result of combination (Or)
|
||||
between gState and RxState values */
|
||||
#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
|
||||
Value is allowed for gState only */
|
||||
Value is allowed for gState only */
|
||||
#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error
|
||||
Value is allowed for gState only */
|
||||
Value is allowed for gState only */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -321,15 +330,15 @@ typedef enum
|
|||
/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
|
||||
#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
|
||||
#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
|
||||
#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
|
||||
#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */
|
||||
#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */
|
||||
#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */
|
||||
#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */
|
||||
#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */
|
||||
#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */
|
||||
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
|
||||
#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
|
@ -622,16 +631,24 @@ typedef enum
|
|||
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
|
||||
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
|
||||
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
|
||||
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
|
||||
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before
|
||||
* guard time interrupt (when interruption available)
|
||||
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
|
||||
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
|
||||
* @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
|
||||
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
|
||||
SMARTCARD_CR_POS) == 1U)?\
|
||||
((__HANDLE__)->Instance->CR1 |= (1UL <<\
|
||||
((__INTERRUPT__) & SMARTCARD_IT_MASK))):\
|
||||
((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
|
||||
SMARTCARD_CR_POS) == 2U)?\
|
||||
((__HANDLE__)->Instance->CR2 |= (1UL <<\
|
||||
((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= (1UL <<\
|
||||
((__INTERRUPT__) & SMARTCARD_IT_MASK))))
|
||||
|
||||
/** @brief Disable the specified SmartCard interrupt.
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
|
@ -641,16 +658,24 @@ typedef enum
|
|||
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
|
||||
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
|
||||
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
|
||||
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
|
||||
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard
|
||||
* time interrupt (when interruption available)
|
||||
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
|
||||
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
|
||||
* @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
|
||||
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
|
||||
SMARTCARD_CR_POS) == 1U)?\
|
||||
((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
|
||||
((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
|
||||
SMARTCARD_CR_POS) == 2U)?\
|
||||
((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
|
||||
((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
|
||||
((__INTERRUPT__) & SMARTCARD_IT_MASK))))
|
||||
|
||||
/** @brief Check whether the specified SmartCard interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
|
@ -660,15 +685,18 @@ typedef enum
|
|||
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
|
||||
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
|
||||
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
|
||||
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
|
||||
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time
|
||||
* interrupt (when interruption available)
|
||||
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
|
||||
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
|
||||
* @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
|
||||
& ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
|
||||
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\
|
||||
(((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\
|
||||
& SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\
|
||||
? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
|
@ -678,16 +706,24 @@ typedef enum
|
|||
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
|
||||
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
|
||||
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
|
||||
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
|
||||
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time
|
||||
* interrupt (when interruption available)
|
||||
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
|
||||
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
|
||||
* @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
|
||||
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
|
||||
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
|
||||
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
|
||||
SMARTCARD_CR_POS) == 0x01U)?\
|
||||
(__HANDLE__)->Instance->CR1 : \
|
||||
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
|
||||
SMARTCARD_CR_POS) == 0x02U)?\
|
||||
(__HANDLE__)->Instance->CR2 : \
|
||||
(__HANDLE__)->Instance->CR3)) &\
|
||||
(0x01UL << (((uint16_t)(__INTERRUPT__))\
|
||||
& SMARTCARD_IT_MASK))) != 0U)\
|
||||
? SET : RESET)
|
||||
|
||||
/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
|
@ -1038,7 +1074,8 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
|
|||
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
|
||||
HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
|
||||
HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
|
||||
pSMARTCARD_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
|
||||
HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
|
||||
|
|
|
@ -65,7 +65,7 @@ typedef struct
|
|||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
|
||||
This parameter can be a value of @ref SMBUS_own_address2_masks. */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
|
@ -132,7 +132,11 @@ typedef struct
|
|||
* @brief SMBUS handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __SMBUS_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
|
||||
|
||||
|
@ -326,6 +330,7 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
|||
#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
|
||||
#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
|
||||
#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
|
||||
#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
|
||||
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
|
||||
#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
|
||||
|
||||
|
@ -353,7 +358,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
|||
#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define SMBUS_IT_RXI I2C_CR1_RXIE
|
||||
#define SMBUS_IT_TXI I2C_CR1_TXIE
|
||||
#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
|
||||
#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | \
|
||||
SMBUS_IT_TXI)
|
||||
#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
|
||||
#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
|
||||
#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
|
||||
|
@ -403,10 +409,10 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
|||
*/
|
||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
(__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
|
||||
#endif
|
||||
|
@ -457,7 +463,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
|||
*
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SMBUS flag is set or not.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
|
@ -483,7 +490,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
|||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define SMBUS_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
|
||||
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
(((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
|
@ -534,15 +542,15 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
|||
*/
|
||||
|
||||
#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
|
||||
((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
|
||||
#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
|
||||
((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
|
||||
|
||||
#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
|
||||
((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
|
||||
|
||||
#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
|
||||
((MASK) == SMBUS_OA2_MASK01) || \
|
||||
|
@ -560,46 +568,49 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
|||
((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
|
||||
|
||||
#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
|
||||
((PEC) == SMBUS_PEC_ENABLE))
|
||||
((PEC) == SMBUS_PEC_ENABLE))
|
||||
|
||||
#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
|
||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
|
||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
|
||||
#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
|
||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
|
||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
|
||||
|
||||
#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
|
||||
((MODE) == SMBUS_AUTOEND_MODE) || \
|
||||
((MODE) == SMBUS_SOFTEND_MODE) || \
|
||||
((MODE) == SMBUS_SENDPEC_MODE) || \
|
||||
((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
|
||||
#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
|
||||
((MODE) == SMBUS_AUTOEND_MODE) || \
|
||||
((MODE) == SMBUS_SOFTEND_MODE) || \
|
||||
((MODE) == SMBUS_SENDPEC_MODE) || \
|
||||
((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
|
||||
|
||||
|
||||
#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
|
||||
((REQUEST) == SMBUS_GENERATE_START_READ) || \
|
||||
((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == SMBUS_NO_STARTSTOP))
|
||||
((REQUEST) == SMBUS_GENERATE_START_READ) || \
|
||||
((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == SMBUS_NO_STARTSTOP))
|
||||
|
||||
|
||||
#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
|
||||
((REQUEST) == SMBUS_FIRST_FRAME) || \
|
||||
((REQUEST) == SMBUS_NEXT_FRAME) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
|
||||
((REQUEST) == SMBUS_FIRST_FRAME) || \
|
||||
((REQUEST) == SMBUS_NEXT_FRAME) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
|
||||
|
||||
#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
|
||||
|
||||
#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
|
||||
#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
|
||||
#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
|
||||
(uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
|
||||
#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
|
||||
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
|
||||
|
||||
#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
|
||||
#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
|
||||
|
@ -607,7 +618,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
|||
#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
|
||||
#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
|
||||
|
||||
#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
|
||||
#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
|
||||
((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
|
||||
#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
|
||||
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
|
@ -623,8 +635,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
|||
*/
|
||||
|
||||
/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
@ -636,7 +648,8 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin
|
|||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID,
|
||||
pSMBUS_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback);
|
||||
|
@ -647,28 +660,33 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
|
|||
*/
|
||||
|
||||
/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/** @addtogroup Blocking_mode_Polling Blocking mode Polling
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
|
||||
uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
|
||||
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
@ -679,8 +697,8 @@ HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
|
|||
*/
|
||||
|
||||
/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
|
||||
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
@ -697,8 +715,8 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
|
|||
*/
|
||||
|
||||
/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State and Errors functions **************************************************/
|
||||
uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
|
|
@ -383,7 +383,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
|
||||
#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
|
||||
#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
|
||||
#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)
|
||||
#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
|
||||
| SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -433,7 +434,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
} while(0)
|
||||
#else
|
||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
|
||||
#endif
|
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified SPI interrupts.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
|
@ -469,7 +470,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
|
@ -529,9 +531,9 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
*/
|
||||
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_fre = 0x00U; \
|
||||
tmpreg_fre = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_fre); \
|
||||
__IO uint32_t tmpreg_fre = 0x00U; \
|
||||
tmpreg_fre = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_fre); \
|
||||
}while(0U)
|
||||
|
||||
/** @brief Enable the SPI peripheral.
|
||||
|
@ -580,7 +582,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __SR__ copy of SPI SR regsiter.
|
||||
* @param __SR__ copy of SPI SR register.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
|
||||
|
@ -594,10 +596,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
* @arg SPI_FLAG_FRLVL: SPI fifo reception level
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
|
||||
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
|
||||
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
||||
* @param __CR2__ copy of SPI CR2 regsiter.
|
||||
* @param __CR2__ copy of SPI CR2 register.
|
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
|
@ -605,15 +608,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
|
||||
(__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks if SPI Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI Mode.
|
||||
* This parameter can be a value of @ref SPI_Mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
|
||||
((__MODE__) == SPI_MODE_MASTER))
|
||||
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
|
||||
((__MODE__) == SPI_MODE_MASTER))
|
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI Direction Mode.
|
||||
|
@ -661,33 +665,33 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
* This parameter can be a value of @ref SPI_Clock_Polarity
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
|
||||
((__CPOL__) == SPI_POLARITY_HIGH))
|
||||
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
|
||||
((__CPOL__) == SPI_POLARITY_HIGH))
|
||||
|
||||
/** @brief Checks if SPI Clock Phase parameter is in allowed range.
|
||||
* @param __CPHA__ specifies the SPI Clock Phase.
|
||||
* This parameter can be a value of @ref SPI_Clock_Phase
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
|
||||
((__CPHA__) == SPI_PHASE_2EDGE))
|
||||
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
|
||||
((__CPHA__) == SPI_PHASE_2EDGE))
|
||||
|
||||
/** @brief Checks if SPI Slave Select parameter is in allowed range.
|
||||
* @param __NSS__ specifies the SPI Slave Select management parameter.
|
||||
* This parameter can be a value of @ref SPI_Slave_Select_management
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_INPUT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_OUTPUT))
|
||||
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_INPUT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_OUTPUT))
|
||||
|
||||
/** @brief Checks if SPI NSS Pulse parameter is in allowed range.
|
||||
* @param __NSSP__ specifies the SPI NSS Pulse Mode parameter.
|
||||
* This parameter can be a value of @ref SPI_NSSP_Mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
|
||||
((__NSSP__) == SPI_NSS_PULSE_DISABLE))
|
||||
#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
|
||||
((__NSSP__) == SPI_NSS_PULSE_DISABLE))
|
||||
|
||||
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
|
||||
* @param __PRESCALER__ specifies the SPI Baudrate prescaler.
|
||||
|
@ -708,16 +712,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
* This parameter can be a value of @ref SPI_MSB_LSB_transmission
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
|
||||
((__BIT__) == SPI_FIRSTBIT_LSB))
|
||||
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
|
||||
((__BIT__) == SPI_FIRSTBIT_LSB))
|
||||
|
||||
/** @brief Checks if SPI TI mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI TI mode.
|
||||
* This parameter can be a value of @ref SPI_TI_mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
|
||||
((__MODE__) == SPI_TIMODE_ENABLE))
|
||||
#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
|
||||
((__MODE__) == SPI_TIMODE_ENABLE))
|
||||
|
||||
/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
|
||||
* @param __CALCULATION__ specifies the SPI CRC calculation enable state.
|
||||
|
@ -732,8 +736,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
* This parameter can be a value of @ref SPI_CRC_length
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\
|
||||
((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \
|
||||
#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \
|
||||
((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \
|
||||
((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
|
||||
|
||||
/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
|
||||
|
@ -741,7 +745,9 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))
|
||||
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
|
||||
((__POLYNOMIAL__) <= 0xFFFFU) && \
|
||||
(((__POLYNOMIAL__)&0x1U) != 0U))
|
||||
|
||||
/** @brief Checks if DMA handle is valid.
|
||||
* @param __HANDLE__ specifies a DMA Handle.
|
||||
|
|
|
@ -60,7 +60,7 @@ typedef enum
|
|||
typedef struct __SRAM_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
|
||||
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
|
||||
{
|
||||
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
|
|
|
@ -304,6 +304,26 @@ typedef enum
|
|||
HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
|
||||
} HAL_TIM_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Channel States definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
|
||||
HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
|
||||
HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
|
||||
} HAL_TIM_ChannelStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA Burst States definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
|
||||
HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
|
||||
HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
|
||||
} HAL_TIM_DMABurstStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Active channel structures definition
|
||||
*/
|
||||
|
@ -327,13 +347,16 @@ typedef struct __TIM_HandleTypeDef
|
|||
typedef struct
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
{
|
||||
TIM_TypeDef *Instance; /*!< Register base address */
|
||||
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
|
||||
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
|
||||
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
|
||||
This array is accessed by a @ref DMA_Handle_index */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
|
||||
TIM_TypeDef *Instance; /*!< Register base address */
|
||||
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
|
||||
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
|
||||
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
|
||||
This array is accessed by a @ref DMA_Handle_index */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
|
||||
__IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */
|
||||
__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
|
||||
__IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
|
||||
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
|
||||
|
@ -373,35 +396,35 @@ typedef struct
|
|||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
|
||||
,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
|
||||
,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
|
||||
,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
|
||||
,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
|
||||
,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
|
||||
,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
|
||||
,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
|
||||
,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
|
||||
,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
|
||||
,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
|
||||
,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
|
||||
,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
|
||||
,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
|
||||
,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
|
||||
,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
|
||||
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
|
||||
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
|
||||
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
|
||||
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
|
||||
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
|
||||
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
|
||||
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
|
||||
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
|
||||
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
|
||||
|
||||
,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
|
||||
,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
|
||||
,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
|
||||
,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
|
||||
,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
|
||||
,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
|
||||
,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
|
||||
,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
|
||||
,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
|
||||
,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
|
||||
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
|
||||
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
|
||||
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
|
||||
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
|
||||
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
|
||||
, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
|
||||
, HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
|
||||
, HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
|
||||
} HAL_TIM_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
|
@ -1028,24 +1051,24 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
|||
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
|
||||
* @{
|
||||
*/
|
||||
#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -1101,25 +1124,49 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
|||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
|
||||
(__HANDLE__)->Base_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
|
||||
(__HANDLE__)->Base_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
|
||||
} while(0)
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
|
@ -1946,15 +1993,15 @@ mode.
|
|||
#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
|
||||
((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
|
||||
|
||||
#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
|
||||
#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
|
||||
|
@ -1965,6 +2012,8 @@ mode.
|
|||
((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
|
||||
|
||||
#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
|
||||
|
||||
#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
|
||||
|
||||
#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
|
||||
|
@ -2001,6 +2050,50 @@ mode.
|
|||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
|
||||
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
|
||||
|
||||
#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
|
||||
(__HANDLE__)->ChannelState[5])
|
||||
|
||||
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
|
||||
((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
|
||||
|
||||
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
|
||||
(__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \
|
||||
} while(0)
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
|
||||
(__HANDLE__)->ChannelNState[3])
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
|
||||
((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
|
||||
(__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -2172,9 +2265,15 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC
|
|||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
|
||||
uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
|
||||
uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
|
||||
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
|
||||
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
@ -2220,6 +2319,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
|
|||
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
|
||||
|
||||
/* Peripheral Channel state functions ************************************************/
|
||||
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -2239,7 +2343,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
|
|||
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
|
||||
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
|
||||
|
||||
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
|
||||
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
|
||||
void TIM_DMAError(DMA_HandleTypeDef *hdma);
|
||||
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
|
||||
|
|
|
@ -119,8 +119,8 @@ TIMEx_BreakInputConfigTypeDef;
|
|||
/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin */
|
||||
#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
|
||||
#define TIM_BREAKINPUTSOURCE_BKIN (0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin */
|
||||
#define TIM_BREAKINPUTSOURCE_DFSDM1 (0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -323,6 +323,7 @@ void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
|
|||
*/
|
||||
/* Extended Peripheral State functions ***************************************/
|
||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -46,42 +46,45 @@ extern "C" {
|
|||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
|
||||
The baud rate register is computed using the following formula:
|
||||
- If oversampling is 16 or in LIN mode,
|
||||
Baud Rate Register = ((uart_ker_ck) / ((huart->Init.BaudRate)))
|
||||
- If oversampling is 8,
|
||||
Baud Rate Register[15:4] = ((2 * uart_ker_ck) / ((huart->Init.BaudRate)))[15:4]
|
||||
Baud Rate Register[3] = 0
|
||||
Baud Rate Register[2:0] = (((2 * uart_ker_ck) / ((huart->Init.BaudRate)))[3:0]) >> 1
|
||||
where uart_ker_ck is the UART input clock */
|
||||
uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
|
||||
The baud rate register is computed using the following formula:
|
||||
- If oversampling is 16 or in LIN mode,
|
||||
Baud Rate Register = ((uart_ker_ck) / ((huart->Init.BaudRate)))
|
||||
- If oversampling is 8,
|
||||
Baud Rate Register[15:4] = ((2 * uart_ker_ck) /
|
||||
((huart->Init.BaudRate)))[15:4]
|
||||
Baud Rate Register[3] = 0
|
||||
Baud Rate Register[2:0] = (((2 * uart_ker_ck) /
|
||||
((huart->Init.BaudRate)))[3:0]) >> 1
|
||||
where uart_ker_ck is the UART input clock */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref UARTEx_Word_Length. */
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref UARTEx_Word_Length. */
|
||||
|
||||
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref UART_Stop_Bits. */
|
||||
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref UART_Stop_Bits. */
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref UART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref UART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref UART_Mode. */
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref UART_Mode. */
|
||||
|
||||
uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
|
||||
or disabled.
|
||||
This parameter can be a value of @ref UART_Hardware_Flow_Control. */
|
||||
uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
|
||||
or disabled.
|
||||
This parameter can be a value of @ref UART_Hardware_Flow_Control. */
|
||||
|
||||
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
|
||||
This parameter can be a value of @ref UART_Over_Sampling. */
|
||||
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled,
|
||||
to achieve higher speed (up to f_PCLK/8).
|
||||
This parameter can be a value of @ref UART_Over_Sampling. */
|
||||
|
||||
uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
|
||||
Selecting the single sample method increases the receiver tolerance to clock
|
||||
deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
|
||||
uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
|
||||
Selecting the single sample method increases the receiver tolerance to clock
|
||||
deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
|
||||
|
||||
|
||||
} UART_InitTypeDef;
|
||||
|
@ -93,7 +96,8 @@ typedef struct
|
|||
{
|
||||
uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
|
||||
Advanced Features may be initialized at the same time .
|
||||
This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
|
||||
This parameter can be a value of
|
||||
@ref UART_Advanced_Features_Initialization_Type. */
|
||||
|
||||
uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
|
||||
This parameter can be a value of @ref UART_Tx_Inv. */
|
||||
|
@ -127,7 +131,8 @@ typedef struct
|
|||
|
||||
/**
|
||||
* @brief HAL UART State definition
|
||||
* @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).
|
||||
* @note HAL UART State value is a combination of 2 different substates:
|
||||
* gState and RxState (see @ref UART_State_Definition).
|
||||
* - gState contains UART state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
|
@ -138,7 +143,7 @@ typedef struct
|
|||
* 11 : Error
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral not initialized. HAL UART Init function already called)
|
||||
* 1 : Init done (Peripheral initialized. HAL UART Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
|
@ -155,7 +160,7 @@ typedef struct
|
|||
* xx : Should be set to 00
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
|
@ -179,6 +184,17 @@ typedef enum
|
|||
UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
|
||||
} UART_ClockSourceTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL UART Reception type definition
|
||||
* @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
|
||||
* It is expected to admit following values :
|
||||
* HAL_UART_RECEPTION_STANDARD = 0x00U,
|
||||
* HAL_UART_RECEPTION_TOIDLE = 0x01U,
|
||||
* HAL_UART_RECEPTION_TORTO = 0x02U,
|
||||
* HAL_UART_RECEPTION_TOCHARMATCH = 0x03U,
|
||||
*/
|
||||
typedef uint32_t HAL_UART_RxTypeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief UART handle Structure definition
|
||||
*/
|
||||
|
@ -204,6 +220,8 @@ typedef struct __UART_HandleTypeDef
|
|||
|
||||
uint16_t Mask; /*!< UART Rx RDR register mask */
|
||||
|
||||
__IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
|
||||
|
||||
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
|
||||
|
||||
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
|
||||
|
@ -215,11 +233,11 @@ typedef struct __UART_HandleTypeDef
|
|||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_UART_StateTypeDef */
|
||||
and also related to Tx operations. This parameter
|
||||
can be a value of @ref HAL_UART_StateTypeDef */
|
||||
|
||||
__IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_UART_StateTypeDef */
|
||||
__IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This
|
||||
parameter can be a value of @ref HAL_UART_StateTypeDef */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< UART Error code */
|
||||
|
||||
|
@ -232,7 +250,12 @@ typedef struct __UART_HandleTypeDef
|
|||
void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */
|
||||
void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
|
||||
void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
|
||||
#endif /* USART_CR3_WUFIE */
|
||||
#endif /* USART_CR1_UESM */
|
||||
void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */
|
||||
|
||||
void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
|
||||
|
@ -264,7 +287,9 @@ typedef enum
|
|||
/**
|
||||
* @brief HAL UART Callback pointer definition
|
||||
*/
|
||||
typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
|
||||
typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
|
||||
typedef void (*pUART_RxEventCallbackTypeDef)
|
||||
(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
|
||||
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
|
||||
|
@ -291,8 +316,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState.
|
||||
Value is result of combination (Or) between gState and RxState values */
|
||||
Not to be used for neither gState nor RxState.Value is result
|
||||
of combination (Or) between gState and RxState values */
|
||||
#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
|
||||
Value is allowed for gState only */
|
||||
#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error
|
||||
|
@ -304,16 +329,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
/** @defgroup UART_Error_Definition UART Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
|
||||
#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
|
||||
#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
|
||||
#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
|
||||
#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */
|
||||
#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */
|
||||
#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */
|
||||
#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */
|
||||
#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */
|
||||
#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */
|
||||
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
|
||||
#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
|
@ -391,10 +416,14 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
|
||||
* @{
|
||||
*/
|
||||
#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */
|
||||
#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */
|
||||
#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */
|
||||
#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */
|
||||
#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection
|
||||
on start bit */
|
||||
#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection
|
||||
on falling edge */
|
||||
#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection
|
||||
on 0x7F frame detection */
|
||||
#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection
|
||||
on 0x55 frame detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -556,8 +585,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
/** @defgroup UART_MSB_First UART Advanced Feature MSB First
|
||||
* @{
|
||||
*/
|
||||
#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */
|
||||
#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */
|
||||
#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received
|
||||
first disable */
|
||||
#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received
|
||||
first enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -585,7 +616,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
|
||||
* @{
|
||||
*/
|
||||
#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */
|
||||
#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -594,9 +625,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
|
||||
* @{
|
||||
*/
|
||||
#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */
|
||||
#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */
|
||||
#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */
|
||||
#if defined(USART_CR3_WUS)
|
||||
#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */
|
||||
#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */
|
||||
#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register
|
||||
not empty or RXFIFO is not empty */
|
||||
#else
|
||||
#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */
|
||||
#define UART_WAKEUP_ON_READDATA_NONEMPTY 0x00000001U /*!< UART wake-up on receive data register
|
||||
not empty or RXFIFO is not empty */
|
||||
#endif /* USART_CR3_WUS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -614,7 +652,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
|
||||
* @{
|
||||
*/
|
||||
#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */
|
||||
#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB
|
||||
position in CR1 register */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -622,7 +661,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
|
||||
* @{
|
||||
*/
|
||||
#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
|
||||
#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB
|
||||
position in CR1 register */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -653,7 +693,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
#endif /* USART_ISR_REACK */
|
||||
#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */
|
||||
#endif /* USART_CR3_WUFIE */
|
||||
#endif /* USART_CR1_UESM */
|
||||
#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */
|
||||
#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */
|
||||
|
@ -695,24 +737,26 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
* - ZZZZ : Flag position in the ISR register(4bits)
|
||||
* @{
|
||||
*/
|
||||
#define UART_IT_PE 0x0028U /*!< UART parity error interruption */
|
||||
#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */
|
||||
#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */
|
||||
#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */
|
||||
#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */
|
||||
#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */
|
||||
#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */
|
||||
#define UART_IT_CM 0x112EU /*!< UART character match interruption */
|
||||
#define UART_IT_PE 0x0028U /*!< UART parity error interruption */
|
||||
#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */
|
||||
#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */
|
||||
#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */
|
||||
#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */
|
||||
#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */
|
||||
#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */
|
||||
#define UART_IT_CM 0x112EU /*!< UART character match interruption */
|
||||
#if defined(USART_CR1_UESM)
|
||||
#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */
|
||||
#endif /* USART_CR3_WUFIE */
|
||||
#endif /* USART_CR1_UESM */
|
||||
#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */
|
||||
#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */
|
||||
|
||||
#define UART_IT_ERR 0x0060U /*!< UART error interruption */
|
||||
#define UART_IT_ERR 0x0060U /*!< UART error interruption */
|
||||
|
||||
#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */
|
||||
#define UART_IT_NE 0x0200U /*!< UART noise error interruption */
|
||||
#define UART_IT_FE 0x0100U /*!< UART frame error interruption */
|
||||
#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */
|
||||
#define UART_IT_NE 0x0200U /*!< UART noise error interruption */
|
||||
#define UART_IT_FE 0x0100U /*!< UART frame error interruption */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -730,13 +774,25 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
|
||||
#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */
|
||||
#endif /* USART_CR3_WUFIE */
|
||||
#endif /* USART_CR1_UESM */
|
||||
#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
|
||||
* @{
|
||||
*/
|
||||
#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
|
||||
#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */
|
||||
#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */
|
||||
#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -790,7 +846,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
* @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
|
||||
* @arg @ref UART_CLEAR_CMF Character Match Clear Flag
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
* @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
|
||||
#endif
|
||||
#endif
|
||||
* @retval None
|
||||
*/
|
||||
|
@ -835,9 +893,11 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
* @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
|
||||
#endif
|
||||
* @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
* @arg @ref UART_FLAG_WUF Wake up from stop mode flag
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
* @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode)
|
||||
* @arg @ref UART_FLAG_SBKF Send Break flag
|
||||
* @arg @ref UART_FLAG_CMF Character match flag
|
||||
|
@ -864,7 +924,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
* @param __INTERRUPT__ specifies the UART interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
* @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
|
||||
#endif
|
||||
#endif
|
||||
* @arg @ref UART_IT_CM Character match interrupt
|
||||
* @arg @ref UART_IT_CTS CTS change interrupt
|
||||
|
@ -878,17 +940,24 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
* @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
|
||||
|
||||
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
|
||||
((__HANDLE__)->Instance->CR1 |= (1U <<\
|
||||
((__INTERRUPT__) & UART_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
|
||||
((__HANDLE__)->Instance->CR2 |= (1U <<\
|
||||
((__INTERRUPT__) & UART_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= (1U <<\
|
||||
((__INTERRUPT__) & UART_IT_MASK))))
|
||||
|
||||
/** @brief Disable the specified UART interrupt.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @param __INTERRUPT__ specifies the UART interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
* @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
|
||||
#endif
|
||||
#endif
|
||||
* @arg @ref UART_IT_CM Character match interrupt
|
||||
* @arg @ref UART_IT_CTS CTS change interrupt
|
||||
|
@ -902,16 +971,24 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
|
||||
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
|
||||
((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
|
||||
((__INTERRUPT__) & UART_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
|
||||
((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
|
||||
((__INTERRUPT__) & UART_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
|
||||
((__INTERRUPT__) & UART_IT_MASK))))
|
||||
|
||||
/** @brief Check whether the specified UART interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @param __INTERRUPT__ specifies the UART interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
* @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
|
||||
#endif
|
||||
#endif
|
||||
* @arg @ref UART_IT_CM Character match interrupt
|
||||
* @arg @ref UART_IT_CTS CTS change interrupt
|
||||
|
@ -933,7 +1010,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
* @param __INTERRUPT__ specifies the UART interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
* @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
|
||||
#endif
|
||||
#endif
|
||||
* @arg @ref UART_IT_CM Character match interrupt
|
||||
* @arg @ref UART_IT_CTS CTS change interrupt
|
||||
|
@ -947,9 +1026,13 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
|
||||
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
|
||||
(__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)
|
||||
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\
|
||||
(__HANDLE__)->Instance->CR1 : \
|
||||
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\
|
||||
(__HANDLE__)->Instance->CR2 : \
|
||||
(__HANDLE__)->Instance->CR3)) & (1U <<\
|
||||
(((uint16_t)(__INTERRUPT__)) &\
|
||||
UART_IT_MASK))) != RESET) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
|
@ -966,8 +1049,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
* @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
|
||||
* @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
|
||||
* @arg @ref UART_CLEAR_CMF Character Match Clear Flag
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
* @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
|
||||
#endif
|
||||
#endif
|
||||
* @retval None
|
||||
*/
|
||||
|
@ -1017,8 +1102,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
|
||||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
|
||||
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
|
||||
* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
|
||||
* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
|
||||
* - macro could only be called when corresponding UART instance is disabled
|
||||
* (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
|
||||
* macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
|
@ -1035,8 +1121,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
|
||||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
|
||||
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
|
||||
* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
|
||||
* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
|
||||
* - macro could only be called when corresponding UART instance is disabled
|
||||
* (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
|
||||
* macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
|
@ -1053,8 +1140,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
|
||||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
|
||||
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
|
||||
* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
|
||||
* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
|
||||
* - macro could only be called when corresponding UART instance is disabled
|
||||
* (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
|
||||
* macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
|
@ -1071,8 +1159,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
|
||||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
|
||||
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
|
||||
* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
|
||||
* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
|
||||
* - macro could only be called when corresponding UART instance is disabled
|
||||
* (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
|
||||
* macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
|
@ -1332,8 +1421,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
* @param __AUTOBAUDRATE__ UART auto Baud rate state.
|
||||
* @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
|
||||
*/
|
||||
#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
|
||||
((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
|
||||
#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \
|
||||
UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
|
||||
((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Ensure that UART DMA enabling or disabling on error setting is valid.
|
||||
|
@ -1375,9 +1465,14 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
* @param __WAKE__ UART wake-up selection.
|
||||
* @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
|
||||
*/
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
|
||||
((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
|
||||
((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
|
||||
#else
|
||||
#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
|
||||
((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
|
||||
#endif /* USART_CR3_WUFIE */
|
||||
#endif /* USART_CR1_UESM */
|
||||
|
||||
/**
|
||||
|
@ -1396,7 +1491,6 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
/* Include UART HAL Extended module */
|
||||
#include "stm32f7xx_hal_uart_ex.h"
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup UART_Exported_Functions UART Exported Functions
|
||||
* @{
|
||||
|
@ -1420,6 +1514,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
|
|||
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
|
||||
pUART_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
|
@ -1458,6 +1555,8 @@ void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
|
|||
void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
|
||||
void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
|
||||
|
||||
void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -1503,13 +1602,15 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
|
|||
* @{
|
||||
*/
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
|
||||
void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
|
||||
uint32_t Tickstart, uint32_t Timeout);
|
||||
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
|
||||
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
@ -117,7 +117,6 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
|
|||
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
|
||||
|
||||
#endif /* USART_CR1_UESM */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -141,6 +140,12 @@ HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart);
|
|||
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -48,11 +48,14 @@ typedef struct
|
|||
{
|
||||
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4]
|
||||
Baud Rate Register[15:4] = ((2 * fclk_pres) /
|
||||
((huart->Init.BaudRate)))[15:4]
|
||||
Baud Rate Register[3] = 0
|
||||
Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1
|
||||
Baud Rate Register[2:0] = (((2 * fclk_pres) /
|
||||
((huart->Init.BaudRate)))[3:0]) >> 1
|
||||
where fclk_pres is the USART input clock frequency
|
||||
@note Oversampling by 8 is systematically applied to achieve high baud rates. */
|
||||
@note Oversampling by 8 is systematically applied to
|
||||
achieve high baud rates. */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USARTEx_Word_Length. */
|
||||
|
@ -200,16 +203,16 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
/** @defgroup USART_Error_Definition USART Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
|
||||
#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
|
||||
#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
|
||||
#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
|
||||
#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
|
||||
#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
|
||||
#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */
|
||||
#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
|
||||
#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
|
||||
#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
|
||||
#define HAL_USART_ERROR_RTO ((uint32_t)0x00000080U) /*!< Receiver Timeout error */
|
||||
#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -245,15 +248,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Over_Sampling USART Over Sampling
|
||||
* @{
|
||||
*/
|
||||
#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
|
||||
#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock USART Clock
|
||||
* @{
|
||||
*/
|
||||
|
@ -474,9 +468,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
|
||||
#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\
|
||||
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
|
||||
((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
|
||||
((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
|
||||
|
||||
/** @brief Disable the specified USART interrupt.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
|
@ -490,10 +487,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
|
||||
|
||||
#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\
|
||||
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
|
||||
((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
|
||||
((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
|
||||
|
||||
/** @brief Check whether the specified USART interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
|
@ -510,7 +509,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
|
||||
& ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
|
||||
& (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
|
||||
USART_ISR_POS))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified USART interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
|
@ -526,10 +526,13 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
* @arg @ref USART_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \
|
||||
(((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
|
||||
(__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET)
|
||||
|
||||
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
|
||||
(__HANDLE__)->Instance->CR1 : \
|
||||
(((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
|
||||
(__HANDLE__)->Instance->CR2 : \
|
||||
(__HANDLE__)->Instance->CR3)) & (0x01U <<\
|
||||
(((uint16_t)(__INTERRUPT__)) &\
|
||||
USART_IT_MASK))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
|
@ -728,14 +731,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
*/
|
||||
#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART oversampling is valid.
|
||||
* @param __SAMPLING__ USART oversampling.
|
||||
* @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
|
||||
*/
|
||||
#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
|
||||
((__SAMPLING__) == USART_OVERSAMPLING_8))
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART clock state is valid.
|
||||
* @param __CLOCK__ USART clock state.
|
||||
|
|
|
@ -45,9 +45,9 @@ extern "C" {
|
|||
/** @defgroup USARTEx_Word_Length USARTEx Word Length
|
||||
* @{
|
||||
*/
|
||||
#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
|
||||
#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */
|
||||
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
|
||||
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
|
||||
#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -56,7 +56,7 @@ typedef struct
|
|||
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
|
||||
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
|
||||
|
||||
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
|
||||
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
|
||||
This parameter can be a value of @ref WWDG_EWI_Mode */
|
||||
|
||||
} WWDG_InitTypeDef;
|
||||
|
@ -68,17 +68,17 @@ typedef struct
|
|||
typedef struct __WWDG_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
{
|
||||
WWDG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
|
||||
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
|
||||
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
|
||||
|
||||
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
|
||||
#endif
|
||||
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
} WWDG_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
|
@ -87,8 +87,8 @@ typedef struct
|
|||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
|
||||
HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
|
||||
HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */
|
||||
HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */
|
||||
} HAL_WWDG_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
|
@ -96,7 +96,7 @@ typedef enum
|
|||
*/
|
||||
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
|
||||
|
||||
#endif
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -260,9 +260,10 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
|
|||
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
|
||||
pWWDG_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
|
||||
#endif
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
@ -402,7 +402,7 @@ typedef struct
|
|||
{
|
||||
uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
|
||||
This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
|
||||
@note On this STM32 serie, setting of external trigger edge is performed
|
||||
@note On this STM32 series, setting of external trigger edge is performed
|
||||
using function @ref LL_ADC_REG_StartConversionExtTrig().
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
|
||||
|
@ -456,7 +456,7 @@ typedef struct
|
|||
{
|
||||
uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
|
||||
This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
|
||||
@note On this STM32 serie, setting of external trigger edge is performed
|
||||
@note On this STM32 series, setting of external trigger edge is performed
|
||||
using function @ref LL_ADC_INJ_StartConversionExtTrig().
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
|
||||
|
@ -500,7 +500,7 @@ typedef struct
|
|||
#define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
|
||||
#define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */
|
||||
#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
|
||||
#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
|
||||
#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
|
||||
#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
|
||||
#define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
|
||||
#define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
|
||||
|
@ -508,9 +508,9 @@ typedef struct
|
|||
#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */
|
||||
#define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */
|
||||
#define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */
|
||||
#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
|
||||
#define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
|
||||
#define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
|
||||
#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
|
||||
#define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
|
||||
#define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
|
||||
#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
|
||||
#define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */
|
||||
#define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */
|
||||
|
@ -524,7 +524,7 @@ typedef struct
|
|||
*/
|
||||
#define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
|
||||
#define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */
|
||||
#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
|
||||
#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
|
||||
#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
|
||||
/**
|
||||
* @}
|
||||
|
@ -561,7 +561,7 @@ typedef struct
|
|||
/* If they are not listed below, they do not require any specific */
|
||||
/* path enable. In this case, Access to measurement path is done */
|
||||
/* only by selecting the corresponding ADC internal channel. */
|
||||
#define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement pathes all disabled */
|
||||
#define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement paths all disabled */
|
||||
#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
|
||||
#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
|
||||
#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */
|
||||
|
@ -584,7 +584,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
|
||||
#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
|
||||
#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -1031,7 +1031,7 @@ typedef struct
|
|||
/* configuration (system clock versus ADC clock), */
|
||||
/* and therefore must be defined in user application. */
|
||||
/* Indications for estimation of ADC timeout delays, for this */
|
||||
/* STM32 serie: */
|
||||
/* STM32 series: */
|
||||
/* - ADC enable time: maximum delay is 2us */
|
||||
/* (refer to device datasheet, parameter "tSTAB") */
|
||||
/* - ADC conversion time: duration depending on ADC clock and ADC */
|
||||
|
@ -1635,7 +1635,7 @@ typedef struct
|
|||
* connected to pin Vref+.
|
||||
* On devices with small package, the pin Vref+ is not present
|
||||
* and internally bonded to pin Vdda.
|
||||
* @note On this STM32 serie, calibration data of internal voltage reference
|
||||
* @note On this STM32 series, calibration data of internal voltage reference
|
||||
* VrefInt corresponds to a resolution of 12 bits,
|
||||
* this is the recommended ADC resolution to convert voltage of
|
||||
* internal voltage reference VrefInt.
|
||||
|
@ -1685,7 +1685,7 @@ typedef struct
|
|||
* @note Analog reference voltage (Vref+) must be either known from
|
||||
* user board environment or can be calculated using ADC measurement
|
||||
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
|
||||
* @note On this STM32 serie, calibration data of temperature sensor
|
||||
* @note On this STM32 series, calibration data of temperature sensor
|
||||
* corresponds to a resolution of 12 bits,
|
||||
* this is the recommended ADC resolution to convert voltage of
|
||||
* temperature sensor.
|
||||
|
@ -1832,7 +1832,7 @@ typedef struct
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
|
||||
{
|
||||
register uint32_t data_reg_addr = 0U;
|
||||
uint32_t data_reg_addr = 0U;
|
||||
|
||||
if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
|
||||
{
|
||||
|
@ -2080,7 +2080,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
|
|||
* @brief Set ADC group regular conversion trigger source:
|
||||
* internal (SW start) or from external IP (timer event,
|
||||
* external interrupt line).
|
||||
* @note On this STM32 serie, setting of external trigger edge is performed
|
||||
* @note On this STM32 series, setting of external trigger edge is performed
|
||||
* using function @ref LL_ADC_REG_StartConversionExtTrig().
|
||||
* @note Availability of parameters of trigger sources from timer
|
||||
* depends on timers availability on the selected device.
|
||||
|
@ -2108,7 +2108,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
|
||||
{
|
||||
/* Note: On this STM32 serie, ADC group regular external trigger edge */
|
||||
/* Note: On this STM32 series, ADC group regular external trigger edge */
|
||||
/* is used to perform a ADC conversion start. */
|
||||
/* This function does not set external trigger edge. */
|
||||
/* This feature is set using function */
|
||||
|
@ -2151,11 +2151,11 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
|
||||
{
|
||||
register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);
|
||||
uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);
|
||||
|
||||
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
|
||||
/* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */
|
||||
register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
|
||||
uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
|
||||
|
||||
/* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */
|
||||
/* to match with triggers literals definition. */
|
||||
|
@ -2184,7 +2184,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
|
|||
/**
|
||||
* @brief Get ADC group regular conversion trigger polarity.
|
||||
* @note Applicable only for trigger source set to external trigger.
|
||||
* @note On this STM32 serie, setting of external trigger edge is performed
|
||||
* @note On this STM32 series, setting of external trigger edge is performed
|
||||
* using function @ref LL_ADC_REG_StartConversionExtTrig().
|
||||
* @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge
|
||||
* @param ADCx ADC instance
|
||||
|
@ -2226,7 +2226,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
|
|||
* highest channel number).
|
||||
* Sequencer ranks are selected using
|
||||
* function "LL_ADC_REG_SetSequencerChannels()".
|
||||
* @note On this STM32 serie, group regular sequencer configuration
|
||||
* @note On this STM32 series, group regular sequencer configuration
|
||||
* is conditioned to ADC instance sequencer mode.
|
||||
* If ADC instance sequencer mode is disabled, sequencers of
|
||||
* all groups (group regular, group injected) can be configured
|
||||
|
@ -2287,7 +2287,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S
|
|||
* highest channel number).
|
||||
* Sequencer ranks are selected using
|
||||
* function "LL_ADC_REG_SetSequencerChannels()".
|
||||
* @note On this STM32 serie, group regular sequencer configuration
|
||||
* @note On this STM32 series, group regular sequencer configuration
|
||||
* is conditioned to ADC instance sequencer mode.
|
||||
* If ADC instance sequencer mode is disabled, sequencers of
|
||||
* all groups (group regular, group injected) can be configured
|
||||
|
@ -2377,13 +2377,13 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
|
|||
* @note This function performs configuration of:
|
||||
* - Channels ordering into each rank of scan sequence:
|
||||
* whatever channel can be placed into whatever rank.
|
||||
* @note On this STM32 serie, ADC group regular sequencer is
|
||||
* @note On this STM32 series, ADC group regular sequencer is
|
||||
* fully configurable: sequencer length and each rank
|
||||
* affectation to a channel are configurable.
|
||||
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
|
||||
* @note Depending on devices and packages, some channels may not be available.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @note On this STM32 serie, to measure internal channels (VrefInt,
|
||||
* @note On this STM32 series, to measure internal channels (VrefInt,
|
||||
* TempSensor, ...), measurement paths to internal channels must be
|
||||
* enabled separately.
|
||||
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
|
||||
|
@ -2455,7 +2455,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
|
|||
/* in register and register position depending on parameter "Rank". */
|
||||
/* Parameters "Rank" and "Channel" are used with masks because containing */
|
||||
/* other bits reserved for other purpose. */
|
||||
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
|
||||
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
|
||||
|
||||
MODIFY_REG(*preg,
|
||||
ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
|
||||
|
@ -2465,7 +2465,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
|
|||
/**
|
||||
* @brief Get ADC group regular sequence: channel on the selected
|
||||
* scan sequence rank.
|
||||
* @note On this STM32 serie, ADC group regular sequencer is
|
||||
* @note On this STM32 series, ADC group regular sequencer is
|
||||
* fully configurable: sequencer length and each rank
|
||||
* affectation to a channel are configurable.
|
||||
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
|
||||
|
@ -2548,7 +2548,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
|
||||
{
|
||||
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
|
||||
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
|
||||
|
||||
return (uint32_t) (READ_BIT(*preg,
|
||||
ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
|
||||
|
@ -2713,7 +2713,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
|
|||
* @brief Set ADC group injected conversion trigger source:
|
||||
* internal (SW start) or from external IP (timer event,
|
||||
* external interrupt line).
|
||||
* @note On this STM32 serie, setting of external trigger edge is performed
|
||||
* @note On this STM32 series, setting of external trigger edge is performed
|
||||
* using function @ref LL_ADC_INJ_StartConversionExtTrig().
|
||||
* @note Availability of parameters of trigger sources from timer
|
||||
* depends on timers availability on the selected device.
|
||||
|
@ -2740,7 +2740,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
|
||||
{
|
||||
/* Note: On this STM32 serie, ADC group injected external trigger edge */
|
||||
/* Note: On this STM32 series, ADC group injected external trigger edge */
|
||||
/* is used to perform a ADC conversion start. */
|
||||
/* This function does not set external trigger edge. */
|
||||
/* This feature is set using function */
|
||||
|
@ -2782,11 +2782,11 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
|
||||
{
|
||||
register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);
|
||||
uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);
|
||||
|
||||
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
|
||||
/* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */
|
||||
register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
|
||||
uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
|
||||
|
||||
/* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */
|
||||
/* to match with triggers literals definition. */
|
||||
|
@ -2833,7 +2833,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
|
|||
* - Sequence length: Number of ranks in the scan sequence.
|
||||
* - Sequence direction: Unless specified in parameters, sequencer
|
||||
* scan direction is forward (from rank 1 to rank n).
|
||||
* @note On this STM32 serie, group injected sequencer configuration
|
||||
* @note On this STM32 series, group injected sequencer configuration
|
||||
* is conditioned to ADC instance sequencer mode.
|
||||
* If ADC instance sequencer mode is disabled, sequencers of
|
||||
* all groups (group regular, group injected) can be configured
|
||||
|
@ -2861,7 +2861,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S
|
|||
* - Sequence length: Number of ranks in the scan sequence.
|
||||
* - Sequence direction: Unless specified in parameters, sequencer
|
||||
* scan direction is forward (from rank 1 to rank n).
|
||||
* @note On this STM32 serie, group injected sequencer configuration
|
||||
* @note On this STM32 series, group injected sequencer configuration
|
||||
* is conditioned to ADC instance sequencer mode.
|
||||
* If ADC instance sequencer mode is disabled, sequencers of
|
||||
* all groups (group regular, group injected) can be configured
|
||||
|
@ -2920,7 +2920,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
|
|||
* sequence rank.
|
||||
* @note Depending on devices and packages, some channels may not be available.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @note On this STM32 serie, to measure internal channels (VrefInt,
|
||||
* @note On this STM32 series, to measure internal channels (VrefInt,
|
||||
* TempSensor, ...), measurement paths to internal channels must be
|
||||
* enabled separately.
|
||||
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
|
||||
|
@ -2968,7 +2968,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
|
|||
/* in register depending on parameter "Rank". */
|
||||
/* Parameters "Rank" and "Channel" are used with masks because containing */
|
||||
/* other bits reserved for other purpose. */
|
||||
register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
|
||||
uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
|
||||
|
||||
MODIFY_REG(ADCx->JSQR,
|
||||
ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),
|
||||
|
@ -3033,7 +3033,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
|
||||
{
|
||||
register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
|
||||
uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
|
||||
|
||||
return (uint32_t)(READ_BIT(ADCx->JSQR,
|
||||
ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))
|
||||
|
@ -3113,7 +3113,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
|
||||
{
|
||||
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
|
||||
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
|
||||
|
||||
MODIFY_REG(*preg,
|
||||
ADC_JOFR1_JOFFSET1,
|
||||
|
@ -3140,7 +3140,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
|
||||
{
|
||||
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
|
||||
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
|
||||
|
||||
return (uint32_t)(READ_BIT(*preg,
|
||||
ADC_JOFR1_JOFFSET1)
|
||||
|
@ -3169,7 +3169,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
|
|||
* TS_temp, ...).
|
||||
* @note Conversion time is the addition of sampling time and processing time.
|
||||
* Refer to reference manual for ADC processing time of
|
||||
* this STM32 serie.
|
||||
* this STM32 series.
|
||||
* @note In case of ADC conversion of internal channel (VrefInt,
|
||||
* temperature sensor, ...), a sampling time minimum value
|
||||
* is required.
|
||||
|
@ -3237,7 +3237,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C
|
|||
/* in register and register position depending on parameter "Channel". */
|
||||
/* Parameter "Channel" is used with masks because containing */
|
||||
/* other bits reserved for other purpose. */
|
||||
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
|
||||
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
|
||||
|
||||
MODIFY_REG(*preg,
|
||||
ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
|
||||
|
@ -3251,7 +3251,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C
|
|||
* of channel mapped on ADC group regular or injected.
|
||||
* @note Conversion time is the addition of sampling time and processing time.
|
||||
* Refer to reference manual for ADC processing time of
|
||||
* this STM32 serie.
|
||||
* this STM32 series.
|
||||
* @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n
|
||||
* SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
|
||||
* SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
|
||||
|
@ -3310,7 +3310,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
|
||||
{
|
||||
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
|
||||
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
|
||||
|
||||
return (uint32_t)(READ_BIT(*preg,
|
||||
ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
|
||||
|
@ -3335,7 +3335,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32
|
|||
* @note In case of need to define a single channel to monitor
|
||||
* with analog watchdog from sequencer channel definition,
|
||||
* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
|
||||
* @note On this STM32 serie, there is only 1 kind of analog watchdog
|
||||
* @note On this STM32 series, there is only 1 kind of analog watchdog
|
||||
* instance:
|
||||
* - AWD standard (instance AWD1):
|
||||
* - channels monitored: can monitor 1 channel or all channels.
|
||||
|
@ -3444,7 +3444,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t
|
|||
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
|
||||
* Applicable only when the analog watchdog is set to monitor
|
||||
* one channel.
|
||||
* @note On this STM32 serie, there is only 1 kind of analog watchdog
|
||||
* @note On this STM32 series, there is only 1 kind of analog watchdog
|
||||
* instance:
|
||||
* - AWD standard (instance AWD1):
|
||||
* - channels monitored: can monitor 1 channel or all channels.
|
||||
|
@ -3529,7 +3529,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
|
|||
* @note In case of ADC resolution different of 12 bits,
|
||||
* analog watchdog thresholds data require a specific shift.
|
||||
* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
|
||||
* @note On this STM32 serie, there is only 1 kind of analog watchdog
|
||||
* @note On this STM32 series, there is only 1 kind of analog watchdog
|
||||
* instance:
|
||||
* - AWD standard (instance AWD1):
|
||||
* - channels monitored: can monitor 1 channel or all channels.
|
||||
|
@ -3547,7 +3547,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
|
||||
{
|
||||
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
|
||||
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
|
||||
|
||||
MODIFY_REG(*preg,
|
||||
ADC_HTR_HT,
|
||||
|
@ -3570,7 +3570,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
|
||||
{
|
||||
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
|
||||
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
|
||||
|
||||
return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
|
||||
}
|
||||
|
@ -3812,7 +3812,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADC
|
|||
|
||||
/**
|
||||
* @brief Enable the selected ADC instance.
|
||||
* @note On this STM32 serie, after ADC enable, a delay for
|
||||
* @note On this STM32 series, after ADC enable, a delay for
|
||||
* ADC internal analog stabilization is required before performing a
|
||||
* ADC conversion start.
|
||||
* Refer to device datasheet, parameter tSTAB.
|
||||
|
@ -3857,7 +3857,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
|
|||
|
||||
/**
|
||||
* @brief Start ADC group regular conversion.
|
||||
* @note On this STM32 serie, this function is relevant only for
|
||||
* @note On this STM32 series, this function is relevant only for
|
||||
* internal trigger (SW start), not for external trigger:
|
||||
* - If ADC trigger has been set to software start, ADC conversion
|
||||
* starts immediately.
|
||||
|
@ -3880,7 +3880,7 @@ __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
|
|||
* @brief Start ADC group regular conversion from external trigger.
|
||||
* @note ADC conversion will start at next trigger event (on the selected
|
||||
* trigger edge) following the ADC start conversion command.
|
||||
* @note On this STM32 serie, this function is relevant for
|
||||
* @note On this STM32 series, this function is relevant for
|
||||
* ADC conversion start from external trigger.
|
||||
* If internal trigger (SW start) is needed, perform ADC conversion
|
||||
* start using function @ref LL_ADC_REG_StartConversionSWStart().
|
||||
|
@ -3902,7 +3902,7 @@ __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32
|
|||
* @note No more ADC conversion will start at next trigger event
|
||||
* following the ADC stop conversion command.
|
||||
* If a conversion is on-going, it will be completed.
|
||||
* @note On this STM32 serie, there is no specific command
|
||||
* @note On this STM32 series, there is no specific command
|
||||
* to stop a conversion on-going or to stop ADC converting
|
||||
* in continuous mode. These actions can be performed
|
||||
* using function @ref LL_ADC_Disable().
|
||||
|
@ -4028,7 +4028,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef
|
|||
|
||||
/**
|
||||
* @brief Start ADC group injected conversion.
|
||||
* @note On this STM32 serie, this function is relevant only for
|
||||
* @note On this STM32 series, this function is relevant only for
|
||||
* internal trigger (SW start), not for external trigger:
|
||||
* - If ADC trigger has been set to software start, ADC conversion
|
||||
* starts immediately.
|
||||
|
@ -4051,7 +4051,7 @@ __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
|
|||
* @brief Start ADC group injected conversion from external trigger.
|
||||
* @note ADC conversion will start at next trigger event (on the selected
|
||||
* trigger edge) following the ADC start conversion command.
|
||||
* @note On this STM32 serie, this function is relevant for
|
||||
* @note On this STM32 series, this function is relevant for
|
||||
* ADC conversion start from external trigger.
|
||||
* If internal trigger (SW start) is needed, perform ADC conversion
|
||||
* start using function @ref LL_ADC_INJ_StartConversionSWStart().
|
||||
|
@ -4073,7 +4073,7 @@ __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32
|
|||
* @note No more ADC conversion will start at next trigger event
|
||||
* following the ADC stop conversion command.
|
||||
* If a conversion is on-going, it will be completed.
|
||||
* @note On this STM32 serie, there is no specific command
|
||||
* @note On this STM32 series, there is no specific command
|
||||
* to stop a conversion on-going or to stop ADC converting
|
||||
* in continuous mode. These actions can be performed
|
||||
* using function @ref LL_ADC_Disable().
|
||||
|
@ -4105,7 +4105,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
|
||||
{
|
||||
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
|
||||
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
|
||||
|
||||
return (uint32_t)(READ_BIT(*preg,
|
||||
ADC_JDR1_JDATA)
|
||||
|
@ -4132,7 +4132,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint
|
|||
*/
|
||||
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
|
||||
{
|
||||
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
|
||||
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
|
||||
|
||||
return (uint16_t)(READ_BIT(*preg,
|
||||
ADC_JDR1_JDATA)
|
||||
|
@ -4159,7 +4159,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint
|
|||
*/
|
||||
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
|
||||
{
|
||||
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
|
||||
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
|
||||
|
||||
return (uint16_t)(READ_BIT(*preg,
|
||||
ADC_JDR1_JDATA)
|
||||
|
@ -4186,7 +4186,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint
|
|||
*/
|
||||
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
|
||||
{
|
||||
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
|
||||
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
|
||||
|
||||
return (uint8_t)(READ_BIT(*preg,
|
||||
ADC_JDR1_JDATA)
|
||||
|
@ -4213,7 +4213,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32
|
|||
*/
|
||||
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
|
||||
{
|
||||
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
|
||||
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
|
||||
|
||||
return (uint8_t)(READ_BIT(*preg,
|
||||
ADC_JDR1_JDATA)
|
||||
|
@ -4263,7 +4263,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
|
||||
{
|
||||
/* Note: on this STM32 serie, there is no flag ADC group injected */
|
||||
/* Note: on this STM32 series, there is no flag ADC group injected */
|
||||
/* end of unitary conversion. */
|
||||
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
|
||||
/* in other STM32 families). */
|
||||
|
@ -4316,7 +4316,7 @@ __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
|
||||
{
|
||||
/* Note: on this STM32 serie, there is no flag ADC group injected */
|
||||
/* Note: on this STM32 series, there is no flag ADC group injected */
|
||||
/* end of unitary conversion. */
|
||||
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
|
||||
/* in other STM32 families). */
|
||||
|
@ -4427,7 +4427,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
|
||||
{
|
||||
/* Note: on this STM32 serie, there is no flag ADC group injected */
|
||||
/* Note: on this STM32 series, there is no flag ADC group injected */
|
||||
/* end of unitary conversion. */
|
||||
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
|
||||
/* in other STM32 families). */
|
||||
|
@ -4443,7 +4443,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
|
||||
{
|
||||
/* Note: on this STM32 serie, there is no flag ADC group injected */
|
||||
/* Note: on this STM32 series, there is no flag ADC group injected */
|
||||
/* end of unitary conversion. */
|
||||
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
|
||||
/* in other STM32 families). */
|
||||
|
@ -4459,7 +4459,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
|
||||
{
|
||||
/* Note: on this STM32 serie, there is no flag ADC group injected */
|
||||
/* Note: on this STM32 series, there is no flag ADC group injected */
|
||||
/* end of unitary conversion. */
|
||||
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
|
||||
/* in other STM32 families). */
|
||||
|
@ -4546,7 +4546,7 @@ __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
|
||||
{
|
||||
/* Note: on this STM32 serie, there is no flag ADC group injected */
|
||||
/* Note: on this STM32 series, there is no flag ADC group injected */
|
||||
/* end of unitary conversion. */
|
||||
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
|
||||
/* in other STM32 families). */
|
||||
|
@ -4599,7 +4599,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
|
||||
{
|
||||
/* Note: on this STM32 serie, there is no flag ADC group injected */
|
||||
/* Note: on this STM32 series, there is no flag ADC group injected */
|
||||
/* end of unitary conversion. */
|
||||
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
|
||||
/* in other STM32 families). */
|
||||
|
@ -4655,7 +4655,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
|
||||
{
|
||||
/* Note: on this STM32 serie, there is no flag ADC group injected */
|
||||
/* Note: on this STM32 series, there is no flag ADC group injected */
|
||||
/* end of unitary conversion. */
|
||||
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
|
||||
/* in other STM32 families). */
|
||||
|
|
|
@ -18,8 +18,8 @@
|
|||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_LL_DAC_H
|
||||
#define __STM32F7xx_LL_DAC_H
|
||||
#ifndef STM32F7xx_LL_DAC_H
|
||||
#define STM32F7xx_LL_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
@ -48,40 +48,76 @@ extern "C" {
|
|||
|
||||
/* Internal masks for DAC channels definition */
|
||||
/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
|
||||
/* - channel bits position into register CR */
|
||||
/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
|
||||
/* - channel bits position into register SWTRIG */
|
||||
/* - channel register offset of data holding register DHRx */
|
||||
/* - channel register offset of data output register DORx */
|
||||
#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
|
||||
#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
|
||||
#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
|
||||
CR, MCR, CCR, SHHR, SHRR of channel 1 */
|
||||
#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
|
||||
CR, MCR, CCR, SHHR, SHRR of channel 2 */
|
||||
#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
|
||||
|
||||
#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
|
||||
#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
|
||||
#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
|
||||
#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
|
||||
#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
|
||||
|
||||
#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
|
||||
#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
|
||||
#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
|
||||
#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
|
||||
#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
|
||||
#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
|
||||
#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
|
||||
#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
|
||||
#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
|
||||
#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
|
||||
#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
|
||||
#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
|
||||
DHR12Rx channel 1 (shifted left of 20 bits) */
|
||||
#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
|
||||
DHR12Rx channel 1 (shifted left of 24 bits) */
|
||||
|
||||
#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
|
||||
#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
|
||||
#define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus
|
||||
DHR12Rx channel 1 (shifted left of 16 bits) */
|
||||
#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
|
||||
DHR12Rx channel 1 (shifted left of 20 bits) */
|
||||
#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
|
||||
DHR12Rx channel 1 (shifted left of 24 bits) */
|
||||
|
||||
#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL
|
||||
#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
|
||||
#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
|
||||
#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
|
||||
| DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
|
||||
|
||||
#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
|
||||
|
||||
#define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus
|
||||
DORx channel 2 (shifted left of 28 bits) */
|
||||
#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
|
||||
|
||||
|
||||
|
||||
#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
|
||||
DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
|
||||
#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
|
||||
to position 0 */
|
||||
#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
|
||||
to position 0 */
|
||||
|
||||
#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx
|
||||
channel 1 or 2 versus DHR12Rx channel 1
|
||||
(shifted left of 16 bits) */
|
||||
#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
|
||||
channel 1 or 2 versus DHR12Rx channel 1
|
||||
(shifted left of 20 bits) */
|
||||
#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
|
||||
channel 1 or 2 versus DHR12Rx channel 1
|
||||
(shifted left of 24 bits) */
|
||||
#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx
|
||||
channel 1 or 2 versus DORx channel 1
|
||||
(shifted left of 28 bits) */
|
||||
|
||||
/* DAC registers bits positions */
|
||||
#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
|
||||
#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
|
||||
#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
|
||||
#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
|
||||
#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
|
||||
#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
|
||||
|
||||
/* Miscellaneous data */
|
||||
#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
|
||||
#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
|
||||
bits (voltage range determined by analog voltage
|
||||
references Vref+ and Vref-, refer to reference manual) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -93,17 +129,6 @@ extern "C" {
|
|||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Driver macro reserved for internal use: isolate bits with the
|
||||
* selected mask and shift them to the register LSB
|
||||
* (shift mask on register position bit 0).
|
||||
* @param __BITS__ Bits in register 32 bits
|
||||
* @param __MASK__ Mask in register 32 bits
|
||||
* @retval Bits in register 32 bits
|
||||
*/
|
||||
#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
|
||||
(((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
|
||||
|
||||
/**
|
||||
* @brief Driver macro reserved for internal use: set a pointer to
|
||||
* a register from a register basis from which an offset
|
||||
|
@ -111,9 +136,9 @@ extern "C" {
|
|||
* @param __REG__ Register basis from which the offset is applied.
|
||||
* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
|
||||
* @retval Pointer to register address
|
||||
*/
|
||||
*/
|
||||
#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
|
||||
((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
|
||||
((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -131,28 +156,38 @@ extern "C" {
|
|||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
|
||||
uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
|
||||
internal (SW start) or from external peripheral
|
||||
(timer event, external interrupt line).
|
||||
This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_DAC_SetTriggerSource(). */
|
||||
|
||||
uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_DAC_SetWaveAutoGeneration(). */
|
||||
|
||||
uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
|
||||
If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
|
||||
If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
|
||||
@note If waveform automatic generation mode is disabled, this parameter is discarded.
|
||||
If waveform automatic generation mode is set to noise, this parameter
|
||||
can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
|
||||
If waveform automatic generation mode is set to triangle,
|
||||
this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
|
||||
@note If waveform automatic generation mode is disabled,
|
||||
this parameter is discarded.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_DAC_SetWaveNoiseLFSR(),
|
||||
@ref LL_DAC_SetWaveTriangleAmplitude()
|
||||
depending on the wave automatic generation selected. */
|
||||
|
||||
uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
|
||||
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_DAC_SetOutputBuffer(). */
|
||||
} LL_DAC_InitTypeDef;
|
||||
|
||||
/**
|
||||
|
@ -174,6 +209,7 @@ typedef struct
|
|||
|
||||
/* DAC channel 2 flags */
|
||||
#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -183,7 +219,9 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
|
||||
|
||||
#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -192,7 +230,9 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
|
||||
|
||||
#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -201,13 +241,13 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
|
||||
#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
|
||||
#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -215,9 +255,9 @@ typedef struct
|
|||
/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
|
||||
#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
|
||||
#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
|
||||
#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
|
||||
#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
|
||||
#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -225,7 +265,7 @@ typedef struct
|
|||
/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
|
||||
* @{
|
||||
*/
|
||||
#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
|
||||
#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
|
||||
#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
|
||||
#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
|
||||
#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
|
||||
|
@ -244,7 +284,7 @@ typedef struct
|
|||
/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
|
||||
* @{
|
||||
*/
|
||||
#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
|
||||
#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
|
||||
#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
|
||||
#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
|
||||
#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
|
||||
|
@ -263,18 +303,17 @@ typedef struct
|
|||
/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
|
||||
* @{
|
||||
*/
|
||||
#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
|
||||
#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
|
||||
#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
|
||||
* @{
|
||||
*/
|
||||
#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
|
||||
#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
|
||||
#define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
|
||||
#define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -285,15 +324,15 @@ typedef struct
|
|||
/* List of DAC registers intended to be used (most commonly) with */
|
||||
/* DMA transfer. */
|
||||
/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
|
||||
#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
|
||||
#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
|
||||
#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
|
||||
#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
|
||||
#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
|
||||
#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
|
||||
* @note Only DAC IP HW delays are defined in DAC LL driver driver,
|
||||
* @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
|
||||
* not timeout values.
|
||||
* For details on delays values, refer to descriptions in source code
|
||||
* above each literal definition.
|
||||
|
@ -312,7 +351,7 @@ typedef struct
|
|||
/* Literal set to maximum value (refer to device datasheet, */
|
||||
/* parameter "tWAKEUP"). */
|
||||
/* Unit: us */
|
||||
#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
|
||||
#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
|
||||
|
||||
/* Delay for DAC channel voltage settling time. */
|
||||
/* Note: DAC channel startup time depends on board application environment: */
|
||||
|
@ -325,7 +364,8 @@ typedef struct
|
|||
/* Literal set to maximum value (refer to device datasheet, */
|
||||
/* parameter "tSETTLING"). */
|
||||
/* Unit: us */
|
||||
#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
|
||||
#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -397,22 +437,8 @@ typedef struct
|
|||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2
|
||||
*/
|
||||
#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
|
||||
(((__DECIMAL_NB__) == 1U) \
|
||||
? ( \
|
||||
LL_DAC_CHANNEL_1 \
|
||||
) \
|
||||
: \
|
||||
(((__DECIMAL_NB__) == 2U) \
|
||||
? ( \
|
||||
LL_DAC_CHANNEL_2 \
|
||||
) \
|
||||
: \
|
||||
( \
|
||||
0 \
|
||||
) \
|
||||
) \
|
||||
)
|
||||
#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
|
||||
(((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
|
||||
|
||||
/**
|
||||
* @brief Helper macro to define the DAC conversion data full-scale digital
|
||||
|
@ -426,7 +452,7 @@ typedef struct
|
|||
* @retval ADC conversion data equivalent voltage value (unit: mVolt)
|
||||
*/
|
||||
#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
|
||||
((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
|
||||
((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
|
||||
|
||||
/**
|
||||
* @brief Helper macro to calculate the DAC conversion data (unit: digital
|
||||
|
@ -437,7 +463,7 @@ typedef struct
|
|||
* @ref LL_DAC_ConvertData12RightAligned().
|
||||
* @note Analog reference voltage (Vref+) must be either known from
|
||||
* user board environment or can be calculated using ADC measurement
|
||||
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
|
||||
* and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
|
||||
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
|
||||
* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
|
||||
* (unit: mVolt).
|
||||
|
@ -449,9 +475,9 @@ typedef struct
|
|||
#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
|
||||
__DAC_VOLTAGE__,\
|
||||
__DAC_RESOLUTION__) \
|
||||
((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
|
||||
/ (__VREFANALOG_VOLTAGE__) \
|
||||
)
|
||||
((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
|
||||
/ (__VREFANALOG_VOLTAGE__) \
|
||||
)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -466,10 +492,6 @@ typedef struct
|
|||
/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the conversion trigger source for the selected DAC channel.
|
||||
* @note For conversion trigger source to be effective, DAC trigger
|
||||
|
@ -611,7 +633,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Set the noise waveform generation for the selected DAC channel:
|
||||
* @brief Get the noise waveform generation for the selected DAC channel:
|
||||
* Noise mode and parameters LFSR (linear feedback shift register).
|
||||
* @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
|
||||
* CR MAMP2 LL_DAC_GetWaveNoiseLFSR
|
||||
|
@ -669,7 +691,8 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC
|
|||
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
|
||||
__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
|
||||
uint32_t TriangleAmplitude)
|
||||
{
|
||||
MODIFY_REG(DACx->CR,
|
||||
DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
|
||||
|
@ -677,7 +700,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Set the triangle waveform generation for the selected DAC channel:
|
||||
* @brief Get the triangle waveform generation for the selected DAC channel:
|
||||
* triangle mode and amplitude.
|
||||
* @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
|
||||
* CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
|
||||
|
@ -802,9 +825,9 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (READ_BIT(DACx->CR,
|
||||
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
== (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
|
||||
return ((READ_BIT(DACx->CR,
|
||||
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
== (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -820,7 +843,8 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_
|
|||
* LL_DMA_ConfigAddresses(DMA1,
|
||||
* LL_DMA_CHANNEL_1,
|
||||
* (uint32_t)&< array or variable >,
|
||||
* LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
|
||||
* LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
|
||||
* LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
|
||||
* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
|
||||
* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
|
||||
* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
|
||||
|
@ -842,7 +866,8 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C
|
|||
{
|
||||
/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
|
||||
/* DAC channel selected. */
|
||||
return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
|
||||
return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
|
||||
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
|
@ -900,9 +925,9 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (READ_BIT(DACx->CR,
|
||||
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
== (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
|
||||
return ((READ_BIT(DACx->CR,
|
||||
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
== (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -958,15 +983,17 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (READ_BIT(DACx->CR,
|
||||
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
== (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
|
||||
return ((READ_BIT(DACx->CR,
|
||||
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
== (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Trig DAC conversion by software for the selected DAC channel.
|
||||
* @note Preliminarily, DAC trigger must be set to software trigger
|
||||
* using function @ref LL_DAC_SetTriggerSource()
|
||||
* using function
|
||||
* @ref LL_DAC_Init()
|
||||
* @ref LL_DAC_SetTriggerSource()
|
||||
* with parameter "LL_DAC_TRIGGER_SOFTWARE".
|
||||
* and DAC trigger must be enabled using
|
||||
* function @ref LL_DAC_EnableTrigger().
|
||||
|
@ -1003,11 +1030,10 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha
|
|||
*/
|
||||
__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
|
||||
{
|
||||
register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
|
||||
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
|
||||
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
|
||||
|
||||
MODIFY_REG(*preg,
|
||||
DAC_DHR12R1_DACC1DHR,
|
||||
Data);
|
||||
MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1025,11 +1051,10 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_
|
|||
*/
|
||||
__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
|
||||
{
|
||||
register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
|
||||
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
|
||||
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
|
||||
|
||||
MODIFY_REG(*preg,
|
||||
DAC_DHR12L1_DACC1DHR,
|
||||
Data);
|
||||
MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1047,13 +1072,13 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t
|
|||
*/
|
||||
__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
|
||||
{
|
||||
register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
|
||||
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
|
||||
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
|
||||
|
||||
MODIFY_REG(*preg,
|
||||
DAC_DHR8R1_DACC1DHR,
|
||||
Data);
|
||||
MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set the data to be loaded in the data holding register
|
||||
* in format 12 bits left alignment (LSB aligned on bit 0),
|
||||
|
@ -1065,7 +1090,8 @@ __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t
|
|||
* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
|
||||
__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
|
||||
uint32_t DataChannel2)
|
||||
{
|
||||
MODIFY_REG(DACx->DHR12RD,
|
||||
(DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
|
||||
|
@ -1083,7 +1109,8 @@ __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uin
|
|||
* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
|
||||
__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
|
||||
uint32_t DataChannel2)
|
||||
{
|
||||
/* Note: Data of DAC channel 2 shift value subtracted of 4 because */
|
||||
/* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
|
||||
|
@ -1104,13 +1131,15 @@ __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint
|
|||
* @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
|
||||
__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
|
||||
uint32_t DataChannel2)
|
||||
{
|
||||
MODIFY_REG(DACx->DHR8RD,
|
||||
(DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
|
||||
((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Retrieve output data currently generated for the selected DAC channel.
|
||||
* @note Whatever alignment and resolution settings
|
||||
|
@ -1127,7 +1156,8 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
|
||||
__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
|
||||
& DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
|
||||
|
||||
return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
|
||||
}
|
||||
|
@ -1139,6 +1169,8 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D
|
|||
/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get DAC underrun flag for DAC channel 1
|
||||
* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
|
||||
|
@ -1147,9 +1179,10 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
|
||||
{
|
||||
return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
|
||||
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get DAC underrun flag for DAC channel 2
|
||||
* @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
|
||||
|
@ -1158,9 +1191,10 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
|
||||
{
|
||||
return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
|
||||
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear DAC underrun flag for DAC channel 1
|
||||
* @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
|
||||
|
@ -1172,6 +1206,7 @@ __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
|
|||
WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear DAC underrun flag for DAC channel 2
|
||||
* @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
|
||||
|
@ -1183,6 +1218,7 @@ __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
|
|||
WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -1202,6 +1238,7 @@ __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
|
|||
SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable DMA underrun interrupt for DAC channel 2
|
||||
* @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
|
||||
|
@ -1213,6 +1250,7 @@ __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
|
|||
SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable DMA underrun interrupt for DAC channel 1
|
||||
* @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
|
||||
|
@ -1224,6 +1262,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
|
|||
CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable DMA underrun interrupt for DAC channel 2
|
||||
* @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
|
||||
|
@ -1235,6 +1274,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
|
|||
CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get DMA underrun interrupt for DAC channel 1
|
||||
* @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
|
||||
|
@ -1243,9 +1283,10 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
|
||||
{
|
||||
return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
|
||||
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get DMA underrun interrupt for DAC channel 2
|
||||
* @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
|
||||
|
@ -1254,9 +1295,10 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
|
||||
{
|
||||
return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
|
||||
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -1266,9 +1308,9 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
|
|||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
|
||||
ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
|
||||
void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
|
||||
ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
|
||||
ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
|
||||
void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -1293,6 +1335,6 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_LL_DAC_H */
|
||||
#endif /* STM32F7xx_LL_DAC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
@ -66,84 +66,116 @@ typedef struct
|
|||
uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
|
||||
- This parameter can be one value of @ref DMA2D_LL_EC_MODE.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/
|
||||
This parameter can be modified afterwards,
|
||||
using unitary function @ref LL_DMA2D_SetMode(). */
|
||||
|
||||
uint32_t ColorMode; /*!< Specifies the color format of the output image.
|
||||
- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
|
||||
This parameter can be modified afterwards using,
|
||||
unitary function @ref LL_DMA2D_SetOutputColorMode(). */
|
||||
|
||||
uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
This parameter can be modified afterwards,
|
||||
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
function @ref LL_DMA2D_ConfigOutputColor(). */
|
||||
|
||||
uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
This parameter can be modified afterwards
|
||||
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
function @ref LL_DMA2D_ConfigOutputColor(). */
|
||||
|
||||
uint32_t OutputRed; /*!< Specifies the Red value of the output image.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
This parameter can be modified afterwards
|
||||
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
function @ref LL_DMA2D_ConfigOutputColor(). */
|
||||
|
||||
uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter is not considered if RGB888 or RGB565 color mode is selected.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
This parameter can be modified afterwards using,
|
||||
unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
function @ref LL_DMA2D_ConfigOutputColor(). */
|
||||
|
||||
uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
|
||||
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
|
||||
This parameter can be modified afterwards,
|
||||
using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
|
||||
|
||||
|
||||
|
||||
uint32_t LineOffset; /*!< Specifies the output line offset value.
|
||||
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
|
||||
This parameter can be modified afterwards,
|
||||
using unitary function @ref LL_DMA2D_SetLineOffset(). */
|
||||
|
||||
uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
|
||||
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x0000 and Max_Data = 0xFFFF.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
|
||||
This parameter can be modified afterwards,
|
||||
using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
|
||||
|
||||
uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transfered.
|
||||
uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred.
|
||||
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
|
||||
This parameter can be modified afterwards using,
|
||||
unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
|
||||
|
||||
#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
|
||||
uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode.
|
||||
- This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
|
||||
This parameter can be modified afterwards using,
|
||||
unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
|
||||
|
||||
uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode.
|
||||
- This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
|
||||
This parameter can be modified afterwards using,
|
||||
unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
|
||||
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
|
||||
|
||||
} LL_DMA2D_InitTypeDef;
|
||||
|
@ -154,7 +186,8 @@ typedef struct
|
|||
typedef struct
|
||||
{
|
||||
uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
|
||||
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
|
||||
|
||||
This parameter can be modified afterwards using unitary functions
|
||||
- @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
|
||||
|
@ -224,7 +257,8 @@ typedef struct
|
|||
- @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
|
||||
|
||||
uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
|
||||
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
|
||||
|
||||
This parameter can be modified afterwards using unitary functions
|
||||
- @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
|
||||
|
@ -257,45 +291,68 @@ typedef struct
|
|||
uint32_t ColorMode; /*!< Specifies the color format of the output image.
|
||||
- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
|
||||
This parameter can be modified afterwards using
|
||||
unitary function @ref LL_DMA2D_SetOutputColorMode(). */
|
||||
|
||||
uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
This parameter can be modified afterwards using,
|
||||
unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
function @ref LL_DMA2D_ConfigOutputColor(). */
|
||||
|
||||
uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
This parameter can be modified afterwards,
|
||||
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
function @ref LL_DMA2D_ConfigOutputColor(). */
|
||||
|
||||
uint32_t OutputRed; /*!< Specifies the Red value of the output image.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
This parameter can be modified afterwards,
|
||||
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
function @ref LL_DMA2D_ConfigOutputColor(). */
|
||||
|
||||
uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
|
||||
- This parameter must be a number between:
|
||||
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
|
||||
- This parameter is not considered if RGB888 or RGB565 color mode is selected.
|
||||
|
||||
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
This parameter can be modified afterwards,
|
||||
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
|
||||
function @ref LL_DMA2D_ConfigOutputColor(). */
|
||||
|
||||
} LL_DMA2D_ColorTypeDef;
|
||||
|
@ -383,9 +440,11 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
|
||||
#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by programmed alpha value */
|
||||
#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by programmed alpha value
|
||||
with original alpha channel value */
|
||||
#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by
|
||||
programmed alpha value */
|
||||
#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by
|
||||
programmed alpha value with,
|
||||
original alpha channel value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -808,7 +808,7 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FMC_Access_Mode FMC Access Mode
|
||||
* @{
|
||||
*/
|
||||
|
|
|
@ -939,7 +939,8 @@ __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMas
|
|||
*/
|
||||
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
|
||||
uint32_t odr = READ_REG(GPIOx->ODR);
|
||||
WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -67,38 +67,38 @@ extern "C" {
|
|||
typedef struct
|
||||
{
|
||||
uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
|
||||
This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
|
||||
This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
|
||||
|
||||
uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
|
||||
This parameter must be set by referring to the STM32CubeMX Tool and
|
||||
the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
|
||||
the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
|
||||
|
||||
uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
|
||||
This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
|
||||
This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
|
||||
|
||||
This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
|
||||
|
||||
uint32_t DigitalFilter; /*!< Configures the digital noise filter.
|
||||
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
|
||||
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the device own address 1.
|
||||
This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
|
||||
This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
|
||||
|
||||
uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
|
||||
This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
|
||||
This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
|
||||
|
||||
uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
|
||||
This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
|
||||
This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
|
||||
} LL_I2C_InitTypeDef;
|
||||
|
@ -360,11 +360,11 @@ typedef struct
|
|||
* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
|
||||
*/
|
||||
#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
|
||||
((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
|
||||
(((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
|
||||
(((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
|
||||
(((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
|
||||
(((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
|
||||
((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
|
||||
(((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
|
||||
(((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
|
||||
(((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
|
||||
(((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -578,17 +578,17 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
|
||||
{
|
||||
register uint32_t data_reg_addr;
|
||||
uint32_t data_reg_addr;
|
||||
|
||||
if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
|
||||
{
|
||||
/* return address of TXDR register */
|
||||
data_reg_addr = (uint32_t) & (I2Cx->TXDR);
|
||||
data_reg_addr = (uint32_t) &(I2Cx->TXDR);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* return address of RXDR register */
|
||||
data_reg_addr = (uint32_t) & (I2Cx->RXDR);
|
||||
data_reg_addr = (uint32_t) &(I2Cx->RXDR);
|
||||
}
|
||||
|
||||
return data_reg_addr;
|
||||
|
@ -902,7 +902,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Configure peripheral mode.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
|
||||
* CR1 SMBDEN LL_I2C_SetMode
|
||||
|
@ -921,7 +921,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
|
|||
|
||||
/**
|
||||
* @brief Get peripheral mode.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
|
||||
* CR1 SMBDEN LL_I2C_GetMode
|
||||
|
@ -939,7 +939,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Enable SMBus alert (Host or Device mode)
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note SMBus Device mode:
|
||||
* - SMBus Alert pin is drived low and
|
||||
|
@ -957,7 +957,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Disable SMBus alert (Host or Device mode)
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note SMBus Device mode:
|
||||
* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
|
||||
|
@ -975,7 +975,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
|
||||
* @param I2Cx I2C Instance.
|
||||
|
@ -988,7 +988,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Enable SMBus Packet Error Calculation (PEC).
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
|
||||
* @param I2Cx I2C Instance.
|
||||
|
@ -1001,7 +1001,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Disable SMBus Packet Error Calculation (PEC).
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
|
||||
* @param I2Cx I2C Instance.
|
||||
|
@ -1014,7 +1014,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
|
||||
* @param I2Cx I2C Instance.
|
||||
|
@ -1027,7 +1027,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Configure the SMBus Clock Timeout.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
|
||||
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
|
||||
|
@ -1050,7 +1050,7 @@ __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Timeo
|
|||
|
||||
/**
|
||||
* @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note These bits can only be programmed when TimeoutA is disabled.
|
||||
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
|
||||
|
@ -1065,7 +1065,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout
|
|||
|
||||
/**
|
||||
* @brief Get the SMBus Clock TimeoutA setting.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
|
||||
* @param I2Cx I2C Instance.
|
||||
|
@ -1078,7 +1078,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Set the SMBus Clock TimeoutA mode.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note This bit can only be programmed when TimeoutA is disabled.
|
||||
* @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
|
||||
|
@ -1095,7 +1095,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim
|
|||
|
||||
/**
|
||||
* @brief Get the SMBus Clock TimeoutA mode.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
|
||||
* @param I2Cx I2C Instance.
|
||||
|
@ -1110,7 +1110,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note These bits can only be programmed when TimeoutB is disabled.
|
||||
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
|
||||
|
@ -1124,8 +1124,8 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
|
||||
* @param I2Cx I2C Instance.
|
||||
|
@ -1138,7 +1138,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Enable the SMBus Clock Timeout.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
|
||||
* TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
|
||||
|
@ -1156,7 +1156,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Clock
|
|||
|
||||
/**
|
||||
* @brief Disable the SMBus Clock Timeout.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
|
||||
* TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
|
||||
|
@ -1174,7 +1174,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc
|
|||
|
||||
/**
|
||||
* @brief Check if the SMBus Clock Timeout is enabled or disabled.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
|
||||
* TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
|
||||
|
@ -1404,7 +1404,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Enable Error interrupts.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note Any of these errors will generate interrupt :
|
||||
* Arbitration Loss (ARLO)
|
||||
|
@ -1424,7 +1424,7 @@ __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Disable Error interrupts.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note Any of these errors will generate interrupt :
|
||||
* Arbitration Loss (ARLO)
|
||||
|
@ -1606,7 +1606,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Indicate the status of SMBus PEC error flag in reception.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note RESET: Clear default value.
|
||||
* SET: When the received PEC does not match with the PEC register content.
|
||||
|
@ -1621,7 +1621,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Indicate the status of SMBus Timeout detection flag.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note RESET: Clear default value.
|
||||
* SET: When a timeout or extended clock timeout occurs.
|
||||
|
@ -1636,7 +1636,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Indicate the status of SMBus alert flag.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note RESET: Clear default value.
|
||||
* SET: When SMBus host configuration, SMBus alert enabled and
|
||||
|
@ -1743,7 +1743,7 @@ __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Clear SMBus PEC error flag.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
|
||||
* @param I2Cx I2C Instance.
|
||||
|
@ -1756,7 +1756,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Clear SMBus Timeout detection flag.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
|
||||
* @param I2Cx I2C Instance.
|
||||
|
@ -1769,7 +1769,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Clear SMBus Alert flag.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
|
||||
* @param I2Cx I2C Instance.
|
||||
|
@ -2051,7 +2051,9 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
|
|||
__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
|
||||
uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
|
||||
{
|
||||
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
|
||||
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
|
||||
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
|
||||
I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
|
||||
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
|
||||
SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
|
||||
}
|
||||
|
@ -2084,7 +2086,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
|
||||
* This bit has no effect when RELOAD bit is set.
|
||||
|
@ -2100,7 +2102,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
|
||||
* @param I2Cx I2C Instance.
|
||||
|
@ -2113,12 +2115,12 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
|
|||
|
||||
/**
|
||||
* @brief Get the SMBus Packet Error byte calculated.
|
||||
* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll PECR PEC LL_I2C_GetSMBusPEC
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
|
||||
|
|
|
@ -304,8 +304,8 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
|
|||
/**
|
||||
* @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
|
||||
* @rmtoll SR PVU LL_IWDG_IsReady\n
|
||||
* SR WVU LL_IWDG_IsReady\n
|
||||
* SR RVU LL_IWDG_IsReady
|
||||
* SR RVU LL_IWDG_IsReady\n
|
||||
* SR WVU LL_IWDG_IsReady
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bits (1 or 0).
|
||||
*/
|
||||
|
@ -318,7 +318,6 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
|
|||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -100,9 +100,9 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
|
||||
#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
|
||||
#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
|
||||
#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
|
||||
#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
|
||||
#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
|
||||
#define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
|
||||
#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
|
||||
|
@ -114,13 +114,13 @@ typedef struct
|
|||
* @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
|
||||
* @{
|
||||
*/
|
||||
#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */
|
||||
#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */
|
||||
#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */
|
||||
#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */
|
||||
#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */
|
||||
#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */
|
||||
#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */
|
||||
#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */
|
||||
#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */
|
||||
#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */
|
||||
#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */
|
||||
#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */
|
||||
#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */
|
||||
#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -155,7 +155,7 @@ typedef struct
|
|||
/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
|
||||
* @{
|
||||
*/
|
||||
#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
|
||||
#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
|
||||
#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
|
||||
/**
|
||||
* @}
|
||||
|
@ -1227,7 +1227,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
|
|||
|
||||
/**
|
||||
* @brief Enable autoreload register write completed interrupt (ARROKIE).
|
||||
* @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
|
||||
* @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval None
|
||||
*/
|
||||
|
@ -1238,7 +1238,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
|
|||
|
||||
/**
|
||||
* @brief Disable autoreload register write completed interrupt (ARROKIE).
|
||||
* @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
|
||||
* @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval None
|
||||
*/
|
||||
|
@ -1249,7 +1249,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
|
|||
|
||||
/**
|
||||
* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
|
||||
* @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
|
||||
* @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit(1 or 0).
|
||||
*/
|
||||
|
@ -1260,7 +1260,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
|
|||
|
||||
/**
|
||||
* @brief Enable direction change to up interrupt (UPIE).
|
||||
* @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
|
||||
* @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval None
|
||||
*/
|
||||
|
@ -1271,7 +1271,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
|
|||
|
||||
/**
|
||||
* @brief Disable direction change to up interrupt (UPIE).
|
||||
* @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
|
||||
* @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval None
|
||||
*/
|
||||
|
@ -1282,7 +1282,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
|
|||
|
||||
/**
|
||||
* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
|
||||
* @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
|
||||
* @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit(1 or 0).
|
||||
*/
|
||||
|
@ -1293,7 +1293,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
|
|||
|
||||
/**
|
||||
* @brief Enable direction change to down interrupt (DOWNIE).
|
||||
* @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
|
||||
* @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval None
|
||||
*/
|
||||
|
@ -1304,7 +1304,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
|
|||
|
||||
/**
|
||||
* @brief Disable direction change to down interrupt (DOWNIE).
|
||||
* @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
|
||||
* @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval None
|
||||
*/
|
||||
|
@ -1315,7 +1315,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
|
|||
|
||||
/**
|
||||
* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
|
||||
* @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
|
||||
* @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit(1 or 0).
|
||||
*/
|
||||
|
|
|
@ -1190,7 +1190,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
|
||||
{
|
||||
register uint32_t temp = 0U;
|
||||
uint32_t temp = 0U;
|
||||
|
||||
temp = Format12_24 | \
|
||||
(((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
|
||||
|
@ -1218,7 +1218,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24,
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
|
||||
{
|
||||
register uint32_t temp = 0U;
|
||||
uint32_t temp = 0U;
|
||||
|
||||
temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
|
||||
return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \
|
||||
|
@ -1520,7 +1520,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
|
||||
{
|
||||
register uint32_t temp = 0U;
|
||||
uint32_t temp = 0U;
|
||||
|
||||
temp = (WeekDay << RTC_DR_WDU_Pos) | \
|
||||
(((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
|
||||
|
@ -1548,7 +1548,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
|
||||
{
|
||||
register uint32_t temp = 0U;
|
||||
uint32_t temp = 0U;
|
||||
|
||||
temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
|
||||
return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
|
||||
|
@ -1848,7 +1848,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
|
||||
{
|
||||
register uint32_t temp = 0U;
|
||||
uint32_t temp = 0U;
|
||||
|
||||
temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
|
||||
(((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
|
||||
|
@ -2214,7 +2214,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
|
||||
{
|
||||
register uint32_t temp = 0U;
|
||||
uint32_t temp = 0U;
|
||||
|
||||
temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
|
||||
(((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
|
||||
|
@ -2992,7 +2992,7 @@ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
|
||||
{
|
||||
register uint32_t tmp = 0U;
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
tmp = (uint32_t)(&(RTCx->BKP0R));
|
||||
tmp += (BackupRegister * 4U);
|
||||
|
@ -3042,7 +3042,7 @@ __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRe
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
|
||||
{
|
||||
register uint32_t tmp = 0U;
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
tmp = (uint32_t)(&(RTCx->BKP0R));
|
||||
tmp += (BackupRegister * 4U);
|
||||
|
|
|
@ -301,7 +301,9 @@ typedef struct
|
|||
#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
|
||||
#define SDMMC_CARD_LOCKED 0x02000000U
|
||||
|
||||
#ifndef SDMMC_DATATIMEOUT
|
||||
#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
|
||||
#endif /* SDMMC_DATATIMEOUT */
|
||||
|
||||
#define SDMMC_0TO7BITS 0x000000FFU
|
||||
#define SDMMC_8TO15BITS 0x0000FF00U
|
||||
|
@ -455,7 +457,7 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDMMC_LL_Data_Length Data Lenght
|
||||
/** @defgroup SDMMC_LL_Data_Length Data Length
|
||||
* @{
|
||||
*/
|
||||
#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
|
||||
|
@ -984,6 +986,7 @@ uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
|
|||
uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
|
||||
uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
|
||||
uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
|
||||
uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
|
||||
uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
|
||||
|
|
|
@ -266,8 +266,8 @@ typedef struct
|
|||
/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
|
||||
* @{
|
||||
*/
|
||||
#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */
|
||||
#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */
|
||||
#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */
|
||||
#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -848,8 +848,8 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
|
||||
{
|
||||
register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
|
||||
register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
|
||||
uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
|
||||
uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
|
||||
return (Ssm | Ssoe);
|
||||
}
|
||||
|
||||
|
@ -1314,7 +1314,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t) & (SPIx->DR);
|
||||
return (uint32_t) &(SPIx->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1361,7 +1361,7 @@ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
|
|||
*spidr = TxData;
|
||||
#else
|
||||
*((__IO uint8_t *)&SPIx->DR) = TxData;
|
||||
#endif
|
||||
#endif /* __GNUC__ */
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1378,7 +1378,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
|
|||
*spidr = TxData;
|
||||
#else
|
||||
SPIx->DR = TxData;
|
||||
#endif
|
||||
#endif /* __GNUC__ */
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1500,10 +1500,10 @@ typedef struct
|
|||
/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
|
||||
* @{
|
||||
*/
|
||||
#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
|
||||
#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
|
||||
#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
|
||||
#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
|
||||
#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */
|
||||
#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */
|
||||
#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */
|
||||
#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -1838,7 +1838,7 @@ __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the master clock ouput (Pin MCK)
|
||||
* @brief Enable the master clock output (Pin MCK)
|
||||
* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
|
||||
* @param SPIx SPI Instance
|
||||
* @retval None
|
||||
|
@ -1849,7 +1849,7 @@ __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the master clock ouput (Pin MCK)
|
||||
* @brief Disable the master clock output (Pin MCK)
|
||||
* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
|
||||
* @param SPIx SPI Instance
|
||||
* @retval None
|
||||
|
@ -1860,7 +1860,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the master clock ouput (Pin MCK) is enabled
|
||||
* @brief Check if the master clock output (Pin MCK) is enabled
|
||||
* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
|
|
|
@ -570,8 +570,8 @@ typedef struct
|
|||
/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
|
||||
#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
|
||||
#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
|
||||
#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -581,8 +581,8 @@ typedef struct
|
|||
*/
|
||||
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
|
||||
#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
|
||||
/**
|
||||
* @}
|
||||
|
@ -1413,7 +1413,16 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
|
||||
uint32_t counter_mode;
|
||||
|
||||
counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
|
||||
|
||||
if (counter_mode == 0U)
|
||||
{
|
||||
counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
|
||||
}
|
||||
|
||||
return counter_mode;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1868,8 +1877,8 @@ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
|
||||
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
|
||||
(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
|
||||
|
@ -1913,8 +1922,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel,
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -1952,8 +1961,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -1986,7 +1995,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -2018,7 +2027,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -2055,7 +2064,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -2087,7 +2096,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel,
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -2112,8 +2121,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
|
||||
|
||||
}
|
||||
|
@ -2138,8 +2147,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
|
||||
|
||||
}
|
||||
|
@ -2164,9 +2173,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
|
||||
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
|
@ -2190,8 +2199,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
|
||||
}
|
||||
|
||||
|
@ -2215,8 +2224,8 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
|
||||
}
|
||||
|
||||
|
@ -2240,9 +2249,9 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
|
||||
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
|
@ -2269,8 +2278,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
|
||||
}
|
||||
|
||||
|
@ -2296,8 +2305,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
|
||||
}
|
||||
|
||||
|
@ -2325,9 +2334,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
|
||||
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
|
@ -2596,8 +2605,8 @@ __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t G
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
|
||||
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
|
||||
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
|
||||
|
@ -2624,8 +2633,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -2648,8 +2657,8 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
|
||||
}
|
||||
|
||||
|
@ -2674,8 +2683,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -2699,8 +2708,8 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel,
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
|
||||
}
|
||||
|
||||
|
@ -2737,8 +2746,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -2774,8 +2783,8 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
|
||||
}
|
||||
|
||||
|
@ -2803,7 +2812,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
|
||||
ICPolarity << SHIFT_TAB_CCxP[iChannel]);
|
||||
}
|
||||
|
@ -2831,7 +2840,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
|
||||
SHIFT_TAB_CCxP[iChannel]);
|
||||
}
|
||||
|
@ -3457,7 +3466,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
|
||||
{
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
|
||||
SET_BIT(*pReg, Source);
|
||||
}
|
||||
|
||||
|
@ -3480,7 +3489,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
|
||||
{
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
|
||||
CLEAR_BIT(*pReg, Source);
|
||||
}
|
||||
|
||||
|
@ -3507,7 +3516,7 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t
|
|||
__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
|
||||
uint32_t Polarity)
|
||||
{
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
|
||||
MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
|
||||
}
|
||||
#endif /* TIM_BREAK_INPUT_SUPPORT */
|
||||
|
|
|
@ -66,37 +66,44 @@ typedef struct
|
|||
|
||||
uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_USART_SetBaudRate().*/
|
||||
|
||||
uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_USART_SetDataWidth().*/
|
||||
|
||||
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref USART_LL_EC_STOPBITS.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_USART_SetStopBitsLength().*/
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref USART_LL_EC_PARITY.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_USART_SetParity().*/
|
||||
|
||||
uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_LL_EC_DIRECTION.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_USART_SetTransferDirection().*/
|
||||
|
||||
uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_USART_SetHWFlowCtrl().*/
|
||||
|
||||
uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
|
||||
This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_USART_SetOverSampling().*/
|
||||
|
||||
} LL_USART_InitTypeDef;
|
||||
|
||||
|
@ -115,20 +122,23 @@ typedef struct
|
|||
uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
|
||||
This parameter can be a value of @ref USART_LL_EC_POLARITY.
|
||||
|
||||
USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
|
||||
USART HW configuration can be modified afterwards using unitary
|
||||
functions @ref LL_USART_SetClockPolarity().
|
||||
For more details, refer to description of this function. */
|
||||
|
||||
uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref USART_LL_EC_PHASE.
|
||||
|
||||
USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
|
||||
USART HW configuration can be modified afterwards using unitary
|
||||
functions @ref LL_USART_SetClockPhase().
|
||||
For more details, refer to description of this function. */
|
||||
|
||||
uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
|
||||
|
||||
USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
|
||||
USART HW configuration can be modified afterwards using unitary
|
||||
functions @ref LL_USART_SetLastClkPulseOutput().
|
||||
For more details, refer to description of this function. */
|
||||
|
||||
} LL_USART_ClockInitTypeDef;
|
||||
|
@ -147,22 +157,24 @@ typedef struct
|
|||
* @brief Flags defines which can be used with LL_USART_WriteReg function
|
||||
* @{
|
||||
*/
|
||||
#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
|
||||
#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
|
||||
#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error detected flag */
|
||||
#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
|
||||
#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
|
||||
#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
|
||||
#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
|
||||
#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
|
||||
#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error detected clear flag */
|
||||
#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
|
||||
#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
|
||||
#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time flag */
|
||||
#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */
|
||||
#endif /* USART_TCBGT_SUPPORT */
|
||||
#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */
|
||||
#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */
|
||||
#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */
|
||||
#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */
|
||||
#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */
|
||||
#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */
|
||||
#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
|
||||
#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */
|
||||
#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */
|
||||
#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
|
||||
#if defined(USART_CR1_UESM)
|
||||
#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
|
||||
#endif /* USART_CR3_WUFIE */
|
||||
#endif /* USART_CR1_UESM */
|
||||
/**
|
||||
* @}
|
||||
|
@ -192,7 +204,9 @@ typedef struct
|
|||
#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
|
||||
#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
|
||||
#endif /* USART_CR3_WUFIE */
|
||||
#endif /* USART_CR1_UESM */
|
||||
#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
|
||||
#if defined(USART_ISR_REACK)
|
||||
|
@ -221,7 +235,9 @@ typedef struct
|
|||
#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
|
||||
#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
|
||||
#endif /* USART_CR3_WUFIE */
|
||||
#endif /* USART_CR1_UESM */
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */
|
||||
|
@ -406,6 +422,7 @@ typedef struct
|
|||
*/
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUS)
|
||||
/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
|
||||
* @{
|
||||
*/
|
||||
|
@ -416,6 +433,7 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USART_CR3_WUS */
|
||||
#endif /* USART_CR1_UESM */
|
||||
/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
|
||||
* @{
|
||||
|
@ -568,7 +586,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
|
|||
* @brief USART enabled in STOP Mode.
|
||||
* @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
|
||||
* USART clock selection is HSI or LSE in RCC.
|
||||
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Wake-up from Stop mode feature is supported by the USARTx instance.
|
||||
* @rmtoll CR1 UESM LL_USART_EnableInStopMode
|
||||
* @param USARTx USART Instance
|
||||
|
@ -582,7 +600,7 @@ __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
|
|||
/**
|
||||
* @brief USART disabled in STOP Mode.
|
||||
* @note When this function is disabled, USART is not able to wake up the MCU from Stop mode
|
||||
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Wake-up from Stop mode feature is supported by the USARTx instance.
|
||||
* @rmtoll CR1 UESM LL_USART_DisableInStopMode
|
||||
* @param USARTx USART Instance
|
||||
|
@ -595,7 +613,7 @@ __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
|
||||
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Wake-up from Stop mode feature is supported by the USARTx instance.
|
||||
* @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode
|
||||
* @param USARTx USART Instance
|
||||
|
@ -876,7 +894,7 @@ __STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
|
||||
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Synchronous mode is supported by the USARTx instance.
|
||||
* @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
|
||||
* @param USARTx USART Instance
|
||||
|
@ -893,7 +911,7 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3
|
|||
/**
|
||||
* @brief Retrieve Clock pulse of the last data bit output configuration
|
||||
* (Last bit Clock pulse output to the SCLK pin or not)
|
||||
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Synchronous mode is supported by the USARTx instance.
|
||||
* @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
|
||||
* @param USARTx USART Instance
|
||||
|
@ -908,7 +926,7 @@ __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Select the phase of the clock output on the SCLK pin in synchronous mode
|
||||
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Synchronous mode is supported by the USARTx instance.
|
||||
* @rmtoll CR2 CPHA LL_USART_SetClockPhase
|
||||
* @param USARTx USART Instance
|
||||
|
@ -924,7 +942,7 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc
|
|||
|
||||
/**
|
||||
* @brief Return phase of the clock output on the SCLK pin in synchronous mode
|
||||
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Synchronous mode is supported by the USARTx instance.
|
||||
* @rmtoll CR2 CPHA LL_USART_GetClockPhase
|
||||
* @param USARTx USART Instance
|
||||
|
@ -939,7 +957,7 @@ __STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
|
||||
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Synchronous mode is supported by the USARTx instance.
|
||||
* @rmtoll CR2 CPOL LL_USART_SetClockPolarity
|
||||
* @param USARTx USART Instance
|
||||
|
@ -955,7 +973,7 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C
|
|||
|
||||
/**
|
||||
* @brief Return polarity of the clock output on the SCLK pin in synchronous mode
|
||||
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Synchronous mode is supported by the USARTx instance.
|
||||
* @rmtoll CR2 CPOL LL_USART_GetClockPolarity
|
||||
* @param USARTx USART Instance
|
||||
|
@ -970,7 +988,7 @@ __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
|
||||
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Synchronous mode is supported by the USARTx instance.
|
||||
* @note Call of this function is equivalent to following function call sequence :
|
||||
* - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
|
||||
|
@ -998,7 +1016,7 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase,
|
|||
|
||||
/**
|
||||
* @brief Enable Clock output on SCLK pin
|
||||
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Synchronous mode is supported by the USARTx instance.
|
||||
* @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1011,7 +1029,7 @@ __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Disable Clock output on SCLK pin
|
||||
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Synchronous mode is supported by the USARTx instance.
|
||||
* @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1024,7 +1042,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Indicate if Clock output on SCLK pin is enabled
|
||||
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Synchronous mode is supported by the USARTx instance.
|
||||
* @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1243,7 +1261,7 @@ __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Enable Auto Baud-Rate Detection
|
||||
* @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Auto Baud Rate detection feature is supported by the USARTx instance.
|
||||
* @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1256,7 +1274,7 @@ __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Disable Auto Baud-Rate Detection
|
||||
* @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Auto Baud Rate detection feature is supported by the USARTx instance.
|
||||
* @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1269,7 +1287,7 @@ __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Indicate if Auto Baud-Rate Detection mechanism is enabled
|
||||
* @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Auto Baud Rate detection feature is supported by the USARTx instance.
|
||||
* @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1282,7 +1300,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Set Auto Baud-Rate mode bits
|
||||
* @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Auto Baud Rate detection feature is supported by the USARTx instance.
|
||||
* @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1300,7 +1318,7 @@ __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_
|
|||
|
||||
/**
|
||||
* @brief Return Auto Baud-Rate mode
|
||||
* @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Auto Baud Rate detection feature is supported by the USARTx instance.
|
||||
* @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1407,7 +1425,7 @@ __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Enable RTS HW Flow Control
|
||||
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Hardware Flow control feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1420,7 +1438,7 @@ __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Disable RTS HW Flow Control
|
||||
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Hardware Flow control feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1433,7 +1451,7 @@ __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Enable CTS HW Flow Control
|
||||
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Hardware Flow control feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1446,7 +1464,7 @@ __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Disable CTS HW Flow Control
|
||||
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Hardware Flow control feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1459,7 +1477,7 @@ __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Configure HW Flow Control mode (both CTS and RTS)
|
||||
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Hardware Flow control feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
|
||||
* CR3 CTSE LL_USART_SetHWFlowCtrl
|
||||
|
@ -1478,7 +1496,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard
|
|||
|
||||
/**
|
||||
* @brief Return HW Flow Control configuration (both CTS and RTS)
|
||||
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Hardware Flow control feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
|
||||
* CR3 CTSE LL_USART_GetHWFlowCtrl
|
||||
|
@ -1561,9 +1579,10 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
|
|||
}
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUS)
|
||||
/**
|
||||
* @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
|
||||
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Wake-up from Stop mode feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 WUS LL_USART_SetWKUPType
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1580,7 +1599,7 @@ __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
|
|||
|
||||
/**
|
||||
* @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
|
||||
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Wake-up from Stop mode feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 WUS LL_USART_GetWKUPType
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1594,6 +1613,7 @@ __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
|
|||
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
|
||||
}
|
||||
|
||||
#endif /* USART_CR3_WUS */
|
||||
#endif /* USART_CR1_UESM */
|
||||
/**
|
||||
* @brief Configure USART BRR register for achieving expected Baud Rate value.
|
||||
|
@ -1615,7 +1635,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph
|
|||
uint32_t BaudRate)
|
||||
{
|
||||
uint32_t usartdiv;
|
||||
register uint32_t brrtemp;
|
||||
uint32_t brrtemp;
|
||||
|
||||
if (OverSampling == LL_USART_OVERSAMPLING_8)
|
||||
{
|
||||
|
@ -1645,8 +1665,8 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
|
||||
{
|
||||
register uint32_t usartdiv;
|
||||
register uint32_t brrresult = 0x0U;
|
||||
uint32_t usartdiv;
|
||||
uint32_t brrresult = 0x0U;
|
||||
|
||||
usartdiv = USARTx->BRR;
|
||||
|
||||
|
@ -1728,7 +1748,7 @@ __STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Enable IrDA mode
|
||||
* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
|
||||
* IrDA feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 IREN LL_USART_EnableIrda
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1741,7 +1761,7 @@ __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Disable IrDA mode
|
||||
* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
|
||||
* IrDA feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 IREN LL_USART_DisableIrda
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1754,7 +1774,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Indicate if IrDA mode is enabled
|
||||
* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
|
||||
* IrDA feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 IREN LL_USART_IsEnabledIrda
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1767,7 +1787,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Configure IrDA Power Mode (Normal or Low Power)
|
||||
* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
|
||||
* IrDA feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1783,7 +1803,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P
|
|||
|
||||
/**
|
||||
* @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
|
||||
* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
|
||||
* IrDA feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1799,7 +1819,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
|
|||
/**
|
||||
* @brief Set Irda prescaler value, used for dividing the USART clock source
|
||||
* to achieve the Irda Low Power frequency (8 bits value)
|
||||
* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
|
||||
* IrDA feature is supported by the USARTx instance.
|
||||
* @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1814,7 +1834,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t P
|
|||
/**
|
||||
* @brief Return Irda prescaler value, used for dividing the USART clock source
|
||||
* to achieve the Irda Low Power frequency (8 bits value)
|
||||
* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
|
||||
* IrDA feature is supported by the USARTx instance.
|
||||
* @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1835,7 +1855,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Enable Smartcard NACK transmission
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1848,7 +1868,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Disable Smartcard NACK transmission
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1861,7 +1881,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Indicate if Smartcard NACK transmission is enabled
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1874,7 +1894,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Enable Smartcard mode
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 SCEN LL_USART_EnableSmartcard
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1887,7 +1907,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Disable Smartcard mode
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 SCEN LL_USART_DisableSmartcard
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1900,7 +1920,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Indicate if Smartcard mode is enabled
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1913,7 +1933,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
|
||||
* In transmission mode, it specifies the number of automatic retransmission retries, before
|
||||
|
@ -1932,7 +1952,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx,
|
|||
|
||||
/**
|
||||
* @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1946,7 +1966,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USAR
|
|||
/**
|
||||
* @brief Set Smartcard prescaler value, used for dividing the USART clock
|
||||
* source to provide the SMARTCARD Clock (5 bits value)
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1961,7 +1981,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint3
|
|||
/**
|
||||
* @brief Return Smartcard prescaler value, used for dividing the USART clock
|
||||
* source to provide the SMARTCARD Clock (5 bits value)
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1975,7 +1995,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
|
|||
/**
|
||||
* @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
|
||||
* (GT[7:0] bits : Guard time value)
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
|
||||
* @param USARTx USART Instance
|
||||
|
@ -1990,7 +2010,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3
|
|||
/**
|
||||
* @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
|
||||
* (GT[7:0] bits : Guard time value)
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2011,7 +2031,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Enable Single Wire Half-Duplex mode
|
||||
* @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Half-Duplex mode is supported by the USARTx instance.
|
||||
* @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2024,7 +2044,7 @@ __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Disable Single Wire Half-Duplex mode
|
||||
* @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Half-Duplex mode is supported by the USARTx instance.
|
||||
* @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2037,7 +2057,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Indicate if Single Wire Half-Duplex mode is enabled
|
||||
* @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Half-Duplex mode is supported by the USARTx instance.
|
||||
* @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2058,7 +2078,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Set LIN Break Detection Length
|
||||
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* LIN feature is supported by the USARTx instance.
|
||||
* @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2074,7 +2094,7 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3
|
|||
|
||||
/**
|
||||
* @brief Return LIN Break Detection Length
|
||||
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* LIN feature is supported by the USARTx instance.
|
||||
* @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2089,7 +2109,7 @@ __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Enable LIN mode
|
||||
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* LIN feature is supported by the USARTx instance.
|
||||
* @rmtoll CR2 LINEN LL_USART_EnableLIN
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2102,7 +2122,7 @@ __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Disable LIN mode
|
||||
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* LIN feature is supported by the USARTx instance.
|
||||
* @rmtoll CR2 LINEN LL_USART_DisableLIN
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2115,7 +2135,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Indicate if LIN mode is enabled
|
||||
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* LIN feature is supported by the USARTx instance.
|
||||
* @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2136,7 +2156,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
|
||||
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Driver Enable feature is supported by the USARTx instance.
|
||||
* @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2150,7 +2170,7 @@ __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32
|
|||
|
||||
/**
|
||||
* @brief Return DEDT (Driver Enable De-Assertion Time)
|
||||
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Driver Enable feature is supported by the USARTx instance.
|
||||
* @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2163,7 +2183,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
|
||||
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Driver Enable feature is supported by the USARTx instance.
|
||||
* @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2177,7 +2197,7 @@ __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t
|
|||
|
||||
/**
|
||||
* @brief Return DEAT (Driver Enable Assertion Time)
|
||||
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Driver Enable feature is supported by the USARTx instance.
|
||||
* @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2190,7 +2210,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Enable Driver Enable (DE) Mode
|
||||
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Driver Enable feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 DEM LL_USART_EnableDEMode
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2203,7 +2223,7 @@ __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Disable Driver Enable (DE) Mode
|
||||
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Driver Enable feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 DEM LL_USART_DisableDEMode
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2216,7 +2236,7 @@ __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Indicate if Driver Enable (DE) Mode is enabled
|
||||
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Driver Enable feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 DEM LL_USART_IsEnabledDEMode
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2229,7 +2249,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Select Driver Enable Polarity
|
||||
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Driver Enable feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 DEP LL_USART_SetDESignalPolarity
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2245,7 +2265,7 @@ __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_
|
|||
|
||||
/**
|
||||
* @brief Return Driver Enable Polarity
|
||||
* @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Driver Enable feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 DEP LL_USART_GetDESignalPolarity
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2309,7 +2329,7 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
|
|||
* - IREN bit in the USART_CR3 register,
|
||||
* - HDSEL bit in the USART_CR3 register.
|
||||
* This function also sets the USART in Synchronous mode.
|
||||
* @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Synchronous mode is supported by the USARTx instance.
|
||||
* @note Call of this function is equivalent to following function call sequence :
|
||||
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
|
||||
|
@ -2348,7 +2368,7 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
|
|||
* - IREN bit in the USART_CR3 register,
|
||||
* - HDSEL bit in the USART_CR3 register.
|
||||
* This function also set the UART/USART in LIN mode.
|
||||
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* LIN feature is supported by the USARTx instance.
|
||||
* @note Call of this function is equivalent to following function call sequence :
|
||||
* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
|
||||
|
@ -2389,7 +2409,7 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
|
|||
* - SCEN bit in the USART_CR3 register,
|
||||
* - IREN bit in the USART_CR3 register,
|
||||
* This function also sets the UART/USART in Half Duplex mode.
|
||||
* @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Half-Duplex mode is supported by the USARTx instance.
|
||||
* @note Call of this function is equivalent to following function call sequence :
|
||||
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
|
||||
|
@ -2429,7 +2449,7 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
|
|||
* This function also configures Stop bits to 1.5 bits and
|
||||
* sets the USART in Smartcard mode (SCEN bit).
|
||||
* Clock Output is also enabled (CLKEN).
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @note Call of this function is equivalent to following function call sequence :
|
||||
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
|
||||
|
@ -2472,7 +2492,7 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
|
|||
* - SCEN bit in the USART_CR3 register,
|
||||
* - HDSEL bit in the USART_CR3 register.
|
||||
* This function also sets the UART/USART in IRDA mode (IREN bit).
|
||||
* @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
|
||||
* IrDA feature is supported by the USARTx instance.
|
||||
* @note Call of this function is equivalent to following function call sequence :
|
||||
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
|
||||
|
@ -2640,7 +2660,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Check if the USART LIN Break Detection Flag is set or not
|
||||
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* LIN feature is supported by the USARTx instance.
|
||||
* @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2653,7 +2673,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Check if the USART CTS interrupt Flag is set or not
|
||||
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Hardware Flow control feature is supported by the USARTx instance.
|
||||
* @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2666,7 +2686,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Check if the USART CTS Flag is set or not
|
||||
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Hardware Flow control feature is supported by the USARTx instance.
|
||||
* @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2690,7 +2710,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Check if the USART End Of Block Flag is set or not
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2703,7 +2723,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Check if the USART Auto-Baud Rate Error Flag is set or not
|
||||
* @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Auto Baud Rate detection feature is supported by the USARTx instance.
|
||||
* @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2716,7 +2736,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Check if the USART Auto-Baud Rate Flag is set or not
|
||||
* @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Auto Baud Rate detection feature is supported by the USARTx instance.
|
||||
* @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2772,9 +2792,10 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
|
|||
}
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
/**
|
||||
* @brief Check if the USART Wake Up from stop mode Flag is set or not
|
||||
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Wake-up from Stop mode feature is supported by the USARTx instance.
|
||||
* @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2785,6 +2806,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
|
|||
return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
#endif /* USART_CR3_WUFIE */
|
||||
#endif /* USART_CR1_UESM */
|
||||
/**
|
||||
* @brief Check if the USART Transmit Enable Acknowledge Flag is set or not
|
||||
|
@ -2906,7 +2928,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Clear LIN Break Detection Flag
|
||||
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* LIN feature is supported by the USARTx instance.
|
||||
* @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2919,7 +2941,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Clear CTS Interrupt Flag
|
||||
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Hardware Flow control feature is supported by the USARTx instance.
|
||||
* @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2943,7 +2965,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Clear End Of Block Flag
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2966,9 +2988,10 @@ __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
|
|||
}
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
/**
|
||||
* @brief Clear Wake Up from stop mode Flag
|
||||
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Wake-up from Stop mode feature is supported by the USARTx instance.
|
||||
* @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP
|
||||
* @param USARTx USART Instance
|
||||
|
@ -2979,6 +3002,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
|
|||
WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
|
||||
}
|
||||
|
||||
#endif /* USART_CR3_WUFIE */
|
||||
#endif /* USART_CR1_UESM */
|
||||
/**
|
||||
* @}
|
||||
|
@ -3067,7 +3091,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Enable End Of Block Interrupt
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB
|
||||
* @param USARTx USART Instance
|
||||
|
@ -3080,7 +3104,7 @@ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Enable LIN Break Detection Interrupt
|
||||
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* LIN feature is supported by the USARTx instance.
|
||||
* @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
|
||||
* @param USARTx USART Instance
|
||||
|
@ -3108,7 +3132,7 @@ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Enable CTS Interrupt
|
||||
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Hardware Flow control feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
|
||||
* @param USARTx USART Instance
|
||||
|
@ -3120,9 +3144,10 @@ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
|
|||
}
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
/**
|
||||
* @brief Enable Wake Up from Stop Mode Interrupt
|
||||
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Wake-up from Stop mode feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP
|
||||
* @param USARTx USART Instance
|
||||
|
@ -3133,12 +3158,13 @@ __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
|
|||
SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
|
||||
}
|
||||
|
||||
#endif /* USART_CR3_WUFIE */
|
||||
#endif /* USART_CR1_UESM */
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
|
||||
/**
|
||||
* @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT
|
||||
* @param USARTx USART Instance
|
||||
|
@ -3229,7 +3255,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Disable End Of Block Interrupt
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB
|
||||
* @param USARTx USART Instance
|
||||
|
@ -3242,7 +3268,7 @@ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Disable LIN Break Detection Interrupt
|
||||
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* LIN feature is supported by the USARTx instance.
|
||||
* @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
|
||||
* @param USARTx USART Instance
|
||||
|
@ -3270,7 +3296,7 @@ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Disable CTS Interrupt
|
||||
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Hardware Flow control feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
|
||||
* @param USARTx USART Instance
|
||||
|
@ -3282,9 +3308,10 @@ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
|
|||
}
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
/**
|
||||
* @brief Disable Wake Up from Stop Mode Interrupt
|
||||
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Wake-up from Stop mode feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP
|
||||
* @param USARTx USART Instance
|
||||
|
@ -3295,12 +3322,13 @@ __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
|
|||
CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
|
||||
}
|
||||
|
||||
#endif /* USART_CR3_WUFIE */
|
||||
#endif /* USART_CR1_UESM */
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
|
||||
/**
|
||||
* @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT
|
||||
* @param USARTx USART Instance
|
||||
|
@ -3391,7 +3419,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Check if the USART End Of Block Interrupt is enabled or disabled.
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB
|
||||
* @param USARTx USART Instance
|
||||
|
@ -3404,7 +3432,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
|
||||
* @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
|
||||
* LIN feature is supported by the USARTx instance.
|
||||
* @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
|
||||
* @param USARTx USART Instance
|
||||
|
@ -3428,7 +3456,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Check if the USART CTS Interrupt is enabled or disabled.
|
||||
* @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Hardware Flow control feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
|
||||
* @param USARTx USART Instance
|
||||
|
@ -3440,9 +3468,10 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
|
|||
}
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
/**
|
||||
* @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
|
||||
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Wake-up from Stop mode feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP
|
||||
* @param USARTx USART Instance
|
||||
|
@ -3453,12 +3482,13 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
|
|||
return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
#endif /* USART_CR3_WUFIE */
|
||||
#endif /* USART_CR1_UESM */
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
|
||||
/**
|
||||
* @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT
|
||||
* @param USARTx USART Instance
|
||||
|
@ -3589,7 +3619,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
|
||||
{
|
||||
register uint32_t data_reg_addr;
|
||||
uint32_t data_reg_addr;
|
||||
|
||||
if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
|
||||
{
|
||||
|
@ -3669,7 +3699,7 @@ __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Valu
|
|||
|
||||
/**
|
||||
* @brief Request an Automatic Baud Rate measurement on next received data frame
|
||||
* @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Auto Baud Rate detection feature is supported by the USARTx instance.
|
||||
* @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate
|
||||
* @param USARTx USART Instance
|
||||
|
@ -3717,7 +3747,7 @@ __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
|
|||
|
||||
/**
|
||||
* @brief Request a Transmit data flush
|
||||
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
|
||||
* Smartcard feature is supported by the USARTx instance.
|
||||
* @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush
|
||||
* @param USARTx USART Instance
|
||||
|
|
|
@ -81,7 +81,7 @@ typedef enum
|
|||
} USB_OTG_HCStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief USB OTG Initialization Structure definition
|
||||
* @brief USB Instance Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
@ -94,14 +94,14 @@ typedef struct
|
|||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint32_t speed; /*!< USB Core speed.
|
||||
This parameter can be any value of @ref USB_Core_Speed_ */
|
||||
This parameter can be any value of @ref USB_Core_Speed */
|
||||
|
||||
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
|
||||
|
||||
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
|
||||
|
||||
uint32_t phy_itface; /*!< Select the used PHY interface.
|
||||
This parameter can be any value of @ref USB_Core_PHY_ */
|
||||
This parameter can be any value of @ref USB_Core_PHY */
|
||||
|
||||
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
|
||||
|
||||
|
@ -116,6 +116,7 @@ typedef struct
|
|||
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
|
||||
|
||||
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
|
||||
|
||||
} USB_OTG_CfgTypeDef;
|
||||
|
||||
typedef struct
|
||||
|
@ -185,6 +186,8 @@ typedef struct
|
|||
|
||||
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
|
||||
|
||||
uint32_t XferSize; /*!< OTG Channel transfer size. */
|
||||
|
||||
uint32_t xfer_len; /*!< Current transfer length. */
|
||||
|
||||
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
|
||||
|
@ -197,13 +200,13 @@ typedef struct
|
|||
|
||||
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
|
||||
|
||||
uint32_t ErrCnt; /*!< Host channel error count.*/
|
||||
uint32_t ErrCnt; /*!< Host channel error count. */
|
||||
|
||||
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
|
||||
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
|
||||
|
||||
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
|
||||
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
|
||||
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
|
||||
} USB_OTG_HCTypeDef;
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
|
@ -318,10 +321,10 @@ typedef struct
|
|||
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
|
||||
* @{
|
||||
*/
|
||||
#define DEP0CTL_MPS_64 0U
|
||||
#define DEP0CTL_MPS_32 1U
|
||||
#define DEP0CTL_MPS_16 2U
|
||||
#define DEP0CTL_MPS_8 3U
|
||||
#define EP_MPS_64 0U
|
||||
#define EP_MPS_32 1U
|
||||
#define EP_MPS_16 2U
|
||||
#define EP_MPS_8 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -408,7 +411,7 @@ typedef struct
|
|||
#define USBPHYC ((USBPHYC_GlobalTypeDef *)((uint32_t )USB_PHY_HS_CONTROLLER_BASE))
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
#define EP_ADDR_MSK 0xFU
|
||||
#define EP_ADDR_MSK 0xFU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -448,7 +451,9 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB
|
|||
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
|
||||
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
|
||||
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
|
||||
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
|
||||
uint8_t ch_ep_num, uint16_t len, uint8_t dma);
|
||||
|
||||
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
|
||||
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
|
@ -476,7 +481,9 @@ uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
|
|||
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
|
||||
uint8_t epnum, uint8_t dev_address, uint8_t speed,
|
||||
uint8_t ep_type, uint16_t mps);
|
||||
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
|
||||
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
|
||||
USB_OTG_HCTypeDef *hc, uint8_t dma);
|
||||
|
||||
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
|
||||
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
|
||||
|
|
|
@ -275,6 +275,7 @@ void LL_mDelay(uint32_t Delay);
|
|||
*/
|
||||
|
||||
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
|
||||
ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
|
||||
|
|
|
@ -50,11 +50,11 @@
|
|||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief STM32F7xx HAL Driver version number V1.2.8
|
||||
* @brief STM32F7xx HAL Driver version number V1.2.9
|
||||
*/
|
||||
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __STM32F7xx_HAL_VERSION_SUB2 (0x08) /*!< [15:8] sub2 version */
|
||||
#define __STM32F7xx_HAL_VERSION_SUB2 (0x09) /*!< [15:8] sub2 version */
|
||||
#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
|
||||
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
* @file stm32f7xx_hal_adc.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
|
||||
* functionalities of the Analog to Digital Converter (ADC) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
* + State and errors functions
|
||||
|
@ -825,6 +825,14 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
|
|||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Set ADC error code to ADC IP internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
@ -916,13 +924,17 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
|
|||
{
|
||||
if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
|
||||
{
|
||||
/* Update ADC state machine to timeout */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
|
||||
{
|
||||
/* Update ADC state machine to timeout */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -987,13 +999,17 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
|
|||
{
|
||||
if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
|
||||
{
|
||||
/* Update ADC state machine to timeout */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
|
||||
{
|
||||
/* Update ADC state machine to timeout */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -1131,6 +1147,14 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
|
|||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Set ADC error code to ADC IP internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
@ -1463,6 +1487,14 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
|
|||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Set ADC error code to ADC IP internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
@ -1496,7 +1528,17 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
|
|||
|
||||
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
|
||||
/* DMA transfer is on going) */
|
||||
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
|
||||
if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
|
||||
{
|
||||
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
|
||||
|
||||
/* Check if DMA channel effectively disabled */
|
||||
if (tmp_hal_status != HAL_OK)
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable ADC overrun interrupt */
|
||||
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
|
||||
|
@ -1574,7 +1616,7 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
|
|||
/**
|
||||
* @brief Error ADC callback.
|
||||
* @note In case of error due to overrun when using ADC with DMA transfer
|
||||
* (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
|
||||
* (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
|
||||
* - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
|
||||
* - If needed, restart a new ADC conversion using function
|
||||
* "HAL_ADC_Start_DMA()"
|
||||
|
|
|
@ -221,6 +221,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
|
|||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Set ADC error code to ADC IP internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
@ -313,6 +321,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
|
|||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Set ADC error code to ADC IP internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
@ -399,10 +415,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
|
|||
{
|
||||
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
|
||||
{
|
||||
hadc->State= HAL_ADC_STATE_TIMEOUT;
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
return HAL_TIMEOUT;
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
|
||||
{
|
||||
hadc->State= HAL_ADC_STATE_TIMEOUT;
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -666,6 +686,14 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
|
|||
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Set ADC error code to ADC IP internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
|
|
@ -120,7 +120,7 @@
|
|||
submitted (the sleep mode is not yet entered), and become
|
||||
HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective.
|
||||
|
||||
(#) The wake-up from sleep mode can be trigged by two ways:
|
||||
(#) The wake-up from sleep mode can be triggered by two ways:
|
||||
(++) Using HAL_CAN_WakeUp(). When returning from this function,
|
||||
the sleep mode is exited (if return status is HAL_OK).
|
||||
(++) When a start of Rx CAN frame is detected by the CAN peripheral,
|
||||
|
@ -1901,7 +1901,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
|
|||
/* Check if message is still pending */
|
||||
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
|
||||
{
|
||||
/* Receive FIFO 0 mesage pending Callback */
|
||||
/* Receive FIFO 0 message pending Callback */
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
/* Call registered callback*/
|
||||
hcan->RxFifo0MsgPendingCallback(hcan);
|
||||
|
@ -1950,7 +1950,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
|
|||
/* Check if message is still pending */
|
||||
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
|
||||
{
|
||||
/* Receive FIFO 1 mesage pending Callback */
|
||||
/* Receive FIFO 1 message pending Callback */
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
/* Call registered callback*/
|
||||
hcan->RxFifo1MsgPendingCallback(hcan);
|
||||
|
|
|
@ -822,19 +822,15 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
|
|||
/* CEC TX byte request interrupt ------------------------------------------------*/
|
||||
if ((reg & CEC_FLAG_TXBR) != 0U)
|
||||
{
|
||||
--hcec->TxXferCount;
|
||||
if (hcec->TxXferCount == 0U)
|
||||
{
|
||||
/* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
|
||||
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
|
||||
hcec->Instance->TXDR = *hcec->pTxBuffPtr;
|
||||
hcec->pTxBuffPtr++;
|
||||
}
|
||||
else
|
||||
{
|
||||
hcec->Instance->TXDR = *hcec->pTxBuffPtr;
|
||||
hcec->pTxBuffPtr++;
|
||||
hcec->TxXferCount--;
|
||||
}
|
||||
/* In all cases transmit the byte */
|
||||
hcec->Instance->TXDR = *hcec->pTxBuffPtr;
|
||||
hcec->pTxBuffPtr++;
|
||||
/* clear Tx-Byte request flag */
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
|
||||
}
|
||||
|
|
|
@ -11,7 +11,7 @@
|
|||
##### How to use this driver #####
|
||||
================================================================================
|
||||
[..]
|
||||
(+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
|
||||
(+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
|
||||
(+) Configure Input or Output data inversion
|
||||
|
||||
@endverbatim
|
||||
|
|
|
@ -586,6 +586,8 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD
|
|||
hcryp->Init.HeaderSize = pConf->HeaderSize;
|
||||
hcryp->Init.B0 = pConf->B0;
|
||||
hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
|
||||
hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
|
||||
hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
|
||||
|
||||
/* Set the key size(This bit field is don’t care in the DES or TDES modes) data type, AlgoMode and operating mode*/
|
||||
#if defined (CRYP)
|
||||
|
@ -660,7 +662,9 @@ HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD
|
|||
pConf->Header = hcryp->Init.Header ;
|
||||
pConf->HeaderSize = hcryp->Init.HeaderSize;
|
||||
pConf->B0 = hcryp->Init.B0;
|
||||
pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
|
||||
pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
|
||||
pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
|
||||
pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hcryp);
|
||||
|
@ -692,8 +696,8 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
|
|||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcryp);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_MspInit could be implemented in the user file
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_MspInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
@ -708,8 +712,8 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
|
|||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcryp);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_MspDeInit could be implemented in the user file
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_MspDeInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
@ -2157,8 +2161,8 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
|
|||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcryp);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_InCpltCallback could be implemented in the user file
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_InCpltCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
@ -2173,8 +2177,8 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
|
|||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcryp);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_OutCpltCallback could be implemented in the user file
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_OutCpltCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
@ -5534,17 +5538,17 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
|
|||
hcryp->CrypInCount++;
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
|
||||
hcryp->CrypInCount++;
|
||||
if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
|
||||
{
|
||||
/* Call Input transfer complete callback */
|
||||
if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
|
||||
{
|
||||
/* Call Input transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
#else
|
||||
/*Call legacy weak Input complete callback*/
|
||||
HAL_CRYP_InCpltCallback(hcryp);
|
||||
/*Call legacy weak Input complete callback*/
|
||||
HAL_CRYP_InCpltCallback(hcryp);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
}
|
||||
else /* Last block of payload < 128bit*/
|
||||
{
|
||||
|
@ -5593,10 +5597,24 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
|
|||
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
|
||||
{
|
||||
uint32_t loopcounter;
|
||||
uint32_t size_in_bytes;
|
||||
uint32_t tmp;
|
||||
uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
|
||||
0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
|
||||
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
|
||||
|
||||
/***************************** Header phase for GCM/GMAC or CCM *********************************/
|
||||
|
||||
if ((hcryp->Init.HeaderSize != 0U))
|
||||
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
|
||||
{
|
||||
size_in_bytes = hcryp->Init.HeaderSize * 4U;
|
||||
}
|
||||
else
|
||||
{
|
||||
size_in_bytes = hcryp->Init.HeaderSize;
|
||||
}
|
||||
|
||||
if (size_in_bytes != 0U)
|
||||
{
|
||||
|
||||
#if defined(CRYP)
|
||||
|
@ -5607,10 +5625,10 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
|
|||
/* Enable the CRYP peripheral */
|
||||
__HAL_CRYP_ENABLE(hcryp);
|
||||
|
||||
if ((hcryp->Init.HeaderSize % 4U) == 0U)
|
||||
if ((size_in_bytes % 16U) == 0U)
|
||||
{
|
||||
/* HeaderSize %4, no padding */
|
||||
for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
|
||||
for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
|
@ -5640,7 +5658,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
|
|||
else
|
||||
{
|
||||
/*Write header block in the IN FIFO without last block */
|
||||
for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
|
||||
for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
|
@ -5667,16 +5685,34 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
|
|||
}
|
||||
}
|
||||
/* Last block optionally pad the data with zeros*/
|
||||
for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
|
||||
for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
|
||||
{
|
||||
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
}
|
||||
while (loopcounter < 4U)
|
||||
/* If the header size is a multiple of words */
|
||||
if ((size_in_bytes % 4U) == 0U)
|
||||
{
|
||||
/* pad the data with zeros to have a complete block */
|
||||
hcryp->Instance->DIN = 0x0U;
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enter last bytes, padded with zeroes */
|
||||
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
|
||||
hcryp->Instance->DIN = tmp;
|
||||
loopcounter++;
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
/* Wait for CCF IFEM to be raised */
|
||||
if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
|
||||
|
@ -5722,10 +5758,11 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
|
|||
__HAL_CRYP_ENABLE(hcryp);
|
||||
|
||||
}
|
||||
if ((hcryp->Init.HeaderSize % 4U) == 0U)
|
||||
/* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */
|
||||
if ((size_in_bytes % 16U) == 0U)
|
||||
{
|
||||
/* HeaderSize %4, no padding */
|
||||
for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
|
||||
/* No padding */
|
||||
for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
|
||||
{
|
||||
/* Write the input block in the data input register */
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
|
@ -5757,7 +5794,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
|
|||
else
|
||||
{
|
||||
/*Write header block in the IN FIFO without last block */
|
||||
for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
|
||||
for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
|
||||
{
|
||||
/* Write the input block in the data input register */
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
|
@ -5785,17 +5822,35 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
|
|||
/* Clear CCF flag */
|
||||
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
|
||||
}
|
||||
/* Last block optionally pad the data with zeros*/
|
||||
for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
|
||||
/* Write last complete words */
|
||||
for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
|
||||
{
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
}
|
||||
while (loopcounter < 4U)
|
||||
/* If the header size is a multiple of words */
|
||||
if ((size_in_bytes % 4U) == 0U)
|
||||
{
|
||||
/*Pad the data with zeros to have a complete block */
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enter last bytes, padded with zeroes */
|
||||
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
|
||||
hcryp->Instance->DINR = tmp;
|
||||
loopcounter++;
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
|
||||
if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
|
||||
|
@ -5846,9 +5901,23 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
|
|||
{
|
||||
__IO uint32_t count = 0U;
|
||||
uint32_t loopcounter;
|
||||
uint32_t headersize_in_bytes;
|
||||
uint32_t tmp;
|
||||
uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
|
||||
0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
|
||||
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
|
||||
|
||||
/***************************** Header phase for GCM/GMAC or CCM *********************************/
|
||||
if ((hcryp->Init.HeaderSize != 0U))
|
||||
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
|
||||
{
|
||||
headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
|
||||
}
|
||||
else
|
||||
{
|
||||
headersize_in_bytes = hcryp->Init.HeaderSize;
|
||||
}
|
||||
|
||||
if (headersize_in_bytes != 0U)
|
||||
{
|
||||
|
||||
#if defined(CRYP)
|
||||
|
@ -5859,10 +5928,10 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
|
|||
/* Enable the CRYP peripheral */
|
||||
__HAL_CRYP_ENABLE(hcryp);
|
||||
|
||||
if ((hcryp->Init.HeaderSize % 4U) == 0U)
|
||||
if ((headersize_in_bytes % 16U) == 0U)
|
||||
{
|
||||
/* HeaderSize %4, no padding */
|
||||
for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
|
||||
for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
|
@ -5897,7 +5966,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
|
|||
else
|
||||
{
|
||||
/*Write header block in the IN FIFO without last block */
|
||||
for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
|
||||
for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
|
@ -5929,16 +5998,34 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
|
|||
} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
|
||||
}
|
||||
/* Last block optionally pad the data with zeros*/
|
||||
for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
|
||||
for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
|
||||
{
|
||||
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
}
|
||||
while (loopcounter < 4U)
|
||||
/* If the header size is a multiple of words */
|
||||
if ((headersize_in_bytes % 4U) == 0U)
|
||||
{
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
hcryp->Instance->DIN = 0x0U;
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enter last bytes, padded with zeroes */
|
||||
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
|
||||
hcryp->Instance->DIN = tmp;
|
||||
loopcounter++;
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
/* Wait for IFEM to be raised */
|
||||
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
|
||||
|
@ -5993,10 +6080,10 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
|
|||
/* Enable the CRYP peripheral */
|
||||
__HAL_CRYP_ENABLE(hcryp);
|
||||
}
|
||||
if ((hcryp->Init.HeaderSize % 4U) == 0U)
|
||||
if ((headersize_in_bytes % 16U) == 0U)
|
||||
{
|
||||
/* HeaderSize %4, no padding */
|
||||
for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
|
||||
for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U)
|
||||
{
|
||||
/* Write the input block in the data input register */
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
|
@ -6035,7 +6122,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
|
|||
else
|
||||
{
|
||||
/*Write header block in the IN FIFO without last block */
|
||||
for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
|
||||
for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
|
||||
{
|
||||
/* Write the Input block in the Data Input register */
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
|
@ -6071,18 +6158,35 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
|
|||
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
|
||||
}
|
||||
/* Last block optionally pad the data with zeros*/
|
||||
for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
|
||||
for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes /4U) % 4U)); loopcounter++)
|
||||
{
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
}
|
||||
while (loopcounter < 4U)
|
||||
/* If the header size is a multiple of words */
|
||||
if ((headersize_in_bytes % 4U) == 0U)
|
||||
{
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enter last bytes, padded with zeroes */
|
||||
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
|
||||
hcryp->Instance->DINR = tmp;
|
||||
loopcounter++;
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
|
||||
/*Wait on CCF flag*/
|
||||
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
|
||||
do
|
||||
|
@ -6141,10 +6245,25 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
|
|||
uint32_t lastwordsize;
|
||||
uint32_t npblb;
|
||||
#endif
|
||||
uint32_t headersize_in_bytes;
|
||||
uint32_t tmp;
|
||||
uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
|
||||
0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
|
||||
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
|
||||
|
||||
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
|
||||
{
|
||||
headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
|
||||
}
|
||||
else
|
||||
{
|
||||
headersize_in_bytes = hcryp->Init.HeaderSize;
|
||||
}
|
||||
|
||||
/***************************** Header phase *********************************/
|
||||
|
||||
#if defined(CRYP)
|
||||
if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
|
||||
if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
|
||||
{
|
||||
/* Disable interrupts */
|
||||
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
|
||||
|
@ -6164,7 +6283,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
|
|||
/* Enable the CRYP peripheral */
|
||||
__HAL_CRYP_ENABLE(hcryp);
|
||||
}
|
||||
else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
|
||||
else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)
|
||||
|
||||
{
|
||||
/* HeaderSize %4, no padding */
|
||||
|
@ -6180,21 +6299,41 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
|
|||
else
|
||||
{
|
||||
/* Last block optionally pad the data with zeros*/
|
||||
for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
|
||||
for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++)
|
||||
{
|
||||
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
}
|
||||
while (loopcounter < 4U)
|
||||
if ((headersize_in_bytes % 4U) == 0U)
|
||||
{
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = 0x0U;
|
||||
loopcounter++;
|
||||
hcryp->CrypHeaderCount++;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enter last bytes, padded with zeros */
|
||||
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
|
||||
hcryp->Instance->DIN = tmp;
|
||||
loopcounter++;
|
||||
hcryp->CrypHeaderCount++;
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DIN = 0x0U;
|
||||
loopcounter++;
|
||||
hcryp->CrypHeaderCount++;
|
||||
}
|
||||
}
|
||||
}
|
||||
#else /* AES */
|
||||
|
||||
if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
|
||||
if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
|
||||
{
|
||||
/* Set the phase */
|
||||
hcryp->Phase = CRYP_PHASE_PROCESS;
|
||||
|
@ -6278,7 +6417,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
|
|||
}
|
||||
}
|
||||
}
|
||||
else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
|
||||
else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)
|
||||
{
|
||||
/* Write the input block in the IN FIFO */
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
|
@ -6293,16 +6432,37 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
|
|||
else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
|
||||
{
|
||||
/* Last block optionally pad the data with zeros*/
|
||||
for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
|
||||
for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++)
|
||||
{
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
}
|
||||
/* If the header size is a multiple of words */
|
||||
if ((headersize_in_bytes % 4U) == 0U)
|
||||
{
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
hcryp->CrypHeaderCount++;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enter last bytes, padded with zeros */
|
||||
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
|
||||
hcryp->Instance->DINR = tmp;
|
||||
loopcounter++;
|
||||
hcryp->CrypHeaderCount++;
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
/* pad the data with zeros to have a complete block */
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
hcryp->CrypHeaderCount++;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* End AES or CRYP */
|
||||
|
|
|
@ -128,10 +128,17 @@
|
|||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
/* Assume first Init.HeaderSize is in words */
|
||||
uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */
|
||||
uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */
|
||||
uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */
|
||||
uint32_t tagaddr = (uint32_t)AuthTag;
|
||||
|
||||
/* Correct headerlength if Init.HeaderSize is actually in bytes */
|
||||
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
|
||||
{
|
||||
headerlength /= 4U;
|
||||
}
|
||||
|
||||
if (hcryp->State == HAL_CRYP_STATE_READY)
|
||||
{
|
||||
/* Process locked */
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -3,9 +3,8 @@
|
|||
* @file stm32f7xx_hal_dac_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended DAC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of DAC extension peripheral:
|
||||
* + Extended features functions
|
||||
* This file provides firmware functions to manage the extended
|
||||
* functionalities of the DAC peripheral.
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
|
@ -13,9 +12,18 @@
|
|||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
|
||||
|
||||
*** Dual mode IO operation ***
|
||||
==============================
|
||||
[..]
|
||||
(+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
|
||||
Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
|
||||
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
|
||||
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
|
||||
Channel 1 and Channel 2.
|
||||
|
||||
*** Signal generation operation ***
|
||||
===================================
|
||||
[..]
|
||||
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
|
||||
(+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
|
||||
|
||||
|
@ -42,27 +50,29 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
|
||||
#if defined(DAC)
|
||||
|
||||
/** @defgroup DACEx DACEx
|
||||
* @brief DAC driver modules
|
||||
* @brief DAC Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Exported_Functions DAC Exported Functions
|
||||
|
||||
/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
*
|
||||
/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
|
||||
* @brief Extended IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Extended features functions #####
|
||||
|
@ -79,33 +89,81 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* @brief Enables DAC and starts conversion of both channels.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval The selected DAC channel data output value.
|
||||
* @retval HAL status
|
||||
*/
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
uint32_t tmp_swtrig = 0UL;
|
||||
|
||||
tmp |= hdac->Instance->DOR1;
|
||||
|
||||
tmp |= hdac->Instance->DOR2 << 16;
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
return tmp;
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
|
||||
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
|
||||
|
||||
/* Check if software trigger enabled */
|
||||
if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
|
||||
{
|
||||
tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
|
||||
}
|
||||
if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)))
|
||||
{
|
||||
tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
|
||||
}
|
||||
/* Enable the selected DAC software conversion*/
|
||||
SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* @brief Disables DAC and stop conversion of both channels.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
|
||||
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the selected DAC channel wave generation.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @param Amplitude: Select max triangle amplitude.
|
||||
* @param Amplitude Select max triangle amplitude.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
|
||||
|
@ -121,7 +179,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
|
|||
* @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
@ -133,8 +191,9 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32
|
|||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the selected wave generation for the selected DAC channel */
|
||||
MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
|
||||
/* Enable the triangle wave generation for the selected DAC channel */
|
||||
MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
|
||||
(DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
@ -147,14 +206,14 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* @brief Enable or disable the selected DAC channel wave generation.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* @param Channel The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
|
||||
* @param Amplitude Unmask DAC channel LFSR for noise wave generation.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
|
||||
|
@ -170,7 +229,7 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32
|
|||
* @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
@ -182,8 +241,9 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
|
|||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the selected wave generation for the selected DAC channel */
|
||||
MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
|
||||
/* Enable the noise wave generation for the selected DAC channel */
|
||||
MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
|
||||
(DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
@ -195,24 +255,26 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for dual DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Alignment: Specifies the data alignment for dual channel DAC.
|
||||
* @param Alignment Specifies the data alignment for dual channel DAC.
|
||||
* This parameter can be one of the following values:
|
||||
* DAC_ALIGN_8B_R: 8bit right data alignment selected
|
||||
* DAC_ALIGN_12B_L: 12bit left data alignment selected
|
||||
* DAC_ALIGN_12B_R: 12bit right data alignment selected
|
||||
* @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
|
||||
* @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.
|
||||
* @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
|
||||
* @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register.
|
||||
* @note In dual mode, a unique register access is required to write in both
|
||||
* DAC channels at the same time.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
|
||||
{
|
||||
uint32_t data = 0, tmp = 0;
|
||||
uint32_t data;
|
||||
uint32_t tmp;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(Alignment));
|
||||
|
@ -222,11 +284,11 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align
|
|||
/* Calculate and set dual DAC data holding register value */
|
||||
if (Alignment == DAC_ALIGN_8B_R)
|
||||
{
|
||||
data = ((uint32_t)Data2 << 8) | Data1;
|
||||
data = ((uint32_t)Data2 << 8U) | Data1;
|
||||
}
|
||||
else
|
||||
{
|
||||
data = ((uint32_t)Data2 << 16) | Data1;
|
||||
data = ((uint32_t)Data2 << 16U) | Data1;
|
||||
}
|
||||
|
||||
tmp = (uint32_t)hdac->Instance;
|
||||
|
@ -240,44 +302,40 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align
|
|||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Conversion complete callback in non blocking mode for Channel2
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* @brief Conversion complete callback in non-blocking mode for Channel2.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
|
||||
__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ConvCpltCallbackCh2 could be implemented in the user file
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Conversion half DMA transfer callback in non blocking mode for Channel2
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* @brief Conversion half DMA transfer callback in non-blocking mode for Channel2.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
|
||||
__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Error DAC callback for Channel2.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
|
@ -286,14 +344,14 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
|
|||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA underrun DAC callback for channel2.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* @brief DMA underrun DAC callback for Channel2.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
|
@ -302,20 +360,74 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
|
|||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Set the specified data holding register value for DAC channel.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Return the last data output value of the selected DAC channel.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
uint32_t tmp = 0UL;
|
||||
|
||||
tmp |= hdac->Instance->DOR1;
|
||||
|
||||
tmp |= hdac->Instance->DOR2 << 16UL;
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
return tmp;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Private_Functions DACEx private functions
|
||||
* @brief Extended private functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA conversion complete callback.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
hdac->ConvCpltCallbackCh2(hdac);
|
||||
|
@ -323,35 +435,35 @@ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
|
|||
HAL_DACEx_ConvCpltCallbackCh2(hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA half transfer complete callback.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
/* Conversion complete callback */
|
||||
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
||||
/* Conversion complete callback */
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
hdac->ConvHalfCpltCallbackCh2(hdac);
|
||||
#else
|
||||
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
|
||||
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA error callback
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* @brief DMA error callback.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
||||
|
||||
/* Set DAC error code to DMA error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
|
||||
|
@ -362,19 +474,22 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
|
|||
HAL_DACEx_ErrorCallbackCh2(hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DAC */
|
||||
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -3334,7 +3334,7 @@ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
|
|||
*/
|
||||
static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
|
||||
{
|
||||
uint32_t channel = 0xFF;
|
||||
uint32_t channel;
|
||||
|
||||
/* Get channel from instance */
|
||||
if(Instance == DFSDM1_Channel0)
|
||||
|
@ -3365,7 +3365,7 @@ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
|
|||
{
|
||||
channel = 6;
|
||||
}
|
||||
else if(Instance == DFSDM1_Channel7)
|
||||
else /* DFSDM1_Channel7 */
|
||||
{
|
||||
channel = 7;
|
||||
}
|
||||
|
|
|
@ -604,7 +604,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
|||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param CompleteLevel Specifies the DMA level complete.
|
||||
* @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
|
||||
* @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead.
|
||||
* This model could be used for debug purpose.
|
||||
* @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
|
||||
* @param Timeout Timeout duration.
|
||||
|
@ -961,7 +961,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
|||
* @brief Register callbacks
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param CallbackID User Callback identifer
|
||||
* @param CallbackID User Callback identifier
|
||||
* a DMA_HandleTypeDef structure as parameter.
|
||||
* @param pCallback pointer to private callbacsk function which has pointer to
|
||||
* a DMA_HandleTypeDef structure as parameter.
|
||||
|
@ -1023,7 +1023,7 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call
|
|||
* @brief UnRegister callbacks
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param CallbackID User Callback identifer
|
||||
* @param CallbackID User Callback identifier
|
||||
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -13,36 +13,57 @@
|
|||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The DSI HAL driver can be used as follows:
|
||||
|
||||
(#) Declare a DSI_HandleTypeDef handle structure, for example: DSI_HandleTypeDef hdsi;
|
||||
|
||||
(#) Initialize the DSI low level resources by implementing the HAL_DSI_MspInit() API:
|
||||
(##) Enable the DSI interface clock
|
||||
(##) NVIC configuration if you need to use interrupt process
|
||||
(+++) Configure the DSI interrupt priority
|
||||
(+++) Enable the NVIC DSI IRQ Channel
|
||||
|
||||
(#) Initialize the DSI Host peripheral, the required PLL parameters, number of lances and
|
||||
TX Escape clock divider by calling the HAL_DSI_Init() API which calls HAL_DSI_MspInit().
|
||||
|
||||
*** Configuration ***
|
||||
=========================
|
||||
[..]
|
||||
(#) Use @ref HAL_DSI_Init() function to initialize the DSI Host IP and program the required
|
||||
PLL parameters, number of lanes and TX Escape clock divider.
|
||||
(#) Use @ref HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted
|
||||
(#) Use HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted
|
||||
command mode.
|
||||
(#) When operating in video mode , use @ref HAL_DSI_ConfigVideoMode() to configure the DSI host.
|
||||
(#) Function @ref HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode.
|
||||
(#) To configure the DSI PHY timings parameters, use function @ref HAL_DSI_ConfigPhyTimer().
|
||||
(#) The DSI Host can be started/stopped using respectively functions @ref HAL_DSI_Start() and @ref HAL_DSI_Stop().
|
||||
Functions @ref HAL_DSI_ShortWrite(), @ref HAL_DSI_LongWrite() and @ref HAL_DSI_Read() allows respectively
|
||||
|
||||
(#) When operating in video mode , use HAL_DSI_ConfigVideoMode() to configure the DSI host.
|
||||
|
||||
(#) Function HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode.
|
||||
|
||||
(#) To configure the DSI PHY timings parameters, use function HAL_DSI_ConfigPhyTimer().
|
||||
|
||||
(#) The DSI Host can be started/stopped using respectively functions HAL_DSI_Start() and HAL_DSI_Stop().
|
||||
Functions HAL_DSI_ShortWrite(), HAL_DSI_LongWrite() and HAL_DSI_Read() allows respectively
|
||||
to write DSI short packets, long packets and to read DSI packets.
|
||||
|
||||
(#) The DSI Host Offers two Low power modes :
|
||||
(+) Low Power Mode on data lanes only: Only DSI data lanes are shut down.
|
||||
It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPMData()
|
||||
and @ref HAL_DSI_ExitULPMData()
|
||||
(++) Low Power Mode on data lanes only: Only DSI data lanes are shut down.
|
||||
It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPMData()
|
||||
and HAL_DSI_ExitULPMData()
|
||||
|
||||
(+) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes.
|
||||
It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPM()
|
||||
and @ref HAL_DSI_ExitULPM()
|
||||
|
||||
(#) User can select the DSI errors to be reported/monitored using function @ref HAL_DSI_ConfigErrorMonitor()
|
||||
When an error occurs, the callback @ref HAL_DSI_ErrorCallback() is asserted and then user can retrieve
|
||||
the error code by calling function @ref HAL_DSI_GetError()
|
||||
(++) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes.
|
||||
It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPM()
|
||||
and HAL_DSI_ExitULPM()
|
||||
|
||||
(#) To control DSI state you can use the following function: HAL_DSI_GetState()
|
||||
|
||||
*** DSI HAL driver macros list ***
|
||||
=============================================
|
||||
[..]
|
||||
*** Error management ***
|
||||
========================
|
||||
[..]
|
||||
(#) User can select the DSI errors to be reported/monitored using function HAL_DSI_ConfigErrorMonitor()
|
||||
When an error occurs, the callback HAL_DSI_ErrorCallback() is asserted and then user can retrieve
|
||||
the error code by calling function HAL_DSI_GetError()
|
||||
|
||||
*** DSI HAL driver macros list ***
|
||||
=============================================
|
||||
[..]
|
||||
Below the list of most used macros in DSI HAL driver.
|
||||
|
||||
(+) __HAL_DSI_ENABLE: Enable the DSI Host.
|
||||
|
@ -59,58 +80,63 @@
|
|||
(+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts.
|
||||
(+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not.
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DSI HAL driver header file for more useful macros
|
||||
|
||||
*** Callback registration ***
|
||||
=============================================
|
||||
[..]
|
||||
The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1
|
||||
allows the user to configure dynamically the driver callbacks.
|
||||
Use Function HAL_DSI_RegisterCallback() to register a callback.
|
||||
|
||||
*** Callback registration ***
|
||||
=============================================
|
||||
[..]
|
||||
Function HAL_DSI_RegisterCallback() allows to register following callbacks:
|
||||
(+) TearingEffectCallback : DSI Tearing Effect Callback.
|
||||
(+) EndOfRefreshCallback : DSI End Of Refresh Callback.
|
||||
(+) ErrorCallback : DSI Error Callback
|
||||
(+) MspInitCallback : DSI MspInit.
|
||||
(+) MspDeInitCallback : DSI MspDeInit.
|
||||
[..]
|
||||
This function takes as parameters the HAL peripheral handle, the callback ID
|
||||
and a pointer to the user callback function.
|
||||
|
||||
The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1
|
||||
allows the user to configure dynamically the driver callbacks.
|
||||
Use Function @ref HAL_DSI_RegisterCallback() to register a callback.
|
||||
[..]
|
||||
Use function HAL_DSI_UnRegisterCallback() to reset a callback to the default
|
||||
weak function.
|
||||
HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
|
||||
and the callback ID.
|
||||
[..]
|
||||
This function allows to reset following callbacks:
|
||||
(+) TearingEffectCallback : DSI Tearing Effect Callback.
|
||||
(+) EndOfRefreshCallback : DSI End Of Refresh Callback.
|
||||
(+) ErrorCallback : DSI Error Callback
|
||||
(+) MspInitCallback : DSI MspInit.
|
||||
(+) MspDeInitCallback : DSI MspDeInit.
|
||||
|
||||
Function @ref HAL_DSI_RegisterCallback() allows to register following callbacks:
|
||||
(+) TearingEffectCallback : DSI Tearing Effect Callback.
|
||||
(+) EndOfRefreshCallback : DSI End Of Refresh Callback.
|
||||
(+) ErrorCallback : DSI Error Callback
|
||||
(+) MspInitCallback : DSI MspInit.
|
||||
(+) MspDeInitCallback : DSI MspDeInit.
|
||||
This function takes as parameters the HAL peripheral handle, the Callback ID
|
||||
and a pointer to the user callback function.
|
||||
[..]
|
||||
By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET
|
||||
all callbacks are set to the corresponding weak functions:
|
||||
examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are respectively
|
||||
reset to the legacy weak (surcharged) functions in the HAL_DSI_Init()
|
||||
and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand).
|
||||
If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit()
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
|
||||
|
||||
Use function @ref HAL_DSI_UnRegisterCallback() to reset a callback to the default
|
||||
weak function.
|
||||
@ref HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
(+) TearingEffectCallback : DSI Tearing Effect Callback.
|
||||
(+) EndOfRefreshCallback : DSI End Of Refresh Callback.
|
||||
(+) ErrorCallback : DSI Error Callback
|
||||
(+) MspInitCallback : DSI MspInit.
|
||||
(+) MspDeInitCallback : DSI MspDeInit.
|
||||
[..]
|
||||
Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only.
|
||||
Exception done MspInit/MspDeInit that can be registered/unregistered
|
||||
in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state,
|
||||
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
|
||||
In that case first register the MspInit/MspDeInit user callbacks
|
||||
using HAL_DSI_RegisterCallback() before calling HAL_DSI_DeInit()
|
||||
or HAL_DSI_Init() function.
|
||||
|
||||
By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET
|
||||
all callbacks are set to the corresponding weak functions:
|
||||
examples @ref HAL_DSI_TearingEffectCallback(), @ref HAL_DSI_EndOfRefreshCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are
|
||||
reset to the legacy weak function in the HAL_DSI_Init/ @ref HAL_DSI_DeInit only when
|
||||
these callbacks are null (not registered beforehand).
|
||||
if not, MspInit or MspDeInit are not null, the @ref HAL_DSI_Init/ @ref HAL_DSI_DeInit
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
|
||||
|
||||
Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only.
|
||||
Exception done MspInit/MspDeInit that can be registered/unregistered
|
||||
in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state,
|
||||
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
|
||||
In that case first register the MspInit/MspDeInit user callbacks
|
||||
using @ref HAL_DSI_RegisterCallback() before calling @ref HAL_DSI_DeInit
|
||||
or HAL_DSI_Init function.
|
||||
|
||||
When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registration feature is not available and all callbacks
|
||||
are set to the corresponding weak functions.
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DSI HAL driver header file for more useful macros
|
||||
[..]
|
||||
When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registration feature is not available and all callbacks
|
||||
are set to the corresponding weak functions.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
|
@ -186,10 +212,10 @@ static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
|
|||
* @param ChannelID Virtual channel ID of the header packet
|
||||
* @param DataType Packet data type of the header packet
|
||||
* This parameter can be any value of :
|
||||
* @ref DSI_SHORT_WRITE_PKT_Data_Type
|
||||
* or @ref DSI_LONG_WRITE_PKT_Data_Type
|
||||
* or @ref DSI_SHORT_READ_PKT_Data_Type
|
||||
* or DSI_MAX_RETURN_PKT_SIZE
|
||||
* @arg DSI_SHORT_WRITE_PKT_Data_Type
|
||||
* @arg DSI_LONG_WRITE_PKT_Data_Type
|
||||
* @arg DSI_SHORT_READ_PKT_Data_Type
|
||||
* @arg DSI_MAX_RETURN_PKT_SIZE
|
||||
* @param Data0 Word count LSB
|
||||
* @param Data1 Word count MSB
|
||||
* @retval None
|
||||
|
@ -210,9 +236,9 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
|
|||
* the configuration information for the DSI.
|
||||
* @param ChannelID Virtual channel ID.
|
||||
* @param Mode DSI short packet data type.
|
||||
* This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
|
||||
* This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type.
|
||||
* @param Param1 DSC command or first generic parameter.
|
||||
* This parameter can be any value of @ref DSI_DCS_Command or a
|
||||
* This parameter can be any value of @arg DSI_DCS_Command or a
|
||||
* generic command code.
|
||||
* @param Param2 DSC parameter or second generic parameter.
|
||||
* @retval HAL status
|
||||
|
@ -464,7 +490,7 @@ HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
|
|||
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
|
||||
* the configuration information for the DSI.
|
||||
* @param ActiveErrors indicates which error interrupts will be enabled.
|
||||
* This parameter can be any combination of @ref DSI_Error_Data_Type.
|
||||
* This parameter can be any combination of @arg DSI_Error_Data_Type.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
|
||||
|
@ -581,11 +607,11 @@ __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi)
|
|||
* @param hdsi dsi handle
|
||||
* @param CallbackID ID of the callback to be registered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
|
||||
* @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
|
||||
* @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID
|
||||
* @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
|
||||
* @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
|
||||
* @arg HAL_DSI_ERROR_CB_ID Error Callback ID
|
||||
* @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @param pCallback pointer to the Callback function
|
||||
* @retval status
|
||||
*/
|
||||
|
@ -676,11 +702,11 @@ HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Call
|
|||
* @param hdsi dsi handle
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
|
||||
* @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
|
||||
* @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID
|
||||
* @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
|
||||
* @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
|
||||
* @arg HAL_DSI_ERROR_CB_ID Error Callback ID
|
||||
* @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @retval status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID)
|
||||
|
@ -1295,7 +1321,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDe
|
|||
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
|
||||
* the configuration information for the DSI.
|
||||
* @param FlowControl flow control feature(s) to be enabled.
|
||||
* This parameter can be any combination of @ref DSI_FlowControl.
|
||||
* This parameter can be any combination of @arg DSI_FlowControl.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
|
||||
|
@ -1488,7 +1514,7 @@ HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
|
|||
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
|
||||
* the configuration information for the DSI.
|
||||
* @param ColorMode Color mode (full or 8-colors).
|
||||
* This parameter can be any value of @ref DSI_Color_Mode
|
||||
* This parameter can be any value of @arg DSI_Color_Mode
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
|
||||
|
@ -1514,7 +1540,7 @@ HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
|
|||
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
|
||||
* the configuration information for the DSI.
|
||||
* @param Shutdown Shut-down (Display-ON or Display-OFF).
|
||||
* This parameter can be any value of @ref DSI_ShutDown
|
||||
* This parameter can be any value of @arg DSI_ShutDown
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
|
||||
|
@ -1541,9 +1567,9 @@ HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
|
|||
* the configuration information for the DSI.
|
||||
* @param ChannelID Virtual channel ID.
|
||||
* @param Mode DSI short packet data type.
|
||||
* This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
|
||||
* This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type.
|
||||
* @param Param1 DSC command or first generic parameter.
|
||||
* This parameter can be any value of @ref DSI_DCS_Command or a
|
||||
* This parameter can be any value of @arg DSI_DCS_Command or a
|
||||
* generic command code.
|
||||
* @param Param2 DSC parameter or second generic parameter.
|
||||
* @retval HAL status
|
||||
|
@ -1575,10 +1601,10 @@ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
|
|||
* the configuration information for the DSI.
|
||||
* @param ChannelID Virtual channel ID.
|
||||
* @param Mode DSI long packet data type.
|
||||
* This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
|
||||
* This parameter can be any value of @arg DSI_LONG_WRITE_PKT_Data_Type.
|
||||
* @param NbParams Number of parameters.
|
||||
* @param Param1 DSC command or first generic parameter.
|
||||
* This parameter can be any value of @ref DSI_DCS_Command or a
|
||||
* This parameter can be any value of @arg DSI_DCS_Command or a
|
||||
* generic command code
|
||||
* @param ParametersTable Pointer to parameter values table.
|
||||
* @retval HAL status
|
||||
|
@ -1665,7 +1691,7 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
|
|||
* @param Array pointer to a buffer to store the payload of a read back operation.
|
||||
* @param Size Data size to be read (in byte).
|
||||
* @param Mode DSI read packet data type.
|
||||
* This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
|
||||
* This parameter can be any value of @arg DSI_SHORT_READ_PKT_Data_Type.
|
||||
* @param DCSCmd DCS get/read command.
|
||||
* @param ParametersTable Pointer to parameter values table.
|
||||
* @retval HAL status
|
||||
|
@ -2120,9 +2146,9 @@ HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
|
|||
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
|
||||
* the configuration information for the DSI.
|
||||
* @param CommDelay Communication delay to be adjusted.
|
||||
* This parameter can be any value of @ref DSI_Communication_Delay
|
||||
* This parameter can be any value of @arg DSI_Communication_Delay
|
||||
* @param Lane select between clock or data lanes.
|
||||
* This parameter can be any value of @ref DSI_Lane_Group
|
||||
* This parameter can be any value of @arg DSI_Lane_Group
|
||||
* @param Value Custom value of the slew-rate or delay
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
@ -2263,10 +2289,10 @@ HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
|
|||
* @brief Custom lane pins configuration
|
||||
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
|
||||
* the configuration information for the DSI.
|
||||
* @param CustomLane Function to be applyed on selected lane.
|
||||
* This parameter can be any value of @ref DSI_CustomLane
|
||||
* @param CustomLane Function to be applied on selected lane.
|
||||
* This parameter can be any value of @arg DSI_CustomLane
|
||||
* @param Lane select between clock or data lane 0 or data lane 1.
|
||||
* This parameter can be any value of @ref DSI_Lane_Select
|
||||
* This parameter can be any value of @arg DSI_Lane_Select
|
||||
* @param State ENABLE or DISABLE
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
@ -2352,7 +2378,7 @@ HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint
|
|||
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
|
||||
* the configuration information for the DSI.
|
||||
* @param Timing PHY timing to be adjusted.
|
||||
* This parameter can be any value of @ref DSI_PHY_Timing
|
||||
* This parameter can be any value of @arg DSI_PHY_Timing
|
||||
* @param State ENABLE or DISABLE
|
||||
* @param Value Custom value of the timing
|
||||
* @retval HAL status
|
||||
|
@ -2500,7 +2526,7 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing
|
|||
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
|
||||
* the configuration information for the DSI.
|
||||
* @param Lane select between clock or data lanes.
|
||||
* This parameter can be any value of @ref DSI_Lane_Group
|
||||
* This parameter can be any value of @arg DSI_Lane_Group
|
||||
* @param State ENABLE or DISABLE
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
|
|
@ -543,7 +543,7 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc
|
|||
/* Fill each DMATxDesc descriptor with the right values */
|
||||
for(i=0; i < TxBuffCount; i++)
|
||||
{
|
||||
/* Get the pointer on the ith member of the Tx Desc list */
|
||||
/* Get the pointer on the member (i) of the Tx Desc list */
|
||||
dmatxdesc = DMATxDescTab + i;
|
||||
|
||||
/* Set Second Address Chained bit */
|
||||
|
@ -610,7 +610,7 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc
|
|||
/* Fill each DMARxDesc descriptor with the right values */
|
||||
for(i=0; i < RxBuffCount; i++)
|
||||
{
|
||||
/* Get the pointer on the ith member of the Rx Desc list */
|
||||
/* Get the pointer on the member (i) of the Rx Desc list */
|
||||
DMARxDesc = DMARxDescTab+i;
|
||||
|
||||
/* Set Own bit of the Rx descriptor Status */
|
||||
|
|
|
@ -660,8 +660,13 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
|
|||
FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
|
||||
FLASH->CR |= FLASH_CR_PG;
|
||||
|
||||
/* Program the double-word */
|
||||
/* Program first word */
|
||||
*(__IO uint32_t*)Address = (uint32_t)Data;
|
||||
/* Barrier to ensure programming is performed in 2 steps, in right order
|
||||
(independently of compiler optimization behavior) */
|
||||
__ISB();
|
||||
|
||||
/* Program second word */
|
||||
*(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
|
||||
|
||||
/* Data synchronous Barrier (DSB) Just after the write operation
|
||||
|
@ -673,7 +678,7 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
|
|||
/**
|
||||
* @brief Program word (32-bit) at a specified address.
|
||||
* @note This function must be used when the device voltage range is from
|
||||
* 2.7V to 3.6V.
|
||||
* 2.7V to 3.3V.
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
|
@ -702,7 +707,7 @@ static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
|
|||
/**
|
||||
* @brief Program a half-word (16-bit) at a specified address.
|
||||
* @note This function must be used when the device voltage range is from
|
||||
* 2.7V to 3.6V.
|
||||
* 2.1V to 3.6V.
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
|
@ -732,7 +737,7 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
|
|||
/**
|
||||
* @brief Program byte (8-bit) at a specified address.
|
||||
* @note This function must be used when the device voltage range is from
|
||||
* 2.7V to 3.6V.
|
||||
* 1.7V to 3.6V.
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
|
|
|
@ -944,7 +944,7 @@ static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_
|
|||
if(status == HAL_OK)
|
||||
{
|
||||
if(BootOption == OPTIONBYTE_BOOTADDR_0)
|
||||
{
|
||||
{
|
||||
MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);
|
||||
}
|
||||
else
|
||||
|
@ -1021,7 +1021,7 @@ static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption)
|
|||
|
||||
/* Return the Boot base Address */
|
||||
if(BootOption == OPTIONBYTE_BOOTADDR_0)
|
||||
{
|
||||
{
|
||||
Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0;
|
||||
}
|
||||
else
|
||||
|
|
|
@ -428,17 +428,16 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
|
|||
*/
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint32_t odr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->ODR & GPIO_Pin) != 0X00u)
|
||||
{
|
||||
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
||||
}
|
||||
/* get current Output Data Register value */
|
||||
odr = GPIOx->ODR;
|
||||
|
||||
/* Set selected pins that were at low level, and reset ones that were high */
|
||||
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -5,7 +5,7 @@
|
|||
* @brief Extended HASH HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the HASH peripheral for SHA-224 and SHA-256
|
||||
* alogrithms:
|
||||
* algorithms:
|
||||
* + HASH or HMAC processing in polling mode
|
||||
* + HASH or HMAC processing in interrupt mode
|
||||
* + HASH or HMAC processing in DMA mode
|
||||
|
@ -46,10 +46,11 @@
|
|||
|
||||
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
|
||||
|
||||
(+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
|
||||
From that point, each buffer can be fed to the Peripheral thru HAL_HASHEx_xxx_Start_DMA() API.
|
||||
(+++) HASH processing: once initialization is done, MDMAT bit must be set through
|
||||
__HAL_HASH_SET_MDMAT() macro.
|
||||
From that point, each buffer can be fed to the Peripheral through HAL_HASHEx_xxx_Start_DMA() API.
|
||||
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
|
||||
macro then wrap-up the HASH processing in feeding the last input buffer thru the
|
||||
macro then wrap-up the HASH processing in feeding the last input buffer through the
|
||||
same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
|
||||
API HAL_HASHEx_xxx_Finish().
|
||||
|
||||
|
@ -107,8 +108,8 @@
|
|||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
|
||||
* @brief HASH extended processing functions using polling mode.
|
||||
*
|
||||
* @brief HASH extended processing functions using polling mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Polling mode HASH extended processing functions #####
|
||||
|
@ -147,7 +148,8 @@
|
|||
* @param Timeout Timeout value
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
@ -174,7 +176,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
{
|
||||
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
|
||||
return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -187,7 +189,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p
|
|||
* @param Timeout Timeout value
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
@ -203,7 +206,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
|
|||
* @param Timeout Timeout value
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
@ -230,7 +234,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
{
|
||||
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
|
||||
return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -243,7 +247,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p
|
|||
* @param Timeout Timeout value
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
@ -253,8 +258,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
|
|||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
|
||||
* @brief HASH extended processing functions using interrupt mode.
|
||||
*
|
||||
* @brief HASH extended processing functions using interrupt mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Interruption mode HASH extended processing functions #####
|
||||
|
@ -285,9 +290,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -310,7 +316,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
{
|
||||
return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
|
||||
return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -322,9 +328,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -337,9 +344,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -362,7 +370,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
{
|
||||
return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
|
||||
return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -374,9 +382,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -384,11 +393,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
|
|||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
|
||||
* @brief HASH extended processing functions using DMA mode.
|
||||
*
|
||||
* @brief HASH extended processing functions using DMA mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### DMA mode HASH extended processing functionss #####
|
||||
##### DMA mode HASH extended processing functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to calculate in DMA mode
|
||||
the hash value using one of the following algorithms:
|
||||
|
@ -440,9 +449,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param Timeout Timeout value.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Finish(hhash, pOutBuffer, Timeout);
|
||||
return HASH_Finish(hhash, pOutBuffer, Timeout);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -470,9 +479,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param Timeout Timeout value.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Finish(hhash, pOutBuffer, Timeout);
|
||||
return HASH_Finish(hhash, pOutBuffer, Timeout);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -480,8 +489,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
|
|||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
|
||||
* @brief HMAC extended processing functions using polling mode.
|
||||
*
|
||||
* @brief HMAC extended processing functions using polling mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Polling mode HMAC extended processing functions #####
|
||||
|
@ -512,7 +521,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
|
|||
* @param Timeout Timeout value.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
@ -530,7 +540,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
* @param Timeout Timeout value.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
@ -541,8 +552,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
|
||||
* @brief HMAC extended processing functions using interruption mode.
|
||||
*
|
||||
* @brief HMAC extended processing functions using interruption mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Interrupt mode HMAC extended processing functions #####
|
||||
|
@ -572,7 +583,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
@ -589,7 +601,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
@ -603,8 +616,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
|
||||
* @brief HMAC extended processing functions using DMA mode.
|
||||
*
|
||||
* @brief HMAC extended processing functions using DMA mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### DMA mode HMAC extended processing functions #####
|
||||
|
@ -681,8 +694,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
|
||||
* @brief HMAC extended processing functions in multi-buffer DMA mode.
|
||||
*
|
||||
* @brief HMAC extended processing functions in multi-buffer DMA mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Multi-buffer DMA mode HMAC extended processing functions #####
|
||||
|
|
|
@ -91,8 +91,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
|
|||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
|
@ -185,9 +185,9 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
|
|||
* This parameter can be a value from 0 to 255
|
||||
* @param speed Current device speed.
|
||||
* This parameter can be one of these values:
|
||||
* HCD_SPEED_HIGH: High speed mode,
|
||||
* HCD_SPEED_FULL: Full speed mode,
|
||||
* HCD_SPEED_LOW: Low speed mode
|
||||
* HCD_DEVICE_SPEED_HIGH: High speed mode,
|
||||
* HCD_DEVICE_SPEED_FULL: Full speed mode,
|
||||
* HCD_DEVICE_SPEED_LOW: Low speed mode
|
||||
* @param ep_type Endpoint Type.
|
||||
* This parameter can be one of these values:
|
||||
* EP_TYPE_CTRL: Control type,
|
||||
|
@ -566,6 +566,16 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|||
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
|
||||
}
|
||||
|
||||
/* Handle Rx Queue Level Interrupts */
|
||||
if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
|
||||
{
|
||||
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
||||
|
||||
HCD_RXQLVL_IRQHandler(hhcd);
|
||||
|
||||
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
||||
}
|
||||
|
||||
/* Handle Host channel Interrupt */
|
||||
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
|
||||
{
|
||||
|
@ -586,19 +596,21 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|||
}
|
||||
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
|
||||
}
|
||||
|
||||
/* Handle Rx Queue Level Interrupts */
|
||||
if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
|
||||
{
|
||||
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
||||
|
||||
HCD_RXQLVL_IRQHandler(hhcd);
|
||||
|
||||
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Handles HCD Wakeup interrupt request.
|
||||
* @param hhcd HCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd)
|
||||
{
|
||||
UNUSED(hhcd);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief SOF callback.
|
||||
* @param hhcd HCD handle
|
||||
|
@ -718,7 +730,9 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t
|
|||
* @param pCallback pointer to the Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
|
||||
HAL_HCD_CallbackIDTypeDef CallbackID,
|
||||
pHCD_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -806,7 +820,7 @@ HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_Call
|
|||
|
||||
/**
|
||||
* @brief Unregister an USB HCD Callback
|
||||
* USB HCD callabck is redirected to the weak predefined callback
|
||||
* USB HCD callback is redirected to the weak predefined callback
|
||||
* @param hhcd USB HCD handle
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
|
@ -910,7 +924,8 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_Ca
|
|||
* @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
|
||||
pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -945,7 +960,7 @@ HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister the USB HCD Host Channel Notify URB Change Callback
|
||||
* @brief Unregister the USB HCD Host Channel Notify URB Change Callback
|
||||
* USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
|
||||
* @param hhcd HCD handle
|
||||
* @retval HAL status
|
||||
|
@ -982,8 +997,8 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef
|
|||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief Management functions
|
||||
*
|
||||
* @brief Management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
|
@ -1041,8 +1056,8 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
|
|||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
|
@ -1192,10 +1207,17 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
|
||||
{
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
|
||||
hhcd->hc[ch_num].state = HC_DATATGLERR;
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
|
||||
{
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
hhcd->hc[ch_num].state = HC_XACTERR;
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -1212,7 +1234,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
{
|
||||
if (hhcd->Init.dma_enable != 0U)
|
||||
{
|
||||
hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \
|
||||
hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].XferSize - \
|
||||
(USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
|
||||
}
|
||||
|
||||
|
@ -1253,8 +1275,18 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
{
|
||||
/* ... */
|
||||
}
|
||||
hhcd->hc[ch_num].toggle_in ^= 1U;
|
||||
|
||||
if (hhcd->Init.dma_enable == 1U)
|
||||
{
|
||||
if (((hhcd->hc[ch_num].XferSize / hhcd->hc[ch_num].max_packet) & 1U) != 0U)
|
||||
{
|
||||
hhcd->hc[ch_num].toggle_in ^= 1U;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
hhcd->hc[ch_num].toggle_in ^= 1U;
|
||||
}
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
|
||||
{
|
||||
|
@ -1262,17 +1294,17 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
|
||||
if (hhcd->hc[ch_num].state == HC_XFRC)
|
||||
{
|
||||
hhcd->hc[ch_num].urb_state = URB_DONE;
|
||||
hhcd->hc[ch_num].urb_state = URB_DONE;
|
||||
}
|
||||
else if (hhcd->hc[ch_num].state == HC_STALL)
|
||||
{
|
||||
hhcd->hc[ch_num].urb_state = URB_STALL;
|
||||
hhcd->hc[ch_num].urb_state = URB_STALL;
|
||||
}
|
||||
else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
|
||||
(hhcd->hc[ch_num].state == HC_DATATGLERR))
|
||||
{
|
||||
hhcd->hc[ch_num].ErrCnt++;
|
||||
if (hhcd->hc[ch_num].ErrCnt > 3U)
|
||||
if (hhcd->hc[ch_num].ErrCnt > 2U)
|
||||
{
|
||||
hhcd->hc[ch_num].ErrCnt = 0U;
|
||||
hhcd->hc[ch_num].urb_state = URB_ERROR;
|
||||
|
@ -1280,18 +1312,19 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
else
|
||||
{
|
||||
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
|
||||
}
|
||||
|
||||
/* re-activate the channel */
|
||||
tmpreg = USBx_HC(ch_num)->HCCHAR;
|
||||
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
||||
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
||||
USBx_HC(ch_num)->HCCHAR = tmpreg;
|
||||
/* re-activate the channel */
|
||||
tmpreg = USBx_HC(ch_num)->HCCHAR;
|
||||
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
||||
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
||||
USBx_HC(ch_num)->HCCHAR = tmpreg;
|
||||
}
|
||||
}
|
||||
else if (hhcd->hc[ch_num].state == HC_NAK)
|
||||
{
|
||||
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
|
||||
/* re-activate the channel */
|
||||
|
||||
/* re-activate the channel */
|
||||
tmpreg = USBx_HC(ch_num)->HCCHAR;
|
||||
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
||||
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
||||
|
@ -1309,14 +1342,6 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
|
||||
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
|
||||
{
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
hhcd->hc[ch_num].ErrCnt++;
|
||||
hhcd->hc[ch_num].state = HC_XACTERR;
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
|
||||
{
|
||||
if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
|
||||
|
@ -1362,6 +1387,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
uint32_t USBx_BASE = (uint32_t)USBx;
|
||||
uint32_t ch_num = (uint32_t)chnum;
|
||||
uint32_t tmpreg;
|
||||
uint32_t num_packets;
|
||||
|
||||
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
|
||||
{
|
||||
|
@ -1380,15 +1406,6 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
}
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
|
||||
{
|
||||
hhcd->hc[ch_num].state = HC_NYET;
|
||||
hhcd->hc[ch_num].do_ping = 1U;
|
||||
hhcd->hc[ch_num].ErrCnt = 0U;
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
|
||||
{
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
|
@ -1398,11 +1415,27 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
|
||||
{
|
||||
hhcd->hc[ch_num].ErrCnt = 0U;
|
||||
|
||||
/* transaction completed with NYET state, update do ping state */
|
||||
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
|
||||
{
|
||||
hhcd->hc[ch_num].do_ping = 1U;
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
|
||||
}
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
|
||||
hhcd->hc[ch_num].state = HC_XFRC;
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
|
||||
{
|
||||
hhcd->hc[ch_num].state = HC_NYET;
|
||||
hhcd->hc[ch_num].do_ping = 1U;
|
||||
hhcd->hc[ch_num].ErrCnt = 0U;
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
|
||||
{
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
|
||||
|
@ -1417,7 +1450,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
|
||||
if (hhcd->hc[ch_num].do_ping == 0U)
|
||||
{
|
||||
if (hhcd->hc[ch_num].speed == HCD_SPEED_HIGH)
|
||||
if (hhcd->hc[ch_num].speed == HCD_DEVICE_SPEED_HIGH)
|
||||
{
|
||||
hhcd->hc[ch_num].do_ping = 1U;
|
||||
}
|
||||
|
@ -1429,9 +1462,26 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
|
||||
{
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
hhcd->hc[ch_num].state = HC_XACTERR;
|
||||
if (hhcd->Init.dma_enable == 0U)
|
||||
{
|
||||
hhcd->hc[ch_num].state = HC_XACTERR;
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
}
|
||||
else
|
||||
{
|
||||
hhcd->hc[ch_num].ErrCnt++;
|
||||
if (hhcd->hc[ch_num].ErrCnt > 2U)
|
||||
{
|
||||
hhcd->hc[ch_num].ErrCnt = 0U;
|
||||
hhcd->hc[ch_num].urb_state = URB_ERROR;
|
||||
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
|
||||
}
|
||||
else
|
||||
{
|
||||
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
|
||||
}
|
||||
}
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
|
||||
|
@ -1452,7 +1502,22 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) ||
|
||||
(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR))
|
||||
{
|
||||
hhcd->hc[ch_num].toggle_out ^= 1U;
|
||||
if (hhcd->Init.dma_enable == 1U)
|
||||
{
|
||||
if (hhcd->hc[ch_num].xfer_len > 0U)
|
||||
{
|
||||
num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet;
|
||||
|
||||
if ((num_packets & 1U) != 0U)
|
||||
{
|
||||
hhcd->hc[ch_num].toggle_out ^= 1U;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
hhcd->hc[ch_num].toggle_out ^= 1U;
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (hhcd->hc[ch_num].state == HC_NAK)
|
||||
|
@ -1471,7 +1536,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
(hhcd->hc[ch_num].state == HC_DATATGLERR))
|
||||
{
|
||||
hhcd->hc[ch_num].ErrCnt++;
|
||||
if (hhcd->hc[ch_num].ErrCnt > 3U)
|
||||
if (hhcd->hc[ch_num].ErrCnt > 2U)
|
||||
{
|
||||
hhcd->hc[ch_num].ErrCnt = 0U;
|
||||
hhcd->hc[ch_num].urb_state = URB_ERROR;
|
||||
|
@ -1479,13 +1544,13 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
else
|
||||
{
|
||||
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
|
||||
}
|
||||
|
||||
/* re-activate the channel */
|
||||
tmpreg = USBx_HC(ch_num)->HCCHAR;
|
||||
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
||||
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
||||
USBx_HC(ch_num)->HCCHAR = tmpreg;
|
||||
/* re-activate the channel */
|
||||
tmpreg = USBx_HC(ch_num)->HCCHAR;
|
||||
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
||||
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
||||
USBx_HC(ch_num)->HCCHAR = tmpreg;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -1512,14 +1577,15 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|||
uint32_t USBx_BASE = (uint32_t)USBx;
|
||||
uint32_t pktsts;
|
||||
uint32_t pktcnt;
|
||||
uint32_t temp;
|
||||
uint32_t GrxstspReg;
|
||||
uint32_t xferSizePktCnt;
|
||||
uint32_t tmpreg;
|
||||
uint32_t ch_num;
|
||||
|
||||
temp = hhcd->Instance->GRXSTSP;
|
||||
ch_num = temp & USB_OTG_GRXSTSP_EPNUM;
|
||||
pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17;
|
||||
pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
|
||||
GrxstspReg = hhcd->Instance->GRXSTSP;
|
||||
ch_num = GrxstspReg & USB_OTG_GRXSTSP_EPNUM;
|
||||
pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17;
|
||||
pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4;
|
||||
|
||||
switch (pktsts)
|
||||
{
|
||||
|
@ -1527,20 +1593,31 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|||
/* Read the data into the host buffer. */
|
||||
if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0))
|
||||
{
|
||||
(void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);
|
||||
|
||||
/*manage multiple Xfer */
|
||||
hhcd->hc[ch_num].xfer_buff += pktcnt;
|
||||
hhcd->hc[ch_num].xfer_count += pktcnt;
|
||||
|
||||
if ((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U)
|
||||
if ((hhcd->hc[ch_num].xfer_count + pktcnt) <= hhcd->hc[ch_num].xfer_len)
|
||||
{
|
||||
/* re-activate the channel when more packets are expected */
|
||||
tmpreg = USBx_HC(ch_num)->HCCHAR;
|
||||
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
||||
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
||||
USBx_HC(ch_num)->HCCHAR = tmpreg;
|
||||
hhcd->hc[ch_num].toggle_in ^= 1U;
|
||||
(void)USB_ReadPacket(hhcd->Instance,
|
||||
hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);
|
||||
|
||||
/* manage multiple Xfer */
|
||||
hhcd->hc[ch_num].xfer_buff += pktcnt;
|
||||
hhcd->hc[ch_num].xfer_count += pktcnt;
|
||||
|
||||
/* get transfer size packet count */
|
||||
xferSizePktCnt = (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19;
|
||||
|
||||
if ((hhcd->hc[ch_num].max_packet == pktcnt) && (xferSizePktCnt > 0U))
|
||||
{
|
||||
/* re-activate the channel when more packets are expected */
|
||||
tmpreg = USBx_HC(ch_num)->HCCHAR;
|
||||
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
||||
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
||||
USBx_HC(ch_num)->HCCHAR = tmpreg;
|
||||
hhcd->hc[ch_num].toggle_in ^= 1U;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
hhcd->hc[ch_num].urb_state = URB_ERROR;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
|
|
@ -93,7 +93,7 @@
|
|||
[..]
|
||||
(+) A specific option field manage the different steps of a sequential transfer
|
||||
(+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
|
||||
(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
|
||||
(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
|
||||
(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
|
||||
and data to transfer without a final stop condition
|
||||
(++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
|
||||
|
@ -112,7 +112,7 @@
|
|||
or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
|
||||
or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
|
||||
or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
|
||||
Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
|
||||
Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
|
||||
without stopping the communication and so generate a restart condition.
|
||||
(++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
|
||||
interface.
|
||||
|
@ -122,7 +122,7 @@
|
|||
or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
|
||||
Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
|
||||
|
||||
(+) Differents sequential I2C interfaces are listed below:
|
||||
(+) Different sequential I2C interfaces are listed below:
|
||||
(++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
|
||||
or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
|
||||
(+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
|
||||
|
@ -351,13 +351,13 @@
|
|||
|
||||
|
||||
/* Private define to centralize the enable/disable of Interrupts */
|
||||
#define I2C_XFER_TX_IT (0x00000001U)
|
||||
#define I2C_XFER_RX_IT (0x00000002U)
|
||||
#define I2C_XFER_LISTEN_IT (0x00000004U)
|
||||
#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
|
||||
#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
|
||||
#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */
|
||||
|
||||
#define I2C_XFER_ERROR_IT (0x00000011U)
|
||||
#define I2C_XFER_CPLT_IT (0x00000012U)
|
||||
#define I2C_XFER_RELOAD_IT (0x00000012U)
|
||||
#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */
|
||||
#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */
|
||||
#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */
|
||||
|
||||
/* Private define Sequential Transfer Options default/reset value */
|
||||
#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
|
||||
|
@ -390,8 +390,10 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
|
|||
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
|
||||
|
||||
/* Private functions to handle IT transfer */
|
||||
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
|
||||
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
|
||||
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
|
||||
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
|
||||
|
||||
/* Private functions for I2C transfer IRQ handler */
|
||||
static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
|
||||
|
@ -400,7 +402,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
|
|||
static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
|
||||
|
||||
/* Private functions to handle flags during polling transfer */
|
||||
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
|
||||
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
|
||||
uint32_t Timeout, uint32_t Tickstart);
|
||||
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
|
||||
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
|
||||
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
|
||||
|
@ -410,11 +413,15 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
|
|||
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
|
||||
static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
|
||||
|
||||
/* Private function to treat different error callback */
|
||||
static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Private function to flush TXDR register */
|
||||
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Private function to handle start, restart or stop a transfer */
|
||||
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
|
||||
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
|
||||
uint32_t Request);
|
||||
|
||||
/* Private function to Convert Specific options */
|
||||
static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
|
||||
|
@ -429,8 +436,8 @@ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
|
|||
*/
|
||||
|
||||
/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
|
@ -669,7 +676,8 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
|
|||
* @param pCallback pointer to the Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
|
||||
pI2C_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -974,8 +982,8 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
|
|||
*/
|
||||
|
||||
/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
|
@ -1057,7 +1065,8 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
|
|||
* @param Timeout Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
|
@ -1171,7 +1180,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
|
|||
* @param Timeout Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
|
@ -1547,7 +1557,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
|
|||
* @param Size Amount of data to be sent
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size)
|
||||
{
|
||||
uint32_t xfermode;
|
||||
|
||||
|
@ -1783,7 +1794,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
|
|||
* @param Size Amount of data to be sent
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size)
|
||||
{
|
||||
uint32_t xfermode;
|
||||
HAL_StatusTypeDef dmaxferstatus;
|
||||
|
@ -1926,7 +1938,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
|
|||
* @param Size Amount of data to be sent
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size)
|
||||
{
|
||||
uint32_t xfermode;
|
||||
HAL_StatusTypeDef dmaxferstatus;
|
||||
|
@ -2277,7 +2290,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
|
|||
* @param Timeout Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
|
@ -2369,8 +2383,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
|
|||
}
|
||||
}
|
||||
|
||||
}
|
||||
while (hi2c->XferCount > 0U);
|
||||
} while (hi2c->XferCount > 0U);
|
||||
|
||||
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
||||
/* Wait until STOPF flag is reset */
|
||||
|
@ -2412,7 +2425,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
|
|||
* @param Timeout Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
|
@ -2504,8 +2518,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
|
|||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
|
||||
}
|
||||
}
|
||||
}
|
||||
while (hi2c->XferCount > 0U);
|
||||
} while (hi2c->XferCount > 0U);
|
||||
|
||||
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
||||
/* Wait until STOPF flag is reset */
|
||||
|
@ -2545,7 +2558,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
|
|||
* @param Size Amount of data to be sent
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint32_t xfermode;
|
||||
|
@ -2636,7 +2650,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
|
|||
* @param Size Amount of data to be sent
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint32_t xfermode;
|
||||
|
@ -2726,7 +2741,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
|
|||
* @param Size Amount of data to be sent
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint32_t xfermode;
|
||||
|
@ -2870,7 +2886,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
|
|||
* @param Size Amount of data to be read
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint32_t xfermode;
|
||||
|
@ -3121,8 +3138,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
|
|||
|
||||
/* Increment Trials */
|
||||
I2C_Trials++;
|
||||
}
|
||||
while (I2C_Trials < Trials);
|
||||
} while (I2C_Trials < Trials);
|
||||
|
||||
/* Update I2C state */
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
@ -3153,7 +3169,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
|
|||
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions)
|
||||
{
|
||||
uint32_t xfermode;
|
||||
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
|
||||
|
@ -3200,7 +3217,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
|
|||
I2C_ConvertOtherXferOptions(hi2c);
|
||||
|
||||
/* Update xfermode accordingly if no reload is necessary */
|
||||
if (hi2c->XferCount < MAX_NBYTE_SIZE)
|
||||
if (hi2c->XferCount <= MAX_NBYTE_SIZE)
|
||||
{
|
||||
xfermode = hi2c->XferOptions;
|
||||
}
|
||||
|
@ -3237,7 +3254,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
|
|||
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions)
|
||||
{
|
||||
uint32_t xfermode;
|
||||
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
|
||||
|
@ -3285,7 +3303,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
|||
I2C_ConvertOtherXferOptions(hi2c);
|
||||
|
||||
/* Update xfermode accordingly if no reload is necessary */
|
||||
if (hi2c->XferCount < MAX_NBYTE_SIZE)
|
||||
if (hi2c->XferCount <= MAX_NBYTE_SIZE)
|
||||
{
|
||||
xfermode = hi2c->XferOptions;
|
||||
}
|
||||
|
@ -3399,7 +3417,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
|||
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions)
|
||||
{
|
||||
uint32_t xfermode;
|
||||
uint32_t xferrequest = I2C_GENERATE_START_READ;
|
||||
|
@ -3446,7 +3465,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_
|
|||
I2C_ConvertOtherXferOptions(hi2c);
|
||||
|
||||
/* Update xfermode accordingly if no reload is necessary */
|
||||
if (hi2c->XferCount < MAX_NBYTE_SIZE)
|
||||
if (hi2c->XferCount <= MAX_NBYTE_SIZE)
|
||||
{
|
||||
xfermode = hi2c->XferOptions;
|
||||
}
|
||||
|
@ -3483,7 +3502,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_
|
|||
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions)
|
||||
{
|
||||
uint32_t xfermode;
|
||||
uint32_t xferrequest = I2C_GENERATE_START_READ;
|
||||
|
@ -3531,7 +3551,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
|
|||
I2C_ConvertOtherXferOptions(hi2c);
|
||||
|
||||
/* Update xfermode accordingly if no reload is necessary */
|
||||
if (hi2c->XferCount < MAX_NBYTE_SIZE)
|
||||
if (hi2c->XferCount <= MAX_NBYTE_SIZE)
|
||||
{
|
||||
xfermode = hi2c->XferOptions;
|
||||
}
|
||||
|
@ -3643,7 +3663,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
|
|||
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
|
||||
|
@ -3738,7 +3759,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t
|
|||
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions)
|
||||
{
|
||||
HAL_StatusTypeDef dmaxferstatus;
|
||||
|
||||
|
@ -3917,7 +3939,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_
|
|||
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
|
||||
|
@ -4012,7 +4035,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t
|
|||
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions)
|
||||
{
|
||||
HAL_StatusTypeDef dmaxferstatus;
|
||||
|
||||
|
@ -4251,9 +4275,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
|
|||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
/* Disable Interrupts */
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
/* Disable Interrupts and Store Previous state */
|
||||
if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
|
||||
{
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
|
||||
}
|
||||
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
||||
{
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
|
||||
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
/* Set State at HAL_I2C_STATE_ABORT */
|
||||
hi2c->State = HAL_I2C_STATE_ABORT;
|
||||
|
@ -4285,8 +4321,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
|
|||
*/
|
||||
|
||||
/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function handles I2C event interrupt request.
|
||||
|
@ -4524,8 +4560,8 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
|
|||
*/
|
||||
|
||||
/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
||||
* @brief Peripheral State, Mode and Error functions
|
||||
*
|
||||
* @brief Peripheral State, Mode and Error functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State, Mode and Error functions #####
|
||||
|
@ -4562,11 +4598,11 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Return the I2C error code.
|
||||
* @brief Return the I2C error code.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @retval I2C Error Code
|
||||
*/
|
||||
* @retval I2C Error Code
|
||||
*/
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
return hi2c->ErrorCode;
|
||||
|
@ -4752,7 +4788,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
|
|||
/* So clear Flag NACKF only */
|
||||
if (hi2c->XferCount == 0U)
|
||||
{
|
||||
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
|
||||
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
|
||||
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
|
||||
{
|
||||
/* Call I2C Listen complete process */
|
||||
I2C_ITListenCplt(hi2c, tmpITFlags);
|
||||
|
@ -4812,7 +4849,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
|
|||
I2C_ITSlaveSeqCplt(hi2c);
|
||||
}
|
||||
}
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
|
||||
{
|
||||
I2C_ITAddrCplt(hi2c, tmpITFlags);
|
||||
}
|
||||
|
@ -4820,7 +4858,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
|
|||
{
|
||||
/* Write data to TXDR only if XferCount not reach "0" */
|
||||
/* A TXIS flag can be set, during STOP treatment */
|
||||
/* Check if all Datas have already been sent */
|
||||
/* Check if all Data have already been sent */
|
||||
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
|
||||
if (hi2c->XferCount > 0U)
|
||||
{
|
||||
|
@ -5001,6 +5039,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
|
|||
{
|
||||
uint32_t tmpoptions = hi2c->XferOptions;
|
||||
uint32_t treatdmanack = 0U;
|
||||
HAL_I2C_StateTypeDef tmpstate;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
@ -5047,7 +5086,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
|
|||
|
||||
if (treatdmanack == 1U)
|
||||
{
|
||||
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
|
||||
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
|
||||
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
|
||||
{
|
||||
/* Call I2C Listen complete process */
|
||||
I2C_ITListenCplt(hi2c, ITFlags);
|
||||
|
@ -5079,8 +5119,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
|
|||
/* Set ErrorCode corresponding to a Non-Acknowledge */
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
||||
|
||||
/* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
|
||||
tmpstate = hi2c->State;
|
||||
|
||||
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
|
||||
{
|
||||
if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
|
||||
{
|
||||
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
|
||||
}
|
||||
else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
|
||||
{
|
||||
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
||||
I2C_ITError(hi2c, hi2c->ErrorCode);
|
||||
}
|
||||
|
@ -5119,7 +5175,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
|
|||
* @param Tickstart Tick start value
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
|
||||
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
|
||||
|
||||
|
@ -5172,7 +5229,8 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
|
|||
* @param Tickstart Tick start value
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
|
||||
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
|
||||
|
||||
|
@ -5369,9 +5427,27 @@ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
|
|||
*/
|
||||
static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
|
||||
|
||||
/* Reset I2C handle mode */
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
|
||||
/* If a DMA is ongoing, Update handle size context */
|
||||
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
|
||||
{
|
||||
/* Disable DMA Request */
|
||||
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
|
||||
}
|
||||
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
|
||||
{
|
||||
/* Disable DMA Request */
|
||||
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
|
||||
{
|
||||
/* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
|
||||
|
@ -5426,19 +5502,36 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
|
|||
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
||||
{
|
||||
uint32_t tmperror;
|
||||
uint32_t tmpITFlags = ITFlags;
|
||||
__IO uint32_t tmpreg;
|
||||
|
||||
/* Clear STOP Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
||||
|
||||
/* Disable Interrupts and Store Previous state */
|
||||
if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
|
||||
{
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
|
||||
}
|
||||
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
||||
{
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
|
||||
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
/* Clear Configuration Register 2 */
|
||||
I2C_RESET_CR2(hi2c);
|
||||
|
||||
/* Reset handle parameters */
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
hi2c->XferISR = NULL;
|
||||
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
|
||||
|
||||
if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET)
|
||||
if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
|
||||
{
|
||||
/* Clear NACK Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
|
@ -5447,12 +5540,17 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
|||
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
||||
}
|
||||
|
||||
/* Fetch Last receive data if any */
|
||||
if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
|
||||
{
|
||||
/* Read data from RXDR */
|
||||
tmpreg = (uint8_t)hi2c->Instance->RXDR;
|
||||
UNUSED(tmpreg);
|
||||
}
|
||||
|
||||
/* Flush TX register */
|
||||
I2C_Flush_TXDR(hi2c);
|
||||
|
||||
/* Disable Interrupts */
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
|
||||
|
||||
/* Store current volatile hi2c->ErrorCode, misra rule */
|
||||
tmperror = hi2c->ErrorCode;
|
||||
|
||||
|
@ -5466,6 +5564,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
|||
else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
|
||||
{
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
|
||||
if (hi2c->Mode == HAL_I2C_MODE_MEM)
|
||||
{
|
||||
|
@ -5500,6 +5599,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
|||
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
||||
{
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
|
||||
if (hi2c->Mode == HAL_I2C_MODE_MEM)
|
||||
{
|
||||
|
@ -5546,12 +5646,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
|||
{
|
||||
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
|
||||
uint32_t tmpITFlags = ITFlags;
|
||||
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
|
||||
|
||||
/* Clear STOP Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
||||
|
||||
/* Disable all interrupts */
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
|
||||
/* Disable Interrupts and Store Previous state */
|
||||
if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
|
||||
{
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
|
||||
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
|
||||
}
|
||||
else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
|
||||
{
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
|
||||
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
|
@ -5565,6 +5679,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
|||
/* If a DMA is ongoing, Update handle size context */
|
||||
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
|
||||
{
|
||||
/* Disable DMA Request */
|
||||
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
|
||||
|
||||
if (hi2c->hdmatx != NULL)
|
||||
{
|
||||
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
|
||||
|
@ -5572,6 +5689,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
|||
}
|
||||
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
|
||||
{
|
||||
/* Disable DMA Request */
|
||||
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
|
||||
|
||||
if (hi2c->hdmarx != NULL)
|
||||
{
|
||||
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
|
||||
|
@ -5608,7 +5728,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
|||
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
||||
}
|
||||
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
hi2c->XferISR = NULL;
|
||||
|
||||
|
@ -5626,11 +5745,12 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
|||
}
|
||||
else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
|
||||
{
|
||||
/* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
|
||||
/* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
|
||||
I2C_ITSlaveSeqCplt(hi2c);
|
||||
|
||||
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
@ -5646,6 +5766,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
|||
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
||||
{
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
@ -5660,6 +5781,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
|||
else
|
||||
{
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
@ -5733,6 +5855,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
|||
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
|
||||
{
|
||||
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
|
||||
uint32_t tmppreviousstate;
|
||||
|
||||
/* Reset handle parameters */
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
|
@ -5752,7 +5875,6 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
|
|||
|
||||
/* keep HAL_I2C_STATE_LISTEN if set */
|
||||
hi2c->State = HAL_I2C_STATE_LISTEN;
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
hi2c->XferISR = I2C_Slave_ISR_IT;
|
||||
}
|
||||
else
|
||||
|
@ -5760,23 +5882,27 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
|
|||
/* Disable all interrupts */
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
|
||||
|
||||
/* If state is an abort treatment on goind, don't change state */
|
||||
/* If state is an abort treatment on going, don't change state */
|
||||
/* This change will be do later */
|
||||
if (hi2c->State != HAL_I2C_STATE_ABORT)
|
||||
{
|
||||
/* Set HAL_I2C_STATE_READY */
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
}
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
hi2c->XferISR = NULL;
|
||||
}
|
||||
|
||||
/* Abort DMA TX transfer if any */
|
||||
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
|
||||
tmppreviousstate = hi2c->PreviousState;
|
||||
if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
|
||||
(tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
|
||||
{
|
||||
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
|
||||
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
|
||||
{
|
||||
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
|
||||
}
|
||||
|
||||
if (hi2c->hdmatx != NULL)
|
||||
if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
|
||||
{
|
||||
/* Set the I2C DMA Abort callback :
|
||||
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
|
||||
|
@ -5792,13 +5918,21 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
|
|||
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
I2C_TreatErrorCallback(hi2c);
|
||||
}
|
||||
}
|
||||
/* Abort DMA RX transfer if any */
|
||||
else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
|
||||
else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
|
||||
(tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
|
||||
{
|
||||
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
|
||||
if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
|
||||
{
|
||||
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
|
||||
}
|
||||
|
||||
if (hi2c->hdmarx != NULL)
|
||||
if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
|
||||
{
|
||||
/* Set the I2C DMA Abort callback :
|
||||
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
|
||||
|
@ -5814,10 +5948,28 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
|
|||
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
I2C_TreatErrorCallback(hi2c);
|
||||
}
|
||||
}
|
||||
else if (hi2c->State == HAL_I2C_STATE_ABORT)
|
||||
else
|
||||
{
|
||||
I2C_TreatErrorCallback(hi2c);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief I2C Error callback treatment.
|
||||
* @param hi2c I2C handle.
|
||||
* @retval None
|
||||
*/
|
||||
static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
if (hi2c->State == HAL_I2C_STATE_ABORT)
|
||||
{
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
@ -5831,6 +5983,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
|
|||
}
|
||||
else
|
||||
{
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
|
@ -6062,30 +6216,16 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
|
|||
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
|
||||
|
||||
/* Reset AbortCpltCallback */
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
hi2c->hdmarx->XferAbortCallback = NULL;
|
||||
|
||||
/* Check if come from abort from user */
|
||||
if (hi2c->State == HAL_I2C_STATE_ABORT)
|
||||
if (hi2c->hdmatx != NULL)
|
||||
{
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
hi2c->AbortCpltCallback(hi2c);
|
||||
#else
|
||||
HAL_I2C_AbortCpltCallback(hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
}
|
||||
else
|
||||
if (hi2c->hdmarx != NULL)
|
||||
{
|
||||
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
hi2c->ErrorCallback(hi2c);
|
||||
#else
|
||||
HAL_I2C_ErrorCallback(hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
hi2c->hdmarx->XferAbortCallback = NULL;
|
||||
}
|
||||
|
||||
I2C_TreatErrorCallback(hi2c);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -6098,7 +6238,8 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
|
|||
* @param Tickstart Tick start value
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
|
||||
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
|
||||
uint32_t Timeout, uint32_t Tickstart)
|
||||
{
|
||||
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
||||
{
|
||||
|
@ -6330,7 +6471,8 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
|
|||
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
|
||||
* @retval None
|
||||
*/
|
||||
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
|
||||
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
|
||||
uint32_t Request)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
|
@ -6338,8 +6480,11 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin
|
|||
assert_param(IS_TRANSFER_REQUEST(Request));
|
||||
|
||||
/* update CR2 register */
|
||||
MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
|
||||
(uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
|
||||
MODIFY_REG(hi2c->Instance->CR2,
|
||||
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
|
||||
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
|
||||
(uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) |
|
||||
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -6362,19 +6507,19 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
|
|||
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
|
||||
if (InterruptRequest == I2C_XFER_ERROR_IT)
|
||||
{
|
||||
/* Enable ERR and NACK interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
|
||||
if (InterruptRequest == I2C_XFER_CPLT_IT)
|
||||
{
|
||||
/* Enable STOP interrupts */
|
||||
tmpisr |= I2C_IT_STOPI;
|
||||
tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
|
||||
if (InterruptRequest == I2C_XFER_RELOAD_IT)
|
||||
{
|
||||
/* Enable TC interrupts */
|
||||
tmpisr |= I2C_IT_TCI;
|
||||
|
@ -6400,7 +6545,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
|
|||
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
|
||||
if (InterruptRequest == I2C_XFER_CPLT_IT)
|
||||
{
|
||||
/* Enable STOP interrupts */
|
||||
tmpisr |= I2C_IT_STOPI;
|
||||
|
@ -6454,19 +6599,19 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
|
|||
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
|
||||
if (InterruptRequest == I2C_XFER_ERROR_IT)
|
||||
{
|
||||
/* Enable ERR and NACK interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
|
||||
if (InterruptRequest == I2C_XFER_CPLT_IT)
|
||||
{
|
||||
/* Enable STOP interrupts */
|
||||
tmpisr |= I2C_IT_STOPI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
|
||||
if (InterruptRequest == I2C_XFER_RELOAD_IT)
|
||||
{
|
||||
/* Enable TC interrupts */
|
||||
tmpisr |= I2C_IT_TCI;
|
||||
|
@ -6479,7 +6624,7 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
|
||||
* @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
|
||||
* @param hi2c I2C handle.
|
||||
* @retval None
|
||||
*/
|
||||
|
|
|
@ -69,7 +69,7 @@
|
|||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
|
|
|
@ -88,6 +88,10 @@
|
|||
(+) Pause the DMA Transfer using HAL_I2S_DMAPause()
|
||||
(+) Resume the DMA Transfer using HAL_I2S_DMAResume()
|
||||
(+) Stop the DMA Transfer using HAL_I2S_DMAStop()
|
||||
In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error
|
||||
HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
|
||||
In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data
|
||||
inside DR register and avoid using DeInit/Init process for the next transfer.
|
||||
|
||||
*** I2S HAL driver macros list ***
|
||||
===================================
|
||||
|
@ -99,6 +103,7 @@
|
|||
(+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
|
||||
(+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
|
||||
(+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
|
||||
(+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data
|
||||
|
||||
[..]
|
||||
(@) You can refer to the I2S HAL driver header file for more useful macros
|
||||
|
@ -113,13 +118,13 @@
|
|||
Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
|
||||
|
||||
Function HAL_I2S_RegisterCallback() allows to register following callbacks:
|
||||
(+) TxCpltCallback : I2S Tx Completed callback
|
||||
(+) RxCpltCallback : I2S Rx Completed callback
|
||||
(+) TxHalfCpltCallback : I2S Tx Half Completed callback
|
||||
(+) RxHalfCpltCallback : I2S Rx Half Completed callback
|
||||
(+) ErrorCallback : I2S Error callback
|
||||
(+) MspInitCallback : I2S Msp Init callback
|
||||
(+) MspDeInitCallback : I2S Msp DeInit callback
|
||||
(++) TxCpltCallback : I2S Tx Completed callback
|
||||
(++) RxCpltCallback : I2S Rx Completed callback
|
||||
(++) TxHalfCpltCallback : I2S Tx Half Completed callback
|
||||
(++) RxHalfCpltCallback : I2S Rx Half Completed callback
|
||||
(++) ErrorCallback : I2S Error callback
|
||||
(++) MspInitCallback : I2S Msp Init callback
|
||||
(++) MspDeInitCallback : I2S Msp DeInit callback
|
||||
This function takes as parameters the HAL peripheral handle, the Callback ID
|
||||
and a pointer to the user callback function.
|
||||
|
||||
|
@ -129,14 +134,15 @@
|
|||
HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
(+) TxCpltCallback : I2S Tx Completed callback
|
||||
(+) RxCpltCallback : I2S Rx Completed callback
|
||||
(+) TxHalfCpltCallback : I2S Tx Half Completed callback
|
||||
(+) RxHalfCpltCallback : I2S Rx Half Completed callback
|
||||
(+) ErrorCallback : I2S Error callback
|
||||
(+) MspInitCallback : I2S Msp Init callback
|
||||
(+) MspDeInitCallback : I2S Msp DeInit callback
|
||||
(++) TxCpltCallback : I2S Tx Completed callback
|
||||
(++) RxCpltCallback : I2S Rx Completed callback
|
||||
(++) TxHalfCpltCallback : I2S Tx Half Completed callback
|
||||
(++) RxHalfCpltCallback : I2S Rx Half Completed callback
|
||||
(++) ErrorCallback : I2S Error callback
|
||||
(++) MspInitCallback : I2S Msp Init callback
|
||||
(++) MspDeInitCallback : I2S Msp DeInit callback
|
||||
|
||||
[..]
|
||||
By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
|
||||
all callbacks are set to the corresponding weak functions:
|
||||
examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
|
||||
|
@ -146,6 +152,7 @@
|
|||
If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
|
||||
|
||||
[..]
|
||||
Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
|
||||
Exception done MspInit/MspDeInit functions that can be registered/unregistered
|
||||
in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
|
||||
|
@ -154,7 +161,8 @@
|
|||
using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
|
||||
or HAL_I2S_Init() function.
|
||||
|
||||
When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
|
||||
[..]
|
||||
When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registering feature is not available
|
||||
and weak (surcharged) callbacks are used.
|
||||
|
||||
|
@ -189,6 +197,7 @@
|
|||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define I2S_TIMEOUT_FLAG 100U /*!< Timeout 100 ms */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
@ -328,7 +337,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
|
|||
/* I2S standard */
|
||||
if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
|
||||
{
|
||||
/* In I2S standard packet lenght is multiplied by 2 */
|
||||
/* In I2S standard packet length is multiplied by 2 */
|
||||
packetlength = packetlength * 2U;
|
||||
}
|
||||
|
||||
|
@ -412,7 +421,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
|
|||
/* Write to SPIx I2SCFGR */
|
||||
SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
|
||||
}
|
||||
#endif
|
||||
#endif /* SPI_I2SCFGR_ASTRTEN */
|
||||
|
||||
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
|
||||
hi2s->State = HAL_I2S_STATE_READY;
|
||||
|
@ -506,7 +515,8 @@ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
|
|||
* @param pCallback pointer to the Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
|
||||
pI2S_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -742,7 +752,7 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @param Timeout Timeout duration
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
|
@ -831,7 +841,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
|
|||
}
|
||||
|
||||
/* Check if Slave mode is selected */
|
||||
if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
|
||||
if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
|
||||
|| ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
|
||||
{
|
||||
/* Wait until Busy flag is reset */
|
||||
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
|
||||
|
@ -858,7 +869,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @param Timeout Timeout duration
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
|
@ -959,7 +970,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
* @retval HAL status
|
||||
|
@ -1023,7 +1034,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
* @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
|
||||
|
@ -1089,7 +1100,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
* @retval HAL status
|
||||
|
@ -1140,7 +1151,10 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
|
|||
hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
|
||||
|
||||
/* Enable the Tx DMA Stream/Channel */
|
||||
if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize))
|
||||
if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx,
|
||||
(uint32_t)hi2s->pTxBuffPtr,
|
||||
(uint32_t)&hi2s->Instance->DR,
|
||||
hi2s->TxXferSize))
|
||||
{
|
||||
/* Update SPI error code */
|
||||
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
|
||||
|
@ -1177,7 +1191,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
* @retval HAL status
|
||||
|
@ -1236,7 +1250,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
|
|||
}
|
||||
|
||||
/* Enable the Rx DMA Stream/Channel */
|
||||
if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize))
|
||||
if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr,
|
||||
hi2s->RxXferSize))
|
||||
{
|
||||
/* Update SPI error code */
|
||||
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
|
||||
|
@ -1350,35 +1365,86 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
|
|||
and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
|
||||
*/
|
||||
|
||||
/* Disable the I2S Tx/Rx DMA requests */
|
||||
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
|
||||
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
|
||||
|
||||
/* Abort the I2S DMA tx Stream/Channel */
|
||||
if (hi2s->hdmatx != NULL)
|
||||
if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
|
||||
{
|
||||
/* Disable the I2S DMA tx Stream/Channel */
|
||||
if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
|
||||
/* Abort the I2S DMA tx Stream/Channel */
|
||||
if (hi2s->hdmatx != NULL)
|
||||
{
|
||||
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
|
||||
errorcode = HAL_ERROR;
|
||||
/* Disable the I2S DMA tx Stream/Channel */
|
||||
if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
|
||||
{
|
||||
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
|
||||
errorcode = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Wait until TXE flag is set */
|
||||
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK)
|
||||
{
|
||||
/* Set the error code */
|
||||
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
|
||||
hi2s->State = HAL_I2S_STATE_READY;
|
||||
errorcode = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Wait until BSY flag is Reset */
|
||||
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK)
|
||||
{
|
||||
/* Set the error code */
|
||||
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
|
||||
hi2s->State = HAL_I2S_STATE_READY;
|
||||
errorcode = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Disable I2S peripheral */
|
||||
__HAL_I2S_DISABLE(hi2s);
|
||||
|
||||
/* Clear UDR flag */
|
||||
__HAL_I2S_CLEAR_UDRFLAG(hi2s);
|
||||
|
||||
/* Disable the I2S Tx DMA requests */
|
||||
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
|
||||
|
||||
}
|
||||
|
||||
/* Abort the I2S DMA rx Stream/Channel */
|
||||
if (hi2s->hdmarx != NULL)
|
||||
else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
|
||||
{
|
||||
/* Disable the I2S DMA rx Stream/Channel */
|
||||
if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
|
||||
/* Abort the I2S DMA rx Stream/Channel */
|
||||
if (hi2s->hdmarx != NULL)
|
||||
{
|
||||
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
|
||||
/* Disable the I2S DMA rx Stream/Channel */
|
||||
if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
|
||||
{
|
||||
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
|
||||
errorcode = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable I2S peripheral */
|
||||
__HAL_I2S_DISABLE(hi2s);
|
||||
|
||||
/* Clear OVR flag */
|
||||
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
|
||||
|
||||
/* Disable the I2S Rx DMA request */
|
||||
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
|
||||
|
||||
if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
|
||||
{
|
||||
/* Set the error code */
|
||||
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
|
||||
|
||||
/* Set the I2S State ready */
|
||||
hi2s->State = HAL_I2S_STATE_READY;
|
||||
errorcode = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Read DR to Flush RX Data */
|
||||
READ_REG((hi2s->Instance)->DR);
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable I2S peripheral */
|
||||
__HAL_I2S_DISABLE(hi2s);
|
||||
|
||||
hi2s->State = HAL_I2S_STATE_READY;
|
||||
|
||||
return errorcode;
|
||||
|
@ -1814,7 +1880,8 @@ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
|
|||
* @param Timeout Duration of the timeout
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout)
|
||||
static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
|
|
|
@ -40,7 +40,8 @@
|
|||
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
|
||||
(+++) Configure the DMA Tx/Rx channel.
|
||||
(+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
|
||||
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
|
||||
(+++) Configure the priority and enable the NVIC for the transfer
|
||||
complete interrupt on the DMA Tx/Rx channel.
|
||||
|
||||
(#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
|
||||
the normal or low power mode and the clock prescaler in the hirda handle Init structure.
|
||||
|
@ -610,43 +611,45 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
|
|||
switch (CallbackID)
|
||||
{
|
||||
case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
|
||||
hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
|
||||
hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_TX_COMPLETE_CB_ID :
|
||||
hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
|
||||
hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
|
||||
hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_RX_COMPLETE_CB_ID :
|
||||
hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
|
||||
hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_ERROR_CB_ID :
|
||||
hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_ABORT_COMPLETE_CB_ID :
|
||||
hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
|
||||
hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
|
||||
hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
|
||||
hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak
|
||||
AbortTransmitCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
|
||||
hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
|
||||
hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak
|
||||
AbortReceiveCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_MSPINIT_CB_ID :
|
||||
hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
|
||||
hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_MSPDEINIT_CB_ID :
|
||||
hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
|
||||
hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
|
||||
break;
|
||||
|
||||
default :
|
||||
|
@ -769,13 +772,16 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
|
|||
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
|
||||
Errors are handled as follows :
|
||||
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
|
||||
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
|
||||
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
|
||||
and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
|
||||
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
|
||||
in Interrupt mode reception .
|
||||
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
|
||||
to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
|
||||
Transfer is kept ongoing on IRDA side.
|
||||
If user wants to abort it, Abort services should be called by user.
|
||||
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
|
||||
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
|
||||
Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
|
||||
Error code is set to allow user to identify error type, and
|
||||
HAL_IRDA_ErrorCallback() user callback is executed.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
|
@ -813,7 +819,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
|
|||
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
|
||||
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
|
||||
|
||||
/* Init tickstart for timeout managment*/
|
||||
/* Init tickstart for timeout management */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
hirda->TxXferSize = Size;
|
||||
|
@ -903,7 +909,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
|
|||
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
|
||||
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
|
||||
|
||||
/* Init tickstart for timeout managment*/
|
||||
/* Init tickstart for timeout management */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
hirda->RxXferSize = Size;
|
||||
|
@ -1278,7 +1284,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
|
|||
/* Clear the Overrun flag before resuming the Rx transfer*/
|
||||
__HAL_IRDA_CLEAR_OREFLAG(hirda);
|
||||
|
||||
/* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
||||
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
||||
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
|
||||
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
|
@ -2314,7 +2320,7 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
|
|||
/* Initialize the IRDA ErrorCode */
|
||||
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
|
||||
|
||||
/* Init tickstart for timeout managment*/
|
||||
/* Init tickstart for timeout management */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Check if the Transmitter is enabled */
|
||||
|
@ -2359,7 +2365,8 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
|
|||
{
|
||||
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
||||
{
|
||||
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
|
||||
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
|
||||
interrupts for the interrupt process */
|
||||
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
|
||||
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
|
|
|
@ -16,52 +16,62 @@
|
|||
(+) The IWDG can be started by either software or hardware (configurable
|
||||
through option byte).
|
||||
|
||||
(+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
|
||||
if the main clock fails.
|
||||
(+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
|
||||
active even if the main clock fails.
|
||||
|
||||
(+) Once the IWDG is started, the LSI is forced ON and both can not be
|
||||
(+) Once the IWDG is started, the LSI is forced ON and both cannot be
|
||||
disabled. The counter starts counting down from the reset value (0xFFF).
|
||||
When it reaches the end of count value (0x000) a reset signal is
|
||||
generated (IWDG reset).
|
||||
|
||||
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
|
||||
the IWDG_RLR value is reloaded in the counter and the watchdog reset is
|
||||
prevented.
|
||||
the IWDG_RLR value is reloaded into the counter and the watchdog reset
|
||||
is prevented.
|
||||
|
||||
(+) The IWDG is implemented in the VDD voltage domain that is still functional
|
||||
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
|
||||
in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
|
||||
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
|
||||
reset occurs.
|
||||
|
||||
(+) Debug mode : When the microcontroller enters debug mode (core halted),
|
||||
(+) Debug mode: When the microcontroller enters debug mode (core halted),
|
||||
the IWDG counter either continues to work normally or stops, depending
|
||||
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
|
||||
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
|
||||
|
||||
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
|
||||
The IWDG timeout may vary due to LSI frequency dispersion. STM32F7xx
|
||||
devices provide the capability to measure the LSI frequency (LSI clock
|
||||
connected internally to TIM16 CH1 input capture). The measured value
|
||||
can be used to have an IWDG timeout with an acceptable accuracy.
|
||||
The IWDG timeout may vary due to LSI clock frequency dispersion.
|
||||
STM32F7xx devices provide the capability to measure the LSI clock
|
||||
frequency (LSI clock is internally connected to TIM16 CH1 input capture).
|
||||
The measured value can be used to have an IWDG timeout with an
|
||||
acceptable accuracy.
|
||||
|
||||
[..] Default timeout value (necessary for IWDG_SR status register update):
|
||||
Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
|
||||
This frequency being subject to variations as mentioned above, the
|
||||
default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
|
||||
below) may become too short or too long.
|
||||
In such cases, this default timeout value can be tuned by redefining
|
||||
the constant LSI_VALUE at user-application level (based, for instance,
|
||||
on the measured LSI clock frequency as explained above).
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Use IWDG using HAL_IWDG_Init() function to :
|
||||
(+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
|
||||
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
|
||||
clock is forced ON and IWDG counter starts counting down.
|
||||
(+) Enable write access to configuration registers:
|
||||
(++) Enable write access to configuration registers:
|
||||
IWDG_PR, IWDG_RLR and IWDG_WINR.
|
||||
(+) Configure the IWDG prescaler and counter reload value. This reload
|
||||
(++) Configure the IWDG prescaler and counter reload value. This reload
|
||||
value will be loaded in the IWDG counter each time the watchdog is
|
||||
reloaded, then the IWDG will start counting down from this value.
|
||||
(+) Wait for status flags to be reset.
|
||||
(+) Depending on window parameter:
|
||||
(++) If Window Init parameter is same as Window register value,
|
||||
(++) Depending on window parameter:
|
||||
(+++) If Window Init parameter is same as Window register value,
|
||||
nothing more is done but reload counter value in order to exit
|
||||
function with exact time base.
|
||||
(++) Else modify Window register. This will automatically reload
|
||||
(+++) Else modify Window register. This will automatically reload
|
||||
watchdog counter.
|
||||
(++) Wait for status flags to be reset.
|
||||
|
||||
(#) Then the application program must refresh the IWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
|
@ -108,10 +118,15 @@
|
|||
/** @defgroup IWDG_Private_Defines IWDG Private Defines
|
||||
* @{
|
||||
*/
|
||||
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
|
||||
higher prescaler (256), and according to LSI variation, we need to wait at
|
||||
least 6 cycles so 48 ms. */
|
||||
#define HAL_IWDG_DEFAULT_TIMEOUT 48u
|
||||
/* Status register needs up to 5 LSI clock periods divided by the clock
|
||||
prescaler to be updated. The number of LSI clock periods is upper-rounded to
|
||||
6 for the timeout value calculation.
|
||||
The timeout value is also calculated using the highest prescaler (256) and
|
||||
the LSI_VALUE constant. The value of this constant can be changed by the user
|
||||
to take into account possible LSI clock period variations.
|
||||
The timeout value is multiplied by 1000 to be converted in milliseconds. */
|
||||
#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
|
||||
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -126,8 +141,8 @@
|
|||
*/
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions_Group1
|
||||
* @brief Initialization and Start functions.
|
||||
*
|
||||
* @brief Initialization and Start functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Start functions #####
|
||||
|
@ -182,11 +197,14 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
|||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for register to be updated */
|
||||
while (hiwdg->Instance->SR != 0x00u)
|
||||
while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -209,14 +227,15 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions_Group2
|
||||
* @brief IO operation functions
|
||||
*
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
|
@ -228,7 +247,6 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
|||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Refresh the IWDG.
|
||||
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
|
||||
|
@ -244,6 +262,7 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -223,15 +223,15 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_JPEG_MODULE_ENABLED
|
||||
|
||||
#if defined (JPEG)
|
||||
|
||||
/** @defgroup JPEG JPEG
|
||||
* @brief JPEG HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_JPEG_MODULE_ENABLED
|
||||
|
||||
#if defined (JPEG)
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup JPEG_Private_Constants
|
||||
* @{
|
||||
|
@ -1116,7 +1116,11 @@ HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg
|
|||
HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf)
|
||||
{
|
||||
uint32_t error;
|
||||
uint32_t numberMCU, hfactor, vfactor, hMCU, vMCU;
|
||||
uint32_t numberMCU;
|
||||
uint32_t hfactor;
|
||||
uint32_t vfactor;
|
||||
uint32_t hMCU;
|
||||
uint32_t vMCU;
|
||||
|
||||
/* Check the JPEG handle allocation */
|
||||
if ((hjpeg == NULL) || (pConf == NULL))
|
||||
|
@ -1296,12 +1300,14 @@ HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTy
|
|||
* @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains
|
||||
* the configuration information for JPEG module
|
||||
* @param pInfo pointer to a JPEG_ConfTypeDef structure that contains
|
||||
* The JPEG decoded header informations
|
||||
* The JPEG decoded header information
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
|
||||
{
|
||||
uint32_t yblockNb, cBblockNb, cRblockNb;
|
||||
uint32_t yblockNb;
|
||||
uint32_t cBblockNb;
|
||||
uint32_t cRblockNb;
|
||||
|
||||
/* Check the JPEG handle allocation */
|
||||
if ((hjpeg == NULL) || (pInfo == NULL))
|
||||
|
@ -2185,7 +2191,8 @@ void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputB
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg)
|
||||
{
|
||||
uint32_t tickstart, tmpContext;
|
||||
uint32_t tickstart;
|
||||
uint32_t tmpContext;
|
||||
tmpContext = hjpeg->Context;
|
||||
|
||||
/*Reset the Context operation and method*/
|
||||
|
@ -2301,7 +2308,7 @@ HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg)
|
|||
* @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains
|
||||
* the configuration information for JPEG module
|
||||
* @param pInfo pointer to a JPEG_ConfTypeDef structure that contains
|
||||
* The JPEG decoded header informations
|
||||
* The JPEG decoded header information
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
|
||||
|
@ -2512,12 +2519,16 @@ uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg)
|
|||
* @param Bits pointer to bits table
|
||||
* @param Huffsize pointer to sizes table
|
||||
* @param Huffcode pointer to codes table
|
||||
* @param LastK pointer to last Coeff (table dimmension)
|
||||
* @param LastK pointer to last Coeff (table dimension)
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK)
|
||||
{
|
||||
uint32_t i, p, l, code, si;
|
||||
uint32_t i;
|
||||
uint32_t p;
|
||||
uint32_t l;
|
||||
uint32_t code;
|
||||
uint32_t si;
|
||||
|
||||
/* Figure C.1: Generation of table of Huffman code sizes */
|
||||
p = 0;
|
||||
|
@ -2683,7 +2694,9 @@ static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCH
|
|||
{
|
||||
HAL_StatusTypeDef error;
|
||||
JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable;
|
||||
uint32_t i, lsb, msb;
|
||||
uint32_t i;
|
||||
uint32_t lsb;
|
||||
uint32_t msb;
|
||||
__IO uint32_t *address, *addressDef;
|
||||
|
||||
if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC0))
|
||||
|
@ -3048,7 +3061,11 @@ static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg)
|
|||
static uint32_t JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable,
|
||||
__IO uint32_t *QTableAddress)
|
||||
{
|
||||
uint32_t i, j, quantRow, quantVal, ScaleFactor;
|
||||
uint32_t i;
|
||||
uint32_t j;
|
||||
uint32_t quantRow;
|
||||
uint32_t quantVal;
|
||||
uint32_t ScaleFactor;
|
||||
__IO uint32_t *tableAddress;
|
||||
|
||||
tableAddress = QTableAddress;
|
||||
|
@ -3308,12 +3325,12 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg)
|
|||
{
|
||||
uint32_t tmpContext;
|
||||
|
||||
/*End of header processing flag rised*/
|
||||
/*End of header processing flag */
|
||||
if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
|
||||
{
|
||||
if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != 0UL)
|
||||
{
|
||||
/*Call Header parsing complet callback */
|
||||
/*Call Header parsing complete callback */
|
||||
(void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);
|
||||
/* Reset the ImageQuality */
|
||||
hjpeg->Conf.ImageQuality = 0;
|
||||
|
@ -3339,13 +3356,13 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg)
|
|||
{
|
||||
if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFTF) != 0UL)
|
||||
{
|
||||
/*Input FIFO threshold flag rised*/
|
||||
/*Input FIFO threshold flag */
|
||||
/*JPEG_FIFO_TH_SIZE words can be written in */
|
||||
JPEG_ReadInputData(hjpeg, JPEG_FIFO_TH_SIZE);
|
||||
}
|
||||
else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFNFF) != 0UL)
|
||||
{
|
||||
/*Input FIFO Not Full flag rised*/
|
||||
/*Input FIFO Not Full flag */
|
||||
/*32-bit value can be written in */
|
||||
JPEG_ReadInputData(hjpeg, 1);
|
||||
}
|
||||
|
@ -3361,13 +3378,13 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg)
|
|||
{
|
||||
if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFTF) != 0UL)
|
||||
{
|
||||
/*Output FIFO threshold flag rised*/
|
||||
/*Output FIFO threshold flag */
|
||||
/*JPEG_FIFO_TH_SIZE words can be read out */
|
||||
JPEG_StoreOutputData(hjpeg, JPEG_FIFO_TH_SIZE);
|
||||
}
|
||||
else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0UL)
|
||||
{
|
||||
/*Output FIFO Not Empty flag rised*/
|
||||
/*Output FIFO Not Empty flag */
|
||||
/*32-bit value can be read out */
|
||||
JPEG_StoreOutputData(hjpeg, 1);
|
||||
}
|
||||
|
@ -3452,7 +3469,10 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg)
|
|||
*/
|
||||
static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords)
|
||||
{
|
||||
uint32_t index, nBwords, nbBytes, dataword;
|
||||
uint32_t index;
|
||||
uint32_t nb_words;
|
||||
uint32_t nb_bytes;
|
||||
uint32_t dataword;
|
||||
|
||||
if (hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords * 4UL)))
|
||||
{
|
||||
|
@ -3479,8 +3499,8 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor
|
|||
}
|
||||
else if (hjpeg->OutDataLength > hjpeg->JpegOutCount)
|
||||
{
|
||||
nBwords = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL;
|
||||
for (index = 0; index < nBwords; index++)
|
||||
nb_words = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL;
|
||||
for (index = 0; index < nb_words; index++)
|
||||
{
|
||||
/*Transfer 32 bits from the JPEG output FIFO*/
|
||||
dataword = hjpeg->Instance->DOR;
|
||||
|
@ -3502,9 +3522,9 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor
|
|||
}
|
||||
else
|
||||
{
|
||||
nbBytes = hjpeg->OutDataLength - hjpeg->JpegOutCount;
|
||||
nb_bytes = hjpeg->OutDataLength - hjpeg->JpegOutCount;
|
||||
dataword = hjpeg->Instance->DOR;
|
||||
for (index = 0; index < nbBytes; index++)
|
||||
for (index = 0; index < nb_bytes; index++)
|
||||
{
|
||||
hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * (index & 0x3UL))) & 0xFFUL);
|
||||
hjpeg->JpegOutCount++;
|
||||
|
@ -3518,8 +3538,8 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor
|
|||
|
||||
hjpeg->JpegOutCount = 0;
|
||||
|
||||
nbBytes = 4UL - nbBytes;
|
||||
for (index = nbBytes; index < 4UL; index++)
|
||||
nb_bytes = 4UL - nb_bytes;
|
||||
for (index = nb_bytes; index < 4UL; index++)
|
||||
{
|
||||
hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * index)) & 0xFFUL);
|
||||
hjpeg->JpegOutCount++;
|
||||
|
@ -3543,7 +3563,11 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor
|
|||
*/
|
||||
static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords)
|
||||
{
|
||||
uint32_t nbBytes = 0, nBwords, index, Dataword, inputCount;
|
||||
uint32_t nb_bytes = 0;
|
||||
uint32_t nb_words;
|
||||
uint32_t index;
|
||||
uint32_t dataword;
|
||||
uint32_t input_count;
|
||||
|
||||
if ((hjpeg->InDataLength == 0UL) || (nbRequestWords == 0UL))
|
||||
{
|
||||
|
@ -3552,7 +3576,7 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord
|
|||
}
|
||||
else if (hjpeg->InDataLength > hjpeg->JpegInCount)
|
||||
{
|
||||
nbBytes = hjpeg->InDataLength - hjpeg->JpegInCount;
|
||||
nb_bytes = hjpeg->InDataLength - hjpeg->JpegInCount;
|
||||
}
|
||||
else if (hjpeg->InDataLength == hjpeg->JpegInCount)
|
||||
{
|
||||
|
@ -3568,39 +3592,39 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord
|
|||
hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL);
|
||||
}
|
||||
hjpeg->JpegInCount = 0;
|
||||
nbBytes = hjpeg->InDataLength;
|
||||
nb_bytes = hjpeg->InDataLength;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Nothing to do */
|
||||
}
|
||||
if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nbBytes > 0UL))
|
||||
if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nb_bytes > 0UL))
|
||||
{
|
||||
nBwords = nbBytes / 4UL;
|
||||
if (nBwords >= nbRequestWords)
|
||||
nb_words = nb_bytes / 4UL;
|
||||
if (nb_words >= nbRequestWords)
|
||||
{
|
||||
for (index = 0; index < nbRequestWords; index++)
|
||||
{
|
||||
inputCount = hjpeg->JpegInCount;
|
||||
hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | \
|
||||
(((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1UL])) << 8) | \
|
||||
(((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2UL])) << 16) | \
|
||||
(((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3UL])) << 24));
|
||||
input_count = hjpeg->JpegInCount;
|
||||
hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \
|
||||
(((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \
|
||||
(((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \
|
||||
(((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24));
|
||||
|
||||
hjpeg->JpegInCount += 4UL;
|
||||
}
|
||||
}
|
||||
else /*nBwords < nbRequestWords*/
|
||||
else /*nb_words < nbRequestWords*/
|
||||
{
|
||||
if (nBwords > 0UL)
|
||||
if (nb_words > 0UL)
|
||||
{
|
||||
for (index = 0; index < nBwords; index++)
|
||||
for (index = 0; index < nb_words; index++)
|
||||
{
|
||||
inputCount = hjpeg->JpegInCount;
|
||||
hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | \
|
||||
(((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1UL])) << 8) | \
|
||||
(((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2UL])) << 16) | \
|
||||
(((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3UL])) << 24));
|
||||
input_count = hjpeg->JpegInCount;
|
||||
hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \
|
||||
(((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \
|
||||
(((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \
|
||||
(((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24));
|
||||
|
||||
hjpeg->JpegInCount += 4UL;
|
||||
}
|
||||
|
@ -3608,13 +3632,13 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord
|
|||
else
|
||||
{
|
||||
/* end of file*/
|
||||
Dataword = 0;
|
||||
for (index = 0; index < nbBytes; index++)
|
||||
dataword = 0;
|
||||
for (index = 0; index < nb_bytes; index++)
|
||||
{
|
||||
Dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL));
|
||||
dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL));
|
||||
hjpeg->JpegInCount++;
|
||||
}
|
||||
hjpeg->Instance->DIR = Dataword;
|
||||
hjpeg->Instance->DIR = dataword;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -3650,10 +3674,10 @@ static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg)
|
|||
/* Set the DMA Out Abort callback */
|
||||
hjpeg->hdmaout->XferAbortCallback = JPEG_DMAOutAbortCallback;
|
||||
|
||||
/*DMA transfer size must be a multiple of 4 bytes i.e mutliple of 32bits words*/
|
||||
/*DMA transfer size must be a multiple of 4 bytes i.e multiple of 32bits words*/
|
||||
hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL);
|
||||
|
||||
/*DMA transfer size must be a multiple of 4 bytes i.e mutliple of 32bits words*/
|
||||
/*DMA transfer size must be a multiple of 4 bytes i.e multiple of 32bits words*/
|
||||
hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % 4UL);
|
||||
|
||||
/* Start DMA FIFO In transfer */
|
||||
|
@ -3791,7 +3815,7 @@ static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg)
|
|||
hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
|
||||
|
||||
tmpContext = hjpeg->Context;
|
||||
/*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
|
||||
/*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
|
||||
hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
|
||||
|
||||
/* Process Unlocked */
|
||||
|
@ -3837,7 +3861,9 @@ static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg)
|
|||
*/
|
||||
static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg)
|
||||
{
|
||||
uint32_t tmpContext, count, dataOut;
|
||||
uint32_t tmpContext;
|
||||
uint32_t count;
|
||||
uint32_t dataOut;
|
||||
|
||||
for (count = JPEG_FIFO_SIZE; count > 0UL; count--)
|
||||
{
|
||||
|
@ -3888,7 +3914,7 @@ static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg)
|
|||
}
|
||||
|
||||
tmpContext = hjpeg->Context;
|
||||
/*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
|
||||
/*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
|
||||
hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
|
||||
|
||||
/* Process Unlocked */
|
||||
|
@ -4127,11 +4153,12 @@ static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg)
|
|||
* @}
|
||||
*/
|
||||
|
||||
#endif /* JPEG */
|
||||
#endif /* HAL_JPEG_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* JPEG */
|
||||
#endif /* HAL_JPEG_MODULE_ENABLED */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
@ -194,8 +194,8 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t
|
|||
*/
|
||||
|
||||
/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
|
@ -232,19 +232,17 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
|
|||
|
||||
assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
|
||||
assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
|
||||
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
|| (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
{
|
||||
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
|
||||
assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
|
||||
}
|
||||
assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
|
||||
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
|
||||
{
|
||||
assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
|
||||
}
|
||||
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
|
||||
{
|
||||
assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
|
||||
assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
|
||||
}
|
||||
assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
|
||||
assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
|
||||
|
@ -278,21 +276,18 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
|
|||
/* Get the LPTIMx CFGR value */
|
||||
tmpcfgr = hlptim->Instance->CFGR;
|
||||
|
||||
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
|| (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
{
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL));
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
|
||||
}
|
||||
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
|
||||
{
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL));
|
||||
}
|
||||
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
|
||||
{
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT));
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
|
||||
}
|
||||
|
||||
/* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
|
||||
/* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
|
||||
LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
|
||||
|
||||
/* Set initialization parameters */
|
||||
|
@ -311,19 +306,21 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
|
|||
hlptim->Init.UltraLowPowerClock.SampleTime);
|
||||
}
|
||||
|
||||
/* Configure the active edge or edges used by the counter only if LPTIM is
|
||||
* clocked by an external clock source
|
||||
*/
|
||||
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
/* Configure LPTIM external clock polarity and digital filter */
|
||||
if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
|| (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
{
|
||||
tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity);
|
||||
tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
|
||||
hlptim->Init.UltraLowPowerClock.SampleTime);
|
||||
}
|
||||
|
||||
/* Configure LPTIM external trigger */
|
||||
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
|
||||
{
|
||||
/* Enable External trigger and set the trigger source */
|
||||
tmpcfgr |= (hlptim->Init.Trigger.Source |
|
||||
hlptim->Init.Trigger.ActiveEdge);
|
||||
tmpcfgr |= (hlptim->Init.Trigger.Source |
|
||||
hlptim->Init.Trigger.ActiveEdge |
|
||||
hlptim->Init.Trigger.SampleTime);
|
||||
}
|
||||
|
||||
/* Write to LPTIMx CFGR */
|
||||
|
@ -418,8 +415,8 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
|
|||
*/
|
||||
|
||||
/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
|
||||
* @brief Start-Stop operation functions.
|
||||
*
|
||||
* @brief Start-Stop operation functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### LPTIM Start Stop operation functions #####
|
||||
|
@ -1548,7 +1545,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
|
|||
hlptim->State = HAL_LPTIM_STATE_BUSY;
|
||||
|
||||
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
|
||||
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
&& (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
{
|
||||
/* Check if clock is prescaled */
|
||||
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
|
||||
|
@ -1631,7 +1629,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
|
|||
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
|
||||
|
||||
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
|
||||
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
&& (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
{
|
||||
/* Check if clock is prescaled */
|
||||
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
|
||||
|
@ -1724,8 +1723,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
|
|||
*/
|
||||
|
||||
/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
|
||||
* @brief Read operation functions.
|
||||
*
|
||||
* @brief Read operation functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### LPTIM Read operation functions #####
|
||||
|
@ -1782,8 +1781,8 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
|
|||
*/
|
||||
|
||||
/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
|
||||
* @brief LPTIM IRQ handler.
|
||||
*
|
||||
* @brief LPTIM IRQ handler.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### LPTIM IRQ handler and callbacks #####
|
||||
|
@ -2251,8 +2250,8 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti
|
|||
*/
|
||||
|
||||
/** @defgroup LPTIM_Group5 Peripheral State functions
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral State functions #####
|
||||
|
@ -2327,8 +2326,7 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t
|
|||
{
|
||||
result = HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
|
||||
} while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
|
@ -54,8 +54,8 @@
|
|||
-@@- HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt
|
||||
and execute the previous callbacks
|
||||
|
||||
(#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API.
|
||||
(##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources
|
||||
(#) Reset the MDIOS peripheral and all related resources by calling the HAL_MDIOS_DeInit() API.
|
||||
(##) HAL_MDIOS_MspDeInit() must be implemented to reset low level resources
|
||||
(GPIO, Clocks, NVIC configuration ...)
|
||||
|
||||
*** Callback registration ***
|
||||
|
|
|
@ -287,6 +287,7 @@
|
|||
static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc);
|
||||
static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc);
|
||||
static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus);
|
||||
static uint32_t MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout);
|
||||
static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc);
|
||||
static void MMC_Write_IT(MMC_HandleTypeDef *hmmc);
|
||||
static void MMC_Read_IT(MMC_HandleTypeDef *hmmc);
|
||||
|
@ -444,6 +445,17 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
|
|||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= errorstate;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
@ -584,17 +596,6 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= errorstate;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure the MMC DPSM (Data Path State Machine) */
|
||||
config.DataTimeOut = SDMMC_DATATIMEOUT;
|
||||
config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
|
||||
|
@ -796,17 +797,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= errorstate;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write Blocks in Polling mode */
|
||||
if(NumberOfBlocks > 1U)
|
||||
{
|
||||
|
@ -984,17 +974,6 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= errorstate;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure the MMC DPSM (Data Path State Machine) */
|
||||
config.DataTimeOut = SDMMC_DATATIMEOUT;
|
||||
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
|
||||
|
@ -1088,17 +1067,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= errorstate;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write Blocks in Polling mode */
|
||||
if(NumberOfBlocks > 1U)
|
||||
{
|
||||
|
@ -1196,16 +1164,9 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
|
||||
hmmc->ErrorCode = errorstate;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Force DMA Direction */
|
||||
hmmc->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||
MODIFY_REG(hmmc->hdmarx->Instance->CR, DMA_SxCR_DIR, hmmc->hdmarx->Init.Direction);
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
if(HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK)
|
||||
|
@ -1321,16 +1282,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= errorstate;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write Blocks in Polling mode */
|
||||
if(NumberOfBlocks > 1U)
|
||||
|
@ -1360,6 +1311,10 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat
|
|||
/* Enable SDMMC DMA transfer */
|
||||
__HAL_MMC_DMA_ENABLE(hmmc);
|
||||
|
||||
/* Force DMA Direction */
|
||||
hmmc->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH;
|
||||
MODIFY_REG(hmmc->hdmatx->Instance->CR, DMA_SxCR_DIR, hmmc->hdmatx->Init.Direction);
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
if(HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK)
|
||||
{
|
||||
|
@ -1997,6 +1952,8 @@ HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTyp
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
|
||||
{
|
||||
uint32_t block_nbr = 0;
|
||||
|
||||
pCSD->CSDStruct = (uint8_t)((hmmc->CSD[0] & 0xC0000000U) >> 30U);
|
||||
|
||||
pCSD->SysSpecVersion = (uint8_t)((hmmc->CSD[0] & 0x3C000000U) >> 26U);
|
||||
|
@ -2035,12 +1992,34 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp
|
|||
|
||||
pCSD->DeviceSizeMul = (uint8_t)((hmmc->CSD[2] & 0x00038000U) >> 15U);
|
||||
|
||||
hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
|
||||
hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
|
||||
hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
|
||||
if(MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
|
||||
hmmc->MmcCard.LogBlockSize = 512U;
|
||||
if(hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD)
|
||||
{
|
||||
hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
|
||||
hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
|
||||
hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
|
||||
hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
|
||||
hmmc->MmcCard.LogBlockSize = 512U;
|
||||
}
|
||||
else if(hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD)
|
||||
{
|
||||
hmmc->MmcCard.BlockNbr = block_nbr;
|
||||
hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr;
|
||||
hmmc->MmcCard.BlockSize = 512U;
|
||||
hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
pCSD->EraseGrSize = (uint8_t)((hmmc->CSD[2] & 0x00004000U) >> 14U);
|
||||
|
||||
|
@ -2122,7 +2101,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32
|
|||
/* Check the parameters */
|
||||
assert_param(IS_SDMMC_BUS_WIDE(WideMode));
|
||||
|
||||
/* Chnage Satte */
|
||||
/* Change State */
|
||||
hmmc->State = HAL_MMC_STATE_BUSY;
|
||||
|
||||
/* Update Clock for Bus mode update */
|
||||
|
@ -2762,6 +2741,93 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
|
|||
return HAL_MMC_ERROR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads extended CSD register to get the sectors number of the device
|
||||
* @param hmmc: Pointer to MMC handle
|
||||
* @param pFieldData: Pointer to the read buffer
|
||||
* @param FieldIndex: Index of the field to be read
|
||||
* @param Timeout: Specify timeout value
|
||||
* @retval HAL status
|
||||
*/
|
||||
static uint32_t MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout)
|
||||
{
|
||||
SDMMC_DataInitTypeDef config;
|
||||
uint32_t errorstate;
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
uint32_t count;
|
||||
uint32_t i = 0;
|
||||
uint32_t tmp_data;
|
||||
|
||||
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
|
||||
|
||||
/* Initialize data control register */
|
||||
hmmc->Instance->DCTRL = 0;
|
||||
|
||||
/* Configure the MMC DPSM (Data Path State Machine) */
|
||||
config.DataTimeOut = SDMMC_DATATIMEOUT;
|
||||
config.DataLength = 512;
|
||||
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
|
||||
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
|
||||
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
|
||||
config.DPSM = SDMMC_DPSM_ENABLE;
|
||||
(void)SDMMC_ConfigData(hmmc->Instance, &config);
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= errorstate;
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Poll on SDMMC flags */
|
||||
while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
|
||||
{
|
||||
if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
|
||||
{
|
||||
/* Read data from SDMMC Rx FIFO */
|
||||
for(count = 0U; count < 8U; count++)
|
||||
{
|
||||
tmp_data = SDMMC_ReadFIFO(hmmc->Instance);
|
||||
/* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */
|
||||
/* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */
|
||||
if ((i + count) == ((uint32_t)FieldIndex/4U))
|
||||
{
|
||||
*pFieldData = tmp_data;
|
||||
}
|
||||
}
|
||||
i += 8U;
|
||||
}
|
||||
|
||||
if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
|
||||
hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
|
||||
hmmc->State= HAL_MMC_STATE_READY;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
|
||||
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
|
||||
if(errorstate != HAL_MMC_ERROR_NONE)
|
||||
{
|
||||
hmmc->ErrorCode |= errorstate;
|
||||
}
|
||||
|
||||
/* Clear all the static flags */
|
||||
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
|
||||
|
||||
hmmc->State = HAL_MMC_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Wrap up reading in non-blocking mode.
|
||||
* @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
|
||||
|
|
|
@ -396,7 +396,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN
|
|||
/* Update the NAND controller state */
|
||||
hnand->State = HAL_NAND_STATE_BUSY;
|
||||
|
||||
/* Send Read ID command sequence */
|
||||
/* Send Read ID command sequence */
|
||||
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;
|
||||
__DSB();
|
||||
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
|
||||
|
@ -754,6 +754,17 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address
|
|||
__DSB();
|
||||
}
|
||||
|
||||
/* Calculate PageSize */
|
||||
if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
|
||||
{
|
||||
size = size / 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
/* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
|
||||
}
|
||||
|
||||
/* Get Data into Buffer */
|
||||
for(; index < size; index++)
|
||||
{
|
||||
|
@ -888,7 +899,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address
|
|||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
|
||||
/* Read status until NAND is ready */
|
||||
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
|
||||
{
|
||||
|
@ -1014,6 +1025,17 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres
|
|||
}
|
||||
}
|
||||
|
||||
/* Calculate PageSize */
|
||||
if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
|
||||
{
|
||||
size = size / 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
/* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
|
||||
}
|
||||
|
||||
/* Write data to memory */
|
||||
for(; index < size; index++)
|
||||
{
|
||||
|
@ -1238,7 +1260,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad
|
|||
nandAddress = ARRAY_ADDRESS(pAddress, hnand);
|
||||
|
||||
/* Column in page address */
|
||||
columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2);
|
||||
columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand));
|
||||
|
||||
/* Spare area(s) read loop */
|
||||
while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
|
||||
|
@ -1471,7 +1493,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad
|
|||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
|
||||
/* Read status until NAND is ready */
|
||||
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
|
||||
{
|
||||
|
@ -1534,7 +1556,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A
|
|||
nandAddress = ARRAY_ADDRESS(pAddress, hnand);
|
||||
|
||||
/* Column in page address */
|
||||
columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2);
|
||||
columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand));
|
||||
|
||||
/* Spare area(s) write loop */
|
||||
while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
|
||||
|
@ -1682,7 +1704,7 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy
|
|||
__DSB();
|
||||
*(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
|
||||
__DSB();
|
||||
|
||||
|
||||
*(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
|
||||
__DSB();
|
||||
|
||||
|
|
|
@ -102,8 +102,8 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint
|
|||
*/
|
||||
|
||||
/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
|
@ -250,7 +250,10 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
|
|||
hpcd->State = HAL_PCD_STATE_BUSY;
|
||||
|
||||
/* Stop Device */
|
||||
(void)HAL_PCD_Stop(hpcd);
|
||||
if (USB_StopDevice(hpcd->Instance) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
if (hpcd->MspDeInitCallback == NULL)
|
||||
|
@ -319,7 +322,9 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
|
|||
* @param pCallback pointer to the Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
|
||||
HAL_PCD_CallbackIDTypeDef CallbackID,
|
||||
pPCD_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -529,7 +534,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_Ca
|
|||
* @param pCallback pointer to the USB PCD Data OUT Stage Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_DataOutStageCallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -564,7 +570,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister the USB PCD Data OUT Stage Callback
|
||||
* @brief Unregister the USB PCD Data OUT Stage Callback
|
||||
* USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
|
@ -602,7 +608,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd
|
|||
* @param pCallback pointer to the USB PCD Data IN Stage Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_DataInStageCallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -637,7 +644,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, p
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister the USB PCD Data IN Stage Callback
|
||||
* @brief Unregister the USB PCD Data IN Stage Callback
|
||||
* USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
|
@ -675,7 +682,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
|
|||
* @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_IsoOutIncpltCallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -710,7 +718,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister the USB PCD Iso OUT incomplete Callback
|
||||
* @brief Unregister the USB PCD Iso OUT incomplete Callback
|
||||
* USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
|
@ -748,7 +756,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd
|
|||
* @param pCallback pointer to the USB PCD Iso IN incomplete Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_IsoInIncpltCallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -783,7 +792,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, p
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister the USB PCD Iso IN incomplete Callback
|
||||
* @brief Unregister the USB PCD Iso IN incomplete Callback
|
||||
* USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
|
@ -856,7 +865,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmC
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister the USB PCD LPM Callback
|
||||
* @brief Unregister the USB PCD LPM Callback
|
||||
* USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
|
@ -893,8 +902,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
|
|||
*/
|
||||
|
||||
/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
|
@ -915,9 +924,10 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
|
|||
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
__HAL_LOCK(hpcd);
|
||||
(void)USB_DevConnect(hpcd->Instance);
|
||||
__HAL_PCD_ENABLE(hpcd);
|
||||
(void)USB_DevConnect(hpcd->Instance);
|
||||
__HAL_UNLOCK(hpcd);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
@ -930,18 +940,15 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
|
|||
{
|
||||
__HAL_LOCK(hpcd);
|
||||
__HAL_PCD_DISABLE(hpcd);
|
||||
|
||||
if (USB_StopDevice(hpcd->Instance) != HAL_OK)
|
||||
{
|
||||
__HAL_UNLOCK(hpcd);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
(void)USB_DevDisconnect(hpcd->Instance);
|
||||
|
||||
(void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
|
||||
|
||||
__HAL_UNLOCK(hpcd);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
/**
|
||||
* @brief Handles PCD interrupt request.
|
||||
|
@ -971,7 +978,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|||
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
|
||||
}
|
||||
|
||||
/* Handle RxQLevel Interrupt */
|
||||
/* Handle RxQLevel Interrupt */
|
||||
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
|
||||
{
|
||||
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
||||
|
@ -1326,6 +1333,30 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Handles PCD Wakeup interrupt request.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
USB_OTG_GlobalTypeDef *USBx;
|
||||
|
||||
USBx = hpcd->Instance;
|
||||
|
||||
if ((USBx->CID & (0x1U << 8)) == 0U)
|
||||
{
|
||||
/* Clear EXTI pending Bit */
|
||||
__HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear EXTI pending Bit */
|
||||
__HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG();
|
||||
}
|
||||
}
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
|
||||
|
@ -1506,8 +1537,8 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
|
|||
*/
|
||||
|
||||
/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
|
@ -1530,6 +1561,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
|
|||
__HAL_LOCK(hpcd);
|
||||
(void)USB_DevConnect(hpcd->Instance);
|
||||
__HAL_UNLOCK(hpcd);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
@ -1543,6 +1575,7 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
|
|||
__HAL_LOCK(hpcd);
|
||||
(void)USB_DevDisconnect(hpcd->Instance);
|
||||
__HAL_UNLOCK(hpcd);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
@ -1558,6 +1591,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
|
|||
hpcd->USB_Address = address;
|
||||
(void)USB_SetDevAddress(hpcd->Instance, address);
|
||||
__HAL_UNLOCK(hpcd);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
/**
|
||||
|
@ -1568,7 +1602,8 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
|
|||
* @param ep_type endpoint type
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint16_t ep_mps, uint8_t ep_type)
|
||||
{
|
||||
HAL_StatusTypeDef ret = HAL_OK;
|
||||
PCD_EPTypeDef *ep;
|
||||
|
@ -1753,10 +1788,12 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|||
__HAL_LOCK(hpcd);
|
||||
|
||||
(void)USB_EPSetStall(hpcd->Instance, ep);
|
||||
|
||||
if ((ep_addr & EP_ADDR_MSK) == 0U)
|
||||
{
|
||||
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
|
||||
}
|
||||
|
||||
__HAL_UNLOCK(hpcd);
|
||||
|
||||
return HAL_OK;
|
||||
|
@ -1847,8 +1884,8 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
|
|||
*/
|
||||
|
||||
/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
|
|
|
@ -49,7 +49,7 @@
|
|||
|
||||
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
||||
* @brief PCDEx control functions
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
|
|
|
@ -41,7 +41,7 @@
|
|||
/** @addtogroup PWR_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
|
||||
* @{
|
||||
*/
|
||||
|
@ -339,7 +339,7 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
|
|||
|
||||
/* Enable wake-up pin */
|
||||
SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity));
|
||||
|
||||
|
||||
/* Specifies the Wake-Up pin polarity for the event detection
|
||||
(rising or falling edge) */
|
||||
MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06));
|
||||
|
|
|
@ -17,8 +17,8 @@
|
|||
(HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
|
||||
and I-Cache are disabled, and all peripherals are off except internal
|
||||
SRAM, Flash and JTAG.
|
||||
(+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
|
||||
all peripherals mapped on these busses are running at HSI speed.
|
||||
(+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
|
||||
all peripherals mapped on these buses are running at HSI speed.
|
||||
(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
|
||||
(+) All GPIOs are in input floating state, except the JTAG pins which
|
||||
are assigned to be used for debug purpose.
|
||||
|
@ -28,7 +28,7 @@
|
|||
(+) Configure the clock source to be used to drive the System clock
|
||||
(if the application needs higher frequency/performance)
|
||||
(+) Configure the System clock frequency and Flash settings
|
||||
(+) Configure the AHB and APB busses prescalers
|
||||
(+) Configure the AHB and APB buses prescalers
|
||||
(+) Enable the clock for the peripheral(s) to be used
|
||||
(+) Configure the clock source(s) for peripherals which clocks are not
|
||||
derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
|
||||
|
@ -154,14 +154,14 @@
|
|||
(#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
|
||||
clock (through a configurable prescaler) on PC9 pin.
|
||||
|
||||
[..] System, AHB and APB busses clocks configuration
|
||||
[..] System, AHB and APB buses clocks configuration
|
||||
(#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
|
||||
HSE and PLL.
|
||||
The AHB clock (HCLK) is derived from System clock through configurable
|
||||
prescaler and used to clock the CPU, memory and peripherals mapped
|
||||
on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
|
||||
from AHB clock through configurable prescalers and used to clock
|
||||
the peripherals mapped on these busses. You can use
|
||||
the peripherals mapped on these buses. You can use
|
||||
"HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
|
||||
|
||||
-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
|
||||
|
@ -696,7 +696,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the CPU, AHB and APB busses clocks according to the specified
|
||||
* @brief Initializes the CPU, AHB and APB buses clocks according to the specified
|
||||
* parameters in the RCC_ClkInitStruct.
|
||||
* @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
|
||||
* contains the configuration information for the RCC peripheral.
|
||||
|
|
|
@ -454,7 +454,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
|
|||
|
||||
/*-------------------------------------- PLLI2S Configuration ---------------------------------*/
|
||||
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
|
||||
if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
|
||||
if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
|
||||
{
|
||||
/* Disable the PLLI2S */
|
||||
__HAL_RCC_PLLI2S_DISABLE();
|
||||
|
@ -1105,7 +1105,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
|
|||
|
||||
/*-------------------------------------- PLLI2S Configuration ---------------------------------*/
|
||||
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */
|
||||
if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
|
||||
if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
|
||||
{
|
||||
/* Disable the PLLI2S */
|
||||
__HAL_RCC_PLLI2S_DISABLE();
|
||||
|
|
|
@ -323,7 +323,19 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
|
|||
|
||||
/* Exit Initialization mode */
|
||||
hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
|
||||
/* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
|
||||
if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
|
||||
{
|
||||
if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
|
||||
{
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
hrtc->State = HAL_RTC_STATE_ERROR;
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
hrtc->Instance->OR &= (uint32_t)~RTC_OR_ALARMTYPE;
|
||||
hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType);
|
||||
|
||||
|
@ -799,10 +811,10 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
|
|||
/* Set the RTC_TR register */
|
||||
hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
|
||||
|
||||
/* Clear the bits to be configured */
|
||||
/* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
|
||||
hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP;
|
||||
|
||||
/* Configure the RTC_CR register */
|
||||
/* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
|
||||
hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
|
||||
|
||||
/* Exit Initialization mode */
|
||||
|
@ -1765,6 +1777,72 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
|
|||
return hrtc->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Daylight Saving Time, Add one hour to the calendar in one single operation
|
||||
* without going through the initialization procedure.
|
||||
* @param hrtc RTC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
UNUSED(hrtc);
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
SET_BIT(RTC->CR, RTC_CR_ADD1H);
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Daylight Saving Time, Subtract one hour from the calendar in one
|
||||
* single operation without going through the initialization procedure.
|
||||
* @param hrtc RTC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
UNUSED(hrtc);
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
SET_BIT(RTC->CR, RTC_CR_SUB1H);
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Daylight Saving Time, Set the store operation bit.
|
||||
* @note It can be used by the software in order to memorize the DST status.
|
||||
* @param hrtc RTC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
UNUSED(hrtc);
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
SET_BIT(RTC->CR, RTC_CR_BKP);
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Daylight Saving Time, Clear the store operation bit.
|
||||
* @param hrtc RTC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
UNUSED(hrtc);
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
CLEAR_BIT(RTC->CR, RTC_CR_BKP);
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Daylight Saving Time, Read the store operation bit.
|
||||
* @param hrtc RTC handle
|
||||
* @retval operation see RTC_StoreOperation_Definitions
|
||||
*/
|
||||
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
UNUSED(hrtc);
|
||||
return READ_BIT(RTC->CR, RTC_CR_BKP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -448,6 +448,17 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
|
|||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
@ -588,17 +599,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure the SD DPSM (Data Path State Machine) */
|
||||
config.DataTimeOut = SDMMC_DATATIMEOUT;
|
||||
config.DataLength = NumberOfBlocks * BLOCKSIZE;
|
||||
|
@ -810,17 +810,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure the SD DPSM (Data Path State Machine) */
|
||||
config.DataTimeOut = SDMMC_DATATIMEOUT;
|
||||
config.DataLength = NumberOfBlocks * BLOCKSIZE;
|
||||
|
@ -1007,18 +996,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
hsd->Context = SD_CONTEXT_NONE;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure the SD DPSM (Data Path State Machine) */
|
||||
config.DataTimeOut = SDMMC_DATATIMEOUT;
|
||||
config.DataLength = BLOCKSIZE * NumberOfBlocks;
|
||||
|
@ -1112,17 +1089,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write Blocks in Polling mode */
|
||||
if(NumberOfBlocks > 1U)
|
||||
{
|
||||
|
@ -1216,6 +1182,10 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
|
|||
/* Set the DMA Abort callback */
|
||||
hsd->hdmarx->XferAbortCallback = NULL;
|
||||
|
||||
/* Force DMA Direction */
|
||||
hsd->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||
MODIFY_REG(hsd->hdmarx->Instance->CR, DMA_SxCR_DIR, hsd->hdmarx->Init.Direction);
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
|
||||
{
|
||||
|
@ -1235,17 +1205,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure the SD DPSM (Data Path State Machine) */
|
||||
config.DataTimeOut = SDMMC_DATATIMEOUT;
|
||||
config.DataLength = BLOCKSIZE * NumberOfBlocks;
|
||||
|
@ -1346,17 +1305,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
|
|||
add *= 512U;
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write Blocks in Polling mode */
|
||||
if(NumberOfBlocks > 1U)
|
||||
{
|
||||
|
@ -1385,6 +1333,10 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
|
|||
/* Enable SDMMC DMA transfer */
|
||||
__HAL_SD_DMA_ENABLE(hsd);
|
||||
|
||||
/* Force DMA Direction */
|
||||
hsd->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH;
|
||||
MODIFY_REG(hsd->hdmatx->Instance->CR, DMA_SxCR_DIR, hsd->hdmatx->Init.Direction);
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
|
||||
{
|
||||
|
@ -1508,6 +1460,7 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui
|
|||
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
hsd->Context = SD_CONTEXT_NONE;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
|
@ -2145,6 +2098,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT
|
|||
{
|
||||
uint32_t sd_status[16];
|
||||
uint32_t errorstate;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
errorstate = SD_SendSDStatus(hsd, sd_status);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
|
@ -2153,7 +2107,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT
|
|||
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -2179,7 +2133,18 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT
|
|||
pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
|
||||
hsd->ErrorCode = errorstate;
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -2218,6 +2183,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
|
|||
{
|
||||
SDMMC_InitTypeDef Init;
|
||||
uint32_t errorstate;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDMMC_BUS_WIDE(WideMode));
|
||||
|
@ -2260,7 +2226,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
|
|||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
return HAL_ERROR;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -2274,10 +2240,20 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
|
|||
(void)SDMMC_Init(hsd->Instance, Init);
|
||||
}
|
||||
|
||||
/* Set Block Size for Card */
|
||||
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
|
||||
if(errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
/* Clear all the static flags */
|
||||
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
|
||||
hsd->ErrorCode |= errorstate;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Change State */
|
||||
hsd->State = HAL_SD_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -3098,13 +3074,17 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
|
|||
return errorstate;
|
||||
}
|
||||
|
||||
while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
|
||||
while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT))
|
||||
{
|
||||
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))
|
||||
{
|
||||
*(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance);
|
||||
index++;
|
||||
}
|
||||
else if(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXACT))
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
|
||||
{
|
||||
|
|
|
@ -35,7 +35,8 @@
|
|||
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
|
||||
(+++) Configure the DMA Tx/Rx channel.
|
||||
(+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
|
||||
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
|
||||
(+++) Configure the priority and enable the NVIC for the transfer complete
|
||||
interrupt on the DMA Tx/Rx channel.
|
||||
|
||||
(#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
|
||||
the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
|
||||
|
@ -107,8 +108,8 @@
|
|||
allows the user to configure dynamically the driver callbacks.
|
||||
|
||||
[..]
|
||||
Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback.
|
||||
Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
|
||||
Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback.
|
||||
Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
|
||||
(+) TxCpltCallback : Tx Complete Callback.
|
||||
(+) RxCpltCallback : Rx Complete Callback.
|
||||
(+) ErrorCallback : Error Callback.
|
||||
|
@ -121,9 +122,9 @@
|
|||
and a pointer to the user callback function.
|
||||
|
||||
[..]
|
||||
Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
|
||||
Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
|
||||
weak (surcharged) function.
|
||||
@ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
|
||||
HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
(+) TxCpltCallback : Tx Complete Callback.
|
||||
|
@ -136,13 +137,13 @@
|
|||
(+) MspDeInitCallback : SMARTCARD MspDeInit.
|
||||
|
||||
[..]
|
||||
By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
|
||||
By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
|
||||
all callbacks are set to the corresponding weak (surcharged) functions:
|
||||
examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback().
|
||||
examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are respectively
|
||||
reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init()
|
||||
and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
|
||||
If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit()
|
||||
reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init()
|
||||
and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
|
||||
If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
|
||||
|
||||
[..]
|
||||
|
@ -151,8 +152,8 @@
|
|||
in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
|
||||
MspInit/DeInit callbacks can be used during the Init/DeInit.
|
||||
In that case first register the MspInit/MspDeInit user callbacks
|
||||
using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit()
|
||||
or @ref HAL_SMARTCARD_Init() function.
|
||||
using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit()
|
||||
or HAL_SMARTCARD_Init() function.
|
||||
|
||||
[..]
|
||||
When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
|
||||
|
@ -194,21 +195,23 @@
|
|||
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
|
||||
#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
|
||||
|
||||
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
|
||||
USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
|
||||
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
|
||||
USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
|
||||
|
||||
#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \
|
||||
USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
|
||||
#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
|
||||
USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
|
||||
|
||||
#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
|
||||
#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \
|
||||
USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
|
||||
|
||||
#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
|
||||
#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | \
|
||||
USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
|
||||
|
||||
#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
|
||||
#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
|
||||
|
||||
#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
|
||||
#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -473,7 +476,8 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
|
|||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
|
||||
HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
|
||||
HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
|
||||
pSMARTCARD_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -599,36 +603,38 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
|
|||
switch (CallbackID)
|
||||
{
|
||||
case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
|
||||
hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
|
||||
hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
|
||||
hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_SMARTCARD_ERROR_CB_ID :
|
||||
hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
break;
|
||||
|
||||
case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
|
||||
hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
|
||||
hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
|
||||
hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
|
||||
hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
|
||||
AbortTransmitCpltCallback*/
|
||||
break;
|
||||
|
||||
case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
|
||||
hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
|
||||
hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
|
||||
AbortReceiveCpltCallback */
|
||||
break;
|
||||
|
||||
|
||||
case HAL_SMARTCARD_MSPINIT_CB_ID :
|
||||
hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
|
||||
hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
|
||||
break;
|
||||
|
||||
case HAL_SMARTCARD_MSPDEINIT_CB_ID :
|
||||
hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
|
||||
hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
|
||||
break;
|
||||
|
||||
default :
|
||||
|
@ -699,62 +705,67 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
|
|||
(+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
|
||||
|
||||
[..]
|
||||
(+) There are two modes of transfer:
|
||||
(++) Blocking mode: The communication is performed in polling mode.
|
||||
(#) There are two modes of transfer:
|
||||
(##) Blocking mode: The communication is performed in polling mode.
|
||||
The HAL status of all data processing is returned by the same function
|
||||
after finishing transfer.
|
||||
(++) Non-Blocking mode: The communication is performed using Interrupts
|
||||
(##) Non-Blocking mode: The communication is performed using Interrupts
|
||||
or DMA, the relevant API's return the HAL status.
|
||||
The end of the data processing will be indicated through the
|
||||
dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
|
||||
using DMA mode.
|
||||
(++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
|
||||
(##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
|
||||
will be executed respectively at the end of the Transmit or Receive process
|
||||
The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
|
||||
error is detected.
|
||||
|
||||
(+) Blocking mode APIs are :
|
||||
(++) HAL_SMARTCARD_Transmit()
|
||||
(++) HAL_SMARTCARD_Receive()
|
||||
(#) Blocking mode APIs are :
|
||||
(##) HAL_SMARTCARD_Transmit()
|
||||
(##) HAL_SMARTCARD_Receive()
|
||||
|
||||
(+) Non Blocking mode APIs with Interrupt are :
|
||||
(++) HAL_SMARTCARD_Transmit_IT()
|
||||
(++) HAL_SMARTCARD_Receive_IT()
|
||||
(++) HAL_SMARTCARD_IRQHandler()
|
||||
(#) Non Blocking mode APIs with Interrupt are :
|
||||
(##) HAL_SMARTCARD_Transmit_IT()
|
||||
(##) HAL_SMARTCARD_Receive_IT()
|
||||
(##) HAL_SMARTCARD_IRQHandler()
|
||||
|
||||
(+) Non Blocking mode functions with DMA are :
|
||||
(++) HAL_SMARTCARD_Transmit_DMA()
|
||||
(++) HAL_SMARTCARD_Receive_DMA()
|
||||
(#) Non Blocking mode functions with DMA are :
|
||||
(##) HAL_SMARTCARD_Transmit_DMA()
|
||||
(##) HAL_SMARTCARD_Receive_DMA()
|
||||
|
||||
(+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
|
||||
(++) HAL_SMARTCARD_TxCpltCallback()
|
||||
(++) HAL_SMARTCARD_RxCpltCallback()
|
||||
(++) HAL_SMARTCARD_ErrorCallback()
|
||||
(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
|
||||
(##) HAL_SMARTCARD_TxCpltCallback()
|
||||
(##) HAL_SMARTCARD_RxCpltCallback()
|
||||
(##) HAL_SMARTCARD_ErrorCallback()
|
||||
|
||||
[..]
|
||||
(#) Non-Blocking mode transfers could be aborted using Abort API's :
|
||||
(++) HAL_SMARTCARD_Abort()
|
||||
(++) HAL_SMARTCARD_AbortTransmit()
|
||||
(++) HAL_SMARTCARD_AbortReceive()
|
||||
(++) HAL_SMARTCARD_Abort_IT()
|
||||
(++) HAL_SMARTCARD_AbortTransmit_IT()
|
||||
(++) HAL_SMARTCARD_AbortReceive_IT()
|
||||
(##) HAL_SMARTCARD_Abort()
|
||||
(##) HAL_SMARTCARD_AbortTransmit()
|
||||
(##) HAL_SMARTCARD_AbortReceive()
|
||||
(##) HAL_SMARTCARD_Abort_IT()
|
||||
(##) HAL_SMARTCARD_AbortTransmit_IT()
|
||||
(##) HAL_SMARTCARD_AbortReceive_IT()
|
||||
|
||||
(#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
|
||||
(++) HAL_SMARTCARD_AbortCpltCallback()
|
||||
(++) HAL_SMARTCARD_AbortTransmitCpltCallback()
|
||||
(++) HAL_SMARTCARD_AbortReceiveCpltCallback()
|
||||
(#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT),
|
||||
a set of Abort Complete Callbacks are provided:
|
||||
(##) HAL_SMARTCARD_AbortCpltCallback()
|
||||
(##) HAL_SMARTCARD_AbortTransmitCpltCallback()
|
||||
(##) HAL_SMARTCARD_AbortReceiveCpltCallback()
|
||||
|
||||
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
|
||||
Errors are handled as follows :
|
||||
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
|
||||
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
|
||||
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
|
||||
and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
|
||||
If user wants to abort it, Abort services should be called by user.
|
||||
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
|
||||
This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
|
||||
Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
|
||||
(##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
|
||||
to be evaluated by user : this concerns Frame Error,
|
||||
Parity Error or Noise Error in Interrupt mode reception .
|
||||
Received character is then retrieved and stored in Rx buffer,
|
||||
Error code is set to allow user to identify error type,
|
||||
and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
|
||||
If user wants to abort it, Abort services should be called by user.
|
||||
(##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
|
||||
This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt
|
||||
mode reception and all errors in DMA mode.
|
||||
Error code is set to allow user to identify error type,
|
||||
and HAL_SMARTCARD_ErrorCallback() user callback is executed.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
|
@ -794,14 +805,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
|
|||
/* Disable the Peripheral first to update mode for TX master */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
|
||||
|
||||
/* Disable Rx, enable Tx */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
|
||||
SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
|
||||
/* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
|
||||
the bidirectional line to detect a NACK signal in case of parity error.
|
||||
Therefore, the receiver block must be enabled as well (RE bit must be set). */
|
||||
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
|
||||
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
{
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
|
||||
}
|
||||
/* Enable Tx */
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
|
||||
|
||||
/* Perform a TX/RX FIFO Flush */
|
||||
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
|
||||
|
||||
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
|
||||
hsmartcard->TxXferSize = Size;
|
||||
hsmartcard->TxXferCount = Size;
|
||||
|
@ -816,20 +836,28 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
|
|||
hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
|
||||
ptmpdata++;
|
||||
}
|
||||
if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart,
|
||||
Timeout) != HAL_OK)
|
||||
if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET,
|
||||
tickstart, Timeout) != HAL_OK)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
/* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
|
||||
if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
|
||||
|
||||
/* Disable the Peripheral first to update mode */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
|
||||
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
|
||||
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
{
|
||||
/* Disable the Peripheral first to update modes */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
|
||||
/* Enable the Peripheral */
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
|
||||
/* In case of TX only mode, if NACK is enabled, receiver block has been enabled
|
||||
for Transmit phase. Disable this receiver block. */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
|
||||
}
|
||||
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
|
||||
|| (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
{
|
||||
/* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
|
||||
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
|
||||
}
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
|
||||
|
||||
/* At end of Tx process, restore hsmartcard->gState to Ready */
|
||||
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
|
||||
|
@ -939,14 +967,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard,
|
|||
/* Disable the Peripheral first to update mode for TX master */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
|
||||
|
||||
/* Disable Rx, enable Tx */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
|
||||
SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
|
||||
/* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
|
||||
the bidirectional line to detect a NACK signal in case of parity error.
|
||||
Therefore, the receiver block must be enabled as well (RE bit must be set). */
|
||||
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
|
||||
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
{
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
|
||||
}
|
||||
/* Enable Tx */
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
|
||||
|
||||
/* Perform a TX/RX FIFO Flush */
|
||||
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
|
||||
|
||||
/* Configure Tx interrupt processing */
|
||||
/* Set the Tx ISR function pointer */
|
||||
hsmartcard->TxISR = SMARTCARD_TxISR;
|
||||
|
@ -1048,14 +1085,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard
|
|||
/* Disable the Peripheral first to update mode for TX master */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
|
||||
|
||||
/* Disable Rx, enable Tx */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
|
||||
SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
|
||||
/* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
|
||||
the bidirectional line to detect a NACK signal in case of parity error.
|
||||
Therefore, the receiver block must be enabled as well (RE bit must be set). */
|
||||
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
|
||||
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
{
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
|
||||
}
|
||||
/* Enable Tx */
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
|
||||
|
||||
/* Perform a TX/RX FIFO Flush */
|
||||
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
|
||||
|
||||
/* Set the SMARTCARD DMA transfer complete callback */
|
||||
hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
|
||||
|
||||
|
@ -1198,7 +1244,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
|
|||
{
|
||||
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1,
|
||||
(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
|
||||
(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE |
|
||||
USART_CR1_EOBIE));
|
||||
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
/* Disable the SMARTCARD DMA Tx request if enabled */
|
||||
|
@ -1257,8 +1304,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
|
|||
|
||||
/* Clear the Error flags in the ICR register */
|
||||
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
|
||||
SMARTCARD_CLEAR_EOBF);
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
|
||||
SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
|
||||
|
||||
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
|
||||
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
|
||||
|
@ -1388,8 +1435,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard
|
|||
|
||||
/* Clear the Error flags in the ICR register */
|
||||
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
|
||||
SMARTCARD_CLEAR_EOBF);
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
|
||||
SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
|
||||
|
||||
/* Restore hsmartcard->RxState to Ready */
|
||||
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
|
||||
|
@ -1418,11 +1465,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
|
|||
|
||||
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1,
|
||||
(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
|
||||
(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE |
|
||||
USART_CR1_EOBIE));
|
||||
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
/* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
|
||||
before any call to DMA Abort functions */
|
||||
/* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle,
|
||||
DMA Abort complete callbacks should be initialised before any call
|
||||
to DMA Abort functions */
|
||||
/* DMA Tx Handle is valid */
|
||||
if (hsmartcard->hdmatx != NULL)
|
||||
{
|
||||
|
@ -1516,8 +1565,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
|
|||
|
||||
/* Clear the Error flags in the ICR register */
|
||||
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
|
||||
SMARTCARD_CLEAR_EOBF);
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
|
||||
SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
|
||||
|
||||
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
|
||||
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
|
||||
|
@ -1687,8 +1736,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc
|
|||
|
||||
/* Clear the Error flags in the ICR register */
|
||||
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
|
||||
SMARTCARD_CLEAR_EOBF);
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
|
||||
SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
|
||||
|
||||
/* Restore hsmartcard->RxState to Ready */
|
||||
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
|
||||
|
@ -1713,8 +1762,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc
|
|||
|
||||
/* Clear the Error flags in the ICR register */
|
||||
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
|
||||
SMARTCARD_CLEAR_EOBF);
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
|
||||
SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
|
||||
|
||||
/* Restore hsmartcard->RxState to Ready */
|
||||
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
|
||||
|
@ -2156,12 +2205,14 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
|
|||
void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
|
||||
{
|
||||
/* Init the SMARTCARD Callback settings */
|
||||
hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
|
||||
hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
|
||||
hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
|
||||
hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
|
||||
hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
|
||||
hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
|
||||
hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
|
||||
AbortTransmitCpltCallback */
|
||||
hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
|
||||
AbortReceiveCpltCallback */
|
||||
|
||||
}
|
||||
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
|
||||
|
@ -2200,7 +2251,8 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
|
|||
* Configure the Parity and Mode:
|
||||
* set PS bit according to hsmartcard->Init.Parity value
|
||||
* set TE and RE bits according to hsmartcard->Init.Mode value */
|
||||
tmpreg = (uint32_t)(hsmartcard->Init.Parity | hsmartcard->Init.Mode | hsmartcard->Init.WordLength);
|
||||
tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) |
|
||||
((uint32_t)hsmartcard->Init.WordLength));
|
||||
MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
||||
|
||||
/*-------------------------- USART CR2 Configuration -----------------------*/
|
||||
|
@ -2405,7 +2457,8 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
|
|||
{
|
||||
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
||||
{
|
||||
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
|
||||
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
|
||||
interrupts for the interrupt process */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
|
||||
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
|
@ -2599,8 +2652,8 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
|
|||
|
||||
/* Clear the Error flags in the ICR register */
|
||||
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
|
||||
SMARTCARD_CLEAR_EOBF);
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
|
||||
SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
|
||||
|
||||
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
|
||||
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
|
||||
|
@ -2648,8 +2701,8 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
|
|||
|
||||
/* Clear the Error flags in the ICR register */
|
||||
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
|
||||
SMARTCARD_CLEAR_EOBF);
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
|
||||
SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
|
||||
|
||||
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
|
||||
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
|
||||
|
@ -2710,8 +2763,8 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
|
|||
|
||||
/* Clear the Error flags in the ICR register */
|
||||
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
|
||||
SMARTCARD_CLEAR_EOBF);
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
|
||||
SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
|
||||
|
||||
/* Restore hsmartcard->RxState to Ready */
|
||||
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
|
||||
|
@ -2773,15 +2826,22 @@ static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
|
|||
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
|
||||
}
|
||||
|
||||
/* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
|
||||
if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
|
||||
/* Disable the Peripheral first to update mode */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
|
||||
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
|
||||
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
{
|
||||
/* Disable the Peripheral first to update modes */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
|
||||
/* Enable the Peripheral */
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
|
||||
/* In case of TX only mode, if NACK is enabled, receiver block has been enabled
|
||||
for Transmit phase. Disable this receiver block. */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
|
||||
}
|
||||
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
|
||||
|| (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
{
|
||||
/* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
|
||||
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
|
||||
}
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
|
||||
|
||||
/* Tx process is ended, restore hsmartcard->gState to Ready */
|
||||
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue