stm32cube: update stm32f1 to version V1.8.2
Update Cube version for STM32F1xx series on https://github.com/STMicroelectronics from version v1.8.0 to version v1.8.2 Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
This commit is contained in:
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commit
1a68ea080a
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@ -1,4 +1,5 @@
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# Copyright (c) 2017 Erwin Rol <erwin@erwinrol.com>
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# Copyright (c) 2020 STMicroelectronics
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#
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# SPDX-License-Identifier: Apache-2.0
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@ -15,6 +16,7 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DAC drivers/src/stm32f1xx_hal_
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DAC_EX drivers/src/stm32f1xx_hal_dac_ex.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DMA drivers/src/stm32f1xx_hal_dma.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_ETH drivers/src/stm32f1xx_hal_eth.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_EXTI drivers/src/stm32f1xx_hal_exti.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_FLASH drivers/src/stm32f1xx_hal_flash.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_FLASH_EX drivers/src/stm32f1xx_hal_flash_ex.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_GPIO drivers/src/stm32f1xx_hal_gpio.c)
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@ -31,13 +33,13 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PCCARD drivers/src/stm32f1xx_h
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PCD drivers/src/stm32f1xx_hal_pcd.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PCD_EX drivers/src/stm32f1xx_hal_pcd_ex.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PWR drivers/src/stm32f1xx_hal_pwr.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RCC drivers/src/stm32f1xx_hal_rcc.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RCC_EX drivers/src/stm32f1xx_hal_rcc_ex.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RTC drivers/src/stm32f1xx_hal_rtc.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RTC_EX drivers/src/stm32f1xx_hal_rtc_ex.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SD drivers/src/stm32f1xx_hal_sd.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMARTCARD drivers/src/stm32f1xx_hal_smartcard.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SPI drivers/src/stm32f1xx_hal_spi.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SPI_EX drivers/src/stm32f1xx_hal_spi_ex.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SRAM drivers/src/stm32f1xx_hal_sram.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_TIM drivers/src/stm32f1xx_hal_tim.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_TIM_EX drivers/src/stm32f1xx_hal_tim_ex.c)
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@ -61,4 +63,3 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_TIM drivers/src/stm32f1xx_ll_ti
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_USART drivers/src/stm32f1xx_ll_usart.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_USB drivers/src/stm32f1xx_ll_usb.c)
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zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_UTILS drivers/src/stm32f1xx_ll_utils.c)
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@ -6,7 +6,7 @@ Origin:
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http://www.st.com/en/embedded-software/stm32cubef1.html
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Status:
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version 1.8.0
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version v1.8.2
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Purpose:
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ST Microelectronics official MCU package for STM32F1 series.
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@ -20,10 +20,10 @@ Dependencies:
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None.
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URL:
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http://www.st.com/en/embedded-software/stm32cubef1.html
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https://github.com/STMicroelectronics/STM32CubeF1
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commit:
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version 1.8.0
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Commit:
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003dfc9e6c2e424c19a25df3934afaf7fce660d6
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Maintained-by:
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External
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@ -36,14 +36,6 @@ License Link:
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Patch List:
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*Extend public SetFlashLatency API to all families
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The LL_SetFlashLatency public API is now defined for families
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beyond G4, L4 and L5. The private function has been made public.
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Impacted files:
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drivers/include/stm32f1xx_ll_utils.h
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drivers/src/stm32f1xx_ll_utils.c
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ST Bug tracker ID: 76118
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*Changes from official delivery:
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-dos2unix applied
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-trailing white spaces removed
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@ -55,3 +47,5 @@ Patch List:
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Impacted files:
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drivers/include/stm32f1xx_hal_conf.h
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ST Bug tracker ID: NA. Not a stm32cube issue
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See release_note.html from STM32Cube
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@ -38,7 +38,6 @@
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#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
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#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
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#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
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/**
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* @}
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*/
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@ -236,12 +235,12 @@
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#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
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#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
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#if defined(STM32G4)
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#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH)
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#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH)
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#if defined(STM32G4) || defined(STM32H7)
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#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
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#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
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#endif
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#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0)
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#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
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#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
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#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
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#endif
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@ -306,8 +305,22 @@
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#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
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#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
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#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
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#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
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#endif
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#endif /* STM32L4 */
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#if defined(STM32G0)
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#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
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#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
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#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
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#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
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#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
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#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
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#endif
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#if defined(STM32H7)
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#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
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@ -365,6 +378,9 @@
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#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
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#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
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#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
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#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
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#endif /* STM32H7 */
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/**
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@ -460,7 +476,9 @@
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#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
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#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
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#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
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#endif
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#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
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#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
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#endif /* STM32H7 */
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/**
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* @}
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#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
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#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
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#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
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#endif
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#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
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defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
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#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
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#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
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#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
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#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
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#endif /* STM32H7 */
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#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
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#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
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#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
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#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
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#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
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#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
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#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
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#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
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#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
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#endif /* STM32G4 */
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#if defined(STM32H7)
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#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
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#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
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#endif /* STM32H7 */
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#if defined(STM32F3)
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/** @brief Constants defining available sources associated to external events.
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*/
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#define HRTIM_EVENTSRC_1 (0x00000000U)
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#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
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#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
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#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
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/** @brief Constants defining the events that can be selected to configure the
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* set/reset crossbar of a timer output
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*/
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#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
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#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
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#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
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#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
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#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
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#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
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#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
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#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
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#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
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#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
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#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
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#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
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#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
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#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
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#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
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#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
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#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
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#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
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/** @brief Constants defining the event filtering applied to external events
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* by a timer
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*/
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#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
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#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
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#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
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#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
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#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
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#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
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/** @brief Constants defining the DLL calibration periods (in micro seconds)
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*/
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#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
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#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
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#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
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#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
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#endif /* STM32F3 */
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/**
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* @}
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*/
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#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
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#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
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#if defined(STM32L1) || defined(STM32L4)
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#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
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#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
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#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
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#endif
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#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
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#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
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#if defined(STM32H7)
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#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
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#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
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#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
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#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
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#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
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#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
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#endif /* STM32H7 */
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/**
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* @}
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*/
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#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
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#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
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#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
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#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
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#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
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#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
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#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
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#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
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#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
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#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
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#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
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#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
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#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
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#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
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#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
|
||||
|
||||
#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
|
||||
#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
|
||||
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
|
||||
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
|
||||
|
||||
#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -1380,6 +1503,13 @@
|
|||
#endif
|
||||
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
|
||||
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
|
||||
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
|
||||
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
|
||||
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
|
||||
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
|
||||
#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
|
||||
#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -1409,16 +1539,18 @@
|
|||
|
||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
||||
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
|
||||
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
|
||||
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
|
||||
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
|
||||
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
|
||||
#if defined(STM32F4)
|
||||
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
|
||||
|
@ -1437,6 +1569,13 @@
|
|||
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32G0)
|
||||
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
|
||||
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
|
||||
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
|
||||
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
|
||||
#endif
|
||||
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
|
||||
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
|
||||
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
|
||||
|
@ -1509,14 +1648,14 @@
|
|||
#define HAL_TIM_DMAError TIM_DMAError
|
||||
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
|
||||
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
|
||||
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)
|
||||
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
|
||||
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
|
||||
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
|
||||
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
|
||||
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
|
||||
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
|
||||
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
|
||||
#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
|
||||
#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -3112,9 +3251,8 @@
|
|||
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
|
||||
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
|
||||
|
||||
#if defined(STM32L4)
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
|
||||
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
|
||||
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
|
||||
#else
|
||||
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
|
||||
#endif
|
||||
|
@ -3242,7 +3380,7 @@
|
|||
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4)
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
|
||||
#else
|
||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||
#endif
|
||||
|
@ -3350,9 +3488,9 @@
|
|||
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
|
||||
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
|
||||
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
|
||||
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
|
||||
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
|
||||
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
|
||||
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
|
||||
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
|
||||
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
|
||||
/* alias CMSIS for compatibilities */
|
||||
#define SDIO_IRQn SDMMC1_IRQn
|
||||
#define SDIO_IRQHandler SDMMC1_IRQHandler
|
||||
|
@ -3365,7 +3503,7 @@
|
|||
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
|
||||
#endif
|
||||
|
||||
#if defined(STM32H7)
|
||||
#if defined(STM32H7) || defined(STM32L5)
|
||||
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
|
||||
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
|
||||
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
|
||||
|
@ -3606,12 +3744,12 @@
|
|||
* @{
|
||||
*/
|
||||
#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
|
||||
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
|
||||
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
|
||||
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
|
||||
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
|
||||
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
|
||||
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
|
||||
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
|
||||
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
|
||||
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
|
||||
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
|
||||
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
|
||||
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
|
@ -3620,9 +3758,9 @@
|
|||
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32L4)
|
||||
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
|
||||
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
|
||||
#endif
|
||||
#endif /* STM32L4 || STM32F4 || STM32F7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -6,29 +6,13 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
|
@ -57,6 +57,7 @@ typedef enum
|
|||
* @}
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
extern __IO uint32_t uwTick;
|
||||
extern uint32_t uwTickPrio;
|
||||
extern HAL_TickFreqTypeDef uwTickFreq;
|
||||
|
||||
|
|
|
@ -295,11 +295,11 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to
|
|||
#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
|
||||
#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
|
||||
#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
|
||||
#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
|
||||
#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
|
||||
#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
|
||||
#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
|
||||
#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
|
||||
|
|
|
@ -1,144 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_can_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CAN HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_CAN_EX_H
|
||||
#define __STM32F1xx_HAL_CAN_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
|
||||
defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CANEx CANEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief CAN filter configuration structure definition
|
||||
*/
|
||||
/* CAN filter banks differences over STM32F1 devices: */
|
||||
/* - STM32F1 Connectivity line: 28 filter banks shared between CAN1 and CAN2 */
|
||||
/* - Other STM32F10x devices: 14 filter banks */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration,
|
||||
first one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration,
|
||||
second one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
|
||||
#else
|
||||
uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 13. */
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||
This parameter can be a value of @ref CAN_filter_mode */
|
||||
|
||||
uint32_t FilterScale; /*!< Specifies the filter scale.
|
||||
This parameter can be a value of @ref CAN_filter_scale */
|
||||
|
||||
uint32_t FilterActivation; /*!< Enable or disable the filter.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t BankNumber; /*!< Select the start slave bank filter
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 28. */
|
||||
|
||||
}CAN_FilterConfTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CANEx_Private_Macros CAN Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
|
||||
#else
|
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13U)
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_CAN_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
@ -147,7 +147,7 @@ typedef struct __CEC_HandleTypeDef
|
|||
void (* MspInitCallback) ( struct __CEC_HandleTypeDef * hcec); /*!< CEC Msp Init callback */
|
||||
void (* MspDeInitCallback) ( struct __CEC_HandleTypeDef * hcec); /*!< CEC Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
|
||||
#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
|
||||
}CEC_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
|
|
|
@ -28,9 +28,7 @@ extern "C" {
|
|||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx.h"
|
||||
#if defined(USE_HAL_LEGACY)
|
||||
#include "Legacy/stm32_hal_legacy.h"
|
||||
#endif
|
||||
#include <stddef.h>
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
@ -108,7 +106,14 @@ typedef enum
|
|||
}while (0U)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((packed))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
|
@ -119,7 +124,14 @@ typedef enum
|
|||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
|
@ -131,7 +143,7 @@ typedef enum
|
|||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler */
|
||||
#if defined (__CC_ARM) /* ARM Compiler V5*/
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
|
@ -143,9 +155,9 @@ typedef enum
|
|||
/**
|
||||
* @brief __RAM_FUNC definition
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
/* ARM Compiler
|
||||
------------
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
/* ARM Compiler V4/V5 and V6
|
||||
--------------------------
|
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
|
@ -175,9 +187,9 @@ typedef enum
|
|||
/**
|
||||
* @brief __NOINLINE definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
|
||||
/* ARM & GNUCompiler
|
||||
----------------
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
|
||||
/* ARM V4/V5 and V6 & GNU Compiler
|
||||
-------------------------------
|
||||
*/
|
||||
#define __NOINLINE __attribute__ ( (noinline) )
|
||||
|
||||
|
|
|
@ -33,7 +33,7 @@ extern "C" {
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HCD
|
||||
/** @addtogroup HCD HCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
@ -108,8 +108,8 @@ typedef struct
|
|||
/** @defgroup HCD_Speed HCD Speed
|
||||
* @{
|
||||
*/
|
||||
#define HCD_SPEED_FULL USBH_FS_SPEED
|
||||
#define HCD_SPEED_LOW USBH_LS_SPEED
|
||||
#define HCD_SPEED_FULL USBH_FSLS_SPEED
|
||||
#define HCD_SPEED_LOW USBH_FSLS_SPEED
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -142,9 +142,9 @@ typedef struct
|
|||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Exported_Macros HCD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
|
||||
|
@ -169,19 +169,15 @@ typedef struct
|
|||
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
|
||||
uint8_t ch_num,
|
||||
uint8_t epnum,
|
||||
uint8_t dev_address,
|
||||
uint8_t speed,
|
||||
uint8_t ep_type,
|
||||
uint16_t mps);
|
||||
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
||||
uint8_t epnum, uint8_t dev_address,
|
||||
uint8_t speed, uint8_t ep_type, uint16_t mps);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
|
||||
void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
|
||||
void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
|
||||
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
|
||||
|
@ -190,14 +186,14 @@ void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
|
|||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
|
||||
HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
|
||||
HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
|
||||
HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
|
||||
HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
|
||||
HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
|
||||
HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
|
||||
HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
|
||||
HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
|
||||
HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
|
||||
|
||||
HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
|
||||
HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
|
||||
HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
|
||||
HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
|
||||
|
||||
} HAL_HCD_CallbackIDTypeDef;
|
||||
/**
|
||||
|
@ -217,10 +213,16 @@ typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
|
|||
* @}
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID);
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
|
||||
HAL_HCD_CallbackIDTypeDef CallbackID,
|
||||
pHCD_CallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
|
||||
HAL_HCD_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
|
||||
pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
|
@ -231,25 +233,21 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef
|
|||
/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
|
||||
uint8_t ch_num,
|
||||
uint8_t direction,
|
||||
uint8_t ep_type,
|
||||
uint8_t token,
|
||||
uint8_t *pbuff,
|
||||
uint16_t length,
|
||||
uint8_t do_ping);
|
||||
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
||||
uint8_t direction, uint8_t ep_type,
|
||||
uint8_t token, uint8_t *pbuff,
|
||||
uint16_t length, uint8_t do_ping);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
|
||||
uint8_t chnum,
|
||||
HCD_URBStateTypeDef urb_state);
|
||||
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
|
||||
HCD_URBStateTypeDef urb_state);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -258,9 +256,9 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
|
|||
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -271,10 +269,11 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
|
|||
*/
|
||||
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
|
||||
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
|
||||
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -285,36 +284,17 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
|
|||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Private_Macros HCD Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup HCD_Private_Functions HCD Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
|
|
|
@ -170,6 +170,7 @@ typedef enum
|
|||
#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */
|
||||
#define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */
|
||||
#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */
|
||||
#define HAL_I2C_WRONG_START 0x00000200U /*!< Wrong start Error */
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
|
@ -181,7 +182,11 @@ typedef enum
|
|||
* @brief I2C handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __I2C_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||
|
||||
|
|
|
@ -174,6 +174,7 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
|
|||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -380,6 +381,15 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
|
|||
tmpreg_udr = ((__HANDLE__)->Instance->SR);\
|
||||
UNUSED(tmpreg_udr); \
|
||||
}while(0U)
|
||||
/** @brief Flush the I2S DR Register.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\
|
||||
__IO uint32_t tmpreg_dr = 0x00U;\
|
||||
tmpreg_dr = ((__HANDLE__)->Instance->DR);\
|
||||
UNUSED(tmpreg_dr); \
|
||||
}while(0U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -462,7 +472,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
|||
*/
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __SR__ copy of I2S SR regsiter.
|
||||
* @param __SR__ copy of I2S SR register.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
||||
|
@ -477,7 +487,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
|||
& ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
||||
* @param __CR2__ copy of I2S CR2 regsiter.
|
||||
* @param __CR2__ copy of I2S CR2 register.
|
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
|
|
|
@ -32,7 +32,7 @@ extern "C" {
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG
|
||||
/** @defgroup IWDG IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
@ -62,9 +62,9 @@ typedef struct
|
|||
IWDG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
|
||||
|
||||
} IWDG_HandleTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -77,22 +77,24 @@ typedef struct
|
|||
/** @defgroup IWDG_Prescaler IWDG Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */
|
||||
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
|
||||
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
|
||||
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
|
||||
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
|
||||
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
|
||||
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */
|
||||
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
|
||||
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
|
||||
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
|
||||
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
|
||||
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
|
||||
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
|
||||
* @{
|
||||
|
@ -107,7 +109,7 @@ typedef struct
|
|||
|
||||
/**
|
||||
* @brief Reload IWDG counter with value defined in the reload register
|
||||
* (write access to IWDG_PR & IWDG_RLR registers disabled).
|
||||
* (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
|
@ -200,6 +202,8 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
|||
*/
|
||||
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -90,10 +90,10 @@ typedef struct
|
|||
typedef struct
|
||||
{
|
||||
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
|
||||
for 8 bits adressing or words for 16 bits addressing */
|
||||
for 8 bits addressing or words for 16 bits addressing */
|
||||
|
||||
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
|
||||
for 8 bits adressing or words for 16 bits addressing */
|
||||
for 8 bits addressing or words for 16 bits addressing */
|
||||
|
||||
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
|
||||
|
||||
|
@ -131,9 +131,9 @@ typedef struct
|
|||
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
|
||||
|
||||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp Init callback */
|
||||
void (* MspDeInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp DeInit callback */
|
||||
void (* ItCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND IT callback */
|
||||
void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */
|
||||
void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */
|
||||
#endif
|
||||
} NAND_HandleTypeDef;
|
||||
|
||||
|
@ -146,7 +146,7 @@ typedef enum
|
|||
HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */
|
||||
HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */
|
||||
HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */
|
||||
}HAL_NAND_CallbackIDTypeDef;
|
||||
} HAL_NAND_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL NAND Callback pointer definition
|
||||
|
@ -161,8 +161,8 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
|
|||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup NAND_Exported_Macros NAND Exported Macros
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset NAND handle state
|
||||
* @param __HANDLE__ specifies the NAND handle.
|
||||
|
@ -192,7 +192,8 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
|
|||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
|
||||
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
|
||||
FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
|
||||
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
|
||||
|
@ -215,15 +216,23 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
|
|||
/* IO operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
|
||||
uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
|
||||
uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
|
||||
uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
|
||||
uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
|
||||
uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
|
||||
uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
|
||||
uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
|
||||
uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
|
||||
|
||||
|
@ -231,7 +240,8 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressT
|
|||
|
||||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
|
||||
/* NAND callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
|
||||
pNAND_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
|
||||
#endif
|
||||
|
||||
|
@ -272,34 +282,34 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
|
|||
/** @defgroup NAND_Private_Constants NAND Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define NAND_DEVICE1 ((uint32_t)0x70000000U)
|
||||
#define NAND_DEVICE2 ((uint32_t)0x80000000U)
|
||||
#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
|
||||
#define NAND_DEVICE1 0x70000000UL
|
||||
#define NAND_DEVICE2 0x80000000UL
|
||||
#define NAND_WRITE_TIMEOUT 0x01000000UL
|
||||
|
||||
#define CMD_AREA ((uint32_t)(1UL<<16U)) /* A16 = CLE high */
|
||||
#define ADDR_AREA ((uint32_t)(1UL<<17U)) /* A17 = ALE high */
|
||||
#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
|
||||
#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
|
||||
|
||||
#define NAND_CMD_AREA_A ((uint8_t)0x00U)
|
||||
#define NAND_CMD_AREA_B ((uint8_t)0x01U)
|
||||
#define NAND_CMD_AREA_C ((uint8_t)0x50U)
|
||||
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
|
||||
#define NAND_CMD_AREA_A ((uint8_t)0x00)
|
||||
#define NAND_CMD_AREA_B ((uint8_t)0x01)
|
||||
#define NAND_CMD_AREA_C ((uint8_t)0x50)
|
||||
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
|
||||
|
||||
#define NAND_CMD_WRITE0 ((uint8_t)0x80U)
|
||||
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
|
||||
#define NAND_CMD_ERASE0 ((uint8_t)0x60U)
|
||||
#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
|
||||
#define NAND_CMD_READID ((uint8_t)0x90U)
|
||||
#define NAND_CMD_STATUS ((uint8_t)0x70U)
|
||||
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
|
||||
#define NAND_CMD_RESET ((uint8_t)0xFFU)
|
||||
#define NAND_CMD_WRITE0 ((uint8_t)0x80)
|
||||
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
|
||||
#define NAND_CMD_ERASE0 ((uint8_t)0x60)
|
||||
#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
|
||||
#define NAND_CMD_READID ((uint8_t)0x90)
|
||||
#define NAND_CMD_STATUS ((uint8_t)0x70)
|
||||
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
|
||||
#define NAND_CMD_RESET ((uint8_t)0xFF)
|
||||
|
||||
/* NAND memory status */
|
||||
#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
|
||||
#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
|
||||
#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
|
||||
#define NAND_BUSY ((uint32_t)0x00000000U)
|
||||
#define NAND_ERROR ((uint32_t)0x00000001U)
|
||||
#define NAND_READY ((uint32_t)0x00000040U)
|
||||
#define NAND_VALID_ADDRESS 0x00000100UL
|
||||
#define NAND_INVALID_ADDRESS 0x00000200UL
|
||||
#define NAND_TIMEOUT_ERROR 0x00000400UL
|
||||
#define NAND_BUSY 0x00000000UL
|
||||
#define NAND_ERROR 0x00000001UL
|
||||
#define NAND_READY 0x00000040UL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -316,7 +326,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
|
|||
* @retval NAND Raw address value
|
||||
*/
|
||||
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
|
||||
(((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
|
||||
(((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
|
||||
|
||||
/**
|
||||
* @brief NAND memory Column address computation.
|
||||
|
|
|
@ -121,9 +121,11 @@ typedef struct
|
|||
|
||||
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
|
||||
|
||||
uint32_t CommandSet; /*!< NOR algorithm command set and control */
|
||||
|
||||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp Init callback */
|
||||
void (* MspDeInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp DeInit callback */
|
||||
void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */
|
||||
#endif
|
||||
} NOR_HandleTypeDef;
|
||||
|
||||
|
@ -135,7 +137,7 @@ typedef enum
|
|||
{
|
||||
HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */
|
||||
HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */
|
||||
}HAL_NOR_CallbackIDTypeDef;
|
||||
} HAL_NOR_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL NOR Callback pointer definition
|
||||
|
@ -178,7 +180,8 @@ typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
|
|||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
|
||||
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing,
|
||||
FSMC_NORSRAM_TimingTypeDef *ExtTiming);
|
||||
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
|
||||
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
|
||||
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
|
||||
|
@ -197,8 +200,10 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
|
|||
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
|
||||
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
|
||||
|
||||
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
|
||||
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
|
||||
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
|
||||
uint32_t uwBufferSize);
|
||||
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
|
||||
uint32_t uwBufferSize);
|
||||
|
||||
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
|
||||
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
|
||||
|
@ -206,7 +211,8 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
|
|||
|
||||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
|
||||
/* NOR callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
|
||||
pNOR_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
|
||||
#endif
|
||||
/**
|
||||
|
@ -246,29 +252,29 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
|
|||
* @{
|
||||
*/
|
||||
/* NOR device IDs addresses */
|
||||
#define MC_ADDRESS ((uint16_t)0x0000U)
|
||||
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
|
||||
#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
|
||||
#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
|
||||
#define MC_ADDRESS ((uint16_t)0x0000)
|
||||
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
|
||||
#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
|
||||
#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
|
||||
|
||||
/* NOR CFI IDs addresses */
|
||||
#define CFI1_ADDRESS ((uint16_t)0x61U)
|
||||
#define CFI2_ADDRESS ((uint16_t)0x62U)
|
||||
#define CFI3_ADDRESS ((uint16_t)0x63U)
|
||||
#define CFI4_ADDRESS ((uint16_t)0x64U)
|
||||
#define CFI1_ADDRESS ((uint16_t)0x61)
|
||||
#define CFI2_ADDRESS ((uint16_t)0x62)
|
||||
#define CFI3_ADDRESS ((uint16_t)0x63)
|
||||
#define CFI4_ADDRESS ((uint16_t)0x64)
|
||||
|
||||
/* NOR operation wait timeout */
|
||||
#define NOR_TMEOUT ((uint16_t)0xFFFFU)
|
||||
#define NOR_TMEOUT ((uint16_t)0xFFFF)
|
||||
|
||||
/* NOR memory data width */
|
||||
#define NOR_MEMORY_8B ((uint8_t)0x0U)
|
||||
#define NOR_MEMORY_16B ((uint8_t)0x1U)
|
||||
#define NOR_MEMORY_8B ((uint8_t)0x0)
|
||||
#define NOR_MEMORY_16B ((uint8_t)0x1)
|
||||
|
||||
/* NOR memory device read/write start address */
|
||||
#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
|
||||
#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
|
||||
#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
|
||||
#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
|
||||
#define NOR_MEMORY_ADRESS1 (0x60000000U)
|
||||
#define NOR_MEMORY_ADRESS2 (0x64000000U)
|
||||
#define NOR_MEMORY_ADRESS3 (0x68000000U)
|
||||
#define NOR_MEMORY_ADRESS4 (0x6C000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -285,7 +291,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
|
|||
* @retval NOR shifted address value
|
||||
*/
|
||||
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
|
||||
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
|
||||
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
|
||||
((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
|
||||
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
|
||||
|
||||
|
|
|
@ -80,9 +80,9 @@ typedef struct
|
|||
HAL_LockTypeDef Lock; /*!< PCCARD Lock */
|
||||
|
||||
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD Msp Init callback */
|
||||
void (* MspDeInitCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD Msp DeInit callback */
|
||||
void (* ItCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD IT callback */
|
||||
void (* MspInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp DeInit callback */
|
||||
void (* ItCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD IT callback */
|
||||
#endif
|
||||
} PCCARD_HandleTypeDef;
|
||||
|
||||
|
@ -95,7 +95,7 @@ typedef enum
|
|||
HAL_PCCARD_MSP_INIT_CB_ID = 0x00U, /*!< PCCARD MspInit Callback ID */
|
||||
HAL_PCCARD_MSP_DEINIT_CB_ID = 0x01U, /*!< PCCARD MspDeInit Callback ID */
|
||||
HAL_PCCARD_IT_CB_ID = 0x02U /*!< PCCARD IT Callback ID */
|
||||
}HAL_PCCARD_CallbackIDTypeDef;
|
||||
} HAL_PCCARD_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL PCCARD Callback pointer definition
|
||||
|
@ -137,7 +137,8 @@ typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
|
|||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
|
||||
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming,
|
||||
FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
|
||||
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
|
||||
void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
|
||||
void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
|
||||
|
@ -150,8 +151,10 @@ void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
|
|||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
|
||||
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
|
||||
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
|
||||
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
|
||||
uint8_t *pStatus);
|
||||
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
|
||||
uint8_t *pStatus);
|
||||
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
|
||||
HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
|
||||
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
|
||||
|
@ -159,8 +162,10 @@ void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
|
|||
|
||||
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
|
||||
/* PCCARD callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, pPCCARD_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId);
|
||||
HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId,
|
||||
pPCCARD_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard,
|
||||
HAL_PCCARD_CallbackIDTypeDef CallbackId);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
|
|
|
@ -104,22 +104,22 @@ typedef struct __PCD_HandleTypeDef
|
|||
typedef struct
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
{
|
||||
PCD_TypeDef *Instance; /*!< Register base address */
|
||||
PCD_InitTypeDef Init; /*!< PCD required parameters */
|
||||
__IO uint8_t USB_Address; /*!< USB Address */
|
||||
PCD_TypeDef *Instance; /*!< Register base address */
|
||||
PCD_InitTypeDef Init; /*!< PCD required parameters */
|
||||
__IO uint8_t USB_Address; /*!< USB Address */
|
||||
#if defined (USB_OTG_FS)
|
||||
PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
|
||||
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
|
||||
PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
|
||||
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
#if defined (USB)
|
||||
PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
|
||||
PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
|
||||
#endif /* defined (USB) */
|
||||
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
|
||||
__IO PCD_StateTypeDef State; /*!< PCD communication state */
|
||||
__IO uint32_t ErrorCode; /*!< PCD Error code */
|
||||
uint32_t Setup[12]; /*!< Setup packet buffer */
|
||||
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
|
||||
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
|
||||
__IO PCD_StateTypeDef State; /*!< PCD communication state */
|
||||
__IO uint32_t ErrorCode; /*!< PCD Error code */
|
||||
uint32_t Setup[12]; /*!< Setup packet buffer */
|
||||
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
|
||||
uint32_t BESL;
|
||||
|
||||
void *pData; /*!< Pointer to upper stack Handler */
|
||||
|
@ -191,9 +191,9 @@ typedef struct
|
|||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Macros PCD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
#if defined (USB_OTG_FS)
|
||||
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
|
@ -203,12 +203,11 @@ typedef struct
|
|||
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
|
||||
|
||||
|
||||
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
|
||||
~(USB_OTG_PCGCCTL_STOPCLK)
|
||||
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
|
||||
|
||||
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
|
||||
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
|
||||
|
||||
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
|
||||
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
|
||||
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||
|
@ -216,28 +215,28 @@ typedef struct
|
|||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
|
||||
do { \
|
||||
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
|
||||
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
|
||||
} while(0U)
|
||||
do { \
|
||||
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
|
||||
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
|
||||
} while(0U)
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
|
||||
#if defined (USB)
|
||||
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
|
||||
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__)))
|
||||
|
||||
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
|
||||
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
|
||||
|
||||
#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
|
||||
do { \
|
||||
EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
|
||||
EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \
|
||||
} while(0U)
|
||||
#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
|
||||
do { \
|
||||
EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
|
||||
EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \
|
||||
} while(0U)
|
||||
|
||||
#endif /* defined (USB) */
|
||||
|
||||
|
@ -272,7 +271,7 @@ typedef enum
|
|||
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
|
||||
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
|
||||
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
|
||||
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
|
||||
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
|
||||
|
||||
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
|
||||
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
|
||||
|
@ -297,19 +296,31 @@ typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t
|
|||
* @}
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
|
||||
HAL_PCD_CallbackIDTypeDef CallbackID,
|
||||
pPCD_CallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
|
||||
HAL_PCD_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_DataOutStageCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_DataInStageCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_IsoOutIncpltCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_IsoInIncpltCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
|
@ -325,6 +336,7 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
|
|||
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
@ -349,16 +361,24 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
|||
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint16_t ep_mps, uint8_t ep_type);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint8_t *pBuf, uint32_t len);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint8_t *pBuf, uint32_t len);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -384,15 +404,11 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @{
|
||||
*/
|
||||
#if defined (USB_OTG_FS)
|
||||
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
|
||||
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
|
||||
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
|
||||
|
||||
#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
|
||||
#if defined (USB)
|
||||
#define USB_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
|
||||
#define USB_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
|
||||
#endif /* defined (USB) */
|
||||
|
||||
/**
|
||||
|
@ -402,10 +418,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
/** @defgroup PCD_EP0_MPS PCD EP0 MPS
|
||||
* @{
|
||||
*/
|
||||
#define PCD_EP0MPS_64 DEP0CTL_MPS_64
|
||||
#define PCD_EP0MPS_32 DEP0CTL_MPS_32
|
||||
#define PCD_EP0MPS_16 DEP0CTL_MPS_16
|
||||
#define PCD_EP0MPS_08 DEP0CTL_MPS_8
|
||||
#define PCD_EP0MPS_64 EP_MPS_64
|
||||
#define PCD_EP0MPS_32 EP_MPS_32
|
||||
#define PCD_EP0MPS_16 EP_MPS_16
|
||||
#define PCD_EP0MPS_08 EP_MPS_8
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -466,8 +482,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup PCD_Private_Macros PCD Private Macros
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
#if defined (USB)
|
||||
/******************** Bit definition for USB_COUNTn_RX register *************/
|
||||
#define USB_CNTRX_NBLK_MSK (0x1FU << 10)
|
||||
|
@ -477,10 +493,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
|
||||
|
||||
/* GetENDPOINT */
|
||||
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
|
||||
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
|
||||
|
||||
/* ENDPOINT transfer */
|
||||
#define USB_EP0StartXfer USB_EPStartXfer
|
||||
#define USB_EP0StartXfer USB_EPStartXfer
|
||||
|
||||
/**
|
||||
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
|
||||
|
@ -489,8 +505,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @param wType Endpoint Type.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
|
||||
((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
|
||||
#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
|
||||
|
||||
/**
|
||||
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
|
||||
|
@ -507,18 +522,19 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @param bEpNum, bDir
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) do { \
|
||||
if ((bDir) == 0U) \
|
||||
{ \
|
||||
/* OUT double buffered endpoint */ \
|
||||
PCD_TX_DTOG((USBx), (bEpNum)); \
|
||||
} \
|
||||
else if ((bDir) == 1U) \
|
||||
{ \
|
||||
/* IN double buffered endpoint */ \
|
||||
PCD_RX_DTOG((USBx), (bEpNum)); \
|
||||
} \
|
||||
} while(0)
|
||||
#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \
|
||||
do { \
|
||||
if ((bDir) == 0U) \
|
||||
{ \
|
||||
/* OUT double buffered endpoint */ \
|
||||
PCD_TX_DTOG((USBx), (bEpNum)); \
|
||||
} \
|
||||
else if ((bDir) == 1U) \
|
||||
{ \
|
||||
/* IN double buffered endpoint */ \
|
||||
PCD_RX_DTOG((USBx), (bEpNum)); \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
|
||||
|
@ -527,21 +543,22 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @param wState new state
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
\
|
||||
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
|
||||
/* toggle first bit ? */ \
|
||||
if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
|
||||
{ \
|
||||
/* toggle first bit ? */ \
|
||||
if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPTX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
|
||||
{ \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPTX_DTOG2; \
|
||||
} \
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} \
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_SET_EP_TX_STATUS */
|
||||
|
||||
/**
|
||||
|
@ -551,19 +568,20 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @param wState new state
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
|
||||
/* toggle first bit ? */ \
|
||||
if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPRX_DTOG1; \
|
||||
_wRegVal ^= USB_EPRX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPRX_DTOG2; \
|
||||
_wRegVal ^= USB_EPRX_DTOG2; \
|
||||
} \
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_SET_EP_RX_STATUS */
|
||||
|
@ -576,8 +594,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @param wStatetx new state.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
|
||||
/* toggle first bit ? */ \
|
||||
|
@ -629,10 +648,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @param bEpNum Endpoint Number.
|
||||
* @retval TRUE = endpoint in stall condition.
|
||||
*/
|
||||
#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
|
||||
== USB_EP_TX_STALL)
|
||||
#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
|
||||
== USB_EP_RX_STALL)
|
||||
#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
|
||||
#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
|
||||
|
||||
/**
|
||||
* @brief set & clear EP_KIND bit.
|
||||
|
@ -640,16 +657,18 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_KIND(USBx, bEpNum) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
#define PCD_SET_EP_KIND(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
|
||||
} while(0) /* PCD_SET_EP_KIND */
|
||||
|
||||
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
|
||||
\
|
||||
|
@ -680,16 +699,18 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_CLEAR_RX_EP_CTR */
|
||||
|
||||
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
|
||||
\
|
||||
|
@ -702,16 +723,18 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_RX_DTOG(USBx, bEpNum) do { \
|
||||
register uint16_t _wEPVal; \
|
||||
#define PCD_RX_DTOG(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wEPVal; \
|
||||
\
|
||||
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
|
||||
} while(0) /* PCD_RX_DTOG */
|
||||
|
||||
#define PCD_TX_DTOG(USBx, bEpNum) do { \
|
||||
register uint16_t _wEPVal; \
|
||||
#define PCD_TX_DTOG(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wEPVal; \
|
||||
\
|
||||
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
|
||||
\
|
||||
|
@ -723,8 +746,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
|
||||
\
|
||||
|
@ -734,8 +758,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
} \
|
||||
} while(0) /* PCD_CLEAR_RX_DTOG */
|
||||
|
||||
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
|
||||
\
|
||||
|
@ -752,8 +777,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @param bAddr Address.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
|
||||
\
|
||||
|
@ -778,23 +804,25 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @param wAddr address to be set (must be word aligned).
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \
|
||||
register __IO uint16_t *_wRegVal; \
|
||||
register uint32_t _wRegBase = (uint32_t)USBx; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
|
||||
*_wRegVal = ((wAddr) >> 1) << 1; \
|
||||
} while(0) /* PCD_SET_EP_TX_ADDRESS */
|
||||
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
|
||||
do { \
|
||||
__IO uint16_t *_wRegVal; \
|
||||
uint32_t _wRegBase = (uint32_t)USBx; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
|
||||
*_wRegVal = ((wAddr) >> 1) << 1; \
|
||||
} while(0) /* PCD_SET_EP_TX_ADDRESS */
|
||||
|
||||
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \
|
||||
register __IO uint16_t *_wRegVal; \
|
||||
register uint32_t _wRegBase = (uint32_t)USBx; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
|
||||
*_wRegVal = ((wAddr) >> 1) << 1; \
|
||||
} while(0) /* PCD_SET_EP_RX_ADDRESS */
|
||||
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
|
||||
do { \
|
||||
__IO uint16_t *_wRegVal; \
|
||||
uint32_t _wRegBase = (uint32_t)USBx; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
|
||||
*_wRegVal = ((wAddr) >> 1) << 1; \
|
||||
} while(0) /* PCD_SET_EP_RX_ADDRESS */
|
||||
|
||||
/**
|
||||
* @brief Gets address of the tx/rx buffer.
|
||||
|
@ -812,7 +840,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @param wNBlocks no. of Blocks.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \
|
||||
#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
|
||||
do { \
|
||||
(wNBlocks) = (wCount) >> 5; \
|
||||
if (((wCount) & 0x1fU) == 0U) \
|
||||
{ \
|
||||
|
@ -821,7 +850,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
*(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
|
||||
} while(0) /* PCD_CALC_BLK32 */
|
||||
|
||||
#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) do { \
|
||||
#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
|
||||
do { \
|
||||
(wNBlocks) = (wCount) >> 1; \
|
||||
if (((wCount) & 0x1U) != 0U) \
|
||||
{ \
|
||||
|
@ -830,7 +860,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
*(pdwReg) = (uint16_t)((wNBlocks) << 10); \
|
||||
} while(0) /* PCD_CALC_BLK2 */
|
||||
|
||||
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) do { \
|
||||
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
|
||||
do { \
|
||||
uint32_t wNBlocks; \
|
||||
if ((wCount) == 0U) \
|
||||
{ \
|
||||
|
@ -847,10 +878,11 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
} \
|
||||
} while(0) /* PCD_SET_EP_CNT_RX_REG */
|
||||
|
||||
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \
|
||||
register uint32_t _wRegBase = (uint32_t)(USBx); \
|
||||
register __IO uint16_t *pdwReg; \
|
||||
\
|
||||
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
|
||||
do { \
|
||||
uint32_t _wRegBase = (uint32_t)(USBx); \
|
||||
__IO uint16_t *pdwReg; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
|
||||
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
|
||||
|
@ -863,23 +895,25 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @param wCount Counter value.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \
|
||||
register uint32_t _wRegBase = (uint32_t)(USBx); \
|
||||
register __IO uint16_t *_wRegVal; \
|
||||
#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
|
||||
do { \
|
||||
uint32_t _wRegBase = (uint32_t)(USBx); \
|
||||
__IO uint16_t *_wRegVal; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
|
||||
*_wRegVal = (uint16_t)(wCount); \
|
||||
} while(0)
|
||||
} while(0)
|
||||
|
||||
#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \
|
||||
register uint32_t _wRegBase = (uint32_t)(USBx); \
|
||||
register __IO uint16_t *_wRegVal; \
|
||||
#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
|
||||
do { \
|
||||
uint32_t _wRegBase = (uint32_t)(USBx); \
|
||||
__IO uint16_t *_wRegVal; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
|
||||
PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
|
||||
} while(0)
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief gets counter of the tx buffer.
|
||||
|
@ -897,10 +931,13 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @param wBuf0Addr buffer 0 address.
|
||||
* @retval Counter value
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) do { \
|
||||
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
|
||||
do { \
|
||||
PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
|
||||
} while(0) /* PCD_SET_EP_DBUF0_ADDR */
|
||||
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) do { \
|
||||
|
||||
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
|
||||
do { \
|
||||
PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
|
||||
} while(0) /* PCD_SET_EP_DBUF1_ADDR */
|
||||
|
||||
|
@ -912,7 +949,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @param wBuf1Addr = buffer 1 address.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) do { \
|
||||
#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
|
||||
do { \
|
||||
PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
|
||||
PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
|
||||
} while(0) /* PCD_SET_EP_DBUF_ADDR */
|
||||
|
@ -935,7 +973,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @param wCount: Counter value
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) do { \
|
||||
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
|
||||
do { \
|
||||
if ((bDir) == 0U) \
|
||||
/* OUT endpoint */ \
|
||||
{ \
|
||||
|
@ -951,8 +990,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
} \
|
||||
} while(0) /* SetEPDblBuf0Count*/
|
||||
|
||||
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \
|
||||
register uint32_t _wBase = (uint32_t)(USBx); \
|
||||
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
|
||||
do { \
|
||||
uint32_t _wBase = (uint32_t)(USBx); \
|
||||
__IO uint16_t *_wEPRegVal; \
|
||||
\
|
||||
if ((bDir) == 0U) \
|
||||
|
@ -972,10 +1012,11 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
} \
|
||||
} while(0) /* SetEPDblBuf1Count */
|
||||
|
||||
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \
|
||||
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
|
||||
do { \
|
||||
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
|
||||
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
|
||||
} while(0) /* PCD_SET_EP_DBUF_CNT */
|
||||
} while(0) /* PCD_SET_EP_DBUF_CNT */
|
||||
|
||||
/**
|
||||
* @brief Gets buffer 0/1 rx/tx counter for double buffering.
|
||||
|
|
|
@ -53,10 +53,8 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
|
|||
#endif /* defined (USB_OTG_FS) */
|
||||
|
||||
#if defined (USB)
|
||||
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
|
||||
uint16_t ep_addr,
|
||||
uint16_t ep_kind,
|
||||
uint32_t pmaadress);
|
||||
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
|
||||
uint16_t ep_kind, uint32_t pmaadress);
|
||||
|
||||
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
|
||||
#endif /* defined (USB) */
|
||||
|
|
|
@ -330,11 +330,11 @@ typedef struct
|
|||
*/
|
||||
#define RCC_PERIPHCLK_RTC 0x00000001U
|
||||
#define RCC_PERIPHCLK_ADC 0x00000002U
|
||||
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
|
||||
|| defined(STM32F107xC)
|
||||
#if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE)\
|
||||
|| defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define RCC_PERIPHCLK_I2S2 0x00000004U
|
||||
#define RCC_PERIPHCLK_I2S3 0x00000008U
|
||||
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||
#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|
||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|
||||
|| defined(STM32F105xC) || defined(STM32F107xC)
|
||||
|
|
|
@ -708,7 +708,7 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
|
|||
|
||||
#define SMARTCARD_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25U)/(4U*(__BAUD__)))
|
||||
#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100U)
|
||||
#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U + 50U) / 100U)
|
||||
#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) ((((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U) + 50U) / 100U)
|
||||
/* SMARTCARD BRR = mantissa + overflow + fraction
|
||||
= (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
|
||||
#define SMARTCARD_BRR(__PCLK__, __BAUD__) (((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4U) + \
|
||||
|
|
|
@ -487,7 +487,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __SR__ copy of SPI SR regsiter.
|
||||
* @param __SR__ copy of SPI SR register.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
|
||||
|
@ -498,10 +498,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
* @arg SPI_FLAG_BSY: Busy flag
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
|
||||
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
|
||||
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
||||
* @param __CR2__ copy of SPI CR2 regsiter.
|
||||
* @param __CR2__ copy of SPI CR2 register.
|
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
|
@ -509,15 +510,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
|
||||
(__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks if SPI Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI Mode.
|
||||
* This parameter can be a value of @ref SPI_Mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
|
||||
((__MODE__) == SPI_MODE_MASTER))
|
||||
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
|
||||
((__MODE__) == SPI_MODE_MASTER))
|
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI Direction Mode.
|
||||
|
@ -554,25 +556,25 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
* This parameter can be a value of @ref SPI_Clock_Polarity
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
|
||||
((__CPOL__) == SPI_POLARITY_HIGH))
|
||||
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
|
||||
((__CPOL__) == SPI_POLARITY_HIGH))
|
||||
|
||||
/** @brief Checks if SPI Clock Phase parameter is in allowed range.
|
||||
* @param __CPHA__ specifies the SPI Clock Phase.
|
||||
* This parameter can be a value of @ref SPI_Clock_Phase
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
|
||||
((__CPHA__) == SPI_PHASE_2EDGE))
|
||||
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
|
||||
((__CPHA__) == SPI_PHASE_2EDGE))
|
||||
|
||||
/** @brief Checks if SPI Slave Select parameter is in allowed range.
|
||||
* @param __NSS__ specifies the SPI Slave Select management parameter.
|
||||
* This parameter can be a value of @ref SPI_Slave_Select_management
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_INPUT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_OUTPUT))
|
||||
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_INPUT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_OUTPUT))
|
||||
|
||||
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
|
||||
* @param __PRESCALER__ specifies the SPI Baudrate prescaler.
|
||||
|
@ -593,8 +595,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
* This parameter can be a value of @ref SPI_MSB_LSB_transmission
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
|
||||
((__BIT__) == SPI_FIRSTBIT_LSB))
|
||||
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
|
||||
((__BIT__) == SPI_FIRSTBIT_LSB))
|
||||
|
||||
/** @brief Checks if SPI TI mode parameter is disabled.
|
||||
* @param __MODE__ SPI_TIMODE_DISABLE. Device not support Ti Mode.
|
||||
|
@ -616,7 +618,9 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
|||
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))
|
||||
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
|
||||
((__POLYNOMIAL__) <= 0xFFFFU) && \
|
||||
(((__POLYNOMIAL__)&0x1U) != 0U))
|
||||
|
||||
/** @brief Checks if DMA handle is valid.
|
||||
* @param __HANDLE__ specifies a DMA Handle.
|
||||
|
|
|
@ -62,7 +62,7 @@ typedef enum
|
|||
typedef struct __SRAM_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
|
||||
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
|
||||
{
|
||||
FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
|
@ -77,10 +77,10 @@ typedef struct
|
|||
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
|
||||
|
||||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp Init callback */
|
||||
void (* MspDeInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp DeInit callback */
|
||||
void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Complete callback */
|
||||
void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Error callback */
|
||||
void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */
|
||||
void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */
|
||||
void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */
|
||||
#endif
|
||||
} SRAM_HandleTypeDef;
|
||||
|
||||
|
@ -94,7 +94,7 @@ typedef enum
|
|||
HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */
|
||||
HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */
|
||||
HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */
|
||||
}HAL_SRAM_CallbackIDTypeDef;
|
||||
} HAL_SRAM_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SRAM Callback pointer definition
|
||||
|
@ -110,8 +110,8 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
|
|||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SRAM handle state
|
||||
* @param __HANDLE__ SRAM handle
|
||||
|
@ -137,11 +137,12 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
|
|||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
|
||||
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing,
|
||||
FSMC_NORSRAM_TimingTypeDef *ExtTiming);
|
||||
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
|
||||
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
|
||||
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
|
||||
|
@ -151,27 +152,37 @@ void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
|
|||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
|
||||
uint32_t BufferSize);
|
||||
|
||||
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
|
||||
|
||||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
||||
/* SRAM callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
|
||||
pSRAM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
|
||||
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
|
||||
pSRAM_DmaCallbackTypeDef pCallback);
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -179,8 +190,8 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR
|
|||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SRAM Control functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
|
||||
|
@ -191,8 +202,8 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
|
|||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SRAM State functions ******************************************************/
|
||||
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
|
||||
|
|
|
@ -167,7 +167,7 @@ typedef struct
|
|||
This parameter can be a value of @ref TIM_Encoder_Mode */
|
||||
|
||||
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
|
||||
|
||||
uint32_t IC1Selection; /*!< Specifies the input.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Selection */
|
||||
|
@ -179,7 +179,7 @@ typedef struct
|
|||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
|
||||
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
|
||||
|
||||
uint32_t IC2Selection; /*!< Specifies the input.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Selection */
|
||||
|
@ -294,6 +294,26 @@ typedef enum
|
|||
HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
|
||||
} HAL_TIM_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Channel States definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
|
||||
HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
|
||||
HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
|
||||
} HAL_TIM_ChannelStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA Burst States definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
|
||||
HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
|
||||
HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
|
||||
} HAL_TIM_DMABurstStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Active channel structures definition
|
||||
*/
|
||||
|
@ -315,13 +335,16 @@ typedef struct __TIM_HandleTypeDef
|
|||
typedef struct
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
{
|
||||
TIM_TypeDef *Instance; /*!< Register base address */
|
||||
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
|
||||
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
|
||||
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
|
||||
This array is accessed by a @ref DMA_Handle_index */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
|
||||
TIM_TypeDef *Instance; /*!< Register base address */
|
||||
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
|
||||
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
|
||||
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
|
||||
This array is accessed by a @ref DMA_Handle_index */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
|
||||
__IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */
|
||||
__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
|
||||
__IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
|
||||
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
|
||||
|
@ -360,34 +383,34 @@ typedef struct
|
|||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
|
||||
,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
|
||||
,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
|
||||
,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
|
||||
,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
|
||||
,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
|
||||
,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
|
||||
,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
|
||||
,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
|
||||
,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
|
||||
,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
|
||||
,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
|
||||
,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
|
||||
,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
|
||||
,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
|
||||
,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
|
||||
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
|
||||
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
|
||||
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
|
||||
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
|
||||
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
|
||||
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
|
||||
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
|
||||
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
|
||||
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
|
||||
|
||||
,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
|
||||
,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
|
||||
,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
|
||||
,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
|
||||
,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
|
||||
,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
|
||||
,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
|
||||
,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
|
||||
,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
|
||||
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
|
||||
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
|
||||
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
|
||||
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
|
||||
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
|
||||
, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
|
||||
, HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
|
||||
} HAL_TIM_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
|
@ -593,6 +616,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
|
||||
#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
|
||||
* @{
|
||||
*/
|
||||
|
@ -984,25 +1016,45 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
|||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
|
||||
(__HANDLE__)->Base_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
|
||||
(__HANDLE__)->Base_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
|
||||
} while(0)
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
|
@ -1547,6 +1599,9 @@ mode.
|
|||
#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
|
||||
((__STATE__) == TIM_OCNIDLESTATE_RESET))
|
||||
|
||||
#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
|
||||
((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
|
||||
|
||||
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
|
||||
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
|
||||
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
|
||||
|
@ -1698,15 +1753,15 @@ mode.
|
|||
#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
|
||||
((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
|
||||
|
||||
#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
|
||||
#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
|
||||
|
@ -1717,6 +1772,8 @@ mode.
|
|||
((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
|
||||
|
||||
#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
|
||||
|
||||
#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
|
||||
|
||||
#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
|
||||
|
@ -1742,11 +1799,49 @@ mode.
|
|||
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
|
||||
|
||||
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP))) :\
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\
|
||||
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))
|
||||
|
||||
#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
|
||||
(__HANDLE__)->ChannelState[3])
|
||||
|
||||
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
|
||||
((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
|
||||
|
||||
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
|
||||
(__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
|
||||
} while(0)
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
|
||||
(__HANDLE__)->ChannelNState[3])
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
|
||||
((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
|
||||
(__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -1918,9 +2013,15 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC
|
|||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
|
||||
uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
|
||||
uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
|
||||
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
|
||||
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
@ -1966,6 +2067,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
|
|||
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
|
||||
|
||||
/* Peripheral Channel state functions ************************************************/
|
||||
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -1985,7 +2091,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
|
|||
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
|
||||
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
|
||||
|
||||
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
|
||||
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
|
||||
void TIM_DMAError(DMA_HandleTypeDef *hdma);
|
||||
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
|
||||
|
|
|
@ -223,6 +223,7 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
|
|||
*/
|
||||
/* Extended Peripheral State functions ***************************************/
|
||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -537,7 +537,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
|
|||
(((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
|
||||
|
||||
/** @brief Checks whether the specified UART interrupt has occurred or not.
|
||||
/** @brief Checks whether the specified UART interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* UART Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
|
@ -806,7 +806,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
|
|||
|
||||
#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
|
||||
#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
|
||||
#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
|
||||
#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
|
||||
/* UART BRR = mantissa + overflow + fraction
|
||||
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
|
||||
#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
|
||||
|
@ -815,7 +815,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
|
|||
|
||||
#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
|
||||
#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
|
||||
#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
|
||||
#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U)
|
||||
/* UART BRR = mantissa + overflow + fraction
|
||||
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
|
||||
#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
|
||||
|
|
|
@ -607,7 +607,7 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
|
|||
|
||||
#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
|
||||
|
||||
#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
|
||||
#define USART_DIVFRAQ(_PCLK_, _BAUD_) ((((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
|
||||
|
||||
/* UART BRR = mantissa + overflow + fraction
|
||||
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF0) << 1) + (UART DIVFRAQ & 0x0FU) */
|
||||
|
|
|
@ -37,6 +37,7 @@ extern "C" {
|
|||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Types WWDG Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
@ -55,7 +56,7 @@ typedef struct
|
|||
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
|
||||
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
|
||||
|
||||
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
|
||||
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
|
||||
This parameter can be a value of @ref WWDG_EWI_Mode */
|
||||
|
||||
} WWDG_InitTypeDef;
|
||||
|
@ -67,16 +68,17 @@ typedef struct
|
|||
typedef struct __WWDG_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
{
|
||||
WWDG_TypeDef *Instance; /*!< Register base address */
|
||||
WWDG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
|
||||
|
||||
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
|
||||
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
|
||||
|
||||
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
|
||||
#endif
|
||||
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
} WWDG_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
|
@ -85,16 +87,16 @@ typedef struct
|
|||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
|
||||
HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
|
||||
}HAL_WWDG_CallbackIDTypeDef;
|
||||
HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */
|
||||
HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */
|
||||
} HAL_WWDG_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL WWDG Callback pointer definition
|
||||
*/
|
||||
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer to a WWDG common callback functions */
|
||||
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
|
||||
|
||||
#endif
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -125,10 +127,10 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer t
|
|||
/** @defgroup WWDG_Prescaler WWDG Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
|
||||
#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
|
||||
#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
|
||||
#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
|
||||
#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
|
||||
#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
|
||||
#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
|
||||
#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -136,7 +138,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer t
|
|||
/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_EWI_DISABLE 0x00000000U /*!< EWI Disable */
|
||||
#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
|
||||
#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
|
||||
/**
|
||||
* @}
|
||||
|
@ -151,9 +153,9 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer t
|
|||
/** @defgroup WWDG_Private_Macros WWDG Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
|
||||
((__PRESCALER__) == WWDG_PRESCALER_2) || \
|
||||
((__PRESCALER__) == WWDG_PRESCALER_4) || \
|
||||
#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
|
||||
((__PRESCALER__) == WWDG_PRESCALER_2) || \
|
||||
((__PRESCALER__) == WWDG_PRESCALER_4) || \
|
||||
((__PRESCALER__) == WWDG_PRESCALER_8))
|
||||
|
||||
#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
|
||||
|
@ -174,14 +176,14 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer t
|
|||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables the WWDG peripheral.
|
||||
* @param __HANDLE__: WWDG handle
|
||||
* @brief Enable the WWDG peripheral.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
|
||||
#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
|
||||
|
||||
/**
|
||||
* @brief Enables the WWDG early wakeup interrupt.
|
||||
* @brief Enable the WWDG early wakeup interrupt.
|
||||
* @param __HANDLE__: WWDG handle
|
||||
* @param __INTERRUPT__ specifies the interrupt to enable.
|
||||
* This parameter can be one of the following values:
|
||||
|
@ -192,23 +194,23 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer t
|
|||
#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the selected WWDG interrupt has occurred or not.
|
||||
* @brief Check whether the selected WWDG interrupt has occurred or not.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @param __INTERRUPT__ specifies the it to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
|
||||
* @retval The new state of WWDG_FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
|
||||
#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
|
||||
|
||||
/** @brief Clear the WWDG's interrupt pending bits
|
||||
/** @brief Clear the WWDG interrupt pending bits.
|
||||
* bits to clear the selected interrupt pending bits.
|
||||
* @param __HANDLE__: WWDG handle
|
||||
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
|
||||
*/
|
||||
#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
|
||||
#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified WWDG flag is set or not.
|
||||
|
@ -218,32 +220,34 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer t
|
|||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
|
||||
* @retval The new state of WWDG_FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clears the WWDG's pending flags.
|
||||
* @param __HANDLE__: WWDG handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* @brief Clear the WWDG's pending flags.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
|
||||
#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
|
||||
|
||||
/** @brief Checks if the specified WWDG interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: WWDG Handle.
|
||||
* @param __INTERRUPT__: specifies the WWDG interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
/** @brief Check whether the specified WWDG interrupt source is enabled or not.
|
||||
* @param __HANDLE__ WWDG Handle.
|
||||
* @param __INTERRUPT__ specifies the WWDG interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
|
||||
* @retval state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup WWDG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
@ -254,12 +258,12 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer t
|
|||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
|
||||
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
|
||||
pWWDG_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
|
||||
#endif
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
@ -67,7 +67,7 @@ extern "C" {
|
|||
#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
|
||||
((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
|
||||
#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
|
||||
((__MODE__) == FSMC_WRAP_MODE_ENABLE))
|
||||
((__MODE__) == FSMC_WRAP_MODE_ENABLE))
|
||||
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
|
||||
((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
|
||||
#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
|
||||
|
@ -97,9 +97,9 @@ extern "C" {
|
|||
|
||||
#define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3)
|
||||
#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
|
||||
((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
|
||||
((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
|
||||
#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
|
||||
((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
|
||||
((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
|
||||
#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
|
||||
((__STATE__) == FSMC_NAND_ECC_ENABLE))
|
||||
|
||||
|
@ -212,7 +212,7 @@ typedef struct
|
|||
|
||||
uint32_t PageSize; /*!< Specifies the memory page size.
|
||||
This parameter can be a value of @ref FSMC_Page_Size */
|
||||
}FSMC_NORSRAM_InitTypeDef;
|
||||
} FSMC_NORSRAM_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NORSRAM Timing parameters structure definition
|
||||
|
@ -255,7 +255,7 @@ typedef struct
|
|||
|
||||
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
|
||||
This parameter can be a value of @ref FSMC_Access_Mode */
|
||||
}FSMC_NORSRAM_TimingTypeDef;
|
||||
} FSMC_NORSRAM_TimingTypeDef;
|
||||
#endif /* FSMC_BANK1 */
|
||||
|
||||
#if defined(FSMC_BANK3)
|
||||
|
@ -286,7 +286,7 @@ typedef struct
|
|||
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
|
||||
}FSMC_NAND_InitTypeDef;
|
||||
} FSMC_NAND_InitTypeDef;
|
||||
#endif
|
||||
|
||||
#if defined(FSMC_BANK3)||defined(FSMC_BANK4)
|
||||
|
@ -319,7 +319,7 @@ typedef struct
|
|||
write access to common/Attribute or I/O memory space (depending
|
||||
on the memory space timing to be configured).
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
|
||||
}FSMC_NAND_PCC_TimingTypeDef;
|
||||
} FSMC_NAND_PCC_TimingTypeDef;
|
||||
#endif /* FSMC_BANK3 */
|
||||
|
||||
#if defined(FSMC_BANK4)
|
||||
|
@ -358,10 +358,10 @@ typedef struct
|
|||
/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
|
||||
#define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
|
||||
#define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
|
||||
#define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
|
||||
#define FSMC_NORSRAM_BANK1 (0x00000000U)
|
||||
#define FSMC_NORSRAM_BANK2 (0x00000002U)
|
||||
#define FSMC_NORSRAM_BANK3 (0x00000004U)
|
||||
#define FSMC_NORSRAM_BANK4 (0x00000006U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -369,8 +369,8 @@ typedef struct
|
|||
/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
|
||||
#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
|
||||
#define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
|
||||
#define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -378,9 +378,9 @@ typedef struct
|
|||
/** @defgroup FSMC_Memory_Type FSMC Memory Type
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
|
||||
#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
|
||||
#define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
|
||||
#define FSMC_MEMORY_TYPE_SRAM (0x00000000U)
|
||||
#define FSMC_MEMORY_TYPE_PSRAM (0x00000004U)
|
||||
#define FSMC_MEMORY_TYPE_NOR (0x00000008U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -388,9 +388,9 @@ typedef struct
|
|||
/** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
|
||||
#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
|
||||
#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
|
||||
#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
|
||||
#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
|
||||
#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -398,8 +398,8 @@ typedef struct
|
|||
/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
|
||||
#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
|
||||
#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
|
||||
#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -407,8 +407,8 @@ typedef struct
|
|||
/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
|
||||
#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
|
||||
#define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
|
||||
#define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -416,8 +416,8 @@ typedef struct
|
|||
/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
|
||||
#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
|
||||
#define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
|
||||
#define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -425,8 +425,8 @@ typedef struct
|
|||
/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U)
|
||||
#define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U)
|
||||
#define FSMC_WRAP_MODE_DISABLE (0x00000000U)
|
||||
#define FSMC_WRAP_MODE_ENABLE (0x00000400U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -434,8 +434,8 @@ typedef struct
|
|||
/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
|
||||
#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
|
||||
#define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
|
||||
#define FSMC_WAIT_TIMING_DURING_WS (0x00000800U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -443,8 +443,8 @@ typedef struct
|
|||
/** @defgroup FSMC_Write_Operation FSMC Write Operation
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
|
||||
#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
|
||||
#define FSMC_WRITE_OPERATION_DISABLE (0x00000000U)
|
||||
#define FSMC_WRITE_OPERATION_ENABLE (0x00001000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -452,8 +452,8 @@ typedef struct
|
|||
/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
|
||||
#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
|
||||
#define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U)
|
||||
#define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -461,8 +461,8 @@ typedef struct
|
|||
/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
|
||||
#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
|
||||
#define FSMC_EXTENDED_MODE_DISABLE (0x00000000U)
|
||||
#define FSMC_EXTENDED_MODE_ENABLE (0x00004000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -470,8 +470,8 @@ typedef struct
|
|||
/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
|
||||
#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
|
||||
#define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
|
||||
#define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -479,11 +479,11 @@ typedef struct
|
|||
/** @defgroup FSMC_Page_Size FSMC Page Size
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
|
||||
#define FSMC_PAGE_SIZE_128 ((uint32_t)0x00010000U)
|
||||
#define FSMC_PAGE_SIZE_256 ((uint32_t)0x00020000U)
|
||||
#define FSMC_PAGE_SIZE_512 ((uint32_t)0x00030000U)
|
||||
#define FSMC_PAGE_SIZE_1024 ((uint32_t)0x00040000U)
|
||||
#define FSMC_PAGE_SIZE_NONE (0x00000000U)
|
||||
#define FSMC_PAGE_SIZE_128 (0x00010000U)
|
||||
#define FSMC_PAGE_SIZE_256 (0x00020000U)
|
||||
#define FSMC_PAGE_SIZE_512 (0x00030000U)
|
||||
#define FSMC_PAGE_SIZE_1024 (0x00040000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -491,8 +491,8 @@ typedef struct
|
|||
/** @defgroup FSMC_Write_Burst FSMC Write Burst
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
|
||||
#define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
|
||||
#define FSMC_WRITE_BURST_DISABLE (0x00000000U)
|
||||
#define FSMC_WRITE_BURST_ENABLE (0x00080000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -500,19 +500,19 @@ typedef struct
|
|||
/** @defgroup FSMC_Continous_Clock FSMC Continuous Clock
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
|
||||
#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
|
||||
#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
|
||||
#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Access_Mode FSMC Access Mode
|
||||
/** @defgroup FSMC_Access_Mode FSMC Access Mode
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
|
||||
#define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
|
||||
#define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
|
||||
#define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
|
||||
#define FSMC_ACCESS_MODE_A (0x00000000U)
|
||||
#define FSMC_ACCESS_MODE_B (0x10000000U)
|
||||
#define FSMC_ACCESS_MODE_C (0x20000000U)
|
||||
#define FSMC_ACCESS_MODE_D (0x30000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -530,8 +530,8 @@ typedef struct
|
|||
/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NAND_BANK2 ((uint32_t)0x00000010U)
|
||||
#define FSMC_NAND_BANK3 ((uint32_t)0x00000100U)
|
||||
#define FSMC_NAND_BANK2 (0x00000010U)
|
||||
#define FSMC_NAND_BANK3 (0x00000100U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -539,8 +539,8 @@ typedef struct
|
|||
/** @defgroup FSMC_Wait_feature FSMC Wait feature
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
|
||||
#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
|
||||
#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U)
|
||||
#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -549,9 +549,9 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#if defined(FSMC_BANK4)
|
||||
#define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U)
|
||||
#define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U)
|
||||
#endif
|
||||
#define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
|
||||
#define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -559,8 +559,8 @@ typedef struct
|
|||
/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
|
||||
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
|
||||
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U)
|
||||
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -568,8 +568,8 @@ typedef struct
|
|||
/** @defgroup FSMC_ECC FSMC ECC
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
|
||||
#define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
|
||||
#define FSMC_NAND_ECC_DISABLE (0x00000000U)
|
||||
#define FSMC_NAND_ECC_ENABLE (0x00000040U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -577,12 +577,12 @@ typedef struct
|
|||
/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -597,9 +597,9 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#if defined(FSMC_BANK3)||defined(FSMC_BANK4)
|
||||
#define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
|
||||
#define FSMC_IT_LEVEL ((uint32_t)0x00000010U)
|
||||
#define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
|
||||
#define FSMC_IT_RISING_EDGE (0x00000008U)
|
||||
#define FSMC_IT_LEVEL (0x00000010U)
|
||||
#define FSMC_IT_FALLING_EDGE (0x00000020U)
|
||||
#endif /* FSMC_BANK3 */
|
||||
/**
|
||||
* @}
|
||||
|
@ -609,10 +609,10 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#if defined(FSMC_BANK3)||defined(FSMC_BANK4)
|
||||
#define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
|
||||
#define FSMC_FLAG_LEVEL ((uint32_t)0x00000002U)
|
||||
#define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
|
||||
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040U)
|
||||
#define FSMC_FLAG_RISING_EDGE (0x00000001U)
|
||||
#define FSMC_FLAG_LEVEL (0x00000002U)
|
||||
#define FSMC_FLAG_FALLING_EDGE (0x00000004U)
|
||||
#define FSMC_FLAG_FEMPT (0x00000040U)
|
||||
#endif /* FSMC_BANK3 */
|
||||
/**
|
||||
* @}
|
||||
|
@ -642,7 +642,8 @@ typedef struct
|
|||
* @param __BANK__ FSMC_NORSRAM Bank
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCRx_MBKEN)
|
||||
#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
|
||||
|= FSMC_BCRx_MBKEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the NORSRAM device access.
|
||||
|
@ -650,7 +651,8 @@ typedef struct
|
|||
* @param __BANK__ FSMC_NORSRAM Bank
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCRx_MBKEN)
|
||||
#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
|
||||
&= ~FSMC_BCRx_MBKEN)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -659,9 +661,9 @@ typedef struct
|
|||
|
||||
#if defined(FSMC_BANK3)
|
||||
/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
|
||||
* @brief macros to handle NAND device enable/disable
|
||||
* @{
|
||||
*/
|
||||
* @brief macros to handle NAND device enable/disable
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the NAND device access.
|
||||
|
@ -688,9 +690,9 @@ typedef struct
|
|||
|
||||
#if defined(FSMC_BANK4)
|
||||
/** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros
|
||||
* @brief macros to handle PCCARD read/write operations
|
||||
* @{
|
||||
*/
|
||||
* @brief macros to handle PCCARD read/write operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the PCCARD device access.
|
||||
* @param __INSTANCE__ FSMC_PCCARD Instance
|
||||
|
@ -859,10 +861,14 @@ typedef struct
|
|||
/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
|
||||
FSMC_NORSRAM_InitTypeDef *Init);
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
|
||||
FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
|
||||
FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
|
||||
FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -888,8 +894,10 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Dev
|
|||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
|
||||
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
|
||||
FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
|
||||
FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
|
||||
/**
|
||||
* @}
|
||||
|
@ -900,7 +908,8 @@ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
|
|||
*/
|
||||
HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
|
||||
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
|
||||
uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -917,9 +926,12 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval,
|
|||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
|
||||
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
|
||||
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
|
||||
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
|
||||
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
|
||||
FSMC_NAND_PCC_TimingTypeDef *Timing);
|
||||
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
|
||||
FSMC_NAND_PCC_TimingTypeDef *Timing);
|
||||
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
|
||||
FSMC_NAND_PCC_TimingTypeDef *Timing);
|
||||
HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
|
||||
/**
|
||||
* @}
|
||||
|
|
|
@ -341,7 +341,7 @@ typedef struct
|
|||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
|
||||
{
|
||||
register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
|
||||
register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
|
||||
MODIFY_REG(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSITION_VAL(Pin) * 4U)));
|
||||
}
|
||||
|
||||
|
@ -381,7 +381,7 @@ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
|
||||
register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
|
||||
return (READ_BIT(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
|
||||
}
|
||||
|
||||
|
@ -419,7 +419,7 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
|||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
|
||||
{
|
||||
register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
|
||||
register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
|
||||
MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)),
|
||||
(Speed << (POSITION_VAL(Pin) * 4U)));
|
||||
}
|
||||
|
@ -457,7 +457,7 @@ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
|
||||
register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
|
||||
return (READ_BIT(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
|
||||
}
|
||||
|
||||
|
@ -493,7 +493,7 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
|||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
|
||||
{
|
||||
register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
|
||||
register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
|
||||
MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)),
|
||||
(OutputType << (POSITION_VAL(Pin) * 4U)));
|
||||
}
|
||||
|
@ -530,7 +530,7 @@ __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin,
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
|
||||
register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
|
||||
return (READ_BIT(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
|
||||
|
||||
}
|
||||
|
@ -861,7 +861,9 @@ __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMas
|
|||
*/
|
||||
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
|
||||
uint32_t odr = READ_REG(GPIOx->ODR);
|
||||
uint32_t pinmask = ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
|
||||
WRITE_REG(GPIOx->BSRR, ((odr & pinmask) << 16u) | (~odr & pinmask));
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -729,8 +729,8 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
|
|||
__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
|
||||
uint32_t DutyCycle)
|
||||
{
|
||||
register uint32_t freqrange = 0x0U;
|
||||
register uint32_t clockconfig = 0x0U;
|
||||
uint32_t freqrange = 0x0U;
|
||||
uint32_t clockconfig = 0x0U;
|
||||
|
||||
/* Compute frequency range */
|
||||
freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
|
||||
|
|
|
@ -45,12 +45,10 @@ extern "C" {
|
|||
/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
|
||||
#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
|
||||
#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
|
||||
#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -69,7 +67,6 @@ extern "C" {
|
|||
*/
|
||||
#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
|
||||
#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -143,7 +140,7 @@ extern "C" {
|
|||
*/
|
||||
__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
|
||||
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -154,7 +151,7 @@ __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
|
||||
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -165,7 +162,7 @@ __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
|
||||
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -176,7 +173,7 @@ __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
|
||||
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -213,7 +210,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(IWDGx->PR));
|
||||
return (READ_REG(IWDGx->PR));
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -236,7 +233,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(IWDGx->RLR));
|
||||
return (READ_REG(IWDGx->RLR));
|
||||
}
|
||||
|
||||
|
||||
|
@ -256,7 +253,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -267,12 +264,11 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
|
||||
* @brief Check if flags Prescaler & Reload Value Update are reset or not
|
||||
* @rmtoll SR PVU LL_IWDG_IsReady\n
|
||||
* SR RVU LL_IWDG_IsReady
|
||||
* @param IWDGx IWDG Instance
|
||||
|
@ -280,7 +276,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U);
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -296,7 +292,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
|
|||
* @}
|
||||
*/
|
||||
|
||||
#endif /* IWDG) */
|
||||
#endif /* IWDG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
@ -1520,8 +1520,8 @@ __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
|
|||
__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
|
||||
{
|
||||
#if defined(RCC_CFGR2_PREDIV1SRC)
|
||||
register uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC);
|
||||
register uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U);
|
||||
uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC);
|
||||
uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U);
|
||||
return (uint32_t)(pllsrc | predivsrc);
|
||||
#else
|
||||
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
|
||||
|
|
|
@ -675,8 +675,8 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
|
||||
{
|
||||
register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
|
||||
register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
|
||||
uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
|
||||
uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
|
||||
return (Ssm | Ssoe);
|
||||
}
|
||||
|
||||
|
@ -1198,10 +1198,10 @@ typedef struct
|
|||
/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
|
||||
* @{
|
||||
*/
|
||||
#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
|
||||
#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
|
||||
#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
|
||||
#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
|
||||
#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */
|
||||
#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */
|
||||
#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */
|
||||
#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -1536,7 +1536,7 @@ __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the master clock ouput (Pin MCK)
|
||||
* @brief Enable the master clock output (Pin MCK)
|
||||
* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
|
||||
* @param SPIx SPI Instance
|
||||
* @retval None
|
||||
|
@ -1547,7 +1547,7 @@ __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the master clock ouput (Pin MCK)
|
||||
* @brief Disable the master clock output (Pin MCK)
|
||||
* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
|
||||
* @param SPIx SPI Instance
|
||||
* @retval None
|
||||
|
@ -1558,7 +1558,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the master clock ouput (Pin MCK) is enabled
|
||||
* @brief Check if the master clock output (Pin MCK) is enabled
|
||||
* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
|
|
|
@ -198,13 +198,14 @@ typedef struct
|
|||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
|
||||
|
||||
uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
|
||||
uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
|
||||
reaches zero, an update event is generated and counting restarts
|
||||
from the RCR value (N).
|
||||
This means in PWM mode that (N+1) corresponds to:
|
||||
- the number of PWM periods in edge-aligned mode
|
||||
- the number of half PWM period in center-aligned mode
|
||||
This parameter must be a number between 0x00 and 0xFF.
|
||||
GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
|
||||
Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
|
||||
} LL_TIM_InitTypeDef;
|
||||
|
@ -512,8 +513,8 @@ typedef struct
|
|||
*/
|
||||
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
|
||||
#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
|
||||
/**
|
||||
* @}
|
||||
|
@ -1331,7 +1332,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
|
|||
* whether or not a timer instance supports a repetition counter.
|
||||
* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
|
||||
* @param TIMx Timer instance
|
||||
* @param RepetitionCounter between Min_Data=0 and Max_Data=255
|
||||
* @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
|
||||
|
@ -1559,8 +1560,8 @@ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
|
||||
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
|
||||
(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
|
||||
|
@ -1594,8 +1595,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel,
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -1623,8 +1624,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -1653,7 +1654,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -1681,7 +1682,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -1714,7 +1715,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -1742,7 +1743,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel,
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -1763,8 +1764,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
|
||||
|
||||
}
|
||||
|
@ -1785,8 +1786,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
|
||||
|
||||
}
|
||||
|
@ -1807,9 +1808,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
|
||||
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
|
@ -1829,8 +1830,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
|
||||
}
|
||||
|
||||
|
@ -1850,8 +1851,8 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
|
||||
}
|
||||
|
||||
|
@ -1871,9 +1872,9 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
|
||||
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
|
@ -1896,8 +1897,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
|
||||
}
|
||||
|
||||
|
@ -1919,8 +1920,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
|
||||
}
|
||||
|
||||
|
@ -1944,9 +1945,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
|
||||
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
|
@ -2116,8 +2117,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
|
||||
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
|
||||
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
|
||||
|
@ -2144,8 +2145,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -2168,8 +2169,8 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
|
||||
}
|
||||
|
||||
|
@ -2194,8 +2195,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -2219,8 +2220,8 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel,
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
|
||||
}
|
||||
|
||||
|
@ -2257,8 +2258,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
|
||||
}
|
||||
|
||||
|
@ -2294,8 +2295,8 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
|
||||
}
|
||||
|
||||
|
@ -2321,7 +2322,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel
|
|||
*/
|
||||
__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
|
||||
ICPolarity << SHIFT_TAB_CCxP[iChannel]);
|
||||
}
|
||||
|
@ -2347,7 +2348,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
|
||||
SHIFT_TAB_CCxP[iChannel]);
|
||||
}
|
||||
|
|
|
@ -377,7 +377,7 @@ typedef struct
|
|||
*/
|
||||
#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__)))
|
||||
#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
|
||||
#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100)
|
||||
#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16) + 50) / 100)
|
||||
/* USART BRR = mantissa + overflow + fraction
|
||||
= (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */
|
||||
#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
|
||||
|
@ -1050,8 +1050,8 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
|
||||
{
|
||||
register uint32_t usartdiv = 0x0U;
|
||||
register uint32_t brrresult = 0x0U;
|
||||
uint32_t usartdiv = 0x0U;
|
||||
uint32_t brrresult = 0x0U;
|
||||
|
||||
usartdiv = USARTx->BRR;
|
||||
|
||||
|
@ -1101,8 +1101,8 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph
|
|||
*/
|
||||
__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk)
|
||||
{
|
||||
register uint32_t usartdiv = 0x0U;
|
||||
register uint32_t brrresult = 0x0U;
|
||||
uint32_t usartdiv = 0x0U;
|
||||
uint32_t brrresult = 0x0U;
|
||||
|
||||
usartdiv = USARTx->BRR;
|
||||
|
||||
|
|
|
@ -81,7 +81,7 @@ typedef enum
|
|||
} USB_OTG_HCStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief USB OTG Initialization Structure definition
|
||||
* @brief USB Instance Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
@ -94,14 +94,14 @@ typedef struct
|
|||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint32_t speed; /*!< USB Core speed.
|
||||
This parameter can be any value of @ref USB_Core_Speed_ */
|
||||
This parameter can be any value of @ref USB_Core_Speed */
|
||||
|
||||
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
|
||||
|
||||
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
|
||||
|
||||
uint32_t phy_itface; /*!< Select the used PHY interface.
|
||||
This parameter can be any value of @ref USB_Core_PHY_ */
|
||||
This parameter can be any value of @ref USB_Core_PHY */
|
||||
|
||||
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
|
||||
|
||||
|
@ -116,6 +116,7 @@ typedef struct
|
|||
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
|
||||
|
||||
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
|
||||
|
||||
} USB_OTG_CfgTypeDef;
|
||||
|
||||
typedef struct
|
||||
|
@ -155,7 +156,7 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t dev_addr ; /*!< USB device address.
|
||||
uint8_t dev_addr; /*!< USB device address.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
|
||||
|
||||
uint8_t ch_num; /*!< Host channel number.
|
||||
|
@ -197,13 +198,13 @@ typedef struct
|
|||
|
||||
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
|
||||
|
||||
uint32_t ErrCnt; /*!< Host channel error count.*/
|
||||
uint32_t ErrCnt; /*!< Host channel error count. */
|
||||
|
||||
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
|
||||
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
|
||||
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
|
||||
|
||||
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
|
||||
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
|
||||
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
|
||||
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
|
||||
} USB_OTG_HCTypeDef;
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
|
||||
|
@ -282,6 +283,10 @@ typedef struct
|
|||
|
||||
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
|
||||
|
||||
uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */
|
||||
|
||||
uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */
|
||||
|
||||
} USB_EPTypeDef;
|
||||
#endif /* defined (USB) */
|
||||
|
||||
|
@ -314,8 +319,8 @@ typedef struct
|
|||
/** @defgroup USB_LL Device Speed
|
||||
* @{
|
||||
*/
|
||||
#define USBD_FS_SPEED 2U
|
||||
#define USBH_FS_SPEED 1U
|
||||
#define USBD_FS_SPEED 2U
|
||||
#define USBH_FSLS_SPEED 1U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -341,8 +346,8 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#ifndef USBD_FS_TRDT_VALUE
|
||||
#define USBD_FS_TRDT_VALUE 5U
|
||||
#define USBD_DEFAULT_TRDT_VALUE 9U
|
||||
#define USBD_FS_TRDT_VALUE 5U
|
||||
#define USBD_DEFAULT_TRDT_VALUE 9U
|
||||
#endif /* USBD_HS_TRDT_VALUE */
|
||||
/**
|
||||
* @}
|
||||
|
@ -351,8 +356,8 @@ typedef struct
|
|||
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
|
||||
#define USB_OTG_MAX_EP0_SIZE 64U
|
||||
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
|
||||
#define USB_OTG_MAX_EP0_SIZE 64U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -381,10 +386,10 @@ typedef struct
|
|||
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
|
||||
* @{
|
||||
*/
|
||||
#define DEP0CTL_MPS_64 0U
|
||||
#define DEP0CTL_MPS_32 1U
|
||||
#define DEP0CTL_MPS_16 2U
|
||||
#define DEP0CTL_MPS_8 3U
|
||||
#define EP_MPS_64 0U
|
||||
#define EP_MPS_32 1U
|
||||
#define EP_MPS_16 2U
|
||||
#define EP_MPS_8 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -474,10 +479,10 @@ typedef struct
|
|||
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
|
||||
* @{
|
||||
*/
|
||||
#define DEP0CTL_MPS_64 0U
|
||||
#define DEP0CTL_MPS_32 1U
|
||||
#define DEP0CTL_MPS_16 2U
|
||||
#define DEP0CTL_MPS_8 3U
|
||||
#define EP_MPS_64 0U
|
||||
#define EP_MPS_32 1U
|
||||
#define EP_MPS_16 2U
|
||||
#define EP_MPS_8 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -550,7 +555,9 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB
|
|||
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
|
||||
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
|
||||
uint8_t ch_ep_num, uint16_t len);
|
||||
|
||||
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
|
||||
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
|
@ -575,14 +582,12 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
|
|||
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
|
||||
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
|
||||
uint8_t ch_num,
|
||||
uint8_t epnum,
|
||||
uint8_t dev_address,
|
||||
uint8_t speed,
|
||||
uint8_t ep_type,
|
||||
uint16_t mps);
|
||||
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc);
|
||||
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
|
||||
uint8_t epnum, uint8_t dev_address, uint8_t speed,
|
||||
uint8_t ep_type, uint16_t mps);
|
||||
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
|
||||
USB_OTG_HCTypeDef *hc);
|
||||
|
||||
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
|
||||
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
|
||||
|
@ -603,8 +608,6 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num);
|
|||
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
|
||||
void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
|
||||
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
|
||||
|
@ -612,17 +615,25 @@ HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
|
|||
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);
|
||||
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src,
|
||||
uint8_t ch_ep_num, uint16_t len);
|
||||
|
||||
void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
|
||||
|
||||
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx);
|
||||
uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx);
|
||||
uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
|
||||
uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx);
|
||||
uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
|
||||
void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt);
|
||||
|
||||
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
|
||||
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||
|
||||
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
|
||||
uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||
|
||||
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
|
||||
uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||
#endif /* defined (USB) */
|
||||
/**
|
||||
* @}
|
||||
|
|
|
@ -236,11 +236,13 @@ void LL_mDelay(uint32_t Delay);
|
|||
*/
|
||||
|
||||
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
|
||||
#if defined(FLASH_ACR_LATENCY)
|
||||
ErrorStatus LL_SetFlashLatency(uint32_t Frequency);
|
||||
#endif /* FLASH_ACR_LATENCY */
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
|
||||
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
ErrorStatus LL_SetFlashLatency(uint32_t Frequency);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
@ -33,6 +33,7 @@ extern "C" {
|
|||
*/
|
||||
|
||||
#if defined (WWDG)
|
||||
|
||||
/** @defgroup WWDG_LL WWDG
|
||||
* @{
|
||||
*/
|
||||
|
@ -51,18 +52,18 @@ extern "C" {
|
|||
* @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
|
||||
* @{
|
||||
*/
|
||||
#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
|
||||
#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
|
||||
* @{
|
||||
*/
|
||||
#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
|
||||
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
|
||||
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
|
||||
#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
|
||||
* @{
|
||||
*/
|
||||
#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
|
||||
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
|
||||
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
|
||||
#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
@ -53,11 +53,11 @@
|
|||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief STM32F1xx HAL Driver version number V1.1.4
|
||||
* @brief STM32F1xx HAL Driver version number V1.1.6
|
||||
*/
|
||||
#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
|
||||
#define __STM32F1xx_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */
|
||||
#define __STM32F1xx_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */
|
||||
#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\
|
||||
|(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
|
||||
|
@ -322,15 +322,25 @@ uint32_t HAL_GetTickPrio(void)
|
|||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
HAL_TickFreqTypeDef prevTickFreq;
|
||||
|
||||
assert_param(IS_TICKFREQ(Freq));
|
||||
|
||||
if (uwTickFreq != Freq)
|
||||
{
|
||||
/* Back up uwTickFreq frequency */
|
||||
prevTickFreq = uwTickFreq;
|
||||
|
||||
/* Update uwTickFreq global variable used by HAL_InitTick() */
|
||||
uwTickFreq = Freq;
|
||||
|
||||
/* Apply the new tick Freq */
|
||||
status = HAL_InitTick(uwTickPrio);
|
||||
if (status == HAL_OK)
|
||||
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
uwTickFreq = Freq;
|
||||
/* Restore previous tick frequency */
|
||||
uwTickFreq = prevTickFreq;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -1711,20 +1711,23 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
|
|||
|
||||
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
|
||||
/* DMA transfer is on going) */
|
||||
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
|
||||
if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
|
||||
{
|
||||
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
|
||||
|
||||
/* Check if DMA channel effectively disabled */
|
||||
if (tmp_hal_status == HAL_OK)
|
||||
{
|
||||
/* Set ADC state */
|
||||
ADC_STATE_CLR_SET(hadc->State,
|
||||
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
|
||||
HAL_ADC_STATE_READY);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
|
||||
/* Check if DMA channel effectively disabled */
|
||||
if (tmp_hal_status == HAL_OK)
|
||||
{
|
||||
/* Set ADC state */
|
||||
ADC_STATE_CLR_SET(hadc->State,
|
||||
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
|
||||
HAL_ADC_STATE_READY);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -486,17 +486,16 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
|
|||
*/
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint32_t odr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->ODR & GPIO_Pin) != 0x00u)
|
||||
{
|
||||
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
||||
}
|
||||
/* get current Ouput Data Register value */
|
||||
odr = GPIOx->ODR;
|
||||
|
||||
/* Set selected pins that were at low level, and reset ones that were high */
|
||||
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -88,8 +88,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
|
|||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
|
@ -595,6 +595,18 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Handles HCD Wakeup interrupt request.
|
||||
* @param hhcd HCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd)
|
||||
{
|
||||
UNUSED(hhcd);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief SOF callback.
|
||||
* @param hhcd HCD handle
|
||||
|
@ -714,7 +726,9 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t
|
|||
* @param pCallback pointer to the Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
|
||||
HAL_HCD_CallbackIDTypeDef CallbackID,
|
||||
pHCD_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -802,7 +816,7 @@ HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_Call
|
|||
|
||||
/**
|
||||
* @brief Unregister an USB HCD Callback
|
||||
* USB HCD callabck is redirected to the weak predefined callback
|
||||
* USB HCD callback is redirected to the weak predefined callback
|
||||
* @param hhcd USB HCD handle
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
|
@ -906,7 +920,8 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_Ca
|
|||
* @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
|
||||
pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -941,7 +956,7 @@ HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister the USB HCD Host Channel Notify URB Change Callback
|
||||
* @brief Unregister the USB HCD Host Channel Notify URB Change Callback
|
||||
* USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
|
||||
* @param hhcd HCD handle
|
||||
* @retval HAL status
|
||||
|
@ -978,8 +993,8 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef
|
|||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief Management functions
|
||||
*
|
||||
* @brief Management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
|
@ -1037,8 +1052,8 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
|
|||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
|
@ -1166,6 +1181,13 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR)
|
||||
{
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR);
|
||||
hhcd->hc[ch_num].state = HC_BBLERR;
|
||||
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
|
||||
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
|
||||
}
|
||||
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
|
||||
{
|
||||
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
|
||||
|
@ -1224,6 +1246,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC)
|
||||
{
|
||||
hhcd->hc[ch_num].urb_state = URB_DONE;
|
||||
hhcd->hc[ch_num].toggle_in ^= 1U;
|
||||
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
|
||||
|
@ -1279,6 +1302,11 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
||||
USBx_HC(ch_num)->HCCHAR = tmpreg;
|
||||
}
|
||||
else if (hhcd->hc[ch_num].state == HC_BBLERR)
|
||||
{
|
||||
hhcd->hc[ch_num].ErrCnt++;
|
||||
hhcd->hc[ch_num].urb_state = URB_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* ... */
|
||||
|
|
|
@ -337,6 +337,7 @@
|
|||
*/
|
||||
#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */
|
||||
#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */
|
||||
#define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */
|
||||
#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
|
||||
|
||||
/* Private define for @ref PreviousState usage */
|
||||
|
@ -377,6 +378,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
|||
static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
|
||||
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
|
||||
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
|
||||
static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c);
|
||||
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Private functions for I2C transfer IRQ handler */
|
||||
|
@ -396,6 +398,8 @@ static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags);
|
|||
static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
|
||||
static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Private function to Convert Specific options */
|
||||
static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
|
@ -504,6 +508,10 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
|||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/*Reset I2C*/
|
||||
hi2c->Instance->CR1 |= I2C_CR1_SWRST;
|
||||
hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
|
||||
|
||||
/* Get PCLK1 frequency */
|
||||
pclk1 = HAL_RCC_GetPCLK1Freq();
|
||||
|
||||
|
@ -1162,6 +1170,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
{
|
||||
__IO uint32_t count = 0U;
|
||||
|
||||
/* Init tickstart for timeout management*/
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
|
@ -1344,10 +1354,27 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
|
|||
hi2c->XferCount--;
|
||||
|
||||
/* Wait until BTF flag is set */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
|
||||
count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
|
||||
do
|
||||
{
|
||||
return HAL_ERROR;
|
||||
count--;
|
||||
if (count == 0U)
|
||||
{
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
||||
|
||||
/* Re-enable IRQs */
|
||||
__enable_irq();
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET);
|
||||
|
||||
/* Generate Stop */
|
||||
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
|
||||
|
@ -2567,6 +2594,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
{
|
||||
__IO uint32_t count = 0U;
|
||||
|
||||
/* Init tickstart for timeout management*/
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
|
@ -2751,10 +2780,27 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
|
|||
hi2c->XferCount--;
|
||||
|
||||
/* Wait until BTF flag is set */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
|
||||
count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
|
||||
do
|
||||
{
|
||||
return HAL_ERROR;
|
||||
count--;
|
||||
if (count == 0U)
|
||||
{
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
||||
|
||||
/* Re-enable IRQs */
|
||||
__enable_irq();
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET);
|
||||
|
||||
/* Generate Stop */
|
||||
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
|
||||
|
@ -3100,6 +3146,27 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
|
|||
/* Send Slave Address and Memory Address */
|
||||
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
|
||||
{
|
||||
/* Abort the ongoing DMA */
|
||||
dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx);
|
||||
|
||||
/* Prevent unused argument(s) compilation and MISRA warning */
|
||||
UNUSED(dmaxferstatus);
|
||||
|
||||
/* Clear directly Complete callback as no XferAbortCallback is used to finalize Abort treatment */
|
||||
if (hi2c->hdmatx != NULL)
|
||||
{
|
||||
hi2c->hdmatx->XferCpltCallback = NULL;
|
||||
}
|
||||
|
||||
/* Disable Acknowledge */
|
||||
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
|
||||
|
||||
hi2c->XferSize = 0U;
|
||||
hi2c->XferCount = 0U;
|
||||
|
||||
/* Disable I2C peripheral to prevent dummy data in buffer */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
|
@ -3243,6 +3310,27 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
|
|||
/* Send Slave Address and Memory Address */
|
||||
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
|
||||
{
|
||||
/* Abort the ongoing DMA */
|
||||
dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx);
|
||||
|
||||
/* Prevent unused argument(s) compilation and MISRA warning */
|
||||
UNUSED(dmaxferstatus);
|
||||
|
||||
/* Clear directly Complete callback as no XferAbortCallback is used to finalize Abort treatment */
|
||||
if (hi2c->hdmarx != NULL)
|
||||
{
|
||||
hi2c->hdmarx->XferCpltCallback = NULL;
|
||||
}
|
||||
|
||||
/* Disable Acknowledge */
|
||||
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
|
||||
|
||||
hi2c->XferSize = 0U;
|
||||
hi2c->XferCount = 0U;
|
||||
|
||||
/* Disable I2C peripheral to prevent dummy data in buffer */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
|
@ -3367,7 +3455,11 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
|
|||
/* Wait until SB flag is set */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
|
||||
{
|
||||
hi2c->ErrorCode = HAL_I2C_WRONG_START;
|
||||
}
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
||||
/* Send slave address */
|
||||
|
@ -3469,7 +3561,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
|
|||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Check Busy Flag only if FIRST call of Master interface */
|
||||
if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
|
||||
if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
|
||||
{
|
||||
/* Wait until BUSY flag is reset */
|
||||
count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
|
||||
|
@ -3568,7 +3660,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
|||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Check Busy Flag only if FIRST call of Master interface */
|
||||
if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
|
||||
if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
|
||||
{
|
||||
/* Wait until BUSY flag is reset */
|
||||
count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
|
||||
|
@ -3734,7 +3826,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_
|
|||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Check Busy Flag only if FIRST call of Master interface */
|
||||
if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
|
||||
if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
|
||||
{
|
||||
/* Wait until BUSY flag is reset */
|
||||
count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
|
||||
|
@ -3859,7 +3951,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
|
|||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Check Busy Flag only if FIRST call of Master interface */
|
||||
if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
|
||||
if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
|
||||
{
|
||||
/* Wait until BUSY flag is reset */
|
||||
count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
|
||||
|
@ -4561,11 +4653,14 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
|
||||
{
|
||||
/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
|
||||
HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
|
||||
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(DevAddress);
|
||||
|
||||
/* Abort Master transfer during Receive or Transmit process */
|
||||
if (hi2c->Mode == HAL_I2C_MODE_MASTER)
|
||||
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER))
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
@ -4596,6 +4691,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
|
|||
{
|
||||
/* Wrong usage of abort function */
|
||||
/* This function should be used only in case of abort monitored by master device */
|
||||
/* Or periphal is not in busy state, mean there is no active sequence to be abort */
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
@ -4667,7 +4763,14 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
|
|||
/* BTF set -------------------------------------------------------------*/
|
||||
else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
|
||||
{
|
||||
I2C_MasterTransmit_BTF(hi2c);
|
||||
if (CurrentMode == HAL_I2C_MODE_MASTER)
|
||||
{
|
||||
I2C_MasterTransmit_BTF(hi2c);
|
||||
}
|
||||
else /* HAL_I2C_MODE_MEM */
|
||||
{
|
||||
I2C_MemoryTransmit_TXE_BTF(hi2c);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -4782,6 +4885,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
|
|||
uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
|
||||
uint32_t itsources = READ_REG(hi2c->Instance->CR2);
|
||||
uint32_t error = HAL_I2C_ERROR_NONE;
|
||||
HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
|
||||
|
||||
/* I2C Bus error interrupt occurred ----------------------------------------*/
|
||||
if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
|
||||
|
@ -4807,7 +4911,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
|
|||
/* I2C Acknowledge failure error interrupt occurred ------------------------*/
|
||||
if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
|
||||
{
|
||||
tmp1 = hi2c->Mode;
|
||||
tmp1 = CurrentMode;
|
||||
tmp2 = hi2c->XferCount;
|
||||
tmp3 = hi2c->State;
|
||||
tmp4 = hi2c->PreviousState;
|
||||
|
@ -4825,7 +4929,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
|
|||
error |= HAL_I2C_ERROR_AF;
|
||||
|
||||
/* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
|
||||
if (hi2c->Mode == HAL_I2C_MODE_MASTER)
|
||||
if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
|
||||
{
|
||||
/* Generate Stop */
|
||||
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
|
||||
|
@ -5150,59 +5254,7 @@ static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
|
|||
{
|
||||
if (hi2c->Mode == HAL_I2C_MODE_MEM)
|
||||
{
|
||||
if (hi2c->EventCount == 0U)
|
||||
{
|
||||
/* If Memory address size is 8Bit */
|
||||
if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
|
||||
{
|
||||
/* Send Memory Address */
|
||||
hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
|
||||
|
||||
hi2c->EventCount += 2U;
|
||||
}
|
||||
/* If Memory address size is 16Bit */
|
||||
else
|
||||
{
|
||||
/* Send MSB of Memory Address */
|
||||
hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
|
||||
|
||||
hi2c->EventCount++;
|
||||
}
|
||||
}
|
||||
else if (hi2c->EventCount == 1U)
|
||||
{
|
||||
/* Send LSB of Memory Address */
|
||||
hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
|
||||
|
||||
hi2c->EventCount++;
|
||||
}
|
||||
else if (hi2c->EventCount == 2U)
|
||||
{
|
||||
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
||||
{
|
||||
/* Generate Restart */
|
||||
hi2c->Instance->CR1 |= I2C_CR1_START;
|
||||
}
|
||||
else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
|
||||
{
|
||||
/* Write data to DR */
|
||||
hi2c->Instance->DR = *hi2c->pBuffPtr;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
/* Update counter */
|
||||
hi2c->XferCount--;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
I2C_MemoryTransmit_TXE_BTF(hi2c);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -5274,29 +5326,104 @@ static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
|
|||
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
if (hi2c->Mode == HAL_I2C_MODE_MEM)
|
||||
{
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
hi2c->MemTxCpltCallback(hi2c);
|
||||
#else
|
||||
HAL_I2C_MemTxCpltCallback(hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
hi2c->MasterTxCpltCallback(hi2c);
|
||||
hi2c->MasterTxCpltCallback(hi2c);
|
||||
#else
|
||||
HAL_I2C_MasterTxCpltCallback(hi2c);
|
||||
HAL_I2C_MasterTxCpltCallback(hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle TXE and BTF flag for Memory transmitter
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for I2C module
|
||||
* @retval None
|
||||
*/
|
||||
static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
|
||||
HAL_I2C_StateTypeDef CurrentState = hi2c->State;
|
||||
|
||||
if (hi2c->EventCount == 0U)
|
||||
{
|
||||
/* If Memory address size is 8Bit */
|
||||
if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
|
||||
{
|
||||
/* Send Memory Address */
|
||||
hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
|
||||
|
||||
hi2c->EventCount += 2U;
|
||||
}
|
||||
/* If Memory address size is 16Bit */
|
||||
else
|
||||
{
|
||||
/* Send MSB of Memory Address */
|
||||
hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
|
||||
|
||||
hi2c->EventCount++;
|
||||
}
|
||||
}
|
||||
else if (hi2c->EventCount == 1U)
|
||||
{
|
||||
/* Send LSB of Memory Address */
|
||||
hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
|
||||
|
||||
hi2c->EventCount++;
|
||||
}
|
||||
else if (hi2c->EventCount == 2U)
|
||||
{
|
||||
if (CurrentState == HAL_I2C_STATE_BUSY_RX)
|
||||
{
|
||||
/* Generate Restart */
|
||||
hi2c->Instance->CR1 |= I2C_CR1_START;
|
||||
}
|
||||
else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
|
||||
{
|
||||
/* Write data to DR */
|
||||
hi2c->Instance->DR = *hi2c->pBuffPtr;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
/* Update counter */
|
||||
hi2c->XferCount--;
|
||||
}
|
||||
else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
|
||||
{
|
||||
/* Generate Stop condition then Call TxCpltCallback() */
|
||||
/* Disable EVT, BUF and ERR interrupt */
|
||||
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
|
||||
|
||||
/* Generate Stop */
|
||||
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
|
||||
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
hi2c->MemTxCpltCallback(hi2c);
|
||||
#else
|
||||
HAL_I2C_MemTxCpltCallback(hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -5333,43 +5460,70 @@ static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
|
|||
}
|
||||
else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U)))
|
||||
{
|
||||
/* Disable Acknowledge */
|
||||
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
|
||||
|
||||
/* Disable EVT, BUF and ERR interrupt */
|
||||
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
|
||||
|
||||
/* Read data from DR */
|
||||
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
/* Update counter */
|
||||
hi2c->XferCount--;
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
if (hi2c->Mode == HAL_I2C_MODE_MEM)
|
||||
if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK)
|
||||
{
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
/* Disable Acknowledge */
|
||||
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
|
||||
|
||||
/* Disable EVT, BUF and ERR interrupt */
|
||||
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
|
||||
|
||||
/* Read data from DR */
|
||||
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
/* Update counter */
|
||||
hi2c->XferCount--;
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
if (hi2c->Mode == HAL_I2C_MODE_MEM)
|
||||
{
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
hi2c->MemRxCpltCallback(hi2c);
|
||||
hi2c->MemRxCpltCallback(hi2c);
|
||||
#else
|
||||
HAL_I2C_MemRxCpltCallback(hi2c);
|
||||
HAL_I2C_MemRxCpltCallback(hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
hi2c->MasterRxCpltCallback(hi2c);
|
||||
#else
|
||||
HAL_I2C_MasterRxCpltCallback(hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
|
||||
/* Disable EVT, BUF and ERR interrupt */
|
||||
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
|
||||
|
||||
/* Read data from DR */
|
||||
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
/* Update counter */
|
||||
hi2c->XferCount--;
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
|
||||
/* Call user error callback */
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
hi2c->MasterRxCpltCallback(hi2c);
|
||||
hi2c->ErrorCallback(hi2c);
|
||||
#else
|
||||
HAL_I2C_MasterRxCpltCallback(hi2c);
|
||||
HAL_I2C_ErrorCallback(hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
|
@ -5540,13 +5694,11 @@ static void I2C_Master_SB(I2C_HandleTypeDef *hi2c)
|
|||
hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
|
||||
}
|
||||
|
||||
if ((hi2c->hdmatx != NULL) || (hi2c->hdmarx != NULL))
|
||||
if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
|
||||
|| ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
|
||||
{
|
||||
if ((hi2c->hdmatx->XferCpltCallback != NULL) || (hi2c->hdmarx->XferCpltCallback != NULL))
|
||||
{
|
||||
/* Enable DMA Request */
|
||||
SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
|
||||
}
|
||||
/* Enable DMA Request */
|
||||
SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
|
||||
}
|
||||
}
|
||||
else
|
||||
|
@ -6159,8 +6311,10 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c)
|
|||
{
|
||||
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
|
||||
HAL_I2C_StateTypeDef CurrentState = hi2c->State;
|
||||
HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
|
||||
uint32_t CurrentError;
|
||||
|
||||
if ((hi2c->Mode == HAL_I2C_MODE_MASTER) && (CurrentState == HAL_I2C_STATE_BUSY_RX))
|
||||
if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX))
|
||||
{
|
||||
/* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
|
||||
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
|
||||
|
@ -6179,9 +6333,9 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c)
|
|||
if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT))
|
||||
{
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
}
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
}
|
||||
|
||||
/* Abort DMA transfer */
|
||||
|
@ -6278,15 +6432,24 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c)
|
|||
HAL_I2C_ErrorCallback(hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
}
|
||||
/* STOP Flag is not set after a NACK reception */
|
||||
|
||||
/* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */
|
||||
CurrentError = hi2c->ErrorCode;
|
||||
|
||||
if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \
|
||||
((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \
|
||||
((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \
|
||||
((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR))
|
||||
{
|
||||
/* Disable EVT, BUF and ERR interrupt */
|
||||
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
|
||||
}
|
||||
|
||||
/* So may inform upper layer that listen phase is stopped */
|
||||
/* during NACK error treatment */
|
||||
CurrentState = hi2c->State;
|
||||
if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN))
|
||||
{
|
||||
/* Disable EVT, BUF and ERR interrupt */
|
||||
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
|
||||
|
||||
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
@ -6334,7 +6497,11 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
|
|||
/* Wait until SB flag is set */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
|
||||
{
|
||||
hi2c->ErrorCode = HAL_I2C_WRONG_START;
|
||||
}
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
||||
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
|
||||
|
@ -6403,7 +6570,11 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
|
|||
/* Wait until SB flag is set */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
|
||||
{
|
||||
hi2c->ErrorCode = HAL_I2C_WRONG_START;
|
||||
}
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
||||
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
|
||||
|
@ -6440,7 +6611,11 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
|
|||
/* Wait until SB flag is set */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
|
||||
{
|
||||
hi2c->ErrorCode = HAL_I2C_WRONG_START;
|
||||
}
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
||||
/* Send header of slave address */
|
||||
|
@ -6476,7 +6651,11 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
|
|||
/* Wait until SB flag is set */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
|
||||
{
|
||||
hi2c->ErrorCode = HAL_I2C_WRONG_START;
|
||||
}
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
||||
/* Send slave address */
|
||||
|
@ -6555,7 +6734,11 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
|
|||
/* Wait until SB flag is set */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
|
||||
{
|
||||
hi2c->ErrorCode = HAL_I2C_WRONG_START;
|
||||
}
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
||||
/* Send slave address */
|
||||
|
@ -6625,7 +6808,11 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
|
|||
/* Wait until SB flag is set */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
|
||||
{
|
||||
hi2c->ErrorCode = HAL_I2C_WRONG_START;
|
||||
}
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
||||
/* Send slave address */
|
||||
|
@ -6658,8 +6845,14 @@ static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
|
|||
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
|
||||
|
||||
/* Clear Complete callback */
|
||||
hi2c->hdmatx->XferCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferCpltCallback = NULL;
|
||||
if (hi2c->hdmatx != NULL)
|
||||
{
|
||||
hi2c->hdmatx->XferCpltCallback = NULL;
|
||||
}
|
||||
if (hi2c->hdmarx != NULL)
|
||||
{
|
||||
hi2c->hdmarx->XferCpltCallback = NULL;
|
||||
}
|
||||
|
||||
if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
|
||||
{
|
||||
|
@ -6782,8 +6975,14 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
|
|||
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
|
||||
|
||||
/* Clear Complete callback */
|
||||
hi2c->hdmatx->XferCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferCpltCallback = NULL;
|
||||
if (hi2c->hdmatx != NULL)
|
||||
{
|
||||
hi2c->hdmatx->XferCpltCallback = NULL;
|
||||
}
|
||||
if (hi2c->hdmarx != NULL)
|
||||
{
|
||||
hi2c->hdmarx->XferCpltCallback = NULL;
|
||||
}
|
||||
|
||||
/* Disable Acknowledge */
|
||||
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
|
||||
|
@ -6808,14 +7007,35 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
|
|||
*/
|
||||
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
__IO uint32_t count = 0U;
|
||||
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
|
||||
|
||||
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
|
||||
HAL_I2C_StateTypeDef CurrentState = hi2c->State;
|
||||
|
||||
/* During abort treatment, check that there is no pending STOP request */
|
||||
/* Wait until STOP flag is reset */
|
||||
count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
|
||||
do
|
||||
{
|
||||
if (count == 0U)
|
||||
{
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
||||
break;
|
||||
}
|
||||
count--;
|
||||
}
|
||||
while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
|
||||
|
||||
/* Clear Complete callback */
|
||||
hi2c->hdmatx->XferCpltCallback = NULL;
|
||||
hi2c->hdmarx->XferCpltCallback = NULL;
|
||||
if (hi2c->hdmatx != NULL)
|
||||
{
|
||||
hi2c->hdmatx->XferCpltCallback = NULL;
|
||||
}
|
||||
if (hi2c->hdmarx != NULL)
|
||||
{
|
||||
hi2c->hdmarx->XferCpltCallback = NULL;
|
||||
}
|
||||
|
||||
/* Disable Acknowledge */
|
||||
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
|
||||
|
@ -6823,8 +7043,14 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
|
|||
hi2c->XferCount = 0U;
|
||||
|
||||
/* Reset XferAbortCallback */
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
hi2c->hdmarx->XferAbortCallback = NULL;
|
||||
if (hi2c->hdmatx != NULL)
|
||||
{
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
}
|
||||
if (hi2c->hdmarx != NULL)
|
||||
{
|
||||
hi2c->hdmarx->XferAbortCallback = NULL;
|
||||
}
|
||||
|
||||
/* Disable I2C peripheral to prevent dummy data in buffer */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
@ -7070,6 +7296,33 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
__IO uint32_t count = 0U;
|
||||
|
||||
/* Wait until STOP flag is reset */
|
||||
count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U);
|
||||
do
|
||||
{
|
||||
count--;
|
||||
if (count == 0U)
|
||||
{
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
|
|
|
@ -90,6 +90,10 @@
|
|||
(+) Pause the DMA Transfer using HAL_I2S_DMAPause()
|
||||
(+) Resume the DMA Transfer using HAL_I2S_DMAResume()
|
||||
(+) Stop the DMA Transfer using HAL_I2S_DMAStop()
|
||||
In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error
|
||||
HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
|
||||
In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data
|
||||
inside DR register and avoid using DeInit/Init process for the next transfer.
|
||||
|
||||
*** I2S HAL driver macros list ***
|
||||
===================================
|
||||
|
@ -101,6 +105,7 @@
|
|||
(+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
|
||||
(+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
|
||||
(+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
|
||||
(+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data
|
||||
|
||||
[..]
|
||||
(@) You can refer to the I2S HAL driver header file for more useful macros
|
||||
|
@ -201,6 +206,7 @@
|
|||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define I2S_TIMEOUT_FLAG 100U /*!< Timeout 100 ms */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
@ -338,7 +344,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
|
|||
/* I2S standard */
|
||||
if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
|
||||
{
|
||||
/* In I2S standard packet lenght is multiplied by 2 */
|
||||
/* In I2S standard packet length is multiplied by 2 */
|
||||
packetlength = packetlength * 2U;
|
||||
}
|
||||
|
||||
|
@ -1369,35 +1375,86 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
|
|||
and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
|
||||
*/
|
||||
|
||||
/* Disable the I2S Tx/Rx DMA requests */
|
||||
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
|
||||
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
|
||||
|
||||
/* Abort the I2S DMA tx Stream/Channel */
|
||||
if (hi2s->hdmatx != NULL)
|
||||
if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
|
||||
{
|
||||
/* Disable the I2S DMA tx Stream/Channel */
|
||||
if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
|
||||
/* Abort the I2S DMA tx Stream/Channel */
|
||||
if (hi2s->hdmatx != NULL)
|
||||
{
|
||||
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
|
||||
errorcode = HAL_ERROR;
|
||||
/* Disable the I2S DMA tx Stream/Channel */
|
||||
if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
|
||||
{
|
||||
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
|
||||
errorcode = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Wait until TXE flag is set */
|
||||
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK)
|
||||
{
|
||||
/* Set the error code */
|
||||
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
|
||||
hi2s->State = HAL_I2S_STATE_READY;
|
||||
errorcode = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Wait until BSY flag is Reset */
|
||||
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK)
|
||||
{
|
||||
/* Set the error code */
|
||||
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
|
||||
hi2s->State = HAL_I2S_STATE_READY;
|
||||
errorcode = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Disable I2S peripheral */
|
||||
__HAL_I2S_DISABLE(hi2s);
|
||||
|
||||
/* Clear UDR flag */
|
||||
__HAL_I2S_CLEAR_UDRFLAG(hi2s);
|
||||
|
||||
/* Disable the I2S Tx DMA requests */
|
||||
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
|
||||
|
||||
}
|
||||
|
||||
/* Abort the I2S DMA rx Stream/Channel */
|
||||
if (hi2s->hdmarx != NULL)
|
||||
else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
|
||||
{
|
||||
/* Disable the I2S DMA rx Stream/Channel */
|
||||
if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
|
||||
/* Abort the I2S DMA rx Stream/Channel */
|
||||
if (hi2s->hdmarx != NULL)
|
||||
{
|
||||
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
|
||||
/* Disable the I2S DMA rx Stream/Channel */
|
||||
if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
|
||||
{
|
||||
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
|
||||
errorcode = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable I2S peripheral */
|
||||
__HAL_I2S_DISABLE(hi2s);
|
||||
|
||||
/* Clear OVR flag */
|
||||
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
|
||||
|
||||
/* Disable the I2S Rx DMA request */
|
||||
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
|
||||
|
||||
if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
|
||||
{
|
||||
/* Set the error code */
|
||||
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
|
||||
|
||||
/* Set the I2S State ready */
|
||||
hi2s->State = HAL_I2S_STATE_READY;
|
||||
errorcode = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Read DR to Flush RX Data */
|
||||
READ_REG((hi2s->Instance)->DR);
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable I2S peripheral */
|
||||
__HAL_I2S_DISABLE(hi2s);
|
||||
|
||||
hi2s->State = HAL_I2S_STATE_READY;
|
||||
|
||||
return errorcode;
|
||||
|
|
|
@ -16,45 +16,56 @@
|
|||
(+) The IWDG can be started by either software or hardware (configurable
|
||||
through option byte).
|
||||
|
||||
(+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
|
||||
if the main clock fails.
|
||||
(+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
|
||||
active even if the main clock fails.
|
||||
|
||||
(+) Once the IWDG is started, the LSI is forced ON and both can not be
|
||||
(+) Once the IWDG is started, the LSI is forced ON and both cannot be
|
||||
disabled. The counter starts counting down from the reset value (0xFFF).
|
||||
When it reaches the end of count value (0x000) a reset signal is
|
||||
generated (IWDG reset).
|
||||
|
||||
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
|
||||
the IWDG_RLR value is reloaded in the counter and the watchdog reset is
|
||||
prevented.
|
||||
the IWDG_RLR value is reloaded into the counter and the watchdog reset
|
||||
is prevented.
|
||||
|
||||
(+) The IWDG is implemented in the VDD voltage domain that is still functional
|
||||
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
|
||||
in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
|
||||
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
|
||||
reset occurs.
|
||||
|
||||
(+) Debug mode : When the microcontroller enters debug mode (core halted),
|
||||
(+) Debug mode: When the microcontroller enters debug mode (core halted),
|
||||
the IWDG counter either continues to work normally or stops, depending
|
||||
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
|
||||
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
|
||||
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
|
||||
|
||||
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
|
||||
The IWDG timeout may vary due to LSI frequency dispersion. STM32F1xx
|
||||
devices provide the capability to measure the LSI frequency (LSI clock
|
||||
connected internally to TIM5 CH4 input capture). The measured value
|
||||
can be used to have an IWDG timeout with an acceptable accuracy.
|
||||
The IWDG timeout may vary due to LSI clock frequency dispersion.
|
||||
STM32F1xx devices provide the capability to measure the LSI clock
|
||||
frequency (LSI clock is internally connected to TIM5 CH4 input capture).
|
||||
The measured value can be used to have an IWDG timeout with an
|
||||
acceptable accuracy.
|
||||
|
||||
[..] Default timeout value (necessary for IWDG_SR status register update):
|
||||
Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
|
||||
This frequency being subject to variations as mentioned above, the
|
||||
default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
|
||||
below) may become too short or too long.
|
||||
In such cases, this default timeout value can be tuned by redefining
|
||||
the constant LSI_VALUE at user-application level (based, for instance,
|
||||
on the measured LSI clock frequency as explained above).
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Use IWDG using HAL_IWDG_Init() function to :
|
||||
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
|
||||
clock is forced ON and IWDG counter starts downcounting.
|
||||
(++) Enable write access to configuration register: IWDG_PR & IWDG_RLR.
|
||||
clock is forced ON and IWDG counter starts counting down.
|
||||
(++) Enable write access to configuration registers:
|
||||
IWDG_PR and IWDG_RLR.
|
||||
(++) Configure the IWDG prescaler and counter reload value. This reload
|
||||
value will be loaded in the IWDG counter each time the watchdog is
|
||||
reloaded, then the IWDG will start counting down from this value.
|
||||
(++) wait for status flags to be reset"
|
||||
(++) Wait for status flags to be reset.
|
||||
|
||||
(#) Then the application program must refresh the IWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
|
@ -91,7 +102,7 @@
|
|||
*/
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
/** @defgroup IWDG IWDG
|
||||
/** @addtogroup IWDG
|
||||
* @brief IWDG HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
@ -101,10 +112,14 @@
|
|||
/** @defgroup IWDG_Private_Defines IWDG Private Defines
|
||||
* @{
|
||||
*/
|
||||
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
|
||||
higher prescaler (256), and according to HSI variation, we need to wait at
|
||||
least 6 cycles so 48 ms. */
|
||||
#define HAL_IWDG_DEFAULT_TIMEOUT 48U
|
||||
/* Status register needs up to 5 LSI clock periods divided by the clock
|
||||
prescaler to be updated. The number of LSI clock periods is upper-rounded to
|
||||
6 for the timeout value calculation.
|
||||
The timeout value is also calculated using the highest prescaler (256) and
|
||||
the LSI_VALUE constant. The value of this constant can be changed by the user
|
||||
to take into account possible LSI clock period variations.
|
||||
The timeout value is multiplied by 1000 to be converted in milliseconds. */
|
||||
#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -158,10 +173,11 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
|||
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
|
||||
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
|
||||
|
||||
/* Enable IWDG. LSI is turned on automaticaly */
|
||||
/* Enable IWDG. LSI is turned on automatically */
|
||||
__HAL_IWDG_START(hiwdg);
|
||||
|
||||
/* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */
|
||||
/* Enable write access to IWDG_PR and IWDG_RLR registers by writing
|
||||
0x5555 in KR */
|
||||
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
|
||||
|
||||
/* Write to IWDG registers the Prescaler & Reload values to work with */
|
||||
|
@ -172,7 +188,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
|||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for register to be updated */
|
||||
while (hiwdg->Instance->SR != RESET)
|
||||
while (hiwdg->Instance->SR != 0x00u)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
|
||||
{
|
||||
|
@ -191,6 +207,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
|||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions_Group2
|
||||
* @brief IO operation functions
|
||||
*
|
||||
|
@ -205,6 +222,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
|||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Refresh the IWDG.
|
||||
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -151,9 +151,35 @@
|
|||
#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
|
||||
#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
|
||||
|
||||
#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF
|
||||
#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040
|
||||
#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8
|
||||
#define NOR_CMD_CONFIRM (uint16_t)0x00D0
|
||||
#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020
|
||||
#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060
|
||||
#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070
|
||||
#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050
|
||||
|
||||
/* Mask on NOR STATUS REGISTER */
|
||||
#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010
|
||||
#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
|
||||
#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
|
||||
#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080
|
||||
|
||||
/* Address of the primary command set */
|
||||
#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013
|
||||
|
||||
/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */
|
||||
#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */
|
||||
#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */
|
||||
#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */
|
||||
#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */
|
||||
#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */
|
||||
#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */
|
||||
#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */
|
||||
#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */
|
||||
#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */
|
||||
#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -200,8 +226,11 @@ static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
|
|||
* @param ExtTiming pointer to NOR extended mode timing structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
|
||||
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing,
|
||||
FSMC_NORSRAM_TimingTypeDef *ExtTiming)
|
||||
{
|
||||
uint32_t deviceaddress;
|
||||
|
||||
/* Check the NOR handle parameter */
|
||||
if (hnor == NULL)
|
||||
{
|
||||
|
@ -214,7 +243,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeD
|
|||
hnor->Lock = HAL_UNLOCKED;
|
||||
|
||||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
|
||||
if(hnor->MspInitCallback == NULL)
|
||||
if (hnor->MspInitCallback == NULL)
|
||||
{
|
||||
hnor->MspInitCallback = HAL_NOR_MspInit;
|
||||
}
|
||||
|
@ -252,7 +281,29 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeD
|
|||
/* Initialize the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
/* Select the NOR device address */
|
||||
if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
|
||||
{
|
||||
deviceaddress = NOR_MEMORY_ADRESS1;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
|
||||
{
|
||||
deviceaddress = NOR_MEMORY_ADRESS2;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
|
||||
{
|
||||
deviceaddress = NOR_MEMORY_ADRESS3;
|
||||
}
|
||||
else /* FSMC_NORSRAM_BANK4 */
|
||||
{
|
||||
deviceaddress = NOR_MEMORY_ADRESS4;
|
||||
}
|
||||
|
||||
/* Get the value of the command set */
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
|
||||
hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
|
||||
|
||||
return HAL_NOR_ReturnToReadMode(hnor);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -264,7 +315,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeD
|
|||
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
|
||||
{
|
||||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
|
||||
if(hnor->MspDeInitCallback == NULL)
|
||||
if (hnor->MspDeInitCallback == NULL)
|
||||
{
|
||||
hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
|
||||
}
|
||||
|
@ -367,6 +418,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
|
|||
{
|
||||
uint32_t deviceaddress;
|
||||
HAL_NOR_StateTypeDef state;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the NOR controller state */
|
||||
state = hnor->State;
|
||||
|
@ -401,15 +453,30 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
|
|||
}
|
||||
|
||||
/* Send read ID command */
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
|
||||
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
||||
{
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
|
||||
}
|
||||
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
|
||||
{
|
||||
NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Primary command set not supported by the driver */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Read the NOR IDs */
|
||||
pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
|
||||
pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
|
||||
pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
|
||||
pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
|
||||
if (status != HAL_ERROR)
|
||||
{
|
||||
/* Read the NOR IDs */
|
||||
pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
|
||||
pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
|
||||
pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
|
||||
pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
|
||||
}
|
||||
|
||||
/* Check the NOR controller state */
|
||||
hnor->State = state;
|
||||
|
@ -422,7 +489,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
|
|||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -435,6 +502,7 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
|
|||
{
|
||||
uint32_t deviceaddress;
|
||||
HAL_NOR_StateTypeDef state;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the NOR controller state */
|
||||
state = hnor->State;
|
||||
|
@ -468,7 +536,19 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
|
|||
deviceaddress = NOR_MEMORY_ADRESS4;
|
||||
}
|
||||
|
||||
NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
|
||||
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
||||
{
|
||||
NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
|
||||
}
|
||||
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
|
||||
{
|
||||
NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Primary command set not supported by the driver */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the NOR controller state */
|
||||
hnor->State = state;
|
||||
|
@ -481,7 +561,7 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
|
|||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -496,6 +576,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
|
|||
{
|
||||
uint32_t deviceaddress;
|
||||
HAL_NOR_StateTypeDef state;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the NOR controller state */
|
||||
state = hnor->State;
|
||||
|
@ -530,12 +611,27 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
|
|||
}
|
||||
|
||||
/* Send read data command */
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
|
||||
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
||||
{
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
|
||||
}
|
||||
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
|
||||
{
|
||||
NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Primary command set not supported by the driver */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Read the data */
|
||||
*pData = (uint16_t)(*(__IO uint32_t *)pAddress);
|
||||
if (status != HAL_ERROR)
|
||||
{
|
||||
/* Read the data */
|
||||
*pData = (uint16_t)(*(__IO uint32_t *)pAddress);
|
||||
}
|
||||
|
||||
/* Check the NOR controller state */
|
||||
hnor->State = state;
|
||||
|
@ -548,7 +644,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
|
|||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -562,6 +658,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
|
|||
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
|
||||
{
|
||||
uint32_t deviceaddress;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the NOR controller state */
|
||||
if (hnor->State == HAL_NOR_STATE_BUSY)
|
||||
|
@ -595,12 +692,27 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
|
|||
}
|
||||
|
||||
/* Send program data command */
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
|
||||
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
||||
{
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
|
||||
}
|
||||
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
|
||||
{
|
||||
NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Primary command set not supported by the driver */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write the data */
|
||||
NOR_WRITE(pAddress, *pData);
|
||||
if (status != HAL_ERROR)
|
||||
{
|
||||
/* Write the data */
|
||||
NOR_WRITE(pAddress, *pData);
|
||||
}
|
||||
|
||||
/* Check the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_READY;
|
||||
|
@ -613,7 +725,7 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
|
|||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -625,11 +737,15 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
|
|||
* @param uwBufferSize number of Half word to read.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
|
||||
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
|
||||
uint32_t uwBufferSize)
|
||||
{
|
||||
uint32_t deviceaddress, size = uwBufferSize, address = uwAddress;
|
||||
uint32_t deviceaddress;
|
||||
uint32_t size = uwBufferSize;
|
||||
uint32_t address = uwAddress;
|
||||
uint16_t *data = pData;
|
||||
HAL_NOR_StateTypeDef state;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the NOR controller state */
|
||||
state = hnor->State;
|
||||
|
@ -664,17 +780,32 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
|
|||
}
|
||||
|
||||
/* Send read data command */
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
|
||||
|
||||
/* Read buffer */
|
||||
while (size > 0U)
|
||||
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
||||
{
|
||||
*data = *(__IO uint16_t *)address;
|
||||
data++;
|
||||
address += 2U;
|
||||
size--;
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
|
||||
}
|
||||
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
|
||||
{
|
||||
NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Primary command set not supported by the driver */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
if (status != HAL_ERROR)
|
||||
{
|
||||
/* Read buffer */
|
||||
while (size > 0U)
|
||||
{
|
||||
*data = *(__IO uint16_t *)address;
|
||||
data++;
|
||||
address += 2U;
|
||||
size--;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check the NOR controller state */
|
||||
|
@ -688,7 +819,7 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
|
|||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -700,12 +831,14 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
|
|||
* @param uwBufferSize Size of the buffer to write
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
|
||||
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
|
||||
uint32_t uwBufferSize)
|
||||
{
|
||||
uint16_t *p_currentaddress;
|
||||
const uint16_t *p_endaddress;
|
||||
uint16_t *data = pData;
|
||||
uint32_t lastloadedaddress, deviceaddress;
|
||||
uint32_t deviceaddress;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the NOR controller state */
|
||||
if (hnor->State == HAL_NOR_STATE_BUSY)
|
||||
|
@ -739,31 +872,51 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
|
|||
}
|
||||
|
||||
/* Initialize variables */
|
||||
p_currentaddress = (uint16_t *)(uwAddress);
|
||||
p_endaddress = (const uint16_t *)(uwAddress + (uwBufferSize - 1U));
|
||||
lastloadedaddress = uwAddress;
|
||||
p_currentaddress = (uint16_t *)(deviceaddress + uwAddress);
|
||||
p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U)));
|
||||
|
||||
/* Issue unlock command sequence */
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
||||
|
||||
/* Write Buffer Load Command */
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uint16_t)(uwBufferSize - 1U));
|
||||
|
||||
/* Load Data into NOR Buffer */
|
||||
while (p_currentaddress <= p_endaddress)
|
||||
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
||||
{
|
||||
/* Store last loaded address & data value (for polling) */
|
||||
lastloadedaddress = (uint32_t)p_currentaddress;
|
||||
/* Issue unlock command sequence */
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
||||
|
||||
NOR_WRITE(p_currentaddress, *data);
|
||||
|
||||
data++;
|
||||
p_currentaddress ++;
|
||||
/* Write Buffer Load Command */
|
||||
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
|
||||
NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
|
||||
}
|
||||
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
|
||||
{
|
||||
/* Write Buffer Load Command */
|
||||
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM);
|
||||
NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Primary command set not supported by the driver */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
|
||||
if (status != HAL_ERROR)
|
||||
{
|
||||
/* Load Data into NOR Buffer */
|
||||
while (p_currentaddress <= p_endaddress)
|
||||
{
|
||||
NOR_WRITE(p_currentaddress, *data);
|
||||
|
||||
data++;
|
||||
p_currentaddress ++;
|
||||
}
|
||||
|
||||
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
||||
{
|
||||
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
|
||||
}
|
||||
else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */
|
||||
{
|
||||
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM);
|
||||
}
|
||||
}
|
||||
|
||||
/* Check the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_READY;
|
||||
|
@ -776,7 +929,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
|
|||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
return status;
|
||||
|
||||
}
|
||||
|
||||
|
@ -791,6 +944,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
|
|||
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
|
||||
{
|
||||
uint32_t deviceaddress;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the NOR controller state */
|
||||
if (hnor->State == HAL_NOR_STATE_BUSY)
|
||||
|
@ -824,12 +978,30 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
|
|||
}
|
||||
|
||||
/* Send block erase command sequence */
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
|
||||
NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
|
||||
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
||||
{
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
|
||||
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
|
||||
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
|
||||
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
|
||||
NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
|
||||
}
|
||||
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
|
||||
{
|
||||
NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK);
|
||||
NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
|
||||
NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE);
|
||||
NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Primary command set not supported by the driver */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the NOR memory status and update the controller state */
|
||||
hnor->State = HAL_NOR_STATE_READY;
|
||||
|
@ -842,7 +1014,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
|
|||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
return status;
|
||||
|
||||
}
|
||||
|
||||
|
@ -856,6 +1028,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
|
|||
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
|
||||
{
|
||||
uint32_t deviceaddress;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
UNUSED(Address);
|
||||
|
||||
/* Check the NOR controller state */
|
||||
|
@ -890,12 +1063,23 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
|
|||
}
|
||||
|
||||
/* Send NOR chip erase command sequence */
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
|
||||
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
||||
{
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
|
||||
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
|
||||
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
|
||||
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
|
||||
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Primary command set not supported by the driver */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the NOR memory status and update the controller state */
|
||||
hnor->State = HAL_NOR_STATE_READY;
|
||||
|
@ -908,7 +1092,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
|
|||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -990,12 +1174,13 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
|
|||
* @param pCallback : pointer to the Callback function
|
||||
* @retval status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
|
||||
pNOR_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
HAL_NOR_StateTypeDef state;
|
||||
|
||||
if(pCallback == NULL)
|
||||
if (pCallback == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
@ -1004,20 +1189,20 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_Cal
|
|||
__HAL_LOCK(hnor);
|
||||
|
||||
state = hnor->State;
|
||||
if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
|
||||
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
|
||||
{
|
||||
switch (CallbackId)
|
||||
{
|
||||
case HAL_NOR_MSP_INIT_CB_ID :
|
||||
hnor->MspInitCallback = pCallback;
|
||||
break;
|
||||
case HAL_NOR_MSP_DEINIT_CB_ID :
|
||||
hnor->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
case HAL_NOR_MSP_INIT_CB_ID :
|
||||
hnor->MspInitCallback = pCallback;
|
||||
break;
|
||||
case HAL_NOR_MSP_DEINIT_CB_ID :
|
||||
hnor->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
|
@ -1041,7 +1226,7 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_Cal
|
|||
* @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
|
||||
* @retval status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
|
||||
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
HAL_NOR_StateTypeDef state;
|
||||
|
@ -1050,20 +1235,20 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C
|
|||
__HAL_LOCK(hnor);
|
||||
|
||||
state = hnor->State;
|
||||
if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
|
||||
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
|
||||
{
|
||||
switch (CallbackId)
|
||||
{
|
||||
case HAL_NOR_MSP_INIT_CB_ID :
|
||||
hnor->MspInitCallback = HAL_NOR_MspInit;
|
||||
break;
|
||||
case HAL_NOR_MSP_DEINIT_CB_ID :
|
||||
hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
case HAL_NOR_MSP_INIT_CB_ID :
|
||||
hnor->MspInitCallback = HAL_NOR_MspInit;
|
||||
break;
|
||||
case HAL_NOR_MSP_DEINIT_CB_ID :
|
||||
hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
|
@ -1083,8 +1268,8 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C
|
|||
*/
|
||||
|
||||
/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### NOR Control functions #####
|
||||
|
@ -1106,7 +1291,7 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C
|
|||
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
|
||||
{
|
||||
/* Check the NOR controller state */
|
||||
if(hnor->State == HAL_NOR_STATE_PROTECTED)
|
||||
if (hnor->State == HAL_NOR_STATE_PROTECTED)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hnor);
|
||||
|
@ -1140,7 +1325,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
|
|||
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
|
||||
{
|
||||
/* Check the NOR controller state */
|
||||
if(hnor->State == HAL_NOR_STATE_READY)
|
||||
if (hnor->State == HAL_NOR_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hnor);
|
||||
|
@ -1170,8 +1355,8 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
|
|||
*/
|
||||
|
||||
/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### NOR State functions #####
|
||||
|
@ -1207,7 +1392,8 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
|
|||
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
|
||||
{
|
||||
HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
|
||||
uint16_t tmpSR1, tmpSR2;
|
||||
uint16_t tmpsr1;
|
||||
uint16_t tmpsr2;
|
||||
uint32_t tickstart;
|
||||
|
||||
/* Poll on NOR memory Ready/Busy signal ------------------------------------*/
|
||||
|
@ -1217,45 +1403,84 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
|
|||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
|
||||
|
||||
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
||||
{
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
|
||||
{
|
||||
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
status = HAL_NOR_STATUS_TIMEOUT;
|
||||
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
||||
{
|
||||
status = HAL_NOR_STATUS_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Read NOR status register (DQ6 and DQ5) */
|
||||
tmpsr1 = *(__IO uint16_t *)Address;
|
||||
tmpsr2 = *(__IO uint16_t *)Address;
|
||||
|
||||
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
|
||||
if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
|
||||
{
|
||||
return HAL_NOR_STATUS_SUCCESS ;
|
||||
}
|
||||
|
||||
if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
|
||||
{
|
||||
status = HAL_NOR_STATUS_ONGOING;
|
||||
}
|
||||
|
||||
tmpsr1 = *(__IO uint16_t *)Address;
|
||||
tmpsr2 = *(__IO uint16_t *)Address;
|
||||
|
||||
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
|
||||
if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
|
||||
{
|
||||
return HAL_NOR_STATUS_SUCCESS;
|
||||
}
|
||||
if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
|
||||
{
|
||||
return HAL_NOR_STATUS_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Read NOR status register (DQ6 and DQ5) */
|
||||
tmpSR1 = *(__IO uint16_t *)Address;
|
||||
tmpSR2 = *(__IO uint16_t *)Address;
|
||||
|
||||
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
|
||||
if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
|
||||
}
|
||||
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
|
||||
{
|
||||
do
|
||||
{
|
||||
return HAL_NOR_STATUS_SUCCESS ;
|
||||
}
|
||||
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
|
||||
tmpsr2 = *(__IO uint16_t *)(Address);
|
||||
|
||||
if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
|
||||
{
|
||||
status = HAL_NOR_STATUS_ONGOING;
|
||||
}
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
||||
{
|
||||
return HAL_NOR_STATUS_TIMEOUT;
|
||||
}
|
||||
}
|
||||
} while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U);
|
||||
|
||||
tmpSR1 = *(__IO uint16_t *)Address;
|
||||
tmpSR2 = *(__IO uint16_t *)Address;
|
||||
|
||||
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
|
||||
if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
|
||||
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
|
||||
tmpsr1 = *(__IO uint16_t *)(Address);
|
||||
if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U)
|
||||
{
|
||||
return HAL_NOR_STATUS_SUCCESS;
|
||||
/* Clear the Status Register */
|
||||
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
|
||||
status = HAL_NOR_STATUS_ERROR;
|
||||
}
|
||||
if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
|
||||
else
|
||||
{
|
||||
return HAL_NOR_STATUS_ERROR;
|
||||
status = HAL_NOR_STATUS_SUCCESS;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Primary command set not supported by the driver */
|
||||
status = HAL_NOR_STATUS_ERROR;
|
||||
}
|
||||
|
||||
/* Return the operation status */
|
||||
return status;
|
||||
|
|
|
@ -162,7 +162,8 @@
|
|||
* @param IOSpaceTiming IO space timing structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
|
||||
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming,
|
||||
FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
|
||||
{
|
||||
/* Check the PCCARD controller state */
|
||||
if (hpccard == NULL)
|
||||
|
@ -175,7 +176,7 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_T
|
|||
/* Allocate lock resource and initialize it */
|
||||
hpccard->Lock = HAL_UNLOCKED;
|
||||
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
|
||||
if(hpccard->MspInitCallback == NULL)
|
||||
if (hpccard->MspInitCallback == NULL)
|
||||
{
|
||||
hpccard->MspInitCallback = HAL_PCCARD_MspInit;
|
||||
}
|
||||
|
@ -223,7 +224,7 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_T
|
|||
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
|
||||
if(hpccard->MspDeInitCallback == NULL)
|
||||
if (hpccard->MspDeInitCallback == NULL)
|
||||
{
|
||||
hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
|
||||
}
|
||||
|
@ -334,8 +335,7 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp
|
|||
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||
|
||||
timeout--;
|
||||
}
|
||||
while ((status != PCCARD_STATUS_OK) && timeout);
|
||||
} while ((status != PCCARD_STATUS_OK) && timeout);
|
||||
|
||||
if (timeout == 0U)
|
||||
{
|
||||
|
@ -368,7 +368,8 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp
|
|||
* @param pStatus pointer to PCCARD status
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
|
||||
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
|
||||
uint8_t *pStatus)
|
||||
{
|
||||
uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
|
||||
uint8_t status = 0;
|
||||
|
@ -398,8 +399,7 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
|
|||
/* wait till the Status = 0x80 */
|
||||
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||
timeout--;
|
||||
}
|
||||
while ((status == 0x80U) && timeout);
|
||||
} while ((status == 0x80U) && timeout);
|
||||
|
||||
if (timeout == 0U)
|
||||
{
|
||||
|
@ -413,8 +413,7 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
|
|||
/* wait till the Status = PCCARD_STATUS_OK */
|
||||
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||
timeout--;
|
||||
}
|
||||
while ((status != PCCARD_STATUS_OK) && timeout);
|
||||
} while ((status != PCCARD_STATUS_OK) && timeout);
|
||||
|
||||
if (timeout == 0U)
|
||||
{
|
||||
|
@ -446,7 +445,8 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
|
|||
* @param pStatus pointer to PCCARD status
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
|
||||
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
|
||||
uint8_t *pStatus)
|
||||
{
|
||||
uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
|
||||
uint8_t status = 0;
|
||||
|
@ -476,8 +476,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_
|
|||
/* Wait till the Status = PCCARD_STATUS_OK */
|
||||
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||
timeout--;
|
||||
}
|
||||
while ((status != PCCARD_STATUS_OK) && timeout);
|
||||
} while ((status != PCCARD_STATUS_OK) && timeout);
|
||||
|
||||
if (timeout == 0U)
|
||||
{
|
||||
|
@ -495,8 +494,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_
|
|||
/* Wait till the Status = PCCARD_STATUS_WRITE_OK */
|
||||
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||
timeout--;
|
||||
}
|
||||
while ((status != PCCARD_STATUS_WRITE_OK) && timeout);
|
||||
} while ((status != PCCARD_STATUS_WRITE_OK) && timeout);
|
||||
|
||||
if (timeout == 0U)
|
||||
{
|
||||
|
@ -615,7 +613,7 @@ HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
|
|||
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
*/
|
||||
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
/* Check PCCARD interrupt Rising edge flag */
|
||||
|
@ -703,11 +701,12 @@ __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
|
|||
* @param pCallback : pointer to the Callback function
|
||||
* @retval status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCCARD_RegisterCallback (PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, pPCCARD_CallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId,
|
||||
pPCCARD_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if(pCallback == NULL)
|
||||
if (pCallback == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
@ -715,39 +714,39 @@ HAL_StatusTypeDef HAL_PCCARD_RegisterCallback (PCCARD_HandleTypeDef *hpccard, HA
|
|||
/* Process locked */
|
||||
__HAL_LOCK(hpccard);
|
||||
|
||||
if(hpccard->State == HAL_PCCARD_STATE_READY)
|
||||
if (hpccard->State == HAL_PCCARD_STATE_READY)
|
||||
{
|
||||
switch (CallbackId)
|
||||
{
|
||||
case HAL_PCCARD_MSP_INIT_CB_ID :
|
||||
hpccard->MspInitCallback = pCallback;
|
||||
break;
|
||||
case HAL_PCCARD_MSP_DEINIT_CB_ID :
|
||||
hpccard->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
case HAL_PCCARD_IT_CB_ID :
|
||||
hpccard->ItCallback = pCallback;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
case HAL_PCCARD_MSP_INIT_CB_ID :
|
||||
hpccard->MspInitCallback = pCallback;
|
||||
break;
|
||||
case HAL_PCCARD_MSP_DEINIT_CB_ID :
|
||||
hpccard->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
case HAL_PCCARD_IT_CB_ID :
|
||||
hpccard->ItCallback = pCallback;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if(hpccard->State == HAL_PCCARD_STATE_RESET)
|
||||
else if (hpccard->State == HAL_PCCARD_STATE_RESET)
|
||||
{
|
||||
switch (CallbackId)
|
||||
{
|
||||
case HAL_PCCARD_MSP_INIT_CB_ID :
|
||||
hpccard->MspInitCallback = pCallback;
|
||||
break;
|
||||
case HAL_PCCARD_MSP_DEINIT_CB_ID :
|
||||
hpccard->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
case HAL_PCCARD_MSP_INIT_CB_ID :
|
||||
hpccard->MspInitCallback = pCallback;
|
||||
break;
|
||||
case HAL_PCCARD_MSP_DEINIT_CB_ID :
|
||||
hpccard->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
|
@ -772,46 +771,46 @@ HAL_StatusTypeDef HAL_PCCARD_RegisterCallback (PCCARD_HandleTypeDef *hpccard, HA
|
|||
* @arg @ref HAL_PCCARD_IT_CB_ID PCCARD IT callback ID
|
||||
* @retval status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback (PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId)
|
||||
HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hpccard);
|
||||
|
||||
if(hpccard->State == HAL_PCCARD_STATE_READY)
|
||||
if (hpccard->State == HAL_PCCARD_STATE_READY)
|
||||
{
|
||||
switch (CallbackId)
|
||||
{
|
||||
case HAL_PCCARD_MSP_INIT_CB_ID :
|
||||
hpccard->MspInitCallback = HAL_PCCARD_MspInit;
|
||||
break;
|
||||
case HAL_PCCARD_MSP_DEINIT_CB_ID :
|
||||
hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
|
||||
break;
|
||||
case HAL_PCCARD_IT_CB_ID :
|
||||
hpccard->ItCallback = HAL_PCCARD_ITCallback;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
case HAL_PCCARD_MSP_INIT_CB_ID :
|
||||
hpccard->MspInitCallback = HAL_PCCARD_MspInit;
|
||||
break;
|
||||
case HAL_PCCARD_MSP_DEINIT_CB_ID :
|
||||
hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
|
||||
break;
|
||||
case HAL_PCCARD_IT_CB_ID :
|
||||
hpccard->ItCallback = HAL_PCCARD_ITCallback;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if(hpccard->State == HAL_PCCARD_STATE_RESET)
|
||||
else if (hpccard->State == HAL_PCCARD_STATE_RESET)
|
||||
{
|
||||
switch (CallbackId)
|
||||
{
|
||||
case HAL_PCCARD_MSP_INIT_CB_ID :
|
||||
hpccard->MspInitCallback = HAL_PCCARD_MspInit;
|
||||
break;
|
||||
case HAL_PCCARD_MSP_DEINIT_CB_ID :
|
||||
hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
case HAL_PCCARD_MSP_INIT_CB_ID :
|
||||
hpccard->MspInitCallback = HAL_PCCARD_MspInit;
|
||||
break;
|
||||
case HAL_PCCARD_MSP_DEINIT_CB_ID :
|
||||
hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
|
@ -831,8 +830,8 @@ HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback (PCCARD_HandleTypeDef *hpccard,
|
|||
*/
|
||||
|
||||
/** @defgroup PCCARD_Exported_Functions_Group3 State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### PCCARD State functions #####
|
||||
|
|
|
@ -94,6 +94,8 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint
|
|||
|
||||
#if defined (USB)
|
||||
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
|
||||
static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
|
||||
static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
|
||||
#endif /* defined (USB) */
|
||||
/**
|
||||
* @}
|
||||
|
@ -105,8 +107,8 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
|
|||
*/
|
||||
|
||||
/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
|
@ -252,7 +254,10 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
|
|||
hpcd->State = HAL_PCD_STATE_BUSY;
|
||||
|
||||
/* Stop Device */
|
||||
(void)HAL_PCD_Stop(hpcd);
|
||||
if (USB_StopDevice(hpcd->Instance) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
if (hpcd->MspDeInitCallback == NULL)
|
||||
|
@ -321,7 +326,9 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
|
|||
* @param pCallback pointer to the Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
|
||||
HAL_PCD_CallbackIDTypeDef CallbackID,
|
||||
pPCD_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -531,7 +538,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_Ca
|
|||
* @param pCallback pointer to the USB PCD Data OUT Stage Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_DataOutStageCallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -566,7 +574,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister the USB PCD Data OUT Stage Callback
|
||||
* @brief Unregister the USB PCD Data OUT Stage Callback
|
||||
* USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
|
@ -604,7 +612,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd
|
|||
* @param pCallback pointer to the USB PCD Data IN Stage Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_DataInStageCallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -639,7 +648,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, p
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister the USB PCD Data IN Stage Callback
|
||||
* @brief Unregister the USB PCD Data IN Stage Callback
|
||||
* USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
|
@ -677,7 +686,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
|
|||
* @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_IsoOutIncpltCallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -712,7 +722,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister the USB PCD Iso OUT incomplete Callback
|
||||
* @brief Unregister the USB PCD Iso OUT incomplete Callback
|
||||
* USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
|
@ -750,7 +760,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd
|
|||
* @param pCallback pointer to the USB PCD Iso IN incomplete Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_IsoInIncpltCallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
@ -785,7 +796,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, p
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister the USB PCD Iso IN incomplete Callback
|
||||
* @brief Unregister the USB PCD Iso IN incomplete Callback
|
||||
* USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
|
@ -823,8 +834,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
|
|||
*/
|
||||
|
||||
/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
|
@ -845,12 +856,15 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
|
|||
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
__HAL_LOCK(hpcd);
|
||||
__HAL_PCD_ENABLE(hpcd);
|
||||
|
||||
#if defined (USB)
|
||||
HAL_PCDEx_SetConnectionState(hpcd, 1U);
|
||||
#endif /* defined (USB) */
|
||||
|
||||
(void)USB_DevConnect(hpcd->Instance);
|
||||
__HAL_PCD_ENABLE(hpcd);
|
||||
__HAL_UNLOCK(hpcd);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
@ -864,17 +878,21 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
|
|||
__HAL_LOCK(hpcd);
|
||||
__HAL_PCD_DISABLE(hpcd);
|
||||
|
||||
if (USB_StopDevice(hpcd->Instance) != HAL_OK)
|
||||
{
|
||||
__HAL_UNLOCK(hpcd);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
#if defined (USB)
|
||||
HAL_PCDEx_SetConnectionState(hpcd, 0U);
|
||||
#endif /* defined (USB) */
|
||||
|
||||
(void)USB_DevDisconnect(hpcd->Instance);
|
||||
|
||||
#if defined (USB_OTG_FS)
|
||||
(void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
|
||||
__HAL_UNLOCK(hpcd);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
#if defined (USB_OTG_FS)
|
||||
/**
|
||||
* @brief Handles PCD interrupt request.
|
||||
|
@ -904,6 +922,38 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|||
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
|
||||
}
|
||||
|
||||
/* Handle RxQLevel Interrupt */
|
||||
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
|
||||
{
|
||||
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
||||
|
||||
temp = USBx->GRXSTSP;
|
||||
|
||||
ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
|
||||
|
||||
if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
|
||||
{
|
||||
if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
|
||||
{
|
||||
(void)USB_ReadPacket(USBx, ep->xfer_buff,
|
||||
(uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
|
||||
|
||||
ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
|
||||
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
|
||||
}
|
||||
}
|
||||
else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
|
||||
{
|
||||
(void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
|
||||
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* ... */
|
||||
}
|
||||
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
||||
}
|
||||
|
||||
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
|
||||
{
|
||||
epnum = 0U;
|
||||
|
@ -925,9 +975,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|||
|
||||
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
|
||||
{
|
||||
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
|
||||
/* Class B setup phase done for previous decoded setup */
|
||||
(void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
|
||||
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
|
||||
}
|
||||
|
||||
if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
|
||||
|
@ -1042,8 +1092,10 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|||
{
|
||||
USBx_INEP(i)->DIEPINT = 0xFB7FU;
|
||||
USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
|
||||
USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
|
||||
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
|
||||
USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
|
||||
USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
|
||||
}
|
||||
USBx_DEVICE->DAINTMSK |= 0x10001U;
|
||||
|
||||
|
@ -1099,38 +1151,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|||
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
|
||||
}
|
||||
|
||||
/* Handle RxQLevel Interrupt */
|
||||
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
|
||||
{
|
||||
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
||||
|
||||
temp = USBx->GRXSTSP;
|
||||
|
||||
ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
|
||||
|
||||
if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
|
||||
{
|
||||
if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
|
||||
{
|
||||
(void)USB_ReadPacket(USBx, ep->xfer_buff,
|
||||
(uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
|
||||
|
||||
ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
|
||||
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
|
||||
}
|
||||
}
|
||||
else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
|
||||
{
|
||||
(void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
|
||||
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* ... */
|
||||
}
|
||||
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
||||
}
|
||||
|
||||
/* Handle SOF Interrupt */
|
||||
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
|
||||
{
|
||||
|
@ -1204,6 +1224,18 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Handles PCD Wakeup interrupt request.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
/* Clear EXTI pending Bit */
|
||||
__HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG();
|
||||
}
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
|
||||
#if defined (USB)
|
||||
|
@ -1214,6 +1246,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|||
*/
|
||||
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
uint16_t store_ep[8];
|
||||
uint8_t i;
|
||||
|
||||
if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_CTR))
|
||||
{
|
||||
/* servicing of the endpoint correct transfer interrupt */
|
||||
|
@ -1260,19 +1295,41 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|||
|
||||
if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP))
|
||||
{
|
||||
/* WA: To Clear Wakeup flag if raised with suspend signal */
|
||||
|
||||
/* Store Endpoint register */
|
||||
for (i = 0U; i < 8U; i++)
|
||||
{
|
||||
store_ep[i] = PCD_GET_ENDPOINT(hpcd->Instance, i);
|
||||
}
|
||||
|
||||
/* FORCE RESET */
|
||||
hpcd->Instance->CNTR |= (uint16_t)(USB_CNTR_FRES);
|
||||
|
||||
/* CLEAR RESET */
|
||||
hpcd->Instance->CNTR &= (uint16_t)(~USB_CNTR_FRES);
|
||||
|
||||
/* wait for reset flag in ISTR */
|
||||
while ((hpcd->Instance->ISTR & USB_ISTR_RESET) == 0U)
|
||||
{
|
||||
}
|
||||
|
||||
/* Clear Reset Flag */
|
||||
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
|
||||
|
||||
/* Restore Registre */
|
||||
for (i = 0U; i < 8U; i++)
|
||||
{
|
||||
PCD_SET_ENDPOINT(hpcd->Instance, i, store_ep[i]);
|
||||
}
|
||||
|
||||
/* Force low-power mode in the macrocell */
|
||||
hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
|
||||
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
|
||||
|
||||
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
|
||||
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
|
||||
|
||||
hpcd->Instance->CNTR |= USB_CNTR_LP_MODE;
|
||||
|
||||
/* WA: Clear Wakeup flag if raised with suspend signal */
|
||||
if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP))
|
||||
{
|
||||
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
|
||||
}
|
||||
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LP_MODE;
|
||||
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->SuspendCallback(hpcd);
|
||||
|
@ -1298,6 +1355,18 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|||
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Handles PCD Wakeup interrupt request.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
/* Clear EXTI pending Bit */
|
||||
__HAL_USB_WAKEUP_EXTI_CLEAR_FLAG();
|
||||
}
|
||||
#endif /* defined (USB) */
|
||||
|
||||
/**
|
||||
|
@ -1477,8 +1546,8 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
|
|||
*/
|
||||
|
||||
/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
|
@ -1499,11 +1568,14 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
|
|||
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
__HAL_LOCK(hpcd);
|
||||
|
||||
#if defined (USB)
|
||||
HAL_PCDEx_SetConnectionState(hpcd, 1U);
|
||||
#endif /* defined (USB) */
|
||||
|
||||
(void)USB_DevConnect(hpcd->Instance);
|
||||
__HAL_UNLOCK(hpcd);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
@ -1515,11 +1587,14 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
|
|||
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
__HAL_LOCK(hpcd);
|
||||
|
||||
#if defined (USB)
|
||||
HAL_PCDEx_SetConnectionState(hpcd, 0U);
|
||||
#endif /* defined (USB) */
|
||||
|
||||
(void)USB_DevDisconnect(hpcd->Instance);
|
||||
__HAL_UNLOCK(hpcd);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
@ -1535,6 +1610,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
|
|||
hpcd->USB_Address = address;
|
||||
(void)USB_SetDevAddress(hpcd->Instance, address);
|
||||
__HAL_UNLOCK(hpcd);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
/**
|
||||
|
@ -1545,7 +1621,8 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
|
|||
* @param ep_type endpoint type
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint16_t ep_mps, uint8_t ep_type)
|
||||
{
|
||||
HAL_StatusTypeDef ret = HAL_OK;
|
||||
PCD_EPTypeDef *ep;
|
||||
|
@ -1672,6 +1749,10 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
|||
/*setup and start the Xfer */
|
||||
ep->xfer_buff = pBuf;
|
||||
ep->xfer_len = len;
|
||||
#if defined (USB)
|
||||
ep->xfer_fill_db = 1U;
|
||||
ep->xfer_len_db = len;
|
||||
#endif /* defined (USB) */
|
||||
ep->xfer_count = 0U;
|
||||
ep->is_in = 1U;
|
||||
ep->num = ep_addr & EP_ADDR_MSK;
|
||||
|
@ -1720,10 +1801,12 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|||
__HAL_LOCK(hpcd);
|
||||
|
||||
(void)USB_EPSetStall(hpcd->Instance, ep);
|
||||
|
||||
if ((ep_addr & EP_ADDR_MSK) == 0U)
|
||||
{
|
||||
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
|
||||
}
|
||||
|
||||
__HAL_UNLOCK(hpcd);
|
||||
|
||||
return HAL_OK;
|
||||
|
@ -1814,8 +1897,8 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
|
|||
*/
|
||||
|
||||
/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
|
@ -1970,8 +2053,7 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint
|
|||
uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
|
||||
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
|
||||
|
||||
|
||||
if ((gSNPSiD == USB_OTG_CORE_ID_310A) &&
|
||||
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
||||
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
|
||||
{
|
||||
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
||||
|
@ -1997,15 +2079,14 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint
|
|||
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
PCD_EPTypeDef *ep;
|
||||
uint16_t count;
|
||||
uint16_t wIstr;
|
||||
uint16_t wEPVal;
|
||||
uint16_t count, wIstr, wEPVal, TxByteNbre;
|
||||
uint8_t epindex;
|
||||
|
||||
/* stay in loop while pending interrupts */
|
||||
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
|
||||
{
|
||||
wIstr = hpcd->Instance->ISTR;
|
||||
|
||||
/* extract highest priority endpoint number */
|
||||
epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
|
||||
|
||||
|
@ -2018,8 +2099,8 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|||
{
|
||||
/* DIR = 0 */
|
||||
|
||||
/* DIR = 0 => IN int */
|
||||
/* DIR = 0 implies that (EP_CTR_TX = 1) always */
|
||||
/* DIR = 0 => IN int */
|
||||
/* DIR = 0 implies that (EP_CTR_TX = 1) always */
|
||||
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
|
||||
ep = &hpcd->IN_ep[0];
|
||||
|
||||
|
@ -2043,20 +2124,20 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|||
{
|
||||
/* DIR = 1 */
|
||||
|
||||
/* DIR = 1 & CTR_RX => SETUP or OUT int */
|
||||
/* DIR = 1 & CTR_RX => SETUP or OUT int */
|
||||
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
|
||||
ep = &hpcd->OUT_ep[0];
|
||||
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
|
||||
|
||||
if ((wEPVal & USB_EP_SETUP) != 0U)
|
||||
{
|
||||
/* Get SETUP Packet*/
|
||||
/* Get SETUP Packet */
|
||||
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
|
||||
|
||||
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
|
||||
ep->pmaadress, (uint16_t)ep->xfer_count);
|
||||
|
||||
/* SETUP bit kept frozen while CTR_RX = 1*/
|
||||
/* SETUP bit kept frozen while CTR_RX = 1 */
|
||||
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
|
||||
|
||||
/* Process SETUP Packet*/
|
||||
|
@ -2066,12 +2147,11 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|||
HAL_PCD_SetupStageCallback(hpcd);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
||||
else if ((wEPVal & USB_EP_CTR_RX) != 0U)
|
||||
{
|
||||
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
|
||||
|
||||
/* Get Control Data OUT Packet*/
|
||||
/* Get Control Data OUT Packet */
|
||||
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
|
||||
|
||||
if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
|
||||
|
@ -2081,7 +2161,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|||
|
||||
ep->xfer_buff += ep->xfer_count;
|
||||
|
||||
/* Process Control Data OUT Packet*/
|
||||
/* Process Control Data OUT Packet */
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->DataOutStageCallback(hpcd, 0U);
|
||||
#else
|
||||
|
@ -2096,20 +2176,21 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|||
}
|
||||
else
|
||||
{
|
||||
/* Decode and service non control endpoints interrupt */
|
||||
|
||||
/* Decode and service non control endpoints interrupt */
|
||||
/* process related endpoint register */
|
||||
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
|
||||
|
||||
if ((wEPVal & USB_EP_CTR_RX) != 0U)
|
||||
{
|
||||
/* clear int flag */
|
||||
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
|
||||
ep = &hpcd->OUT_ep[epindex];
|
||||
|
||||
/* OUT double Buffering*/
|
||||
/* OUT Single Buffering */
|
||||
if (ep->doublebuffer == 0U)
|
||||
{
|
||||
count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
|
||||
|
||||
if (count != 0U)
|
||||
{
|
||||
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
|
||||
|
@ -2117,28 +2198,39 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|||
}
|
||||
else
|
||||
{
|
||||
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
|
||||
/* manage double buffer bulk out */
|
||||
if (ep->type == EP_TYPE_BULK)
|
||||
{
|
||||
/*read from endpoint BUF0Addr buffer*/
|
||||
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
|
||||
if (count != 0U)
|
||||
count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
|
||||
}
|
||||
else /* manage double buffer iso out */
|
||||
{
|
||||
/* free EP OUT Buffer */
|
||||
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
|
||||
|
||||
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
|
||||
{
|
||||
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
|
||||
/* read from endpoint BUF0Addr buffer */
|
||||
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
|
||||
|
||||
if (count != 0U)
|
||||
{
|
||||
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* read from endpoint BUF1Addr buffer */
|
||||
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
|
||||
|
||||
if (count != 0U)
|
||||
{
|
||||
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*read from endpoint BUF1Addr buffer*/
|
||||
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
|
||||
if (count != 0U)
|
||||
{
|
||||
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
|
||||
}
|
||||
}
|
||||
/* free EP OUT Buffer */
|
||||
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
|
||||
}
|
||||
/*multi-packet on the NON control OUT endpoint*/
|
||||
/* multi-packet on the NON control OUT endpoint */
|
||||
ep->xfer_count += count;
|
||||
ep->xfer_buff += count;
|
||||
|
||||
|
@ -2153,10 +2245,10 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|||
}
|
||||
else
|
||||
{
|
||||
(void)HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
|
||||
(void) USB_EPStartXfer(hpcd->Instance, ep);
|
||||
}
|
||||
|
||||
} /* if((wEPVal & EP_CTR_RX) */
|
||||
}
|
||||
|
||||
if ((wEPVal & USB_EP_CTR_TX) != 0U)
|
||||
{
|
||||
|
@ -2165,29 +2257,294 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|||
/* clear int flag */
|
||||
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
|
||||
|
||||
/*multi-packet on the NON control IN endpoint*/
|
||||
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
|
||||
ep->xfer_buff += ep->xfer_count;
|
||||
|
||||
/* Zero Length Packet? */
|
||||
if (ep->xfer_len == 0U)
|
||||
/* Manage all non bulk transaction or Bulk Single Buffer Transaction */
|
||||
if ((ep->type != EP_TYPE_BULK) ||
|
||||
((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U)))
|
||||
{
|
||||
/* TX COMPLETE */
|
||||
/* multi-packet on the NON control IN endpoint */
|
||||
TxByteNbre = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
|
||||
|
||||
if (ep->xfer_len > TxByteNbre)
|
||||
{
|
||||
ep->xfer_len -= TxByteNbre;
|
||||
}
|
||||
else
|
||||
{
|
||||
ep->xfer_len = 0U;
|
||||
}
|
||||
|
||||
/* Zero Length Packet? */
|
||||
if (ep->xfer_len == 0U)
|
||||
{
|
||||
/* TX COMPLETE */
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->DataInStageCallback(hpcd, ep->num);
|
||||
hpcd->DataInStageCallback(hpcd, ep->num);
|
||||
#else
|
||||
HAL_PCD_DataInStageCallback(hpcd, ep->num);
|
||||
HAL_PCD_DataInStageCallback(hpcd, ep->num);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Transfer is not yet Done */
|
||||
ep->xfer_buff += TxByteNbre;
|
||||
ep->xfer_count += TxByteNbre;
|
||||
(void)USB_EPStartXfer(hpcd->Instance, ep);
|
||||
}
|
||||
}
|
||||
/* bulk in double buffer enable in case of transferLen> Ep_Mps */
|
||||
else
|
||||
{
|
||||
(void)HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
|
||||
(void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Manage double buffer bulk out transaction from ISR
|
||||
* @param hpcd PCD handle
|
||||
* @param ep current endpoint handle
|
||||
* @param wEPVal Last snapshot of EPRx register value taken in ISR
|
||||
* @retval HAL status
|
||||
*/
|
||||
static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
|
||||
PCD_EPTypeDef *ep, uint16_t wEPVal)
|
||||
{
|
||||
uint16_t count;
|
||||
|
||||
/* Manage Buffer0 OUT */
|
||||
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
|
||||
{
|
||||
/* Get count of received Data on buffer0 */
|
||||
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
|
||||
|
||||
if (ep->xfer_len >= count)
|
||||
{
|
||||
ep->xfer_len -= count;
|
||||
}
|
||||
else
|
||||
{
|
||||
ep->xfer_len = 0U;
|
||||
}
|
||||
|
||||
if (ep->xfer_len == 0U)
|
||||
{
|
||||
/* set NAK to OUT endpoint since double buffer is enabled */
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
|
||||
}
|
||||
|
||||
/* Check if Buffer1 is in blocked sate which requires to toggle */
|
||||
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
|
||||
{
|
||||
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
|
||||
}
|
||||
|
||||
if (count != 0U)
|
||||
{
|
||||
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
|
||||
}
|
||||
}
|
||||
/* Manage Buffer 1 DTOG_RX=0 */
|
||||
else
|
||||
{
|
||||
/* Get count of received data */
|
||||
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
|
||||
|
||||
if (ep->xfer_len >= count)
|
||||
{
|
||||
ep->xfer_len -= count;
|
||||
}
|
||||
else
|
||||
{
|
||||
ep->xfer_len = 0U;
|
||||
}
|
||||
|
||||
if (ep->xfer_len == 0U)
|
||||
{
|
||||
/* set NAK on the current endpoint */
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
|
||||
}
|
||||
|
||||
/*Need to FreeUser Buffer*/
|
||||
if ((wEPVal & USB_EP_DTOG_TX) == 0U)
|
||||
{
|
||||
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
|
||||
}
|
||||
|
||||
if (count != 0U)
|
||||
{
|
||||
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
|
||||
}
|
||||
}
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Manage double buffer bulk IN transaction from ISR
|
||||
* @param hpcd PCD handle
|
||||
* @param ep current endpoint handle
|
||||
* @param wEPVal Last snapshot of EPRx register value taken in ISR
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
|
||||
PCD_EPTypeDef *ep, uint16_t wEPVal)
|
||||
{
|
||||
uint32_t len;
|
||||
uint16_t TxByteNbre;
|
||||
|
||||
/* Data Buffer0 ACK received */
|
||||
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
|
||||
{
|
||||
/* multi-packet on the NON control IN endpoint */
|
||||
TxByteNbre = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
|
||||
|
||||
if (ep->xfer_len > TxByteNbre)
|
||||
{
|
||||
ep->xfer_len -= TxByteNbre;
|
||||
}
|
||||
else
|
||||
{
|
||||
ep->xfer_len = 0U;
|
||||
}
|
||||
/* Transfer is completed */
|
||||
if (ep->xfer_len == 0U)
|
||||
{
|
||||
/* TX COMPLETE */
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->DataInStageCallback(hpcd, ep->num);
|
||||
#else
|
||||
HAL_PCD_DataInStageCallback(hpcd, ep->num);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
|
||||
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
|
||||
{
|
||||
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
|
||||
}
|
||||
}
|
||||
else /* Transfer is not yet Done */
|
||||
{
|
||||
/* need to Free USB Buff */
|
||||
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
|
||||
{
|
||||
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
|
||||
}
|
||||
|
||||
/* Still there is data to Fill in the next Buffer */
|
||||
if (ep->xfer_fill_db == 1U)
|
||||
{
|
||||
ep->xfer_buff += TxByteNbre;
|
||||
ep->xfer_count += TxByteNbre;
|
||||
|
||||
/* Calculate the len of the new buffer to fill */
|
||||
if (ep->xfer_len_db >= ep->maxpacket)
|
||||
{
|
||||
len = ep->maxpacket;
|
||||
ep->xfer_len_db -= len;
|
||||
}
|
||||
else if (ep->xfer_len_db == 0U)
|
||||
{
|
||||
len = TxByteNbre;
|
||||
ep->xfer_fill_db = 0U;
|
||||
}
|
||||
else
|
||||
{
|
||||
ep->xfer_fill_db = 0U;
|
||||
len = ep->xfer_len_db;
|
||||
ep->xfer_len_db = 0U;
|
||||
}
|
||||
|
||||
/* Write remaining Data to Buffer */
|
||||
/* Set the Double buffer counter for pma buffer1 */
|
||||
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
|
||||
|
||||
/* Copy user buffer to USB PMA */
|
||||
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len);
|
||||
}
|
||||
}
|
||||
}
|
||||
else /* Data Buffer1 ACK received */
|
||||
{
|
||||
/* multi-packet on the NON control IN endpoint */
|
||||
TxByteNbre = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
|
||||
|
||||
if (ep->xfer_len >= TxByteNbre)
|
||||
{
|
||||
ep->xfer_len -= TxByteNbre;
|
||||
}
|
||||
else
|
||||
{
|
||||
ep->xfer_len = 0U;
|
||||
}
|
||||
|
||||
/* Transfer is completed */
|
||||
if (ep->xfer_len == 0U)
|
||||
{
|
||||
/* TX COMPLETE */
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->DataInStageCallback(hpcd, ep->num);
|
||||
#else
|
||||
HAL_PCD_DataInStageCallback(hpcd, ep->num);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
|
||||
/*need to Free USB Buff*/
|
||||
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
|
||||
{
|
||||
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
|
||||
}
|
||||
}
|
||||
else /* Transfer is not yet Done */
|
||||
{
|
||||
/* need to Free USB Buff */
|
||||
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
|
||||
{
|
||||
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
|
||||
}
|
||||
|
||||
/* Still there is data to Fill in the next Buffer */
|
||||
if (ep->xfer_fill_db == 1U)
|
||||
{
|
||||
ep->xfer_buff += TxByteNbre;
|
||||
ep->xfer_count += TxByteNbre;
|
||||
|
||||
/* Calculate the len of the new buffer to fill */
|
||||
if (ep->xfer_len_db >= ep->maxpacket)
|
||||
{
|
||||
len = ep->maxpacket;
|
||||
ep->xfer_len_db -= len;
|
||||
}
|
||||
else if (ep->xfer_len_db == 0U)
|
||||
{
|
||||
len = TxByteNbre;
|
||||
ep->xfer_fill_db = 0U;
|
||||
}
|
||||
else
|
||||
{
|
||||
len = ep->xfer_len_db;
|
||||
ep->xfer_len_db = 0U;
|
||||
ep->xfer_fill_db = 0;
|
||||
}
|
||||
|
||||
/* Set the Double buffer counter for pmabuffer1 */
|
||||
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
|
||||
|
||||
/* Copy the user buffer to USB PMA */
|
||||
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*enable endpoint IN*/
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
#endif /* defined (USB) */
|
||||
|
||||
/**
|
||||
|
|
|
@ -49,7 +49,7 @@
|
|||
|
||||
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
||||
* @brief PCDEx control functions
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
|
@ -135,10 +135,8 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
|
|||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
|
||||
uint16_t ep_addr,
|
||||
uint16_t ep_kind,
|
||||
uint32_t pmaadress)
|
||||
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
|
||||
uint16_t ep_kind, uint32_t pmaadress)
|
||||
{
|
||||
PCD_EPTypeDef *ep;
|
||||
|
||||
|
@ -176,8 +174,8 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
|
|||
* @brief Software Device Connection,
|
||||
* this function is not required by USB OTG FS peripheral, it is used
|
||||
* only by USB Device FS peripheral.
|
||||
* @param hpcd: PCD handle
|
||||
* @param state: connection state (0 : disconnected / 1: connected)
|
||||
* @param hpcd PCD handle
|
||||
* @param state connection state (0 : disconnected / 1: connected)
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
|
||||
|
|
|
@ -132,7 +132,7 @@
|
|||
(+) Tamper1EventCallback : RTC Tamper 1 Event callback.
|
||||
(+) MspInitCallback : RTC MspInit callback.
|
||||
(+) MspDeInitCallback : RTC MspDeInit callback.
|
||||
[..]
|
||||
[..]
|
||||
This function takes as parameters the HAL peripheral handle, the Callback ID
|
||||
and a pointer to the user callback function.
|
||||
|
||||
|
|
|
@ -755,7 +755,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc,
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
{
|
||||
uint16_t* tmp;
|
||||
uint8_t *tmp = pData;
|
||||
uint32_t tickstart = 0U;
|
||||
|
||||
if(hsc->gState == HAL_SMARTCARD_STATE_READY)
|
||||
|
@ -783,9 +783,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
|
|||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
tmp = (uint16_t*) pData;
|
||||
hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
|
||||
pData +=1U;
|
||||
hsc->Instance->DR = (uint8_t)(*tmp & 0xFFU);
|
||||
tmp++;
|
||||
}
|
||||
|
||||
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
|
||||
|
@ -818,7 +817,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
{
|
||||
uint16_t* tmp;
|
||||
uint8_t *tmp = pData;
|
||||
uint32_t tickstart = 0U;
|
||||
|
||||
if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
|
||||
|
@ -848,9 +847,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
|
|||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
tmp = (uint16_t*) pData;
|
||||
*tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
|
||||
pData +=1U;
|
||||
*tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFFU);
|
||||
tmp++;
|
||||
}
|
||||
|
||||
/* At end of Rx process, restore hsc->RxState to Ready */
|
||||
|
@ -1567,7 +1565,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
|
|||
}
|
||||
|
||||
/* SMARTCARD Over-Run interrupt occurred -------------------------------*/
|
||||
if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
|
||||
if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
|
||||
{
|
||||
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
|
||||
}
|
||||
|
@ -1996,14 +1994,12 @@ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc)
|
|||
*/
|
||||
static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
|
||||
{
|
||||
uint16_t* tmp;
|
||||
|
||||
/* Check that a Tx process is ongoing */
|
||||
if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)
|
||||
{
|
||||
tmp = (uint16_t*) hsc->pTxBuffPtr;
|
||||
hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
|
||||
hsc->pTxBuffPtr += 1U;
|
||||
hsc->Instance->DR = (uint8_t)(*hsc->pTxBuffPtr & 0xFFU);
|
||||
hsc->pTxBuffPtr++;
|
||||
|
||||
if(--hsc->TxXferCount == 0U)
|
||||
{
|
||||
|
@ -2058,14 +2054,12 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
|
|||
*/
|
||||
static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
|
||||
{
|
||||
uint16_t* tmp;
|
||||
|
||||
/* Check that a Rx process is ongoing */
|
||||
if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
|
||||
{
|
||||
tmp = (uint16_t*) hsc->pRxBuffPtr;
|
||||
*tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
|
||||
hsc->pRxBuffPtr += 1U;
|
||||
*hsc->pRxBuffPtr = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFFU);
|
||||
hsc->pRxBuffPtr++;
|
||||
|
||||
if(--hsc->RxXferCount == 0U)
|
||||
{
|
||||
|
|
|
@ -131,7 +131,7 @@
|
|||
DataSize = SPI_DATASIZE_8BIT:
|
||||
+----------------------------------------------------------------------------------------------+
|
||||
| | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
|
||||
| Process | Tranfert mode |---------------------|----------------------|----------------------|
|
||||
| Process | Transfer mode |---------------------|----------------------|----------------------|
|
||||
| | | Master | Slave | Master | Slave | Master | Slave |
|
||||
|==============================================================================================|
|
||||
| T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
|
||||
|
@ -156,7 +156,7 @@
|
|||
DataSize = SPI_DATASIZE_16BIT:
|
||||
+----------------------------------------------------------------------------------------------+
|
||||
| | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
|
||||
| Process | Tranfert mode |---------------------|----------------------|----------------------|
|
||||
| Process | Transfer mode |---------------------|----------------------|----------------------|
|
||||
| | | Master | Slave | Master | Slave | Master | Slave |
|
||||
|==============================================================================================|
|
||||
| T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
|
||||
|
@ -355,6 +355,24 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
|||
{
|
||||
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
|
||||
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
|
||||
|
||||
if (hspi->Init.Mode == SPI_MODE_MASTER)
|
||||
{
|
||||
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
|
||||
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
||||
|
||||
/* Force polarity and phase to TI protocaol requirements */
|
||||
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
|
||||
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
|
||||
}
|
||||
#if (USE_SPI_CRC != 0U)
|
||||
assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
|
||||
|
@ -403,9 +421,15 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
|||
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
|
||||
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
|
||||
Communication speed, First bit and CRC calculation state */
|
||||
WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
|
||||
hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
|
||||
hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
|
||||
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
|
||||
(hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
|
||||
(hspi->Init.DataSize & SPI_CR1_DFF) |
|
||||
(hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
|
||||
(hspi->Init.CLKPhase & SPI_CR1_CPHA) |
|
||||
(hspi->Init.NSS & SPI_CR1_SSM) |
|
||||
(hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
|
||||
(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
|
||||
(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
|
||||
|
||||
/* Configure : NSS management */
|
||||
WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE));
|
||||
|
@ -415,7 +439,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
|||
/* Configure : CRC Polynomial */
|
||||
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
|
||||
{
|
||||
WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
|
||||
WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
|
||||
}
|
||||
#endif /* USE_SPI_CRC */
|
||||
|
||||
|
@ -813,6 +837,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
|
|||
/* Configure communication direction : 1Line */
|
||||
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
||||
{
|
||||
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
||||
__HAL_SPI_DISABLE(hspi);
|
||||
SPI_1LINE_TX(hspi);
|
||||
}
|
||||
|
||||
|
@ -988,6 +1014,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
|
|||
/* Configure communication direction: 1Line */
|
||||
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
||||
{
|
||||
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
||||
__HAL_SPI_DISABLE(hspi);
|
||||
SPI_1LINE_RX(hspi);
|
||||
}
|
||||
|
||||
|
@ -1414,6 +1442,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
|
|||
/* Configure communication direction : 1Line */
|
||||
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
||||
{
|
||||
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
||||
__HAL_SPI_DISABLE(hspi);
|
||||
SPI_1LINE_TX(hspi);
|
||||
}
|
||||
|
||||
|
@ -1501,6 +1531,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
|
|||
/* Configure communication direction : 1Line */
|
||||
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
||||
{
|
||||
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
||||
__HAL_SPI_DISABLE(hspi);
|
||||
SPI_1LINE_RX(hspi);
|
||||
}
|
||||
|
||||
|
@ -1671,6 +1703,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
|
|||
/* Configure communication direction : 1Line */
|
||||
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
||||
{
|
||||
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
||||
__HAL_SPI_DISABLE(hspi);
|
||||
SPI_1LINE_TX(hspi);
|
||||
}
|
||||
|
||||
|
@ -1784,6 +1818,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
|
|||
/* Configure communication direction : 1Line */
|
||||
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
||||
{
|
||||
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
||||
__HAL_SPI_DISABLE(hspi);
|
||||
SPI_1LINE_RX(hspi);
|
||||
}
|
||||
|
||||
|
@ -2400,7 +2436,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
|
|||
|
||||
/* SPI in Error Treatment --------------------------------------------------*/
|
||||
if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET))
|
||||
&& (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
|
||||
&& (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
|
||||
{
|
||||
/* SPI Overrun error interrupt occurred ----------------------------------*/
|
||||
if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
|
||||
|
@ -2752,8 +2788,17 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
|
|||
}
|
||||
#endif /* USE_SPI_CRC */
|
||||
|
||||
/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
|
||||
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
|
||||
/* Check if we are in Master RX 2 line mode */
|
||||
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
|
||||
{
|
||||
/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
|
||||
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Normal case */
|
||||
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
|
||||
}
|
||||
|
||||
/* Check the end of the transaction */
|
||||
if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
|
||||
|
@ -3151,7 +3196,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
|
|||
*/
|
||||
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
|
||||
{
|
||||
/* Read 8bit CRC to flush Data Regsiter */
|
||||
/* Read 8bit CRC to flush Data Register */
|
||||
READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
|
||||
|
||||
/* Disable RXNE and ERR interrupt */
|
||||
|
@ -3242,7 +3287,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
|
|||
*/
|
||||
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
|
||||
{
|
||||
/* Read 16bit CRC to flush Data Regsiter */
|
||||
/* Read 16bit CRC to flush Data Register */
|
||||
READ_REG(hspi->Instance->DR);
|
||||
|
||||
/* Disable RXNE interrupt */
|
||||
|
@ -3468,15 +3513,26 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
|
|||
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
|
||||
uint32_t Timeout, uint32_t Tickstart)
|
||||
{
|
||||
__IO uint32_t count;
|
||||
uint32_t tmp_timeout;
|
||||
uint32_t tmp_tickstart;
|
||||
|
||||
/* Adjust Timeout value in case of end of transfer */
|
||||
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
|
||||
tmp_tickstart = HAL_GetTick();
|
||||
|
||||
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
|
||||
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
|
||||
|
||||
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
|
||||
{
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
|
||||
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
|
||||
{
|
||||
/* Disable the SPI and reset the CRC: the CRC value should be cleared
|
||||
on both master and slave sides in order to resynchronize the master
|
||||
and slave for their respective CRC calculation */
|
||||
on both master and slave sides in order to resynchronize the master
|
||||
and slave for their respective CRC calculation */
|
||||
|
||||
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
|
||||
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
|
||||
|
@ -3501,6 +3557,12 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi,
|
|||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
|
||||
if(count == 0U)
|
||||
{
|
||||
tmp_timeout = 0U;
|
||||
}
|
||||
count--;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -3574,7 +3636,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
|
|||
uint32_t tickstart;
|
||||
__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
|
||||
|
||||
/* Init tickstart for timeout managment*/
|
||||
/* Init tickstart for timeout management */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Disable ERR interrupt */
|
||||
|
@ -3867,9 +3929,9 @@ uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
|
|||
#if defined(SPI_CRC_ERROR_WORKAROUND_FEATURE) && (USE_SPI_CRC_ERROR_WORKAROUND != 0U)
|
||||
/* Check how to handle this CRC error (workaround to be applied or not) */
|
||||
/* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
|
||||
if(hspi->Instance == SPI2)
|
||||
if (hspi->Instance == SPI2)
|
||||
{
|
||||
if(hspi->Instance->RXCRCR == 0U)
|
||||
if (hspi->Instance->RXCRCR == 0U)
|
||||
{
|
||||
return (SPI_INVALID_CRC_ERROR);
|
||||
}
|
||||
|
|
|
@ -1,231 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_spi_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended SPI HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities SPI extension peripheral:
|
||||
* + Extended Peripheral Control functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
|
||||
/** @defgroup SPI_Private_Variables SPI Private Variables
|
||||
* @{
|
||||
*/
|
||||
#if (USE_SPI_CRC != 0U)
|
||||
/* Variable used to determine if device is impacted by implementation of workaround
|
||||
related to wrong CRC errors detection on SPI2. Conditions in which this workaround has to be applied, are:
|
||||
- STM32F101CDE/STM32F103CDE
|
||||
- Revision ID : Z
|
||||
- SPI2
|
||||
- In receive only mode, with CRC calculation enabled, at the end of the CRC reception,
|
||||
the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC:
|
||||
+ If the value is 0, the complete data transfer is successful.
|
||||
+ Otherwise, one or more errors have been detected during the data transfer by CPU or DMA.
|
||||
If CRCERR is found reset, the complete data transfer is considered successful.
|
||||
*/
|
||||
uint8_t uCRCErrorWorkaroundCheck = 0U;
|
||||
#endif /* USE_SPI_CRC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group1
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the SPI according to the specified parameters
|
||||
* in the SPI_InitTypeDef and create the associated handle.
|
||||
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
|
||||
* the configuration information for SPI module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
||||
{
|
||||
/* Check the SPI handle allocation */
|
||||
if(hspi == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
|
||||
assert_param(IS_SPI_MODE(hspi->Init.Mode));
|
||||
assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
|
||||
assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
|
||||
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
|
||||
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
|
||||
assert_param(IS_SPI_NSS(hspi->Init.NSS));
|
||||
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
||||
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
|
||||
|
||||
#if (USE_SPI_CRC != 0U)
|
||||
assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
|
||||
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
|
||||
{
|
||||
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
|
||||
}
|
||||
#else
|
||||
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
||||
#endif /* USE_SPI_CRC */
|
||||
|
||||
if(hspi->State == HAL_SPI_STATE_RESET)
|
||||
{
|
||||
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
||||
HAL_SPI_MspInit(hspi);
|
||||
}
|
||||
|
||||
hspi->State = HAL_SPI_STATE_BUSY;
|
||||
|
||||
/* Disble the selected SPI peripheral */
|
||||
__HAL_SPI_DISABLE(hspi);
|
||||
|
||||
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
|
||||
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
|
||||
Communication speed, First bit and CRC calculation state */
|
||||
WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
|
||||
hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
|
||||
hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
|
||||
|
||||
/* Configure : NSS management */
|
||||
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
|
||||
|
||||
/*---------------------------- SPIx CRCPOLY Configuration ------------------*/
|
||||
/* Configure : CRC Polynomial */
|
||||
WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
|
||||
|
||||
#if defined(SPI_I2SCFGR_I2SMOD)
|
||||
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
|
||||
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
|
||||
#endif /* SPI_I2SCFGR_I2SMOD */
|
||||
|
||||
#if (USE_SPI_CRC != 0U)
|
||||
#if defined (STM32F101xE) || defined (STM32F103xE)
|
||||
/* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
|
||||
CRC errors wrongly detected */
|
||||
/* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode.
|
||||
Revision ID information is only available in Debug mode, so Workaround could not be implemented
|
||||
to distinguish Rev Z devices (issue present) from more recent version (issue fixed).
|
||||
So, in case of Revison Z F101 or F103 devices, below variable should be assigned to 1 */
|
||||
uCRCErrorWorkaroundCheck = 0U;
|
||||
#else
|
||||
uCRCErrorWorkaroundCheck = 0U;
|
||||
#endif /* STM32F101xE || STM32F103xE */
|
||||
#endif /* USE_SPI_CRC */
|
||||
|
||||
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
||||
hspi->State = HAL_SPI_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
#if (USE_SPI_CRC != 0U)
|
||||
/**
|
||||
* @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
|
||||
* according to SPI instance, Device type, and revision ID.
|
||||
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
|
||||
* the configuration information for SPI module.
|
||||
* @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
|
||||
*/
|
||||
uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
|
||||
{
|
||||
#if defined(STM32F101xE) || defined(STM32F103xE)
|
||||
/* Check how to handle this CRC error (workaround to be applied or not) */
|
||||
/* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
|
||||
if((uCRCErrorWorkaroundCheck != 0U) && (hspi->Instance == SPI2))
|
||||
{
|
||||
if(hspi->Instance->RXCRCR == 0U)
|
||||
{
|
||||
return (SPI_INVALID_CRC_ERROR);
|
||||
}
|
||||
}
|
||||
return (SPI_VALID_CRC_ERROR);
|
||||
#else
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hspi);
|
||||
|
||||
return (SPI_VALID_CRC_ERROR);
|
||||
#endif
|
||||
}
|
||||
#endif /* USE_SPI_CRC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
@ -136,9 +136,9 @@
|
|||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
static void SRAM_DMACplt (DMA_HandleTypeDef *hdma);
|
||||
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
|
||||
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
|
||||
static void SRAM_DMAError (DMA_HandleTypeDef *hdma);
|
||||
static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
@endcond
|
||||
*/
|
||||
|
@ -171,10 +171,11 @@ static void SRAM_DMAError (DMA_HandleTypeDef *hdma);
|
|||
* @param ExtTiming Pointer to SRAM extended mode timing structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
|
||||
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing,
|
||||
FSMC_NORSRAM_TimingTypeDef *ExtTiming)
|
||||
{
|
||||
/* Check the SRAM handle parameter */
|
||||
if (hsram == NULL)
|
||||
if ((hsram == NULL) || (hsram->Init.BurstAccessMode == FSMC_BURST_ACCESS_MODE_ENABLE))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
@ -185,7 +186,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTy
|
|||
hsram->Lock = HAL_UNLOCKED;
|
||||
|
||||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
||||
if(hsram->MspInitCallback == NULL)
|
||||
if (hsram->MspInitCallback == NULL)
|
||||
{
|
||||
hsram->MspInitCallback = HAL_SRAM_MspInit;
|
||||
}
|
||||
|
@ -207,7 +208,8 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTy
|
|||
(void)FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
|
||||
|
||||
/* Initialize SRAM extended mode timing Interface */
|
||||
(void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
|
||||
(void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
|
||||
hsram->Init.ExtendedMode);
|
||||
|
||||
/* Enable the NORSRAM device */
|
||||
__FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
|
||||
|
@ -227,7 +229,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTy
|
|||
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
|
||||
{
|
||||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
||||
if(hsram->MspDeInitCallback == NULL)
|
||||
if (hsram->MspDeInitCallback == NULL)
|
||||
{
|
||||
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
|
||||
}
|
||||
|
@ -342,11 +344,12 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
|
|||
* @param BufferSize Size of the buffer to read from memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
|
||||
uint32_t BufferSize)
|
||||
{
|
||||
uint32_t size;
|
||||
__IO uint8_t *psramaddress = (uint8_t *)pAddress;
|
||||
uint8_t * pdestbuff = pDstBuffer;
|
||||
uint8_t *pdestbuff = pDstBuffer;
|
||||
HAL_SRAM_StateTypeDef state = hsram->State;
|
||||
|
||||
/* Check the SRAM controller state */
|
||||
|
@ -389,11 +392,12 @@ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress
|
|||
* @param BufferSize Size of the buffer to write to memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
|
||||
uint32_t BufferSize)
|
||||
{
|
||||
uint32_t size;
|
||||
__IO uint8_t *psramaddress = (uint8_t *)pAddress;
|
||||
uint8_t * psrcbuff = pSrcBuffer;
|
||||
uint8_t *psrcbuff = pSrcBuffer;
|
||||
|
||||
/* Check the SRAM controller state */
|
||||
if (hsram->State == HAL_SRAM_STATE_READY)
|
||||
|
@ -435,7 +439,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
|
|||
* @param BufferSize Size of the buffer to read from memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
|
||||
uint32_t BufferSize)
|
||||
{
|
||||
uint32_t size;
|
||||
__IO uint32_t *psramaddress = pAddress;
|
||||
|
@ -452,11 +457,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
|
|||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Check if the size is a 32-bits mulitple */
|
||||
/* Check if the size is a 32-bits multiple */
|
||||
limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
|
||||
|
||||
/* Read data from memory */
|
||||
for (size = BufferSize; size != limit; size-=2U)
|
||||
for (size = BufferSize; size != limit; size -= 2U)
|
||||
{
|
||||
*pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
|
||||
pdestbuff++;
|
||||
|
@ -494,11 +499,12 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
|
|||
* @param BufferSize Size of the buffer to write to memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
|
||||
uint32_t BufferSize)
|
||||
{
|
||||
uint32_t size;
|
||||
__IO uint32_t *psramaddress = pAddress;
|
||||
uint16_t * psrcbuff = pSrcBuffer;
|
||||
uint16_t *psrcbuff = pSrcBuffer;
|
||||
uint8_t limit;
|
||||
|
||||
/* Check the SRAM controller state */
|
||||
|
@ -510,11 +516,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
|
|||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Check if the size is a 32-bits mulitple */
|
||||
/* Check if the size is a 32-bits multiple */
|
||||
limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
|
||||
|
||||
/* Write data to memory */
|
||||
for (size = BufferSize; size != limit; size-=2U)
|
||||
for (size = BufferSize; size != limit; size -= 2U)
|
||||
{
|
||||
*psramaddress = (uint32_t)(*psrcbuff);
|
||||
psrcbuff++;
|
||||
|
@ -552,11 +558,12 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
|
|||
* @param BufferSize Size of the buffer to read from memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
|
||||
uint32_t BufferSize)
|
||||
{
|
||||
uint32_t size;
|
||||
__IO uint32_t * psramaddress = pAddress;
|
||||
uint32_t * pdestbuff = pDstBuffer;
|
||||
__IO uint32_t *psramaddress = pAddress;
|
||||
uint32_t *pdestbuff = pDstBuffer;
|
||||
HAL_SRAM_StateTypeDef state = hsram->State;
|
||||
|
||||
/* Check the SRAM controller state */
|
||||
|
@ -599,11 +606,12 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
|
|||
* @param BufferSize Size of the buffer to write to memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
|
||||
uint32_t BufferSize)
|
||||
{
|
||||
uint32_t size;
|
||||
__IO uint32_t * psramaddress = pAddress;
|
||||
uint32_t * psrcbuff = pSrcBuffer;
|
||||
__IO uint32_t *psramaddress = pAddress;
|
||||
uint32_t *psrcbuff = pSrcBuffer;
|
||||
|
||||
/* Check the SRAM controller state */
|
||||
if (hsram->State == HAL_SRAM_STATE_READY)
|
||||
|
@ -645,7 +653,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
|
|||
* @param BufferSize Size of the buffer to read from memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
|
||||
uint32_t BufferSize)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
HAL_SRAM_StateTypeDef state = hsram->State;
|
||||
|
@ -678,7 +687,7 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
|
|||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
|
@ -693,7 +702,8 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
|
|||
* @param BufferSize Size of the buffer to write to memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
|
||||
uint32_t BufferSize)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
|
@ -718,7 +728,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
|
|||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
|
@ -736,12 +746,13 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
|
|||
* @param pCallback : pointer to the Callback function
|
||||
* @retval status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
|
||||
pSRAM_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
HAL_SRAM_StateTypeDef state;
|
||||
|
||||
if(pCallback == NULL)
|
||||
if (pCallback == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
@ -750,20 +761,20 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM
|
|||
__HAL_LOCK(hsram);
|
||||
|
||||
state = hsram->State;
|
||||
if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
|
||||
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
|
||||
{
|
||||
switch (CallbackId)
|
||||
{
|
||||
case HAL_SRAM_MSP_INIT_CB_ID :
|
||||
hsram->MspInitCallback = pCallback;
|
||||
break;
|
||||
case HAL_SRAM_MSP_DEINIT_CB_ID :
|
||||
hsram->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
case HAL_SRAM_MSP_INIT_CB_ID :
|
||||
hsram->MspInitCallback = pCallback;
|
||||
break;
|
||||
case HAL_SRAM_MSP_DEINIT_CB_ID :
|
||||
hsram->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
|
@ -789,7 +800,7 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM
|
|||
* @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
|
||||
* @retval status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
|
||||
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
HAL_SRAM_StateTypeDef state;
|
||||
|
@ -798,42 +809,42 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SR
|
|||
__HAL_LOCK(hsram);
|
||||
|
||||
state = hsram->State;
|
||||
if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
|
||||
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
|
||||
{
|
||||
switch (CallbackId)
|
||||
{
|
||||
case HAL_SRAM_MSP_INIT_CB_ID :
|
||||
hsram->MspInitCallback = HAL_SRAM_MspInit;
|
||||
break;
|
||||
case HAL_SRAM_MSP_DEINIT_CB_ID :
|
||||
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
|
||||
break;
|
||||
case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
|
||||
hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
|
||||
break;
|
||||
case HAL_SRAM_DMA_XFER_ERR_CB_ID :
|
||||
hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
case HAL_SRAM_MSP_INIT_CB_ID :
|
||||
hsram->MspInitCallback = HAL_SRAM_MspInit;
|
||||
break;
|
||||
case HAL_SRAM_MSP_DEINIT_CB_ID :
|
||||
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
|
||||
break;
|
||||
case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
|
||||
hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
|
||||
break;
|
||||
case HAL_SRAM_DMA_XFER_ERR_CB_ID :
|
||||
hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if(state == HAL_SRAM_STATE_RESET)
|
||||
else if (state == HAL_SRAM_STATE_RESET)
|
||||
{
|
||||
switch (CallbackId)
|
||||
{
|
||||
case HAL_SRAM_MSP_INIT_CB_ID :
|
||||
hsram->MspInitCallback = HAL_SRAM_MspInit;
|
||||
break;
|
||||
case HAL_SRAM_MSP_DEINIT_CB_ID :
|
||||
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
case HAL_SRAM_MSP_INIT_CB_ID :
|
||||
hsram->MspInitCallback = HAL_SRAM_MspInit;
|
||||
break;
|
||||
case HAL_SRAM_MSP_DEINIT_CB_ID :
|
||||
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
|
@ -858,12 +869,13 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SR
|
|||
* @param pCallback : pointer to the Callback function
|
||||
* @retval status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
|
||||
pSRAM_DmaCallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
HAL_SRAM_StateTypeDef state;
|
||||
|
||||
if(pCallback == NULL)
|
||||
if (pCallback == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
@ -872,20 +884,20 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR
|
|||
__HAL_LOCK(hsram);
|
||||
|
||||
state = hsram->State;
|
||||
if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
|
||||
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
|
||||
{
|
||||
switch (CallbackId)
|
||||
{
|
||||
case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
|
||||
hsram->DmaXferCpltCallback = pCallback;
|
||||
break;
|
||||
case HAL_SRAM_DMA_XFER_ERR_CB_ID :
|
||||
hsram->DmaXferErrorCallback = pCallback;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
|
||||
hsram->DmaXferCpltCallback = pCallback;
|
||||
break;
|
||||
case HAL_SRAM_DMA_XFER_ERR_CB_ID :
|
||||
hsram->DmaXferErrorCallback = pCallback;
|
||||
break;
|
||||
default :
|
||||
/* update return status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
|
@ -905,8 +917,8 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR
|
|||
*/
|
||||
|
||||
/** @defgroup SRAM_Exported_Functions_Group3 Control functions
|
||||
* @brief Control functions
|
||||
*
|
||||
* @brief Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### SRAM Control functions #####
|
||||
|
@ -928,7 +940,7 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR
|
|||
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
|
||||
{
|
||||
/* Check the SRAM controller state */
|
||||
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||
if (hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
@ -962,7 +974,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
|
|||
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
|
||||
{
|
||||
/* Check the SRAM controller state */
|
||||
if(hsram->State == HAL_SRAM_STATE_READY)
|
||||
if (hsram->State == HAL_SRAM_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
@ -992,8 +1004,8 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
|
|||
*/
|
||||
|
||||
/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### SRAM State functions #####
|
||||
|
@ -1035,7 +1047,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
|
|||
*/
|
||||
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
|
||||
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
|
||||
|
||||
/* Disable the DMA channel */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
@ -1057,7 +1069,7 @@ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
|
|||
*/
|
||||
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
|
||||
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
|
||||
|
||||
/* Disable the DMA channel */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
@ -1079,7 +1091,7 @@ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
|
|||
*/
|
||||
static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
|
||||
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
|
||||
|
||||
/* Disable the DMA channel */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -54,7 +54,7 @@
|
|||
the commutation event).
|
||||
|
||||
(#) Activate the TIM peripheral using one of the start functions:
|
||||
(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
|
||||
(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
|
||||
(++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
|
||||
(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
|
||||
(++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
|
||||
|
@ -90,9 +90,11 @@
|
|||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
|
||||
static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
|
||||
static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
@ -123,6 +125,9 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha
|
|||
*/
|
||||
/**
|
||||
* @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
|
||||
* @note When the timer instance is initialized in Hall Sensor Interface mode,
|
||||
* timer channels 1 and channel 2 are reserved and cannot be used for
|
||||
* other purpose.
|
||||
* @param htim TIM Hall Sensor Interface handle
|
||||
* @param sConfig TIM Hall Sensor configuration structure
|
||||
* @retval HAL status
|
||||
|
@ -208,6 +213,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
|
|||
htim->Instance->CR2 &= ~TIM_CR2_MMS;
|
||||
htim->Instance->CR2 |= TIM_TRGO_OC2REF;
|
||||
|
||||
/* Initialize the DMA burst operation state */
|
||||
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
||||
|
||||
/* Initialize the TIM channels state */
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
||||
|
||||
/* Initialize the TIM state*/
|
||||
htim->State = HAL_TIM_STATE_READY;
|
||||
|
||||
|
@ -241,6 +255,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
|
|||
HAL_TIMEx_HallSensor_MspDeInit(htim);
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
|
||||
/* Change the DMA burst operation state */
|
||||
htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
|
||||
|
||||
/* Change the TIM channels state */
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
|
||||
|
||||
/* Change TIM state */
|
||||
htim->State = HAL_TIM_STATE_RESET;
|
||||
|
||||
|
@ -288,17 +311,43 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
|
|||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
|
||||
{
|
||||
uint32_t tmpsmcr;
|
||||
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
|
||||
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
|
||||
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
|
||||
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
|
||||
|
||||
/* Check the TIM channels state */
|
||||
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Set the TIM channels state */
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
|
||||
/* Enable the Input Capture channel 1
|
||||
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
||||
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
||||
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
||||
|
||||
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
||||
{
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
|
@ -324,6 +373,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
|
|||
/* Disable the Peripheral */
|
||||
__HAL_TIM_DISABLE(htim);
|
||||
|
||||
/* Set the TIM channels state */
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
@ -336,10 +391,29 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
|
|||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
|
||||
{
|
||||
uint32_t tmpsmcr;
|
||||
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
|
||||
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
|
||||
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
|
||||
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
|
||||
|
||||
/* Check the TIM channels state */
|
||||
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Set the TIM channels state */
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
|
||||
/* Enable the capture compare Interrupts 1 event */
|
||||
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
||||
|
||||
|
@ -348,8 +422,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
|
|||
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
||||
|
||||
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
||||
{
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
|
@ -378,6 +459,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
|
|||
/* Disable the Peripheral */
|
||||
__HAL_TIM_DISABLE(htim);
|
||||
|
||||
/* Set the TIM channels state */
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
@ -392,29 +479,36 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
|
|||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
|
||||
{
|
||||
uint32_t tmpsmcr;
|
||||
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
|
||||
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
|
||||
|
||||
if (htim->State == HAL_TIM_STATE_BUSY)
|
||||
/* Set the TIM channel state */
|
||||
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
|
||||
|| (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
else if (htim->State == HAL_TIM_STATE_READY)
|
||||
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
|
||||
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
|
||||
{
|
||||
if (((uint32_t)pData == 0U) && (Length > 0U))
|
||||
if ((pData == NULL) && (Length > 0U))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
htim->State = HAL_TIM_STATE_BUSY;
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* nothing to do */
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Enable the Input Capture channel 1
|
||||
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
||||
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
||||
|
@ -428,14 +522,22 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
|
|||
/* Enable the DMA channel for Capture 1*/
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Enable the capture compare 1 Interrupt */
|
||||
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
|
||||
|
||||
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
||||
{
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
|
@ -463,9 +565,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
|
|||
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
|
||||
|
||||
(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_TIM_DISABLE(htim);
|
||||
|
||||
/* Set the TIM channel state */
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
@ -512,6 +619,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
||||
|
||||
/* Check the TIM complementary channel state */
|
||||
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Set the TIM complementary channel state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
|
||||
/* Enable the Capture compare channel N */
|
||||
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
|
||||
|
||||
|
@ -519,8 +635,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|||
__HAL_TIM_MOE_ENABLE(htim);
|
||||
|
||||
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
||||
{
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
|
@ -554,6 +677,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|||
/* Disable the Peripheral */
|
||||
__HAL_TIM_DISABLE(htim);
|
||||
|
||||
/* Set the TIM complementary channel state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
@ -576,6 +702,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
|
|||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
||||
|
||||
/* Check the TIM complementary channel state */
|
||||
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Set the TIM complementary channel state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
|
||||
switch (Channel)
|
||||
{
|
||||
case TIM_CHANNEL_1:
|
||||
|
@ -614,8 +749,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
|
|||
__HAL_TIM_MOE_ENABLE(htim);
|
||||
|
||||
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
||||
{
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
|
@ -684,6 +826,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
|
|||
/* Disable the Peripheral */
|
||||
__HAL_TIM_DISABLE(htim);
|
||||
|
||||
/* Set the TIM complementary channel state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
@ -708,24 +853,25 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
|
|||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
||||
|
||||
if (htim->State == HAL_TIM_STATE_BUSY)
|
||||
/* Set the TIM complementary channel state */
|
||||
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
else if (htim->State == HAL_TIM_STATE_READY)
|
||||
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
|
||||
{
|
||||
if (((uint32_t)pData == 0U) && (Length > 0U))
|
||||
if ((pData == NULL) && (Length > 0U))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
htim->State = HAL_TIM_STATE_BUSY;
|
||||
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* nothing to do */
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
switch (Channel)
|
||||
|
@ -733,15 +879,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
|
|||
case TIM_CHANNEL_1:
|
||||
{
|
||||
/* Set the DMA compare callbacks */
|
||||
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
||||
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
|
||||
htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
||||
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Enable the TIM Output Compare DMA request */
|
||||
|
@ -752,15 +899,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
|
|||
case TIM_CHANNEL_2:
|
||||
{
|
||||
/* Set the DMA compare callbacks */
|
||||
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
||||
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
|
||||
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
||||
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Enable the TIM Output Compare DMA request */
|
||||
|
@ -771,15 +919,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
|
|||
case TIM_CHANNEL_3:
|
||||
{
|
||||
/* Set the DMA compare callbacks */
|
||||
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
||||
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
|
||||
htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
||||
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Enable the TIM Output Compare DMA request */
|
||||
|
@ -798,8 +947,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
|
|||
__HAL_TIM_MOE_ENABLE(htim);
|
||||
|
||||
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
||||
{
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
|
@ -863,8 +1019,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
|
|||
/* Disable the Peripheral */
|
||||
__HAL_TIM_DISABLE(htim);
|
||||
|
||||
/* Change the htim state */
|
||||
htim->State = HAL_TIM_STATE_READY;
|
||||
/* Set the TIM complementary channel state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
@ -921,6 +1077,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
|
|||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
||||
|
||||
/* Check the TIM complementary channel state */
|
||||
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Set the TIM complementary channel state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
|
||||
/* Enable the complementary PWM output */
|
||||
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
|
||||
|
||||
|
@ -928,8 +1093,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
|
|||
__HAL_TIM_MOE_ENABLE(htim);
|
||||
|
||||
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
||||
{
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
|
@ -962,6 +1134,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|||
/* Disable the Peripheral */
|
||||
__HAL_TIM_DISABLE(htim);
|
||||
|
||||
/* Set the TIM complementary channel state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
@ -984,6 +1159,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
|
|||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
||||
|
||||
/* Check the TIM complementary channel state */
|
||||
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Set the TIM complementary channel state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
|
||||
switch (Channel)
|
||||
{
|
||||
case TIM_CHANNEL_1:
|
||||
|
@ -1021,8 +1205,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
|
|||
__HAL_TIM_MOE_ENABLE(htim);
|
||||
|
||||
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
||||
{
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
|
@ -1092,6 +1283,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
|
|||
/* Disable the Peripheral */
|
||||
__HAL_TIM_DISABLE(htim);
|
||||
|
||||
/* Set the TIM complementary channel state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
@ -1116,39 +1310,42 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
|
|||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
||||
|
||||
if (htim->State == HAL_TIM_STATE_BUSY)
|
||||
/* Set the TIM complementary channel state */
|
||||
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
else if (htim->State == HAL_TIM_STATE_READY)
|
||||
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
|
||||
{
|
||||
if (((uint32_t)pData == 0U) && (Length > 0U))
|
||||
if ((pData == NULL) && (Length > 0U))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
htim->State = HAL_TIM_STATE_BUSY;
|
||||
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* nothing to do */
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
switch (Channel)
|
||||
{
|
||||
case TIM_CHANNEL_1:
|
||||
{
|
||||
/* Set the DMA compare callbacks */
|
||||
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
||||
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
|
||||
htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
||||
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Enable the TIM Capture/Compare 1 DMA request */
|
||||
|
@ -1159,15 +1356,16 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
|
|||
case TIM_CHANNEL_2:
|
||||
{
|
||||
/* Set the DMA compare callbacks */
|
||||
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
||||
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
|
||||
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
||||
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Enable the TIM Capture/Compare 2 DMA request */
|
||||
|
@ -1178,15 +1376,16 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
|
|||
case TIM_CHANNEL_3:
|
||||
{
|
||||
/* Set the DMA compare callbacks */
|
||||
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
||||
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
|
||||
htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
||||
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Enable the TIM Capture/Compare 3 DMA request */
|
||||
|
@ -1205,8 +1404,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
|
|||
__HAL_TIM_MOE_ENABLE(htim);
|
||||
|
||||
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
||||
{
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
|
@ -1270,8 +1476,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
|
|||
/* Disable the Peripheral */
|
||||
__HAL_TIM_DISABLE(htim);
|
||||
|
||||
/* Change the htim state */
|
||||
htim->State = HAL_TIM_STATE_READY;
|
||||
/* Set the TIM complementary channel state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
@ -1311,11 +1517,27 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
||||
{
|
||||
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
|
||||
HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
|
||||
HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
|
||||
|
||||
/* Enable the complementary One Pulse output */
|
||||
/* Check the TIM channels state */
|
||||
if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
|| (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Set the TIM channels state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
|
||||
/* Enable the complementary One Pulse output channel and the Input Capture channel */
|
||||
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
|
||||
TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
|
||||
|
||||
/* Enable the Main Output */
|
||||
__HAL_TIM_MOE_ENABLE(htim);
|
||||
|
@ -1336,12 +1558,14 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
||||
{
|
||||
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
|
||||
|
||||
/* Disable the complementary One Pulse output */
|
||||
/* Disable the complementary One Pulse output channel and the Input Capture channel */
|
||||
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
|
||||
TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
|
||||
|
||||
/* Disable the Main Output */
|
||||
__HAL_TIM_MOE_DISABLE(htim);
|
||||
|
@ -1349,6 +1573,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
|
|||
/* Disable the Peripheral */
|
||||
__HAL_TIM_DISABLE(htim);
|
||||
|
||||
/* Set the TIM channels state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
@ -1365,17 +1593,33 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
||||
{
|
||||
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
|
||||
HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
|
||||
HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
|
||||
|
||||
/* Check the TIM channels state */
|
||||
if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
|| (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Set the TIM channels state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
|
||||
/* Enable the TIM Capture/Compare 1 interrupt */
|
||||
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
||||
|
||||
/* Enable the TIM Capture/Compare 2 interrupt */
|
||||
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
||||
|
||||
/* Enable the complementary One Pulse output */
|
||||
/* Enable the complementary One Pulse output channel and the Input Capture channel */
|
||||
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
|
||||
TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
|
||||
|
||||
/* Enable the Main Output */
|
||||
__HAL_TIM_MOE_ENABLE(htim);
|
||||
|
@ -1396,6 +1640,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
||||
{
|
||||
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
|
||||
|
||||
|
@ -1405,8 +1651,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
|
|||
/* Disable the TIM Capture/Compare 2 interrupt */
|
||||
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
||||
|
||||
/* Disable the complementary One Pulse output */
|
||||
/* Disable the complementary One Pulse output channel and the Input Capture channel */
|
||||
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
|
||||
TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
|
||||
|
||||
/* Disable the Main Output */
|
||||
__HAL_TIM_MOE_DISABLE(htim);
|
||||
|
@ -1414,6 +1661,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
|
|||
/* Disable the Peripheral */
|
||||
__HAL_TIM_DISABLE(htim);
|
||||
|
||||
/* Set the TIM channels state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
@ -1633,7 +1884,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|||
uint32_t tmpsmcr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
|
||||
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
||||
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
||||
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
||||
|
||||
|
@ -1654,16 +1905,19 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|||
/* Select the TRGO source */
|
||||
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
||||
|
||||
/* Reset the MSM Bit */
|
||||
tmpsmcr &= ~TIM_SMCR_MSM;
|
||||
/* Set master mode */
|
||||
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
||||
|
||||
/* Update TIMx CR2 */
|
||||
htim->Instance->CR2 = tmpcr2;
|
||||
|
||||
/* Update TIMx SMCR */
|
||||
htim->Instance->SMCR = tmpsmcr;
|
||||
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
||||
{
|
||||
/* Reset the MSM Bit */
|
||||
tmpsmcr &= ~TIM_SMCR_MSM;
|
||||
/* Set master mode */
|
||||
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
||||
|
||||
/* Update TIMx SMCR */
|
||||
htim->Instance->SMCR = tmpsmcr;
|
||||
}
|
||||
|
||||
/* Change the htim state */
|
||||
htim->State = HAL_TIM_STATE_READY;
|
||||
|
@ -1733,6 +1987,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(htim);
|
||||
UNUSED(Remap);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
@ -1829,6 +2086,27 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
|
|||
return htim->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return actual state of the TIM complementary channel.
|
||||
* @param htim TIM handle
|
||||
* @param ChannelN TIM Complementary channel
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2
|
||||
* @arg TIM_CHANNEL_3: TIM Channel 3
|
||||
* @retval TIM Complementary channel state
|
||||
*/
|
||||
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
|
||||
{
|
||||
HAL_TIM_ChannelStateTypeDef channel_state;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
|
||||
|
||||
channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
|
||||
|
||||
return channel_state;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
@ -1881,6 +2159,103 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
|
|||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief TIM DMA Delay Pulse complete callback (complementary channel).
|
||||
* @param hdma pointer to DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
||||
|
||||
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* nothing to do */
|
||||
}
|
||||
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->PWM_PulseFinishedCallback(htim);
|
||||
#else
|
||||
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief TIM DMA error callback (complementary channel)
|
||||
* @param hdma pointer to DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
||||
|
||||
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* nothing to do */
|
||||
}
|
||||
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->ErrorCallback(htim);
|
||||
#else
|
||||
HAL_TIM_ErrorCallback(htim);
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the TIM Capture Compare Channel xN.
|
||||
* @param TIMx to select the TIM peripheral
|
||||
|
|
|
@ -1026,7 +1026,8 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
{
|
||||
uint16_t *tmp;
|
||||
uint8_t *pdata8bits;
|
||||
uint16_t *pdata16bits;
|
||||
uint32_t tickstart = 0U;
|
||||
|
||||
/* Check that a Tx process is not already ongoing */
|
||||
|
@ -1048,34 +1049,39 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
|
|||
|
||||
huart->TxXferSize = Size;
|
||||
huart->TxXferCount = Size;
|
||||
|
||||
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
|
||||
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
||||
{
|
||||
pdata8bits = NULL;
|
||||
pdata16bits = (uint16_t *) pData;
|
||||
}
|
||||
else
|
||||
{
|
||||
pdata8bits = pData;
|
||||
pdata16bits = NULL;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
while (huart->TxXferCount > 0U)
|
||||
{
|
||||
huart->TxXferCount--;
|
||||
if (huart->Init.WordLength == UART_WORDLENGTH_9B)
|
||||
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
|
||||
{
|
||||
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
tmp = (uint16_t *) pData;
|
||||
huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
|
||||
if (huart->Init.Parity == UART_PARITY_NONE)
|
||||
{
|
||||
pData += 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
pData += 1U;
|
||||
}
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
if (pdata8bits == NULL)
|
||||
{
|
||||
huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
|
||||
pdata16bits++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
|
||||
huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
|
||||
pdata8bits++;
|
||||
}
|
||||
huart->TxXferCount--;
|
||||
}
|
||||
|
||||
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
|
||||
|
@ -1086,9 +1092,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
|
|||
/* At end of Tx process, restore huart->gState to Ready */
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
|
@ -1111,7 +1114,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
{
|
||||
uint16_t *tmp;
|
||||
uint8_t *pdata8bits;
|
||||
uint16_t *pdata16bits;
|
||||
uint32_t tickstart = 0U;
|
||||
|
||||
/* Check that a Rx process is not already ongoing */
|
||||
|
@ -1134,53 +1138,51 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
|
|||
huart->RxXferSize = Size;
|
||||
huart->RxXferCount = Size;
|
||||
|
||||
/* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
|
||||
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
||||
{
|
||||
pdata8bits = NULL;
|
||||
pdata16bits = (uint16_t *) pData;
|
||||
}
|
||||
else
|
||||
{
|
||||
pdata8bits = pData;
|
||||
pdata16bits = NULL;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
/* Check the remain data to be received */
|
||||
while (huart->RxXferCount > 0U)
|
||||
{
|
||||
huart->RxXferCount--;
|
||||
if (huart->Init.WordLength == UART_WORDLENGTH_9B)
|
||||
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
|
||||
{
|
||||
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
tmp = (uint16_t *) pData;
|
||||
if (huart->Init.Parity == UART_PARITY_NONE)
|
||||
{
|
||||
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
|
||||
pData += 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
|
||||
pData += 1U;
|
||||
}
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
if (pdata8bits == NULL)
|
||||
{
|
||||
*pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF);
|
||||
pdata16bits++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
|
||||
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
if (huart->Init.Parity == UART_PARITY_NONE)
|
||||
{
|
||||
*pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
|
||||
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
|
||||
}
|
||||
else
|
||||
{
|
||||
*pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
|
||||
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
|
||||
}
|
||||
|
||||
pdata8bits++;
|
||||
}
|
||||
huart->RxXferCount--;
|
||||
}
|
||||
|
||||
/* At end of Rx process, restore huart->RxState to Ready */
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
|
@ -2060,7 +2062,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|||
}
|
||||
|
||||
/* UART Over-Run interrupt occurred --------------------------------------*/
|
||||
if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
|
||||
if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
|
||||
{
|
||||
huart->ErrorCode |= HAL_UART_ERROR_ORE;
|
||||
}
|
||||
|
@ -2924,18 +2926,11 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
|
|||
/* Check that a Tx process is ongoing */
|
||||
if (huart->gState == HAL_UART_STATE_BUSY_TX)
|
||||
{
|
||||
if (huart->Init.WordLength == UART_WORDLENGTH_9B)
|
||||
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
||||
{
|
||||
tmp = (uint16_t *) huart->pTxBuffPtr;
|
||||
huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
|
||||
if (huart->Init.Parity == UART_PARITY_NONE)
|
||||
{
|
||||
huart->pTxBuffPtr += 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
huart->pTxBuffPtr += 1U;
|
||||
}
|
||||
huart->pTxBuffPtr += 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -2991,35 +2986,33 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
|
|||
*/
|
||||
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
|
||||
{
|
||||
uint16_t *tmp;
|
||||
uint8_t *pdata8bits;
|
||||
uint16_t *pdata16bits;
|
||||
|
||||
/* Check that a Rx process is ongoing */
|
||||
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
||||
{
|
||||
if (huart->Init.WordLength == UART_WORDLENGTH_9B)
|
||||
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
||||
{
|
||||
tmp = (uint16_t *) huart->pRxBuffPtr;
|
||||
if (huart->Init.Parity == UART_PARITY_NONE)
|
||||
{
|
||||
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
|
||||
huart->pRxBuffPtr += 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
|
||||
huart->pRxBuffPtr += 1U;
|
||||
}
|
||||
pdata8bits = NULL;
|
||||
pdata16bits = (uint16_t *) huart->pRxBuffPtr;
|
||||
*pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
|
||||
huart->pRxBuffPtr += 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (huart->Init.Parity == UART_PARITY_NONE)
|
||||
pdata8bits = (uint8_t *) huart->pRxBuffPtr;
|
||||
pdata16bits = NULL;
|
||||
|
||||
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
|
||||
{
|
||||
*huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
|
||||
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
|
||||
}
|
||||
else
|
||||
{
|
||||
*huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
|
||||
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
|
||||
}
|
||||
huart->pRxBuffPtr += 1U;
|
||||
}
|
||||
|
||||
if (--huart->RxXferCount == 0U)
|
||||
|
@ -3099,48 +3092,28 @@ static void UART_SetConfig(UART_HandleTypeDef *huart)
|
|||
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
|
||||
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
|
||||
|
||||
#if defined(USART_CR1_OVER8)
|
||||
/* Check the Over Sampling */
|
||||
if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
||||
{
|
||||
/*-------------------------- USART BRR Configuration ---------------------*/
|
||||
if(huart->Instance == USART1)
|
||||
{
|
||||
pclk = HAL_RCC_GetPCLK2Freq();
|
||||
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
|
||||
}
|
||||
else
|
||||
{
|
||||
pclk = HAL_RCC_GetPCLK1Freq();
|
||||
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*-------------------------- USART BRR Configuration ---------------------*/
|
||||
if(huart->Instance == USART1)
|
||||
{
|
||||
pclk = HAL_RCC_GetPCLK2Freq();
|
||||
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
||||
}
|
||||
else
|
||||
{
|
||||
pclk = HAL_RCC_GetPCLK1Freq();
|
||||
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
||||
}
|
||||
}
|
||||
#else
|
||||
/*-------------------------- USART BRR Configuration ---------------------*/
|
||||
|
||||
if(huart->Instance == USART1)
|
||||
{
|
||||
pclk = HAL_RCC_GetPCLK2Freq();
|
||||
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
||||
}
|
||||
else
|
||||
{
|
||||
pclk = HAL_RCC_GetPCLK1Freq();
|
||||
}
|
||||
|
||||
/*-------------------------- USART BRR Configuration ---------------------*/
|
||||
#if defined(USART_CR1_OVER8)
|
||||
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
||||
{
|
||||
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
|
||||
}
|
||||
else
|
||||
{
|
||||
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
||||
}
|
||||
#else
|
||||
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
||||
#endif /* USART_CR1_OVER8 */
|
||||
}
|
||||
|
||||
|
|
|
@ -537,9 +537,9 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Unregister an UART Callback
|
||||
* UART callaback is redirected to the weak predefined callback
|
||||
* @param husart uart handle
|
||||
* @brief Unregister an USART Callback
|
||||
* USART callaback is redirected to the weak predefined callback
|
||||
* @param husart usart handle
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
|
||||
|
@ -731,7 +731,7 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
|
|||
|
||||
/**
|
||||
* @brief Simplex Send an amount of data in blocking mode.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the sent data is handled as a set of u16. In this case, Size must indicate the number
|
||||
* of u16 provided through pTxData.
|
||||
* @param husart Pointer to a USART_HandleTypeDef structure that contains
|
||||
|
@ -816,7 +816,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
|
|||
/**
|
||||
* @brief Full-Duplex Receive an amount of data in blocking mode.
|
||||
* @note To receive synchronous data, dummy data are simultaneously transmitted.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of u16. In this case, Size must indicate the number
|
||||
* of u16 available through pRxData.
|
||||
* @param husart Pointer to a USART_HandleTypeDef structure that contains
|
||||
|
@ -924,7 +924,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
|
|||
|
||||
/**
|
||||
* @brief Full-Duplex Send and Receive an amount of data in full-duplex mode (blocking mode).
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
|
||||
* of u16 available through pTxData and through pRxData.
|
||||
* @param husart Pointer to a USART_HandleTypeDef structure that contains
|
||||
|
@ -1042,7 +1042,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
|
|||
|
||||
/**
|
||||
* @brief Simplex Send an amount of data in non-blocking mode.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the sent data is handled as a set of u16. In this case, Size must indicate the number
|
||||
* of u16 provided through pTxData.
|
||||
* @param husart Pointer to a USART_HandleTypeDef structure that contains
|
||||
|
@ -1096,7 +1096,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
|
|||
/**
|
||||
* @brief Simplex Receive an amount of data in non-blocking mode.
|
||||
* @note To receive synchronous data, dummy data are simultaneously transmitted.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of u16. In this case, Size must indicate the number
|
||||
* of u16 available through pRxData.
|
||||
* @param husart Pointer to a USART_HandleTypeDef structure that contains
|
||||
|
@ -1145,7 +1145,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
|
|||
|
||||
/**
|
||||
* @brief Full-Duplex Send and Receive an amount of data in full-duplex mode (non-blocking).
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
|
||||
* of u16 available through pTxData and through pRxData.
|
||||
* @param husart Pointer to a USART_HandleTypeDef structure that contains
|
||||
|
@ -1201,7 +1201,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
|
|||
|
||||
/**
|
||||
* @brief Simplex Send an amount of data in DMA mode.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the sent data is handled as a set of u16. In this case, Size must indicate the number
|
||||
* of u16 provided through pTxData.
|
||||
* @param husart Pointer to a USART_HandleTypeDef structure that contains
|
||||
|
@ -1266,7 +1266,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
|
|||
|
||||
/**
|
||||
* @brief Full-Duplex Receive an amount of data in DMA mode.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of u16. In this case, Size must indicate the number
|
||||
* of u16 available through pRxData.
|
||||
* @param husart Pointer to a USART_HandleTypeDef structure that contains
|
||||
|
@ -1361,7 +1361,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
|
|||
|
||||
/**
|
||||
* @brief Full-Duplex Transmit Receive an amount of data in DMA mode.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
|
||||
* of u16 available through pTxData and through pRxData.
|
||||
* @param husart Pointer to a USART_HandleTypeDef structure that contains
|
||||
|
@ -1789,7 +1789,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
|
|||
}
|
||||
|
||||
/* USART Over-Run interrupt occurred -----------------------------------*/
|
||||
if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
|
||||
if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
|
||||
{
|
||||
husart->ErrorCode |= HAL_USART_ERROR_ORE;
|
||||
}
|
||||
|
@ -2155,8 +2155,6 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
|
|||
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
|
||||
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
|
||||
|
||||
husart->State = HAL_USART_STATE_READY;
|
||||
|
||||
/* The USART state is HAL_USART_STATE_BUSY_RX */
|
||||
if (husart->State == HAL_USART_STATE_BUSY_RX)
|
||||
{
|
||||
|
@ -2179,6 +2177,7 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
|
|||
HAL_USART_TxRxCpltCallback(husart);
|
||||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
|
||||
}
|
||||
husart->State = HAL_USART_STATE_READY;
|
||||
}
|
||||
/* DMA circular mode */
|
||||
else
|
||||
|
|
|
@ -65,7 +65,7 @@
|
|||
* @brief FSMC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
|
@ -203,9 +203,12 @@
|
|||
* @param Init Pointer to NORSRAM Initialization structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init)
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
|
||||
FSMC_NORSRAM_InitTypeDef *Init)
|
||||
{
|
||||
uint32_t flashaccess;
|
||||
uint32_t btcr_reg;
|
||||
uint32_t mask;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
|
||||
|
@ -237,36 +240,40 @@ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_
|
|||
flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE;
|
||||
}
|
||||
|
||||
MODIFY_REG(Device->BTCR[Init->NSBank],
|
||||
(FSMC_BCRx_MBKEN |
|
||||
FSMC_BCRx_MUXEN |
|
||||
FSMC_BCRx_MTYP |
|
||||
FSMC_BCRx_MWID |
|
||||
FSMC_BCRx_FACCEN |
|
||||
FSMC_BCRx_BURSTEN |
|
||||
FSMC_BCRx_WAITPOL |
|
||||
FSMC_BCRx_WRAPMOD |
|
||||
FSMC_BCRx_WAITCFG |
|
||||
FSMC_BCRx_WREN |
|
||||
FSMC_BCRx_WAITEN |
|
||||
FSMC_BCRx_EXTMOD |
|
||||
FSMC_BCRx_ASYNCWAIT |
|
||||
FSMC_BCRx_CBURSTRW |
|
||||
0x00070000U), /* CPSIZE to be defined in CMSIS file */
|
||||
(flashaccess |
|
||||
Init->DataAddressMux |
|
||||
Init->MemoryType |
|
||||
Init->MemoryDataWidth |
|
||||
Init->BurstAccessMode |
|
||||
Init->WaitSignalPolarity |
|
||||
Init->WrapMode |
|
||||
Init->WaitSignalActive |
|
||||
Init->WriteOperation |
|
||||
Init->WaitSignal |
|
||||
Init->ExtendedMode |
|
||||
Init->AsynchronousWait |
|
||||
Init->WriteBurst |
|
||||
Init->PageSize));
|
||||
btcr_reg = (flashaccess | \
|
||||
Init->DataAddressMux | \
|
||||
Init->MemoryType | \
|
||||
Init->MemoryDataWidth | \
|
||||
Init->BurstAccessMode | \
|
||||
Init->WaitSignalPolarity | \
|
||||
Init->WaitSignalActive | \
|
||||
Init->WriteOperation | \
|
||||
Init->WaitSignal | \
|
||||
Init->ExtendedMode | \
|
||||
Init->AsynchronousWait | \
|
||||
Init->WriteBurst);
|
||||
|
||||
btcr_reg |= Init->WrapMode;
|
||||
btcr_reg |= Init->PageSize;
|
||||
|
||||
mask = (FSMC_BCRx_MBKEN |
|
||||
FSMC_BCRx_MUXEN |
|
||||
FSMC_BCRx_MTYP |
|
||||
FSMC_BCRx_MWID |
|
||||
FSMC_BCRx_FACCEN |
|
||||
FSMC_BCRx_BURSTEN |
|
||||
FSMC_BCRx_WAITPOL |
|
||||
FSMC_BCRx_WAITCFG |
|
||||
FSMC_BCRx_WREN |
|
||||
FSMC_BCRx_WAITEN |
|
||||
FSMC_BCRx_EXTMOD |
|
||||
FSMC_BCRx_ASYNCWAIT |
|
||||
FSMC_BCRx_CBURSTRW);
|
||||
|
||||
mask |= FSMC_BCRx_WRAPMOD;
|
||||
mask |= 0x00070000U; /* CPSIZE to be defined in CMSIS file */
|
||||
|
||||
MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
|
||||
|
||||
|
||||
return HAL_OK;
|
||||
|
@ -279,7 +286,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_
|
|||
* @param Bank NORSRAM bank number
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
|
||||
FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
|
||||
|
@ -315,7 +323,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM
|
|||
* @param Bank NORSRAM bank number
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
|
||||
FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
|
||||
{
|
||||
|
||||
/* Check the parameters */
|
||||
|
@ -331,12 +340,12 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NO
|
|||
|
||||
/* Set FSMC_NORSRAM device timing parameters */
|
||||
MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
|
||||
((Timing->AddressHoldTime) << FSMC_BTRx_ADDHLD_Pos) |
|
||||
((Timing->DataSetupTime) << FSMC_BTRx_DATAST_Pos) |
|
||||
((Timing->BusTurnAroundDuration) << FSMC_BTRx_BUSTURN_Pos) |
|
||||
(((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) |
|
||||
(((Timing->DataLatency) - 2U) << FSMC_BTRx_DATLAT_Pos) |
|
||||
(Timing->AccessMode)));
|
||||
((Timing->AddressHoldTime) << FSMC_BTRx_ADDHLD_Pos) |
|
||||
((Timing->DataSetupTime) << FSMC_BTRx_DATAST_Pos) |
|
||||
((Timing->BusTurnAroundDuration) << FSMC_BTRx_BUSTURN_Pos) |
|
||||
(((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) |
|
||||
(((Timing->DataLatency) - 2U) << FSMC_BTRx_DATLAT_Pos) |
|
||||
(Timing->AccessMode)));
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
@ -353,7 +362,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NO
|
|||
* @arg FSMC_EXTENDED_MODE_ENABLE
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
|
||||
FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
|
||||
|
@ -403,8 +413,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDe
|
|||
*/
|
||||
|
||||
/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
|
||||
* @brief management functions
|
||||
*
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### FSMC_NORSRAM Control functions #####
|
||||
|
@ -490,8 +500,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi
|
|||
*/
|
||||
|
||||
/** @defgroup FSMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de_initialization functions #####
|
||||
|
@ -560,7 +570,8 @@ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDe
|
|||
* @param Bank NAND bank number
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
|
||||
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
|
||||
FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_NAND_DEVICE(Device));
|
||||
|
@ -599,7 +610,8 @@ HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, F
|
|||
* @param Bank NAND bank number
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
|
||||
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
|
||||
FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_NAND_DEVICE(Device));
|
||||
|
@ -746,7 +758,8 @@ HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank
|
|||
* @param Timeout Timeout wait value
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
|
||||
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
|
@ -869,7 +882,8 @@ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_Init
|
|||
* @param Timing Pointer to PCCARD timing structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
|
||||
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
|
||||
FSMC_NAND_PCC_TimingTypeDef *Timing)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
|
||||
|
@ -895,7 +909,8 @@ HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Devic
|
|||
* @param Timing Pointer to PCCARD timing structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
|
||||
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
|
||||
FSMC_NAND_PCC_TimingTypeDef *Timing)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
|
||||
|
@ -921,7 +936,8 @@ HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *De
|
|||
* @param Timing Pointer to PCCARD timing structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
|
||||
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
|
||||
FSMC_NAND_PCC_TimingTypeDef *Timing)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
|
||||
|
@ -981,5 +997,8 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
@ -189,12 +189,6 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
|
|||
assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
|
||||
assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
|
||||
|
||||
/* Pin Mode configuration */
|
||||
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
|
||||
|
||||
/* Pull-up Pull-down resistor configuration*/
|
||||
LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
|
||||
|
||||
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
|
||||
{
|
||||
/* Check speed and Output mode parameters */
|
||||
|
@ -207,6 +201,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
|
|||
/* Output mode configuration*/
|
||||
LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType);
|
||||
}
|
||||
|
||||
/* Pull-up Pull-down resistor configuration*/
|
||||
LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
|
||||
|
||||
/* Pin Mode configuration */
|
||||
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
|
||||
}
|
||||
pinpos++;
|
||||
}
|
||||
|
|
|
@ -310,7 +310,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
|
|||
TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
|
||||
TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
|
||||
TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
|
||||
TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
|
||||
TIM_InitStruct->RepetitionCounter = 0x00000000U;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -243,6 +243,77 @@ void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
|
|||
SystemCoreClock = HCLKFrequency;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update number of Flash wait states in line with new frequency and current
|
||||
voltage range.
|
||||
* @param Frequency SYSCLK frequency
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Latency has been modified
|
||||
* - ERROR: Latency cannot be modified
|
||||
*/
|
||||
#if defined(FLASH_ACR_LATENCY)
|
||||
ErrorStatus LL_SetFlashLatency(uint32_t Frequency)
|
||||
{
|
||||
uint32_t timeout;
|
||||
uint32_t getlatency;
|
||||
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Frequency cannot be equal to 0 */
|
||||
if (Frequency == 0U)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (Frequency > UTILS_LATENCY2_FREQ)
|
||||
{
|
||||
/* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
|
||||
latency = LL_FLASH_LATENCY_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (Frequency > UTILS_LATENCY1_FREQ)
|
||||
{
|
||||
/* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
|
||||
latency = LL_FLASH_LATENCY_1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
|
||||
latency = LL_FLASH_LATENCY_0;
|
||||
}
|
||||
}
|
||||
|
||||
if (status != ERROR)
|
||||
{
|
||||
LL_FLASH_SetLatency(latency);
|
||||
|
||||
/* Check that the new number of wait states is taken into account to access the Flash
|
||||
memory by reading the FLASH_ACR register */
|
||||
timeout = 2;
|
||||
do
|
||||
{
|
||||
/* Wait for Flash latency to be updated */
|
||||
getlatency = LL_FLASH_GetLatency();
|
||||
timeout--;
|
||||
} while ((getlatency != latency) && (timeout > 0));
|
||||
|
||||
if(getlatency != latency)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = SUCCESS;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
#endif /* FLASH_ACR_LATENCY */
|
||||
|
||||
/**
|
||||
* @brief This function configures system clock with HSI as clock source of the PLL
|
||||
* @note The application need to ensure that PLL is disabled.
|
||||
|
@ -379,56 +450,6 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa
|
|||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update number of Flash wait states in line with new frequency and current
|
||||
voltage range.
|
||||
* @param Frequency SYSCLK frequency
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Latency has been modified
|
||||
* - ERROR: Latency cannot be modified
|
||||
*/
|
||||
#if defined(FLASH_ACR_LATENCY)
|
||||
ErrorStatus LL_SetFlashLatency(uint32_t Frequency)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
|
||||
|
||||
/* Frequency cannot be equal to 0 */
|
||||
if (Frequency == 0U)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (Frequency > UTILS_LATENCY2_FREQ)
|
||||
{
|
||||
/* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
|
||||
latency = LL_FLASH_LATENCY_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (Frequency > UTILS_LATENCY1_FREQ)
|
||||
{
|
||||
/* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
|
||||
latency = LL_FLASH_LATENCY_1;
|
||||
}
|
||||
/* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
|
||||
}
|
||||
|
||||
LL_FLASH_SetLatency(latency);
|
||||
|
||||
/* Check that the new number of wait states is taken into account to access the Flash
|
||||
memory by reading the FLASH_ACR register */
|
||||
if (LL_FLASH_GetLatency() != latency)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
#endif /* FLASH_ACR_LATENCY */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -4880,7 +4880,6 @@ typedef struct
|
|||
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
|
||||
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Inter-integrated Circuit Interface */
|
||||
|
@ -5718,8 +5717,6 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
|
@ -5921,15 +5918,15 @@ typedef struct
|
|||
#define ADC1_2_IRQn ADC1_IRQn
|
||||
#define USBWakeUp_IRQn CEC_IRQn
|
||||
#define OTG_FS_WKUP_IRQn CEC_IRQn
|
||||
#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM10_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM6_IRQn TIM6_DAC_IRQn
|
||||
|
||||
|
||||
|
@ -5937,15 +5934,15 @@ typedef struct
|
|||
#define ADC1_2_IRQHandler ADC1_IRQHandler
|
||||
#define USBWakeUp_IRQHandler CEC_IRQHandler
|
||||
#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
|
||||
#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
|
||||
|
||||
|
||||
|
|
|
@ -5394,7 +5394,6 @@ typedef struct
|
|||
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
|
||||
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Inter-integrated Circuit Interface */
|
||||
|
@ -6283,8 +6282,6 @@ typedef struct
|
|||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
|
@ -6522,17 +6519,17 @@ typedef struct
|
|||
|
||||
/* Aliases for __IRQn */
|
||||
#define ADC1_2_IRQn ADC1_IRQn
|
||||
#define USBWakeUp_IRQn CEC_IRQn
|
||||
#define OTG_FS_WKUP_IRQn CEC_IRQn
|
||||
#define USBWakeUp_IRQn CEC_IRQn
|
||||
#define TIM8_BRK_IRQn TIM12_IRQn
|
||||
#define TIM8_BRK_TIM12_IRQn TIM12_IRQn
|
||||
#define TIM8_UP_TIM13_IRQn TIM13_IRQn
|
||||
#define TIM8_UP_IRQn TIM13_IRQn
|
||||
#define TIM8_TRG_COM_IRQn TIM14_IRQn
|
||||
#define TIM8_UP_TIM13_IRQn TIM13_IRQn
|
||||
#define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn
|
||||
#define TIM8_TRG_COM_IRQn TIM14_IRQn
|
||||
#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
|
@ -6544,17 +6541,17 @@ typedef struct
|
|||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_2_IRQHandler ADC1_IRQHandler
|
||||
#define USBWakeUp_IRQHandler CEC_IRQHandler
|
||||
#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
|
||||
#define USBWakeUp_IRQHandler CEC_IRQHandler
|
||||
#define TIM8_BRK_IRQHandler TIM12_IRQHandler
|
||||
#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler
|
||||
#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler
|
||||
#define TIM8_UP_IRQHandler TIM13_IRQHandler
|
||||
#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
|
||||
#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler
|
||||
#define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler
|
||||
#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
|
||||
#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
|
|
|
@ -4412,12 +4412,10 @@ typedef struct
|
|||
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
|
||||
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
|
||||
|
||||
/****************** Bit definition for SPI_I2SCFGR register *****************/
|
||||
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
|
||||
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
|
||||
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Inter-integrated Circuit Interface */
|
||||
|
@ -5170,8 +5168,6 @@ typedef struct
|
|||
(((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
|
|
|
@ -4474,12 +4474,10 @@ typedef struct
|
|||
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
|
||||
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
|
||||
|
||||
/****************** Bit definition for SPI_I2SCFGR register *****************/
|
||||
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
|
||||
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
|
||||
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Inter-integrated Circuit Interface */
|
||||
|
@ -5279,8 +5277,6 @@ typedef struct
|
|||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
|
|
|
@ -514,6 +514,7 @@ typedef struct
|
|||
__IO uint32_t RXCRCR;
|
||||
__IO uint32_t TXCRCR;
|
||||
__IO uint32_t I2SCFGR;
|
||||
__IO uint32_t I2SPR;
|
||||
} SPI_TypeDef;
|
||||
|
||||
/**
|
||||
|
@ -5283,6 +5284,10 @@ typedef struct
|
|||
/* Serial Peripheral Interface */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
|
||||
*/
|
||||
#define SPI_I2S_SUPPORT /*!< I2S support */
|
||||
#define SPI_CRC_ERROR_WORKAROUND_FEATURE
|
||||
|
||||
/******************* Bit definition for SPI_CR1 register ********************/
|
||||
|
@ -5401,10 +5406,52 @@ typedef struct
|
|||
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
|
||||
|
||||
/****************** Bit definition for SPI_I2SCFGR register *****************/
|
||||
#define SPI_I2SCFGR_CHLEN_Pos (0U)
|
||||
#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
|
||||
#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!< Channel length (number of bits per audio channel) */
|
||||
|
||||
#define SPI_I2SCFGR_DATLEN_Pos (1U)
|
||||
#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
|
||||
#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!< DATLEN[1:0] bits (Data length to be transferred) */
|
||||
#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
|
||||
#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define SPI_I2SCFGR_CKPOL_Pos (3U)
|
||||
#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
|
||||
#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!< steady state clock polarity */
|
||||
|
||||
#define SPI_I2SCFGR_I2SSTD_Pos (4U)
|
||||
#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
|
||||
#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!< I2SSTD[1:0] bits (I2S standard selection) */
|
||||
#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
|
||||
#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
|
||||
|
||||
#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
|
||||
#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
|
||||
#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!< PCM frame synchronization */
|
||||
|
||||
#define SPI_I2SCFGR_I2SCFG_Pos (8U)
|
||||
#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
|
||||
#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!< I2SCFG[1:0] bits (I2S configuration mode) */
|
||||
#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
|
||||
#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
|
||||
|
||||
#define SPI_I2SCFGR_I2SE_Pos (10U)
|
||||
#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
|
||||
#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!< I2S Enable */
|
||||
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
|
||||
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
|
||||
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
|
||||
|
||||
/****************** Bit definition for SPI_I2SPR register *******************/
|
||||
#define SPI_I2SPR_I2SDIV_Pos (0U)
|
||||
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
|
||||
#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!< I2S Linear prescaler */
|
||||
#define SPI_I2SPR_ODD_Pos (8U)
|
||||
#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
|
||||
#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!< Odd factor for the prescaler */
|
||||
#define SPI_I2SPR_MCKOE_Pos (9U)
|
||||
#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
|
||||
#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!< Master Clock Output Enable */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
@ -6153,6 +6200,10 @@ typedef struct
|
|||
/******************************* SMBUS Instances ******************************/
|
||||
#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
|
||||
|
||||
/******************************** I2S Instances *******************************/
|
||||
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
|
||||
((INSTANCE) == SPI3))
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
|
@ -6253,8 +6304,6 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5))
|
||||
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
|
|
|
@ -526,6 +526,7 @@ typedef struct
|
|||
__IO uint32_t RXCRCR;
|
||||
__IO uint32_t TXCRCR;
|
||||
__IO uint32_t I2SCFGR;
|
||||
__IO uint32_t I2SPR;
|
||||
} SPI_TypeDef;
|
||||
|
||||
/**
|
||||
|
@ -5358,6 +5359,10 @@ typedef struct
|
|||
/* Serial Peripheral Interface */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
|
||||
*/
|
||||
#define SPI_I2S_SUPPORT /*!< I2S support */
|
||||
|
||||
/******************* Bit definition for SPI_CR1 register ********************/
|
||||
#define SPI_CR1_CPHA_Pos (0U)
|
||||
|
@ -5475,10 +5480,52 @@ typedef struct
|
|||
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
|
||||
|
||||
/****************** Bit definition for SPI_I2SCFGR register *****************/
|
||||
#define SPI_I2SCFGR_CHLEN_Pos (0U)
|
||||
#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
|
||||
#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!< Channel length (number of bits per audio channel) */
|
||||
|
||||
#define SPI_I2SCFGR_DATLEN_Pos (1U)
|
||||
#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
|
||||
#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!< DATLEN[1:0] bits (Data length to be transferred) */
|
||||
#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
|
||||
#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define SPI_I2SCFGR_CKPOL_Pos (3U)
|
||||
#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
|
||||
#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!< steady state clock polarity */
|
||||
|
||||
#define SPI_I2SCFGR_I2SSTD_Pos (4U)
|
||||
#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
|
||||
#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!< I2SSTD[1:0] bits (I2S standard selection) */
|
||||
#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
|
||||
#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
|
||||
|
||||
#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
|
||||
#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
|
||||
#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!< PCM frame synchronization */
|
||||
|
||||
#define SPI_I2SCFGR_I2SCFG_Pos (8U)
|
||||
#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
|
||||
#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!< I2SCFG[1:0] bits (I2S configuration mode) */
|
||||
#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
|
||||
#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
|
||||
|
||||
#define SPI_I2SCFGR_I2SE_Pos (10U)
|
||||
#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
|
||||
#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!< I2S Enable */
|
||||
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
|
||||
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
|
||||
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
|
||||
|
||||
/****************** Bit definition for SPI_I2SPR register *******************/
|
||||
#define SPI_I2SPR_I2SDIV_Pos (0U)
|
||||
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
|
||||
#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!< I2S Linear prescaler */
|
||||
#define SPI_I2SPR_ODD_Pos (8U)
|
||||
#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
|
||||
#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!< Odd factor for the prescaler */
|
||||
#define SPI_I2SPR_MCKOE_Pos (9U)
|
||||
#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
|
||||
#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!< Master Clock Output Enable */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
@ -6286,6 +6333,10 @@ typedef struct
|
|||
/******************************* SMBUS Instances ******************************/
|
||||
#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
|
||||
|
||||
/******************************** I2S Instances *******************************/
|
||||
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
|
||||
((INSTANCE) == SPI3))
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
|
@ -6407,8 +6458,6 @@ typedef struct
|
|||
((INSTANCE) == TIM9) || \
|
||||
((INSTANCE) == TIM12))
|
||||
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
|
@ -6602,18 +6651,18 @@ typedef struct
|
|||
#define TIM1_UP_TIM16_IRQn TIM10_IRQn
|
||||
#define TIM1_UP_IRQn TIM10_IRQn
|
||||
#define TIM1_UP_TIM10_IRQn TIM10_IRQn
|
||||
#define TIM1_TRG_COM_IRQn TIM11_IRQn
|
||||
#define TIM1_TRG_COM_TIM17_IRQn TIM11_IRQn
|
||||
#define TIM1_TRG_COM_TIM11_IRQn TIM11_IRQn
|
||||
#define TIM1_TRG_COM_IRQn TIM11_IRQn
|
||||
#define TIM8_BRK_TIM12_IRQn TIM12_IRQn
|
||||
#define TIM8_BRK_IRQn TIM12_IRQn
|
||||
#define TIM8_BRK_TIM12_IRQn TIM12_IRQn
|
||||
#define TIM8_UP_TIM13_IRQn TIM13_IRQn
|
||||
#define TIM8_UP_IRQn TIM13_IRQn
|
||||
#define TIM8_TRG_COM_IRQn TIM14_IRQn
|
||||
#define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn
|
||||
#define TIM6_DAC_IRQn TIM6_IRQn
|
||||
#define TIM1_BRK_IRQn TIM9_IRQn
|
||||
#define TIM1_BRK_TIM15_IRQn TIM9_IRQn
|
||||
#define TIM1_BRK_IRQn TIM9_IRQn
|
||||
#define TIM1_BRK_TIM9_IRQn TIM9_IRQn
|
||||
|
||||
|
||||
|
@ -6623,18 +6672,18 @@ typedef struct
|
|||
#define TIM1_UP_TIM16_IRQHandler TIM10_IRQHandler
|
||||
#define TIM1_UP_IRQHandler TIM10_IRQHandler
|
||||
#define TIM1_UP_TIM10_IRQHandler TIM10_IRQHandler
|
||||
#define TIM1_TRG_COM_IRQHandler TIM11_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM17_IRQHandler TIM11_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM11_IRQHandler TIM11_IRQHandler
|
||||
#define TIM1_TRG_COM_IRQHandler TIM11_IRQHandler
|
||||
#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler
|
||||
#define TIM8_BRK_IRQHandler TIM12_IRQHandler
|
||||
#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler
|
||||
#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler
|
||||
#define TIM8_UP_IRQHandler TIM13_IRQHandler
|
||||
#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
|
||||
#define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler
|
||||
#define TIM6_DAC_IRQHandler TIM6_IRQHandler
|
||||
#define TIM1_BRK_IRQHandler TIM9_IRQHandler
|
||||
#define TIM1_BRK_TIM15_IRQHandler TIM9_IRQHandler
|
||||
#define TIM1_BRK_IRQHandler TIM9_IRQHandler
|
||||
#define TIM1_BRK_TIM9_IRQHandler TIM9_IRQHandler
|
||||
|
||||
|
||||
|
|
|
@ -5531,12 +5531,10 @@ typedef struct
|
|||
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
|
||||
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
|
||||
|
||||
/****************** Bit definition for SPI_I2SCFGR register *****************/
|
||||
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
|
||||
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
|
||||
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Inter-integrated Circuit Interface */
|
||||
|
@ -6289,8 +6287,6 @@ typedef struct
|
|||
(((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
|
|
|
@ -5585,12 +5585,10 @@ typedef struct
|
|||
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
|
||||
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
|
||||
|
||||
/****************** Bit definition for SPI_I2SCFGR register *****************/
|
||||
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
|
||||
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
|
||||
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Inter-integrated Circuit Interface */
|
||||
|
@ -6389,8 +6387,6 @@ typedef struct
|
|||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
|
@ -6532,20 +6528,20 @@ typedef struct
|
|||
#define ADC1_2_IRQn ADC1_IRQn
|
||||
#define CEC_IRQn USBWakeUp_IRQn
|
||||
#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
|
||||
#define CAN1_TX_IRQn USB_HP_IRQn
|
||||
#define USB_HP_CAN1_TX_IRQn USB_HP_IRQn
|
||||
#define USB_LP_CAN1_RX0_IRQn USB_LP_IRQn
|
||||
#define CAN1_TX_IRQn USB_HP_IRQn
|
||||
#define CAN1_RX0_IRQn USB_LP_IRQn
|
||||
#define USB_LP_CAN1_RX0_IRQn USB_LP_IRQn
|
||||
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_2_IRQHandler ADC1_IRQHandler
|
||||
#define CEC_IRQHandler USBWakeUp_IRQHandler
|
||||
#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
|
||||
#define CAN1_TX_IRQHandler USB_HP_IRQHandler
|
||||
#define USB_HP_CAN1_TX_IRQHandler USB_HP_IRQHandler
|
||||
#define USB_LP_CAN1_RX0_IRQHandler USB_LP_IRQHandler
|
||||
#define CAN1_TX_IRQHandler USB_HP_IRQHandler
|
||||
#define CAN1_RX0_IRQHandler USB_LP_IRQHandler
|
||||
#define USB_LP_CAN1_RX0_IRQHandler USB_LP_IRQHandler
|
||||
|
||||
|
||||
/**
|
||||
|
|
|
@ -9128,12 +9128,10 @@ typedef struct
|
|||
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
|
||||
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
|
||||
|
||||
/****************** Bit definition for SPI_I2SCFGR register *****************/
|
||||
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
|
||||
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
|
||||
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Inter-integrated Circuit Interface */
|
||||
|
@ -9912,8 +9910,6 @@ typedef struct
|
|||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
|
@ -10051,40 +10047,40 @@ typedef struct
|
|||
|
||||
/* Aliases for __IRQn */
|
||||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
|
||||
#define TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
|
||||
#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
|
||||
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
|
||||
#define TIM10_IRQn TIM1_UP_IRQn
|
||||
#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
|
||||
#define CEC_IRQn USBWakeUp_IRQn
|
||||
#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
|
||||
#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
|
||||
#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
|
||||
#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
|
||||
#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
|
||||
#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
|
||||
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
|
||||
#define CEC_IRQHandler USBWakeUp_IRQHandler
|
||||
#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
|
||||
#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
|
||||
#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
|
||||
#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
|
||||
#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
|
||||
#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
|
||||
|
||||
|
||||
/**
|
||||
|
|
|
@ -9190,12 +9190,10 @@ typedef struct
|
|||
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
|
||||
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
|
||||
|
||||
/****************** Bit definition for SPI_I2SCFGR register *****************/
|
||||
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
|
||||
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
|
||||
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Inter-integrated Circuit Interface */
|
||||
|
@ -10021,8 +10019,6 @@ typedef struct
|
|||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
|
@ -10182,40 +10178,40 @@ typedef struct
|
|||
|
||||
/* Aliases for __IRQn */
|
||||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
|
||||
#define TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM10_IRQn TIM1_UP_IRQn
|
||||
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
|
||||
#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
|
||||
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
|
||||
#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
|
||||
#define CEC_IRQn USBWakeUp_IRQn
|
||||
#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
|
||||
#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
|
||||
#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
|
||||
#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
|
||||
#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
|
||||
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
|
||||
#define CEC_IRQHandler USBWakeUp_IRQHandler
|
||||
#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
|
||||
#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
|
||||
#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
|
||||
#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
|
||||
#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
|
||||
|
||||
|
||||
/**
|
||||
|
|
|
@ -10583,7 +10583,6 @@ typedef struct
|
|||
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
|
||||
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
|
||||
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
|
||||
|
||||
/****************** Bit definition for SPI_I2SPR register *******************/
|
||||
#define SPI_I2SPR_I2SDIV_Pos (0U)
|
||||
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
|
||||
|
@ -11484,8 +11483,6 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5))
|
||||
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
|
@ -11693,20 +11690,20 @@ typedef struct
|
|||
/* Aliases for __IRQn */
|
||||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn
|
||||
#define TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM10_IRQn TIM1_UP_IRQn
|
||||
#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
|
||||
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
|
||||
#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
|
||||
#define TIM10_IRQn TIM1_UP_IRQn
|
||||
#define TIM6_DAC_IRQn TIM6_IRQn
|
||||
#define TIM12_IRQn TIM8_BRK_IRQn
|
||||
#define TIM8_BRK_TIM12_IRQn TIM8_BRK_IRQn
|
||||
#define TIM8_TRG_COM_TIM14_IRQn TIM8_TRG_COM_IRQn
|
||||
#define TIM12_IRQn TIM8_BRK_IRQn
|
||||
#define TIM14_IRQn TIM8_TRG_COM_IRQn
|
||||
#define TIM8_TRG_COM_TIM14_IRQn TIM8_TRG_COM_IRQn
|
||||
#define TIM8_UP_TIM13_IRQn TIM8_UP_IRQn
|
||||
#define TIM13_IRQn TIM8_UP_IRQn
|
||||
#define CEC_IRQn USBWakeUp_IRQn
|
||||
|
@ -11720,20 +11717,20 @@ typedef struct
|
|||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler
|
||||
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM6_DAC_IRQHandler TIM6_IRQHandler
|
||||
#define TIM12_IRQHandler TIM8_BRK_IRQHandler
|
||||
#define TIM8_BRK_TIM12_IRQHandler TIM8_BRK_IRQHandler
|
||||
#define TIM8_TRG_COM_TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
|
||||
#define TIM12_IRQHandler TIM8_BRK_IRQHandler
|
||||
#define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
|
||||
#define TIM8_TRG_COM_TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
|
||||
#define TIM8_UP_TIM13_IRQHandler TIM8_UP_IRQHandler
|
||||
#define TIM13_IRQHandler TIM8_UP_IRQHandler
|
||||
#define CEC_IRQHandler USBWakeUp_IRQHandler
|
||||
|
|
|
@ -10652,7 +10652,6 @@ typedef struct
|
|||
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
|
||||
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
|
||||
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
|
||||
|
||||
/****************** Bit definition for SPI_I2SPR register *******************/
|
||||
#define SPI_I2SPR_I2SDIV_Pos (0U)
|
||||
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
|
||||
|
@ -11642,8 +11641,6 @@ typedef struct
|
|||
((INSTANCE) == TIM9) || \
|
||||
((INSTANCE) == TIM12))
|
||||
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
|
@ -11878,11 +11875,11 @@ typedef struct
|
|||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn
|
||||
#define TIM9_IRQn TIM1_BRK_TIM9_IRQn
|
||||
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_TIM9_IRQn
|
||||
#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn
|
||||
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_TIM9_IRQn
|
||||
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_TIM11_IRQn
|
||||
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn
|
||||
#define TIM11_IRQn TIM1_TRG_COM_TIM11_IRQn
|
||||
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_TIM11_IRQn
|
||||
#define TIM10_IRQn TIM1_UP_TIM10_IRQn
|
||||
#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn
|
||||
#define TIM1_UP_TIM16_IRQn TIM1_UP_TIM10_IRQn
|
||||
|
@ -11891,25 +11888,25 @@ typedef struct
|
|||
#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn
|
||||
#define TIM14_IRQn TIM8_TRG_COM_TIM14_IRQn
|
||||
#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn
|
||||
#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn
|
||||
#define TIM13_IRQn TIM8_UP_TIM13_IRQn
|
||||
#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn
|
||||
#define CEC_IRQn USBWakeUp_IRQn
|
||||
#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
|
||||
#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
|
||||
#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
|
||||
#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
|
||||
#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
|
||||
#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
|
||||
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler
|
||||
#define TIM9_IRQHandler TIM1_BRK_TIM9_IRQHandler
|
||||
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_TIM9_IRQHandler
|
||||
#define TIM1_BRK_IRQHandler TIM1_BRK_TIM9_IRQHandler
|
||||
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_TIM9_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
|
||||
#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
|
||||
#define TIM11_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
|
||||
#define TIM10_IRQHandler TIM1_UP_TIM10_IRQHandler
|
||||
#define TIM1_UP_IRQHandler TIM1_UP_TIM10_IRQHandler
|
||||
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_TIM10_IRQHandler
|
||||
|
@ -11918,14 +11915,14 @@ typedef struct
|
|||
#define TIM8_BRK_IRQHandler TIM8_BRK_TIM12_IRQHandler
|
||||
#define TIM14_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler
|
||||
#define TIM8_TRG_COM_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler
|
||||
#define TIM8_UP_IRQHandler TIM8_UP_TIM13_IRQHandler
|
||||
#define TIM13_IRQHandler TIM8_UP_TIM13_IRQHandler
|
||||
#define TIM8_UP_IRQHandler TIM8_UP_TIM13_IRQHandler
|
||||
#define CEC_IRQHandler USBWakeUp_IRQHandler
|
||||
#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
|
||||
#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
|
||||
#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
|
||||
#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
|
||||
#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
|
||||
#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
|
||||
|
||||
|
||||
/**
|
||||
|
|
|
@ -1250,6 +1250,11 @@ typedef struct
|
|||
/* Reset and Clock Control */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
|
||||
*/
|
||||
#define RCC_PLL2_SUPPORT /*!< Support PLL2 */
|
||||
#define RCC_PLLI2S_SUPPORT
|
||||
|
||||
/******************** Bit definition for RCC_CR register ********************/
|
||||
#define RCC_CR_HSION_Pos (0U)
|
||||
|
@ -1283,11 +1288,6 @@ typedef struct
|
|||
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
|
||||
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
|
||||
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
|
||||
*/
|
||||
#define RCC_PLL2_SUPPORT /*!< Support PLL2 */
|
||||
|
||||
#define RCC_CR_PLL2ON_Pos (26U)
|
||||
#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
|
||||
#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */
|
||||
|
@ -1295,11 +1295,6 @@ typedef struct
|
|||
#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
|
||||
#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */
|
||||
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
|
||||
*/
|
||||
#define RCC_PLLI2S_SUPPORT /*!< Support PLL3 (PLLI2S)*/
|
||||
|
||||
#define RCC_CR_PLL3ON_Pos (28U)
|
||||
#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
|
||||
#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */
|
||||
|
@ -11914,7 +11909,6 @@ typedef struct
|
|||
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
|
||||
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
|
||||
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
|
||||
|
||||
/****************** Bit definition for SPI_I2SPR register *******************/
|
||||
#define SPI_I2SPR_I2SDIV_Pos (0U)
|
||||
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
|
||||
|
@ -14092,8 +14086,6 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5))
|
||||
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
|
@ -14289,15 +14281,15 @@ typedef struct
|
|||
#define DMA2_Channel4_5_IRQn DMA2_Channel4_IRQn
|
||||
#define USBWakeUp_IRQn OTG_FS_WKUP_IRQn
|
||||
#define CEC_IRQn OTG_FS_WKUP_IRQn
|
||||
#define TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM10_IRQn TIM1_UP_IRQn
|
||||
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
|
||||
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
|
||||
#define TIM10_IRQn TIM1_UP_IRQn
|
||||
#define TIM6_DAC_IRQn TIM6_IRQn
|
||||
|
||||
|
||||
|
@ -14310,15 +14302,15 @@ typedef struct
|
|||
#define DMA2_Channel4_5_IRQHandler DMA2_Channel4_IRQHandler
|
||||
#define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler
|
||||
#define CEC_IRQHandler OTG_FS_WKUP_IRQHandler
|
||||
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM6_DAC_IRQHandler TIM6_IRQHandler
|
||||
|
||||
|
||||
|
|
|
@ -1330,6 +1330,11 @@ typedef struct
|
|||
/* Reset and Clock Control */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
|
||||
*/
|
||||
#define RCC_PLL2_SUPPORT /*!< Support PLL2 */
|
||||
#define RCC_PLLI2S_SUPPORT
|
||||
|
||||
/******************** Bit definition for RCC_CR register ********************/
|
||||
#define RCC_CR_HSION_Pos (0U)
|
||||
|
@ -1363,11 +1368,6 @@ typedef struct
|
|||
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
|
||||
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
|
||||
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
|
||||
*/
|
||||
#define RCC_PLL2_SUPPORT /*!< Support PLL2 */
|
||||
|
||||
#define RCC_CR_PLL2ON_Pos (26U)
|
||||
#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
|
||||
#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */
|
||||
|
@ -1375,11 +1375,6 @@ typedef struct
|
|||
#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
|
||||
#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */
|
||||
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
|
||||
*/
|
||||
#define RCC_PLLI2S_SUPPORT /*!< Support PLL3 (PLLI2S)*/
|
||||
|
||||
#define RCC_CR_PLL3ON_Pos (28U)
|
||||
#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
|
||||
#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */
|
||||
|
@ -12006,7 +12001,6 @@ typedef struct
|
|||
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
|
||||
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
|
||||
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
|
||||
|
||||
/****************** Bit definition for SPI_I2SPR register *******************/
|
||||
#define SPI_I2SPR_I2SDIV_Pos (0U)
|
||||
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
|
||||
|
@ -15003,8 +14997,6 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5))
|
||||
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
|
@ -15195,42 +15187,42 @@ typedef struct
|
|||
|
||||
/* Aliases for __IRQn */
|
||||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn
|
||||
#define USB_LP_IRQn CAN1_RX0_IRQn
|
||||
#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
|
||||
#define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn
|
||||
#define USB_HP_IRQn CAN1_TX_IRQn
|
||||
#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
|
||||
#define DMA2_Channel4_5_IRQn DMA2_Channel4_IRQn
|
||||
#define USBWakeUp_IRQn OTG_FS_WKUP_IRQn
|
||||
#define CEC_IRQn OTG_FS_WKUP_IRQn
|
||||
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
|
||||
#define TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
|
||||
#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
|
||||
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
|
||||
#define TIM10_IRQn TIM1_UP_IRQn
|
||||
#define TIM6_DAC_IRQn TIM6_IRQn
|
||||
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler
|
||||
#define USB_LP_IRQHandler CAN1_RX0_IRQHandler
|
||||
#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler
|
||||
#define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler
|
||||
#define USB_HP_IRQHandler CAN1_TX_IRQHandler
|
||||
#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler
|
||||
#define DMA2_Channel4_5_IRQHandler DMA2_Channel4_IRQHandler
|
||||
#define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler
|
||||
#define CEC_IRQHandler OTG_FS_WKUP_IRQHandler
|
||||
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM6_DAC_IRQHandler TIM6_IRQHandler
|
||||
|
||||
|
|
|
@ -90,11 +90,11 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V4.3.1
|
||||
* @brief CMSIS Device version number V4.3.2
|
||||
*/
|
||||
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
|
||||
#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
|
||||
#define __STM32F1_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
|
||||
#define __STM32F1_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
|
||||
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
|
||||
|
|
|
@ -89,12 +89,31 @@
|
|||
/* #define DATA_IN_ExtSRAM */
|
||||
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/* Note: Following vector table addresses must be defined in line with linker
|
||||
configuration. */
|
||||
/*!< Uncomment the following line if you need to relocate the vector table
|
||||
anywhere in Flash or Sram, else the vector table is kept at the automatic
|
||||
remap of boot address selected */
|
||||
/* #define USER_VECT_TAB_ADDRESS */
|
||||
|
||||
#if defined(USER_VECT_TAB_ADDRESS)
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table
|
||||
in Sram else user remap will be done in Flash. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#endif /* USER_VECT_TAB_ADDRESS */
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -156,57 +175,16 @@ const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};
|
|||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= 0x00000001U;
|
||||
|
||||
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
|
||||
#if !defined(STM32F105xC) && !defined(STM32F107xC)
|
||||
RCC->CFGR &= 0xF8FF0000U;
|
||||
#else
|
||||
RCC->CFGR &= 0xF0FF0000U;
|
||||
#endif /* STM32F105xC */
|
||||
|
||||
/* Reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= 0xFEF6FFFFU;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= 0xFFFBFFFFU;
|
||||
|
||||
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
|
||||
RCC->CFGR &= 0xFF80FFFFU;
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
/* Reset PLL2ON and PLL3ON bits */
|
||||
RCC->CR &= 0xEBFFFFFFU;
|
||||
|
||||
/* Disable all interrupts and clear pending bits */
|
||||
RCC->CIR = 0x00FF0000U;
|
||||
|
||||
/* Reset CFGR2 register */
|
||||
RCC->CFGR2 = 0x00000000U;
|
||||
#elif defined(STM32F100xB) || defined(STM32F100xE)
|
||||
/* Disable all interrupts and clear pending bits */
|
||||
RCC->CIR = 0x009F0000U;
|
||||
|
||||
/* Reset CFGR2 register */
|
||||
RCC->CFGR2 = 0x00000000U;
|
||||
#else
|
||||
/* Disable all interrupts and clear pending bits */
|
||||
RCC->CIR = 0x009F0000U;
|
||||
#endif /* STM32F105xC */
|
||||
|
||||
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
SystemInit_ExtMemCtl();
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
#endif
|
||||
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
|
||||
#endif
|
||||
/* Configure the Vector Table location -------------------------------------*/
|
||||
#if defined(USER_VECT_TAB_ADDRESS)
|
||||
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
||||
#endif /* USER_VECT_TAB_ADDRESS */
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
Loading…
Reference in New Issue