scripts/genpinctrl: Remove mode for default (non-F1) config

Due to inference of mode for default configurations, mode
should not be set unless it specifies a specific signal variant.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2020-10-26 17:23:22 +01:00 committed by Kumar Gala
parent 634a286b27
commit 0f855853fe
1 changed files with 3 additions and 46 deletions

View File

@ -11,10 +11,12 @@
# be as precise as possible. Note that it needs to be escaped here in the
# configuration file.
#
# - mode (mandatory): Mode setting (analog, alternate). Mode needs to
# - mode (optional): Mode setting (analog, alternate). Mode needs to
# be set according to the following rules:
# * Pin operates in analog configuration: analog
# * Pin operates in alternate function configuration: alternate
# In default case, mode could be infered from CubeMX SoC description files
# and can be omitted.
#
# - bias (optional): Bias setting (disable, pull-up, pull-down). Equivalent to
# "disable" (a.k.a floating) if not set.
@ -33,167 +35,133 @@
---
- name: ADC_IN / ADC_INN / ADC_INP
match: "^ADC(?:\\d+)?_IN[NP]?\\d+$"
mode: analog
- name: CAN_RX
match: "^CAN\\d*_RX$"
mode: alternate
bias: pull-up
- name: CAN_TX
match: "^CAN\\d*_TX$"
mode: alternate
- name: DAC_OUT
match: "^DAC(?:\\d+)?_OUT\\d+$"
mode: analog
- name: ETH_COL
match: "^ETH_COL$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_CRS
match: "^ETH_CRS$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_CRS_DV
match: "^ETH_CRS_DV$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_MDC
match: "^ETH_MDC$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_MDIO
match: "^ETH_MDIO$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_PPS_OUT
match: "^ETH_PPS_OUT$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_REF_CLK
match: "^ETH_REF_CLK$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_RX_CLK
match: "^ETH_RX_CLK$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_RX_DV
match: "^ETH_RX_DV$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_RX_ER
match: "^ETH_RX_ER$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_RXD0
match: "^ETH_RXD0$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_RXD1
match: "^ETH_RXD1$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_RXD2
match: "^ETH_RXD2$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_RXD3
match: "^ETH_RXD3$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_TX_CLK
match: "^ETH_TX_CLK$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_TX_EN
match: "^ETH_TX_EN$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_TXD0
match: "^ETH_TXD0$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_TXD1
match: "^ETH_TXD1$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_TXD2
match: "^ETH_TXD2$"
mode: alternate
slew-rate: very-high-speed
- name: ETH_TXD3
match: "^ETH_TXD3$"
mode: alternate
slew-rate: very-high-speed
- name: FDCAN_RX
match: "^FDCAN\\d+_RX$"
mode: alternate
- name: FDCAN_TX
match: "^FDCAN\\d+_TX$"
mode: alternate
- name: I2C_SCL
match: "^I2C\\d+_SCL$"
mode: alternate
drive: open-drain
bias: pull-up
- name: I2C_SDA
match: "^I2C\\d+_SDA$"
mode: alternate
drive: open-drain
bias: pull-up
- name: I2S_CK
match: "^I2S\\d+_CK$"
mode: alternate
slew-rate: very-high-speed
- name: I2S_WS
match: "^I2S\\d+_WS$"
mode: alternate
- name: I2S_SD
match: "^I2S\\d+_SD$"
mode: alternate
- name: SDMMC
match: "^SDMMC\\d+_(?:CK)?(?:CKIN)?(?:CDIR)?(?:CMD)?(?:D\\d+)?(?:D0DIR)?(?:D123DIR)?$"
mode: alternate
slew-rate: very-high-speed
- name: SPI_MISO
match: "^SPI\\d+_MISO$"
mode: alternate
bias: pull-down
- name: SPI_MOSI
match: "^SPI\\d+_MOSI$"
mode: alternate
bias: pull-down
# NOTE: The SPI_SCK pins speed must be set to very-high-speed to avoid last data
@ -201,51 +169,40 @@
# peripheral (ref. ES0182 Rev 12, 2.5.12, p. 22).
- name: SPI_SCK
match: "^SPI\\d+_SCK$"
mode: alternate
slew-rate: very-high-speed
- name: SPI_NSS
match: "^SPI\\d+_NSS$"
mode: alternate
bias: pull-up
- name: TIM_CH / TIM_CHN
match: "^TIM\\d+_CH\\d+N?$"
mode: alternate
- name: UART_CTS / USART_CTS / LPUART_CTS
match: "^(?:LP)?US?ART\\d+_CTS$"
mode: alternate
drive: open-drain
bias: pull-up
- name: UART_RTS / USART_RTS / LPUART_RTS
match: "^(?:LP)?US?ART\\d+_RTS$"
mode: alternate
drive: open-drain
bias: pull-up
- name: UART_TX / USART_TX / LPUART_TX
match: "^(?:LP)?US?ART\\d+_TX$"
mode: alternate
bias: pull-up
- name: UART_RX / USART_RX / LPUART_RX
match: "^(?:LP)?US?ART\\d+_RX$"
mode: alternate
- name: USB_OTG_FS
match: "^USB_OTG_FS_(?:DM)?(?:DP)?(?:SOF)?(?:ID)?(?:VBUS)?$"
mode: alternate
- name: USB_OTG_HS
match: "^USB_OTG_HS_(?:DM)?(?:DP)?(?:SOF)?(?:ID)?(?:VBUS)?$"
mode: alternate
- name: USB_OTG_HS_ULPI
match: "^USB_OTG_HS_ULPI_(?:DIR)?(?:STP)?(?:NXT)?(?:D\\d+)?$"
mode: alternate
- name: USB
match: "^USB_(?:DM)?(?:DP)?(?:NOE)?$"
mode: alternate