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gecko: emlib files updated | Update to GSDK 4.4.0 

Updated the files present in gecko/emlib folder.
Purpose of this PR is to align the codebase of hal_silabs with gecko_sdk 4.4.0

Signed-off-by: Sateesh Kotapati <sateesh.kotapati@silabs.com>
This commit is contained in:
Sateesh Kotapati 2024-01-10 12:45:50 +05:30 committed by Filip Kokosiński
parent e670e74976
commit 4cfb0e3e36
32 changed files with 2641 additions and 1088 deletions
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13
gecko/common/inc/sl_common.h
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@ -58,7 +58,7 @@ extern "C" {
* This SDK supports the following compilers/IDEs:
* @li Simplicity Studio
* @li IAR Embedded Workbench
* @li Keil µVision IDE
* @li Keil uVision IDE
* @li Plain armgcc
*
* Certain compiler features such as alignment is implemented differently in the tools.
@ -72,6 +72,11 @@ extern "C" {
* @{
******************************************************************************/
/** @brief Macros to concatenate. */
#define SL_CONCAT_PASTER_2(first, second) first ## second ///< sl concat paster 2.
#define SL_CONCAT_PASTER_3(first, second, third) first ## second ## third ///< sl concat paster 3.
#define SL_CONCAT_PASTER_4(first, second, third, fourth) first ## second ## third ## fourth ///< sl concat paster 4.
/** @brief Round n up to closest interval of i. */
#define SL_CEILING(n, i) ((((n) + (i) - 1U) / (i)) * (i))
@ -255,6 +260,12 @@ extern "C" {
#else
#define SL_DEPRECATED_API_SDK_4_2 __attribute__ ((deprecated))
#endif
#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_4_4
#define SL_DEPRECATED_API_SDK_4_4
#else
#define SL_DEPRECATED_API_SDK_4_4 __attribute__ ((deprecated))
#endif
/** @endcond */
/***************************************************************************//**

83
gecko/common/inc/sl_status.h
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@ -44,36 +44,36 @@
// -----------------------------------------------------------------------------
// Space Defines
#define SL_STATUS_SPACE_MASK ((sl_status_t)0xFF00)
#define SL_STATUS_SPACE_MASK ((sl_status_t)0xFF00) ///< sl status space mask.
#define SL_STATUS_GENERIC_SPACE ((sl_status_t)0x0000)
#define SL_STATUS_GENERIC_SPACE ((sl_status_t)0x0000) ///< sl status generic space.
#define SL_STATUS_PLATFORM_1_SPACE ((sl_status_t)0x0100)
#define SL_STATUS_PLATFORM_2_SPACE ((sl_status_t)0x0200)
#define SL_STATUS_HARDWARE_SPACE ((sl_status_t)0x0300)
#define SL_STATUS_PLATFORM_1_SPACE ((sl_status_t)0x0100) ///< sl status platform 1 space.
#define SL_STATUS_PLATFORM_2_SPACE ((sl_status_t)0x0200) ///< sl status platform 2 space.
#define SL_STATUS_HARDWARE_SPACE ((sl_status_t)0x0300) ///< sl status hardware space.
#define SL_STATUS_BLUETOOTH_SPACE ((sl_status_t)0x0400)
#define SL_STATUS_BLUETOOTH_MESH_SPACE ((sl_status_t)0x0500)
#define SL_STATUS_CAN_CANOPEN_SPACE ((sl_status_t)0x0600)
#define SL_STATUS_CONNECT_SPACE ((sl_status_t)0x0700)
#define SL_STATUS_NET_SUITE_SPACE ((sl_status_t)0x0800)
#define SL_STATUS_THREAD_SPACE ((sl_status_t)0x0900)
#define SL_STATUS_USB_SPACE ((sl_status_t)0x0A00)
#define SL_STATUS_WIFI_SPACE ((sl_status_t)0x0B00)
#define SL_STATUS_ZIGBEE_SPACE ((sl_status_t)0x0C00)
#define SL_STATUS_Z_WAVE_SPACE ((sl_status_t)0x0D00)
#define SL_STATUS_BLUETOOTH_SPACE ((sl_status_t)0x0400) ///< sl status bluetooth space.
#define SL_STATUS_BLUETOOTH_MESH_SPACE ((sl_status_t)0x0500) ///< sl status bluetooth mesh space.
#define SL_STATUS_CAN_CANOPEN_SPACE ((sl_status_t)0x0600) ///< sl status can canopen space.
#define SL_STATUS_CONNECT_SPACE ((sl_status_t)0x0700) ///< sl status connect space.
#define SL_STATUS_NET_SUITE_SPACE ((sl_status_t)0x0800) ///< sl status net suite space.
#define SL_STATUS_THREAD_SPACE ((sl_status_t)0x0900) ///< sl status thread space.
#define SL_STATUS_USB_SPACE ((sl_status_t)0x0A00) ///< sl status usb space.
#define SL_STATUS_WIFI_SPACE ((sl_status_t)0x0B00) ///< sl status wifi space.
#define SL_STATUS_ZIGBEE_SPACE ((sl_status_t)0x0C00) ///< sl status zigbee space.
#define SL_STATUS_Z_WAVE_SPACE ((sl_status_t)0x0D00) ///< sl status z wave space.
#define SL_STATUS_GECKO_OS_1_SPACE ((sl_status_t)0x0E00)
#define SL_STATUS_GECKO_OS_2_SPACE ((sl_status_t)0x0F00)
#define SL_STATUS_GECKO_OS_1_SPACE ((sl_status_t)0x0E00) ///< sl status gecko os 1 space.
#define SL_STATUS_GECKO_OS_2_SPACE ((sl_status_t)0x0F00) ///< sl status gecko os 2 space.
#define SL_STATUS_BLUETOOTH_CTRL_SPACE ((sl_status_t)0x1000)
#define SL_STATUS_BLUETOOTH_ATT_SPACE ((sl_status_t)0x1100)
#define SL_STATUS_BLUETOOTH_SMP_SPACE ((sl_status_t)0x1200)
#define SL_STATUS_BLUETOOTH_MESH_FOUNDATION_SPACE ((sl_status_t)0x1300)
#define SL_STATUS_BLUETOOTH_CTRL_SPACE ((sl_status_t)0x1000) ///< sl status bluetooth ctrl space.
#define SL_STATUS_BLUETOOTH_ATT_SPACE ((sl_status_t)0x1100) ///< sl status bluetooth att space.
#define SL_STATUS_BLUETOOTH_SMP_SPACE ((sl_status_t)0x1200) ///< sl status bluetooth mesh foundation space.
#define SL_STATUS_BLUETOOTH_MESH_FOUNDATION_SPACE ((sl_status_t)0x1300) ///< sl status bluetooth mesh foundation space.
#define SL_STATUS_WISUN_SPACE ((sl_status_t)0x1400)
#define SL_STATUS_WISUN_SPACE ((sl_status_t)0x1400) ///< sl status wisun space.
#define SL_STATUS_COMPUTE_SPACE ((sl_status_t)0x1500)
#define SL_STATUS_COMPUTE_SPACE ((sl_status_t)0x1500) ///< sl status compute space.
// -----------------------------------------------------------------------------
// Status Defines
@ -148,20 +148,20 @@
#define SL_STATUS_MESSAGE_TOO_LONG ((sl_status_t)0x0038) ///< Message is too long.
// EEPROM/Flash Errors
#define SL_STATUS_EEPROM_MFG_VERSION_MISMATCH ((sl_status_t)0x0039) ///<
#define SL_STATUS_EEPROM_STACK_VERSION_MISMATCH ((sl_status_t)0x003A) ///<
#define SL_STATUS_EEPROM_MFG_VERSION_MISMATCH ((sl_status_t)0x0039) ///< EEPROM MFG version mismatch.
#define SL_STATUS_EEPROM_STACK_VERSION_MISMATCH ((sl_status_t)0x003A) ///< EEPROM Stack version mismatch.
#define SL_STATUS_FLASH_WRITE_INHIBITED ((sl_status_t)0x003B) ///< Flash write is inhibited.
#define SL_STATUS_FLASH_VERIFY_FAILED ((sl_status_t)0x003C) ///< Flash verification failed.
#define SL_STATUS_FLASH_PROGRAM_FAILED ((sl_status_t)0x003D) ///< Flash programming failed.
#define SL_STATUS_FLASH_ERASE_FAILED ((sl_status_t)0x003E) ///< Flash erase failed.
// MAC Errors
#define SL_STATUS_MAC_NO_DATA ((sl_status_t)0x003F) ///<
#define SL_STATUS_MAC_NO_ACK_RECEIVED ((sl_status_t)0x0040) ///<
#define SL_STATUS_MAC_INDIRECT_TIMEOUT ((sl_status_t)0x0041) ///<
#define SL_STATUS_MAC_UNKNOWN_HEADER_TYPE ((sl_status_t)0x0042) ///<
#define SL_STATUS_MAC_ACK_HEADER_TYPE ((sl_status_t)0x0043) ///<
#define SL_STATUS_MAC_COMMAND_TRANSMIT_FAILURE ((sl_status_t)0x0044) ///<
#define SL_STATUS_MAC_NO_DATA ((sl_status_t)0x003F) ///< MAC no data.
#define SL_STATUS_MAC_NO_ACK_RECEIVED ((sl_status_t)0x0040) ///< MAC no ACK received.
#define SL_STATUS_MAC_INDIRECT_TIMEOUT ((sl_status_t)0x0041) ///< MAC indirect timeout.
#define SL_STATUS_MAC_UNKNOWN_HEADER_TYPE ((sl_status_t)0x0042) ///< MAC unknown header type.
#define SL_STATUS_MAC_ACK_HEADER_TYPE ((sl_status_t)0x0043) ///< MAC ACK unknown header type.
#define SL_STATUS_MAC_COMMAND_TRANSMIT_FAILURE ((sl_status_t)0x0044) ///< MAC command transmit failure.
// CLI_STORAGE Errors
#define SL_STATUS_CLI_STORAGE_NVM_OPEN_ERROR ((sl_status_t)0x0045) ///< Error in open NVM
@ -179,13 +179,13 @@
#define SL_STATUS_BUS_ERROR ((sl_status_t)0x004B) ///< Bus error, e.g. invalid DMA address
// Unified MAC Errors
#define SL_STATUS_CCA_FAILURE ((sl_status_t)0x004C) ///<
#define SL_STATUS_CCA_FAILURE ((sl_status_t)0x004C) ///< CCA failure.
// Scan errors
#define SL_STATUS_MAC_SCANNING ((sl_status_t)0x004D) ///<
#define SL_STATUS_MAC_INCORRECT_SCAN_TYPE ((sl_status_t)0x004E) ///<
#define SL_STATUS_INVALID_CHANNEL_MASK ((sl_status_t)0x004F) ///<
#define SL_STATUS_BAD_SCAN_DURATION ((sl_status_t)0x0050) ///<
#define SL_STATUS_MAC_SCANNING ((sl_status_t)0x004D) ///< MAC scanning.
#define SL_STATUS_MAC_INCORRECT_SCAN_TYPE ((sl_status_t)0x004E) ///< MAC incorrect scan type.
#define SL_STATUS_INVALID_CHANNEL_MASK ((sl_status_t)0x004F) ///< Invalid channel mask.
#define SL_STATUS_BAD_SCAN_DURATION ((sl_status_t)0x0050) ///< Bad scan duration.
// Bluetooth status codes
#define SL_STATUS_BT_OUT_OF_BONDS ((sl_status_t)0x0402) ///< Bonding procedure can't be started because device has no space left for bond.
@ -210,7 +210,7 @@
#define SL_STATUS_BT_PS_STORE_FULL ((sl_status_t)0x041B) ///< Flash reserved for PS store is full
#define SL_STATUS_BT_PS_KEY_NOT_FOUND ((sl_status_t)0x041C) ///< PS key not found
#define SL_STATUS_BT_APPLICATION_MISMATCHED_OR_INSUFFICIENT_SECURITY ((sl_status_t)0x041D) ///< Mismatched or insufficient security level
#define SL_STATUS_BT_APPLICATION_ENCRYPTION_DECRYPTION_ERROR ((sl_status_t)0x041E) ///< Encrypion/decryption operation failed.
#define SL_STATUS_BT_APPLICATION_ENCRYPTION_DECRYPTION_ERROR ((sl_status_t)0x041E) ///< Encryption/decryption operation failed.
// Bluetooth controller status codes
#define SL_STATUS_BT_CTRL_UNKNOWN_CONNECTION_IDENTIFIER ((sl_status_t)0x1002) ///< Connection does not exist, or connection open request was cancelled.
@ -251,7 +251,7 @@
#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_NO_SUITABLE_CHANNEL_FOUND ((sl_status_t)0x1039) ///< The Controller could not calculate an appropriate value for the Channel selection operation.
#define SL_STATUS_BT_CTRL_CONTROLLER_BUSY ((sl_status_t)0x103A) ///< Operation was rejected because the controller is busy and unable to process the request.
#define SL_STATUS_BT_CTRL_UNACCEPTABLE_CONNECTION_INTERVAL ((sl_status_t)0x103B) ///< Remote device terminated the connection because of an unacceptable connection interval.
#define SL_STATUS_BT_CTRL_ADVERTISING_TIMEOUT ((sl_status_t)0x103C) ///< Ddvertising for a fixed duration completed or, for directed advertising, that advertising completed without a connection being created.
#define SL_STATUS_BT_CTRL_ADVERTISING_TIMEOUT ((sl_status_t)0x103C) ///< Advertising for a fixed duration completed or, for directed advertising, that advertising completed without a connection being created.
#define SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_DUE_TO_MIC_FAILURE ((sl_status_t)0x103D) ///< Connection was terminated because the Message Integrity Check (MIC) failed on a received packet.
#define SL_STATUS_BT_CTRL_CONNECTION_FAILED_TO_BE_ESTABLISHED ((sl_status_t)0x103E) ///< LL initiated a connection but the connection has failed to be established. Controller did not receive any packets from remote end.
#define SL_STATUS_BT_CTRL_MAC_CONNECTION_FAILED ((sl_status_t)0x103F) ///< The MAC of the 802.11 AMP was requested to connect to a peer, but the connection failed.
@ -270,7 +270,7 @@
#define SL_STATUS_BT_ATT_REQUEST_NOT_SUPPORTED ((sl_status_t)0x1106) ///< Attribute Server does not support the request received from the client.
#define SL_STATUS_BT_ATT_INVALID_OFFSET ((sl_status_t)0x1107) ///< Offset specified was past the end of the attribute
#define SL_STATUS_BT_ATT_INSUFFICIENT_AUTHORIZATION ((sl_status_t)0x1108) ///< The attribute requires authorization before it can be read or written.
#define SL_STATUS_BT_ATT_PREPARE_QUEUE_FULL ((sl_status_t)0x1109) ///< Too many prepare writes have been queueud
#define SL_STATUS_BT_ATT_PREPARE_QUEUE_FULL ((sl_status_t)0x1109) ///< Too many prepare writes have been queued
#define SL_STATUS_BT_ATT_ATT_NOT_FOUND ((sl_status_t)0x110A) ///< No attribute found within the given attribute handle range.
#define SL_STATUS_BT_ATT_ATT_NOT_LONG ((sl_status_t)0x110B) ///< The attribute cannot be read or written using the Read Blob Request
#define SL_STATUS_BT_ATT_INSUFFICIENT_ENC_KEY_SIZE ((sl_status_t)0x110C) ///< The Encryption Key Size used for encrypting this link is insufficient.
@ -281,7 +281,7 @@
#define SL_STATUS_BT_ATT_INSUFFICIENT_RESOURCES ((sl_status_t)0x1111) ///< Insufficient Resources to complete the request
#define SL_STATUS_BT_ATT_OUT_OF_SYNC ((sl_status_t)0x1112) ///< The server requests the client to rediscover the database.
#define SL_STATUS_BT_ATT_VALUE_NOT_ALLOWED ((sl_status_t)0x1113) ///< The attribute parameter value was not allowed.
#define SL_STATUS_BT_ATT_APPLICATION ((sl_status_t)0x1180) ///< When this is returned in a BGAPI response, the application tried to read or write the value of a user attribute from the GATT databa
#define SL_STATUS_BT_ATT_APPLICATION ((sl_status_t)0x1180) ///< When this is returned in a BGAPI response, the application tried to read or write the value of a user attribute from the GATT database.
#define SL_STATUS_BT_ATT_WRITE_REQUEST_REJECTED ((sl_status_t)0x11FC) ///< The requested write operation cannot be fulfilled for reasons other than permissions.
#define SL_STATUS_BT_ATT_CLIENT_CHARACTERISTIC_CONFIGURATION_DESCRIPTOR_IMPROPERLY_CONFIGURED ((sl_status_t)0x11FD) ///< The Client Characteristic Configuration descriptor is not configured according to the requirements of the profile or service.
#define SL_STATUS_BT_ATT_PROCEDURE_ALREADY_IN_PROGRESS ((sl_status_t)0x11FE) ///< The profile or service request cannot be serviced because an operation that has been previously triggered is still in progress.
@ -382,7 +382,6 @@
#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_INFINITY ((sl_status_t)0x1507) ///< Infinity encountered during array store conversion
#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_NAN ((sl_status_t)0x1508) ///< NaN encountered during array store conversion
#define SL_STATUS_COMPUTE_MATH_FAULT ((sl_status_t)0x1511) ///< MATH Critical fault
#define SL_STATUS_COMPUTE_MATH_NAN ((sl_status_t)0x1512) ///< MATH NaN encountered
#define SL_STATUS_COMPUTE_MATH_INFINITY ((sl_status_t)0x1513) ///< MATH Infinity encountered
#define SL_STATUS_COMPUTE_MATH_OVERFLOW ((sl_status_t)0x1514) ///< MATH numeric overflow
@ -390,7 +389,7 @@
// -----------------------------------------------------------------------------
// Data Types
/** @brief define global status variable. */
typedef uint32_t sl_status_t;
// -----------------------------------------------------------------------------

674
gecko/emlib/inc/em_acmp.h
View File

@ -52,7 +52,7 @@ extern "C" {
******************************** ENUMS ************************************
******************************************************************************/
/** Resistor values used for the internal capacative sense resistor. See
/** Resistor values used for the internal capacitive sense resistor. See
* data sheet for your device for details on each resistor value. */
typedef enum {
#if defined(_ACMP_INPUTCTRL_CSRESSEL_MASK)
@ -196,55 +196,55 @@ typedef enum {
/** ACMP input to the VA divider. This enumeration is used to select the input for
* the VA Divider. */
typedef enum {
acmpVAInputVDD = _ACMP_INPUTSEL_VASEL_VDD,
acmpVAInputAPORT2YCH0 = _ACMP_INPUTSEL_VASEL_APORT2YCH0,
acmpVAInputAPORT2YCH2 = _ACMP_INPUTSEL_VASEL_APORT2YCH2,
acmpVAInputAPORT2YCH4 = _ACMP_INPUTSEL_VASEL_APORT2YCH4,
acmpVAInputAPORT2YCH6 = _ACMP_INPUTSEL_VASEL_APORT2YCH6,
acmpVAInputAPORT2YCH8 = _ACMP_INPUTSEL_VASEL_APORT2YCH8,
acmpVAInputAPORT2YCH10 = _ACMP_INPUTSEL_VASEL_APORT2YCH10,
acmpVAInputAPORT2YCH12 = _ACMP_INPUTSEL_VASEL_APORT2YCH12,
acmpVAInputAPORT2YCH14 = _ACMP_INPUTSEL_VASEL_APORT2YCH14,
acmpVAInputAPORT2YCH16 = _ACMP_INPUTSEL_VASEL_APORT2YCH16,
acmpVAInputAPORT2YCH18 = _ACMP_INPUTSEL_VASEL_APORT2YCH18,
acmpVAInputAPORT2YCH20 = _ACMP_INPUTSEL_VASEL_APORT2YCH20,
acmpVAInputAPORT2YCH22 = _ACMP_INPUTSEL_VASEL_APORT2YCH22,
acmpVAInputAPORT2YCH24 = _ACMP_INPUTSEL_VASEL_APORT2YCH24,
acmpVAInputAPORT2YCH26 = _ACMP_INPUTSEL_VASEL_APORT2YCH26,
acmpVAInputAPORT2YCH28 = _ACMP_INPUTSEL_VASEL_APORT2YCH28,
acmpVAInputAPORT2YCH30 = _ACMP_INPUTSEL_VASEL_APORT2YCH30,
acmpVAInputAPORT1XCH0 = _ACMP_INPUTSEL_VASEL_APORT1XCH0,
acmpVAInputAPORT1YCH1 = _ACMP_INPUTSEL_VASEL_APORT1YCH1,
acmpVAInputAPORT1XCH2 = _ACMP_INPUTSEL_VASEL_APORT1XCH2,
acmpVAInputAPORT1YCH3 = _ACMP_INPUTSEL_VASEL_APORT1YCH3,
acmpVAInputAPORT1XCH4 = _ACMP_INPUTSEL_VASEL_APORT1XCH4,
acmpVAInputAPORT1YCH5 = _ACMP_INPUTSEL_VASEL_APORT1YCH5,
acmpVAInputAPORT1XCH6 = _ACMP_INPUTSEL_VASEL_APORT1XCH6,
acmpVAInputAPORT1YCH7 = _ACMP_INPUTSEL_VASEL_APORT1YCH7,
acmpVAInputAPORT1XCH8 = _ACMP_INPUTSEL_VASEL_APORT1XCH8,
acmpVAInputAPORT1YCH9 = _ACMP_INPUTSEL_VASEL_APORT1YCH9,
acmpVAInputAPORT1XCH10 = _ACMP_INPUTSEL_VASEL_APORT1XCH10,
acmpVAInputAPORT1YCH11 = _ACMP_INPUTSEL_VASEL_APORT1YCH11,
acmpVAInputAPORT1XCH12 = _ACMP_INPUTSEL_VASEL_APORT1XCH12,
acmpVAInputAPORT1YCH13 = _ACMP_INPUTSEL_VASEL_APORT1YCH13,
acmpVAInputAPORT1XCH14 = _ACMP_INPUTSEL_VASEL_APORT1XCH14,
acmpVAInputAPORT1YCH15 = _ACMP_INPUTSEL_VASEL_APORT1YCH15,
acmpVAInputAPORT1XCH16 = _ACMP_INPUTSEL_VASEL_APORT1XCH16,
acmpVAInputAPORT1YCH17 = _ACMP_INPUTSEL_VASEL_APORT1YCH17,
acmpVAInputAPORT1XCH18 = _ACMP_INPUTSEL_VASEL_APORT1XCH18,
acmpVAInputAPORT1YCH19 = _ACMP_INPUTSEL_VASEL_APORT1YCH19,
acmpVAInputAPORT1XCH20 = _ACMP_INPUTSEL_VASEL_APORT1XCH20,
acmpVAInputAPORT1YCH21 = _ACMP_INPUTSEL_VASEL_APORT1YCH21,
acmpVAInputAPORT1XCH22 = _ACMP_INPUTSEL_VASEL_APORT1XCH22,
acmpVAInputAPORT1YCH23 = _ACMP_INPUTSEL_VASEL_APORT1YCH23,
acmpVAInputAPORT1XCH24 = _ACMP_INPUTSEL_VASEL_APORT1XCH24,
acmpVAInputAPORT1YCH25 = _ACMP_INPUTSEL_VASEL_APORT1YCH25,
acmpVAInputAPORT1XCH26 = _ACMP_INPUTSEL_VASEL_APORT1XCH26,
acmpVAInputAPORT1YCH27 = _ACMP_INPUTSEL_VASEL_APORT1YCH27,
acmpVAInputAPORT1XCH28 = _ACMP_INPUTSEL_VASEL_APORT1XCH28,
acmpVAInputAPORT1YCH29 = _ACMP_INPUTSEL_VASEL_APORT1YCH29,
acmpVAInputAPORT1XCH30 = _ACMP_INPUTSEL_VASEL_APORT1XCH30,
acmpVAInputAPORT1YCH31 = _ACMP_INPUTSEL_VASEL_APORT1YCH31
acmpVAInputVDD = _ACMP_INPUTSEL_VASEL_VDD, /**< Select VDD for the VA divider. */
acmpVAInputAPORT2YCH0 = _ACMP_INPUTSEL_VASEL_APORT2YCH0, /**< Select APORT2Y CHannel 0 for the VA divider. */
acmpVAInputAPORT2YCH2 = _ACMP_INPUTSEL_VASEL_APORT2YCH2, /**< Select APORT2Y CHannel 2 for the VA divider. */
acmpVAInputAPORT2YCH4 = _ACMP_INPUTSEL_VASEL_APORT2YCH4, /**< Select APORT2Y CHannel 4 for the VA divider. */
acmpVAInputAPORT2YCH6 = _ACMP_INPUTSEL_VASEL_APORT2YCH6, /**< Select APORT2Y CHannel 6 for the VA divider. */
acmpVAInputAPORT2YCH8 = _ACMP_INPUTSEL_VASEL_APORT2YCH8, /**< Select APORT2Y CHannel 8 for the VA divider. */
acmpVAInputAPORT2YCH10 = _ACMP_INPUTSEL_VASEL_APORT2YCH10, /**< Select APORT2Y CHannel 10 for the VA divider. */
acmpVAInputAPORT2YCH12 = _ACMP_INPUTSEL_VASEL_APORT2YCH12, /**< Select APORT2Y CHannel 12 for the VA divider. */
acmpVAInputAPORT2YCH14 = _ACMP_INPUTSEL_VASEL_APORT2YCH14, /**< Select APORT2Y CHannel 14 for the VA divider. */
acmpVAInputAPORT2YCH16 = _ACMP_INPUTSEL_VASEL_APORT2YCH16, /**< Select APORT2Y CHannel 16 for the VA divider. */
acmpVAInputAPORT2YCH18 = _ACMP_INPUTSEL_VASEL_APORT2YCH18, /**< Select APORT2Y CHannel 18 for the VA divider. */
acmpVAInputAPORT2YCH20 = _ACMP_INPUTSEL_VASEL_APORT2YCH20, /**< Select APORT2Y CHannel 20 for the VA divider. */
acmpVAInputAPORT2YCH22 = _ACMP_INPUTSEL_VASEL_APORT2YCH22, /**< Select APORT2Y CHannel 22 for the VA divider. */
acmpVAInputAPORT2YCH24 = _ACMP_INPUTSEL_VASEL_APORT2YCH24, /**< Select APORT2Y CHannel 24 for the VA divider. */
acmpVAInputAPORT2YCH26 = _ACMP_INPUTSEL_VASEL_APORT2YCH26, /**< Select APORT2Y CHannel 26 for the VA divider. */
acmpVAInputAPORT2YCH28 = _ACMP_INPUTSEL_VASEL_APORT2YCH28, /**< Select APORT2Y CHannel 28 for the VA divider. */
acmpVAInputAPORT2YCH30 = _ACMP_INPUTSEL_VASEL_APORT2YCH30, /**< Select APORT2Y CHannel 30 for the VA divider. */
acmpVAInputAPORT1XCH0 = _ACMP_INPUTSEL_VASEL_APORT1XCH0, /**< Select APORT1X CHannel 0 for the VA divider. */
acmpVAInputAPORT1YCH1 = _ACMP_INPUTSEL_VASEL_APORT1YCH1, /**< Select APORT1Y CHannel 1 for the VA divider. */
acmpVAInputAPORT1XCH2 = _ACMP_INPUTSEL_VASEL_APORT1XCH2, /**< Select APORT1X CHannel 2 for the VA divider. */
acmpVAInputAPORT1YCH3 = _ACMP_INPUTSEL_VASEL_APORT1YCH3, /**< Select APORT1Y CHannel 3 for the VA divider. */
acmpVAInputAPORT1XCH4 = _ACMP_INPUTSEL_VASEL_APORT1XCH4, /**< Select APORT1X CHannel 4 for the VA divider. */
acmpVAInputAPORT1YCH5 = _ACMP_INPUTSEL_VASEL_APORT1YCH5, /**< Select APORT1Y CHannel 5 for the VA divider. */
acmpVAInputAPORT1XCH6 = _ACMP_INPUTSEL_VASEL_APORT1XCH6, /**< Select APORT1X CHannel 6 for the VA divider. */
acmpVAInputAPORT1YCH7 = _ACMP_INPUTSEL_VASEL_APORT1YCH7, /**< Select APORT1Y CHannel 7 for the VA divider. */
acmpVAInputAPORT1XCH8 = _ACMP_INPUTSEL_VASEL_APORT1XCH8, /**< Select APORT1X CHannel 8 for the VA divider. */
acmpVAInputAPORT1YCH9 = _ACMP_INPUTSEL_VASEL_APORT1YCH9, /**< Select APORT1Y CHannel 9 for the VA divider. */
acmpVAInputAPORT1XCH10 = _ACMP_INPUTSEL_VASEL_APORT1XCH10, /**< Select APORT1X CHannel 10 for the VA divider. */
acmpVAInputAPORT1YCH11 = _ACMP_INPUTSEL_VASEL_APORT1YCH11, /**< Select APORT1Y CHannel 11 for the VA divider. */
acmpVAInputAPORT1XCH12 = _ACMP_INPUTSEL_VASEL_APORT1XCH12, /**< Select APORT1X CHannel 12 for the VA divider. */
acmpVAInputAPORT1YCH13 = _ACMP_INPUTSEL_VASEL_APORT1YCH13, /**< Select APORT1Y CHannel 13 for the VA divider. */
acmpVAInputAPORT1XCH14 = _ACMP_INPUTSEL_VASEL_APORT1XCH14, /**< Select APORT1X CHannel 14 for the VA divider. */
acmpVAInputAPORT1YCH15 = _ACMP_INPUTSEL_VASEL_APORT1YCH15, /**< Select APORT1Y CHannel 15 for the VA divider. */
acmpVAInputAPORT1XCH16 = _ACMP_INPUTSEL_VASEL_APORT1XCH16, /**< Select APORT1X CHannel 16 for the VA divider. */
acmpVAInputAPORT1YCH17 = _ACMP_INPUTSEL_VASEL_APORT1YCH17, /**< Select APORT1Y CHannel 17 for the VA divider. */
acmpVAInputAPORT1XCH18 = _ACMP_INPUTSEL_VASEL_APORT1XCH18, /**< Select APORT1X CHannel 18 for the VA divider. */
acmpVAInputAPORT1YCH19 = _ACMP_INPUTSEL_VASEL_APORT1YCH19, /**< Select APORT1Y CHannel 19 for the VA divider. */
acmpVAInputAPORT1XCH20 = _ACMP_INPUTSEL_VASEL_APORT1XCH20, /**< Select APORT1X CHannel 20 for the VA divider. */
acmpVAInputAPORT1YCH21 = _ACMP_INPUTSEL_VASEL_APORT1YCH21, /**< Select APORT1Y CHannel 21 for the VA divider. */
acmpVAInputAPORT1XCH22 = _ACMP_INPUTSEL_VASEL_APORT1XCH22, /**< Select APORT1X CHannel 22 for the VA divider. */
acmpVAInputAPORT1YCH23 = _ACMP_INPUTSEL_VASEL_APORT1YCH23, /**< Select APORT1Y CHannel 23 for the VA divider. */
acmpVAInputAPORT1XCH24 = _ACMP_INPUTSEL_VASEL_APORT1XCH24, /**< Select APORT1X CHannel 24 for the VA divider. */
acmpVAInputAPORT1YCH25 = _ACMP_INPUTSEL_VASEL_APORT1YCH25, /**< Select APORT1Y CHannel 25 for the VA divider. */
acmpVAInputAPORT1XCH26 = _ACMP_INPUTSEL_VASEL_APORT1XCH26, /**< Select APORT1X CHannel 26 for the VA divider. */
acmpVAInputAPORT1YCH27 = _ACMP_INPUTSEL_VASEL_APORT1YCH27, /**< Select APORT1Y CHannel 27 for the VA divider. */
acmpVAInputAPORT1XCH28 = _ACMP_INPUTSEL_VASEL_APORT1XCH28, /**< Select APORT1X CHannel 28 for the VA divider. */
acmpVAInputAPORT1YCH29 = _ACMP_INPUTSEL_VASEL_APORT1YCH29, /**< Select APORT1Y CHannel 29 for the VA divider. */
acmpVAInputAPORT1XCH30 = _ACMP_INPUTSEL_VASEL_APORT1XCH30, /**< Select APORT1X CHannel 30 for the VA divider. */
acmpVAInputAPORT1YCH31 = _ACMP_INPUTSEL_VASEL_APORT1YCH31 /**< Select APORT1Y CHannel 31 for the VA divider. */
} ACMP_VAInput_TypeDef;
#endif
@ -254,8 +254,8 @@ typedef enum {
* the VB divider.
*/
typedef enum {
acmpVBInput1V25 = _ACMP_INPUTSEL_VBSEL_1V25,
acmpVBInput2V5 = _ACMP_INPUTSEL_VBSEL_2V5
acmpVBInput1V25 = _ACMP_INPUTSEL_VBSEL_1V25, /**< Mode 1V25 for ACMP_INPUTSEL */
acmpVBInput2V5 = _ACMP_INPUTSEL_VBSEL_2V5 /**< Mode 2V5 for ACMP_INPUTSEL */
} ACMP_VBInput_TypeDef;
#endif
@ -264,269 +264,275 @@ typedef enum {
* ACMP Low-Power Input Selection.
*/
typedef enum {
acmpVLPInputVADIV = _ACMP_INPUTSEL_VLPSEL_VADIV,
acmpVLPInputVBDIV = _ACMP_INPUTSEL_VLPSEL_VBDIV
acmpVLPInputVADIV = _ACMP_INPUTSEL_VLPSEL_VADIV, /**< Mode VADIV for ACMP_INPUTSEL */
acmpVLPInputVBDIV = _ACMP_INPUTSEL_VLPSEL_VBDIV /**< Mode VBDIV for ACMP_INPUTSEL */
} ACMP_VLPInput_Typedef;
#endif
#if defined(_ACMP_INPUTCTRL_MASK)
/** ACMP Input Selection. */
typedef enum {
acmpInputVSS = _ACMP_INPUTCTRL_POSSEL_VSS,
acmpInputVREFDIVAVDD = _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD,
acmpInputVREFDIVAVDDLP = _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP,
acmpInputVREFDIV1V25 = _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25,
acmpInputVREFDIV1V25LP = _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP,
acmpInputVREFDIV2V5 = _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5,
acmpInputVREFDIV2V5LP = _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP,
acmpInputVSENSE01DIV4 = _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4,
acmpInputVSENSE01DIV4LP = _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP,
acmpInputVSENSE11DIV4 = _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4,
acmpInputVSENSE11DIV4LP = _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP,
acmpInputCAPSENSE = _ACMP_INPUTCTRL_NEGSEL_CAPSENSE,
acmpInputVSS = _ACMP_INPUTCTRL_POSSEL_VSS, /**< Select VSS. */
acmpInputVREFDIVAVDD = _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD, /**< Select Divided AVDD. */
acmpInputVREFDIVAVDDLP = _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP, /**< Select Low-Power Divided AVDD. */
acmpInputVREFDIV1V25 = _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25, /**< Select Divided 1V25 reference. */
acmpInputVREFDIV1V25LP = _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP, /**< Select Low-power Divided 1V25 reference. */
acmpInputVREFDIV2V5 = _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5, /**< Select Divided 2V5 reference. */
acmpInputVREFDIV2V5LP = _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP, /**< Select Low-power Divided 2V5 reference. */
acmpInputVSENSE01DIV4 = _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4, /**< Select VSENSE0 divided by 4. */
acmpInputVSENSE01DIV4LP = _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP, /**< Select Low-power VSENSE0 divided by 4. */
acmpInputVSENSE11DIV4 = _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4, /**< VSENSE1 divided by 4. */
acmpInputVSENSE11DIV4LP = _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP, /**< Low-power VSENSE1 divided by 4. */
acmpInputCAPSENSE = _ACMP_INPUTCTRL_NEGSEL_CAPSENSE, /**< Select Low-Power Divided AVDD. */
#if defined(_ACMP_INPUTCTRL_POSSEL_VDACOUT0)
acmpInputVDACOUT0 = _ACMP_INPUTCTRL_POSSEL_VDACOUT0,
acmpInputVDACOUT1 = _ACMP_INPUTCTRL_POSSEL_VDACOUT1,
acmpInputVDACOUT0 = _ACMP_INPUTCTRL_POSSEL_VDACOUT0, /**< Select VDAC0 channel 0 output. */
acmpInputVDACOUT1 = _ACMP_INPUTCTRL_POSSEL_VDACOUT1, /**< Select VDAC0 channel 1 output. */
#endif
acmpInputPA0 = _ACMP_INPUTCTRL_POSSEL_PA0,
acmpInputPA1 = _ACMP_INPUTCTRL_POSSEL_PA1,
acmpInputPA2 = _ACMP_INPUTCTRL_POSSEL_PA2,
acmpInputPA3 = _ACMP_INPUTCTRL_POSSEL_PA3,
acmpInputPA4 = _ACMP_INPUTCTRL_POSSEL_PA4,
acmpInputPA5 = _ACMP_INPUTCTRL_POSSEL_PA5,
acmpInputPA6 = _ACMP_INPUTCTRL_POSSEL_PA6,
acmpInputPA7 = _ACMP_INPUTCTRL_POSSEL_PA7,
acmpInputPA8 = _ACMP_INPUTCTRL_POSSEL_PA8,
acmpInputPA9 = _ACMP_INPUTCTRL_POSSEL_PA9,
acmpInputPA10 = _ACMP_INPUTCTRL_POSSEL_PA10,
acmpInputPA11 = _ACMP_INPUTCTRL_POSSEL_PA11,
acmpInputPA12 = _ACMP_INPUTCTRL_POSSEL_PA12,
acmpInputPA13 = _ACMP_INPUTCTRL_POSSEL_PA13,
acmpInputPA14 = _ACMP_INPUTCTRL_POSSEL_PA14,
acmpInputPA15 = _ACMP_INPUTCTRL_POSSEL_PA15,
acmpInputPB0 = _ACMP_INPUTCTRL_POSSEL_PB0,
acmpInputPB1 = _ACMP_INPUTCTRL_POSSEL_PB1,
acmpInputPB2 = _ACMP_INPUTCTRL_POSSEL_PB2,
acmpInputPB3 = _ACMP_INPUTCTRL_POSSEL_PB3,
acmpInputPB4 = _ACMP_INPUTCTRL_POSSEL_PB4,
acmpInputPB5 = _ACMP_INPUTCTRL_POSSEL_PB5,
acmpInputPB6 = _ACMP_INPUTCTRL_POSSEL_PB6,
acmpInputPB7 = _ACMP_INPUTCTRL_POSSEL_PB7,
acmpInputPB8 = _ACMP_INPUTCTRL_POSSEL_PB8,
acmpInputPB9 = _ACMP_INPUTCTRL_POSSEL_PB9,
acmpInputPB10 = _ACMP_INPUTCTRL_POSSEL_PB10,
acmpInputPB11 = _ACMP_INPUTCTRL_POSSEL_PB11,
acmpInputPB12 = _ACMP_INPUTCTRL_POSSEL_PB12,
acmpInputPB13 = _ACMP_INPUTCTRL_POSSEL_PB13,
acmpInputPB14 = _ACMP_INPUTCTRL_POSSEL_PB14,
acmpInputPB15 = _ACMP_INPUTCTRL_POSSEL_PB15,
acmpInputPC0 = _ACMP_INPUTCTRL_POSSEL_PC0,
acmpInputPC1 = _ACMP_INPUTCTRL_POSSEL_PC1,
acmpInputPC2 = _ACMP_INPUTCTRL_POSSEL_PC2,
acmpInputPC3 = _ACMP_INPUTCTRL_POSSEL_PC3,
acmpInputPC4 = _ACMP_INPUTCTRL_POSSEL_PC4,
acmpInputPC5 = _ACMP_INPUTCTRL_POSSEL_PC5,
acmpInputPC6 = _ACMP_INPUTCTRL_POSSEL_PC6,
acmpInputPC7 = _ACMP_INPUTCTRL_POSSEL_PC7,
acmpInputPC8 = _ACMP_INPUTCTRL_POSSEL_PC8,
acmpInputPC9 = _ACMP_INPUTCTRL_POSSEL_PC9,
acmpInputPC10 = _ACMP_INPUTCTRL_POSSEL_PC10,
acmpInputPC11 = _ACMP_INPUTCTRL_POSSEL_PC11,
acmpInputPC12 = _ACMP_INPUTCTRL_POSSEL_PC12,
acmpInputPC13 = _ACMP_INPUTCTRL_POSSEL_PC13,
acmpInputPC14 = _ACMP_INPUTCTRL_POSSEL_PC14,
acmpInputPC15 = _ACMP_INPUTCTRL_POSSEL_PC15,
acmpInputPD0 = _ACMP_INPUTCTRL_POSSEL_PD0,
acmpInputPD1 = _ACMP_INPUTCTRL_POSSEL_PD1,
acmpInputPD2 = _ACMP_INPUTCTRL_POSSEL_PD2,
acmpInputPD3 = _ACMP_INPUTCTRL_POSSEL_PD3,
acmpInputPD4 = _ACMP_INPUTCTRL_POSSEL_PD4,
acmpInputPD5 = _ACMP_INPUTCTRL_POSSEL_PD5,
acmpInputPD6 = _ACMP_INPUTCTRL_POSSEL_PD6,
acmpInputPD7 = _ACMP_INPUTCTRL_POSSEL_PD7,
acmpInputPD8 = _ACMP_INPUTCTRL_POSSEL_PD8,
acmpInputPD9 = _ACMP_INPUTCTRL_POSSEL_PD9,
acmpInputPD10 = _ACMP_INPUTCTRL_POSSEL_PD10,
acmpInputPD11 = _ACMP_INPUTCTRL_POSSEL_PD11,
acmpInputPD12 = _ACMP_INPUTCTRL_POSSEL_PD12,
acmpInputPD13 = _ACMP_INPUTCTRL_POSSEL_PD13,
acmpInputPD14 = _ACMP_INPUTCTRL_POSSEL_PD14,
acmpInputPD15 = _ACMP_INPUTCTRL_POSSEL_PD15,
#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2)
acmpInputEXTPA = _ACMP_INPUTCTRL_POSSEL_EXTPA, /**< Select external interface, base is PA0. */
acmpInputEXTPB = _ACMP_INPUTCTRL_POSSEL_EXTPB, /**< Select external interface, base is PB0. */
acmpInputEXTPC = _ACMP_INPUTCTRL_POSSEL_EXTPC, /**< Select external interface, base is PC0. */
acmpInputEXTPD = _ACMP_INPUTCTRL_POSSEL_EXTPD, /**< Select external interface, base is PD0. */
#endif
acmpInputPA0 = _ACMP_INPUTCTRL_POSSEL_PA0, /**< Select Port A Pin0. */
acmpInputPA1 = _ACMP_INPUTCTRL_POSSEL_PA1, /**< Select Port A Pin1. */
acmpInputPA2 = _ACMP_INPUTCTRL_POSSEL_PA2, /**< Select Port A Pin2. */
acmpInputPA3 = _ACMP_INPUTCTRL_POSSEL_PA3, /**< Select Port A Pin3. */
acmpInputPA4 = _ACMP_INPUTCTRL_POSSEL_PA4, /**< Select Port A Pin4. */
acmpInputPA5 = _ACMP_INPUTCTRL_POSSEL_PA5, /**< Select Port A Pin5. */
acmpInputPA6 = _ACMP_INPUTCTRL_POSSEL_PA6, /**< Select Port A Pin6. */
acmpInputPA7 = _ACMP_INPUTCTRL_POSSEL_PA7, /**< Select Port A Pin7. */
acmpInputPA8 = _ACMP_INPUTCTRL_POSSEL_PA8, /**< Select Port A Pin8. */
acmpInputPA9 = _ACMP_INPUTCTRL_POSSEL_PA9, /**< Select Port A Pin9. */
acmpInputPA10 = _ACMP_INPUTCTRL_POSSEL_PA10, /**< Select Port A Pin10. */
acmpInputPA11 = _ACMP_INPUTCTRL_POSSEL_PA11, /**< Select Port A Pin11. */
acmpInputPA12 = _ACMP_INPUTCTRL_POSSEL_PA12, /**< Select Port A Pin12. */
acmpInputPA13 = _ACMP_INPUTCTRL_POSSEL_PA13, /**< Select Port A Pin13. */
acmpInputPA14 = _ACMP_INPUTCTRL_POSSEL_PA14, /**< Select Port A Pin14. */
acmpInputPA15 = _ACMP_INPUTCTRL_POSSEL_PA15, /**< Select Port A Pin15. */
acmpInputPB0 = _ACMP_INPUTCTRL_POSSEL_PB0, /**< Select Port B Pin0. */
acmpInputPB1 = _ACMP_INPUTCTRL_POSSEL_PB1, /**< Select Port B Pin1. */
acmpInputPB2 = _ACMP_INPUTCTRL_POSSEL_PB2, /**< Select Port B Pin2. */
acmpInputPB3 = _ACMP_INPUTCTRL_POSSEL_PB3, /**< Select Port B Pin3. */
acmpInputPB4 = _ACMP_INPUTCTRL_POSSEL_PB4, /**< Select Port B Pin4. */
acmpInputPB5 = _ACMP_INPUTCTRL_POSSEL_PB5, /**< Select Port B Pin5. */
acmpInputPB6 = _ACMP_INPUTCTRL_POSSEL_PB6, /**< Select Port B Pin6. */
acmpInputPB7 = _ACMP_INPUTCTRL_POSSEL_PB7, /**< Select Port B Pin7. */
acmpInputPB8 = _ACMP_INPUTCTRL_POSSEL_PB8, /**< Select Port B Pin8. */
acmpInputPB9 = _ACMP_INPUTCTRL_POSSEL_PB9, /**< Select Port B Pin9. */
acmpInputPB10 = _ACMP_INPUTCTRL_POSSEL_PB10, /**< Select Port B Pin10. */
acmpInputPB11 = _ACMP_INPUTCTRL_POSSEL_PB11, /**< Select Port B Pin11. */
acmpInputPB12 = _ACMP_INPUTCTRL_POSSEL_PB12, /**< Select Port B Pin12. */
acmpInputPB13 = _ACMP_INPUTCTRL_POSSEL_PB13, /**< Select Port B Pin13. */
acmpInputPB14 = _ACMP_INPUTCTRL_POSSEL_PB14, /**< Select Port B Pin14. */
acmpInputPB15 = _ACMP_INPUTCTRL_POSSEL_PB15, /**< Select Port B Pin15. */
acmpInputPC0 = _ACMP_INPUTCTRL_POSSEL_PC0, /**< Select Port C Pin0. */
acmpInputPC1 = _ACMP_INPUTCTRL_POSSEL_PC1, /**< Select Port C Pin1. */
acmpInputPC2 = _ACMP_INPUTCTRL_POSSEL_PC2, /**< Select Port C Pin2. */
acmpInputPC3 = _ACMP_INPUTCTRL_POSSEL_PC3, /**< Select Port C Pin3. */
acmpInputPC4 = _ACMP_INPUTCTRL_POSSEL_PC4, /**< Select Port C Pin4. */
acmpInputPC5 = _ACMP_INPUTCTRL_POSSEL_PC5, /**< Select Port C Pin5. */
acmpInputPC6 = _ACMP_INPUTCTRL_POSSEL_PC6, /**< Select Port C Pin6. */
acmpInputPC7 = _ACMP_INPUTCTRL_POSSEL_PC7, /**< Select Port C Pin7. */
acmpInputPC8 = _ACMP_INPUTCTRL_POSSEL_PC8, /**< Select Port C Pin8. */
acmpInputPC9 = _ACMP_INPUTCTRL_POSSEL_PC9, /**< Select Port C Pin9. */
acmpInputPC10 = _ACMP_INPUTCTRL_POSSEL_PC10, /**< Select Port C Pin10. */
acmpInputPC11 = _ACMP_INPUTCTRL_POSSEL_PC11, /**< Select Port C Pin11. */
acmpInputPC12 = _ACMP_INPUTCTRL_POSSEL_PC12, /**< Select Port C Pin12. */
acmpInputPC13 = _ACMP_INPUTCTRL_POSSEL_PC13, /**< Select Port C Pin13. */
acmpInputPC14 = _ACMP_INPUTCTRL_POSSEL_PC14, /**< Select Port C Pin14. */
acmpInputPC15 = _ACMP_INPUTCTRL_POSSEL_PC15, /**< Select Port C Pin15. */
acmpInputPD0 = _ACMP_INPUTCTRL_POSSEL_PD0, /**< Select Port D Pin0. */
acmpInputPD1 = _ACMP_INPUTCTRL_POSSEL_PD1, /**< Select Port D Pin1. */
acmpInputPD2 = _ACMP_INPUTCTRL_POSSEL_PD2, /**< Select Port D Pin2. */
acmpInputPD3 = _ACMP_INPUTCTRL_POSSEL_PD3, /**< Select Port D Pin3. */
acmpInputPD4 = _ACMP_INPUTCTRL_POSSEL_PD4, /**< Select Port D Pin4. */
acmpInputPD5 = _ACMP_INPUTCTRL_POSSEL_PD5, /**< Select Port D Pin5. */
acmpInputPD6 = _ACMP_INPUTCTRL_POSSEL_PD6, /**< Select Port D Pin6. */
acmpInputPD7 = _ACMP_INPUTCTRL_POSSEL_PD7, /**< Select Port D Pin7. */
acmpInputPD8 = _ACMP_INPUTCTRL_POSSEL_PD8, /**< Select Port D Pin8. */
acmpInputPD9 = _ACMP_INPUTCTRL_POSSEL_PD9, /**< Select Port D Pin9. */
acmpInputPD10 = _ACMP_INPUTCTRL_POSSEL_PD10, /**< Select Port D Pin10. */
acmpInputPD11 = _ACMP_INPUTCTRL_POSSEL_PD11, /**< Select Port D Pin11. */
acmpInputPD12 = _ACMP_INPUTCTRL_POSSEL_PD12, /**< Select Port D Pin12. */
acmpInputPD13 = _ACMP_INPUTCTRL_POSSEL_PD13, /**< Select Port D Pin13. */
acmpInputPD14 = _ACMP_INPUTCTRL_POSSEL_PD14, /**< Select Port D Pin14. */
acmpInputPD15 = _ACMP_INPUTCTRL_POSSEL_PD15, /**< Select Port D Pin15. */
} ACMP_Channel_TypeDef;
#elif defined(_ACMP_INPUTSEL_POSSEL_APORT0XCH0)
/** ACMP Input Selection. */
typedef enum {
acmpInputAPORT0XCH0 = _ACMP_INPUTSEL_POSSEL_APORT0XCH0,
acmpInputAPORT0XCH1 = _ACMP_INPUTSEL_POSSEL_APORT0XCH1,
acmpInputAPORT0XCH2 = _ACMP_INPUTSEL_POSSEL_APORT0XCH2,
acmpInputAPORT0XCH3 = _ACMP_INPUTSEL_POSSEL_APORT0XCH3,
acmpInputAPORT0XCH4 = _ACMP_INPUTSEL_POSSEL_APORT0XCH4,
acmpInputAPORT0XCH5 = _ACMP_INPUTSEL_POSSEL_APORT0XCH5,
acmpInputAPORT0XCH6 = _ACMP_INPUTSEL_POSSEL_APORT0XCH6,
acmpInputAPORT0XCH7 = _ACMP_INPUTSEL_POSSEL_APORT0XCH7,
acmpInputAPORT0XCH8 = _ACMP_INPUTSEL_POSSEL_APORT0XCH8,
acmpInputAPORT0XCH9 = _ACMP_INPUTSEL_POSSEL_APORT0XCH9,
acmpInputAPORT0XCH10 = _ACMP_INPUTSEL_POSSEL_APORT0XCH10,
acmpInputAPORT0XCH11 = _ACMP_INPUTSEL_POSSEL_APORT0XCH11,
acmpInputAPORT0XCH12 = _ACMP_INPUTSEL_POSSEL_APORT0XCH12,
acmpInputAPORT0XCH13 = _ACMP_INPUTSEL_POSSEL_APORT0XCH13,
acmpInputAPORT0XCH14 = _ACMP_INPUTSEL_POSSEL_APORT0XCH14,
acmpInputAPORT0XCH15 = _ACMP_INPUTSEL_POSSEL_APORT0XCH15,
acmpInputAPORT0YCH0 = _ACMP_INPUTSEL_POSSEL_APORT0YCH0,
acmpInputAPORT0YCH1 = _ACMP_INPUTSEL_POSSEL_APORT0YCH1,
acmpInputAPORT0YCH2 = _ACMP_INPUTSEL_POSSEL_APORT0YCH2,
acmpInputAPORT0YCH3 = _ACMP_INPUTSEL_POSSEL_APORT0YCH3,
acmpInputAPORT0YCH4 = _ACMP_INPUTSEL_POSSEL_APORT0YCH4,
acmpInputAPORT0YCH5 = _ACMP_INPUTSEL_POSSEL_APORT0YCH5,
acmpInputAPORT0YCH6 = _ACMP_INPUTSEL_POSSEL_APORT0YCH6,
acmpInputAPORT0YCH7 = _ACMP_INPUTSEL_POSSEL_APORT0YCH7,
acmpInputAPORT0YCH8 = _ACMP_INPUTSEL_POSSEL_APORT0YCH8,
acmpInputAPORT0YCH9 = _ACMP_INPUTSEL_POSSEL_APORT0YCH9,
acmpInputAPORT0YCH10 = _ACMP_INPUTSEL_POSSEL_APORT0YCH10,
acmpInputAPORT0YCH11 = _ACMP_INPUTSEL_POSSEL_APORT0YCH11,
acmpInputAPORT0YCH12 = _ACMP_INPUTSEL_POSSEL_APORT0YCH12,
acmpInputAPORT0YCH13 = _ACMP_INPUTSEL_POSSEL_APORT0YCH13,
acmpInputAPORT0YCH14 = _ACMP_INPUTSEL_POSSEL_APORT0YCH14,
acmpInputAPORT0YCH15 = _ACMP_INPUTSEL_POSSEL_APORT0YCH15,
acmpInputAPORT1XCH0 = _ACMP_INPUTSEL_POSSEL_APORT1XCH0,
acmpInputAPORT1YCH1 = _ACMP_INPUTSEL_POSSEL_APORT1YCH1,
acmpInputAPORT1XCH2 = _ACMP_INPUTSEL_POSSEL_APORT1XCH2,
acmpInputAPORT1YCH3 = _ACMP_INPUTSEL_POSSEL_APORT1YCH3,
acmpInputAPORT1XCH4 = _ACMP_INPUTSEL_POSSEL_APORT1XCH4,
acmpInputAPORT1YCH5 = _ACMP_INPUTSEL_POSSEL_APORT1YCH5,
acmpInputAPORT1XCH6 = _ACMP_INPUTSEL_POSSEL_APORT1XCH6,
acmpInputAPORT1YCH7 = _ACMP_INPUTSEL_POSSEL_APORT1YCH7,
acmpInputAPORT1XCH8 = _ACMP_INPUTSEL_POSSEL_APORT1XCH8,
acmpInputAPORT1YCH9 = _ACMP_INPUTSEL_POSSEL_APORT1YCH9,
acmpInputAPORT1XCH10 = _ACMP_INPUTSEL_POSSEL_APORT1XCH10,
acmpInputAPORT1YCH11 = _ACMP_INPUTSEL_POSSEL_APORT1YCH11,
acmpInputAPORT1XCH12 = _ACMP_INPUTSEL_POSSEL_APORT1XCH12,
acmpInputAPORT1YCH13 = _ACMP_INPUTSEL_POSSEL_APORT1YCH13,
acmpInputAPORT1XCH14 = _ACMP_INPUTSEL_POSSEL_APORT1XCH14,
acmpInputAPORT1YCH15 = _ACMP_INPUTSEL_POSSEL_APORT1YCH15,
acmpInputAPORT1XCH16 = _ACMP_INPUTSEL_POSSEL_APORT1XCH16,
acmpInputAPORT1YCH17 = _ACMP_INPUTSEL_POSSEL_APORT1YCH17,
acmpInputAPORT1XCH18 = _ACMP_INPUTSEL_POSSEL_APORT1XCH18,
acmpInputAPORT1YCH19 = _ACMP_INPUTSEL_POSSEL_APORT1YCH19,
acmpInputAPORT1XCH20 = _ACMP_INPUTSEL_POSSEL_APORT1XCH20,
acmpInputAPORT1YCH21 = _ACMP_INPUTSEL_POSSEL_APORT1YCH21,
acmpInputAPORT1XCH22 = _ACMP_INPUTSEL_POSSEL_APORT1XCH22,
acmpInputAPORT1YCH23 = _ACMP_INPUTSEL_POSSEL_APORT1YCH23,
acmpInputAPORT1XCH24 = _ACMP_INPUTSEL_POSSEL_APORT1XCH24,
acmpInputAPORT1YCH25 = _ACMP_INPUTSEL_POSSEL_APORT1YCH25,
acmpInputAPORT1XCH26 = _ACMP_INPUTSEL_POSSEL_APORT1XCH26,
acmpInputAPORT1YCH27 = _ACMP_INPUTSEL_POSSEL_APORT1YCH27,
acmpInputAPORT1XCH28 = _ACMP_INPUTSEL_POSSEL_APORT1XCH28,
acmpInputAPORT1YCH29 = _ACMP_INPUTSEL_POSSEL_APORT1YCH29,
acmpInputAPORT1XCH30 = _ACMP_INPUTSEL_POSSEL_APORT1XCH30,
acmpInputAPORT1YCH31 = _ACMP_INPUTSEL_POSSEL_APORT1YCH31,
acmpInputAPORT2YCH0 = _ACMP_INPUTSEL_POSSEL_APORT2YCH0,
acmpInputAPORT2XCH1 = _ACMP_INPUTSEL_POSSEL_APORT2XCH1,
acmpInputAPORT2YCH2 = _ACMP_INPUTSEL_POSSEL_APORT2YCH2,
acmpInputAPORT2XCH3 = _ACMP_INPUTSEL_POSSEL_APORT2XCH3,
acmpInputAPORT2YCH4 = _ACMP_INPUTSEL_POSSEL_APORT2YCH4,
acmpInputAPORT2XCH5 = _ACMP_INPUTSEL_POSSEL_APORT2XCH5,
acmpInputAPORT2YCH6 = _ACMP_INPUTSEL_POSSEL_APORT2YCH6,
acmpInputAPORT2XCH7 = _ACMP_INPUTSEL_POSSEL_APORT2XCH7,
acmpInputAPORT2YCH8 = _ACMP_INPUTSEL_POSSEL_APORT2YCH8,
acmpInputAPORT2XCH9 = _ACMP_INPUTSEL_POSSEL_APORT2XCH9,
acmpInputAPORT2YCH10 = _ACMP_INPUTSEL_POSSEL_APORT2YCH10,
acmpInputAPORT2XCH11 = _ACMP_INPUTSEL_POSSEL_APORT2XCH11,
acmpInputAPORT2YCH12 = _ACMP_INPUTSEL_POSSEL_APORT2YCH12,
acmpInputAPORT2XCH13 = _ACMP_INPUTSEL_POSSEL_APORT2XCH13,
acmpInputAPORT2YCH14 = _ACMP_INPUTSEL_POSSEL_APORT2YCH14,
acmpInputAPORT2XCH15 = _ACMP_INPUTSEL_POSSEL_APORT2XCH15,
acmpInputAPORT2YCH16 = _ACMP_INPUTSEL_POSSEL_APORT2YCH16,
acmpInputAPORT2XCH17 = _ACMP_INPUTSEL_POSSEL_APORT2XCH17,
acmpInputAPORT2YCH18 = _ACMP_INPUTSEL_POSSEL_APORT2YCH18,
acmpInputAPORT2XCH19 = _ACMP_INPUTSEL_POSSEL_APORT2XCH19,
acmpInputAPORT2YCH20 = _ACMP_INPUTSEL_POSSEL_APORT2YCH20,
acmpInputAPORT2XCH21 = _ACMP_INPUTSEL_POSSEL_APORT2XCH21,
acmpInputAPORT2YCH22 = _ACMP_INPUTSEL_POSSEL_APORT2YCH22,
acmpInputAPORT2XCH23 = _ACMP_INPUTSEL_POSSEL_APORT2XCH23,
acmpInputAPORT2YCH24 = _ACMP_INPUTSEL_POSSEL_APORT2YCH24,
acmpInputAPORT2XCH25 = _ACMP_INPUTSEL_POSSEL_APORT2XCH25,
acmpInputAPORT2YCH26 = _ACMP_INPUTSEL_POSSEL_APORT2YCH26,
acmpInputAPORT2XCH27 = _ACMP_INPUTSEL_POSSEL_APORT2XCH27,
acmpInputAPORT2YCH28 = _ACMP_INPUTSEL_POSSEL_APORT2YCH28,
acmpInputAPORT2XCH29 = _ACMP_INPUTSEL_POSSEL_APORT2XCH29,
acmpInputAPORT2YCH30 = _ACMP_INPUTSEL_POSSEL_APORT2YCH30,
acmpInputAPORT2XCH31 = _ACMP_INPUTSEL_POSSEL_APORT2XCH31,
acmpInputAPORT3XCH0 = _ACMP_INPUTSEL_POSSEL_APORT3XCH0,
acmpInputAPORT3YCH1 = _ACMP_INPUTSEL_POSSEL_APORT3YCH1,
acmpInputAPORT3XCH2 = _ACMP_INPUTSEL_POSSEL_APORT3XCH2,
acmpInputAPORT3YCH3 = _ACMP_INPUTSEL_POSSEL_APORT3YCH3,
acmpInputAPORT3XCH4 = _ACMP_INPUTSEL_POSSEL_APORT3XCH4,
acmpInputAPORT3YCH5 = _ACMP_INPUTSEL_POSSEL_APORT3YCH5,
acmpInputAPORT3XCH6 = _ACMP_INPUTSEL_POSSEL_APORT3XCH6,
acmpInputAPORT3YCH7 = _ACMP_INPUTSEL_POSSEL_APORT3YCH7,
acmpInputAPORT3XCH8 = _ACMP_INPUTSEL_POSSEL_APORT3XCH8,
acmpInputAPORT3YCH9 = _ACMP_INPUTSEL_POSSEL_APORT3YCH9,
acmpInputAPORT3XCH10 = _ACMP_INPUTSEL_POSSEL_APORT3XCH10,
acmpInputAPORT3YCH11 = _ACMP_INPUTSEL_POSSEL_APORT3YCH11,
acmpInputAPORT3XCH12 = _ACMP_INPUTSEL_POSSEL_APORT3XCH12,
acmpInputAPORT3YCH13 = _ACMP_INPUTSEL_POSSEL_APORT3YCH13,
acmpInputAPORT3XCH14 = _ACMP_INPUTSEL_POSSEL_APORT3XCH14,
acmpInputAPORT3YCH15 = _ACMP_INPUTSEL_POSSEL_APORT3YCH15,
acmpInputAPORT3XCH16 = _ACMP_INPUTSEL_POSSEL_APORT3XCH16,
acmpInputAPORT3YCH17 = _ACMP_INPUTSEL_POSSEL_APORT3YCH17,
acmpInputAPORT3XCH18 = _ACMP_INPUTSEL_POSSEL_APORT3XCH18,
acmpInputAPORT3YCH19 = _ACMP_INPUTSEL_POSSEL_APORT3YCH19,
acmpInputAPORT3XCH20 = _ACMP_INPUTSEL_POSSEL_APORT3XCH20,
acmpInputAPORT3YCH21 = _ACMP_INPUTSEL_POSSEL_APORT3YCH21,
acmpInputAPORT3XCH22 = _ACMP_INPUTSEL_POSSEL_APORT3XCH22,
acmpInputAPORT3YCH23 = _ACMP_INPUTSEL_POSSEL_APORT3YCH23,
acmpInputAPORT3XCH24 = _ACMP_INPUTSEL_POSSEL_APORT3XCH24,
acmpInputAPORT3YCH25 = _ACMP_INPUTSEL_POSSEL_APORT3YCH25,
acmpInputAPORT3XCH26 = _ACMP_INPUTSEL_POSSEL_APORT3XCH26,
acmpInputAPORT3YCH27 = _ACMP_INPUTSEL_POSSEL_APORT3YCH27,
acmpInputAPORT3XCH28 = _ACMP_INPUTSEL_POSSEL_APORT3XCH28,
acmpInputAPORT3YCH29 = _ACMP_INPUTSEL_POSSEL_APORT3YCH29,
acmpInputAPORT3XCH30 = _ACMP_INPUTSEL_POSSEL_APORT3XCH30,
acmpInputAPORT3YCH31 = _ACMP_INPUTSEL_POSSEL_APORT3YCH31,
acmpInputAPORT4YCH0 = _ACMP_INPUTSEL_POSSEL_APORT4YCH0,
acmpInputAPORT4XCH1 = _ACMP_INPUTSEL_POSSEL_APORT4XCH1,
acmpInputAPORT4YCH2 = _ACMP_INPUTSEL_POSSEL_APORT4YCH2,
acmpInputAPORT4XCH3 = _ACMP_INPUTSEL_POSSEL_APORT4XCH3,
acmpInputAPORT4YCH4 = _ACMP_INPUTSEL_POSSEL_APORT4YCH4,
acmpInputAPORT4XCH5 = _ACMP_INPUTSEL_POSSEL_APORT4XCH5,
acmpInputAPORT4YCH6 = _ACMP_INPUTSEL_POSSEL_APORT4YCH6,
acmpInputAPORT4XCH7 = _ACMP_INPUTSEL_POSSEL_APORT4XCH7,
acmpInputAPORT4YCH8 = _ACMP_INPUTSEL_POSSEL_APORT4YCH8,
acmpInputAPORT4XCH9 = _ACMP_INPUTSEL_POSSEL_APORT4XCH9,
acmpInputAPORT4YCH10 = _ACMP_INPUTSEL_POSSEL_APORT4YCH10,
acmpInputAPORT4XCH11 = _ACMP_INPUTSEL_POSSEL_APORT4XCH11,
acmpInputAPORT4YCH12 = _ACMP_INPUTSEL_POSSEL_APORT4YCH12,
acmpInputAPORT4XCH13 = _ACMP_INPUTSEL_POSSEL_APORT4XCH13,
acmpInputAPORT4YCH16 = _ACMP_INPUTSEL_POSSEL_APORT4YCH16,
acmpInputAPORT4XCH17 = _ACMP_INPUTSEL_POSSEL_APORT4XCH17,
acmpInputAPORT4YCH18 = _ACMP_INPUTSEL_POSSEL_APORT4YCH18,
acmpInputAPORT4XCH19 = _ACMP_INPUTSEL_POSSEL_APORT4XCH19,
acmpInputAPORT4YCH20 = _ACMP_INPUTSEL_POSSEL_APORT4YCH20,
acmpInputAPORT4XCH21 = _ACMP_INPUTSEL_POSSEL_APORT4XCH21,
acmpInputAPORT4YCH22 = _ACMP_INPUTSEL_POSSEL_APORT4YCH22,
acmpInputAPORT4XCH23 = _ACMP_INPUTSEL_POSSEL_APORT4XCH23,
acmpInputAPORT4YCH24 = _ACMP_INPUTSEL_POSSEL_APORT4YCH24,
acmpInputAPORT4XCH25 = _ACMP_INPUTSEL_POSSEL_APORT4XCH25,
acmpInputAPORT4YCH26 = _ACMP_INPUTSEL_POSSEL_APORT4YCH26,
acmpInputAPORT4XCH27 = _ACMP_INPUTSEL_POSSEL_APORT4XCH27,
acmpInputAPORT4YCH28 = _ACMP_INPUTSEL_POSSEL_APORT4YCH28,
acmpInputAPORT4XCH29 = _ACMP_INPUTSEL_POSSEL_APORT4XCH29,
acmpInputAPORT4YCH30 = _ACMP_INPUTSEL_POSSEL_APORT4YCH30,
acmpInputAPORT4YCH14 = _ACMP_INPUTSEL_POSSEL_APORT4YCH14,
acmpInputAPORT4XCH15 = _ACMP_INPUTSEL_POSSEL_APORT4XCH15,
acmpInputAPORT4XCH31 = _ACMP_INPUTSEL_POSSEL_APORT4XCH31,
acmpInputAPORT0XCH0 = _ACMP_INPUTSEL_POSSEL_APORT0XCH0, /**< Select Dedicated APORT0X CHannel 0. */
acmpInputAPORT0XCH1 = _ACMP_INPUTSEL_POSSEL_APORT0XCH1, /**< Select Dedicated APORT0X CHannel 1. */
acmpInputAPORT0XCH2 = _ACMP_INPUTSEL_POSSEL_APORT0XCH2, /**< Select Dedicated APORT0X CHannel 2. */
acmpInputAPORT0XCH3 = _ACMP_INPUTSEL_POSSEL_APORT0XCH3, /**< Select Dedicated APORT0X CHannel 3. */
acmpInputAPORT0XCH4 = _ACMP_INPUTSEL_POSSEL_APORT0XCH4, /**< Select Dedicated APORT0X CHannel 4. */
acmpInputAPORT0XCH5 = _ACMP_INPUTSEL_POSSEL_APORT0XCH5, /**< Select Dedicated APORT0X CHannel 5. */
acmpInputAPORT0XCH6 = _ACMP_INPUTSEL_POSSEL_APORT0XCH6, /**< Select Dedicated APORT0X CHannel 6. */
acmpInputAPORT0XCH7 = _ACMP_INPUTSEL_POSSEL_APORT0XCH7, /**< Select Dedicated APORT0X CHannel 7. */
acmpInputAPORT0XCH8 = _ACMP_INPUTSEL_POSSEL_APORT0XCH8, /**< Select Dedicated APORT0X CHannel 8. */
acmpInputAPORT0XCH9 = _ACMP_INPUTSEL_POSSEL_APORT0XCH9, /**< Select Dedicated APORT0X CHannel 9. */
acmpInputAPORT0XCH10 = _ACMP_INPUTSEL_POSSEL_APORT0XCH10, /**< Select Dedicated APORT0X CHannel 10. */
acmpInputAPORT0XCH11 = _ACMP_INPUTSEL_POSSEL_APORT0XCH11, /**< Select Dedicated APORT0X CHannel 11. */
acmpInputAPORT0XCH12 = _ACMP_INPUTSEL_POSSEL_APORT0XCH12, /**< Select Dedicated APORT0X CHannel 12. */
acmpInputAPORT0XCH13 = _ACMP_INPUTSEL_POSSEL_APORT0XCH13, /**< Select Dedicated APORT0X CHannel 13. */
acmpInputAPORT0XCH14 = _ACMP_INPUTSEL_POSSEL_APORT0XCH14, /**< Select Dedicated APORT0X CHannel 14. */
acmpInputAPORT0XCH15 = _ACMP_INPUTSEL_POSSEL_APORT0XCH15, /**< Select Dedicated APORT0X CHannel 15. */
acmpInputAPORT0YCH0 = _ACMP_INPUTSEL_POSSEL_APORT0YCH0, /**< Select Dedicated APORT0Y CHannel 0. */
acmpInputAPORT0YCH1 = _ACMP_INPUTSEL_POSSEL_APORT0YCH1, /**< Select Dedicated APORT0Y CHannel 1. */
acmpInputAPORT0YCH2 = _ACMP_INPUTSEL_POSSEL_APORT0YCH2, /**< Select Dedicated APORT0Y CHannel 2. */
acmpInputAPORT0YCH3 = _ACMP_INPUTSEL_POSSEL_APORT0YCH3, /**< Select Dedicated APORT0Y CHannel 3. */
acmpInputAPORT0YCH4 = _ACMP_INPUTSEL_POSSEL_APORT0YCH4, /**< Select Dedicated APORT0Y CHannel 4. */
acmpInputAPORT0YCH5 = _ACMP_INPUTSEL_POSSEL_APORT0YCH5, /**< Select Dedicated APORT0Y CHannel 5. */
acmpInputAPORT0YCH6 = _ACMP_INPUTSEL_POSSEL_APORT0YCH6, /**< Select Dedicated APORT0Y CHannel 6. */
acmpInputAPORT0YCH7 = _ACMP_INPUTSEL_POSSEL_APORT0YCH7, /**< Select Dedicated APORT0Y CHannel 7. */
acmpInputAPORT0YCH8 = _ACMP_INPUTSEL_POSSEL_APORT0YCH8, /**< Select Dedicated APORT0Y CHannel 8. */
acmpInputAPORT0YCH9 = _ACMP_INPUTSEL_POSSEL_APORT0YCH9, /**< Select Dedicated APORT0Y CHannel 9. */
acmpInputAPORT0YCH10 = _ACMP_INPUTSEL_POSSEL_APORT0YCH10, /**< Select Dedicated APORT0Y CHannel 10. */
acmpInputAPORT0YCH11 = _ACMP_INPUTSEL_POSSEL_APORT0YCH11, /**< Select Dedicated APORT0Y CHannel 11. */
acmpInputAPORT0YCH12 = _ACMP_INPUTSEL_POSSEL_APORT0YCH12, /**< Select Dedicated APORT0Y CHannel 12. */
acmpInputAPORT0YCH13 = _ACMP_INPUTSEL_POSSEL_APORT0YCH13, /**< Select Dedicated APORT0Y CHannel 13. */
acmpInputAPORT0YCH14 = _ACMP_INPUTSEL_POSSEL_APORT0YCH14, /**< Select Dedicated APORT0Y CHannel 14. */
acmpInputAPORT0YCH15 = _ACMP_INPUTSEL_POSSEL_APORT0YCH15, /**< Select Dedicated APORT0Y CHannel 15. */
acmpInputAPORT1XCH0 = _ACMP_INPUTSEL_POSSEL_APORT1XCH0, /**< Select Dedicated APORT1X CHannel 0. */
acmpInputAPORT1YCH1 = _ACMP_INPUTSEL_POSSEL_APORT1YCH1, /**< Select Dedicated APORT1Y CHannel 1. */
acmpInputAPORT1XCH2 = _ACMP_INPUTSEL_POSSEL_APORT1XCH2, /**< Select Dedicated APORT1X CHannel 2. */
acmpInputAPORT1YCH3 = _ACMP_INPUTSEL_POSSEL_APORT1YCH3, /**< Select Dedicated APORT1Y CHannel 3. */
acmpInputAPORT1XCH4 = _ACMP_INPUTSEL_POSSEL_APORT1XCH4, /**< Select Dedicated APORT1X CHannel 4. */
acmpInputAPORT1YCH5 = _ACMP_INPUTSEL_POSSEL_APORT1YCH5, /**< Select Dedicated APORT1Y CHannel 5. */
acmpInputAPORT1XCH6 = _ACMP_INPUTSEL_POSSEL_APORT1XCH6, /**< Select Dedicated APORT1X CHannel 6. */
acmpInputAPORT1YCH7 = _ACMP_INPUTSEL_POSSEL_APORT1YCH7, /**< Select Dedicated APORT1Y CHannel 7. */
acmpInputAPORT1XCH8 = _ACMP_INPUTSEL_POSSEL_APORT1XCH8, /**< Select Dedicated APORT1X CHannel 8. */
acmpInputAPORT1YCH9 = _ACMP_INPUTSEL_POSSEL_APORT1YCH9, /**< Select Dedicated APORT1Y CHannel 9. */
acmpInputAPORT1XCH10 = _ACMP_INPUTSEL_POSSEL_APORT1XCH10, /**< Select Dedicated APORT1X CHannel 10. */
acmpInputAPORT1YCH11 = _ACMP_INPUTSEL_POSSEL_APORT1YCH11, /**< Select Dedicated APORT1Y CHannel 11. */
acmpInputAPORT1XCH12 = _ACMP_INPUTSEL_POSSEL_APORT1XCH12, /**< Select Dedicated APORT1X CHannel 12. */
acmpInputAPORT1YCH13 = _ACMP_INPUTSEL_POSSEL_APORT1YCH13, /**< Select Dedicated APORT1Y CHannel 13. */
acmpInputAPORT1XCH14 = _ACMP_INPUTSEL_POSSEL_APORT1XCH14, /**< Select Dedicated APORT1X CHannel 14. */
acmpInputAPORT1YCH15 = _ACMP_INPUTSEL_POSSEL_APORT1YCH15, /**< Select Dedicated APORT1Y CHannel 15. */
acmpInputAPORT1XCH16 = _ACMP_INPUTSEL_POSSEL_APORT1XCH16, /**< Select Dedicated APORT1X CHannel 16. */
acmpInputAPORT1YCH17 = _ACMP_INPUTSEL_POSSEL_APORT1YCH17, /**< Select Dedicated APORT1Y CHannel 17. */
acmpInputAPORT1XCH18 = _ACMP_INPUTSEL_POSSEL_APORT1XCH18, /**< Select Dedicated APORT1X CHannel 18. */
acmpInputAPORT1YCH19 = _ACMP_INPUTSEL_POSSEL_APORT1YCH19, /**< Select Dedicated APORT1Y CHannel 19. */
acmpInputAPORT1XCH20 = _ACMP_INPUTSEL_POSSEL_APORT1XCH20, /**< Select Dedicated APORT1X CHannel 20. */
acmpInputAPORT1YCH21 = _ACMP_INPUTSEL_POSSEL_APORT1YCH21, /**< Select Dedicated APORT1Y CHannel 21. */
acmpInputAPORT1XCH22 = _ACMP_INPUTSEL_POSSEL_APORT1XCH22, /**< Select Dedicated APORT1X CHannel 22. */
acmpInputAPORT1YCH23 = _ACMP_INPUTSEL_POSSEL_APORT1YCH23, /**< Select Dedicated APORT1Y CHannel 23. */
acmpInputAPORT1XCH24 = _ACMP_INPUTSEL_POSSEL_APORT1XCH24, /**< Select Dedicated APORT1X CHannel 24. */
acmpInputAPORT1YCH25 = _ACMP_INPUTSEL_POSSEL_APORT1YCH25, /**< Select Dedicated APORT1Y CHannel 25. */
acmpInputAPORT1XCH26 = _ACMP_INPUTSEL_POSSEL_APORT1XCH26, /**< Select Dedicated APORT1X CHannel 26. */
acmpInputAPORT1YCH27 = _ACMP_INPUTSEL_POSSEL_APORT1YCH27, /**< Select Dedicated APORT1Y CHannel 27. */
acmpInputAPORT1XCH28 = _ACMP_INPUTSEL_POSSEL_APORT1XCH28, /**< Select Dedicated APORT1X CHannel 28. */
acmpInputAPORT1YCH29 = _ACMP_INPUTSEL_POSSEL_APORT1YCH29, /**< Select Dedicated APORT1Y CHannel 29. */
acmpInputAPORT1XCH30 = _ACMP_INPUTSEL_POSSEL_APORT1XCH30, /**< Select Dedicated APORT1X CHannel 30. */
acmpInputAPORT1YCH31 = _ACMP_INPUTSEL_POSSEL_APORT1YCH31, /**< Select Dedicated APORT1Y CHannel 31. */
acmpInputAPORT2YCH0 = _ACMP_INPUTSEL_POSSEL_APORT2YCH0, /**< Select Dedicated APORT2Y CHannel 0. */
acmpInputAPORT2XCH1 = _ACMP_INPUTSEL_POSSEL_APORT2XCH1, /**< Select Dedicated APORT2X CHannel 1. */
acmpInputAPORT2YCH2 = _ACMP_INPUTSEL_POSSEL_APORT2YCH2, /**< Select Dedicated APORT2Y CHannel 2. */
acmpInputAPORT2XCH3 = _ACMP_INPUTSEL_POSSEL_APORT2XCH3, /**< Select Dedicated APORT2X CHannel 3. */
acmpInputAPORT2YCH4 = _ACMP_INPUTSEL_POSSEL_APORT2YCH4, /**< Select Dedicated APORT2Y CHannel 4. */
acmpInputAPORT2XCH5 = _ACMP_INPUTSEL_POSSEL_APORT2XCH5, /**< Select Dedicated APORT2X CHannel 5. */
acmpInputAPORT2YCH6 = _ACMP_INPUTSEL_POSSEL_APORT2YCH6, /**< Select Dedicated APORT2Y CHannel 6. */
acmpInputAPORT2XCH7 = _ACMP_INPUTSEL_POSSEL_APORT2XCH7, /**< Select Dedicated APORT2X CHannel 7. */
acmpInputAPORT2YCH8 = _ACMP_INPUTSEL_POSSEL_APORT2YCH8, /**< Select Dedicated APORT2Y CHannel 8. */
acmpInputAPORT2XCH9 = _ACMP_INPUTSEL_POSSEL_APORT2XCH9, /**< Select Dedicated APORT2X CHannel 9. */
acmpInputAPORT2YCH10 = _ACMP_INPUTSEL_POSSEL_APORT2YCH10, /**< Select Dedicated APORT2Y CHannel 10. */
acmpInputAPORT2XCH11 = _ACMP_INPUTSEL_POSSEL_APORT2XCH11, /**< Select Dedicated APORT2X CHannel 11. */
acmpInputAPORT2YCH12 = _ACMP_INPUTSEL_POSSEL_APORT2YCH12, /**< Select Dedicated APORT2Y CHannel 12. */
acmpInputAPORT2XCH13 = _ACMP_INPUTSEL_POSSEL_APORT2XCH13, /**< Select Dedicated APORT2X CHannel 13. */
acmpInputAPORT2YCH14 = _ACMP_INPUTSEL_POSSEL_APORT2YCH14, /**< Select Dedicated APORT2Y CHannel 14. */
acmpInputAPORT2XCH15 = _ACMP_INPUTSEL_POSSEL_APORT2XCH15, /**< Select Dedicated APORT2X CHannel 15. */
acmpInputAPORT2YCH16 = _ACMP_INPUTSEL_POSSEL_APORT2YCH16, /**< Select Dedicated APORT2Y CHannel 16. */
acmpInputAPORT2XCH17 = _ACMP_INPUTSEL_POSSEL_APORT2XCH17, /**< Select Dedicated APORT2X CHannel 17. */
acmpInputAPORT2YCH18 = _ACMP_INPUTSEL_POSSEL_APORT2YCH18, /**< Select Dedicated APORT2Y CHannel 18. */
acmpInputAPORT2XCH19 = _ACMP_INPUTSEL_POSSEL_APORT2XCH19, /**< Select Dedicated APORT2X CHannel 19. */
acmpInputAPORT2YCH20 = _ACMP_INPUTSEL_POSSEL_APORT2YCH20, /**< Select Dedicated APORT2Y CHannel 20. */
acmpInputAPORT2XCH21 = _ACMP_INPUTSEL_POSSEL_APORT2XCH21, /**< Select Dedicated APORT2X CHannel 21. */
acmpInputAPORT2YCH22 = _ACMP_INPUTSEL_POSSEL_APORT2YCH22, /**< Select Dedicated APORT2Y CHannel 22. */
acmpInputAPORT2XCH23 = _ACMP_INPUTSEL_POSSEL_APORT2XCH23, /**< Select Dedicated APORT2X CHannel 23. */
acmpInputAPORT2YCH24 = _ACMP_INPUTSEL_POSSEL_APORT2YCH24, /**< Select Dedicated APORT2Y CHannel 24. */
acmpInputAPORT2XCH25 = _ACMP_INPUTSEL_POSSEL_APORT2XCH25, /**< Select Dedicated APORT2X CHannel 25. */
acmpInputAPORT2YCH26 = _ACMP_INPUTSEL_POSSEL_APORT2YCH26, /**< Select Dedicated APORT2Y CHannel 26. */
acmpInputAPORT2XCH27 = _ACMP_INPUTSEL_POSSEL_APORT2XCH27, /**< Select Dedicated APORT2X CHannel 27. */
acmpInputAPORT2YCH28 = _ACMP_INPUTSEL_POSSEL_APORT2YCH28, /**< Select Dedicated APORT2Y CHannel 28. */
acmpInputAPORT2XCH29 = _ACMP_INPUTSEL_POSSEL_APORT2XCH29, /**< Select Dedicated APORT2X CHannel 29. */
acmpInputAPORT2YCH30 = _ACMP_INPUTSEL_POSSEL_APORT2YCH30, /**< Select Dedicated APORT2Y CHannel 30. */
acmpInputAPORT2XCH31 = _ACMP_INPUTSEL_POSSEL_APORT2XCH31, /**< Select Dedicated APORT2X CHannel 31. */
acmpInputAPORT3XCH0 = _ACMP_INPUTSEL_POSSEL_APORT3XCH0, /**< Select Dedicated APORT3X CHannel 0. */
acmpInputAPORT3YCH1 = _ACMP_INPUTSEL_POSSEL_APORT3YCH1, /**< Select Dedicated APORT3Y CHannel 1. */
acmpInputAPORT3XCH2 = _ACMP_INPUTSEL_POSSEL_APORT3XCH2, /**< Select Dedicated APORT3X CHannel 2. */
acmpInputAPORT3YCH3 = _ACMP_INPUTSEL_POSSEL_APORT3YCH3, /**< Select Dedicated APORT3Y CHannel 3. */
acmpInputAPORT3XCH4 = _ACMP_INPUTSEL_POSSEL_APORT3XCH4, /**< Select Dedicated APORT3X CHannel 4. */
acmpInputAPORT3YCH5 = _ACMP_INPUTSEL_POSSEL_APORT3YCH5, /**< Select Dedicated APORT3Y CHannel 5. */
acmpInputAPORT3XCH6 = _ACMP_INPUTSEL_POSSEL_APORT3XCH6, /**< Select Dedicated APORT3X CHannel 6. */
acmpInputAPORT3YCH7 = _ACMP_INPUTSEL_POSSEL_APORT3YCH7, /**< Select Dedicated APORT3Y CHannel 7. */
acmpInputAPORT3XCH8 = _ACMP_INPUTSEL_POSSEL_APORT3XCH8, /**< Select Dedicated APORT3X CHannel 8. */
acmpInputAPORT3YCH9 = _ACMP_INPUTSEL_POSSEL_APORT3YCH9, /**< Select Dedicated APORT3Y CHannel 9. */
acmpInputAPORT3XCH10 = _ACMP_INPUTSEL_POSSEL_APORT3XCH10, /**< Select Dedicated APORT3X CHannel 10. */
acmpInputAPORT3YCH11 = _ACMP_INPUTSEL_POSSEL_APORT3YCH11, /**< Select Dedicated APORT3Y CHannel 11. */
acmpInputAPORT3XCH12 = _ACMP_INPUTSEL_POSSEL_APORT3XCH12, /**< Select Dedicated APORT3X CHannel 12. */
acmpInputAPORT3YCH13 = _ACMP_INPUTSEL_POSSEL_APORT3YCH13, /**< Select Dedicated APORT3Y CHannel 13. */
acmpInputAPORT3XCH14 = _ACMP_INPUTSEL_POSSEL_APORT3XCH14, /**< Select Dedicated APORT3X CHannel 14. */
acmpInputAPORT3YCH15 = _ACMP_INPUTSEL_POSSEL_APORT3YCH15, /**< Select Dedicated APORT3Y CHannel 15. */
acmpInputAPORT3XCH16 = _ACMP_INPUTSEL_POSSEL_APORT3XCH16, /**< Select Dedicated APORT3X CHannel 16. */
acmpInputAPORT3YCH17 = _ACMP_INPUTSEL_POSSEL_APORT3YCH17, /**< Select Dedicated APORT3Y CHannel 17. */
acmpInputAPORT3XCH18 = _ACMP_INPUTSEL_POSSEL_APORT3XCH18, /**< Select Dedicated APORT3X CHannel 18. */
acmpInputAPORT3YCH19 = _ACMP_INPUTSEL_POSSEL_APORT3YCH19, /**< Select Dedicated APORT3Y CHannel 19. */
acmpInputAPORT3XCH20 = _ACMP_INPUTSEL_POSSEL_APORT3XCH20, /**< Select Dedicated APORT3X CHannel 20. */
acmpInputAPORT3YCH21 = _ACMP_INPUTSEL_POSSEL_APORT3YCH21, /**< Select Dedicated APORT3Y CHannel 21. */
acmpInputAPORT3XCH22 = _ACMP_INPUTSEL_POSSEL_APORT3XCH22, /**< Select Dedicated APORT3X CHannel 22. */
acmpInputAPORT3YCH23 = _ACMP_INPUTSEL_POSSEL_APORT3YCH23, /**< Select Dedicated APORT3Y CHannel 23. */
acmpInputAPORT3XCH24 = _ACMP_INPUTSEL_POSSEL_APORT3XCH24, /**< Select Dedicated APORT3X CHannel 24. */
acmpInputAPORT3YCH25 = _ACMP_INPUTSEL_POSSEL_APORT3YCH25, /**< Select Dedicated APORT3Y CHannel 25. */
acmpInputAPORT3XCH26 = _ACMP_INPUTSEL_POSSEL_APORT3XCH26, /**< Select Dedicated APORT3X CHannel 26. */
acmpInputAPORT3YCH27 = _ACMP_INPUTSEL_POSSEL_APORT3YCH27, /**< Select Dedicated APORT3Y CHannel 27. */
acmpInputAPORT3XCH28 = _ACMP_INPUTSEL_POSSEL_APORT3XCH28, /**< Select Dedicated APORT3X CHannel 28. */
acmpInputAPORT3YCH29 = _ACMP_INPUTSEL_POSSEL_APORT3YCH29, /**< Select Dedicated APORT3Y CHannel 29. */
acmpInputAPORT3XCH30 = _ACMP_INPUTSEL_POSSEL_APORT3XCH30, /**< Select Dedicated APORT3X CHannel 30. */
acmpInputAPORT3YCH31 = _ACMP_INPUTSEL_POSSEL_APORT3YCH31, /**< Select Dedicated APORT3Y CHannel 31. */
acmpInputAPORT4YCH0 = _ACMP_INPUTSEL_POSSEL_APORT4YCH0, /**< Select Dedicated APORT4Y CHannel 0. */
acmpInputAPORT4XCH1 = _ACMP_INPUTSEL_POSSEL_APORT4XCH1, /**< Select Dedicated APORT4X CHannel 1. */
acmpInputAPORT4YCH2 = _ACMP_INPUTSEL_POSSEL_APORT4YCH2, /**< Select Dedicated APORT4Y CHannel 2. */
acmpInputAPORT4XCH3 = _ACMP_INPUTSEL_POSSEL_APORT4XCH3, /**< Select Dedicated APORT4X CHannel 3. */
acmpInputAPORT4YCH4 = _ACMP_INPUTSEL_POSSEL_APORT4YCH4, /**< Select Dedicated APORT4Y CHannel 4. */
acmpInputAPORT4XCH5 = _ACMP_INPUTSEL_POSSEL_APORT4XCH5, /**< Select Dedicated APORT4X CHannel 5. */
acmpInputAPORT4YCH6 = _ACMP_INPUTSEL_POSSEL_APORT4YCH6, /**< Select Dedicated APORT4Y CHannel 6. */
acmpInputAPORT4XCH7 = _ACMP_INPUTSEL_POSSEL_APORT4XCH7, /**< Select Dedicated APORT4X CHannel 7. */
acmpInputAPORT4YCH8 = _ACMP_INPUTSEL_POSSEL_APORT4YCH8, /**< Select Dedicated APORT4Y CHannel 8. */
acmpInputAPORT4XCH9 = _ACMP_INPUTSEL_POSSEL_APORT4XCH9, /**< Select Dedicated APORT4X CHannel 9. */
acmpInputAPORT4YCH10 = _ACMP_INPUTSEL_POSSEL_APORT4YCH10, /**< Select Dedicated APORT4Y CHannel 10. */
acmpInputAPORT4XCH11 = _ACMP_INPUTSEL_POSSEL_APORT4XCH11, /**< Select Dedicated APORT4X CHannel 11. */
acmpInputAPORT4YCH12 = _ACMP_INPUTSEL_POSSEL_APORT4YCH12, /**< Select Dedicated APORT4Y CHannel 12. */
acmpInputAPORT4XCH13 = _ACMP_INPUTSEL_POSSEL_APORT4XCH13, /**< Select Dedicated APORT4X CHannel 13. */
acmpInputAPORT4YCH16 = _ACMP_INPUTSEL_POSSEL_APORT4YCH16, /**< Select Dedicated APORT4Y CHannel 14. */
acmpInputAPORT4XCH17 = _ACMP_INPUTSEL_POSSEL_APORT4XCH17, /**< Select Dedicated APORT4X CHannel 15. */
acmpInputAPORT4YCH18 = _ACMP_INPUTSEL_POSSEL_APORT4YCH18, /**< Select Dedicated APORT4Y CHannel 16. */
acmpInputAPORT4XCH19 = _ACMP_INPUTSEL_POSSEL_APORT4XCH19, /**< Select Dedicated APORT4X CHannel 17. */
acmpInputAPORT4YCH20 = _ACMP_INPUTSEL_POSSEL_APORT4YCH20, /**< Select Dedicated APORT4Y CHannel 18. */
acmpInputAPORT4XCH21 = _ACMP_INPUTSEL_POSSEL_APORT4XCH21, /**< Select Dedicated APORT4X CHannel 19. */
acmpInputAPORT4YCH22 = _ACMP_INPUTSEL_POSSEL_APORT4YCH22, /**< Select Dedicated APORT4Y CHannel 20. */
acmpInputAPORT4XCH23 = _ACMP_INPUTSEL_POSSEL_APORT4XCH23, /**< Select Dedicated APORT4X CHannel 21. */
acmpInputAPORT4YCH24 = _ACMP_INPUTSEL_POSSEL_APORT4YCH24, /**< Select Dedicated APORT4Y CHannel 22. */
acmpInputAPORT4XCH25 = _ACMP_INPUTSEL_POSSEL_APORT4XCH25, /**< Select Dedicated APORT4X CHannel 23. */
acmpInputAPORT4YCH26 = _ACMP_INPUTSEL_POSSEL_APORT4YCH26, /**< Select Dedicated APORT4Y CHannel 24. */
acmpInputAPORT4XCH27 = _ACMP_INPUTSEL_POSSEL_APORT4XCH27, /**< Select Dedicated APORT4X CHannel 25. */
acmpInputAPORT4YCH28 = _ACMP_INPUTSEL_POSSEL_APORT4YCH28, /**< Select Dedicated APORT4Y CHannel 26. */
acmpInputAPORT4XCH29 = _ACMP_INPUTSEL_POSSEL_APORT4XCH29, /**< Select Dedicated APORT4X CHannel 27. */
acmpInputAPORT4YCH30 = _ACMP_INPUTSEL_POSSEL_APORT4YCH30, /**< Select Dedicated APORT4Y CHannel 28. */
acmpInputAPORT4YCH14 = _ACMP_INPUTSEL_POSSEL_APORT4YCH14, /**< Select Dedicated APORT4X CHannel 29. */
acmpInputAPORT4XCH15 = _ACMP_INPUTSEL_POSSEL_APORT4XCH15, /**< Select Dedicated APORT4Y CHannel 30. */
acmpInputAPORT4XCH31 = _ACMP_INPUTSEL_POSSEL_APORT4XCH31, /**< Select Dedicated APORT4X CHannel 31. */
#if defined(_ACMP_INPUTSEL_POSSEL_DACOUT0)
acmpInputDACOUT0 = _ACMP_INPUTSEL_POSSEL_DACOUT0,
acmpInputDACOUT0 = _ACMP_INPUTSEL_POSSEL_DACOUT0, /**< Select DAC Channel 0 Output. */
#endif
#if defined(_ACMP_INPUTSEL_POSSEL_DACOUT1)
acmpInputDACOUT1 = _ACMP_INPUTSEL_POSSEL_DACOUT1,
acmpInputDACOUT1 = _ACMP_INPUTSEL_POSSEL_DACOUT1, /**< Select DAC Channel 1 Output. */
#endif
acmpInputVLP = _ACMP_INPUTSEL_POSSEL_VLP,
acmpInputVBDIV = _ACMP_INPUTSEL_POSSEL_VBDIV,
acmpInputVADIV = _ACMP_INPUTSEL_POSSEL_VADIV,
acmpInputVDD = _ACMP_INPUTSEL_POSSEL_VDD,
acmpInputVSS = _ACMP_INPUTSEL_POSSEL_VSS,
acmpInputVLP = _ACMP_INPUTSEL_POSSEL_VLP, /**< Select Low-Power Sampled Voltage. */
acmpInputVBDIV = _ACMP_INPUTSEL_POSSEL_VBDIV, /**< Select Divided VB Voltage. */
acmpInputVADIV = _ACMP_INPUTSEL_POSSEL_VADIV, /**< Select Divided VA Voltage. */
acmpInputVDD = _ACMP_INPUTSEL_POSSEL_VDD, /**< ACMPVDD as selected via PWRSEL. */
acmpInputVSS = _ACMP_INPUTSEL_POSSEL_VSS, /**< Select VSS. */
} ACMP_Channel_TypeDef;
#else
/** ACMP inputs. Note that scaled VDD and bandgap references can only be used
@ -579,20 +585,20 @@ typedef enum {
* the ACMP input.
*/
typedef enum {
acmpExternalInputAPORT0X = _ACMP_EXTIFCTRL_APORTSEL_APORT0X,
acmpExternalInputAPORT0Y = _ACMP_EXTIFCTRL_APORTSEL_APORT0Y,
acmpExternalInputAPORT1X = _ACMP_EXTIFCTRL_APORTSEL_APORT1X,
acmpExternalInputAPORT1Y = _ACMP_EXTIFCTRL_APORTSEL_APORT1Y,
acmpExternalInputAPORT1XY = _ACMP_EXTIFCTRL_APORTSEL_APORT1XY,
acmpExternalInputAPORT2X = _ACMP_EXTIFCTRL_APORTSEL_APORT2X,
acmpExternalInputAPORT2Y = _ACMP_EXTIFCTRL_APORTSEL_APORT2Y,
acmpExternalInputAPORT2YX = _ACMP_EXTIFCTRL_APORTSEL_APORT2YX,
acmpExternalInputAPORT3X = _ACMP_EXTIFCTRL_APORTSEL_APORT3X,
acmpExternalInputAPORT3Y = _ACMP_EXTIFCTRL_APORTSEL_APORT3Y,
acmpExternalInputAPORT3XY = _ACMP_EXTIFCTRL_APORTSEL_APORT3XY,
acmpExternalInputAPORT4X = _ACMP_EXTIFCTRL_APORTSEL_APORT4X,
acmpExternalInputAPORT4Y = _ACMP_EXTIFCTRL_APORTSEL_APORT4Y,
acmpExternalInputAPORT4YX = _ACMP_EXTIFCTRL_APORTSEL_APORT4YX,
acmpExternalInputAPORT0X = _ACMP_EXTIFCTRL_APORTSEL_APORT0X, /**< Select APORT0X as an external input. */
acmpExternalInputAPORT0Y = _ACMP_EXTIFCTRL_APORTSEL_APORT0Y, /**< Select APORT0Y as an external input. */
acmpExternalInputAPORT1X = _ACMP_EXTIFCTRL_APORTSEL_APORT1X, /**< Select APORT1X as an external input. */
acmpExternalInputAPORT1Y = _ACMP_EXTIFCTRL_APORTSEL_APORT1Y, /**< Select APORT1Y as an external input. */
acmpExternalInputAPORT1XY = _ACMP_EXTIFCTRL_APORTSEL_APORT1XY, /**< Select APORT1XY as an external input. */
acmpExternalInputAPORT2X = _ACMP_EXTIFCTRL_APORTSEL_APORT2X, /**< Select APORT2X as an external input. */
acmpExternalInputAPORT2Y = _ACMP_EXTIFCTRL_APORTSEL_APORT2Y, /**< Select APORT2Y as an external input. */
acmpExternalInputAPORT2YX = _ACMP_EXTIFCTRL_APORTSEL_APORT2YX, /**< Select APORT2YX as an external input. */
acmpExternalInputAPORT3X = _ACMP_EXTIFCTRL_APORTSEL_APORT3X, /**< Select APORT3X as an external input. */
acmpExternalInputAPORT3Y = _ACMP_EXTIFCTRL_APORTSEL_APORT3Y, /**< Select APORT3Y as an external input. */
acmpExternalInputAPORT3XY = _ACMP_EXTIFCTRL_APORTSEL_APORT3XY, /**< Select APORT3XY as an external input. */
acmpExternalInputAPORT4X = _ACMP_EXTIFCTRL_APORTSEL_APORT4X, /**< Select APORT4X as an external input. */
acmpExternalInputAPORT4Y = _ACMP_EXTIFCTRL_APORTSEL_APORT4Y, /**< Select APORT4Y as an external input. */
acmpExternalInputAPORT4YX = _ACMP_EXTIFCTRL_APORTSEL_APORT4YX, /**< Select APORT4YX as an external input. */
} ACMP_ExternalInput_Typedef;
#endif
@ -636,7 +642,7 @@ typedef struct {
ACMP_HysteresisLevel_TypeDef hysteresisLevel_1;
#endif
/** A resistor used in the capacative sensing circuit. For values see
/** A resistor used in the capacitive sensing circuit. For values see
* the device data sheet. */
ACMP_CapsenseResistor_TypeDef resistor;
@ -680,13 +686,21 @@ typedef struct {
/** A default configuration for capacitive sense mode initialization. */
#if defined(_ACMP_CFG_MASK)
#define ACMP_CAPSENSE_INIT_DEFAULT \
{ \
_ACMP_CFG_BIAS_DEFAULT, /* Using biasProg default value. */ \
acmpHysteresisDisabled, /* Disable hysteresis. */ \
acmpResistor5, /* Use internal resistor value 5. */ \
0x3F, /* Set VREFDIV to maximum to disable divide. */ \
true /* Enable after init. */ \
// PM5507: provide default configuration that is functional
/** Analog comparator CFG with initial bias value */
#define PM5507_ACMP_CFG_BIAS_DEFAULT 0x00000004UL
/** Analog comparator reset value */
#define PM5507_ACMP_CFG_RESETVALUE 0x00000004UL
/** Capacitive sense mode configuration default values. */
#define ACMP_CAPSENSE_INIT_DEFAULT \
{ \
PM5507_ACMP_CFG_BIAS_DEFAULT, /* Using biasProg default value. */ \
acmpHysteresisDisabled, /* Disable hysteresis. */ \
acmpResistor5, /* Use internal resistor value 5. */ \
0x3F, /* Set VREFDIV to maximum to disable divide. */ \
true /* Enable after init. */ \
}
#elif defined(_ACMP_HYSTERESIS0_HYST_MASK)
#define ACMP_CAPSENSE_INIT_DEFAULT \
@ -823,15 +837,15 @@ typedef struct {
/** Default configuration for ACMP regular initialization. */
#if defined(_ACMP_CFG_MASK)
#define ACMP_INIT_DEFAULT \
{ \
_ACMP_CFG_BIAS_DEFAULT, /* Using biasProg default value. */ \
acmpInputRangeFull, /* Input range from 0 to Vdd. */ \
acmpAccuracyLow, /* Low accuracy, less current usage. */ \
acmpHysteresisDisabled, /* Disable hysteresis. */ \
false, /* Output 0 when ACMP is inactive. */ \
0x3F, /* Set VREFDIV to maximum to disable divide. */ \
true /* Enable after init. */ \
#define ACMP_INIT_DEFAULT \
{ \
PM5507_ACMP_CFG_BIAS_DEFAULT, /* Using biasProg default value. */ \
acmpInputRangeFull, /* Input range from 0 to Vdd. */ \
acmpAccuracyLow, /* Low accuracy, less current usage. */ \
acmpHysteresisDisabled, /* Disable hysteresis. */ \
false, /* Output 0 when ACMP is inactive. */ \
0x3F, /* Set VREFDIV to maximum to disable divide. */ \
true /* Enable after init. */ \
}
#elif defined(_ACMP_HYSTERESIS0_HYST_MASK)
#define ACMP_INIT_DEFAULT \

4
gecko/emlib/inc/em_adc.h
View File

@ -321,7 +321,7 @@ typedef enum {
#endif
#if defined(_ADC_SINGLECTRL_POSSEL_MASK)
/** Positive input selection for single and scan coversion. */
/** Positive input selection for single and scan conversion. */
typedef enum {
adcPosSelAPORT0XCH0 = _ADC_SINGLECTRL_POSSEL_APORT0XCH0,
adcPosSelAPORT0XCH1 = _ADC_SINGLECTRL_POSSEL_APORT0XCH1,
@ -993,7 +993,7 @@ typedef struct {
#if defined(_ADC_SINGLECTRL_NEGSEL_MASK)
/** Select negative input for single channel conversion mode. Negative input is grounded
for single-ended (non-differential) converison. */
for single-ended (non-differential) conversion. */
ADC_NegSel_TypeDef negSel;
#endif

4
gecko/emlib/inc/em_can.h
View File

@ -165,7 +165,7 @@ typedef struct {
/** Default Phase Buffer Segment 2. */
uint8_t phaseBufferSegment2;
/** Default Synchronisation Jump Width. */
/** Default Synchronization Jump Width. */
uint8_t synchronisationJumpWidth;
} CAN_Init_TypeDef;
@ -321,7 +321,7 @@ __STATIC_INLINE CAN_ErrorCode_TypeDef CAN_GetLastErrorCode(CAN_TypeDef *can)
/***************************************************************************//**
* @brief
* Indicates which message objects have received new data.
* Indicate which message objects have received new data.
*
* @param[in] can
* A pointer to the CAN peripheral register block.

9
gecko/emlib/inc/em_chip.h
View File

@ -33,10 +33,15 @@
#include "em_device.h"
#include "sl_common.h"
#if defined(_SILICON_LABS_32B_SERIES) && (_SILICON_LABS_32B_SERIES <= 2)
#include "em_system.h"
#include "em_gpio.h"
#endif
#include "em_bus.h"
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
#include "em_gpio.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
@ -301,7 +306,7 @@ __STATIC_INLINE void CHIP_Init(void)
*(volatile uint32_t *)(EMU_BASE + 0x1A4) |= 0x1f << 10;
#endif
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_200)
#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
SYSTEM_ChipRevision_TypeDef chipRev;
SYSTEM_ChipRevisionGet(&chipRev);

6
gecko/emlib/inc/em_cmu_fpga.h
View File

@ -173,6 +173,7 @@ typedef enum {
cmuClock_ULFRCO, /**< ULFRCO clock. */
cmuClock_LFXO, /**< LFXO clock. */
cmuClock_HFRCO0, /**< HFRCO0 clock. */
cmuClock_HFRCOEM23, /**< HFRCOEM23 clock. */
cmuClock_WDOG0CLK, /**< WDOG0 clock. */
#if WDOG_COUNT > 1
cmuClock_WDOG1CLK, /**< WDOG1 clock. */
@ -184,7 +185,7 @@ typedef enum {
cmuClock_RTCCCLK, /**< RTCC clock. */
#if defined(LESENSE_PRESENT)
cmuClock_LESENSEHFCLK,
cmuClock_LESENSELFCLK,
cmuClock_LESENSECLK,
#endif
/*********************/
@ -196,6 +197,9 @@ typedef enum {
cmuClock_ACMP0, /**< ACMP0 clock. */
cmuClock_ACMP1, /**< ACMP1 clock. */
cmuClock_BURTC, /**< BURTC clock. */
#if defined(ETAMPDET_PRESENT)
cmuClock_ETAMPDET, /**< ETAMPDET clock. */
#endif
cmuClock_GPCRC, /**< GPCRC clock. */
cmuClock_GPIO, /**< GPIO clock. */
cmuClock_I2C0, /**< I2C0 clock. */

14
gecko/emlib/inc/em_cryotimer.h
View File

@ -46,10 +46,10 @@ extern "C" {
* @brief Ultra Low Energy Timer/Counter (CRYOTIMER) Peripheral API
*
* @details
* The CRYOTIMER is a 32 bit counter which operates on a low-frequency
* The CRYOTIMER is a 32 bit counter, which operates on a low-frequency
* oscillator and is capable of running in all Energy Modes. It can provide
* periodic wakeup events and PRS signals which can be used to wake up
* peripherals from any energy mode. The CRYOTIMER provides a very wide range
* periodic wakeup events and PRS signals, which can be used to wake up
* peripherals from any energy mode. The CRYOTIMER provides a wide range
* of periods for the interrupts facilitating flexible ultra-low energy
* operation. Because of its simplicity, the CRYOTIMER is a lower energy
* solution for periodically waking up the MCU compared to the RTCC.
@ -83,8 +83,8 @@ extern "C" {
* @ref CRYOTIMER_EM4WakeupEnable.
*
* Note that when using the CRYOTIMER to wake up from EM4, the application has
* the responsibility to clear the wakeup event. This is done by calling
* @ref CRYOTIMER_IntClear. If the user does not clear the wakeup event,
* the responsibility to clear the wakeup event by calling
* @ref CRYOTIMER_IntClear. If the you do not clear the wakeup event,
* the wakeup event will stay pending and will cause an immediate wakeup the
* next time the application attempts to enter EM4.
*
@ -96,9 +96,9 @@ extern "C" {
* @details
* All the low frequency oscillators can be used in EM4, however, the
* oscillator that is used must be be configured to be retained when going
* into EM4. This can be configured by using functions in the @ref emu module.
* into EM4 by using functions in the @ref emu module.
* See @ref EMU_EM4Init and @ref EMU_EM4Init_TypeDef. If an oscillator is
* retained in EM4, the user is also responsible for unlatching the retained
* retained in EM4, users are also responsible for unlatching the retained
* configuration on a wakeup from EM4.
*
* @{

50
gecko/emlib/inc/em_csen.h
View File

@ -46,7 +46,7 @@ extern "C" {
* @brief Capacitive Sense (CSEN) Peripheral API.
*
* @details
* Provides functions for controlling the capacitive sense
* Provides functions to control the capacitive sense
* peripheral of Silicon Labs' 32-bit MCUs and SoCs. The CSEN includes a
* capacitance-to-digital circuit that measures capacitance on selected
* inputs. Measurements are performed using either a Successive Approximation
@ -57,7 +57,7 @@ extern "C" {
* mode. Also, several port pins can be shorted together to measure the
* combined capacitance.
*
* The CSEN includes an accumulator which can be configured to average
* The CSEN includes an accumulator, which can be configured to average
* multiple conversions on the selected input. Additionally, an Exponential
* Moving Average (EMA) calculator is included to provide data smoothing.
* A comparator is also included and can be used to terminate a continuous
@ -498,15 +498,15 @@ typedef struct {
/***************************************************************************//**
* @brief
* Get last conversion result.
* Get the last conversion result.
*
* @note
* Check conversion busy flag before calling this function. In addition,
* Check the conversion busy flag before calling this function. In addition,
* the result width and format depend on the parameters passed to the
* @ref CSEN_InitMode() function.
*
* @param[in] csen
* Pointer to CSEN peripheral register block.
* Pointer to a CSEN peripheral register block.
*
* @return
* Result data from last conversion.
@ -518,13 +518,13 @@ __STATIC_INLINE uint32_t CSEN_DataGet(CSEN_TypeDef *csen)
/***************************************************************************//**
* @brief
* Get last exponential moving average.
* Get the last exponential moving average.
*
* @note
* Confirm CSEN is idle before calling this function.
* Confirm that CSEN is idle before calling this function.
*
* @param[in] csen
* Pointer to CSEN peripheral register block.
* Pointer to a CSEN peripheral register block.
*
* @return
* Exponential moving average from last conversion.
@ -536,13 +536,13 @@ __STATIC_INLINE uint32_t CSEN_EMAGet(CSEN_TypeDef *csen)
/***************************************************************************//**
* @brief
* Set exponential moving average initial value.
* Set the exponential moving average initial value.
*
* @note
* Call this function before starting a conversion.
*
* @param[in] csen
* Pointer to CSEN peripheral register block.
* Pointer to a CSEN peripheral register block.
*
* @param[in] ema
* Initial value for the exponential moving average.
@ -554,10 +554,10 @@ __STATIC_INLINE void CSEN_EMASet(CSEN_TypeDef *csen, uint32_t ema)
/***************************************************************************//**
* @brief
* Disables the CSEN.
* Disable CSEN.
*
* @param[in] csen
* Pointer to CSEN peripheral register block.
* Pointer to a CSEN peripheral register block.
******************************************************************************/
__STATIC_INLINE void CSEN_Disable(CSEN_TypeDef *csen)
{
@ -566,10 +566,10 @@ __STATIC_INLINE void CSEN_Disable(CSEN_TypeDef *csen)
/***************************************************************************//**
* @brief
* Enables the CSEN.
* Enable CSEN.
*
* @param[in] csen
* Pointer to CSEN peripheral register block.
* Pointer to a CSEN peripheral register block.
******************************************************************************/
__STATIC_INLINE void CSEN_Enable(CSEN_TypeDef *csen)
{
@ -586,7 +586,7 @@ void CSEN_Reset(CSEN_TypeDef *csen);
* Clear one or more pending CSEN interrupts.
*
* @param[in] csen
* Pointer to CSEN peripheral register block.
* Pointer to a CSEN peripheral register block.
*
* @param[in] flags
* Pending CSEN interrupt source to clear. Use a bitwise logic OR combination
@ -602,7 +602,7 @@ __STATIC_INLINE void CSEN_IntClear(CSEN_TypeDef *csen, uint32_t flags)
* Disable one or more CSEN interrupts.
*
* @param[in] csen
* Pointer to CSEN peripheral register block.
* Pointer to a CSEN peripheral register block.
*
* @param[in] flags
* CSEN interrupt sources to disable. Use a bitwise logic OR combination of
@ -618,12 +618,12 @@ __STATIC_INLINE void CSEN_IntDisable(CSEN_TypeDef *csen, uint32_t flags)
* Enable one or more CSEN interrupts.
*
* @note
* Depending on the use, a pending interrupt may already be set prior to
* Depending on the use case, a pending interrupt may already be set prior to
* enabling the interrupt. Consider using CSEN_IntClear() prior to enabling
* if such a pending interrupt should be ignored.
*
* @param[in] csen
* Pointer to CSEN peripheral register block.
* Pointer to a CSEN peripheral register block.
*
* @param[in] flags
* CSEN interrupt sources to enable. Use a bitwise logic OR combination of
@ -642,7 +642,7 @@ __STATIC_INLINE void CSEN_IntEnable(CSEN_TypeDef *csen, uint32_t flags)
* The event bits are not cleared by the use of this function.
*
* @param[in] csen
* Pointer to CSEN peripheral register block.
* Pointer to a CSEN peripheral register block.
*
* @return
* CSEN interrupt sources pending. A bitwise logic OR combination of valid
@ -659,7 +659,7 @@ __STATIC_INLINE uint32_t CSEN_IntGet(CSEN_TypeDef *csen)
* Useful for handling more interrupt sources in the same interrupt handler.
*
* @param[in] csen
* Pointer to CSEN peripheral register block.
* Pointer to a CSEN peripheral register block.
*
* @note
* Interrupt flags are not cleared by the use of this function.
@ -676,7 +676,7 @@ __STATIC_INLINE uint32_t CSEN_IntGetEnabled(CSEN_TypeDef *csen)
{
uint32_t ien;
/* Store CSENx->IEN in temporary variable in order to define explicit order
/* Store CSENx->IEN in temporary variable to define explicit order
* of volatile accesses. */
ien = csen->IEN;
@ -689,7 +689,7 @@ __STATIC_INLINE uint32_t CSEN_IntGetEnabled(CSEN_TypeDef *csen)
* Set one or more pending CSEN interrupts from SW.
*
* @param[in] csen
* Pointer to CSEN peripheral register block.
* Pointer to a CSEN peripheral register block.
*
* @param[in] flags
* CSEN interrupt sources to set to pending. Use a bitwise logic OR combination
@ -705,7 +705,7 @@ __STATIC_INLINE void CSEN_IntSet(CSEN_TypeDef *csen, uint32_t flags)
* Return CSEN conversion busy status.
*
* @param[in] csen
* Pointer to CSEN peripheral register block.
* Pointer to a CSEN peripheral register block.
*
* @return
* True if CSEN conversion is in progress.
@ -717,10 +717,10 @@ __STATIC_INLINE bool CSEN_IsBusy(CSEN_TypeDef *csen)
/***************************************************************************//**
* @brief
* Start scan sequence and/or single conversion.
* Start a scan sequence and/or a single conversion.
*
* @param[in] csen
* Pointer to CSEN peripheral register block.
* Pointer to a CSEN peripheral register block.
******************************************************************************/
__STATIC_INLINE void CSEN_Start(CSEN_TypeDef *csen)
{

2
gecko/emlib/inc/em_dbg.h
View File

@ -106,7 +106,7 @@ void DBG_DisableDebugAccess(DBG_LockMode_TypeDef lockMode);
* (powers down the EFR). Execute Simplicity Commander with command line
* parameters:
* "./commander.exe device recover"
* and then immediately move the switch to the AEM postion. An additional
* and then immediately move the switch to the AEM position. An additional
* "./commander.exe device masserase"
* command completes the recovery procedure.
*

169
gecko/emlib/inc/em_eusart.h
View File

@ -32,9 +32,14 @@
#define EM_EUSART_H
#include "em_device.h"
#if defined(EUART_PRESENT) || defined(EUSART_PRESENT)
#include "sl_enum.h"
#include "em_eusart_compat.h"
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-OFF* */
// *****************************************************************************
/// @addtogroup eusart EUSART - Extended USART
@ -139,6 +144,30 @@
// *****************************************************************************
/* *INDENT-ON* */
/*******************************************************************************
******************************* DEFINES ***********************************
******************************************************************************/
/** Define EUSART FIFO Depth information */
#if !defined(EUSART_FIFO_DEPTH)
#if defined(EUART_PRESENT)
#define EUSART0_FIFO_DEPTH 4
#elif defined(EUSART_PRESENT)
#define EUSART0_FIFO_DEPTH 16
#endif /* EUART_PRESENT */
#define EUSART1_FIFO_DEPTH EUSART0_FIFO_DEPTH
#define EUSART2_FIFO_DEPTH EUSART0_FIFO_DEPTH
#define EUSART3_FIFO_DEPTH EUSART0_FIFO_DEPTH
#define EUSART4_FIFO_DEPTH EUSART0_FIFO_DEPTH
#define EUSART_FIFO_DEPTH(n) (((n) == 0) ? EUSART0_FIFO_DEPTH \
: ((n) == 1) ? EUSART1_FIFO_DEPTH \
: ((n) == 2) ? EUSART2_FIFO_DEPTH \
: ((n) == 3) ? EUSART3_FIFO_DEPTH \
: ((n) == 4) ? EUSART4_FIFO_DEPTH \
: 0x0UL)
#endif /* EUSART_FIFO_DEPTH */
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
@ -162,7 +191,7 @@ typedef enum {
typedef enum {
eusartDataBits7 = EUSART_FRAMECFG_DATABITS_SEVEN, ///< 7 data bits.
eusartDataBits8 = EUSART_FRAMECFG_DATABITS_EIGHT, ///< 8 data bits.
eusartDataBits9 = EUSART_FRAMECFG_DATABITS_NINE, ///< 9 data bits.
eusartDataBits9 = EUSART_FRAMECFG_DATABITS_NINE, ///< 9 data bits.
#if defined(EUSART_PRESENT)
eusartDataBits10 = EUSART_FRAMECFG_DATABITS_TEN, ///< 10 data bits, SPI mode only.
eusartDataBits11 = EUSART_FRAMECFG_DATABITS_ELEVEN, ///< 11 data bits, SPI mode only.
@ -284,30 +313,20 @@ typedef enum {
eusartInvertIOEnable = (EUSART_CFG0_RXINV_ENABLE | EUSART_CFG0_TXINV_ENABLE)
} EUSART_InvertIO_TypeDef;
#if defined(EUSART_PRESENT)
/// Clock polarity/phase mode.
typedef enum {
/// Clock idle low, sample on rising edge.
eusartClockMode0 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLELEADING,
/// Auto TX delay transmission.
SL_ENUM(EUSART_AutoTxDelay_TypeDef) {
/// Frames are transmitted immediately.
eusartAutoTxDelayNone = EUSART_TIMINGCFG_TXDELAY_NONE,
/// Clock idle low, sample on falling edge.
eusartClockMode1 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLETRAILING,
/// Transmission of new frames is delayed by a single bit period.
eusartAutoTxDelaySingle = EUSART_TIMINGCFG_TXDELAY_SINGLE,
/// Clock idle high, sample on falling edge.
eusartClockMode2 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLELEADING,
/// Transmission of new frames is delayed by a two bit periods.
eusartAutoTxDelayDouble = EUSART_TIMINGCFG_TXDELAY_DOUBLE,
/// Clock idle high, sample on rising edge.
eusartClockMode3 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLETRAILING
} EUSART_ClockMode_TypeDef;
/// Chip select polarity.
typedef enum {
/// Chip select active low.
eusartCsActiveLow = EUSART_CFG2_CSINV_AL,
/// Chip select active high.
eusartCsActiveHigh = EUSART_CFG2_CSINV_AH,
} EUSART_CsPolarity_TypeDef;
/// Transmission of new frames is delayed by a three bit periods.
eusartAutoTxDelayTripple = EUSART_TIMINGCFG_TXDELAY_TRIPPLE
};
/// RX FIFO Interrupt ans Status Watermark.
typedef enum {
@ -353,6 +372,31 @@ typedef enum {
#endif
} EUSART_TxFifoWatermark_TypeDef;
#if defined(EUSART_PRESENT)
/// Clock polarity/phase mode.
typedef enum {
/// Clock idle low, sample on rising edge.
eusartClockMode0 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLELEADING,
/// Clock idle low, sample on falling edge.
eusartClockMode1 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLETRAILING,
/// Clock idle high, sample on falling edge.
eusartClockMode2 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLELEADING,
/// Clock idle high, sample on rising edge.
eusartClockMode3 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLETRAILING
} EUSART_ClockMode_TypeDef;
/// Chip select polarity.
typedef enum {
/// Chip select active low.
eusartCsActiveLow = EUSART_CFG2_CSINV_AL,
/// Chip select active high.
eusartCsActiveHigh = EUSART_CFG2_CSINV_AH,
} EUSART_CsPolarity_TypeDef;
#if defined(EUSART_DALICFG_DALIEN)
/// DALI TX databits (8-32).
typedef enum {
@ -459,6 +503,15 @@ typedef struct {
/// Multiprocessor address bit value. If true, 9th bit of address frame must bit 1, 0 otherwise.
bool multiProcessorAddressBitHigh;
/// Auto TX delay before new transfers. Frames sent back-to-back are not delayed.
EUSART_AutoTxDelay_TypeDef autoTxDelay;
/// Interrupt and status level of the Receive FIFO.
EUSART_RxFifoWatermark_TypeDef RxFifoWatermark;
/// Interrupt and status level of the Transmit FIFO.
EUSART_TxFifoWatermark_TypeDef TxFifoWatermark;
} EUSART_AdvancedInit_TypeDef;
/// Initialization structure.
@ -649,21 +702,24 @@ typedef struct {
#define EUSART_DEFAULT_START_FRAME 0x00u
/// Default configuration for EUSART advanced initialization structure.
#define EUSART_ADVANCED_INIT_DEFAULT \
{ \
eusartHwFlowControlNone, /* Flow control disabled. */ \
false, /* Collision detection disabled. */ \
false, /* Data is sent with the least significant bit first. */ \
eusartInvertIODisable, /* RX and TX signal active high. */ \
false, /* No DMA wake up on reception. */ \
false, /* No DMA wake up on transmission. */ \
false, /* Halt DMA on error disabled. */ \
EUSART_DEFAULT_START_FRAME, /* No start frame. */ \
false, /* TX auto tristate disabled. */ \
false, /* Do not use PRS signal as RX signal.*/ \
(EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \
false, /* Multiprocessor mode disabled. */ \
false, /* Multiprocessor address bit : 0.*/ \
#define EUSART_ADVANCED_INIT_DEFAULT \
{ \
eusartHwFlowControlNone, /* Flow control disabled. */ \
false, /* Collision detection disabled. */ \
false, /* Data is sent with the least significant bit first. */ \
eusartInvertIODisable, /* RX and TX signal active high. */ \
false, /* No DMA wake up on reception. */ \
false, /* No DMA wake up on transmission. */ \
false, /* Halt DMA on error disabled. */ \
EUSART_DEFAULT_START_FRAME, /* No start frame. */ \
false, /* TX auto tristate disabled. */ \
false, /* Do not use PRS signal as RX signal.*/ \
(EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \
false, /* Multiprocessor mode disabled. */ \
false, /* Multiprocessor address bit : 0.*/ \
eusartAutoTxDelayNone, /* Frames are transmitted immediately */ \
eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \
eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \
}
/// Default configuration for EUSART initialization structure in UART mode with low-frequency clock.
@ -764,21 +820,24 @@ typedef struct {
#if defined(EUSART_DALICFG_DALIEN)
/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock.
/// Default configuration for EUSART advanced initialization structure.
#define EUSART_ADVANCED_DALI_INIT_DEFAULT \
{ \
eusartHwFlowControlNone, /* Flow control disabled. */ \
false, /* Collision detection disabled. */ \
true, /* Data is sent with the most significant bit first. */ \
eusartInvertIODisable, /* RX and TX signal active high. */ \
false, /* No DMA wake up on reception. */ \
false, /* No DMA wake up on transmission. */ \
false, /* Halt DMA on error disabled. */ \
EUSART_DEFAULT_START_FRAME, /* No start frame. */ \
false, /* TX auto tristate disabled. */ \
false, /* Do not use PRS signal as RX signal.*/ \
(EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \
false, /* Multiprocessor mode disabled. */ \
false, /* Multiprocessor address bit : 0.*/ \
#define EUSART_ADVANCED_DALI_INIT_DEFAULT \
{ \
eusartHwFlowControlNone, /* Flow control disabled. */ \
false, /* Collision detection disabled. */ \
true, /* Data is sent with the most significant bit first. */ \
eusartInvertIODisable, /* RX and TX signal active high. */ \
false, /* No DMA wake up on reception. */ \
false, /* No DMA wake up on transmission. */ \
false, /* Halt DMA on error disabled. */ \
EUSART_DEFAULT_START_FRAME, /* No start frame. */ \
false, /* TX auto tristate disabled. */ \
false, /* Do not use PRS signal as RX signal.*/ \
(EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \
false, /* Multiprocessor mode disabled. */ \
false, /* Multiprocessor address bit : 0.*/ \
eusartAutoTxDelayNone, /* Frames are transmitted immediately */ \
eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \
eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \
}
/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock.
@ -1046,7 +1105,7 @@ void EUSART_TxTristateSet(EUSART_TypeDef *eusart,
* Initialize the automatic enabling of transmissions and/or reception using
* the PRS as a trigger.
* @note
* Initialize EUSART with sl_eusart_initHf() or sl_eusart_initLf() before
* Initialize EUSART with EUSART_UartInitHf() or EUSART_UartInitLf() before
* enabling the PRS trigger.
*
* @param eusart Pointer to the EUSART peripheral register block.
@ -1155,6 +1214,10 @@ __STATIC_INLINE void EUSART_IntSet(EUSART_TypeDef *eusart, uint32_t flags)
eusart->IF_SET = flags;
}
#ifdef __cplusplus
}
#endif
/** @} (end addtogroup eusart) */
#endif /* defined(EUART_PRESENT) || defined(EUSART_PRESENT) */
#endif /* EM_EUSART_H */

24
gecko/emlib/inc/em_gpcrc.h
View File

@ -60,7 +60,7 @@ extern "C" {
* See this link for other polynomials:
* https://en.wikipedia.org/wiki/Cyclic_redundancy_check
*
* Before a CRC calculation can begin it is important to call the
* Before a CRC calculation can begin, call the
* @ref GPCRC_Start function. This function will reset CRC calculation
* by copying the configured initialization value over to the CRC data register.
*
@ -95,16 +95,16 @@ extern "C" {
typedef struct {
/**
* CRC polynomial value. GPCRC supports either a fixed 32-bit polynomial
* or a user configurable 16 bit polynomial. The fixed 32-bit polynomial
* or a user-configurable 16 bit polynomial. The fixed 32-bit polynomial
* is the one used in IEEE 802.3, which has the value 0x04C11DB7. To use the
* 32-bit fixed polynomial, just assign 0x04C11DB7 to the crcPoly field.
* 32-bit fixed polynomial, assign 0x04C11DB7 to the crcPoly field.
* To use a 16-bit polynomial, assign a value to crcPoly where the upper 16
* bits are zero.
*
* The polynomial should be written in normal bit order. For instance,
* to use the CRC-16 polynomial X^16 + X^15 + X^2 + 1, first convert
* it to hex representation and remove the highest order term
* of the polynomial. This would give us 0x8005 as the value to write into
* of the polynomial. This will give 0x8005 as the value to write into
* crcPoly.
*/
uint32_t crcPoly;
@ -190,10 +190,10 @@ __STATIC_INLINE void GPCRC_Enable(GPCRC_TypeDef * gpcrc, bool enable)
/***************************************************************************//**
* @brief
* Issues a command to initialize CRC calculation.
* Issue a command to initialize the CRC calculation.
*
* @details
* Issues the command INIT in GPCRC_CMD that initializes
* Issues the command INIT in GPCRC_CMD that initializes the
* CRC calculation by writing the initial values to the DATA register.
*
* @param[in] gpcrc
@ -222,7 +222,7 @@ __STATIC_INLINE void GPCRC_InitValueSet(GPCRC_TypeDef * gpcrc, uint32_t initValu
/***************************************************************************//**
* @brief
* Writes a 32-bit value to the input data register of the CRC.
* Write a 32-bit value to the input data register of the CRC.
*
* @details
* Use this function to write a 32-bit input data to the CRC. CRC
@ -242,7 +242,7 @@ __STATIC_INLINE void GPCRC_InputU32(GPCRC_TypeDef * gpcrc, uint32_t data)
/***************************************************************************//**
* @brief
* Writes a 16-bit value to the input data register of the CRC.
* Write a 16-bit value to the input data register of the CRC.
*
* @details
* Use this function to write a 16 bit input data to the CRC. CRC
@ -262,7 +262,7 @@ __STATIC_INLINE void GPCRC_InputU16(GPCRC_TypeDef * gpcrc, uint16_t data)
/***************************************************************************//**
* @brief
* Writes an 8-bit value to the input data register of the CRC.
* Write an 8-bit value to the CRC input data register.
*
* @details
* Use this function to write an 8-bit input data to the CRC. CRC
@ -282,7 +282,7 @@ __STATIC_INLINE void GPCRC_InputU8(GPCRC_TypeDef * gpcrc, uint8_t data)
/***************************************************************************//**
* @brief
* Reads the data register of the CRC.
* Read the CRC data register.
*
* @details
* Use this function to read the calculated CRC value.
@ -300,7 +300,7 @@ __STATIC_INLINE uint32_t GPCRC_DataRead(GPCRC_TypeDef * gpcrc)
/***************************************************************************//**
* @brief
* Reads the data register of the CRC bit reversed.
* Read the data register of the CRC bit reversed.
*
* @details
* Use this function to read the calculated CRC value bit reversed. When
@ -320,7 +320,7 @@ __STATIC_INLINE uint32_t GPCRC_DataReadBitReversed(GPCRC_TypeDef * gpcrc)
/***************************************************************************//**
* @brief
* Reads the data register of the CRC byte reversed.
* Read the data register of the CRC byte reversed.
*
* @details
* Use this function to read the calculated CRC value byte reversed.

56
gecko/emlib/inc/em_gpio.h
View File

@ -37,8 +37,8 @@
#include <stdbool.h>
#include "sl_assert.h"
#include "em_bus.h"
#include "sl_enum.h"
#include "sl_common.h"
#include "sl_enum.h"
#ifdef __cplusplus
extern "C" {
@ -1285,60 +1285,6 @@ __STATIC_INLINE void GPIO_Unlock(void)
GPIO->LOCK = GPIO_LOCK_LOCKKEY_UNLOCK;
}
/*******************************************************************************
*********************** DEPRECATED PROTOTYPES *****************************
*********************** (will be removed) *****************************
******************************************************************************/
/***************************************************************************//**
* @brief
* Configure GPIO interrupt.
*
* @details
* If reconfiguring a GPIO interrupt that is already enabled, it is generally
* recommended to disable it first, see @ref GPIO_IntDisable().
*
* The actual GPIO interrupt handler must be in place before enabling the
* interrupt.
*
* Notice that any pending interrupt for the selected pin is cleared by this
* function.
*
* @deprecated
* Deprecated function. New code should use @ref GPIO_ExtIntConfig().
*
* @note
* A certain pin number can only be associated with one port; i.e., if GPIO
* interrupt 1 is assigned to port A/pin 1, then it is not possible to use
* pin 1 from any other ports for interrupts. Refer to the reference
* manual. On devices which implement GPIO_EXTIPINSEL registers a more
* flexible approach is possible, refer to @ref GPIO_ExtIntConfig().
*
* @param[in] port
* The port to associate with @p pin.
*
* @param[in] pin
* The pin number on the port ( == GPIO EXTI interrupt number).
*
* @param[in] risingEdge
* Set to true if interrupts will be enabled on rising edge, otherwise false.
*
* @param[in] fallingEdge
* Set to true if interrupts will be enabled on falling edge, otherwise false.
*
* @param[in] enable
* Set to true if interrupt will be enabled after configuration completed,
* false to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable().
******************************************************************************/
__STATIC_INLINE SL_DEPRECATED_API_SDK_4_1 void GPIO_IntConfig(GPIO_Port_TypeDef port,
unsigned int pin,
bool risingEdge,
bool fallingEdge,
bool enable)
{
GPIO_ExtIntConfig(port, pin, pin, risingEdge, fallingEdge, enable);
}
/** @} (end addtogroup gpio) */
#ifdef __cplusplus

38
gecko/emlib/inc/em_i2c.h
View File

@ -165,7 +165,7 @@ typedef enum {
i2cClockHLRFast = _I2C_CTRL_CLHR_FAST /**< Ratio is 11:3 */
} I2C_ClockHLR_TypeDef;
/** Return codes for single master mode transfer function. */
/** Return codes for single Controller mode transfer function. */
typedef enum {
/* In progress code (>0) */
i2cTransferInProgress = 1, /**< Transfer in progress. */
@ -190,19 +190,19 @@ typedef struct {
/** Enable I2C peripheral when initialization completed. */
bool enable;
/** Set to master (true) or slave (false) mode */
/** Set to Controller (true) or Target (false) mode */
bool master;
/**
* I2C reference clock assumed when configuring bus frequency setup.
* Set it to 0 if currently configured reference clock will be used
* This parameter is only applicable if operating in master mode.
* This parameter is only applicable if operating in Controller mode.
*/
uint32_t refFreq;
/**
* (Max) I2C bus frequency to use. This parameter is only applicable
* if operating in master mode.
* if operating in Controller mode.
*/
uint32_t freq;
@ -214,7 +214,7 @@ typedef struct {
#define I2C_INIT_DEFAULT \
{ \
true, /* Enable when initialization done. */ \
true, /* Set to master mode. */ \
true, /* Set to Controller mode. */ \
0, /* Use currently configured reference clock. */ \
I2C_FREQ_STANDARD_MAX, /* Set to standard rate assuring being */ \
/* within I2C specification. */ \
@ -413,19 +413,19 @@ void I2C_Reset(I2C_TypeDef *i2c);
/***************************************************************************//**
* @brief
* Get slave address used for I2C peripheral (when operating in slave mode).
* Get Target address used for I2C peripheral (when operating in Target mode).
*
* @details
* For 10-bit addressing mode, the address is split in two bytes, and only
* the first byte setting is fetched, effectively only controlling the 2 most
* significant bits of the 10-bit address. Full handling of 10-bit addressing
* in slave mode requires additional SW handling.
* in Target mode requires additional SW handling.
*
* @param[in] i2c
* Pointer to I2C peripheral register block.
*
* @return
* I2C slave address in use. The 7 most significant bits define the actual
* I2C Target address in use. The 7 most significant bits define the actual
* address, the least significant bit is reserved and always returned as 0.
******************************************************************************/
__STATIC_INLINE uint8_t I2C_SlaveAddressGet(I2C_TypeDef *i2c)
@ -435,19 +435,19 @@ __STATIC_INLINE uint8_t I2C_SlaveAddressGet(I2C_TypeDef *i2c)
/***************************************************************************//**
* @brief
* Set slave address to use for I2C peripheral (when operating in slave mode).
* Set Target address to use for I2C peripheral (when operating in Target mode).
*
* @details
* For 10- bit addressing mode, the address is split in two bytes, and only
* the first byte is set, effectively only controlling the 2 most significant
* bits of the 10-bit address. Full handling of 10-bit addressing in slave
* bits of the 10-bit address. Full handling of 10-bit addressing in Target
* mode requires additional SW handling.
*
* @param[in] i2c
* Pointer to I2C peripheral register block.
*
* @param[in] addr
* I2C slave address to use. The 7 most significant bits define the actual
* I2C Target address to use. The 7 most significant bits define the actual
* address, the least significant bit is reserved and always set to 0.
******************************************************************************/
__STATIC_INLINE void I2C_SlaveAddressSet(I2C_TypeDef *i2c, uint8_t addr)
@ -457,14 +457,14 @@ __STATIC_INLINE void I2C_SlaveAddressSet(I2C_TypeDef *i2c, uint8_t addr)
/***************************************************************************//**
* @brief
* Get slave address mask used for I2C peripheral (when operating in slave
* Get Target address mask used for I2C peripheral (when operating in Target
* mode).
*
* @details
* The address mask defines how the comparator works. A bit position with
* value 0 means that the corresponding slave address bit is ignored during
* value 0 means that the corresponding Target address bit is ignored during
* comparison (don't care). A bit position with value 1 means that the
* corresponding slave address bit must match.
* corresponding Target address bit must match.
*
* For 10-bit addressing mode, the address is split in two bytes, and only
* the mask for the first address byte is fetched, effectively only
@ -474,7 +474,7 @@ __STATIC_INLINE void I2C_SlaveAddressSet(I2C_TypeDef *i2c, uint8_t addr)
* Pointer to I2C peripheral register block.
*
* @return
* I2C slave address mask in use. The 7 most significant bits define the
* I2C Target address mask in use. The 7 most significant bits define the
* actual address mask, the least significant bit is reserved and always
* returned as 0.
******************************************************************************/
@ -485,14 +485,14 @@ __STATIC_INLINE uint8_t I2C_SlaveAddressMaskGet(I2C_TypeDef *i2c)
/***************************************************************************//**
* @brief
* Set slave address mask used for I2C peripheral (when operating in slave
* Set Target address mask used for I2C peripheral (when operating in Target
* mode).
*
* @details
* The address mask defines how the comparator works. A bit position with
* value 0 means that the corresponding slave address bit is ignored during
* value 0 means that the corresponding Target address bit is ignored during
* comparison (don't care). A bit position with value 1 means that the
* corresponding slave address bit must match.
* corresponding Target address bit must match.
*
* For 10-bit addressing mode, the address is split in two bytes, and only
* the mask for the first address byte is set, effectively only controlling
@ -502,7 +502,7 @@ __STATIC_INLINE uint8_t I2C_SlaveAddressMaskGet(I2C_TypeDef *i2c)
* Pointer to I2C peripheral register block.
*
* @param[in] mask
* I2C slave address mask to use. The 7 most significant bits define the
* I2C Target address mask to use. The 7 most significant bits define the
* actual address mask, the least significant bit is reserved and should
* be 0.
******************************************************************************/

76
gecko/emlib/inc/em_lcd.h
View File

@ -50,11 +50,24 @@ extern "C" {
******************************** DEFINES **********************************
******************************************************************************/
/** Default Clock Prescaler. */
#define LCD_DEFAULT_CLOCK_PRESCALER 64
/** Default LCD Frame Rate Divisor. */
#define LCD_DEFAULT_FRAME_RATE_DIV 4
/** Default LCD Contrast. */
#define LCD_DEFAULT_CONTRAST 15
#if defined(_SILICON_LABS_32B_SERIES_2)
/** Maximum common lines of LCD. */
#if defined(LCD_OCTAPLEX) && (LCD_OCTAPLEX == 1)
#define LCD_COM_LINES_MAX (LCD_COM_NUM + LCD_SEGASCOM_NUM)
#else
#define LCD_COM_LINES_MAX LCD_COM_NUM
#endif
/** Maximum segment lines of LCD. */
#define LCD_SEGMENT_LINES_MAX LCD_SEG_NUM
#endif
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
@ -72,12 +85,12 @@ typedef enum {
#if defined(LCD_DISPCTRL_MUXE_MUXE)
/** Sextaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]). */
lcdMuxSextaplex = LCD_DISPCTRL_MUXE_MUXE | LCD_DISPCTRL_MUX_DUPLEX,
/** Octaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]). */
/** Octaplex / 1/8 Duty cycle (segments can be multiplexed with LCD_COM[0:7]). */
lcdMuxOctaplex = LCD_DISPCTRL_MUXE_MUXE | LCD_DISPCTRL_MUX_QUADRUPLEX
#elif defined(LCD_DISPCTRL_MUX_SEXTAPLEX)
/** Sextaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]). */
lcdMuxSextaplex = LCD_DISPCTRL_MUX_SEXTAPLEX,
/** Octaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]). */
/** Octaplex / 1/8 Duty cycle (segments can be multiplexed with LCD_COM[0:7]). */
lcdMuxOctaplex = LCD_DISPCTRL_MUX_OCTAPLEX,
#endif
} LCD_Mux_TypeDef;
@ -247,7 +260,23 @@ typedef enum {
/** Starts synchronizing registers after a write to SEGD2. */
lcdLoadAddrSegd2 = LCD_UPDATECTRL_LOADADDR_SEGD2WR,
/** Starts synchronizing registers after a write to SEGD3. */
lcdLoadAddrSegd3 = LCD_UPDATECTRL_LOADADDR_SEGD3WR
lcdLoadAddrSegd3 = LCD_UPDATECTRL_LOADADDR_SEGD3WR,
#if defined(LCD_UPDATECTRL_LOADADDR_SEGD4WR)
/** Starts synchronizing registers after a write to SEGD4. */
lcdLoadAddrSegd4 = LCD_UPDATECTRL_LOADADDR_SEGD4WR,
#endif
#if defined(LCD_UPDATECTRL_LOADADDR_SEGD5WR)
/** Starts synchronizing registers after a write to SEGD5. */
lcdLoadAddrSegd5 = LCD_UPDATECTRL_LOADADDR_SEGD5WR,
#endif
#if defined(LCD_UPDATECTRL_LOADADDR_SEGD6WR)
/** Starts synchronizing registers after a write to SEGD6. */
lcdLoadAddrSegd6 = LCD_UPDATECTRL_LOADADDR_SEGD6WR,
#endif
#if defined(LCD_UPDATECTRL_LOADADDR_SEGD7WR)
/** Starts synchronizing registers after a write to SEGD7. */
lcdLoadAddrSegd7 = LCD_UPDATECTRL_LOADADDR_SEGD7WR,
#endif
} LCD_LoadAddr_TypeDef;
#endif
@ -284,10 +313,13 @@ typedef enum {
typedef enum {
/** Disable charge redistribution. */
lcdChargeRedistributionDisable = LCD_DISPCTRL_CHGRDST_DISABLE,
/** Enable charge redistribution. */
/** Use 1 prescaled low frequency clock cycle for charge redistribution. */
lcdChargeRedistributionEnable = LCD_DISPCTRL_CHGRDST_ONE,
/** Use 2 prescaled low frequency clock cycle for charge redistribution. */
lcdChargeRedistributionTwoCycle = LCD_DISPCTRL_CHGRDST_TWO,
/** Use 3 prescaled low frequency clock cycle for charge redistribution. */
lcdChargeRedistributionThreeCycle = LCD_DISPCTRL_CHGRDST_THREE,
/** Use 4 prescaled low frequency clock cycle for charge redistribution. */
lcdChargeRedistributionFourCycle = LCD_DISPCTRL_CHGRDST_FOUR
} LCD_ChargeRedistribution_TypeDef;
#endif
@ -356,8 +388,14 @@ typedef struct {
LCD_Mode_Typedef mode;
/** Charge redistribution cycles. */
LCD_ChargeRedistribution_TypeDef chargeRedistribution;
/** Frame rate divider. */
uint8_t frameRateDivider;
/** Contrast level. */
int contrastLevel;
#if defined(_SILICON_LABS_32B_SERIES_2)
/** Clock Prescaler. */
uint32_t clockPrescaler;
#endif
#endif
} LCD_Init_TypeDef;
@ -398,7 +436,8 @@ typedef struct {
lcdModeStepDown, \
lcdChargeRedistributionEnable, \
LCD_DEFAULT_FRAME_RATE_DIV, \
LCD_DEFAULT_CONTRAST \
LCD_DEFAULT_CONTRAST, \
LCD_DEFAULT_CLOCK_PRESCALER \
}
#endif
@ -459,7 +498,7 @@ __STATIC_INLINE void LCD_LoadBusyWait(void)
#if defined(_SILICON_LABS_32B_SERIES_2)
/***************************************************************************//**
* @brief
* Waits for the LCD to complete resetting or disabling procedure.
* Wait for the LCD to complete resetting or disabling procedure.
******************************************************************************/
__STATIC_INLINE void LCD_ReadyWait(void)
{
@ -521,14 +560,15 @@ __STATIC_INLINE void LCD_Reset(void)
{
LCD->SWRST_SET = LCD_SWRST_SWRST;
/* Wait for reset to complete. s*/
while ((LCD->SWRST & _LCD_SWRST_RESETTING_MASK)) ;
/* Wait for reset to complete. */
while ((LCD->SWRST & _LCD_SWRST_RESETTING_MASK)) {
}
}
#endif
/***************************************************************************//**
* @brief
* Enables or disables LCD Animation feature.
* Enable or disable LCD Animation feature.
*
* @param[in] enable
* Boolean true enables animation, false disables animation.
@ -552,7 +592,7 @@ __STATIC_INLINE void LCD_AnimEnable(bool enable)
/***************************************************************************//**
* @brief
* Enables or disables LCD blink.
* Enable or disable the LCD blink.
*
* @param[in] enable
* Boolean true enables blink, false disables blink.
@ -576,7 +616,7 @@ __STATIC_INLINE void LCD_BlinkEnable(bool enable)
/***************************************************************************//**
* @brief
* Disables all segments, while keeping segment state.
* Disable all segments while keeping segment state.
*
* @param[in] enable
* Boolean true clears all segments, boolean false restores all segment lines.
@ -600,7 +640,7 @@ __STATIC_INLINE void LCD_BlankEnable(bool enable)
/***************************************************************************//**
* @brief
* Enables or disables LCD Frame counter.
* Enable or disable LCD Frame counter.
*
* @param[in] enable
* Boolean true enables frame counter, false disables frame counter.
@ -630,7 +670,7 @@ __STATIC_INLINE void LCD_FrameCountEnable(bool enable)
#if defined(_SILICON_LABS_32B_SERIES_2)
/***************************************************************************//**
* @brief
* Enables or disables LCD Display counter.
* Enable or disable the LCD Display counter.
*
* @param[in] enable
* Boolean true enables display counter, false disables display counter.
@ -650,7 +690,7 @@ __STATIC_INLINE void LCD_DisplayCountEnable(bool enable)
/***************************************************************************//**
* @brief
* Returns current animation state.
* Return the current animation state.
*
* @return
* Animation state, in range 0-15.
@ -662,7 +702,7 @@ __STATIC_INLINE int LCD_AnimState(void)
/***************************************************************************//**
* @brief
* Returns current blink state.
* Return the current blink state.
*
* @return
* Return value is 1 if segments are enabled, 0 if disabled.
@ -694,7 +734,7 @@ __STATIC_INLINE void LCD_FreezeEnable(bool enable)
#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
/***************************************************************************//**
* @brief
* Returns SYNCBUSY bits, indicating which registers have pending updates.
* Return SYNCBUSY bits, indicating which registers have pending updates.
*
* @return
* Bit fields for LCD registers that have pending updates.
@ -708,7 +748,7 @@ __STATIC_INLINE uint32_t LCD_SyncBusyGet(void)
#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
/***************************************************************************//**
* @brief
* Polls LCD SYNCBUSY flags, until flag has been cleared.
* Poll LCD SYNCBUSY flags until the flag has been cleared.
*
* @param[in] flags
* Bit fields for LCD registers that will be updated before we continue.
@ -811,7 +851,7 @@ __STATIC_INLINE uint32_t LCD_IntGetEnabled(void)
{
uint32_t ien;
/* Stores LCD->IEN in temporary variable in order to define explicit order
/* Store the LCD->IEN in temporary variable to define the explicit order
* of volatile accesses. */
ien = LCD->IEN;

1323
gecko/emlib/inc/em_ldma.h
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File diff suppressed because it is too large Load Diff

250
gecko/emlib/inc/em_lesense.h
View File

@ -48,7 +48,10 @@ extern "C" {
/** Number of decoder states supported by current device. */
#define LESENSE_NUM_DECODER_STATES (_LESENSE_DECSTATE_DECSTATE_MASK + 1)
#if defined(_SILICON_LABS_32B_SERIES_2)
/** Number of ARCs supported by current device. Number of ARCS is the number of states times 2 */
#define LESENSE_NUM_ARCS (LESENSE_NUM_DECODER_STATES << 1)
#endif
/** Number of LESENSE channels. */
#define LESENSE_NUM_CHANNELS 16
@ -352,7 +355,7 @@ typedef enum {
lesenseDecInputPRS = LESENSE_DECCTRL_INPUT_PRS
} LESENSE_DecInput_TypeDef;
#else
/** Ocelot only provides SENSORSTATE as input for the decoder. */
/** Ocelot only provides SENSORSTATE as input for the decoder. */
#endif
/** Compare source selection for sensor sampling. */
@ -379,16 +382,21 @@ typedef enum {
/** Interrupt generation setup for CHx interrupt flag. */
typedef enum {
/** No interrupt is generated. */
lesenseSetIntNone = LESENSE_CH_INTERACT_SETIF_NONE,
lesenseSetIntNone = LESENSE_CH_INTERACT_SETIF_NONE,
/** Set interrupt flag if the sensor triggers. */
lesenseSetIntLevel = LESENSE_CH_INTERACT_SETIF_LEVEL,
lesenseSetIntLevel = LESENSE_CH_INTERACT_SETIF_LEVEL,
/** Set interrupt flag on positive edge of the sensor state. */
lesenseSetIntPosEdge = LESENSE_CH_INTERACT_SETIF_POSEDGE,
lesenseSetIntPosEdge = LESENSE_CH_INTERACT_SETIF_POSEDGE,
/** Set interrupt flag on negative edge of the sensor state. */
lesenseSetIntNegEdge = LESENSE_CH_INTERACT_SETIF_NEGEDGE
lesenseSetIntNegEdge = LESENSE_CH_INTERACT_SETIF_NEGEDGE,
#if defined(LESENSE_CH_INTERACT_SETIF_BOTHEDGES)
/** Set interrupt flag on both edges of the sensor state. */
lesenseSetIntBothEdges = LESENSE_CH_INTERACT_SETIF_BOTHEDGES
#endif
} LESENSE_ChIntMode_TypeDef;
/** Channel pin mode for the excitation phase of the scan sequence. */
@ -487,6 +495,41 @@ typedef enum {
} LESENSE_ChCompMode_TypeDef;
#endif
/** Mode of Storing of Sensor Sample in Result Buffer. */
#if defined(_SILICON_LABS_32B_SERIES_0)
typedef enum {
/** Nothing will be stored in the result buffer. */
lesenseStoreSampleDisable = _LESENSE_CH_EVAL_STRSAMPLE_DEFAULT,
/** The sensor sample data will be stored in the result buffer. */
lesenseStoreSampleData = _LESENSE_CH_EVAL_STRSAMPLE_MASK >> _LESENSE_CH_EVAL_STRSAMPLE_SHIFT
} LESENSE_StoreSample_TypeDef;
#elif defined (_SILICON_LABS_32B_SERIES_1)
typedef enum {
/** Nothing will be stored in the result buffer. */
lesenseStoreSampleDisable = _LESENSE_CH_EVAL_STRSAMPLE_DISABLE,
/** The sensor sample data will be stored in the result buffer. */
lesenseStoreSampleData = _LESENSE_CH_EVAL_STRSAMPLE_DATA,
/** The data source (i.e. the channel) will be stored alongside the sensor
* sample data. */
lesenseStoreSampleDataSrc = _LESENSE_CH_EVAL_STRSAMPLE_DATASRC
} LESENSE_StoreSample_TypeDef;
#else
typedef enum {
/** Nothing will be stored in the result buffer. */
lesenseStoreSampleDisable = _LESENSE_CH_EVALCFG_STRSAMPLE_DISABLE,
/** The sensor sample data will be stored in the result buffer. */
lesenseStoreSampleData = _LESENSE_CH_EVALCFG_STRSAMPLE_DATA,
/** The data source (i.e. the channel) will be stored alongside the sensor
* sample data. */
lesenseStoreSampleDataSrc = _LESENSE_CH_EVALCFG_STRSAMPLE_DATASRC
} LESENSE_StoreSample_TypeDef;
#endif
/** Sensor evaluation modes. */
#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
#if defined(_LESENSE_CH_EVAL_MODE_MASK)
@ -706,18 +749,18 @@ typedef struct {
true /* Keep LESENSE running in debug mode. */ \
}
#else
#define LESENSE_CORECTRL_DESC_DEFAULT \
{ \
lesenseScanStartPeriodic,/* Start new scan each time the period counter overflows. */ \
lesensePRSCh0, /* Default PRS channel is selected. */ \
lesenseScanConfDirMap, /* Direct mapping SCANCONF register usage strategy. */ \
false, /* Do not invert ACMP0 output. */ \
false, /* Do not invert ACMP1 output. */ \
false, /* Disable dual sampling. */ \
true, /* Store scan result after each scan. */ \
15u, /* Default value for the fifo trigger level */ \
lesenseDMAWakeUpDisable, /* Do not wake up on DMA from EM2. */ \
true /* Keep LESENSE running in debug mode. */ \
#define LESENSE_CORECTRL_DESC_DEFAULT \
{ \
lesenseScanStartPeriodic,/* Start new scan each time the period counter overflows. */ \
lesensePRSCh0, /* Default PRS channel is selected. */ \
lesenseScanConfDirMap, /* Direct mapping SCANCONF register usage strategy. */ \
false, /* Do not invert ACMP0 output. */ \
false, /* Do not invert ACMP1 output. */ \
false, /* Disable dual sampling. */ \
true, /* Store scan result after each scan. */ \
15u, /* Default value for the FIFO trigger level */ \
lesenseDMAWakeUpDisable, /* Do not wake up on DMA from EM2. */ \
true /* Keep LESENSE running in debug mode. */ \
}
#endif
@ -929,15 +972,15 @@ typedef struct {
lesensePRSCh3, /* PRS Channel 3 as input for bit 3 of LESENSE decoder. */ \
}
#else
#define LESENSE_DECCTRL_DESC_DEFAULT \
{ \
false, /* Disable check of current state. */ \
true, /* Enable channel x % 16 interrupt on state x change. */ \
true, /* Enable decoder hysteresis on PRS0 output. */ \
true, /* Enable decoder hysteresis on PRS1 output. */ \
true, /* Enable decoder hysteresis on PRS2 output. */ \
true, /* Enable decoder hysteresis on PRS3 output. */ \
false, /* Disable count mode on decoder PRS channels 0 and 1*/ \
#define LESENSE_DECCTRL_DESC_DEFAULT \
{ \
false, /* Disable check of current state. */ \
true, /* Enable channel x % 16 interrupt on state x change. */ \
true, /* Enable decoder hysteresis on PRS0 output. */ \
true, /* Enable decoder hysteresis on PRS1 output. */ \
true, /* Enable decoder hysteresis on PRS2 output. */ \
true, /* Enable decoder hysteresis on PRS3 output. */ \
false, /* Disable count mode on decoder PRS channels 0 and 1*/ \
}
#endif
@ -996,7 +1039,7 @@ typedef struct {
/** Set to store counter value in the RAM (accessible via RESDATA) and make
* the comparison result available in the SCANRES register. */
bool storeCntRes;
LESENSE_StoreSample_TypeDef storeCntRes;
/** Select clock used for the excitation timing. */
LESENSE_ChClk_TypeDef exClk;
@ -1043,10 +1086,17 @@ typedef struct {
/** Select the mode for counter comparison. */
LESENSE_ChCompMode_TypeDef compMode;
#if defined(_LESENSE_CH_EVAL_MODE_MASK) || defined(_SILICON_LABS_32B_SERIES_2)
#if defined(_LESENSE_CH_EVAL_MODE_MASK) || defined(_LESENSE_CH_EVALCFG_MODE_MASK)
/** Select the sensor evaluation mode. */
LESENSE_ChEvalMode_TypeDef evalMode;
#endif
#if defined(_LESENSE_CH_INTERACT_OFFSET_MASK)
/** Offset for IADC/ACMP interaction.
* ACMP: offset determines which of the port I/O pins on the external override interface
* to access.
* IADC: offset determines which of the IADC scanner channels is sampled. */
uint8_t offset;
#endif
} LESENSE_ChDesc_TypeDef;
/** Configuration structure for all the scan channels. */
@ -1056,52 +1106,77 @@ typedef struct {
} LESENSE_ChAll_TypeDef;
/** Default configuration for the scan channel. */
#if defined(_LESENSE_CH_EVAL_MODE_MASK) || defined(_SILICON_LABS_32B_SERIES_2)
#define LESENSE_CH_CONF_DEFAULT \
{ \
false, /* Disable scan channel. */ \
false, /* Disable assigned pin on scan channel. */ \
false, /* Disable interrupts on channel. */ \
lesenseChPinExDis, /* Channel pin is disabled during excitation period. */ \
lesenseChPinIdleDis, /* Channel pin is disabled during idle period. */ \
false, /* Do not use alternate excitation pins for excitation. */ \
false, /* Disabled to shift results from this channel to decoder register. */ \
false, /* Disabled to invert scan result bit. */ \
false, /* Disabled to store counter value in result buffer. */ \
lesenseClkLF, /* Use LF clock for excitation timing. */ \
lesenseClkLF, /* Use LF clock for sample timing. */ \
0x00U, /* Excitation time is set to 0(+1) excitation clock cycles. */ \
0x00U, /* Sample delay is set to 0(+1) sample clock cycles. */ \
0x00U, /* Measure delay is set to 0 excitation clock cycles.*/ \
0x00U, /* ACMP threshold has been set to 0. */ \
lesenseSampleModeACMP, /* ACMP output will be used in comparison. */ \
lesenseSetIntNone, /* No interrupt is generated by the channel. */ \
0x00U, /* Counter threshold has bee set to 0x00. */ \
lesenseCompModeLess, /* Compare mode has been set to trigger interrupt on "less". */ \
lesenseEvalModeThreshold /* Evaluation mode has been set to trigger interrupt on threshold. */ \
#if defined(_LESENSE_CH_EVALCFG_MODE_MASK) && defined(_LESENSE_CH_INTERACT_OFFSET_MASK)
#define LESENSE_CH_CONF_DEFAULT \
{ \
false, /* Disable scan channel. */ \
false, /* Disable assigned pin on scan channel. */ \
false, /* Disable interrupts on channel. */ \
lesenseChPinExDis, /* Channel pin is disabled during excitation period. */ \
lesenseChPinIdleDis, /* Channel pin is disabled during idle period. */ \
false, /* Do not use alternate excitation pins for excitation. */ \
false, /* Disabled to shift results from this channel to decoder register. */ \
false, /* Disabled to invert scan result bit. */ \
lesenseStoreSampleDisable,/* Disabled to store counter value in result buffer. */ \
lesenseClkLF, /* Use LF clock for excitation timing. */ \
lesenseClkLF, /* Use LF clock for sample timing. */ \
0x00U, /* Excitation time is set to 0(+1) excitation clock cycles. */ \
0x00U, /* Sample delay is set to 0(+1) sample clock cycles. */ \
0x00U, /* Measure delay is set to 0 excitation clock cycles.*/ \
0x00U, /* ACMP threshold has been set to 0. */ \
lesenseSampleModeACMP, /* ACMP output will be used in comparison. */ \
lesenseSetIntNone, /* No interrupt is generated by the channel. */ \
0x00U, /* Counter threshold has bee set to 0x00. */ \
lesenseCompModeLess, /* Compare mode has been set to trigger interrupt on "less". */ \
lesenseEvalModeThreshold, /* Evaluation mode has been set to trigger interrupt on threshold. */ \
0x00U /* No offset for IADC or ACMP interaction. */ \
}
#else
#define LESENSE_CH_CONF_DEFAULT \
{ \
false, /* Disable scan channel. */ \
false, /* Disable assigned pin on scan channel. */ \
false, /* Disable interrupts on channel. */ \
lesenseChPinExDis, /* Channel pin is disabled during excitation period. */ \
lesenseChPinIdleDis, /* Channel pin is disabled during idle period. */ \
false, /* Do not use alternate excitation pins for excitation. */ \
false, /* Disabled to shift results from this channel to decoder register. */ \
false, /* Disabled to invert scan result bit. */ \
false, /* Disabled to store counter value in result buffer. */ \
lesenseClkLF, /* Use LF clock for excitation timing. */ \
lesenseClkLF, /* Use LF clock for sample timing. */ \
0x00U, /* Excitation time is set to 0(+1) excitation clock cycles. */ \
0x00U, /* Sample delay is set to 0(+1) sample clock cycles. */ \
0x00U, /* Measure delay is set to 0 excitation clock cycles.*/ \
0x00U, /* ACMP threshold has been set to 0. */ \
lesenseSampleModeACMP, /* ACMP output will be used in comparison. */ \
lesenseSetIntNone, /* No interrupt is generated by the channel. */ \
0x00U, /* Counter threshold has bee set to 0x00. */ \
lesenseCompModeLess /* Compare mode has been set to trigger interrupt on "less". */ \
#elif defined(_LESENSE_CH_EVAL_MODE_MASK) /* _SILICON_LABS_32B_SERIES_1 */
#define LESENSE_CH_CONF_DEFAULT \
{ \
false, /* Disable scan channel. */ \
false, /* Disable assigned pin on scan channel. */ \
false, /* Disable interrupts on channel. */ \
lesenseChPinExDis, /* Channel pin is disabled during excitation period. */ \
lesenseChPinIdleDis, /* Channel pin is disabled during idle period. */ \
false, /* Do not use alternate excitation pins for excitation. */ \
false, /* Disabled to shift results from this channel to decoder register. */ \
false, /* Disabled to invert scan result bit. */ \
lesenseStoreSampleDisable,/* Disabled to store counter value in result buffer. */ \
lesenseClkLF, /* Use LF clock for excitation timing. */ \
lesenseClkLF, /* Use LF clock for sample timing. */ \
0x00U, /* Excitation time is set to 0(+1) excitation clock cycles. */ \
0x00U, /* Sample delay is set to 0(+1) sample clock cycles. */ \
0x00U, /* Measure delay is set to 0 excitation clock cycles.*/ \
0x00U, /* ACMP threshold has been set to 0. */ \
lesenseSampleModeACMP, /* ACMP output will be used in comparison. */ \
lesenseSetIntNone, /* No interrupt is generated by the channel. */ \
0x00U, /* Counter threshold has bee set to 0x00. */ \
lesenseCompModeLess, /* Compare mode has been set to trigger interrupt on "less". */ \
lesenseEvalModeThreshold /* Evaluation mode has been set to trigger interrupt on threshold. */ \
}
#else /* _SILICON_LABS_32B_SERIES_0 */
#define LESENSE_CH_CONF_DEFAULT \
{ \
false, /* Disable scan channel. */ \
false, /* Disable assigned pin on scan channel. */ \
false, /* Disable interrupts on channel. */ \
lesenseChPinExDis, /* Channel pin is disabled during excitation period. */ \
lesenseChPinIdleDis, /* Channel pin is disabled during idle period. */ \
false, /* Do not use alternate excitation pins for excitation. */ \
false, /* Disabled to shift results from this channel to decoder register. */ \
false, /* Disabled to invert scan result bit. */ \
lesenseStoreSampleDisable,/* Disabled to store counter value in result buffer. */ \
lesenseClkLF, /* Use LF clock for excitation timing. */ \
lesenseClkLF, /* Use LF clock for sample timing. */ \
0x00U, /* Excitation time is set to 0(+1) excitation clock cycles. */ \
0x00U, /* Sample delay is set to 0(+1) sample clock cycles. */ \
0x00U, /* Measure delay is set to 0 excitation clock cycles.*/ \
0x00U, /* ACMP threshold has been set to 0. */ \
lesenseSampleModeACMP, /* ACMP output will be used in comparison. */ \
lesenseSetIntNone, /* No interrupt is generated by the channel. */ \
0x00U, /* Counter threshold has bee set to 0x00. */ \
lesenseCompModeLess /* Compare mode has been set to trigger interrupt on "less". */ \
}
#endif
@ -1332,8 +1407,13 @@ typedef LESENSE_DecStCond_TypeDef LESENSE_DecStDesc_TypeDef;
/** Configuration structure for decoder. */
typedef struct {
#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
/** Descriptor of the 16 or 32 decoder states depending on the device. */
LESENSE_DecStDesc_TypeDef St[LESENSE_NUM_DECODER_STATES];
#else
/** Descriptor of the 64 Arcs on series 2 devices. */
LESENSE_DecStDesc_TypeDef St[LESENSE_NUM_ARCS];
#endif
} LESENSE_DecStAll_TypeDef;
/** Default configuration for all decoder states. */
@ -1463,7 +1543,7 @@ void LESENSE_ChannelTimingSet(uint8_t chIdx,
void LESENSE_ChannelThresSet(uint8_t chIdx,
uint16_t acmpThres,
uint16_t cntThres);
#if defined(_LESENSE_CH_EVAL_MODE_MASK) || defined(_SILICON_LABS_32B_SERIES_2)
#if defined(_LESENSE_CH_EVAL_MODE_MASK) || defined(_LESENSE_CH_EVALCFG_MODE_MASK)
void LESENSE_ChannelSlidingWindow(uint8_t chIdx,
uint32_t windowSize,
uint32_t initValue);
@ -1562,14 +1642,14 @@ __STATIC_INLINE uint32_t LESENSE_StatusGet(void)
* @li LESENSE_STATUS_DACACTIVE - The DAC interface is currently active.
* The OR combination of the following status bits for EFR series 2:
* @li LESENSE_STATUS_RESFIFOV - Result Fifo valid. Set when data is available
* in result Fifo. Cleared when Fifo is empty.
* @li LESENSE_STATUS_RESFIFOFULL - Result Fifo full. Set when result
* Fifo is full.
* @li LESENSE_STATUS_RESFIFOV - Result FIFO valid. Set when data is available
* in result FIFO. Cleared when FIFO is empty.
* @li LESENSE_STATUS_RESFIFOFULL - Result FIFO full. Set when result
* FIFO is full.
* @li LESENSE_STATUS_RUNNING - LESENSE is active.
* @li LESENSE_STATUS_SCANACTIVE - LESENSE is currently interfacing sensors.
* @li LESENSE_STATUS_FLUSHING - Fifo flushing
* @li LESENSE_STATUS_READBUSY - Fifo Read busy
* @li LESENSE_STATUS_FLUSHING - FIFO flushing
* @li LESENSE_STATUS_READBUSY - FIFO Read busy
******************************************************************************/
__STATIC_INLINE void LESENSE_StatusWait(uint32_t flag)
{
@ -1608,7 +1688,7 @@ __STATIC_INLINE uint32_t LESENSE_ScanResultGet(void)
/***************************************************************************//**
* @brief
* Get the oldest unread data from result buffer.
* Get the oldest unread data from the result buffer.
*
* @note
* Make sure that the STORERES bit is set in LESENSE_CHx_EVAL, or
@ -1631,7 +1711,7 @@ __STATIC_INLINE uint32_t LESENSE_ScanResultDataGet(void)
#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
/***************************************************************************//**
* @brief
* Get the data from result data buffer.
* Get data from the result data buffer.
*
* @note
* Make sure that the STORERES bit is set in LESENSE_CHx_EVAL, or
@ -1653,7 +1733,7 @@ __STATIC_INLINE uint32_t LESENSE_ScanResultDataBufferGet(uint32_t idx)
/***************************************************************************//**
* @brief
* Get the current state of LESENSE sensor.
* Get the current state of the LESENSE sensor.
*
* @return
* Returns the value of LESENSE_SENSORSTATE register that
@ -1667,7 +1747,7 @@ __STATIC_INLINE uint32_t LESENSE_SensorStateGet(void)
#if defined(LESENSE_POWERDOWN_RAM)
/***************************************************************************//**
* @brief
* Shut off the power to the LESENSE RAM, disables LESENSE.
* Shut off the power to the LESENSE RAM, which disables LESENSE.
*
* @details
* Shuts off the LESENSE RAM in order to decrease leakage

4
gecko/emlib/inc/em_letimer.h
View File

@ -285,7 +285,7 @@ __STATIC_INLINE void LETIMER_IntSet(LETIMER_TypeDef *letimer, uint32_t flags)
#if defined(_LETIMER_LOCK_MASK)
/***************************************************************************//**
* @brief
* Locks LETIMER registers.
* Lock LETIMER registers.
*
* @param[in] letimer
* Pointer to LETIMER peripheral register block.
@ -304,7 +304,7 @@ __STATIC_INLINE void LETIMER_Lock(LETIMER_TypeDef *letimer)
#if defined(_LETIMER_LOCK_MASK)
/***************************************************************************//**
* @brief
* Unlocks LETIMER registers.
* Unlock LETIMER registers.
*
* @param[in] letimer
* Pointer to LETIMER peripheral register block.

62
gecko/emlib/inc/em_msc.h
View File

@ -44,6 +44,7 @@
#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT)
#include "sli_tz_ns_interface.h"
#include "sli_tz_service_msc.h"
#include "sli_tz_s_interface.h"
#endif
#ifdef __cplusplus
@ -272,6 +273,17 @@ typedef struct {
{ 0, 1 }, \
}
#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)
/** xG26 chips incorporate 2 memory banks including ECC support. */
#define MSC_ECC_BANKS (2)
/** Default MSC EccConfig initialization */
#define MSC_ECCCONFIG_DEFAULT \
{ \
{ false, false }, \
{ 0, 1 }, \
}
#elif defined(_SILICON_LABS_32B_SERIES_2)
/** Series 2 chips incorporate 1 memory bank including ECC support. */
@ -319,13 +331,13 @@ typedef struct {
__STATIC_INLINE bool MSC_LockGetLocked(void)
{
#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT)
return (bool)sli_tz_ns_interface_dispatch_simple(
(sli_tz_simple_veneer_fn)sli_tz_msc_get_locked,
SLI_TZ_DISPATCH_UNUSED_ARG);
return (bool)sli_tz_ns_interface_dispatch_simple_noarg(
(sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args,
SLI_TZ_MSC_GET_LOCKED_SID);
#elif defined(_MSC_STATUS_REGLOCK_MASK)
return (MSC->STATUS & _MSC_STATUS_REGLOCK_MASK) != MSC_STATUS_REGLOCK_UNLOCKED;
#else
return (MSC->LOCK & _MSC_LOCK_MASK) != MSC_LOCK_LOCKKEY_UNLOCK;
return (MSC->LOCK & _MSC_LOCK_MASK) != MSC_LOCK_LOCKKEY_UNLOCKED;
#endif
}
@ -336,9 +348,9 @@ __STATIC_INLINE bool MSC_LockGetLocked(void)
__STATIC_INLINE void MSC_LockSetLocked(void)
{
#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT)
(void)sli_tz_ns_interface_dispatch_simple(
(sli_tz_simple_veneer_fn)sli_tz_msc_set_locked,
SLI_TZ_DISPATCH_UNUSED_ARG);
(void)sli_tz_ns_interface_dispatch_simple_noarg(
(sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args,
SLI_TZ_MSC_SET_LOCKED_SID);
#else
MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK;
#endif
@ -351,9 +363,9 @@ __STATIC_INLINE void MSC_LockSetLocked(void)
__STATIC_INLINE void MSC_LockSetUnlocked(void)
{
#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT)
(void)sli_tz_ns_interface_dispatch_simple(
(sli_tz_simple_veneer_fn)sli_tz_msc_set_unlocked,
SLI_TZ_DISPATCH_UNUSED_ARG);
(void)sli_tz_ns_interface_dispatch_simple_noarg(
(sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args,
SLI_TZ_MSC_SET_UNLOCKED_SID);
#else
MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK;
#endif
@ -369,9 +381,9 @@ __STATIC_INLINE void MSC_LockSetUnlocked(void)
__STATIC_INLINE uint32_t MSC_ReadCTRLGet(void)
{
#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT)
return sli_tz_ns_interface_dispatch_simple(
(sli_tz_simple_veneer_fn)sli_tz_msc_get_readctrl,
SLI_TZ_DISPATCH_UNUSED_ARG);
return sli_tz_ns_interface_dispatch_simple_noarg(
(sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args,
SLI_TZ_MSC_GET_READCTRL_SID);
#else
return MSC->READCTRL;
#endif
@ -388,7 +400,8 @@ __STATIC_INLINE void MSC_ReadCTRLSet(uint32_t value)
{
#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT)
(void)sli_tz_ns_interface_dispatch_simple(
(sli_tz_simple_veneer_fn)sli_tz_msc_set_readctrl,
(sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple,
SLI_TZ_MSC_SET_READCTRL_SID,
value);
#else
MSC->READCTRL = value;
@ -410,7 +423,8 @@ __STATIC_INLINE void MSC_PageLockSetLocked(uint32_t page_number)
{
#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT)
(void)sli_tz_ns_interface_dispatch_simple(
(sli_tz_simple_veneer_fn)sli_tz_msc_set_pagelock,
(sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple,
SLI_TZ_MSC_SET_PAGELOCK_SID,
page_number);
#else
EFM_ASSERT(page_number < (FLASH_SIZE / FLASH_PAGE_SIZE));
@ -440,7 +454,8 @@ __STATIC_INLINE bool MSC_PageLockGetLocked(uint32_t page_number)
{
#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT)
return (bool)sli_tz_ns_interface_dispatch_simple(
(sli_tz_simple_veneer_fn)sli_tz_msc_get_pagelock,
(sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple,
SLI_TZ_MSC_GET_PAGELOCK_SID,
page_number);
#else
EFM_ASSERT(page_number < (FLASH_SIZE / FLASH_PAGE_SIZE));
@ -469,9 +484,9 @@ __STATIC_INLINE bool MSC_PageLockGetLocked(uint32_t page_number)
__STATIC_INLINE uint32_t MSC_UserDataGetSize(void)
{
#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT)
return sli_tz_ns_interface_dispatch_simple(
(sli_tz_simple_veneer_fn)sli_tz_msc_get_userdata_size,
SLI_TZ_DISPATCH_UNUSED_ARG);
return sli_tz_ns_interface_dispatch_simple_noarg(
(sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args,
SLI_TZ_MSC_GET_USERDATA_SIZE_SID);
#else
return MSC->USERDATASIZE;
#endif
@ -492,9 +507,9 @@ __STATIC_INLINE uint32_t MSC_UserDataGetSize(void)
__STATIC_INLINE uint32_t MSC_MiscLockWordGet(void)
{
#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT)
return sli_tz_ns_interface_dispatch_simple(
(sli_tz_simple_veneer_fn)sli_tz_msc_get_misclockword,
SLI_TZ_DISPATCH_UNUSED_ARG);
return sli_tz_ns_interface_dispatch_simple_noarg(
(sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args,
SLI_TZ_MSC_GET_MISCLOCKWORD_SID);
#else
return MSC->MISCLOCKWORD;
#endif
@ -512,7 +527,8 @@ __STATIC_INLINE void MSC_MiscLockWordSet(uint32_t value)
{
#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT)
(void)sli_tz_ns_interface_dispatch_simple(
(sli_tz_simple_veneer_fn)sli_tz_msc_set_misclockword,
(sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple,
SLI_TZ_MSC_SET_MISCLOCKWORD_SID,
value);
#else
MSC->MISCLOCKWORD = value;

145
gecko/emlib/inc/em_pcnt.h
View File

@ -50,32 +50,34 @@ extern "C" {
******************************************************************************/
/** PCNT0 Counter register size. */
#if defined(_EFM32_GECKO_FAMILY)
#define PCNT0_CNT_SIZE (8) /* PCNT0 counter is 8 bits. */
#define PCNT0_CNT_SIZE (8) /**< PCNT0 counter is 8 bits. */
#else
#define PCNT0_CNT_SIZE (16) /* PCNT0 counter is 16 bits. */
#define PCNT0_CNT_SIZE (16) /**< PCNT0 counter is 16 bits. */
#endif
#ifdef PCNT1
/** PCNT1 Counter register size. */
#if defined(_SILICON_LABS_32B_SERIES_0)
#define PCNT1_CNT_SIZE (8) /* PCNT1 counter is 8 bits. */
#define PCNT1_CNT_SIZE (8) /**< PCNT1 counter is 8 bits. */
#else
#define PCNT1_CNT_SIZE (16) /* PCNT1 counter is 16 bits. */
#define PCNT1_CNT_SIZE (16) /**< PCNT1 counter is 16 bits. */
#endif
#endif
#ifdef PCNT2
/** PCNT2 Counter register size. */
#if defined(_SILICON_LABS_32B_SERIES_0)
#define PCNT2_CNT_SIZE (8) /* PCNT2 counter is 8 bits. */
#define PCNT2_CNT_SIZE (8) /**< PCNT2 counter is 8 bits. */
#else
#define PCNT2_CNT_SIZE (16) /* PCNT2 counter is 16 bits. */
#define PCNT2_CNT_SIZE (16) /**< PCNT2 counter is 16 bits. */
#endif
#endif
/* Define values that can be used in case some state/mode are not defined for some devices.*/
/** PCNT mode disable. */
#define PCNT_MODE_DISABLE 0xFF
#define PCNT_CNT_EVEN_NONE 0xFF
/** PCNT count event is none. */
#define PCNT_CNT_EVENT_NONE 0xFF
/*******************************************************************************
******************************** ENUMS ************************************
@ -151,13 +153,13 @@ typedef enum {
#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
pcntCntEventNone = _PCNT_CTRL_CNTEV_NONE
#else
pcntCntEventNone = PCNT_CNT_EVEN_NONE
pcntCntEventNone = PCNT_CNT_EVENT_NONE
#endif
} PCNT_CntEvent_TypeDef;
#endif
#if defined(_PCNT_INPUT_MASK)
/** PRS sources for @p s0PRS and @p s1PRS. */
#if defined(_PCNT_INPUT_MASK)
typedef enum {
pcntPRSCh0 = 0, /**< PRS channel 0. */
pcntPRSCh1 = 1, /**< PRS channel 1. */
@ -185,7 +187,43 @@ typedef enum {
pcntPRSCh10 = 10, /**< PRS channel 10. */
#endif
#if defined(PCNT_INPUT_S0PRSSEL_PRSCH11)
pcntPRSCh11 = 11 /**< PRS channel 11. */
pcntPRSCh11 = 11, /**< PRS channel 11. */
#endif
#if defined(PCNT_INPUT_S0PRSSEL_PRSCH12)
pcntPRSCh12 = 12, /**< PRS channel 12. */
#endif
#if defined(PCNT_INPUT_S0PRSSEL_PRSCH13)
pcntPRSCh13 = 13, /**< PRS channel 13. */
#endif
#if defined(PCNT_INPUT_S0PRSSEL_PRSCH14)
pcntPRSCh14 = 14, /**< PRS channel 14. */
#endif
#if defined(PCNT_INPUT_S0PRSSEL_PRSCH15)
pcntPRSCh15 = 15, /**< PRS channel 15. */
#endif
#if defined(PCNT_INPUT_S0PRSSEL_PRSCH16)
pcntPRSCh16 = 16, /**< PRS channel 16. */
#endif
#if defined(PCNT_INPUT_S0PRSSEL_PRSCH17)
pcntPRSCh17 = 17, /**< PRS channel 17. */
#endif
#if defined(PCNT_INPUT_S0PRSSEL_PRSCH18)
pcntPRSCh18 = 18, /**< PRS channel 18. */
#endif
#if defined(PCNT_INPUT_S0PRSSEL_PRSCH19)
pcntPRSCh19 = 19, /**< PRS channel 19. */
#endif
#if defined(PCNT_INPUT_S0PRSSEL_PRSCH20)
pcntPRSCh20 = 20, /**< PRS channel 20. */
#endif
#if defined(PCNT_INPUT_S0PRSSEL_PRSCH21)
pcntPRSCh21 = 21, /**< PRS channel 21. */
#endif
#if defined(PCNT_INPUT_S0PRSSEL_PRSCH22)
pcntPRSCh22 = 22, /**< PRS channel 22. */
#endif
#if defined(PCNT_INPUT_S0PRSSEL_PRSCH23)
pcntPRSCh23 = 23, /**< PRS channel 23. */
#endif
} PCNT_PRSSel_TypeDef;
#elif defined(_SILICON_LABS_32B_SERIES_2)
@ -274,47 +312,54 @@ typedef struct {
#endif
} PCNT_Init_TypeDef;
/** Default configuration for PCNT initialization structure. */
/** Default Debug. */
#if defined(_SILICON_LABS_32B_SERIES_2)
#define DEFAULT_DEBUG_HALT true,
#else
#define DEFAULT_DEBUG_HALT
#endif
#define DEFAULT_MODE pcntModeDisable, /* Disabled by default. */
/** Default Mode. */
#define DEFAULT_MODE pcntModeDisable, /**< Disabled by default. */
/** Default Hysteresis. */
#if defined(PCNT_CTRL_HYST) || defined(_SILICON_LABS_32B_SERIES_2)
#define DEFAULT_HYST false, /* Hysteresis disabled. */
#define DEFAULT_HYST false, /**< Hysteresis disabled. */
#else
#define DEFAULT_HYST
#endif
/** Default counter direction*/
#if defined(PCNT_CTRL_S1CDIR)
#define DEFAULT_CDIR true, /* Counter direction is given by CNTDIR. */
#define DEFAULT_CDIR true, /**< Counter direction is given by CNTDIR. */
#else
#define DEFAULT_CDIR
#endif
/** Default count event*/
#if defined(_PCNT_CTRL_CNTEV_SHIFT)
#define DEFAULT_CNTEV pcntCntEventUp, /* Regular counter counts up on upcount events. */
#define DEFAULT_CNTEV pcntCntEventUp, /**< Regular counter counts up on upcount events. */
#else
#define DEFAULT_CNTEV
#endif
/** Default auxiliary count event. */
#if defined(_PCNT_CTRL_AUXCNTEV_SHIFT)
#define DEFAULT_AUXCNTEV pcntCntEventNone, /* Auxiliary counter doesn't respond to events. */
#define DEFAULT_AUXCNTEV pcntCntEventNone, /**< Auxiliary counter doesn't respond to events. */
#else
#define DEFAULT_AUXCNTEV
#endif
/** Default selected PRS channel as S0IN and S1IN. */
#if defined(_PCNT_INPUT_MASK)
#define DEFAULT_PRS_CH pcntPRSCh0, /* PRS channel 0 selected as S0IN and as S1IN. */
#define DEFAULT_PRS_CH pcntPRSCh0, /**< PRS channel 0 selected as S0IN and as S1IN. */
#elif defined(_SILICON_LABS_32B_SERIES_2)
#define DEFAULT_PRS_CH 0u,
#else
#define DEFAULT_PRS_CH
#endif
/** Default configuration for PCNT initialization structure. */
#define PCNT_INIT_DEFAULT \
{ \
DEFAULT_MODE /* Default mode. */ \
@ -440,10 +485,10 @@ typedef struct {
/***************************************************************************//**
* @brief
* Get pulse counter value.
* Get the pulse counter value.
*
* @param[in] pcnt
* Pointer to PCNT peripheral register block.
* Pointer to the PCNT peripheral register block.
*
* @return
* Current pulse counter value.
@ -456,10 +501,10 @@ __STATIC_INLINE uint32_t PCNT_CounterGet(PCNT_TypeDef *pcnt)
#if defined(_PCNT_AUXCNT_MASK)
/***************************************************************************//**
* @brief
* Get auxiliary counter value.
* Get the auxiliary counter value.
*
* @param[in] pcnt
* Pointer to PCNT peripheral register block.
* Pointer to the PCNT peripheral register block.
*
* @return
* Current auxiliary counter value.
@ -475,10 +520,10 @@ void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top);
/***************************************************************************//**
* @brief
* Set counter value.
* Set a counter value.
*
* @details
* Pulse counter is disabled while changing counter value, and re-enabled
* Pulse counter is disabled while changing counter value and re-enabled
* (if originally enabled) when counter value has been set.
*
* @note
@ -489,7 +534,7 @@ void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top);
* operating in (or about to enable) #pcntModeOvsSingle mode.
*
* @param[in] pcnt
* Pointer to PCNT peripheral register block.
* Pointer to the PCNT peripheral register block.
*
* @param[in] count
* Value to set in counter register.
@ -525,7 +570,7 @@ void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config);
* Clear one or more pending PCNT interrupts.
*
* @param[in] pcnt
* Pointer to PCNT peripheral register block.
* Pointer to the PCNT peripheral register block.
*
* @param[in] flags
* Pending PCNT interrupt source to clear. Use a bitwise logic OR combination
@ -545,7 +590,7 @@ __STATIC_INLINE void PCNT_IntClear(PCNT_TypeDef *pcnt, uint32_t flags)
* Disable one or more PCNT interrupts.
*
* @param[in] pcnt
* Pointer to PCNT peripheral register block.
* Pointer to the PCNT peripheral register block.
*
* @param[in] flags
* PCNT interrupt sources to disable. Use a bitwise logic OR combination of
@ -570,7 +615,7 @@ __STATIC_INLINE void PCNT_IntDisable(PCNT_TypeDef *pcnt, uint32_t flags)
* PCNT_IntClear() prior to enabling the interrupt.
*
* @param[in] pcnt
* Pointer to PCNT peripheral register block.
* Pointer to the PCNT peripheral register block.
*
* @param[in] flags
* PCNT interrupt sources to enable. Use a bitwise logic OR combination of
@ -593,7 +638,7 @@ __STATIC_INLINE void PCNT_IntEnable(PCNT_TypeDef *pcnt, uint32_t flags)
* The event bits are not cleared by the use of this function.
*
* @param[in] pcnt
* Pointer to PCNT peripheral register block.
* Pointer to the PCNT peripheral register block.
*
* @return
* PCNT interrupt sources pending. A bitwise logic OR combination of valid
@ -615,7 +660,7 @@ __STATIC_INLINE uint32_t PCNT_IntGet(PCNT_TypeDef *pcnt)
* The event bits are not cleared by the use of this function.
*
* @param[in] pcnt
* Pointer to PCNT peripheral register block.
* Pointer to thePCNT peripheral register block.
*
* @return
* Pending and enabled PCNT interrupt sources.
@ -642,7 +687,7 @@ __STATIC_INLINE uint32_t PCNT_IntGetEnabled(PCNT_TypeDef *pcnt)
* Set one or more pending PCNT interrupts from SW.
*
* @param[in] pcnt
* Pointer to PCNT peripheral register block.
* Pointer to the PCNT peripheral register block.
*
* @param[in] flags
* PCNT interrupt sources to set to pending. Use a bitwise logic OR combination
@ -660,10 +705,10 @@ __STATIC_INLINE void PCNT_IntSet(PCNT_TypeDef *pcnt, uint32_t flags)
#if defined(_PCNT_LOCK_MASK)
/***************************************************************************//**
* @brief
* Locks PCNT registers.
* Lock PCNT registers.
*
* @param[in] pcnt
* Pointer to PCNT peripheral register block.
* Pointer to the PCNT peripheral register block.
*
* @note When PCNT registers are locked PCNT_CFG, PCNT_EN, PCNT_SWRST, PCNT_CMD,
* PCNT_CTRL, PCNT_OVSCTRL, PCNT_CNT, PCNT_TOP, and PCNT_TOPB registers
@ -678,10 +723,10 @@ __STATIC_INLINE void PCNT_Lock(PCNT_TypeDef *pcnt)
#if defined(_PCNT_LOCK_MASK)
/***************************************************************************//**
* @brief
* Unlocks PCNT registers.
* Unlock PCNT registers.
*
* @param[in] pcnt
* Pointer to PCNT peripheral register block.
* Pointer to thePCNT peripheral register block.
******************************************************************************/
__STATIC_INLINE void PCNT_Unlock(PCNT_TypeDef *pcnt)
{
@ -693,10 +738,10 @@ void PCNT_Reset(PCNT_TypeDef *pcnt);
/***************************************************************************//**
* @brief
* Get pulse counter top buffer value.
* Get the pulse counter top buffer value.
*
* @param[in] pcnt
* Pointer to PCNT peripheral register block.
* Pointer to the PCNT peripheral register block.
*
* @return
* Current pulse counter top buffer value.
@ -714,10 +759,10 @@ void PCNT_TopBufferSet(PCNT_TypeDef *pcnt, uint32_t val);
/***************************************************************************//**
* @brief
* Get pulse counter top value.
* Get the pulse counter top value.
*
* @param[in] pcnt
* Pointer to PCNT peripheral register block.
* Pointer to the PCNT peripheral register block.
*
* @return
* Current pulse counter top value.
@ -756,8 +801,8 @@ __STATIC_INLINE void PCNT_Sync(PCNT_TypeDef *pcnt, uint32_t mask)
/* Wait for any pending previous write operation to have been completed in
* low-frequency domain. */
while (pcnt->SYNCBUSY & mask)
;
while (pcnt->SYNCBUSY & mask) {
}
}
#if defined(_SILICON_LABS_32B_SERIES_2)
@ -765,12 +810,15 @@ __STATIC_INLINE void PCNT_Sync(PCNT_TypeDef *pcnt, uint32_t mask)
* @brief
* Start the main PCNT counter.
*
* @detail
* @details
* This function will send a start command to the PCNT peripheral. The PCNT
* peripheral will use some LF clock ticks before the command is executed.
* The @ref PCNT_Sync() function can be used to wait for the start command
* to be executed.
*
* @param[in] pcnt
* A pointer to the PCNT peripheral register block.
*
* @note
* This function requires the PCNT to be enabled.
******************************************************************************/
@ -784,12 +832,15 @@ __STATIC_INLINE void PCNT_StartMainCnt(PCNT_TypeDef *pcnt)
* @brief
* Stop the main PCNT counter.
*
* @detail
* @details
* This function will send a stop command to the PCNT peripheral. The PCNT
* peripheral will use some LF clock ticks before the command is executed.
* The @ref PCNT_Sync() function can be used to wait for the stop command
* to be executed.
*
* @param[in] pcnt
* A pointer to the PCNT peripheral register block.
*
* @note
* This function requires the PCNT to be enabled.
******************************************************************************/
@ -803,12 +854,15 @@ __STATIC_INLINE void PCNT_StopMainCnt(PCNT_TypeDef *pcnt)
* @brief
* Start the auxiliary PCNT counter.
*
* @detail
* @details
* This function will send a start command to the PCNT peripheral. The PCNT
* peripheral will use some LF clock ticks before the command is executed.
* The @ref PCNT_Sync() function can be used to wait for the start command
* to be executed.
*
* @param[in] pcnt
* A pointer to the PCNT peripheral register block.
*
* @note
* This function requires the PCNT to be enabled.
******************************************************************************/
@ -822,12 +876,15 @@ __STATIC_INLINE void PCNT_StartAuxCnt(PCNT_TypeDef *pcnt)
* @brief
* Stop the auxiliary PCNT counter.
*
* @detail
* @details
* This function will send a stop command to the PCNT peripheral. The PCNT
* peripheral will use some LF clock ticks before the command is executed.
* The @ref PCNT_Sync() function can be used to wait for the stop command
* to be executed.
*
* @param[in] pcnt
* A pointer to the PCNT peripheral register block.
*
* @note
* This function requires the PCNT to be enabled.
******************************************************************************/

16
gecko/emlib/inc/em_pdm.h
View File

@ -49,9 +49,9 @@ extern "C" {
*
* @details
* PDM API functions provide full support for the PDM peripheral.
* The PDM peripheral accept PDM bitstreams and produce PCM encoded output.
* The PDM peripheral accepts PDM bitstreams and produces PCM encoded output.
*
* <b> Example PDM usage when interfacing to two PDM microphones: </b>
* <b> The following is an example PDM usage when interfacing to two PDM microphones: </b>
*
* Configure clocks and GPIO pins:
* @code
@ -59,7 +59,7 @@ extern "C" {
CMU_DPLLInit_TypeDef pllInit = CMU_DPLL_LFXO_TO_40MHZ;
CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
// Lock PLL to 1,411,209 Hz to achive 44,100 kHz PCM sampling rate
// Lock PLL to 1,411,209 Hz to achieve 44,100 kHz PCM sampling rate
// when using 32x PDM oversampling
pllInit.frequency = 1411209;
pllInit.m = 14;
@ -249,7 +249,7 @@ void PDM_Reset(PDM_TypeDef *pdm);
/***************************************************************************//**
* @brief
* Clear PDM filter.
* Clear the PDM filter.
*
* @param[in] pdm
* A pointer to the PDM peripheral register block.
@ -384,7 +384,7 @@ __STATIC_INLINE uint32_t PDM_IntGetEnabled(PDM_TypeDef *pdm)
/***************************************************************************//**
* @brief
* Set one or more pending PDM interrupts
* Set one or more pending PDM interrupts.
*
* @param[in] pdm
* A pointer to the PDM peripheral register block.
@ -428,7 +428,7 @@ __STATIC_INLINE uint32_t PDM_Rx(PDM_TypeDef *pdm)
/***************************************************************************//**
* @brief
* Start PDM operation (start the PDM filter).
* Start the PDM operation (start the PDM filter).
*
* @param[in] pdm
* A pointer to the PDM peripheral register block.
@ -443,7 +443,7 @@ __STATIC_INLINE void PDM_Start(PDM_TypeDef *pdm)
/***************************************************************************//**
* @brief
* Get PDM STATUS register.
* Get the PDM STATUS register.
*
* @param[in] pdm
* A pointer to the PDM peripheral register block.
@ -458,7 +458,7 @@ __STATIC_INLINE uint32_t PDM_StatusGet(PDM_TypeDef *pdm)
/***************************************************************************//**
* @brief
* Stop PDM operation (stop the PDM filter).
* Stop the PDM operation (stop the PDM filter).
*
* @param[in] pdm
* A pointer to the PDM peripheral register block.

4
gecko/emlib/inc/em_qspi.h
View File

@ -184,7 +184,7 @@ typedef struct {
bool enable;
/**
* Master mode baude rate divisor. Values can be even numbers in the range
* Master mode baud rate divisor. Values can be even numbers in the range
* [2-32] inclusive. */
uint8_t divisor;
} QSPI_Init_TypeDef;
@ -260,7 +260,7 @@ __STATIC_INLINE uint16_t QSPI_GetReadLevel(QSPI_TypeDef * qspi)
* Pointer to QSPI peripheral register block.
*
* @param[in] enable
* true to enable quad spi, false to disable quad spi.
* true to enable Quad SPI, false to disable Quad SPI.
******************************************************************************/
__STATIC_INLINE void QSPI_Enable(QSPI_TypeDef * qspi, bool enable)
{

14
gecko/emlib/inc/em_ramfunc.h
View File

@ -45,7 +45,7 @@ extern "C" {
* @{
@note
Other cross-compiler support macros are implemented in @ref common.
Other cross-compiler support macros are implemented in [COMMON](../../common/api/group-common).
@note
Functions executing from RAM should not be declared as static.
@ -73,8 +73,8 @@ extern "C" {
void MyPrint(const char* string);
@endverbatim
Issues have been observed with armgcc when there is no declarator. It is
recommended to have a declarator also for internal functions, but move the
Issues have been observed with ARM GCC when there is no declarator. It is
recommended to have a declarator also for internal functions but move the
declarator to the .c file.
In your .c file:
@ -137,9 +137,15 @@ extern "C" {
#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR
#define SL_RAMFUNC_DEFINITION_END
#elif defined(__GNUC__) && defined(CONFIG_SOC_FAMILY_EXX32)
/* Zephyr environment */
#define SL_RAMFUNC_DECLARATOR __attribute__ ((section(".ramfunc")))
#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR
#define SL_RAMFUNC_DEFINITION_END
#elif defined(__GNUC__)
/* Simplicity Studio, Atollic and Vanilla armgcc */
#define SL_RAMFUNC_DECLARATOR __attribute__ ((section(".ramfunc")))
#define SL_RAMFUNC_DECLARATOR __attribute__ ((section(".ram")))
#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR
#define SL_RAMFUNC_DEFINITION_END

69
gecko/emlib/inc/em_se.h
View File

@ -30,10 +30,19 @@
#ifndef EM_SE_H
#define EM_SE_H
#include "em_device.h"
#include "em_common.h"
#if defined(__linux__)
#if defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT)
#define SLI_EM_SE_HOST
#else
#include "em_device.h"
#endif // __linux__
#include "sl_common.h"
#if defined(SLI_EM_SE_HOST) || defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT)
#include <stdint.h>
#include <stdbool.h>
@ -61,7 +70,7 @@ extern "C" {
* @note The high-level SE API has been moved to the SE manager, and the
* implementation in em_se should not be used.
*
* @note Using the SE's mailbox is not thread-safe in emlib, and accessing the
* @note Using the SE's mailbox is not thread-safe in EMLIB, and accessing the
* SE's mailbox both in regular and IRQ context is not safe. SE operations
* should be performed using the SE manager if possible.
*
@ -166,11 +175,14 @@ void SE_addDataOutput(SE_Command_t *command,
void SE_addParameter(SE_Command_t *command, uint32_t parameter);
#if !defined(SLI_EM_SE_HOST)
void SE_executeCommand(SE_Command_t *command);
#endif // #if !defined(SLI_EM_SE_HOST)
#if defined(CRYPTOACC_PRESENT)
SE_Response_t SE_getVersion(uint32_t *version);
SE_Response_t SE_getConfigStatusBits(uint32_t *cfgStatus);
SE_Response_t SE_getOTPVersion(uint32_t *otpVersion);
SE_Response_t SE_ackCommand(SE_Command_t *command);
#endif // #if defined(CRYPTOACC_PRESENT)
@ -184,9 +196,11 @@ uint32_t SE_readExecutedCommand(void);
SE_Response_t SE_readCommandResponse(void);
#endif // #if defined(SEMAILBOX_PRESENT)
#if !defined(SLI_EM_SE_HOST)
__STATIC_INLINE void SE_waitCommandCompletion(void);
__STATIC_INLINE void SE_disableInterrupt(uint32_t flags);
__STATIC_INLINE void SE_enableInterrupt(uint32_t flags);
#endif // #if !defined(SLI_EM_SE_HOST)
#if defined(SEMAILBOX_PRESENT)
/***************************************************************************//**
@ -202,22 +216,7 @@ __STATIC_INLINE bool SE_isCommandCompleted(void)
{
return (bool)(SEMAILBOX_HOST->RX_STATUS & SEMAILBOX_RX_STATUS_RXINT);
}
#endif
/***************************************************************************//**
* @brief
* Wait for completion of the current command.
*
* @details
* This function "busy"-waits until the execution of the ongoing instruction
* has completed.
******************************************************************************/
__STATIC_INLINE void SE_waitCommandCompletion(void)
{
/* Wait for completion */
while (!SE_isCommandCompleted()) {
}
}
#endif // #if defined(SEMAILBOX_PRESENT)
#if defined(SEMAILBOX_PRESENT)
/***************************************************************************//**
@ -243,6 +242,22 @@ __STATIC_INLINE SE_Response_t SE_readCommandResponse(void)
}
#endif // #if defined(SEMAILBOX_PRESENT)
#if !defined(SLI_EM_SE_HOST)
/***************************************************************************//**
* @brief
* Wait for completion of the current command.
*
* @details
* This function "busy"-waits until the execution of the ongoing instruction
* has completed.
******************************************************************************/
__STATIC_INLINE void SE_waitCommandCompletion(void)
{
/* Wait for completion */
while (!SE_isCommandCompleted()) {
}
}
/***************************************************************************//**
* @brief
* Disable one or more SE interrupts.
@ -279,6 +294,8 @@ __STATIC_INLINE void SE_enableInterrupt(uint32_t flags)
#endif
}
#endif // #if !defined(SLI_EM_SE_HOST)
/*******************************************************************************
***************************** DEPRECATED *********************************
******************************************************************************/
@ -289,7 +306,7 @@ __STATIC_INLINE void SE_enableInterrupt(uint32_t flags)
*
* @deprecated
* The following functions have been deprecated and will be removed in a
* future version of emlib. All high-level functionality have been moved to
* future version of EMLIB. All high-level functionality have been moved to
* the SE manager.
*
* @{
@ -299,6 +316,7 @@ __STATIC_INLINE void SE_enableInterrupt(uint32_t flags)
****************************** DEFINES ***********************************
******************************************************************************/
#if !defined(SLI_EM_SE_HOST)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
#if defined(SEMAILBOX_PRESENT)
/* Command words for the Security Engine. */
@ -465,7 +483,7 @@ __STATIC_INLINE void SE_enableInterrupt(uint32_t flags)
#define SE_COMMAND_OPTION_READ 0x00000000UL
#define SE_COMMAND_OPTION_WRITE 0x00000100UL
/** Magic paramater for deleting user data */
/** Magic parameter for deleting user data */
#define SE_COMMAND_OPTION_ERASE_UD 0xDE1E7EADUL
#endif /* SEMAILBOX_PRESENT */
@ -572,12 +590,10 @@ SE_Response_t SE_initPubkey(uint32_t key_type,
bool signature)
SL_DEPRECATED_API_SDK_3_0;
SE_Response_t SE_initOTP(SE_OTPInit_t *otp_init);
SE_Response_t SE_initPubkey(uint32_t key_type,
void* pubkey,
uint32_t numBytes,
bool signature);
bool signature) SL_DEPRECATED_API_SDK_4_4;
#if defined(SEMAILBOX_PRESENT)
@ -593,7 +609,7 @@ SE_Response_t SE_eraseUserData(void) SL_DEPRECATED_API_SDK_3_0;
SE_Response_t SE_readPubkey(uint32_t key_type,
void* pubkey,
uint32_t numBytes,
bool signature);
bool signature) SL_DEPRECATED_API_SDK_4_4;
// Debug commands
SE_Response_t SE_debugLockStatus(SE_DebugStatus_t *status) SL_DEPRECATED_API_SDK_3_0;
@ -608,6 +624,7 @@ SE_Response_t SE_getStatus(SE_Status_t *output) SL_DEPRECATED_API_SDK_3_0;
SE_Response_t SE_serialNumber(void *serial) SL_DEPRECATED_API_SDK_3_0;
#endif // #if defined(SEMAILBOX_PRESENT)
#endif // #if !defined(SLI_EM_SE_HOST)
/** @} (end addtogroup se_deprecated) */

8
gecko/emlib/inc/em_vcmp.h
View File

@ -118,7 +118,7 @@ typedef struct {
false, /** Rising edge sense not enabled. */ \
vcmpWarmTime4Cycles, /** 4 clock cycles warm-up time. */ \
vcmpHystNone, /** No hysteresis. */ \
0, /** 0 in digital ouput when inactive. */ \
0, /** 0 in digital output when inactive. */ \
true, /** Do not use low power reference. */ \
39, /** Trigger level just below 3V. */ \
true, /** Enable after initialization. */ \
@ -170,7 +170,7 @@ __STATIC_INLINE uint32_t VCMP_VoltageToLevel(float v)
/***************************************************************************//**
* @brief
* Check if VDD is lower than trigger level.
* Check whether VDD is lower than the trigger level.
*
* @return
* True if Voltage Comparator indicated VDD < trigger level, else
@ -187,7 +187,7 @@ __STATIC_INLINE bool VCMP_VDDLower(void)
/***************************************************************************//**
* @brief
* Check if VDD is higher than trigger level.
* Check whether VDD is higher than the trigger level.
*
* @return
* True if Voltage Comparator indicated VDD > trigger level, else
@ -204,7 +204,7 @@ __STATIC_INLINE bool VCMP_VDDHigher(void)
/***************************************************************************//**
* @brief
* Check if VCMP output is ready.
* Check whether the VCMP output is ready.
*
* @return
* True if VCMP output is ready.

21
gecko/emlib/inc/em_version.h
View File

@ -45,33 +45,16 @@ extern "C" {
* @{
******************************************************************************/
/* *INDENT-OFF* */
/** @deprecated Version number of EMLIB peripheral API. */
#define _EMLIB_VERSION 6.0.0
/* *INDENT-ON* */
/** @deprecated Major version of EMLIB. This is the 32-bit MCU SDK version.
A new version system for EMLIB will be provided in a later release. */
#define _EMLIB_VERSION_MAJOR 6
/** @deprecated Minor version of EMLIB. This is the 32-bit MCU SDK version.
A new version system for EMLIB will be provided in a later release. */
#define _EMLIB_VERSION_MINOR 0
/** @deprecated Patch revision of EMLIB. This is the 32-bit MCU SDK version.
A new version system for EMLIB will be provided in a later release. */
#define _EMLIB_VERSION_PATCH 0
/* *INDENT-OFF* */
/** Version number of targeted CMSIS package. */
#define _CMSIS_VERSION 5.3.0
#define _CMSIS_VERSION 5.8.0
/* *INDENT-ON* */
/** Major version of CMSIS. */
#define _CMSIS_VERSION_MAJOR 5
/** Minor version of CMSIS. */
#define _CMSIS_VERSION_MINOR 3
#define _CMSIS_VERSION_MINOR 8
/** Patch revision of CMSIS. */
#define _CMSIS_VERSION_PATCH 0

90
gecko/emlib/inc/sli_em_cmu.h
View File

@ -182,6 +182,10 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void);
#define CMU_TIMER6_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL
#define CMU_TIMER7_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL
#endif /* TIMER_COUNT > 7 */
#if TIMER_COUNT > 9
#define CMU_TIMER8_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL
#define CMU_TIMER9_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL
#endif /* TIMER_COUNT > 9 */
#if defined(KEYSCAN_PRESENT)
#define CMU_KEYSCAN_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL
#endif /* KEYSCAN_PRESENT*/
@ -204,6 +208,10 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void);
#define CMU_TIMER6_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO
#define CMU_TIMER7_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO
#endif /* TIMER_COUNT > 7 */
#if TIMER_COUNT > 9
#define CMU_TIMER8_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO
#define CMU_TIMER9_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO
#endif /* TIMER_COUNT > 9 */
#if defined(KEYSCAN_PRESENT)
#define CMU_KEYSCAN_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO
#endif /* KEYSCAN_PRESENT*/
@ -227,6 +235,10 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void);
#define CMU_TIMER6_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23
#define CMU_TIMER7_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23
#endif /* TIMER_COUNT > 7 */
#if TIMER_COUNT > 9
#define CMU_TIMER8_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23
#define CMU_TIMER9_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23
#endif /* TIMER_COUNT > 9 */
#if defined(KEYSCAN_PRESENT)
#define CMU_KEYSCAN_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23
#endif /* KEYSCAN_PRESENT*/
@ -250,10 +262,20 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void);
#define CMU_TIMER6_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO
#define CMU_TIMER7_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO
#endif /* TIMER_COUNT > 7 */
#if TIMER_COUNT > 9
#define CMU_TIMER8_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO
#define CMU_TIMER9_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO
#endif /* TIMER_COUNT > 9 */
#if defined(KEYSCAN_PRESENT)
#define CMU_KEYSCAN_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO
#endif /* KEYSCAN_PRESENT*/
#define CMU_EM01GRPACLK_SELECT_DISABLED \
do { \
CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \
| CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED; \
} while (0)
#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT)
#define CMU_EM01GRPACLK_SELECT_HFRCODPLLRT \
do { \
@ -273,6 +295,10 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void);
#define CMU_TIMER6_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT
#define CMU_TIMER7_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT
#endif /* TIMER_COUNT > 7 */
#if TIMER_COUNT > 9
#define CMU_TIMER8_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT
#define CMU_TIMER9_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT
#endif /* TIMER_COUNT > 9 */
#if defined(KEYSCAN_PRESENT)
#define CMU_KEYSCAN_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT
#endif /* KEYSCAN_PRESENT*/
@ -297,6 +323,10 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void);
#define CMU_TIMER6_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT
#define CMU_TIMER7_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT
#endif /* TIMER_COUNT > 7 */
#if TIMER_COUNT > 9
#define CMU_TIMER8_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT
#define CMU_TIMER9_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT
#endif /* TIMER_COUNT > 9 */
#if defined(KEYSCAN_PRESENT)
#define CMU_KEYSCAN_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT
#endif /* KEYSCAN_PRESENT*/
@ -368,6 +398,12 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void);
#define CMU_LESENSECLK_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO
#endif /* LESENSE_PRESENT */
#define CMU_EM23GRPACLK_SELECT_DISABLED \
do { \
CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \
| CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED; \
} while (0)
#define CMU_EM4GRPACLK_SELECT_LFRCO \
do { \
CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \
@ -402,6 +438,12 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void);
#define CMU_BURTC_SELECT_ULFRCO CMU_EM4GRPACLK_SELECT_ULFRCO
#define CMU_EM4GRPACLK_SELECT_DISABLED \
do { \
CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \
| CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED; \
} while (0)
#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK)
#define CMU_EM01GRPBCLK_SELECT_HFRCODPLL \
do { \
@ -450,6 +492,13 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void);
} while (0)
#define CMU_PDMREF_SELECT_HFXORT CMU_EM01GRPBCLK_SELECT_HFXORT
#define CMU_EM01GRPBCLK_SELECT_DISABLED \
do { \
CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \
| CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED; \
} while (0)
#endif /* defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) */
#define CMU_WDOG0_SELECT_LFRCO \
@ -494,6 +543,13 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void);
#define CMU_WDOG0CLK_SELECT_HCLKDIV1024 CMU_WDOG0_SELECT_HCLKDIV1024
#define CMU_WDOG0_SELECT_DISABLED \
do { \
CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \
| CMU_WDOG0CLKCTRL_CLKSEL_DISABLED; \
} while (0)
#define CMU_WDOG0CLK_SELECT_DISABLED CMU_WDOG0_SELECT_DISABLED
#if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK)
#define CMU_WDOG1_SELECT_LFRCO \
do { \
@ -536,6 +592,13 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void);
} while (0)
#define CMU_WDOG1CLK_SELECT_HCLKDIV1024 CMU_WDOG1_SELECT_HCLKDIV1024
#define CMU_WDOG1_SELECT_DISABLED \
do { \
CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \
| CMU_WDOG1CLKCTRL_CLKSEL_DISABLED; \
} while (0)
#define CMU_WDOG1CLK_SELECT_DISABLED CMU_WDOG1_SELECT_DISABLED
#endif /* defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) */
#define CMU_DPLLREFCLK_SELECT_HFXO \
@ -564,6 +627,7 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void);
#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \
|| defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \
|| defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \
|| defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \
|| defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \
&& defined(CoreDebug_DEMCR_TRCENA_Msk)
@ -598,6 +662,7 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void);
#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \
|| defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \
|| defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \
|| defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \
|| defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)
#define CMU_TRACECLK_SELECT_SYSCLK \
@ -645,6 +710,13 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void);
} while (0)
#define CMU_EUART0CLK_SELECT_EM23GRPACLK CMU_EUART0_SELECT_EM23GRPACLK
#define CMU_EUART0_SELECT_DISABLED \
do { \
CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \
| _CMU_EUART0CLKCTRL_CLKSEL_DISABLED; \
} while (0)
#define CMU_EUART0CLK_SELECT_DISABLED CMU_EUART0_SELECT_DISABLED
#endif /* _CMU_EUART0CLKCTRL_CLKSEL_MASK */
#if defined(EUSART_PRESENT)
@ -727,6 +799,16 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void);
#define CMU_EUSART0CLK_SELECT_LFXO CMU_EUSART0_SELECT_LFXO
#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_LFXO */
#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED)
#define CMU_EUSART0_SELECT_DISABLED \
do { \
CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \
| _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED; \
} while (0)
#define CMU_EUSART0CLK_SELECT_DISABLED CMU_EUSART0_SELECT_DISABLED
#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED */
#endif /* EUSART_PRESENT */
#if defined(_CMU_EM01GRPCCLKCTRL_MASK)
@ -920,6 +1002,14 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void);
} while (0)
#define CMU_SYSRTCCLK_SELECT_ULFRCO CMU_SYSRTC_SELECT_ULFRCO
#define CMU_SYSRTC_SELECT_DISABLED \
do { \
CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \
| CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED; \
} while (0)
#define CMU_SYSRTCCLK_SELECT_DISABLED CMU_SYSRTC_SELECT_DISABLED
#endif /* SYSRTC_PRESENT */
#if defined(LCD_PRESENT)

21
gecko/emlib/src/em_cmu_fpga.c
View File

@ -66,6 +66,14 @@ CMU_Select_TypeDef cmu_eusart2_clk_source = cmuSelect_HFRCO;
CMU_Select_TypeDef cmu_eusart3_clk_source = cmuSelect_HFRCO;
CMU_Select_TypeDef cmu_eusart4_clk_source = cmuSelect_HFRCO;
void sli_em_cmu_SYSCLKInitPreClockSelect(void)
{
}
void sli_em_cmu_SYSCLKInitPostClockSelect(void)
{
}
uint32_t Get_Fpga_Core_freq(void)
{
if ((SYSCFG->FPGAIPOTHW & SYSCFG_FPGAIPOTHW_FPGA_FPGA) != 0U) {
@ -209,6 +217,9 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
case cmuClock_LESENSE:
return LFRCO_CLK_FREQ;
case cmuClock_BURTC:
#if defined(ETAMPDET_PRESENT)
case cmuClock_ETAMPDET:
#endif
#if defined(WDOG1)
case cmuClock_WDOG1:
#endif
@ -386,6 +397,16 @@ void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit)
(void) hfxoInit;
}
void CMU_HFXOCTuneSet(uint32_t ctune)
{
(void) ctune; /* Unused parameter */
}
uint32_t CMU_HFXOCTuneGet(void)
{
return 0;
}
void CMU_HFXOCTuneDeltaSet(int32_t delta)
{
(void) delta; /* Unused parameter */

98
gecko/emlib/src/em_eusart.c
View File

@ -159,7 +159,10 @@ void EUSART_UartInitLf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *in
(clock_source == cmuSelect_ULFRCO)
|| (clock_source == cmuSelect_LFXO)
|| (clock_source == cmuSelect_LFRCO)
|| (clock_source == cmuSelect_EM23GRPACLK) /* ULFRCO, LFXO, or LFRCO */
|| (clock_source == cmuSelect_EM23GRPACLK)
#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK)
|| (clock_source == cmuSelect_EM01GRPCCLK) /* ULFRCO, LFXO, LFRCO, EM23GRPACLK or EM01GRPCCLK */
#endif
);
}
#endif
@ -228,7 +231,6 @@ void EUSART_SpiInit(EUSART_TypeDef *eusart, EUSART_SpiInit_TypeDef const *init)
}
} else {
EFM_ASSERT(init->bitRate <= 10000000);
if (init->advancedSettings && init->advancedSettings->forceLoad) {
// If baud-rate is more than 5MHz, a value of 4 is recommended, any values
// smaller than that can be tried out but avoid using 0. If baud-rate is less than 5MHz,
@ -300,7 +302,8 @@ void EUSART_Reset(EUSART_TypeDef *eusart)
#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \
|| defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \
|| defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5)
|| defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \
|| defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)
// Manual toggling tx_sclk_mst to synchronize handshake
// when switching from SPI master to other modes
// so module is disabling correctly.
@ -386,13 +389,38 @@ void EUSART_Enable(EUSART_TypeDef *eusart, EUSART_Enable_TypeDef enable)
/***************************************************************************//**
* Receives one 8 bit frame, (or part of 9 bit frame).
*
* @note (1) Handles the case where the RX Fifo Watermark has been set to N frames,
* and when N is greater than one. Attempt to read a frame from the RX Fifo.
* If the read is unsuccessful (i.e. no frames in the RX fifo), the RXFU
* interrupt flag is set. If the flag is set, wait to read again until the RXFL
* status flag is set, indicating there are N frames in the RX Fifo, where N
* is equal to the RX watermark level. Once there are N frames in the Fifo,
* read and return one frame. For consecutive N-1 reads there will be data available
* in the Fifo. Therefore, the RXUF interrupt will not be triggered eliminating
* delays between reads and sending N data frames in "bursts".
******************************************************************************/
uint8_t EUSART_Rx(EUSART_TypeDef *eusart)
{
while (!(eusart->STATUS & EUSART_STATUS_RXFL)) {
} // Wait for incoming data.
// If RX watermark has not been configured.
if ((eusart->CFG1 & _EUSART_CFG1_RXFIW_MASK) == EUSART_CFG1_RXFIW_DEFAULT) {
while (!(eusart->STATUS & EUSART_STATUS_RXFL)) {
} // Wait for incoming data.
return (uint8_t)eusart->RXDATA;
}
return (uint8_t)eusart->RXDATA;
// See Note #1.
uint8_t rx_data = eusart->RXDATA;
// If there is underflow i.e Rx data read was unsuccessful
if (eusart->IF & EUSART_IF_RXUF) {
// Wait until data becomes available in Rx fifo
while (!(eusart->STATUS & EUSART_STATUS_RXFL)) {
}
// Read Rx data again once data is available in the fifo
rx_data = eusart->RXDATA;
}
return rx_data;
}
/***************************************************************************//**
@ -902,17 +930,25 @@ static void EUSART_AsyncInitCommon(EUSART_TypeDef *eusart,
}
if (init->advancedSettings) {
eusart->CFG0 |= (uint32_t)init->advancedSettings->dmaHaltOnError << _EUSART_CFG0_ERRSDMA_SHIFT;
eusart->CFG0 |= (uint32_t)init->advancedSettings->txAutoTristate << _EUSART_CFG0_AUTOTRI_SHIFT;
eusart->CFG0 |= (uint32_t)init->advancedSettings->invertIO & (_EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK);
eusart->CFG0 |= (uint32_t)init->advancedSettings->collisionDetectEnable << _EUSART_CFG0_CCEN_SHIFT;
eusart->CFG0 |= (uint32_t)init->advancedSettings->multiProcessorEnable << _EUSART_CFG0_MPM_SHIFT;
eusart->CFG0 |= (uint32_t)init->advancedSettings->multiProcessorAddressBitHigh << _EUSART_CFG0_MPAB_SHIFT;
eusart->CFG0 |= (uint32_t)init->advancedSettings->msbFirst << _EUSART_CFG0_MSBF_SHIFT;
eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_ERRSDMA_MASK | _EUSART_CFG0_AUTOTRI_MASK
| _EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK
| _EUSART_CFG0_CCEN_MASK | _EUSART_CFG0_MPM_MASK
| _EUSART_CFG0_MPAB_MASK | _EUSART_CFG0_MSBF_MASK))
| (uint32_t)(init->advancedSettings->dmaHaltOnError << _EUSART_CFG0_ERRSDMA_SHIFT)
| (uint32_t)(init->advancedSettings->txAutoTristate << _EUSART_CFG0_AUTOTRI_SHIFT)
| (uint32_t)(init->advancedSettings->invertIO & (_EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK))
| (uint32_t)(init->advancedSettings->collisionDetectEnable << _EUSART_CFG0_CCEN_SHIFT)
| (uint32_t)(init->advancedSettings->multiProcessorEnable << _EUSART_CFG0_MPM_SHIFT)
| (uint32_t)(init->advancedSettings->multiProcessorAddressBitHigh << _EUSART_CFG0_MPAB_SHIFT)
| (uint32_t)(init->advancedSettings->msbFirst << _EUSART_CFG0_MSBF_SHIFT);
// Configure global configuration register 1.
eusart->CFG1 = (uint32_t)init->advancedSettings->dmaWakeUpOnRx << _EUSART_CFG1_RXDMAWU_SHIFT
| (uint32_t)init->advancedSettings->dmaWakeUpOnTx << _EUSART_CFG1_TXDMAWU_SHIFT;
eusart->CFG1 = (eusart->CFG1 & ~(_EUSART_CFG1_RXFIW_MASK | _EUSART_CFG1_TXFIW_MASK
| _EUSART_CFG1_RXDMAWU_MASK | _EUSART_CFG1_TXDMAWU_MASK))
| (uint32_t)(init->advancedSettings->RxFifoWatermark)
| (uint32_t)(init->advancedSettings->TxFifoWatermark)
| (uint32_t)(init->advancedSettings->dmaWakeUpOnRx << _EUSART_CFG1_RXDMAWU_SHIFT)
| (uint32_t)(init->advancedSettings->dmaWakeUpOnTx << _EUSART_CFG1_TXDMAWU_SHIFT);
if (init->advancedSettings->hwFlowControl == eusartHwFlowControlCts
|| init->advancedSettings->hwFlowControl == eusartHwFlowControlCtsAndRts) {
@ -949,8 +985,8 @@ static void EUSART_AsyncInitCommon(EUSART_TypeDef *eusart,
}
#if defined(EUSART1)
if (eusart == EUSART1) {
PRS->CONSUMER_EUSART1_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART1_RX_MASK);
}
PRS->CONSUMER_EUSART1_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART1_RX_MASK);
#endif
#if defined(EUSART2)
if (eusart == EUSART2) {
@ -969,6 +1005,10 @@ static void EUSART_AsyncInitCommon(EUSART_TypeDef *eusart,
#endif
#endif
}
// Configure global configuration timing register.
eusart->TIMINGCFG = (eusart->TIMINGCFG & ~_EUSART_TIMINGCFG_TXDELAY_MASK)
| (uint32_t)(init->advancedSettings->autoTxDelay);
}
if (irdaInit) {
@ -994,18 +1034,22 @@ static void EUSART_AsyncInitCommon(EUSART_TypeDef *eusart,
eusart->DALICFG_SET = EUSART_DALICFG_DALIRXENDT;
}
// keep track of the number of 16-bits packet to send
if (daliInit->TXdatabits <= eusartDaliTxDataBits16) {
dali_tx_nb_packets[EUSART_NUM(eusart)] = 1;
} else {
dali_tx_nb_packets[EUSART_NUM(eusart)] = 2;
}
if (EUSART_REF_VALID(eusart)) {
uint8_t index = EUSART_NUM(eusart);
// keep track of the number of 16-bits packet to receive
if (daliInit->RXdatabits <= eusartDaliRxDataBits16) {
dali_rx_nb_packets[EUSART_NUM(eusart)] = 1;
} else {
dali_rx_nb_packets[EUSART_NUM(eusart)] = 2;
// keep track of the number of 16-bits packet to send
if (daliInit->TXdatabits <= eusartDaliTxDataBits16) {
dali_tx_nb_packets[index] = 1;
} else {
dali_tx_nb_packets[index] = 2;
}
// keep track of the number of 16-bits packet to receive
if (daliInit->RXdatabits <= eusartDaliRxDataBits16) {
dali_rx_nb_packets[index] = 1;
} else {
dali_rx_nb_packets[index] = 2;
}
}
// Configure the numbers of bits per TX and RX frames

87
gecko/emlib/src/em_gpio.c
View File

@ -199,7 +199,7 @@ void GPIO_ExtIntConfig(GPIO_Port_TypeDef port,
BUS_RegMaskedWrite(&GPIO->EXTIPSELL,
_GPIO_EXTIPSELL_EXTIPSEL0_MASK
<< (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo),
port << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo));
(uint32_t)port << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo));
} else {
#if defined(_GPIO_EXTIPSELH_MASK)
tmp = intNo - 8;
@ -207,12 +207,12 @@ void GPIO_ExtIntConfig(GPIO_Port_TypeDef port,
BUS_RegMaskedWrite(&GPIO->EXTIPSELH,
_GPIO_EXTIPSELH_EXTIPSEL0_MASK
<< (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp),
port << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp));
(uint32_t)port << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp));
#elif defined(_GPIO_EXTIPSELH_EXTIPSEL8_MASK)
BUS_RegMaskedWrite(&GPIO->EXTIPSELH,
_GPIO_EXTIPSELH_EXTIPSEL8_MASK
<< (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp),
port << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp));
(uint32_t)port << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp));
#else
#error Invalid GPIO_EXTIPINSELH bit fields
#endif
@ -227,21 +227,21 @@ void GPIO_ExtIntConfig(GPIO_Port_TypeDef port,
BUS_RegMaskedWrite(&GPIO->EXTIPINSELL,
_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK
<< (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo),
((pin % 4) & _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK)
(uint32_t)((pin % 4) & _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK)
<< (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo));
} else {
#if defined (_GPIO_EXTIPINSELH_EXTIPINSEL8_MASK)
BUS_RegMaskedWrite(&GPIO->EXTIPINSELH,
_GPIO_EXTIPINSELH_EXTIPINSEL8_MASK
<< (_GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT * tmp),
((pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK)
(uint32_t)((pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK)
<< (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp));
#endif
#if defined (_GPIO_EXTIPINSELH_EXTIPINSEL0_MASK)
BUS_RegMaskedWrite(&GPIO->EXTIPINSELH,
_GPIO_EXTIPINSELH_EXTIPINSEL0_MASK
<< (_GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT * tmp),
((pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK)
(uint32_t)((pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK)
<< (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp));
#endif
}
@ -260,6 +260,73 @@ void GPIO_ExtIntConfig(GPIO_Port_TypeDef port,
BUS_RegBitWrite(&(GPIO->IEN), intNo, enable);
}
#if _SILICON_LABS_32B_SERIES > 0
/***************************************************************************//**
* @brief
* Configure EM4WU pins as external level-sensitive interrupts.
*
* @details
* It is recommended to disable interrupts before configuring the GPIO pin interrupt.
* See @ref GPIO_IntDisable() for more information.
*
* The GPIO interrupt handler must be in place before enabling the
* interrupt.
*
* Notice that any pending interrupt for the selected interrupt is cleared
* by this function.
*
* @note
* The selected port/pin must be mapped to an existant EM4WU interrupt.
* Each EM4WU signal is connected to a fixed pin.
* Refer to the Alternate Function Table in the device Datasheet for the
* location of each EM4WU signal. For example, on xG22 device, the interrupt
* of EM4WU6 is fixed to pin PC00.
*
* @param[in] port
* The port to associate with the @p pin.
*
* @param[in] pin
* The pin number on the port.
*
* @param[in] intNo
* The EM4WU interrupt number to trigger.
*
* @param[in] polarity
* true = Active high level-sensitive interrupt.
* false = Active low level-sensitive interrupt.
*
* @param[in] enable
* Set to true if the interrupt will be enabled after the configuration is complete.
* False to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable().
******************************************************************************/
void GPIO_EM4WUExtIntConfig(GPIO_Port_TypeDef port,
unsigned int pin,
uint32_t intNo,
bool polarity,
bool enable)
{
EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
// GPIO pin mode set.
GPIO_PinModeSet(port, pin, gpioModeInputPullFilter, (unsigned int)!polarity);
// Enable EM4WU function and set polarity
uint32_t polarityMask = (uint32_t)polarity << (intNo + _GPIO_EM4WUEN_EM4WUEN_SHIFT);
uint32_t pinmask = 1UL << (intNo + _GPIO_EM4WUEN_EM4WUEN_SHIFT);
GPIO_EM4EnablePinWakeup(pinmask, polarityMask);
// Enable EM4WU interrupt
#if defined(_SILICON_LABS_32B_SERIES_1)
BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WU_SHIFT, enable);
#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WUIEN_SHIFT, enable);
#else
BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WUIEN0_SHIFT, enable);
#endif
}
#endif
/***************************************************************************//**
* @brief
* Set the mode for a GPIO pin.
@ -297,11 +364,11 @@ void GPIO_PinModeSet(GPIO_Port_TypeDef port,
/* There are two registers controlling the pins for each port. The MODEL
* register controls pins 0-7 and MODEH controls pins 8-15. */
if (pin < 8) {
GPIO->P[port].MODEL = (GPIO->P[port].MODEL & ~(0xFu << (pin * 4)))
| (mode << (pin * 4));
// Cast parameter [mode] to 32 bits to fix C99 Undefined Behavior (see SEI CERT C INT34-C)
// Compiler assigned 8 bits for enum. Same thing for other branch.
BUS_RegMaskedWrite(&(GPIO->P[port].MODEL), 0xFu << (pin * 4), (uint32_t)mode << (pin * 4));
} else {
GPIO->P[port].MODEH = (GPIO->P[port].MODEH & ~(0xFu << ((pin - 8) * 4)))
| (mode << ((pin - 8) * 4));
BUS_RegMaskedWrite(&(GPIO->P[port].MODEH), 0xFu << ((pin - 8) * 4), (uint32_t)mode << ((pin - 8) * 4));
}
if (mode == gpioModeDisabled) {

103
gecko/emlib/src/em_msc.c
View File

@ -149,6 +149,11 @@
#define ECC_RAM0_SYNDROMES_INIT (MPAHBRAM_CTRL_ECCWEN)
#define ECC_RAM0_CORRECTION_EN (MPAHBRAM_CTRL_ECCEN)
#if defined(DMEM_COUNT) && (DMEM_COUNT == 2)
#define ECC_RAM1_SYNDROMES_INIT (MPAHBRAM_CTRL_ECCWEN)
#define ECC_RAM1_CORRECTION_EN (MPAHBRAM_CTRL_ECCEN)
#endif
#define ECC_IF_REG (DMEM->IF)
/* number of AHB ports is between 1 and 4 */
#if defined(MPAHBRAM_IF_AHB3ERR1B)
@ -168,6 +173,27 @@
#endif /* #if defined(if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) */
#define ECC_RAM_SIZE_MAX (RAM_MEM_SIZE)
#if defined(DMEM_COUNT) && (DMEM_COUNT == 2)
#define ECC_RAM0_MEM_BASE (DMEM0_RAM0_RAM_MEM_BASE)
#define ECC_RAM0_MEM_SIZE (DMEM0_RAM0_RAM_MEM_SIZE)
#define ECC_RAM1_MEM_BASE (DMEM1_RAM0_RAM_MEM_BASE)
#define ECC_RAM1_MEM_SIZE (DMEM1_RAM0_RAM_MEM_SIZE)
#define ECC_CTRL0_REG (DMEM0->CTRL)
#define ECC_CTRL1_REG (DMEM1->CTRL)
#define ECC_IFC0_REG (DMEM0->IF_CLR)
#define ECC_IFC1_REG (DMEM1->IF_CLR)
#define ECC_IFC_MASK (_MPAHBRAM_IF_MASK)
#define ECC_FAULT_CTRL0_REG (DMEM0->CTRL)
#define ECC_FAULT_CTRL1_REG (DMEM1->CTRL)
#define ECC_FAULT_EN (MPAHBRAM_CTRL_ECCERRFAULTEN)
#else
#define ECC_RAM0_MEM_BASE (SRAM_BASE)
#define ECC_RAM0_MEM_SIZE (SRAM_SIZE)
@ -188,6 +214,8 @@
#define ECC_FAULT_EN (MPAHBRAM_CTRL_ECCERRFAULTEN)
#endif
#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */
#else
#error Unknown device.
@ -665,7 +693,7 @@ MSC_RAMFUNC_DEFINITION_END
* A pointer to the flash word to write to. Must be aligned to words.
*
* @param[in] data
* Data to write to flash.
* Data to write to flash and be aligned to words.
*
* @param[in] numBytes
* A number of bytes to write from flash. NB: Must be divisible by four.
@ -1379,7 +1407,7 @@ MSC_RAMFUNC_DEFINITION_END
* @param[in] data
* Data to write to flash. Note that this argument must be an address in RAM.
* This function does not support copying data from flash to flash on series-1
* devices.
* devices. Must be aligned to words.
*
* @param[in] numBytes
* A number of bytes to write from flash. NB: Must be divisible by four.
@ -1540,9 +1568,22 @@ static void mscEccReadWriteExistingPio(const MSC_EccBank_Typedef *eccBank)
{
volatile uint32_t *ramptr = (volatile uint32_t *) eccBank->base;
const uint32_t *endptr = (const uint32_t *) (eccBank->base + eccBank->size);
volatile uint32_t *ctrlreg = &ECC_CTRL_REG;
volatile uint32_t *ctrlreg;
uint32_t enableEcc;
#if defined(DMEM_COUNT) && (DMEM_COUNT == 2)
if (eccBank->base == ECC_RAM0_MEM_BASE) {
ctrlreg = &ECC_CTRL0_REG;
} else if (eccBank->base == ECC_RAM1_MEM_BASE) {
ctrlreg = &ECC_CTRL1_REG;
} else {
EFM_ASSERT(0);
return;
}
#else
ctrlreg = &ECC_CTRL_REG;
#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */
EFM_ASSERT(ramptr < endptr);
#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7)
@ -1551,10 +1592,21 @@ static void mscEccReadWriteExistingPio(const MSC_EccBank_Typedef *eccBank)
/* MPAHBRAM ECC requires both ECCEN and ECCWEN to be set for the syndromes
to be written in ECC */
enableEcc = eccBank->correctionEnable;
/* Enable ECC syndrome write */
ECC_CTRL_REG |= eccBank->initSyndromeEnable;
/* Enable ECC syndrome write */
#if defined(DMEM_COUNT) && (DMEM_COUNT == 2)
if (eccBank->base == ECC_RAM0_MEM_BASE) {
ECC_CTRL0_REG |= eccBank->initSyndromeEnable;
ECC_IFC0_REG = ECC_IFC_MASK;
} else if (eccBank->base == ECC_RAM1_MEM_BASE) {
ECC_CTRL1_REG |= eccBank->initSyndromeEnable;
ECC_IFC1_REG = ECC_IFC_MASK;
}
#else
ECC_CTRL_REG |= eccBank->initSyndromeEnable;
ECC_IFC_REG = ECC_IFC_MASK;
#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */
#endif
#ifndef __GNUC__
@ -1790,7 +1842,15 @@ static void mscEccBankInit(const MSC_EccBank_Typedef *eccBank,
/* Clear any ECC errors that may have been reported before or during
initialization. */
#if defined(DMEM_COUNT) && (DMEM_COUNT == 2)
if (eccBank->base == ECC_RAM0_MEM_BASE) {
ECC_IFC0_REG = ECC_IFC_MASK;
} else if (eccBank->base == ECC_RAM1_MEM_BASE) {
ECC_IFC1_REG = ECC_IFC_MASK;
}
#else
ECC_IFC_REG = ECC_IFC_MASK;
#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */
#if !defined(_MPAHBRAM_CTRL_MASK)
/* Enable ECC decoder to detect and report ECC errors. */
@ -1815,7 +1875,15 @@ static void mscEccBankInit(const MSC_EccBank_Typedef *eccBank,
static void mscEccBankDisable(const MSC_EccBank_Typedef *eccBank)
{
/* Disable ECC write (encoder) and checking (decoder). */
#if defined(DMEM_COUNT) && (DMEM_COUNT == 2)
if (eccBank->base == ECC_RAM0_MEM_BASE) {
ECC_CTRL0_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable);
} else if (eccBank->base == ECC_RAM1_MEM_BASE) {
ECC_CTRL1_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable);
}
#else
ECC_CTRL_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable);
#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */
}
/***************************************************************************//**
@ -1902,13 +1970,22 @@ void MSC_EccConfigSet(MSC_EccConfig_TypeDef *eccConfig)
******************************************************************************/
void MSC_DmemPortMapSet(MSC_DmemMaster_TypeDef master, uint8_t port)
{
#if defined(DMEM_COUNT) && (DMEM_COUNT == 1)
uint32_t bitfieldMask = DMEM_NUM_PORTS - 1;
#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2)
uint32_t bitfieldMask = DMEM0_NUM_PORTS - 1;
#endif
/* make sure master is within the mask of port map that can be changed
* make sure port is a sensible value
*/
EFM_ASSERT(((1 << master) & _SYSCFG_DMEM0PORTMAPSEL_MASK) != 0x0);
#if defined(DMEM_COUNT) && (DMEM_COUNT == 1)
EFM_ASSERT(port < DMEM_NUM_PORTS);
#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2)
EFM_ASSERT(port < DMEM0_NUM_PORTS);
#endif
#if defined(CMU_CLKEN0_SYSCFG)
bool disableSyscfgClk = false;
@ -1950,11 +2027,22 @@ void MSC_DmemPortMapSet(MSC_DmemMaster_TypeDef master, uint8_t port)
******************************************************************************/
void MSC_PortSetPriority(MSC_PortPriority_TypeDef portPriority)
{
#if defined(DMEM_COUNT) && (DMEM_COUNT == 1)
EFM_ASSERT(portPriority < ((DMEM_NUM_PORTS + 1) << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT));
BUS_RegMaskedWrite(&DMEM->CTRL,
_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK,
(uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT);
#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2)
EFM_ASSERT(portPriority < ((DMEM0_NUM_PORTS + 1) << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT));
BUS_RegMaskedWrite(&DMEM0->CTRL,
_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK,
(uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT);
BUS_RegMaskedWrite(&DMEM1->CTRL,
_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK,
(uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT);
#endif
}
/***************************************************************************//**
@ -1971,8 +2059,13 @@ MSC_PortPriority_TypeDef MSC_PortGetCurrentPriority(void)
{
uint32_t port = 0;
#if defined(DMEM_COUNT) && (DMEM_COUNT == 1)
port = BUS_RegMaskedRead(&DMEM->CTRL,
_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK);
#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2)
port = BUS_RegMaskedRead(&DMEM0->CTRL,
_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK);
#endif
return (MSC_PortPriority_TypeDef)(port >> _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT);
}

192
gecko/emlib/src/em_se.c
View File

@ -27,14 +27,19 @@
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
#include "em_device.h"
#include "em_se.h"
#if defined(SLI_EM_SE_HOST) || defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT)
#if defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT)
#include "em_se.h"
#include "em_assert.h"
#include "em_core.h"
#include "sl_assert.h"
#include "em_system.h"
#endif
/***************************************************************************//**
* @addtogroup se
* @{
@ -53,24 +58,49 @@
#if defined(CRYPTOACC_PRESENT)
/* Size of Root Code Mailbox instance.
/// Signal that OTP version is incorporated into the status field of the output
#define SE_VSE_REPLY_STATUS_OTP_VERSION_SET (1 << 21)
/// Mask defining the region of the status field that contains the OTP version
/// number.
#define SE_VSE_REPLY_STATUS_OTP_VERSION_MASK (0xFF000000UL)
/// Shift to insert a number into the otp version part of the status field
#define SE_VSE_REPLY_STATUS_OTP_VERSION_SHIFT (24)
/* Size of VSE Mailbox instance.
There are two instances, input and output. */
#define ROOT_MAILBOX_SIZE (512UL)
/* Base addresses of the Root Code Input and Output Mailbox data structures.
(Must be stored in a RAM area which is not used by the root code)
We use the upper 1KB of FRC RAM for the root code mailboxes. */
#define ROOT_MAILBOX_OUTPUT_BASE (RDMEM_FRCRAM_S_MEM_END + 1 - ROOT_MAILBOX_SIZE)
#define ROOT_MAILBOX_INPUT_BASE (ROOT_MAILBOX_OUTPUT_BASE - ROOT_MAILBOX_SIZE)
/* Base addresses of the VSE Input and Output Mailbox data structures.
(Must be stored in a RAM area which is not used by the VSE)
We use the upper 1KB of FRC RAM for the VSE mailboxes. */
#define ROOT_MAILBOX_OUTPUT_S_BASE (RDMEM_FRCRAM_S_MEM_END + 1 - ROOT_MAILBOX_SIZE)
#define ROOT_MAILBOX_INPUT_S_BASE (ROOT_MAILBOX_OUTPUT_S_BASE - ROOT_MAILBOX_SIZE)
/* Position of parameter number field in Root Code Input Mailbox LENGTH field.*/
// SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S is defined in sl_trustzone_secure_config.h
#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S)) \
|| (defined(SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S) && SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S))
#define RDMEM_FRCRAM_MEM_BASE RDMEM_FRCRAM_S_MEM_BASE
#define ROOT_MAILBOX_OUTPUT_BASE SYSCFG->ROOTDATA1;
#define ROOT_MAILBOX_OUTPUT_BASE_EXPECTED ROOT_MAILBOX_OUTPUT_S_BASE
#else
#define RDMEM_FRCRAM_MEM_BASE RDMEM_FRCRAM_NS_MEM_BASE
// VSE will always output the secure address, if NS is desired, caculate the NS address.
#define ROOT_MAILBOX_OUTPUT_BASE (SYSCFG->ROOTDATA1 - RDMEM_FRCRAM_S_MEM_BASE + RDMEM_FRCRAM_NS_MEM_BASE);
#define ROOT_MAILBOX_OUTPUT_BASE_EXPECTED (RDMEM_FRCRAM_NS_MEM_END + 1 - ROOT_MAILBOX_SIZE)
#endif
#define ROOT_MAILBOX_INPUT_BASE (ROOT_MAILBOX_OUTPUT_BASE_EXPECTED - ROOT_MAILBOX_SIZE)
/* Position of parameter number field in VSE Input Mailbox LENGTH field.*/
#define ROOT_MB_LENGTH_PARAM_NUM_SHIFT (24)
/* Done flag indicating that the Root Code Mailbox handler has completed
/* Done flag indicating that the VSE Mailbox handler has completed
processing the mailbox command. */
#define ROOT_MB_DONE (1 << 23)
/* Root Code Configuration Status bits mask */
/* VSE Configuration Status bits mask */
#define ROOT_MB_OUTPUT_STATUS_CONFIG_BITS_MASK (0xFFFF)
#endif // #if defined(CRYPTOACC_PRESENT)
@ -81,7 +111,7 @@
******************************************************************************/
#if defined(CRYPTOACC_PRESENT)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
// Root Code Input Mailbox structure
// VSE Input Mailbox structure
typedef struct {
volatile uint32_t magic;
volatile uint32_t command;
@ -89,7 +119,7 @@ typedef struct {
volatile uint32_t data[0];
} root_InputMailbox_t;
// Root Code Output Mailbox structure
// VSE Output Mailbox structure
typedef struct {
volatile uint32_t magic;
volatile uint32_t version;
@ -225,6 +255,7 @@ void SE_addParameter(SE_Command_t *command, uint32_t parameter)
command->num_parameters += 1;
}
#if !defined(SLI_EM_SE_HOST)
/***************************************************************************//**
* @brief
* Execute the passed command
@ -267,9 +298,13 @@ void SE_executeCommand(SE_Command_t *command)
}
#elif defined(CRYPTOACC_PRESENT)
// Prepare the VSE Mailbox within a critical section to prevent
// the process from getting interrupted. At this point, the only option
// we have is to go through a reset, so it is safe to enter the critical section.
(void)CORE_EnterCritical();
// Setup pointer to the Root Code Mailbox Input data structure
// (must be stored in a RAM area which is not used by the root code)
// Setup pointer to the VSE Mailbox Input data structure
// (must be stored in a RAM area which is not used by the VSE)
root_InputMailbox_t *rootInMb = (root_InputMailbox_t*)ROOT_MAILBOX_INPUT_BASE;
uint32_t *mbData;
unsigned int mbDataLen, inDataLen, i;
@ -278,14 +313,16 @@ void SE_executeCommand(SE_Command_t *command)
uint32_t checksum;
bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0);
CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG;
// Set base of Mailbox Input data structure in SYSCFG register in order
// for Root Code to find it.
SYSCFG->ROOTDATA0 = ROOT_MAILBOX_INPUT_BASE;
// Store the secure memory base addresses for VSE to be able to read from the address
// Set base of Mailbox Input data structure in SYSCFG register in order
// for VSE to find it.
SYSCFG->ROOTDATA0 = ROOT_MAILBOX_INPUT_S_BASE;
// Set base of Mailbox Output data structure in SYSCFG register in order
// for Root Code to know where to write output data.
// for VSE to know where to write output data.
// Write command into FIFO
SYSCFG->ROOTDATA1 = ROOT_MAILBOX_OUTPUT_BASE;
SYSCFG->ROOTDATA1 = ROOT_MAILBOX_OUTPUT_S_BASE;
if (!sysCfgClkWasEnabled) {
CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG;
}
@ -333,25 +370,29 @@ void SE_executeCommand(SE_Command_t *command)
__NVIC_SystemReset();
#endif // #if defined(SEMAILBOX_PRESENT)
return;
}
#if defined(CRYPTOACC_PRESENT)
#endif // #if !defined(SLI_EM_SE_HOST)
#if defined(CRYPTOACC_PRESENT)
/***************************************************************************//**
* @brief
* Check whether the Root Code Output Mailbox is valid.
* Check whether the VSE Output Mailbox is valid.
*
* @return True if the Root Code Output Mailbox is valid (magic and checksum OK)
* @return True if the VSE Output Mailbox is valid (magic and checksum OK)
******************************************************************************/
bool rootIsOutputMailboxValid(void)
{
// Setup pointer to the Root Code Output Mailbox data structure
// (must be stored in a RAM area which is not used by the root code)
// Setup pointer to the VSE Output Mailbox data structure
// (must be stored in a RAM area which is not used by the VSE)
bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0);
CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG;
root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) SYSCFG->ROOTDATA1;
root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE;
if ((uint32_t)rootOutMb > ROOT_MAILBOX_OUTPUT_BASE_EXPECTED
|| (uint32_t)rootOutMb < RDMEM_FRCRAM_MEM_BASE) {
return false;
}
if (!sysCfgClkWasEnabled) {
CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG;
}
@ -385,10 +426,10 @@ bool rootIsOutputMailboxValid(void)
* Get current SE version
*
* @details
* This function returns the current root code version
* This function returns the current VSE version
*
* @param[in] version
* Pointer to location where to copy the version of root code to.
* Pointer to location where to copy the version of VSE to.
*
* @return
* One of the SE_RESPONSE return codes:
@ -400,7 +441,7 @@ SE_Response_t SE_getVersion(uint32_t *version)
{
bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0);
CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG;
root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) SYSCFG->ROOTDATA1;
root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE;
if (!sysCfgClkWasEnabled) {
CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG;
}
@ -422,10 +463,10 @@ SE_Response_t SE_getVersion(uint32_t *version)
/***************************************************************************//**
* @brief
* Get Root Code configuration and status bits
* Get VSE configuration and status bits
*
* @details
* This function returns the current Root Code configuration and status bits.
* This function returns the current VSE configuration and status bits.
* The following list explains what the different bits in cfgStatus indicate.
* A bit value of 1 means enabled, while 0 means disabled:
* * [0]: Secure boot
@ -433,7 +474,7 @@ SE_Response_t SE_getVersion(uint32_t *version)
* * [2]: Anti-rollback
* * [3]: Narrow page lock
* * [4]: Full page lock
* The following status bits can be read with Root Code versions
* The following status bits can be read with VSE versions
* higher than 1.2.2.
* * [10]: Debug port lock
* * [11]: Device erase enabled
@ -459,7 +500,7 @@ SE_Response_t SE_getConfigStatusBits(uint32_t *cfgStatus)
{
bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0);
CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG;
root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) SYSCFG->ROOTDATA1;
root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE;
if (!sysCfgClkWasEnabled) {
CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG;
}
@ -479,6 +520,50 @@ SE_Response_t SE_getConfigStatusBits(uint32_t *cfgStatus)
return SE_RESPONSE_OK;
}
/***************************************************************************//**
* @brief
* Get the version number of the OTP from the status field of the output
* mailbox
* @details
* This function checks if the OTP version number flag is set in the output
* mailbox. If it is, the version number is writen to @ref otpVersion pointer
* location. If not, it returns error response.
*
* @param[out] otpVersion
* Pointer to location to copy OTP version number into.
* @return
* One of the SE_RESPONSE return codes.
* @retval SE_RESPONSE_OK when the command was executed successfully
******************************************************************************/
SE_Response_t SE_getOTPVersion(uint32_t *otpVersion)
{
bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0);
CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG;
root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE;
if (!sysCfgClkWasEnabled) {
CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG;
}
if (otpVersion == NULL) {
return SE_RESPONSE_INVALID_PARAMETER;
}
// First verify that the response is ok.
if (!rootIsOutputMailboxValid()) {
return SE_RESPONSE_MAILBOX_INVALID;
}
bool isOTPVersionSet = rootOutMb->status & SE_VSE_REPLY_STATUS_OTP_VERSION_SET;
if (isOTPVersionSet) {
// Return the OTP version from the status field.
*otpVersion = (rootOutMb->status & SE_VSE_REPLY_STATUS_OTP_VERSION_MASK) >> SE_VSE_REPLY_STATUS_OTP_VERSION_SHIFT;
} else {
return SE_RESPONSE_INVALID_COMMAND;
}
return SE_RESPONSE_OK;
}
/***************************************************************************//**
* @brief
* Check whether the running command has completed.
@ -492,7 +577,7 @@ bool SE_isCommandCompleted(void)
{
bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0);
CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG;
root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) SYSCFG->ROOTDATA1;
root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE;
if (!sysCfgClkWasEnabled) {
CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG;
}
@ -521,7 +606,7 @@ uint32_t SE_readExecutedCommand(void)
{
bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0);
CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG;
root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) SYSCFG->ROOTDATA1;
root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE;
if (!sysCfgClkWasEnabled) {
CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG;
}
@ -558,7 +643,7 @@ SE_Response_t SE_readCommandResponse(void)
{
bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0);
CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG;
root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) SYSCFG->ROOTDATA1;
root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE;
if (!sysCfgClkWasEnabled) {
CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG;
}
@ -602,11 +687,11 @@ SE_Response_t SE_readCommandResponse(void)
******************************************************************************/
SE_Response_t SE_ackCommand(SE_Command_t *command)
{
// Setup pointer to the Root Code Output Mailbox data structure
// (must be stored in a RAM area which is not used by the root code)
// Setup pointer to the VSE Output Mailbox data structure
// (must be stored in a RAM area which is not used by the VSE)
bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0);
CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG;
root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) SYSCFG->ROOTDATA1;
root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE;
if (!sysCfgClkWasEnabled) {
CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG;
}
@ -675,6 +760,7 @@ SE_Response_t SE_ackCommand(SE_Command_t *command)
* manager.
*******************************************************************************/
#if !defined(SLI_EM_SE_HOST)
/***************************************************************************//**
* @brief
*
@ -716,7 +802,7 @@ SE_Response_t SE_ackCommand(SE_Command_t *command)
******************************************************************************/
SE_Response_t SE_initPubkey(uint32_t key_type, void *pubkey, uint32_t numBytes, bool signature)
{
uint32_t commandWord;
uint32_t commandWord = SE_COMMAND_INIT_PUBKEY;
SE_Response_t res = SE_RESPONSE_INVALID_COMMAND;
EFM_ASSERT((key_type == SE_KEY_TYPE_BOOT)
@ -737,7 +823,6 @@ SE_Response_t SE_initPubkey(uint32_t key_type, void *pubkey, uint32_t numBytes,
(signature) ? SE_COMMAND_INIT_PUBKEY_SIGNATURE : SE_COMMAND_INIT_PUBKEY;
#elif defined(CRYPTOACC_PRESENT)
(void)signature;
commandWord = SE_COMMAND_INIT_PUBKEY;
#endif
SE_Command_t command = SE_COMMAND_DEFAULT(commandWord | key_type);
@ -796,9 +881,18 @@ SE_Response_t SE_initOTP(SE_OTPInit_t *otp_init)
#if defined(SEMAILBOX_PRESENT)
uint8_t pubkey[64];
res = SE_readPubkey(SE_KEY_TYPE_BOOT, &pubkey, 64, false);
if (res != SE_RESPONSE_OK) {
return SE_RESPONSE_ABORT;
{
EFM_ASSERT(!((size_t)pubkey & 3U));
// SE command structures
SE_Command_t commandPubkeyRead = SE_COMMAND_DEFAULT(SE_COMMAND_READ_PUBKEY | SE_KEY_TYPE_BOOT);
SE_DataTransfer_t pubkeyData = SE_DATATRANSFER_DEFAULT(pubkey, sizeof(pubkey));
SE_addDataOutput(&commandPubkeyRead, &pubkeyData);
SE_executeCommand(&commandPubkeyRead);
res = SE_readCommandResponse();
if (res != SE_RESPONSE_OK) {
return SE_RESPONSE_ABORT;
}
res = SE_RESPONSE_INVALID_COMMAND;
}
#endif
}
@ -868,6 +962,9 @@ SE_Response_t SE_initOTP(SE_OTPInit_t *otp_init)
SE_addDataInput(&command, &mcuSettingsFlagsData);
SE_executeCommand(&command);
#else
(void)command;
(void)parameters;
#endif
return res;
@ -1267,6 +1364,7 @@ SE_Response_t SE_deviceEraseDisable(void)
}
#endif // #if defined(SEMAILBOX_PRESENT)
#endif // #if !defined(SLI_EM_SE_HOST)
/** @} (end addtogroup deprecated_se) */
/** @} (end addtogroup se) */