Remove references to FPGA IP core drivers
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
This commit is contained in:
Jan Kowalewski
Kumar Gala
parent
7deb3aab1c
commit
b3a66fe6d0
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@ -1001,30 +1001,6 @@ typedef struct
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__IO uint32_t CID3;
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}TIMER_TypeDef;
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/*
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* FPGA GPIO
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*/
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typedef struct
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{
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__IO uint32_t ID_VALUE;
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__IO uint32_t REV_LEVEL;
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__IO uint32_t GPIO_INPUT;
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__IO uint32_t GPIO_OUTPUT;
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__IO uint32_t GPIO_DIR_CTRL;
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}FPGA_GPIO_TypeDef;
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typedef struct
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{
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__IO uint32_t UART_DR_DLLSB; /* Receive/Transmit/DL_LSB: 0x00 */
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__IO uint32_t UART_IER_DLMSB; /* Interrupt Enable Register/DL_MSB: 0x04 */
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__IO uint32_t UART_IIR_FCR; /* Interrupt Identification Register, FIFO Control Register 0x08 */
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__IO uint32_t UART_LCR; /* Line Control Register 0xC */
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__IO uint32_t UART_MCR; /* Modem Control Register 0x10 */
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__IO uint32_t UART_LSR; /* Line Status Register 0x14 */
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__IO uint32_t UART_MSR; /* Modem Status Register 0x18 */
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__IO uint32_t UART_SR; /* Scratch Register 0x1C */
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} FPGA_UART_TypeDef;
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/**
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* @brief Peripheral_memory_map
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*/
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@ -1092,12 +1068,6 @@ typedef struct
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/* Debug MCU registers base address */
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#define DBGMCU_BASE ((uint32_t )0xE0042000)
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#define FB_GPIO_BASE FPGA_PERIPH_BASE
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#define FB_UART_BASE (FPGA_PERIPH_BASE+0x1000)
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/* IR register definitions */
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#define FB_IR_DEVID_REG (FPGA_PERIPH_BASE+(0x800)+(0x50<<2)) // (FPGA_PERIPH_BASE+(0x50<<2))
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/*
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* Peripheral_declaration
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*/
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@ -1121,10 +1091,6 @@ typedef struct
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#define EXT_REGS_FFE ((EXT_REGS_FFE_TypeDef *)EXT_REGS_FFE_BASE)
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#define AIP ((AIP_Typedef*)AIP_BASE)
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#define SPT ((SPT_REGS_TypeDef *)SPT_BASE)
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#define FB_GPIO ((FPGA_GPIO_TypeDef *)FB_GPIO_BASE)
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#define FB_UART ((FPGA_UART_TypeDef *)FB_UART_BASE)
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#define FB_I2C ((FPGA_I2C_TypeDef *)FB_I2C_BASE)
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#define FB_HRM ((FPGA_HRM_TypeDef *)FB_HRM_BASE)
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#define TIMER ((TIMER_TypeDef *)TIMER1_BASE)
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#define SHM_QL_BASE (0x2007C000)
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@ -1,91 +0,0 @@
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/*
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* ==========================================================
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*
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* Copyright (C) 2020 QuickLogic Corporation
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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* http://www.apache.org/licenses/LICENSE-2.0
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* File : eoss3_hal_fpga_adc_api.h
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* Purpose : This file contains ADC wrapper APIs to use by FPGA ADC IP drivers
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* for data transfer to and from FPGA ADC IP on S3.
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* These APIs can be used by only FPGA IP applications.
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*
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* ===========================================================
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*
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*/
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#ifndef HAL_EOSS3_HAL_FPGA_ADC_API_H_
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#define HAL_EOSS3_HAL_FPGA_ADC_API_H_
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#include "eoss3_dev.h"
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#include "eoss3_hal_def.h"
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/* ADC LTC1859 command configuration.
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* channelX_command 8 bit format as follows:
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* bit 7:4->Channel Mux Address ==> Channel selection and Single/Differential config.
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* bit 3:2->Input Range selection ==> Polarity and Gain of input signal.
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* bit 1:0->Power down modes. [NAP:SLEEP]. Currently these bits are not supported.
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* Each channel can be configured independently of others.
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* Refere data sheet "LTC185x Datasheet.pdf" for details about these configuration.
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*/
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typedef struct __LTC1859_cfg_t
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{
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uint32_t frequency;
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/* today - we support 4 channels, future we might support 8 single ended */
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#define LTC1859_MAX_CHANNELS 8
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uint8_t chnl_commands[LTC1859_MAX_CHANNELS];
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uint8_t channel_enable_bits;
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} HAL_LTC1859_cfg_t;
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/*
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* This structure maps a "config" value
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* into two things:
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* (1) A format char for the JSON data.
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* (2) conversion factors that convert the ADC count into uVolts.
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*/
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struct LTC1859_ymx_plus_b {
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uint8_t masked_config_value;
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char python_format_char;
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int8_t is_signed;
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int8_t dummy_pad;
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int32_t slopeM; /* multiplier */
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int32_t slopeD; /* divisor */
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int32_t intercept;
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};
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/* given a config value, return a valid conversion struct for the sensor value */
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const struct LTC1859_ymx_plus_b *HAL_LTC1859_CfgToYmxB( int config );
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int LTC1859_to_uVolts( uint8_t cfg, uint16_t value );
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/* Initilazation of FPGA ADC HAL driver.
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* cfg -> pointer to filled configuration structure for adc channels.
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* pcb_read is call back function which gets called when sensor data read is
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* completed when HAL_FPGA_ADC_Read() is called.
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* Returns Success/Failure.
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*/
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HAL_StatusTypeDef HAL_LTC1859_ADC_Init(HAL_LTC1859_cfg_t *cfg, void (*pcb_read)(void));
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/*
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* API to read block of sensor data.
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* Returns success/failure.
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* This is non-blocking API, when it fills buffer, read call back will be called.
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* Buffer length is expected to be multiple of 4 bytes. If buffer length is not
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* multiple of 4 bytes, it will fill buffer upto nearest multiple of 4 [= n_bytes/4*4]
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*/
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HAL_StatusTypeDef HAL_LTC1859_ADC_Read(void *buffer, size_t n_bytes);
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/*
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* API to release acquired resources.
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*/
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void HAL_LTC1859_ADC_De_Init(void);
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#endif //HAL_EOSS3_HAL_FPGA_ADC_API_H_
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@ -1,62 +0,0 @@
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/*
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* ==========================================================
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*
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* Copyright (C) 2020 QuickLogic Corporation
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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* http://www.apache.org/licenses/LICENSE-2.0
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* File : eoss3_hal_fpga_adc_reg.h
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* Purpose : This file contains Register definitions of FPGA ADC interface IP.
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*
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* ===========================================================
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*
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*/
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#ifndef HAL_EOSS3_HAL_FPGA_ADC_REG_H_
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#define HAL_EOSS3_HAL_FPGA_ADC_REG_H_
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#define FPGA_ADC_BASE (FPGA_PERIPH_BASE)
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/* FPGA AGC register definitions. */
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typedef struct
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{
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__IO uint32_t CHIP_ID; /*0x0 */ //IP DEVICE ID = {0x55ADC}
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__IO uint32_t REV_NO; /*0x4 */ //IP Revision number value = 0x0100 [version 1.0]
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__IO uint32_t FIFO_RESET; /*0x8 */ //RX FIFO FLUSH HW auto clear
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__IO uint32_t SEN_ENR; /*0xC */ //Sensor Enable Register. Bit Mask for Sensor Channels
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__IO uint32_t SEN1_SETTING; /*0x10 */ //Sensor1 settings.
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__IO uint32_t SEN2_SETTING; /*0x14 */ //Sensor2 settings.
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__IO uint32_t SEN3_SETTING; /*0x18 */ //Sensor3 settings.
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__IO uint32_t SEN4_SETTING; /*0x1C */ //Sensor4 settings.
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/* Timer works on C21 Clock (C21 = 2 MHz, SW setting, 0.5usec pulse) Load 0x100 for 16kHz, 0x29 for 100kHz*/
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__IO uint32_t TIMER_COUNT; /*0x20 */ //Time count for highest sampling rate.
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__IO uint32_t TIMER_ENABLE; /*0x24 */ //Timer Enable
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} FPGA_ADC_TypeDef;
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#define FPGA_ADC ((FPGA_ADC_TypeDef *) FPGA_ADC_BASE)
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#define ADC_CHIP_ID_VAL (0x55ADC)
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#define SENSOR_SAMPLE_RATE_100KHZ (100000)
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#define SENSOR_SAMPLE_RATE_16KHZ (16000)
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#define SENSOR_SAMPLE_RATE_100KHZ_DIV_VALUE (0x29)
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#define SENSOR_SAMPLE_RATE_16KHZ_DIV_VALUE (0x100)
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#define FOUR_MEGA_HZ (4096000)
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#define ADC_FIFO_RESET_BIT (0x1)
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#define ADC_TIMER_ENABLE_BIT (0x1)
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#define CHANNEL0_ENABLE_MASK (0x1 << 0)
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#define CHANNEL1_ENABLE_MASK (0x1 << 1)
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#define CHANNEL2_ENABLE_MASK (0x1 << 2)
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#define CHANNEL3_ENABLE_MASK (0x1 << 3)
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#endif //HAL_EOSS3_HAL_FPGA_ADC_REG_H_
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@ -1,132 +0,0 @@
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/*
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* ==========================================================
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*
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* Copyright (C) 2020 QuickLogic Corporation
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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* http://www.apache.org/licenses/LICENSE-2.0
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* File : eoss3_hal_fpga_clk_sync.h
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* Purpose :
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*
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* ===========================================================
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*
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*/
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#ifndef __EOSS3_HAL_FPGA_CLK_SYNC_H_
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#define __EOSS3_HAL_FPGA_CLK_SYNC_H_
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/**
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* @brief return value definitions
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*/
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#include <stdint.h>
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/**
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* @brief return value definitions
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*/
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#define HAL_FB_CLK_SYNC_RET_VAL (0x0)
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#define HAL_FB_CLK_SYNC_ERR (0x20)
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#define HAL_FB_CLK_SYNC_SUCCESS (HAL_FB_CLK_SYNC_ERR + 0x0)
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#define HAL_FB_CLK_SYNC_INIT_ERR (HAL_FB_CLK_SYNC_ERR + 0x1)
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#define HAL_FB_CLK_SYNC_START_ERR (HAL_FB_CLK_SYNC_ERR + 0x2)
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#define HAL_FB_CLK_SYNC_STOP_ERR (HAL_FB_CLK_SYNC_ERR + 0x3)
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#define HAL_FB_CLK_SYNC_ADJUST_ERR (HAL_FB_CLK_SYNC_ERR + 0x4)
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/* HS Oscillator frequency increase in multiple of 32 kHz */
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#define HAL_HSOSC_ADJ_UNIT (32768 * 1)
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/* Sampling rate of word select clock, This is external clock from the other chip */
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#define HAL_FB_EXT_CLK_48KHZ 48000 /* External clock is 48 kHz */
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#define HAL_FB_EXT_CLK_32KHZ 32000 /* External clock is 32 kHz */
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#define HAL_FB_EXT_CLK_16KHZ 16000 /* External clock is 16 kHz */
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/**
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* @brief HSOSC clock synchronization structure
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*/
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typedef struct
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{
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uint16_t sampling_freq; /* Sampling frequency of external clock */
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uint32_t clk_osc; /* Clock oscialltor adjustment unit */
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} FB_clk_sync_Cfg_t;
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/**
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* @brief HAL_FB_Clk_Sync_init Clock synchronization initialization.
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*
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* @param[in] clksync_cfg, configurations for clock sync.
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*
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* @retval uint32_t, Returns a HAL_FB_CLK_SYNC_SUCCESS in case of success.
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* In case of failure returns HAL_FB_CLK_SYNC_INIT_ERR.
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*
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*/
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uint32_t HAL_FB_Clk_Sync_init (FB_clk_sync_Cfg_t clksync_cfg);
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/**
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* @brief HAL_FB_Clk_Sync_start this API will enable the FB Clocks and enables the
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* clock synchronization flag
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*
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* @param[in] void
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*
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* @retval uint32_t, Returns a HAL_FB_CLK_SYNC_SUCCESS in case of success.
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* In case of failure returns HAL_FB_CLK_SYNC_START_ERR.
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*
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*/
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uint32_t HAL_FB_Clk_Sync_start (void);
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/**
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* @brief HAL_FB_Clk_Sync_adjust this API will check the sample count and re-adjust clock
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* if there is any difference in the samples. This has to be called every time when
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* the data arrives. To be called from dma handler.
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*
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* @param[out] difference in samples
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*
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* @retval uint32_t, Returns a HAL_FB_CLK_SYNC_SUCCESS in case of success.
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* In case of failure returns HAL_FB_CLK_SYNC_ERR.
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*
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*/
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uint32_t HAL_FB_Clk_Sync_adjust (int32_t *adjust_unit);
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/**
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* @brief HAL_FB_Clk_Sync_stop This API will disable the FB Clock and disables
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* clock synchronization
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*
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* @param[in] void
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*
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* @retval uint32_t, Returns a HAL_FB_CLK_SYNC_SUCCESS in case of success.
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* In case of failure returns HAL_FB_CLK_SYNC_STOP_ERR.
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*
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*/
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uint32_t HAL_FB_Clk_Sync_stop (void);
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/**
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* @brief HAL_FB_Clk_Sync_Reset_counter This API will reset the I2S, MIC counter
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* and the clock synchronization starts again.
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*
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* @param[in] void
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*
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* @retval uint32_t, Returns a HAL_FB_CLK_SYNC_SUCCESS in case of success.
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* In case of failure returns HAL_FB_CLK_SYNC_ERR.
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*
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*/
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uint32_t HAL_FB_Clk_Sync_Reset_counter (void);
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/**
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* @brief HAL_FB_Clk_Sync_uninit This API will uninit the clock synchronization
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* process.
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*
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* @param[in] void
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*
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* @retval uint32_t, Returns a HAL_FB_CLK_SYNC_SUCCESS in case of success.
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* In case of failure returns HAL_FB_CLK_SYNC_ERR.
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*
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*/
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uint32_t HAL_FB_Clk_Sync_uninit (void);
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#endif /* __EOSS3_HAL_FPGA_CLK_SYNC_H_ */
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@ -1,116 +0,0 @@
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/*
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* ==========================================================
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*
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* Copyright (C) 2020 QuickLogic Corporation
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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* http://www.apache.org/licenses/LICENSE-2.0
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* Unless required by applicable law or agreed to in writing, software
|
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* File : eoss3_hal_fpga_gpio.h
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* Purpose :
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*
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* ===========================================================
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*
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*/
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#ifndef __EOSS3_HAL_FPGA_GPIO_H
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#define __EOSS3_HAL_FPGA_GPIO_H
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#include "eoss3_dev.h"
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#include "eoss3_hal_def.h"
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#define xCUR_BOARD
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* FPGA July 28 release for REV01
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Pin Name PAD Number
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SIN (UART RXD) PAD[45]
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SOUT (UART TXD) PAD[44]
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I2C_SCL (LCD) PAD[6]
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I2C_SDA (LCD) PAD[7]
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GPIO_PIN[0] PAD[3]
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GPIO_PIN[1] PAD[11]
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GPIO_PIN[2] PAD[19]
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GPIO_PIN[3] PAD[43]
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GPIO_PIN[4] PAD[8]
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GPIO_PIN[5] PAD[41]
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GPIO_PIN[6] PAD[9]
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GPIO_PIN[7] PAD[13]
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GPIO_PIN[8] PAD[10]
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GPIO_PIN[9] PAD[17]
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GPIO_PIN[10] PAD[18]
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GPIO_PIN[11] PAD[23]
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GPIO_PIN[12] PAD[20]
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GPIO_PIN[13] PAD[21]
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GPIO_PIN[14] PAD[22]
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GPIO_PIN[15] PAD[16]
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GPIO_PIN[16] PAD[26]
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GPIO_PIN[17] PAD[27]
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GPIO_PIN[18] PAD[42]
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GPIO_PIN[19] PAD[12]
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GPIO_PIN[20] PAD[40]
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GPIO_PIN[21] PAD[2]
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I2C_SCL_SEN (HRM) PAD[29]
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I2C_SDA_SEN (HRM) PAD[28]
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CLK_4MHZ_IN PAD[30]
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CLK_1MHZ_OUT PAD[31]
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*/
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// REV00 // REV01
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#define FB_GPIO_0 0 // PAD3 // PAD[3]
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#define FB_GPIO_1 1 // PAD6 // PAD[11]
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#define FB_GPIO_2 2 // PAD8 // PAD[19]
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#define FB_GPIO_3 3 // PAD9 // PAD[43]
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#define FB_GPIO_4 4 // PAD10 // PAD[8]
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#define FB_GPIO_5 5 // PAD11 // PAD[41]
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#define FB_GPIO_6 6 // PAD12 // PAD[9]
|
||||
#define FB_GPIO_7 7 // PAD13 // PAD[13]
|
||||
#define FB_GPIO_8 8 // PAD23 // PAD[10]
|
||||
#define FB_GPIO_9 9 // PAD17 // PAD[17]
|
||||
#define FB_GPIO_10 10 // PAD18 // PAD[18]
|
||||
#define FB_GPIO_11 11 // PAD19 // PAD[23]
|
||||
#define FB_GPIO_12 12 // PAD20 // PAD[20]
|
||||
#define FB_GPIO_13 13 // PAD21 // PAD[21]
|
||||
#define FB_GPIO_14 14 // PAD22 // PAD[22]
|
||||
#define FB_GPIO_15 15 // PAD16 // PAD[16]
|
||||
#define FB_GPIO_16 16 // PAD26 // PAD[26]
|
||||
#define FB_GPIO_17 17 // PAD27 // PAD[27]
|
||||
#define FB_GPIO_18 18 // SFBIO[10] // PAD[42]
|
||||
#define FB_GPIO_19 19 // SFBIO[11] // PAD[12]
|
||||
#define FB_GPIO_20 20 // PAD7 // PAD[40]
|
||||
#define FB_GPIO_21 21 // PAD2 // PAD[2]
|
||||
|
||||
|
||||
|
||||
/*! \fn HAL_StatusTypeDef HAL_FB_GPIO_Read(uint8_t ucGpioIndex, uint8_t *ucGpioVal)
|
||||
\brief fpga GPIO read function to read pad status. Before using this function
|
||||
given pad needs to be initalized.
|
||||
\param ucGpioIndex - GPIO index that needs to be read.
|
||||
\param *ucGpioVal - GPIO status read, return value pointer.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FB_GPIO_Read(uint8_t ucGpioIndex, uint8_t *ucGpioVal);
|
||||
|
||||
/*! \fn HAL_StatusTypeDef HAL_FB_GPIO_Write(uint8_t ucGpioIndex, uint8_t ucGpioVal)
|
||||
\brief fpga GPIO write function to read pad status. Before using this function
|
||||
given pad needs to be initalized.
|
||||
\param ucGpioIndex - GPIO index that needs to be read.
|
||||
\param ucGpioVal - GPIO status that nees to be written.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FB_GPIO_Write(uint8_t ucGpioIndex, uint8_t ucGpioVal);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __EOSS3_HAL_FPGA_GPIO_H */
|
||||
|
|
@ -1,77 +0,0 @@
|
|||
/*
|
||||
* ==========================================================
|
||||
*
|
||||
* Copyright (C) 2020 QuickLogic Corporation
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* File : eoss3_hal_fpga_sdma_api.h
|
||||
* Purpose :
|
||||
*
|
||||
* ===========================================================
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef HAL_EOSS3_HAL_FPGA_SDMA_API_H_
|
||||
#define HAL_EOSS3_HAL_FPGA_SDMA_API_H_
|
||||
|
||||
#include "eoss3_dev.h"
|
||||
#include "eoss3_hal_def.h"
|
||||
|
||||
/* Datasize unit of SDMA transfers. */
|
||||
typedef enum
|
||||
{
|
||||
DATASIZE_BYTE = 8,
|
||||
DATASIZE_HWORD = 16,
|
||||
DATASIZE_WORD = 32,
|
||||
DTASIZE_INVALID
|
||||
} DATA_SIZE;
|
||||
|
||||
/* SDMA channel configuration to use in HAL_FSDMA_GetChannel API. */
|
||||
typedef struct __FSDMA_Channel_Config
|
||||
{
|
||||
DATA_SIZE data_size;
|
||||
uint32_t r_power;
|
||||
}ch_cfg_t;
|
||||
|
||||
/* Initilazation of FPGA SDMA HAL driver. */
|
||||
HAL_StatusTypeDef HAL_FSDMA_Init(void);
|
||||
|
||||
/*
|
||||
* API to get a channel handle to make transfer and Receive data from FPGA IP.
|
||||
* On channel resource allocation, handle will be returned. Applciation should use
|
||||
* this handle for next transfer/Receive APIs.
|
||||
* If transfer completes between FPGA and SRAM, callback will be triggered.
|
||||
* If callback parameter is NULL, Transfer and receive APIs are synchronous.
|
||||
*/
|
||||
void* HAL_FSDMA_GetChannel(void (*pCallback)(void*), ch_cfg_t *cfg);
|
||||
|
||||
/*
|
||||
* API to release channel resource.
|
||||
*
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FSDMA_ReleaseChannel(void *handle);
|
||||
|
||||
/*
|
||||
* Transfer data of length bytes from SRAM source to FPGA IP.
|
||||
* Assuming, Destination in FPGA IP is fixed Fifo Data register
|
||||
* length is transfer size in bytes.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FSDMA_Send(void *handle, void *srcptr, uint32_t length);
|
||||
|
||||
/*
|
||||
* Transfer data of length bytes from FPGA IP to SRAM destination address.
|
||||
* Assuming, Source in FPGA IP is fixed Fifo Data register.
|
||||
* length is transfer size in bytes.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FSDMA_Receive(void *handle, void *dstptr, uint32_t length);
|
||||
|
||||
|
||||
#endif //HAL_EOSS3_HAL_FPGA_SDMA_API_H_
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
/*
|
||||
* ==========================================================
|
||||
*
|
||||
* Copyright (C) 2020 QuickLogic Corporation
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* File : eoss3_hal_fpga_sdma_reg.h
|
||||
* Purpose :
|
||||
*
|
||||
* ===========================================================
|
||||
*
|
||||
*/
|
||||
#ifndef HAL_EOSS3_HAL_FPGA_SDMA_REG_H_
|
||||
#define HAL_EOSS3_HAL_FPGA_SDMA_REG_H_
|
||||
|
||||
#define FB_FSDMA_BASE (FPGA_PERIPH_BASE + 0x10000)
|
||||
#define FB_SDMA ((FSDMA_TypeDef *) FB_FSDMA_BASE)
|
||||
|
||||
#define FSDMA_CH0_DATA_REGISTER (FB_FSDMA_BASE + 0x1000)
|
||||
#define FSDMA_CH1_DATA_REGISTER (FB_FSDMA_BASE + 0x2000)
|
||||
#define FSDMA_CH2_DATA_REGISTER (FB_FSDMA_BASE + 0x3000)
|
||||
#define FSDMA_CH3_DATA_REGISTER (FB_FSDMA_BASE + 0x4000)
|
||||
|
||||
/* FPGA SDMA register definitions. */
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t FSDMA_ENR; /*0x0 */ //DMA Enable Register
|
||||
__IO uint32_t FSDMA_SR; /*0x4 */ // DMA status Register
|
||||
__IO uint32_t FSDMA_INTEN; /*0x8 */ //DMA Interrupt Enable Register
|
||||
|
||||
} FSDMA_TypeDef;
|
||||
|
||||
#define FSDMA_CHANNEL_EN(ch) (0x1 << ch) //DMA Channel Enable
|
||||
#define FSDMA_CHANNEL_INTR_CLR(ch) (0x1 << ch) //DMA Interrupt Status [Read - Status, Write - clearing interrupt]
|
||||
#define FSDMA_CHANNEL_INTR_EN(ch) (0x1 << ch) //DMA Interrupt Enable at IP level [NVIC level enabling is seperate from this]
|
||||
#define FSDMA_CHANNEL_POS(ch) (ch) // Get Channel Position value
|
||||
|
||||
#endif //HAL_EOSS3_HAL_FPGA_SDMA_REG_H_
|
||||
|
|
@ -1,154 +0,0 @@
|
|||
/*
|
||||
* ==========================================================
|
||||
*
|
||||
* Copyright (C) 2020 QuickLogic Corporation
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* File : eoss3_hal_fpga_uart.h
|
||||
* Purpose : This file contains API declaration for UART read/write
|
||||
* implmented in fpga
|
||||
*
|
||||
* ===========================================================
|
||||
*
|
||||
*/
|
||||
#ifndef __EOSS3_HAL_FB_UART_H_
|
||||
#define __EOSS3_HAL_FB_UART_H_
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include "eoss3_dev.h"
|
||||
#include "eoss3_hal_def.h"
|
||||
#include "eoss3_hal_uart.h"
|
||||
|
||||
|
||||
//
|
||||
// Interrupt Enable Register
|
||||
//
|
||||
|
||||
#define IER_ERXRDY 0x01
|
||||
#define IER_ETXRDY 0x02
|
||||
#define IER_ERLS 0x04
|
||||
#define IER_EMSC 0x08
|
||||
|
||||
//
|
||||
// Interrupt Identification Register
|
||||
//
|
||||
|
||||
#define IIR_IMASK 0x0F
|
||||
#define IIR_NOPEND 0x01
|
||||
#define IIR_MLSC 0x00
|
||||
#define IIR_TXRDY 0x02
|
||||
#define IIR_RXRDY 0x04
|
||||
#define IIR_RLS 0x06
|
||||
#define IIR_RXTOUT 0x0C
|
||||
#define IIR_FIFO_MASK 0xC0 // Set if FIFOs are enabled
|
||||
|
||||
//
|
||||
// FIFO Control Register
|
||||
//
|
||||
|
||||
#define FCR_ENABLE 0x01
|
||||
#define FCR_RCV_RST 0x02
|
||||
#define FCR_XMT_RST 0x04
|
||||
#define FCR_DMA_MODE 0x08
|
||||
#define FCR_TRIGGER_1 0x00
|
||||
#define FCR_TRIGGER_4 0x40
|
||||
#define FCR_TRIGGER_8 0x80
|
||||
#define FCR_TRIGGER_14 0xC0
|
||||
|
||||
//
|
||||
// Line Control Register
|
||||
//
|
||||
|
||||
#define LCR_DLAB 0x80
|
||||
#define LCR_SBREAK 0x40
|
||||
#define LCR_PZERO 0x30
|
||||
#define LCR_PONE 0x20
|
||||
#define LCR_PEVEN 0x10
|
||||
#define LCR_PODD 0x00
|
||||
#define LCR_PENAB 0x08
|
||||
#define LCR_STOPB 0x04
|
||||
#define LCR_8BITS 0x03
|
||||
#define LCR_7BITS 0x02
|
||||
#define LCR_6BITS 0x01
|
||||
#define LCR_5BITS 0x00
|
||||
|
||||
//
|
||||
// Modem Control Register
|
||||
//
|
||||
|
||||
|
||||
#define MCR_FLOW 0x20
|
||||
#define MCR_LOOPBACK 0x10
|
||||
#define MCR_OUT2 0x08
|
||||
#define MCR_OUT1 0x04
|
||||
#define MCR_RTS 0x02
|
||||
#define MCR_DTR 0x01
|
||||
|
||||
//
|
||||
// Line Status Register
|
||||
//
|
||||
|
||||
#define LSR_RCV_FIFO 0x80
|
||||
#define LSR_THRE 0x40
|
||||
#define LSR_TXRDY 0x20
|
||||
#define LSR_BI 0x10
|
||||
#define LSR_FE 0x08
|
||||
#define LSR_PE 0x04
|
||||
#define LSR_OE 0x02
|
||||
#define LSR_RXRDY 0x01
|
||||
#define LSR_RCV_MASK 0x1F
|
||||
|
||||
//
|
||||
// Modem Status Register
|
||||
//
|
||||
|
||||
#define MSR_DCD 0x80
|
||||
#define MSR_RI 0x40
|
||||
#define MSR_DSR 0x20
|
||||
#define MSR_CTS 0x10
|
||||
#define MSR_DDCD 0x08
|
||||
#define MSR_TERI 0x04
|
||||
#define MSR_DDSR 0x02
|
||||
#define MSR_DCTS 0x01
|
||||
|
||||
/*! \fn vvoid HAL_FB_UART_Init(UartHandler *ptrObj)
|
||||
* \brief Initialize UART implemented in FPGA
|
||||
*
|
||||
* \param ptrObj Pointer to UART handler structure
|
||||
* \return status
|
||||
*/
|
||||
//HAL_StatusTypeDef HAL_FB_UART_Init(UartHandler *pxObj);
|
||||
void HAL_FB_UART_Init(UartHandler *pxObj);
|
||||
|
||||
/*! \fn void HAL_FB_UART_Stop(void)
|
||||
* \brief Stop pending RX/TX.
|
||||
*
|
||||
*/
|
||||
void HAL_FB_UART_Stop(void);
|
||||
|
||||
|
||||
/*! \fn void HAL_FB_UART_Tx(int c)
|
||||
* \brief Send byte over UART.
|
||||
*
|
||||
* \param c Byte to transmit over UART
|
||||
*/
|
||||
void HAL_FB_UART_Tx(int c);
|
||||
|
||||
/*! \fn int HAL_FB_UART_Rx(void)
|
||||
* \brief Send byte over UART implemented in FPGA.
|
||||
*
|
||||
* \return Byte read from UART
|
||||
*/
|
||||
int HAL_FB_UART_Rx(void);
|
||||
|
||||
int fb_uart_read(int uartid, ptrdiff_t buf, size_t len);
|
||||
|
||||
#endif /* !__EOSS3_HAL_FB_UART_H_ */
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/*
|
||||
* ==========================================================
|
||||
*
|
||||
* Copyright (C) 2020 QuickLogic Corporation
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* File : eoss3_hal_leds.h
|
||||
* Purpose :
|
||||
*
|
||||
* ===========================================================
|
||||
*
|
||||
*/
|
||||
#ifndef _leds_h
|
||||
#define _leds_h
|
||||
|
||||
void LedGreenOn(void);
|
||||
void LedGreenOff(void);
|
||||
|
||||
void LedBlueOn(void);
|
||||
void LedBlueOff(void);
|
||||
|
||||
void LedOrangeOn_AutoOff(void);
|
||||
void LedOrangeOn(void);
|
||||
void LedOrangeOff(void);
|
||||
|
||||
void LedYellowOn(void);
|
||||
void LedYellowOff(void);
|
||||
void LedYellowBlink(void);
|
||||
|
||||
void turnOnLeds(uint8_t on);
|
||||
|
||||
#endif /* !_leds_h */
|
||||
Loading…
Reference in New Issue