s32: build sources for S32Z27 devices

Add necessary CMake files to build bare-metal drivers and their default
configuration.

Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Arguelles 2022-09-19 14:56:00 +07:00 committed by Mahesh Mahadevan
parent 145eb418f8
commit a12fada9f1
10 changed files with 81 additions and 1 deletions

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@ -1,7 +1,12 @@
# Copyright 2022 NXP
# Set the SoC specific drivers and configuration to build
message(FATAL_ERROR "SoC ${CONFIG_SOC} not supported")
if(${CONFIG_SOC} STREQUAL "s32z27")
set(SOC_BASE ${CONFIG_SOC})
set(DRIVERS_BASE s32ze)
else()
message(FATAL_ERROR "SoC ${CONFIG_SOC} not supported")
endif()
add_subdirectory(drivers/${DRIVERS_BASE})
add_subdirectory(soc/${SOC_BASE})

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@ -0,0 +1,10 @@
# Copyright 2022 NXP
# SPDX-License-Identifier: BSD-3-Clause
zephyr_include_directories(header)
zephyr_include_directories(include)
zephyr_library_sources(src/OsIf_Interrupts.c)
zephyr_library_sources(src/OsIf_Timer.c)
zephyr_library_sources(src/OsIf_Timer_System.c)
zephyr_library_sources(src/OsIf_Timer_System_Internal_GenericTimer.c)
zephyr_library_sources(src/OsIf_Timer_System_Internal_Systick.c)

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@ -0,0 +1,10 @@
# Copyright 2022 NXP
# SPDX-License-Identifier: BSD-3-Clause
add_subdirectory(BaseNXP)
add_subdirectory_ifdef(CONFIG_GPIO_S32 Dio)
add_subdirectory_ifdef(CONFIG_EIRQ_S32 Icu)
add_subdirectory(Mcu)
add_subdirectory_ifdef(CONFIG_PINCTRL_S32 Port)
add_subdirectory(Rte)
add_subdirectory_ifdef(CONFIG_UART_S32_LINFLEXD Uart)

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@ -0,0 +1,5 @@
# Copyright 2022 NXP
# SPDX-License-Identifier: BSD-3-Clause
zephyr_include_directories(include)
zephyr_library_sources(src/Siul2_Dio_Ip.c)

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@ -0,0 +1,6 @@
# Copyright 2022 NXP
# SPDX-License-Identifier: BSD-3-Clause
zephyr_include_directories(include)
zephyr_library_sources(src/Siul2_Icu_Ip.c)
zephyr_library_sources(src/Siul2_Icu_Ip_Irq.c)

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@ -0,0 +1,19 @@
# Copyright 2022 NXP
# SPDX-License-Identifier: BSD-3-Clause
zephyr_include_directories(include)
zephyr_library_sources(src/Clock_Ip.c)
zephyr_library_sources(src/Clock_Ip_Data.c)
zephyr_library_sources(src/Clock_Ip_Divider.c)
zephyr_library_sources(src/Clock_Ip_DividerTrigger.c)
zephyr_library_sources(src/Clock_Ip_ExtOsc.c)
zephyr_library_sources(src/Clock_Ip_FracDiv.c)
zephyr_library_sources(src/Clock_Ip_Frequency.c)
zephyr_library_sources(src/Clock_Ip_Gate.c)
zephyr_library_sources(src/Clock_Ip_IntOsc.c)
zephyr_library_sources(src/Clock_Ip_Irq.c)
zephyr_library_sources(src/Clock_Ip_Monitor.c)
zephyr_library_sources(src/Clock_Ip_Pll.c)
zephyr_library_sources(src/Clock_Ip_ProgFreqSwitch.c)
zephyr_library_sources(src/Clock_Ip_Selector.c)
zephyr_library_sources(src/Clock_Ip_Specific.c)

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@ -0,0 +1,5 @@
# Copyright 2022 NXP
# SPDX-License-Identifier: BSD-3-Clause
zephyr_include_directories(include)
zephyr_library_sources(src/Siul2_Port_Ip.c)

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@ -0,0 +1,9 @@
# Copyright 2022 NXP
# SPDX-License-Identifier: BSD-3-Clause
zephyr_include_directories(include)
zephyr_library_sources_ifdef(CONFIG_GPIO_S32 src/SchM_Dio.c)
zephyr_library_sources_ifdef(CONFIG_EIRQ_S32 src/SchM_Icu.c)
zephyr_library_sources(src/SchM_Mcu.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_S32 src/SchM_Port.c)
zephyr_library_sources_ifdef(CONFIG_UART_S32_LINFLEXD src/SchM_Uart.c)

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@ -0,0 +1,6 @@
# Copyright 2022 NXP
# SPDX-License-Identifier: BSD-3-Clause
zephyr_include_directories(include)
zephyr_library_sources(src/Linflexd_Uart_Ip.c)
zephyr_library_sources(src/Linflexd_Uart_Ip_Irq.c)

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@ -0,0 +1,5 @@
zephyr_include_directories(include)
zephyr_library_sources(
src/Clock_Ip_Cfg.c
)