devices: MIMX8UD7: add header and source files for HIFI4 DSP core
Add header and source files for 8ULP's HIFI4 DSP core. Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit is contained in:
Laurentiu Mihalcea
Mahesh Mahadevan
parent
fca2c47e87
commit
6e08dbfcef
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/*
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** ###################################################################
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** Version: rev. 5.0, 2023-04-27
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** Build: b240228
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**
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** Abstract:
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** Chip specific module features.
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2024 NXP
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2020-05-25)
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** Initial version.
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** - rev. 2.0 (2020-09-18)
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** Base on rev A RM
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** - rev. 3.0 (2021-01-20)
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** Base on rev A.1 RM
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** - rev. 4.0 (2021-07-05)
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** Base on rev B RM
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** - rev. 5.0 (2023-04-27)
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** Base on rev D RM
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**
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** ###################################################################
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*/
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#ifndef _MIMX8UD7_dsp1_FEATURES_H_
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#define _MIMX8UD7_dsp1_FEATURES_H_
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/* SOC module features */
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/* @brief ACMP availability on the SoC. */
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#define FSL_FEATURE_SOC_ACMP_COUNT (2)
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/* @brief AXBS availability on the SoC. */
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#define FSL_FEATURE_SOC_AXBS_COUNT (2)
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/* @brief BBNSM availability on the SoC. */
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#define FSL_FEATURE_SOC_BBNSM_COUNT (1)
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/* @brief CACHE64_CTRL availability on the SoC. */
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#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (2)
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/* @brief CASPER availability on the SoC. */
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#define FSL_FEATURE_SOC_CASPER_COUNT (1)
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/* @brief CGC availability on the SoC. */
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#define FSL_FEATURE_SOC_CGC_COUNT (3)
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/* @brief CMC availability on the SoC. */
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#define FSL_FEATURE_SOC_CMC_COUNT (3)
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/* @brief DAC12 availability on the SoC. */
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#define FSL_FEATURE_SOC_DAC12_COUNT (2)
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/* @brief EDMA availability on the SoC. */
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#define FSL_FEATURE_SOC_EDMA_COUNT (3)
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/* @brief ENET availability on the SoC. */
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#define FSL_FEATURE_SOC_ENET_COUNT (1)
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/* @brief EPDC availability on the SoC. */
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#define FSL_FEATURE_SOC_EPDC_COUNT (1)
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/* @brief EWM availability on the SoC. */
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#define FSL_FEATURE_SOC_EWM_COUNT (1)
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/* @brief FLEXCAN availability on the SoC. */
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#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
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/* @brief FLEXIO availability on the SoC. */
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#define FSL_FEATURE_SOC_FLEXIO_COUNT (2)
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/* @brief FLEXSPI availability on the SoC. */
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#define FSL_FEATURE_SOC_FLEXSPI_COUNT (3)
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/* @brief I3C availability on the SoC. */
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#define FSL_FEATURE_SOC_I3C_COUNT (3)
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/* @brief I2S availability on the SoC. */
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#define FSL_FEATURE_SOC_I2S_COUNT (8)
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/* @brief ISI availability on the SoC. */
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#define FSL_FEATURE_SOC_ISI_COUNT (1)
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/* @brief LCDIF availability on the SoC. */
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#define FSL_FEATURE_SOC_LCDIF_COUNT (1)
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/* @brief LPADC availability on the SoC. */
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#define FSL_FEATURE_SOC_LPADC_COUNT (2)
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/* @brief LPI2C availability on the SoC. */
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#define FSL_FEATURE_SOC_LPI2C_COUNT (8)
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/* @brief LPIT availability on the SoC. */
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#define FSL_FEATURE_SOC_LPIT_COUNT (2)
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/* @brief LPSPI availability on the SoC. */
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#define FSL_FEATURE_SOC_LPSPI_COUNT (6)
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/* @brief LPTMR availability on the SoC. */
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#define FSL_FEATURE_SOC_LPTMR_COUNT (2)
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/* @brief LPUART availability on the SoC. */
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#define FSL_FEATURE_SOC_LPUART_COUNT (8)
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/* @brief MCM availability on the SoC. */
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#define FSL_FEATURE_SOC_MCM_COUNT (1)
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/* @brief MIPI_CSI2RX availability on the SoC. */
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#define FSL_FEATURE_SOC_MIPI_CSI2RX_COUNT (1)
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/* @brief MIPI_DSI_HOST availability on the SoC. */
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#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (1)
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/* @brief MRT availability on the SoC. */
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#define FSL_FEATURE_SOC_MRT_COUNT (1)
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/* @brief MU availability on the SoC. */
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#define FSL_FEATURE_SOC_MU_COUNT (2)
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/* @brief PCC availability on the SoC. */
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#define FSL_FEATURE_SOC_PCC_COUNT (6)
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/* @brief PDM availability on the SoC. */
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#define FSL_FEATURE_SOC_PDM_COUNT (1)
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/* @brief POWERQUAD availability on the SoC. */
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#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
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/* @brief PXP availability on the SoC. */
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#define FSL_FEATURE_SOC_PXP_COUNT (1)
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/* @brief RGPIO availability on the SoC. */
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#define FSL_FEATURE_SOC_RGPIO_COUNT (6)
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/* @brief SEMA42 availability on the SoC. */
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#define FSL_FEATURE_SOC_SEMA42_COUNT (3)
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/* @brief SIM availability on the SoC. */
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#define FSL_FEATURE_SOC_SIM_COUNT (4)
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/* @brief SPDIF availability on the SoC. */
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#define FSL_FEATURE_SOC_SPDIF_COUNT (1)
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/* @brief SYSPM availability on the SoC. */
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#define FSL_FEATURE_SOC_SYSPM_COUNT (2)
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/* @brief TPM availability on the SoC. */
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#define FSL_FEATURE_SOC_TPM_COUNT (9)
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/* @brief TRGMUX availability on the SoC. */
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#define FSL_FEATURE_SOC_TRGMUX_COUNT (2)
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/* @brief TSTMR availability on the SoC. */
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#define FSL_FEATURE_SOC_TSTMR_COUNT (2)
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/* @brief USBHS availability on the SoC. */
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#define FSL_FEATURE_SOC_USBHS_COUNT (3)
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/* @brief USBHSDCD availability on the SoC. */
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#define FSL_FEATURE_SOC_USBHSDCD_COUNT (2)
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/* @brief USBNC availability on the SoC. */
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#define FSL_FEATURE_SOC_USBNC_COUNT (3)
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/* @brief USBPHY availability on the SoC. */
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#define FSL_FEATURE_SOC_USBPHY_COUNT (2)
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/* @brief USDHC availability on the SoC. */
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#define FSL_FEATURE_SOC_USDHC_COUNT (3)
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/* @brief WDOG availability on the SoC. */
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#define FSL_FEATURE_SOC_WDOG_COUNT (6)
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/* @brief WUU availability on the SoC. */
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#define FSL_FEATURE_SOC_WUU_COUNT (2)
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/* @brief XRDC availability on the SoC. */
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#define FSL_FEATURE_SOC_XRDC_COUNT (1)
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/* LPADC module features */
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/* @brief FIFO availability on the SoC. */
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#define FSL_FEATURE_LPADC_FIFO_COUNT (0)
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/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1)
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/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (1)
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/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (1)
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/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (0)
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/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (0)
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/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
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#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
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/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
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#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
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/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
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#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (0)
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/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
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#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (0)
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/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
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#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (0)
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/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
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/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
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/* @brief Has calibration (bitfield CFG[CALOFS]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
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/* @brief Has offset trim (register OFSTRIM). */
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#define FSL_FEATURE_LPADC_HAS_OFSTRIM (0)
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/* @brief Has Trigger status register. */
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#define FSL_FEATURE_LPADC_HAS_TSTAT (1)
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/* @brief Has power select (bitfield CFG[PWRSEL]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1)
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/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0)
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/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0)
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/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0)
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/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */
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#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)
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/* @brief Conversion averaged bitfiled width. */
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#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3)
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/* @brief Has B side channels. */
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#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1)
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/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */
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#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1)
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/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */
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#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1)
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/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */
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#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (0)
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/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */
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#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1)
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/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */
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#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1)
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/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */
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#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1)
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/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1)
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/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1)
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/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1)
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/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */
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#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2)
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/* AXBS module features */
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/* No feature definitions */
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/* CACHE64_CTRL module features */
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/* @brief Cache Line size in byte. */
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#define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (16)
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/* @brief Cache doesn't support write buffer. */
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#define FSL_FEATURE_CACHE64_CTRL_HAS_NO_WRITE_BUF (1)
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/* CACHEC module features */
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/* @brief L1 ICACHE line size in byte. */
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#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32)
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/* @brief L1 DCACHE line size in byte. */
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#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32)
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/* FLEXCAN module features */
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/* @brief Has more than 64 MBs. */
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#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0)
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/* @brief Message buffer size */
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#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64)
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/* @brief Has doze mode support (register bit field MCR[DOZE]). */
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#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1)
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/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
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#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1)
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/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
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#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
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/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
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#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1)
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/* @brief Instance has extended bit timing register (register CBT). */
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#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1)
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/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
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#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1)
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/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
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#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1)
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/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */
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#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1)
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/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */
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#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1)
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/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
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#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
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/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */
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#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0)
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/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */
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#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0)
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/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */
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#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0)
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/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
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#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1)
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/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */
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#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1)
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/* @brief Has memory error control (register MECR). */
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#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0)
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/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */
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#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1)
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/* @brief Has Pretended Networking mode support. */
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#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1)
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/* @brief Has Enhanced Rx FIFO. */
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#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1)
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/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */
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#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12)
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/* @brief The number of enhanced Rx FIFO filter element registers. */
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#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32)
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/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */
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#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0)
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/* CASPER module features */
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/* @brief Base address of the CASPER dedicated RAM. */
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#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x28420000u)
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/* CMC module features */
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/* @brief Has RSTCNT register */
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#define FSL_FEATURE_CMC_HAS_RSTCNT_REGISTER (0)
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/* @brief Does not have SRAMCTL register */
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#define FSL_FEATURE_CMC_HAS_NO_SRAMCTL_REGISTER (1)
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/* ACMP module features */
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/* @brief Has CMP_C3. */
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#define FSL_FEATURE_ACMP_HAS_C3_REG (1)
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/* @brief Has C0 LINKEN Bit */
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#define FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT (1)
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/* @brief Has C0 OFFSET Bit */
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#define FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT (0)
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/* @brief Has C0 HYSTCTR Bit */
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#define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1)
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/* @brief Has C1 INPSEL Bit */
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#define FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT (0)
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/* @brief Has C1 INNSEL Bit */
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#define FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT (0)
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/* @brief Has C1 DACOE Bit */
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#define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (0)
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/* @brief Has C1 DMODE Bit */
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#define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1)
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/* @brief Has C2 RRE Bit */
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#define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0)
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/* DAC12 module features */
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/* @brief Has no ITRM register. */
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#define FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER (1)
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/* @brief Has hardware trigger. */
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#define FSL_FEATURE_DAC12_HAS_HW_TRIGGER (1)
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/* EDMA module features */
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/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
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#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32)
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/* @brief If 8 bytes transfer supported. */
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#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1)
|
||||
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
|
||||
#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
|
||||
/* @brief If 16 bytes transfer supported. */
|
||||
#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1)
|
||||
/* @brief Total number of DMA channels on all modules. */
|
||||
#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32)
|
||||
/* @brief Has DMA_Error interrupt vector. */
|
||||
#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
|
||||
/* @brief If 64 bytes transfer supported. */
|
||||
#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1)
|
||||
/* @brief Has register access permission. */
|
||||
#define FSL_FEATURE_HAVE_DMA_CONTROL_REGISTER_ACCESS_PERMISSION (1)
|
||||
/* @brief If 128 bytes transfer supported. */
|
||||
#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1)
|
||||
/* @brief whether has prot register */
|
||||
#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0)
|
||||
/* @brief If 128 bytes transfer supported. */
|
||||
#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1)
|
||||
/* @brief whether has MP channel mux */
|
||||
#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0)
|
||||
/* @brief Has register CH_CSR. */
|
||||
#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1)
|
||||
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
|
||||
#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
|
||||
/* @brief If channel clock controlled independently */
|
||||
#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1)
|
||||
/* @brief Has channel mux */
|
||||
#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1)
|
||||
/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */
|
||||
#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (32)
|
||||
/* @brief Instance has channel mux */
|
||||
#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1)
|
||||
/* @brief Has no register bit fields MP_CSR[EBW]. */
|
||||
#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1)
|
||||
/* @brief Has register CH_SBR. */
|
||||
#define FSL_FEATURE_EDMA_HAS_SBR (1)
|
||||
/* @brief If dma has common clock gate */
|
||||
#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (1)
|
||||
/* @brief Has no register bit fields CH_SBR[ATTR]. */
|
||||
#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (0)
|
||||
/* @brief If dma channel IRQ support parameter */
|
||||
#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (1)
|
||||
/* @brief Has register bit field CH_CSR[SWAP]. */
|
||||
#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0)
|
||||
/* @brief NBYTES must be multiple of 8 when using scatter gather. */
|
||||
#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0)
|
||||
/* @brief Instance has register bit field CH_CSR[SWAP]. */
|
||||
#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0)
|
||||
/* @brief NBYTES must be multiple of 8 when using scatter gather. */
|
||||
#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0)
|
||||
/* @brief Has register bit field CH_SBR[INSTR]. */
|
||||
#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0)
|
||||
/* @brief Has register bit fields MP_CSR[GMRC]. */
|
||||
#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1)
|
||||
/* @brief Instance has register bit field CH_SBR[INSTR]. */
|
||||
#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0)
|
||||
/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */
|
||||
#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0)
|
||||
/* @brief Instance has register CH_MATTR. */
|
||||
#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0)
|
||||
/* @brief Has register bit field CH_CSR[SIGNEXT]. */
|
||||
#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0)
|
||||
/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */
|
||||
#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0)
|
||||
/* @brief Has register bit field TCD_CSR[BWC]. */
|
||||
#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1)
|
||||
/* @brief Instance has register bit field TCD_CSR[BWC]. */
|
||||
#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1)
|
||||
/* @brief Has register bit fields TCD_CSR[TMC]. */
|
||||
#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0)
|
||||
/* @brief Instance has register bit fields TCD_CSR[TMC]. */
|
||||
#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0)
|
||||
/* @brief Has no register bit fields CH_SBR[SEC]. */
|
||||
#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0)
|
||||
|
||||
/* EDGELOCK module features */
|
||||
|
||||
/* @brief EDGELOCK availabilty on the soc. */
|
||||
#define FSL_FEATURE_EDGELOCK (1)
|
||||
|
||||
/* ENET module features */
|
||||
|
||||
/* @brief Support Interrupt Coalesce */
|
||||
#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1)
|
||||
/* @brief Queue Size. */
|
||||
#define FSL_FEATURE_ENET_QUEUE (1)
|
||||
/* @brief Has AVB Support. */
|
||||
#define FSL_FEATURE_ENET_HAS_AVB (0)
|
||||
/* @brief Has Timer Pulse Width control. */
|
||||
#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1)
|
||||
/* @brief Has Extend MDIO Support. */
|
||||
#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1)
|
||||
/* @brief Has Additional 1588 Timer Channel Interrupt. */
|
||||
#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0)
|
||||
/* @brief Support Interrupt Coalesce for each instance */
|
||||
#define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (1)
|
||||
/* @brief Queue Size for each instance. */
|
||||
#define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (1)
|
||||
/* @brief Has AVB Support for each instance. */
|
||||
#define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) (0)
|
||||
/* @brief Has Timer Pulse Width control for each instance. */
|
||||
#define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) (1)
|
||||
/* @brief Has Extend MDIO Support for each instance. */
|
||||
#define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1)
|
||||
/* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */
|
||||
#define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0)
|
||||
/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
|
||||
#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1)
|
||||
/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */
|
||||
#define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0)
|
||||
/* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */
|
||||
#define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0)
|
||||
/* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */
|
||||
#define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0)
|
||||
/* @brief ENET Has Extra Clock Gate.(RW610). */
|
||||
#define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0)
|
||||
|
||||
/* EWM module features */
|
||||
|
||||
/* @brief Has clock select (register CLKCTRL). */
|
||||
#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0)
|
||||
/* @brief Has clock prescaler (register CLKPRESCALER). */
|
||||
#define FSL_FEATURE_EWM_HAS_PRESCALER (1)
|
||||
|
||||
/* FLEXIO module features */
|
||||
|
||||
/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
|
||||
#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
|
||||
/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
|
||||
#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
|
||||
/* @brief Has pin input output related registers */
|
||||
#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1)
|
||||
/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
|
||||
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
|
||||
/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
|
||||
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
|
||||
/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
|
||||
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
|
||||
/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
|
||||
#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
|
||||
/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
|
||||
#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
|
||||
/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
|
||||
#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
|
||||
/* @brief Reset value of the FLEXIO_VERID register */
|
||||
#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003)
|
||||
/* @brief Reset value of the FLEXIO_PARAM register */
|
||||
#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808)
|
||||
/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */
|
||||
#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3)
|
||||
|
||||
/* FLEXSPI module features */
|
||||
|
||||
/* @brief FlexSPI AHB buffer count */
|
||||
#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8)
|
||||
/* @brief FlexSPI has no MCR0 ARDFEN bit */
|
||||
#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0)
|
||||
/* @brief FlexSPI has no MCR0 ATDFEN bit */
|
||||
#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0)
|
||||
|
||||
/* RGPIO module features */
|
||||
|
||||
/* @brief Has GPIO attribute checker register (GACR). */
|
||||
#define FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER (0)
|
||||
/* @brief There is ICR registers */
|
||||
#define FSL_FEATURE_RGPIO_HAS_IRQ_CONFIG (1)
|
||||
/* @brief There is PIDR register */
|
||||
#define FSL_FEATURE_RGPIO_HAS_PORT_INPUT_DISABLE (1)
|
||||
|
||||
/* I3C module features */
|
||||
|
||||
/* @brief Has TERM bitfile in MERRWARN register. */
|
||||
#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0)
|
||||
/* @brief SOC has no reset driver. */
|
||||
#define FSL_FEATURE_I3C_HAS_NO_RESET (0)
|
||||
/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */
|
||||
#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0)
|
||||
/* @brief Register SCONFIG do not have IDRAND bitfield. */
|
||||
#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0)
|
||||
/* @brief Register SCONFIG has HDROK bitfield. */
|
||||
#define FSL_FEATURE_I3C_HAS_HDROK (0)
|
||||
/* @brief SOC doesn't support slave IBI/MR/HJ. */
|
||||
#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1)
|
||||
|
||||
/* LCDIF module features */
|
||||
|
||||
/* @brief Support D/CX Pin polarity. */
|
||||
#define FSL_FEATURE_LCDIF_HAS_DBIX_POLARITY (1)
|
||||
/* @brief Has DBI Type C Option. */
|
||||
#define FSL_FEATURE_LCDIF_HAS_TYPEC (1)
|
||||
|
||||
/* LPI2C module features */
|
||||
|
||||
/* @brief Has separate DMA RX and TX requests. */
|
||||
#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
|
||||
|
||||
/* LPIT module features */
|
||||
|
||||
/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
|
||||
#define FSL_FEATURE_LPIT_TIMER_COUNT (4)
|
||||
/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
|
||||
#define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0)
|
||||
/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
|
||||
#define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (1)
|
||||
|
||||
/* LPSPI module features */
|
||||
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) \
|
||||
(((x) == LPSPI0) ? (4) : \
|
||||
(((x) == LPSPI1) ? (4) : \
|
||||
(((x) == LPSPI2) ? (4) : \
|
||||
(((x) == LPSPI3) ? (4) : \
|
||||
(((x) == LPSPI4) ? (16) : \
|
||||
(((x) == LPSPI5) ? (16) : (-1)))))))
|
||||
/* @brief Has separate DMA RX and TX requests. */
|
||||
#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
|
||||
/* @brief Has CCR1 (related to existence of registers CCR1). */
|
||||
#define FSL_FEATURE_LPSPI_HAS_CCR1 (1)
|
||||
/* @brief Has no PCSCFG bit in CFGR1 register */
|
||||
#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0)
|
||||
/* @brief Has no WIDTH bits in TCR register */
|
||||
#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0)
|
||||
|
||||
/* LPTMR module features */
|
||||
|
||||
/* @brief Has shared interrupt handler with another LPTMR module. */
|
||||
#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
|
||||
/* @brief Whether LPTMR counter is 32 bits width. */
|
||||
#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
|
||||
/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
|
||||
#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1)
|
||||
/* @brief Do not has prescaler clock source 0. */
|
||||
#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0)
|
||||
/* @brief Do not has prescaler clock source 1. */
|
||||
#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0)
|
||||
/* @brief Do not has prescaler clock source 2. */
|
||||
#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0)
|
||||
/* @brief Do not has prescaler clock source 3. */
|
||||
#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0)
|
||||
|
||||
/* LPUART module features */
|
||||
|
||||
/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
|
||||
#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
|
||||
/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
|
||||
/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPUART_HAS_FIFO (1)
|
||||
/* @brief Has 32-bit register MODIR */
|
||||
#define FSL_FEATURE_LPUART_HAS_MODIR (1)
|
||||
/* @brief Hardware flow control (RTS, CTS) is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
|
||||
/* @brief Infrared (modulation) is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
|
||||
/* @brief 2 bits long stop bit is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
|
||||
/* @brief If 10-bit mode is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
|
||||
/* @brief If 7-bit mode is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
|
||||
/* @brief Baud rate fine adjustment is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
|
||||
/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
|
||||
/* @brief Baud rate oversampling is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
|
||||
/* @brief Baud rate oversampling is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
|
||||
/* @brief Peripheral type. */
|
||||
#define FSL_FEATURE_LPUART_IS_SCI (1)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8)
|
||||
/* @brief Supports two match addresses to filter incoming frames. */
|
||||
#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
|
||||
/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
|
||||
/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
|
||||
#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
|
||||
/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
|
||||
/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
|
||||
/* @brief Has improved smart card (ISO7816 protocol) support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
|
||||
/* @brief Has local operation network (CEA709.1-B protocol) support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
|
||||
/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
|
||||
#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
|
||||
/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
|
||||
#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
|
||||
/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
|
||||
#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
|
||||
/* @brief Has separate DMA RX and TX requests. */
|
||||
#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
|
||||
/* @brief Has separate RX and TX interrupts. */
|
||||
#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
|
||||
/* @brief Has LPAURT_PARAM. */
|
||||
#define FSL_FEATURE_LPUART_HAS_PARAM (1)
|
||||
/* @brief Has LPUART_VERID. */
|
||||
#define FSL_FEATURE_LPUART_HAS_VERID (1)
|
||||
/* @brief Has LPUART_GLOBAL. */
|
||||
#define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
|
||||
/* @brief Has LPUART_PINCFG. */
|
||||
#define FSL_FEATURE_LPUART_HAS_PINCFG (1)
|
||||
/* @brief Has register MODEM Control. */
|
||||
#define FSL_FEATURE_LPUART_HAS_MCR (0)
|
||||
/* @brief Has register Half Duplex Control. */
|
||||
#define FSL_FEATURE_LPUART_HAS_HDCR (0)
|
||||
/* @brief Has register Timeout. */
|
||||
#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0)
|
||||
|
||||
/* MEMORY module features */
|
||||
|
||||
/* @brief Memory map has offset between subsystems. */
|
||||
#define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (1)
|
||||
|
||||
/* MIPI_CSI2RX module features */
|
||||
|
||||
/* @brief Offset between MIPI CSI controller and CSR in the MIPI CSI subsystem. */
|
||||
#define FSL_FEATURE_CSI2RX_CSR_OFFSET (0x20100)
|
||||
|
||||
/* MIPI_DSI_HOST module features */
|
||||
|
||||
/* @brief Does not have DPHY PLL(DPHY_CM) */
|
||||
#define FSL_FEATURE_MIPI_DSI_HOST_NO_DPHY_PLL (0)
|
||||
/* @brief Support TX ULPS */
|
||||
#define FSL_FEATURE_MIPI_DSI_HOST_HAS_ULPS (1)
|
||||
/* @brief Has control register to enable or disable TX ULPS */
|
||||
#define FSL_FEATURE_MIPI_DSI_HOST_HAS_ULPS_CTRL (0)
|
||||
/* @brief Has pixel-link to DPI remap */
|
||||
#define FSL_FEATURE_MIPI_DSI_HOST_HAS_PXL2DPI (0)
|
||||
|
||||
/* MRT module features */
|
||||
|
||||
/* @brief number of channels. */
|
||||
#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
|
||||
|
||||
/* MU module features */
|
||||
|
||||
/* @brief MU side for current core */
|
||||
#define FSL_FEATURE_MU_SIDE_B (1)
|
||||
/* @brief MU supports reset assert interrupt. CIER0[RAIE] or CR[RAIE] or BCR[RAIE] . */
|
||||
#define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT (1)
|
||||
/* @brief MU supports reset de-assert interrupt. CR[RDIE] or BCR[RDIE]. */
|
||||
#define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT (0)
|
||||
/* @brief MU does not support core status. Register CSSR0 or CSR0. */
|
||||
#define FSL_FEATURE_MU_NO_CORE_STATUS (0)
|
||||
/* @brief MU supports Power-Down mode entry interrupt. CIER0[PDIE] */
|
||||
#define FSL_FEATURE_MU_HAS_PD_INT (1)
|
||||
/* @brief MU supports STOP mode entry interrupt. CIER0[STOPIE] */
|
||||
#define FSL_FEATURE_MU_HAS_STOP_INT (1)
|
||||
/* @brief MU supports WAIT mode entry interrupt. CIER0[WAITIE] */
|
||||
#define FSL_FEATURE_MU_HAS_WAIT_INT (1)
|
||||
/* @brief MU supports HALT mode entry interrupt. CIER0[HALTIE] */
|
||||
#define FSL_FEATURE_MU_HAS_HALT_INT (1)
|
||||
/* @brief MU supports RUN mode entry interrupt. CIER0[RUNIE] */
|
||||
#define FSL_FEATURE_MU_HAS_RUN_INT (1)
|
||||
/* @brief MU supports hardware reset interrupt. CSSR0[HRIP] or CSR0[HRIP]. */
|
||||
#define FSL_FEATURE_MU_HAS_SR_HRIP (1)
|
||||
/* @brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */
|
||||
#define FSL_FEATURE_MU_NO_CLKE (0)
|
||||
/* @brief MU does not support NMI. Register bit CCR0[NMI]. */
|
||||
#define FSL_FEATURE_MU_NO_NMI (0)
|
||||
/* @brief MU does not support core event pending. Register bit SR[CEP]. */
|
||||
#define FSL_FEATURE_MU_NO_CEP (0)
|
||||
/* @brief MU supports reset interrupt. Register bit SR[MURIP]. */
|
||||
#define FSL_FEATURE_MU_HAS_SR_MURIP (1)
|
||||
/* @brief MU has bit CCR0[RSTH]. */
|
||||
#define FSL_FEATURE_MU_HAS_RSTH (1)
|
||||
/* @brief MU has bit CCR0[RSTH] by instance. */
|
||||
#define FSL_FEATURE_MU_HAS_RSTH_BY_INSTANCEn(x) (1)
|
||||
/* @brief MU has bit CCR0[BOOT]. */
|
||||
#define FSL_FEATURE_MU_HAS_BOOT (1)
|
||||
/* @brief MU has bit CCR0[BOOT] by instance. */
|
||||
#define FSL_FEATURE_MU_HAS_BOOT_BY_INSTANCEn(x) (1)
|
||||
/* @brief MU supports MU reset, CR[MUR]. */
|
||||
#define FSL_FEATURE_MU_HAS_MUR (1)
|
||||
/* @brief MU supports hardware reset, CR[HR] or CCR0[HR]. */
|
||||
#define FSL_FEATURE_MU_HAS_HR (1)
|
||||
/* @brief MU supports hardware reset by instance */
|
||||
#define FSL_FEATURE_MU_HAS_HR_BY_INSTANCEn(x) (1)
|
||||
/* @brief The number of general purpose interrupts supported by MU. */
|
||||
#define FSL_FEATURE_MU_GPI_COUNT (4)
|
||||
|
||||
/* PCC module features */
|
||||
|
||||
/* @brief PCC has SAI clock divider. */
|
||||
#define FSL_FEATURE_PCC_HAS_SAI_DIVIDER (0)
|
||||
/* @brief Remove EWM Clock Gate. */
|
||||
#define FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE (1)
|
||||
|
||||
/* PDM module features */
|
||||
|
||||
/* @brief PDM FIFO offset */
|
||||
#define FSL_FEATURE_PDM_FIFO_OFFSET (4)
|
||||
/* @brief PDM Channel Number */
|
||||
#define FSL_FEATURE_PDM_CHANNEL_NUM (8)
|
||||
/* @brief PDM FIFO WIDTH Size */
|
||||
#define FSL_FEATURE_PDM_FIFO_WIDTH (4)
|
||||
/* @brief PDM FIFO DEPTH Size */
|
||||
#define FSL_FEATURE_PDM_FIFO_DEPTH (8)
|
||||
/* @brief PDM has RANGE_CTRL register */
|
||||
#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1)
|
||||
/* @brief PDM Has Low Frequency */
|
||||
#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (0)
|
||||
/* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */
|
||||
#define FSL_FEATURE_PDM_HAS_NO_VADEF (1)
|
||||
/* @brief PDM Has no minimum clkdiv */
|
||||
#define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1)
|
||||
/* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */
|
||||
#define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1)
|
||||
/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */
|
||||
#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0)
|
||||
/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */
|
||||
#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0)
|
||||
/* @brief PDM Has DC_OUT_CTRL */
|
||||
#define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1)
|
||||
/* @brief PDM Has Fixed DC CTRL VALUE. */
|
||||
#define FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED (1)
|
||||
/* @brief PDM Has no independent error IRQ. */
|
||||
#define FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ (1)
|
||||
|
||||
/* PXP module features */
|
||||
|
||||
/* @brief PXP module has dither engine. */
|
||||
#define FSL_FEATURE_PXP_HAS_DITHER (1)
|
||||
/* @brief PXP module supports repeat run */
|
||||
#define FSL_FEATURE_PXP_HAS_EN_REPEAT (0)
|
||||
/* @brief PXP doesn't have CSC */
|
||||
#define FSL_FEATURE_PXP_HAS_NO_CSC2 (0)
|
||||
/* @brief PXP doesn't have LUT */
|
||||
#define FSL_FEATURE_PXP_HAS_NO_LUT (0)
|
||||
/* @brief PXP doesn't have PORTER_DUFF_CTR */
|
||||
#define FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL (1)
|
||||
/* @brief PXP 3.0 version */
|
||||
#define FSL_FEATURE_PXP_V3 (1)
|
||||
/* @brief PXP doesn't have ROT_POS */
|
||||
#define FSL_FEATURE_PXP_HAS_NO_ROT_POS (1)
|
||||
|
||||
/* SAI module features */
|
||||
|
||||
/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */
|
||||
#define FSL_FEATURE_SAI_HAS_FIFO (1)
|
||||
/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
|
||||
#define FSL_FEATURE_SAI_FIFO_COUNTn(x) (16)
|
||||
/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
|
||||
#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \
|
||||
(((x) == SAI0) ? (2) : \
|
||||
(((x) == SAI1) ? (4) : \
|
||||
(((x) == SAI2) ? (2) : \
|
||||
(((x) == SAI3) ? (2) : \
|
||||
(((x) == SAI4) ? (2) : \
|
||||
(((x) == SAI5) ? (4) : \
|
||||
(((x) == SAI6) ? (4) : \
|
||||
(((x) == SAI7) ? (4) : (-1)))))))))
|
||||
/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
|
||||
#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
|
||||
/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
|
||||
#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
|
||||
/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
|
||||
#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
|
||||
/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
|
||||
#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
|
||||
/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
|
||||
#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
|
||||
/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
|
||||
#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
|
||||
/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
|
||||
#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
|
||||
/* @brief Interrupt source number */
|
||||
#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1)
|
||||
/* @brief Has register of MCR. */
|
||||
#define FSL_FEATURE_SAI_HAS_MCR (0)
|
||||
/* @brief Has bit field MICS of the MCR register. */
|
||||
#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1)
|
||||
/* @brief Has register of MDR */
|
||||
#define FSL_FEATURE_SAI_HAS_MDR (0)
|
||||
/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
|
||||
#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1)
|
||||
/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */
|
||||
#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0)
|
||||
/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
|
||||
#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1)
|
||||
/* @brief Support synchronous with another SAI. */
|
||||
#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0)
|
||||
|
||||
/* SEMA42 module features */
|
||||
|
||||
/* @brief Gate counts */
|
||||
#define FSL_FEATURE_SEMA42_GATE_COUNT (16)
|
||||
|
||||
/* TPM module features */
|
||||
|
||||
/* @brief Number of channels. */
|
||||
#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
|
||||
(((x) == TPM0) ? (6) : \
|
||||
(((x) == TPM1) ? (2) : \
|
||||
(((x) == TPM2) ? (2) : \
|
||||
(((x) == TPM3) ? (6) : \
|
||||
(((x) == TPM4) ? (6) : \
|
||||
(((x) == TPM5) ? (2) : \
|
||||
(((x) == TPM6) ? (2) : \
|
||||
(((x) == TPM7) ? (6) : \
|
||||
(((x) == TPM8) ? (6) : (-1))))))))))
|
||||
/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
|
||||
#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
|
||||
/* @brief Has TPM_PARAM. */
|
||||
#define FSL_FEATURE_TPM_HAS_PARAM (1)
|
||||
/* @brief Has TPM_VERID. */
|
||||
#define FSL_FEATURE_TPM_HAS_VERID (1)
|
||||
/* @brief Has TPM_GLOBAL. */
|
||||
#define FSL_FEATURE_TPM_HAS_GLOBAL (1)
|
||||
/* @brief Has TPM_TRIG. */
|
||||
#define FSL_FEATURE_TPM_HAS_TRIG (1)
|
||||
/* @brief Whether TRIG register has effect. */
|
||||
#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \
|
||||
(((x) == TPM0) ? (1) : \
|
||||
(((x) == TPM1) ? (0) : \
|
||||
(((x) == TPM2) ? (0) : \
|
||||
(((x) == TPM3) ? (1) : \
|
||||
(((x) == TPM4) ? (1) : \
|
||||
(((x) == TPM5) ? (0) : \
|
||||
(((x) == TPM6) ? (0) : \
|
||||
(((x) == TPM7) ? (1) : \
|
||||
(((x) == TPM8) ? (1) : (-1))))))))))
|
||||
/* @brief Has counter pause on trigger. */
|
||||
#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
|
||||
/* @brief Has external trigger selection. */
|
||||
#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
|
||||
/* @brief Has TPM_COMBINE register. */
|
||||
#define FSL_FEATURE_TPM_HAS_COMBINE (1)
|
||||
/* @brief Whether COMBINE register has effect. */
|
||||
#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1)
|
||||
/* @brief Has TPM_POL. */
|
||||
#define FSL_FEATURE_TPM_HAS_POL (1)
|
||||
/* @brief Whether POL register has effect. */
|
||||
#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \
|
||||
(((x) == TPM0) ? (1) : \
|
||||
(((x) == TPM1) ? (0) : \
|
||||
(((x) == TPM2) ? (0) : \
|
||||
(((x) == TPM3) ? (1) : \
|
||||
(((x) == TPM4) ? (1) : \
|
||||
(((x) == TPM5) ? (0) : \
|
||||
(((x) == TPM6) ? (0) : \
|
||||
(((x) == TPM7) ? (1) : \
|
||||
(((x) == TPM8) ? (1) : (-1))))))))))
|
||||
/* @brief Has TPM_FILTER register. */
|
||||
#define FSL_FEATURE_TPM_HAS_FILTER (1)
|
||||
/* @brief Whether FILTER register has effect. */
|
||||
#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1)
|
||||
/* @brief Has TPM_QDCTRL register. */
|
||||
#define FSL_FEATURE_TPM_HAS_QDCTRL (1)
|
||||
/* @brief Whether QDCTRL register has effect. */
|
||||
#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1)
|
||||
/* @brief Has pause level select. */
|
||||
#define FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT (1)
|
||||
/* @brief Whether 32 bits counter has effect. */
|
||||
#define FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x) \
|
||||
(((x) == TPM0) ? (0) : \
|
||||
(((x) == TPM1) ? (1) : \
|
||||
(((x) == TPM2) ? (1) : \
|
||||
(((x) == TPM3) ? (0) : \
|
||||
(((x) == TPM4) ? (0) : \
|
||||
(((x) == TPM5) ? (1) : \
|
||||
(((x) == TPM6) ? (1) : \
|
||||
(((x) == TPM7) ? (0) : \
|
||||
(((x) == TPM8) ? (0) : (-1))))))))))
|
||||
|
||||
/* TSTMR module features */
|
||||
|
||||
/* @brief TSTMR clock frequency is 1MHZ. */
|
||||
#define FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ (1)
|
||||
|
||||
/* USBHS module features */
|
||||
|
||||
/* @brief EHCI module instance count */
|
||||
#define FSL_FEATURE_USBHS_EHCI_COUNT (3)
|
||||
/* @brief Number of endpoints supported */
|
||||
#define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
|
||||
|
||||
/* USBPHY module features */
|
||||
|
||||
/* @brief USBPHY contain DCD analog module */
|
||||
#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0)
|
||||
/* @brief USBPHY has register TRIM_OVERRIDE_EN */
|
||||
#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1)
|
||||
/* @brief USBPHY is 28FDSOI */
|
||||
#define FSL_FEATURE_USBPHY_28FDSOI (0)
|
||||
|
||||
/* USDHC module features */
|
||||
|
||||
/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
|
||||
#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0)
|
||||
/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */
|
||||
#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1)
|
||||
/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */
|
||||
#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1)
|
||||
/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
|
||||
#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1)
|
||||
/* @brief USDHC has reset control */
|
||||
#define FSL_FEATURE_USDHC_HAS_RESET (0)
|
||||
/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */
|
||||
#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1)
|
||||
/* @brief If USDHC instance support 8 bit width */
|
||||
#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1)
|
||||
/* @brief If USDHC instance support HS400 mode */
|
||||
#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0)
|
||||
/* @brief If USDHC instance support 1v8 signal */
|
||||
#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1)
|
||||
/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */
|
||||
#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1)
|
||||
/* @brief Has no VSELECT bit in VEND_SPEC register */
|
||||
#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0)
|
||||
/* @brief Has no VS18 bit in HOST_CTRL_CAP register */
|
||||
#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0)
|
||||
|
||||
/* WDOG module features */
|
||||
|
||||
/* @brief Watchdog is available. */
|
||||
#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
|
||||
/* @brief WDOG_CNT can be 32-bit written. */
|
||||
#define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1)
|
||||
|
||||
/* WUU module features */
|
||||
|
||||
/* @brief Has MF register. */
|
||||
#define FSL_FEATURE_WUU_HAS_MF (1)
|
||||
|
||||
#endif /* _MIMX8UD7_dsp1_FEATURES_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMX8UD7CVP08_dsp1
|
||||
** MIMX8UD7DVK08_dsp1
|
||||
** MIMX8UD7DVP08_dsp1
|
||||
**
|
||||
** Compiler: Xtensa Compiler
|
||||
** Reference manual: IMX8ULPRM, Rev. D, December. 2022
|
||||
** Version: rev. 5.0, 2023-04-27
|
||||
** Build: b240228
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2024 NXP
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2020-05-25)
|
||||
** Initial version.
|
||||
** - rev. 2.0 (2020-09-18)
|
||||
** Base on rev A RM
|
||||
** - rev. 3.0 (2021-01-20)
|
||||
** Base on rev A.1 RM
|
||||
** - rev. 4.0 (2021-07-05)
|
||||
** Base on rev B RM
|
||||
** - rev. 5.0 (2023-04-27)
|
||||
** Base on rev D RM
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MIMX8UD7_dsp1
|
||||
* @version 1.0
|
||||
* @date 280224
|
||||
* @brief Device specific configuration file for MIMX8UD7 (implementation file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- Core clock
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInit()
|
||||
---------------------------------------------------------------------------- */
|
||||
static uint32_t getPll0Freq(void)
|
||||
{
|
||||
uint32_t freq;
|
||||
uint32_t mult;
|
||||
uint8_t pll0Multi[] = {0U, 15U, 16U, 20U, 22U, 25U, 30U, 0U};
|
||||
|
||||
if ((CGC_RTD->PLL0CFG & CGC_PLL0CFG_SOURCE_MASK) != 0UL) /* If use FRO24M */
|
||||
{
|
||||
freq = CLK_FRO_192MHZ / 8U;
|
||||
}
|
||||
else /* Use System OSC. */
|
||||
{
|
||||
freq = CLK_XTAL_OSC_CLK;
|
||||
}
|
||||
|
||||
mult = ((CGC_RTD->PLL0CFG & CGC_PLL0CFG_MULT_MASK) >> CGC_PLL0CFG_MULT_SHIFT);
|
||||
freq *= pll0Multi[mult]; /* Multiplier. */
|
||||
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
SystemInitHook();
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemCoreClockUpdate()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t fracValue;
|
||||
uint32_t CGCOUTClock;
|
||||
/* Identify current system clock source. */
|
||||
switch (CGC_RTD->FUSIONCLK & CGC_FUSIONCLK_SCS_MASK)
|
||||
{
|
||||
case CGC_FUSIONCLK_SCS(0):
|
||||
/* FRO clock */
|
||||
CGCOUTClock = CLK_FRO_192MHZ;
|
||||
break;
|
||||
case CGC_FUSIONCLK_SCS(1):
|
||||
/* PLL0 PFD0 */
|
||||
CGCOUTClock = getPll0Freq();
|
||||
fracValue = (CGC_RTD->PLL0PFDCFG & CGC_PLL0PFDCFG_PFD0_MASK) >> CGC_PLL0PFDCFG_PFD0_SHIFT;
|
||||
CGCOUTClock = (uint32_t)(((uint64_t)CGCOUTClock * 18U) / fracValue);
|
||||
break;
|
||||
case CGC_FUSIONCLK_SCS(2):
|
||||
/* PLL0 PFD1 */
|
||||
CGCOUTClock = getPll0Freq();
|
||||
fracValue = (CGC_RTD->PLL0PFDCFG & CGC_PLL0PFDCFG_PFD1_MASK) >> CGC_PLL0PFDCFG_PFD1_SHIFT;
|
||||
CGCOUTClock = (uint32_t)(((uint64_t)CGCOUTClock * 18U) / fracValue);
|
||||
break;
|
||||
case CGC_FUSIONCLK_SCS(3):
|
||||
/* SOSC */
|
||||
CGCOUTClock = CLK_XTAL_OSC_CLK;
|
||||
break;
|
||||
case CGC_FUSIONCLK_SCS(4):
|
||||
/* RTC32K */
|
||||
CGCOUTClock = CLK_RTC_32K_CLK;
|
||||
break;
|
||||
case CGC_FUSIONCLK_SCS(5):
|
||||
/* LVDS */
|
||||
CGCOUTClock = CLK_LVDS_CLK;
|
||||
break;
|
||||
case CGC_FUSIONCLK_SCS(6):
|
||||
/* PLL0 */
|
||||
CGCOUTClock = getPll0Freq();
|
||||
break;
|
||||
default:
|
||||
CGCOUTClock = 0U;
|
||||
break;
|
||||
}
|
||||
/* Divide the CGC output clock to get the Fusion Core clock. */
|
||||
CGCOUTClock /= ((CGC_RTD->FUSIONCLK & CGC_FUSIONCLK_DIVCORE_MASK) >> CGC_FUSIONCLK_DIVCORE_SHIFT) + 1U;
|
||||
/* Update System Core Clock. */
|
||||
SystemCoreClock = CGCOUTClock;
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInitHook()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
__attribute__((weak)) void SystemInitHook(void)
|
||||
{
|
||||
/* Void implementation of the weak function. */
|
||||
}
|
||||
|
|
@ -0,0 +1,114 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMX8UD7CVP08_dsp1
|
||||
** MIMX8UD7DVK08_dsp1
|
||||
** MIMX8UD7DVP08_dsp1
|
||||
**
|
||||
** Compiler: Xtensa Compiler
|
||||
** Reference manual: IMX8ULPRM, Rev. D, December. 2022
|
||||
** Version: rev. 5.0, 2023-04-27
|
||||
** Build: b240228
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2024 NXP
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2020-05-25)
|
||||
** Initial version.
|
||||
** - rev. 2.0 (2020-09-18)
|
||||
** Base on rev A RM
|
||||
** - rev. 3.0 (2021-01-20)
|
||||
** Base on rev A.1 RM
|
||||
** - rev. 4.0 (2021-07-05)
|
||||
** Base on rev B RM
|
||||
** - rev. 5.0 (2023-04-27)
|
||||
** Base on rev D RM
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MIMX8UD7_dsp1
|
||||
* @version 1.0
|
||||
* @date 280224
|
||||
* @brief Device specific configuration file for MIMX8UD7_cm33 (header file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
#ifndef _SYSTEM_MIMX8UD7_dsp1_H_
|
||||
#define _SYSTEM_MIMX8UD7_dsp1_H_ /**< Symbol preventing repeated inclusion */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define DEFAULT_SYSTEM_CLOCK 192000000U /* Default System clock value */
|
||||
#ifndef CLK_XTAL_OSC_CLK
|
||||
#define CLK_XTAL_OSC_CLK 24000000U /* Default XTAL OSC clock */
|
||||
#endif
|
||||
#define CLK_RTC_32K_CLK 32768U /* RTC oscillator 32 kHz (32k_clk) */
|
||||
#define CLK_FRO_192MHZ 192000000U /* FRO 192 MHz (fro_192m) */
|
||||
#define CLK_LPOSC_1MHZ 1000000U /* LPOSC 1 MHz */
|
||||
#ifndef CLK_LVDS_CLK
|
||||
#define CLK_LVDS_CLK 0U /* Default LVDS clock */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief System clock frequency (core clock)
|
||||
*
|
||||
* The system clock frequency supplied to the SysTick timer and the processor
|
||||
* core clock. This variable can be used by the user application to setup the
|
||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||
* query the frequency of the debug timer or configure the trace clock speed
|
||||
* SystemCoreClock is initialized with a correct predefined value.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Typically this function configures the oscillator (PLL) that is part of the
|
||||
* microcontroller device. For systems with variable clock speed it also updates
|
||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||
*/
|
||||
void SystemInit(void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock variable.
|
||||
*
|
||||
* It must be called whenever the core clock is changed during program
|
||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||
* the current core clock.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void);
|
||||
|
||||
/**
|
||||
* @brief SystemInit function hook.
|
||||
*
|
||||
* This weak function allows to call specific initialization code during the
|
||||
* SystemInit() execution.This can be used when an application specific code needs
|
||||
* to be called as close to the reset entry as possible (for example the Multicore
|
||||
* Manager MCMGR_EarlyInit() function call).
|
||||
* NOTE: No global r/w variables can be used in this hook function because the
|
||||
* initialization of these variables happens after this function.
|
||||
*/
|
||||
void SystemInitHook(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SYSTEM_MIMX8UD7_dsp1_H_ */
|
||||
Loading…
Reference in New Issue