dts: s32: add pinmux definitions for S32Z27
Pinmux was autogenerated based on S32Z27 RM Rev1 DraftAJ. Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Arguelles
Mahesh Mahadevan
parent
a12fada9f1
commit
3e36485268
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/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef HAL_NXP_DTS_NXP_S32_S32Z27_BGA400_PINCTRL_H_
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#define HAL_NXP_DTS_NXP_S32_S32Z27_BGA400_PINCTRL_H_
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#include <zephyr/dt-bindings/pinctrl/s32-pinctrl.h>
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/* SIUL2_0 */
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#define PA1_EIRQ_1 S32_PINMUX(0, 1, 0, 69, 2)
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#define PA3_EIRQ_0 S32_PINMUX(0, 3, 0, 68, 2)
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#define PA5_EIRQ_2 S32_PINMUX(0, 5, 0, 70, 2)
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#define PA12_EIRQ_3 S32_PINMUX(0, 12, 0, 71, 2)
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#define PA13_EIRQ_4 S32_PINMUX(0, 13, 0, 72, 2)
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#define PA14_EIRQ_5 S32_PINMUX(0, 14, 0, 73, 2)
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/* LINFLEX_0 */
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#define PA0_LIN_0_TX S32_PINMUX(0, 0, 1, 0, 0)
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#define PA1_LIN_0_RX S32_PINMUX(0, 1, 0, 47, 2)
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/* GTM */
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#define PA0_GTM_000_O S32_PINMUX(0, 0, 2, 0, 0)
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#define PA1_GTM_001_O S32_PINMUX(0, 1, 1, 0, 0)
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#define PA2_GTM_002_O S32_PINMUX(0, 2, 2, 0, 0)
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#define PA3_GTM_003_O S32_PINMUX(0, 3, 1, 0, 0)
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#define PA4_GTM_004_O S32_PINMUX(0, 4, 2, 0, 0)
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#define PA5_GTM_005_O S32_PINMUX(0, 5, 1, 0, 0)
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#define PA6_GTM_006_O S32_PINMUX(0, 6, 2, 0, 0)
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#define PA7_GTM_007_O S32_PINMUX(0, 7, 2, 0, 0)
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#define PA8_GTM_008_O S32_PINMUX(0, 8, 1, 0, 0)
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#define PA9_GTM_009_O S32_PINMUX(0, 9, 1, 0, 0)
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#define PA10_GTM_010_O S32_PINMUX(0, 10, 1, 0, 0)
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#define PA11_GTM_011_O S32_PINMUX(0, 11, 2, 0, 0)
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#define PA12_GTM_012_O S32_PINMUX(0, 12, 2, 0, 0)
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#define PA13_GTM_013_O S32_PINMUX(0, 13, 1, 0, 0)
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#define PA14_GTM_014_O S32_PINMUX(0, 14, 2, 0, 0)
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#define PA14_GTM_A2_3_0_HR S32_PINMUX(0, 14, 3, 0, 0)
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#define PB6_GTM_022_O S32_PINMUX(0, 22, 2, 0, 0)
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#define PB6_GTM_A1_2_1_HR S32_PINMUX(0, 22, 3, 0, 0)
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#define PB7_GTM_023_O S32_PINMUX(0, 23, 1, 0, 0)
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#define PB7_GTM_A1_2_0_HR S32_PINMUX(0, 23, 2, 0, 0)
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#define PD7_GTM_039_O S32_PINMUX(1, 39, 1, 0, 0)
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#define PD9_GTM_040_O S32_PINMUX(1, 41, 2, 0, 0)
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#define PD10_GTM_041_O S32_PINMUX(1, 42, 2, 0, 0)
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#define PD11_GTM_042_O S32_PINMUX(1, 43, 1, 0, 0)
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#define PD12_GTM_043_O S32_PINMUX(1, 44, 2, 0, 0)
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#define PD13_GTM_044_O S32_PINMUX(1, 45, 1, 0, 0)
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#define PD14_GTM_045_O S32_PINMUX(1, 46, 2, 0, 0)
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#define PD15_GTM_046_O S32_PINMUX(1, 47, 4, 0, 0)
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#define PE0_GTM_047_O S32_PINMUX(1, 48, 4, 0, 0)
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#define PE1_GTM_048_O S32_PINMUX(1, 49, 4, 0, 0)
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#define PE2_GTM_049_O S32_PINMUX(1, 50, 3, 0, 0)
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#define PE3_GTM_050_O S32_PINMUX(1, 51, 3, 0, 0)
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#define PE4_GTM_051_O S32_PINMUX(1, 52, 2, 0, 0)
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#define PE5_GTM_052_O S32_PINMUX(1, 53, 2, 0, 0)
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#define PE6_GTM_053_O S32_PINMUX(1, 54, 2, 0, 0)
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#define PE7_GTM_054_O S32_PINMUX(1, 55, 2, 0, 0)
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#define PE8_GTM_055_O S32_PINMUX(1, 56, 2, 0, 0)
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#define PE9_GTM_056_O S32_PINMUX(1, 57, 2, 0, 0)
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#define PE10_GTM_057_O S32_PINMUX(1, 58, 2, 0, 0)
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#define PE11_GTM_058_O S32_PINMUX(1, 59, 2, 0, 0)
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#define PE12_GTM_059_O S32_PINMUX(1, 60, 2, 0, 0)
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#define PE13_GTM_060_O S32_PINMUX(1, 61, 4, 0, 0)
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#define PE14_GTM_061_O S32_PINMUX(1, 62, 4, 0, 0)
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#define PE15_GTM_062_O S32_PINMUX(1, 63, 4, 0, 0)
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#define PF0_GTM_063_O S32_PINMUX(1, 64, 3, 0, 0)
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#define PF1_GTM_064_O S32_PINMUX(1, 65, 3, 0, 0)
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#define PF2_GTM_065_O S32_PINMUX(1, 66, 2, 0, 0)
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#define PF3_GTM_066_O S32_PINMUX(1, 67, 2, 0, 0)
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#define PF4_GTM_067_O S32_PINMUX(1, 68, 2, 0, 0)
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#define PF5_GTM_068_O S32_PINMUX(1, 69, 2, 0, 0)
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#define PF6_GTM_069_O S32_PINMUX(1, 70, 2, 0, 0)
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#define PF7_GTM_070_O S32_PINMUX(1, 71, 2, 0, 0)
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#define PF8_GTM_071_O S32_PINMUX(1, 72, 2, 0, 0)
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#define PF9_GTM_072_O S32_PINMUX(1, 73, 1, 0, 0)
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#define PF10_GTM_073_O S32_PINMUX(1, 74, 1, 0, 0)
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#define PF11_GTM_074_O S32_PINMUX(1, 75, 1, 0, 0)
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#define PH12_GTM_091_O S32_PINMUX(4, 92, 1, 0, 0)
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#define PH13_GTM_092_O S32_PINMUX(4, 93, 2, 0, 0)
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#define PH14_GTM_093_O S32_PINMUX(4, 94, 2, 0, 0)
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#define PH15_GTM_094_O S32_PINMUX(4, 95, 2, 0, 0)
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#define PI0_GTM_095_O S32_PINMUX(4, 96, 2, 0, 0)
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#define PI1_GTM_096_O S32_PINMUX(4, 97, 2, 0, 0)
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#define PI2_GTM_097_O S32_PINMUX(4, 98, 2, 0, 0)
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#define PI3_GTM_098_O S32_PINMUX(4, 99, 2, 0, 0)
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#define PI4_GTM_099_O S32_PINMUX(4, 100, 2, 0, 0)
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#define PI5_GTM_100_O S32_PINMUX(4, 101, 2, 0, 0)
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#define PI6_GTM_101_O S32_PINMUX(4, 102, 2, 0, 0)
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#define PI7_GTM_102_O S32_PINMUX(4, 103, 2, 0, 0)
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#define PI8_GTM_103_O S32_PINMUX(4, 104, 2, 0, 0)
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#define PI9_GTM_104_O S32_PINMUX(4, 105, 2, 0, 0)
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#define PI10_GTM_105_O S32_PINMUX(4, 106, 3, 0, 0)
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#define PI11_GTM_106_O S32_PINMUX(4, 107, 3, 0, 0)
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#define PI12_GTM_107_O S32_PINMUX(4, 108, 6, 0, 0)
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#define PI13_GTM_108_O S32_PINMUX(4, 109, 3, 0, 0)
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#define PI14_GTM_109_O S32_PINMUX(4, 110, 4, 0, 0)
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#define PI15_GTM_110_O S32_PINMUX(4, 111, 2, 0, 0)
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#define PJ0_GTM_111_O S32_PINMUX(4, 112, 5, 0, 0)
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#define PJ1_GTM_112_O S32_PINMUX(4, 113, 3, 0, 0)
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#define PJ2_GTM_113_O S32_PINMUX(4, 114, 5, 0, 0)
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#define PJ3_GTM_114_O S32_PINMUX(4, 115, 4, 0, 0)
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#define PJ4_GTM_115_O S32_PINMUX(4, 116, 4, 0, 0)
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#define PJ5_GTM_116_O S32_PINMUX(4, 117, 4, 0, 0)
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#define PJ6_GTM_117_O S32_PINMUX(4, 118, 2, 0, 0)
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#define PJ7_GTM_118_O S32_PINMUX(4, 119, 1, 0, 0)
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#define PJ8_GTM_119_O S32_PINMUX(4, 120, 2, 0, 0)
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#define PJ9_GTM_120_O S32_PINMUX(4, 121, 1, 0, 0)
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#define PJ10_GTM_121_O S32_PINMUX(4, 122, 1, 0, 0)
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#define PJ11_GTM_122_O S32_PINMUX(4, 123, 2, 0, 0)
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#define PJ12_GTM_123_O S32_PINMUX(4, 124, 1, 0, 0)
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#define PJ13_GTM_124_O S32_PINMUX(4, 125, 3, 0, 0)
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#define PJ14_GTM_125_O S32_PINMUX(4, 126, 1, 0, 0)
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#define PJ15_GTM_126_O S32_PINMUX(4, 127, 2, 0, 0)
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#define PK0_GTM_127_O S32_PINMUX(4, 128, 1, 0, 0)
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#define PK1_GTM_128_O S32_PINMUX(4, 129, 1, 0, 0)
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#define PK2_GTM_129_O S32_PINMUX(4, 130, 1, 0, 0)
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#define PK3_GTM_130_O S32_PINMUX(4, 131, 1, 0, 0)
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#define PK4_GTM_131_O S32_PINMUX(4, 132, 1, 0, 0)
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#define PK5_GTM_132_O S32_PINMUX(4, 133, 1, 0, 0)
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#define PK6_GTM_133_O S32_PINMUX(4, 134, 1, 0, 0)
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#define PK7_GTM_134_O S32_PINMUX(4, 135, 1, 0, 0)
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#define PK8_GTM_135_O S32_PINMUX(4, 136, 1, 0, 0)
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#define PK9_GTM_136_O S32_PINMUX(4, 137, 1, 0, 0)
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#define PK10_GTM_137_O S32_PINMUX(4, 138, 1, 0, 0)
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#define PK11_GTM_138_O S32_PINMUX(4, 139, 1, 0, 0)
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#define PK12_GTM_139_O S32_PINMUX(4, 140, 3, 0, 0)
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#define PK13_GTM_140_O S32_PINMUX(4, 141, 2, 0, 0)
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#define PK14_GTM_141_O S32_PINMUX(4, 142, 3, 0, 0)
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#define PK15_GTM_142_O S32_PINMUX(4, 143, 3, 0, 0)
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#define PL0_GTM_143_O S32_PINMUX(4, 144, 3, 0, 0)
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#define PL1_GTM_144_O S32_PINMUX(4, 145, 3, 0, 0)
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#define PM2_GTM_145_O S32_PINMUX(5, 146, 2, 0, 0)
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#define PM3_GTM_146_O S32_PINMUX(5, 147, 1, 0, 0)
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#define PM4_GTM_147_O S32_PINMUX(5, 148, 2, 0, 0)
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#define PM5_GTM_148_O S32_PINMUX(5, 149, 1, 0, 0)
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#define PM6_GTM_149_O S32_PINMUX(5, 150, 2, 0, 0)
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#define PM7_GTM_150_O S32_PINMUX(5, 151, 1, 0, 0)
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#define PM8_GTM_151_O S32_PINMUX(5, 152, 2, 0, 0)
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#define PM9_GTM_152_O S32_PINMUX(5, 153, 1, 0, 0)
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#define PM10_GTM_153_O S32_PINMUX(5, 154, 2, 0, 0)
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#define PM11_GTM_154_O S32_PINMUX(5, 155, 1, 0, 0)
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#define PM12_GTM_155_O S32_PINMUX(5, 156, 1, 0, 0)
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#define PM13_GTM_156_O S32_PINMUX(5, 157, 2, 0, 0)
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#define PM14_GTM_157_O S32_PINMUX(5, 158, 1, 0, 0)
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#define PM15_GTM_158_O S32_PINMUX(5, 159, 2, 0, 0)
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#define PN0_GTM_159_O S32_PINMUX(5, 160, 1, 0, 0)
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#define PN1_GTM_160_O S32_PINMUX(5, 161, 2, 0, 0)
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#define PN2_GTM_161_O S32_PINMUX(5, 162, 1, 0, 0)
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#define PN3_GTM_162_O S32_PINMUX(5, 163, 1, 0, 0)
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#define PN4_GTM_163_O S32_PINMUX(5, 164, 1, 0, 0)
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#define PN5_GTM_164_O S32_PINMUX(5, 165, 1, 0, 0)
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#define PN6_GTM_165_O S32_PINMUX(5, 166, 1, 0, 0)
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#define PN7_GTM_166_O S32_PINMUX(5, 167, 1, 0, 0)
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#define PN8_GTM_167_O S32_PINMUX(5, 168, 1, 0, 0)
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#define PN9_GTM_168_O S32_PINMUX(5, 169, 1, 0, 0)
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/* FR_0 */
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#define PA0_FR_0_TXE_B_B S32_PINMUX(0, 0, 3, 0, 0)
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#define PA1_FR_0_TXD_B S32_PINMUX(0, 1, 2, 0, 0)
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#define PA2_FR_0_RXD_B S32_PINMUX(0, 2, 0, 39, 2)
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#define PA4_FR_0_DBG0 S32_PINMUX(0, 4, 3, 0, 0)
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#define PA5_FR_0_DBG1 S32_PINMUX(0, 5, 3, 0, 0)
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#define PA6_FR_0_TXE_A_B S32_PINMUX(0, 6, 1, 0, 0)
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#define PA7_FR_0_TXD_A S32_PINMUX(0, 7, 1, 0, 0)
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#define PA8_FR_0_RXD_A S32_PINMUX(0, 8, 0, 38, 2)
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#define PA9_FR_0_DBG2 S32_PINMUX(0, 9, 3, 0, 0)
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#define PA10_FR_0_DBG3 S32_PINMUX(0, 10, 2, 0, 0)
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/* SPI_0 */
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#define PA0_DSPI_0_PCS2 S32_PINMUX(0, 0, 4, 0, 0)
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#define PA1_DSPI_0_PCS3 S32_PINMUX(0, 1, 3, 0, 0)
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#define PA2_DSPI_0_PCS0_O S32_PINMUX(0, 2, 3, 0, 0)
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#define PA2_DSPI_0_PCS0_I S32_PINMUX(0, 2, 0, 3, 2)
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#define PA3_DSPI_0_PCS1 S32_PINMUX(0, 3, 2, 0, 0)
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#define PA6_DSPI_0_SCK_O S32_PINMUX(0, 6, 4, 0, 0)
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#define PA6_DSPI_0_SCK_I S32_PINMUX(0, 6, 0, 4, 2)
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#define PA7_DSPI_0_SIN S32_PINMUX(0, 7, 0, 5, 2)
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#define PA8_DSPI_0_SOUT S32_PINMUX(0, 8, 2, 0, 0)
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#define PA9_DSPI_0_PCS4 S32_PINMUX(0, 9, 2, 0, 0)
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/* EMIOS_1 */
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#define PA0_EMIOS_1_CH6_O S32_PINMUX(0, 0, 5, 0, 0)
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#define PA0_EMIOS_1_CH6_I S32_PINMUX(0, 0, 0, 35, 2)
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#define PA1_EMIOS_1_CH7_O S32_PINMUX(0, 1, 5, 0, 0)
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#define PA1_EMIOS_1_CH7_I S32_PINMUX(0, 1, 0, 36, 2)
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#define PA2_EMIOS_1_CH1_O S32_PINMUX(0, 2, 5, 0, 0)
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#define PA2_EMIOS_1_CH1_I S32_PINMUX(0, 2, 0, 11, 2)
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#define PA3_EMIOS_1_CH2_O S32_PINMUX(0, 3, 4, 0, 0)
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#define PA3_EMIOS_1_CH2_I S32_PINMUX(0, 3, 0, 19, 2)
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#define PA4_EMIOS_1_CH5_O S32_PINMUX(0, 4, 5, 0, 0)
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#define PA4_EMIOS_1_CH5_I S32_PINMUX(0, 4, 0, 34, 2)
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#define PA5_EMIOS_1_CH0_O S32_PINMUX(0, 5, 5, 0, 0)
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#define PA5_EMIOS_1_CH0_I S32_PINMUX(0, 5, 0, 10, 2)
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#define PA6_EMIOS_1_CH3_O S32_PINMUX(0, 6, 6, 0, 0)
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#define PA6_EMIOS_1_CH3_I S32_PINMUX(0, 6, 0, 30, 2)
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#define PA7_EMIOS_1_CH4_O S32_PINMUX(0, 7, 6, 0, 0)
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#define PA7_EMIOS_1_CH4_I S32_PINMUX(0, 7, 0, 33, 2)
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#define PA11_EMIOS_1_CH16_O S32_PINMUX(0, 11, 4, 0, 0)
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#define PA11_EMIOS_1_CH16_I S32_PINMUX(0, 11, 0, 15, 2)
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#define PA12_EMIOS_1_CH23_O S32_PINMUX(0, 12, 5, 0, 0)
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#define PA12_EMIOS_1_CH23_I S32_PINMUX(0, 12, 0, 23, 2)
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#define PA13_EMIOS_1_CH22_O S32_PINMUX(0, 13, 3, 0, 0)
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#define PA13_EMIOS_1_CH22_I S32_PINMUX(0, 13, 0, 22, 2)
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#define PA14_EMIOS_1_CH31_O S32_PINMUX(0, 14, 5, 0, 0)
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#define PA14_EMIOS_1_CH31_I S32_PINMUX(0, 14, 0, 32, 2)
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#define PB6_EMIOS_1_CH18_O S32_PINMUX(0, 22, 5, 0, 0)
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#define PB6_EMIOS_1_CH18_I S32_PINMUX(0, 22, 0, 17, 2)
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#define PB7_EMIOS_1_CH19_O S32_PINMUX(0, 23, 4, 0, 0)
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#define PB7_EMIOS_1_CH19_I S32_PINMUX(0, 23, 0, 18, 2)
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#define PI15_EMIOS_1_CH16_I S32_PINMUX(0, 111, 0, 15, 3)
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#define PJ0_EMIOS_1_CH23_I S32_PINMUX(0, 112, 0, 23, 4)
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#define PJ1_EMIOS_1_CH21_I S32_PINMUX(0, 113, 0, 21, 4)
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#define PJ2_EMIOS_1_CH20_I S32_PINMUX(0, 114, 0, 20, 4)
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#define PJ3_EMIOS_1_CH19_I S32_PINMUX(0, 115, 0, 18, 3)
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#define PJ4_EMIOS_1_CH18_I S32_PINMUX(0, 116, 0, 17, 3)
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#define PJ5_EMIOS_1_CH17_I S32_PINMUX(0, 117, 0, 16, 4)
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#define PJ8_EMIOS_1_CH31_I S32_PINMUX(0, 120, 0, 32, 3)
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#define PJ9_EMIOS_1_CH30_I S32_PINMUX(0, 121, 0, 31, 4)
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#define PJ11_EMIOS_1_CH29_I S32_PINMUX(0, 123, 0, 29, 3)
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#define PJ12_EMIOS_1_CH28_I S32_PINMUX(0, 124, 0, 28, 3)
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#define PJ13_EMIOS_1_CH27_I S32_PINMUX(0, 125, 0, 27, 3)
|
||||
#define PJ14_EMIOS_1_CH26_I S32_PINMUX(0, 126, 0, 26, 3)
|
||||
#define PJ15_EMIOS_1_CH25_I S32_PINMUX(0, 127, 0, 25, 3)
|
||||
#define PK0_EMIOS_1_CH24_I S32_PINMUX(0, 128, 0, 24, 3)
|
||||
#define PK1_EMIOS_1_CH23_I S32_PINMUX(0, 129, 0, 23, 4)
|
||||
#define PK2_EMIOS_1_CH22_I S32_PINMUX(0, 130, 0, 22, 3)
|
||||
#define PK3_EMIOS_1_CH8_I S32_PINMUX(0, 131, 0, 37, 3)
|
||||
#define PK4_EMIOS_1_CH17_I S32_PINMUX(0, 132, 0, 16, 4)
|
||||
#define PK5_EMIOS_1_CH10_I S32_PINMUX(0, 133, 0, 12, 3)
|
||||
#define PK6_EMIOS_1_CH20_I S32_PINMUX(0, 134, 0, 20, 4)
|
||||
#define PK7_EMIOS_1_CH12_I S32_PINMUX(0, 135, 0, 13, 3)
|
||||
#define PK8_EMIOS_1_CH21_I S32_PINMUX(0, 136, 0, 21, 4)
|
||||
#define PK9_EMIOS_1_CH14_I S32_PINMUX(0, 137, 0, 14, 3)
|
||||
#define PK10_EMIOS_1_CH0_I S32_PINMUX(0, 138, 0, 10, 3)
|
||||
#define PK11_EMIOS_1_CH1_I S32_PINMUX(0, 139, 0, 11, 3)
|
||||
#define PK12_EMIOS_1_CH2_I S32_PINMUX(0, 140, 0, 19, 3)
|
||||
#define PK13_EMIOS_1_CH3_I S32_PINMUX(0, 141, 0, 30, 3)
|
||||
#define PK14_EMIOS_1_CH4_I S32_PINMUX(0, 142, 0, 33, 3)
|
||||
#define PK15_EMIOS_1_CH5_I S32_PINMUX(0, 143, 0, 34, 3)
|
||||
#define PL0_EMIOS_1_CH6_I S32_PINMUX(0, 144, 0, 35, 3)
|
||||
#define PL1_EMIOS_1_CH7_I S32_PINMUX(0, 145, 0, 36, 3)
|
||||
|
||||
/* CTU */
|
||||
#define PA0_CTU_EXT_IN S32_PINMUX(0, 0, 0, 2, 2)
|
||||
#define PA8_CTU_EXT_IN S32_PINMUX(0, 8, 0, 2, 3)
|
||||
|
||||
/* EMIOS_0 */
|
||||
#define PA0_EMIOS_0_CH6_I S32_PINMUX(4, 0, 0, 322, 3)
|
||||
#define PA1_EMIOS_0_CH7_I S32_PINMUX(4, 1, 0, 323, 3)
|
||||
#define PA2_EMIOS_0_CH1_I S32_PINMUX(4, 2, 0, 317, 3)
|
||||
#define PA3_EMIOS_0_CH2_I S32_PINMUX(4, 3, 0, 318, 3)
|
||||
#define PA4_EMIOS_0_CH5_I S32_PINMUX(4, 4, 0, 321, 3)
|
||||
#define PA5_EMIOS_0_CH0_I S32_PINMUX(4, 5, 0, 316, 3)
|
||||
#define PA6_EMIOS_0_CH3_I S32_PINMUX(4, 6, 0, 319, 3)
|
||||
#define PA7_EMIOS_0_CH4_I S32_PINMUX(4, 7, 0, 320, 3)
|
||||
#define PA11_EMIOS_0_CH16_I S32_PINMUX(4, 11, 0, 328, 3)
|
||||
#define PA12_EMIOS_0_CH23_I S32_PINMUX(4, 12, 0, 335, 4)
|
||||
#define PA13_EMIOS_0_CH22_I S32_PINMUX(4, 13, 0, 334, 3)
|
||||
#define PA14_EMIOS_0_CH31_I S32_PINMUX(4, 14, 0, 343, 3)
|
||||
#define PB6_EMIOS_0_CH18_I S32_PINMUX(4, 22, 0, 330, 3)
|
||||
#define PB7_EMIOS_0_CH19_I S32_PINMUX(4, 23, 0, 331, 3)
|
||||
#define PI15_EMIOS_0_CH16_O S32_PINMUX(4, 111, 5, 0, 0)
|
||||
#define PI15_EMIOS_0_CH16_I S32_PINMUX(4, 111, 0, 328, 2)
|
||||
#define PJ0_EMIOS_0_CH23_O S32_PINMUX(4, 112, 6, 0, 0)
|
||||
#define PJ0_EMIOS_0_CH23_I S32_PINMUX(4, 112, 0, 335, 2)
|
||||
#define PJ1_EMIOS_0_CH21_O S32_PINMUX(4, 113, 4, 0, 0)
|
||||
#define PJ1_EMIOS_0_CH21_I S32_PINMUX(4, 113, 0, 333, 3)
|
||||
#define PJ2_EMIOS_0_CH20_O S32_PINMUX(4, 114, 6, 0, 0)
|
||||
#define PJ2_EMIOS_0_CH20_I S32_PINMUX(4, 114, 0, 332, 2)
|
||||
#define PJ3_EMIOS_0_CH19_O S32_PINMUX(4, 115, 5, 0, 0)
|
||||
#define PJ3_EMIOS_0_CH19_I S32_PINMUX(4, 115, 0, 331, 2)
|
||||
#define PJ4_EMIOS_0_CH18_O S32_PINMUX(4, 116, 6, 0, 0)
|
||||
#define PJ4_EMIOS_0_CH18_I S32_PINMUX(4, 116, 0, 330, 2)
|
||||
#define PJ5_EMIOS_0_CH17_O S32_PINMUX(4, 117, 5, 0, 0)
|
||||
#define PJ5_EMIOS_0_CH17_I S32_PINMUX(4, 117, 0, 329, 2)
|
||||
#define PJ8_EMIOS_0_CH31_O S32_PINMUX(4, 120, 5, 0, 0)
|
||||
#define PJ8_EMIOS_0_CH31_I S32_PINMUX(4, 120, 0, 343, 2)
|
||||
#define PJ9_EMIOS_0_CH30_O S32_PINMUX(4, 121, 3, 0, 0)
|
||||
#define PJ9_EMIOS_0_CH30_I S32_PINMUX(4, 121, 0, 342, 2)
|
||||
#define PJ11_EMIOS_0_CH29_O S32_PINMUX(4, 123, 4, 0, 0)
|
||||
#define PJ11_EMIOS_0_CH29_I S32_PINMUX(4, 123, 0, 341, 2)
|
||||
#define PJ12_EMIOS_0_CH28_O S32_PINMUX(4, 124, 3, 0, 0)
|
||||
#define PJ12_EMIOS_0_CH28_I S32_PINMUX(4, 124, 0, 340, 2)
|
||||
#define PJ13_EMIOS_0_CH27_O S32_PINMUX(4, 125, 5, 0, 0)
|
||||
#define PJ13_EMIOS_0_CH27_I S32_PINMUX(4, 125, 0, 339, 2)
|
||||
#define PJ14_EMIOS_0_CH26_O S32_PINMUX(4, 126, 3, 0, 0)
|
||||
#define PJ14_EMIOS_0_CH26_I S32_PINMUX(4, 126, 0, 338, 2)
|
||||
#define PJ15_EMIOS_0_CH25_O S32_PINMUX(4, 127, 4, 0, 0)
|
||||
#define PJ15_EMIOS_0_CH25_I S32_PINMUX(4, 127, 0, 337, 2)
|
||||
#define PK0_EMIOS_0_CH24_O S32_PINMUX(4, 128, 2, 0, 0)
|
||||
#define PK0_EMIOS_0_CH24_I S32_PINMUX(4, 128, 0, 336, 2)
|
||||
#define PK1_EMIOS_0_CH23_O S32_PINMUX(4, 129, 2, 0, 0)
|
||||
#define PK1_EMIOS_0_CH23_I S32_PINMUX(4, 129, 0, 335, 3)
|
||||
#define PK2_EMIOS_0_CH22_O S32_PINMUX(4, 130, 2, 0, 0)
|
||||
#define PK2_EMIOS_0_CH22_I S32_PINMUX(4, 130, 0, 334, 2)
|
||||
#define PK3_EMIOS_0_CH8_O S32_PINMUX(4, 131, 2, 0, 0)
|
||||
#define PK3_EMIOS_0_CH8_I S32_PINMUX(4, 131, 0, 324, 2)
|
||||
#define PK4_EMIOS_0_CH17_O S32_PINMUX(4, 132, 2, 0, 0)
|
||||
#define PK4_EMIOS_0_CH17_I S32_PINMUX(4, 132, 0, 329, 3)
|
||||
#define PK5_EMIOS_0_CH10_O S32_PINMUX(4, 133, 3, 0, 0)
|
||||
#define PK5_EMIOS_0_CH10_I S32_PINMUX(4, 133, 0, 325, 2)
|
||||
#define PK6_EMIOS_0_CH20_O S32_PINMUX(4, 134, 3, 0, 0)
|
||||
#define PK6_EMIOS_0_CH20_I S32_PINMUX(4, 134, 0, 332, 3)
|
||||
#define PK7_EMIOS_0_CH12_O S32_PINMUX(4, 135, 3, 0, 0)
|
||||
#define PK7_EMIOS_0_CH12_I S32_PINMUX(4, 135, 0, 326, 2)
|
||||
#define PK8_EMIOS_0_CH21_O S32_PINMUX(4, 136, 3, 0, 0)
|
||||
#define PK8_EMIOS_0_CH21_I S32_PINMUX(4, 136, 0, 333, 2)
|
||||
#define PK9_EMIOS_0_CH14_O S32_PINMUX(4, 137, 3, 0, 0)
|
||||
#define PK9_EMIOS_0_CH14_I S32_PINMUX(4, 137, 0, 327, 2)
|
||||
#define PK10_EMIOS_0_CH0_O S32_PINMUX(4, 138, 3, 0, 0)
|
||||
#define PK10_EMIOS_0_CH0_I S32_PINMUX(4, 138, 0, 316, 2)
|
||||
#define PK11_EMIOS_0_CH1_O S32_PINMUX(4, 139, 2, 0, 0)
|
||||
#define PK11_EMIOS_0_CH1_I S32_PINMUX(4, 139, 0, 317, 2)
|
||||
#define PK12_EMIOS_0_CH2_O S32_PINMUX(4, 140, 4, 0, 0)
|
||||
#define PK12_EMIOS_0_CH2_I S32_PINMUX(4, 140, 0, 318, 2)
|
||||
#define PK13_EMIOS_0_CH3_O S32_PINMUX(4, 141, 3, 0, 0)
|
||||
#define PK13_EMIOS_0_CH3_I S32_PINMUX(4, 141, 0, 319, 2)
|
||||
#define PK14_EMIOS_0_CH4_O S32_PINMUX(4, 142, 4, 0, 0)
|
||||
#define PK14_EMIOS_0_CH4_I S32_PINMUX(4, 142, 0, 320, 2)
|
||||
#define PK15_EMIOS_0_CH5_O S32_PINMUX(4, 143, 4, 0, 0)
|
||||
#define PK15_EMIOS_0_CH5_I S32_PINMUX(4, 143, 0, 321, 2)
|
||||
#define PL0_EMIOS_0_CH6_O S32_PINMUX(4, 144, 4, 0, 0)
|
||||
#define PL0_EMIOS_0_CH6_I S32_PINMUX(4, 144, 0, 322, 2)
|
||||
#define PL1_EMIOS_0_CH7_O S32_PINMUX(4, 145, 4, 0, 0)
|
||||
#define PL1_EMIOS_0_CH7_I S32_PINMUX(4, 145, 0, 323, 2)
|
||||
|
||||
/* I3C_0 */
|
||||
#define PA1_I3C_0_SDA3_O S32_PINMUX(0, 1, 4, 0, 0)
|
||||
#define PA1_I3C_0_SDA3_I S32_PINMUX(0, 1, 0, 46, 2)
|
||||
#define PA4_I3C_0_SDA2_O S32_PINMUX(0, 4, 4, 0, 0)
|
||||
#define PA4_I3C_0_SDA2_I S32_PINMUX(0, 4, 0, 45, 2)
|
||||
#define PA5_I3C_0_SDA1_O S32_PINMUX(0, 5, 4, 0, 0)
|
||||
#define PA5_I3C_0_SDA1_I S32_PINMUX(0, 5, 0, 44, 2)
|
||||
#define PA6_I3C_0_SDA0_O S32_PINMUX(0, 6, 5, 0, 0)
|
||||
#define PA6_I3C_0_SDA0_I S32_PINMUX(0, 6, 0, 43, 2)
|
||||
#define PA7_I3C_0_SCL_O S32_PINMUX(0, 7, 5, 0, 0)
|
||||
#define PA7_I3C_0_SCL_I S32_PINMUX(0, 7, 0, 42, 2)
|
||||
#define PA8_I3C_0_PUR S32_PINMUX(0, 8, 3, 0, 0)
|
||||
|
||||
/* LINFLEX_1 */
|
||||
#define PA2_LIN_1_TX S32_PINMUX(0, 2, 1, 0, 0)
|
||||
#define PA3_LIN_1_RX S32_PINMUX(0, 3, 0, 48, 2)
|
||||
|
||||
/* PSI5_S_0 */
|
||||
#define PA2_PSI5_S_0_TX S32_PINMUX(0, 2, 4, 0, 0)
|
||||
#define PA3_PSI5_S_0_RX S32_PINMUX(0, 3, 0, 59, 2)
|
||||
#define PA5_PSI5_S_0_TXCLK S32_PINMUX(0, 5, 2, 0, 0)
|
||||
#define PB7_PSI5_S_0_TX S32_PINMUX(0, 23, 5, 0, 0)
|
||||
|
||||
/* PSI5_0 */
|
||||
#define PA2_PSI5_0_SDIN0 S32_PINMUX(0, 2, 0, 55, 2)
|
||||
#define PA3_PSI5_0_SDOUT0 S32_PINMUX(0, 3, 3, 0, 0)
|
||||
#define PA6_PSI5_0_SDIN1 S32_PINMUX(0, 6, 0, 56, 2)
|
||||
#define PA7_PSI5_0_SDOUT1 S32_PINMUX(0, 7, 4, 0, 0)
|
||||
#define PA12_PSI5_0_SDIN0 S32_PINMUX(0, 12, 0, 55, 3)
|
||||
|
||||
/* CAN_HUB */
|
||||
#define PA4_CAN_0_TX S32_PINMUX(0, 4, 1, 0, 0)
|
||||
#define PA5_CAN_0_RX S32_PINMUX(3, 5, 0, 512, 2)
|
||||
#define PA12_CAN_0_TX S32_PINMUX(0, 12, 3, 0, 0)
|
||||
#define PA13_CAN_0_RX S32_PINMUX(3, 13, 0, 512, 3)
|
||||
#define PB6_CAN_1_TX S32_PINMUX(0, 22, 1, 0, 0)
|
||||
#define PB7_CAN_1_RX S32_PINMUX(3, 23, 0, 513, 2)
|
||||
#define PE1_CAN_3_TX S32_PINMUX(1, 49, 6, 0, 0)
|
||||
#define PE2_CAN_3_RX S32_PINMUX(3, 50, 0, 515, 3)
|
||||
#define PE3_CAN_4_TX S32_PINMUX(1, 51, 4, 0, 0)
|
||||
#define PE4_CAN_4_RX S32_PINMUX(3, 52, 0, 516, 3)
|
||||
#define PI10_CAN_6_TX S32_PINMUX(4, 106, 4, 0, 0)
|
||||
#define PI11_CAN_6_RX S32_PINMUX(3, 107, 0, 518, 2)
|
||||
#define PI12_CAN_7_TX S32_PINMUX(4, 108, 3, 0, 0)
|
||||
#define PI13_CAN_7_RX S32_PINMUX(3, 109, 0, 519, 2)
|
||||
#define PI14_CAN_8_TX S32_PINMUX(4, 110, 3, 0, 0)
|
||||
#define PI15_CAN_8_RX S32_PINMUX(3, 111, 0, 520, 2)
|
||||
#define PJ0_CAN_3_TX S32_PINMUX(4, 112, 4, 0, 0)
|
||||
#define PJ1_CAN_3_RX S32_PINMUX(3, 113, 0, 515, 5)
|
||||
#define PJ2_CAN_4_TX S32_PINMUX(4, 114, 4, 0, 0)
|
||||
#define PJ3_CAN_4_RX S32_PINMUX(3, 115, 0, 516, 5)
|
||||
#define PJ4_CAN_6_TX S32_PINMUX(4, 116, 5, 0, 0)
|
||||
#define PJ5_CAN_6_RX S32_PINMUX(3, 117, 0, 518, 3)
|
||||
#define PJ6_CAN_7_TX S32_PINMUX(4, 118, 5, 0, 0)
|
||||
#define PJ7_CAN_7_RX S32_PINMUX(3, 119, 0, 519, 3)
|
||||
#define PJ8_CAN_12_TX S32_PINMUX(4, 120, 3, 0, 0)
|
||||
#define PJ9_CAN_12_RX S32_PINMUX(3, 121, 0, 524, 2)
|
||||
#define PJ10_CAN_17_TX S32_PINMUX(4, 122, 3, 0, 0)
|
||||
#define PJ11_CAN_17_RX S32_PINMUX(3, 123, 0, 529, 2)
|
||||
#define PJ13_CAN_2_TX S32_PINMUX(4, 125, 2, 0, 0)
|
||||
#define PJ14_CAN_2_RX S32_PINMUX(3, 126, 0, 514, 3)
|
||||
#define PJ15_CAN_12_TX S32_PINMUX(4, 127, 1, 0, 0)
|
||||
#define PJ15_CAN_18_TX S32_PINMUX(4, 127, 6, 0, 0)
|
||||
#define PK0_CAN_12_RX S32_PINMUX(3, 128, 0, 524, 3)
|
||||
#define PK0_CAN_18_RX S32_PINMUX(3, 128, 0, 530, 2)
|
||||
#define PK1_CAN_19_TX S32_PINMUX(4, 129, 4, 0, 0)
|
||||
#define PK2_CAN_19_RX S32_PINMUX(3, 130, 0, 531, 2)
|
||||
#define PK3_CAN_20_TX S32_PINMUX(4, 131, 3, 0, 0)
|
||||
#define PK4_CAN_20_RX S32_PINMUX(3, 132, 0, 532, 2)
|
||||
#define PK5_CAN_21_TX S32_PINMUX(4, 133, 4, 0, 0)
|
||||
#define PK6_CAN_1_TX S32_PINMUX(4, 134, 4, 0, 0)
|
||||
#define PK7_CAN_1_RX S32_PINMUX(3, 135, 0, 513, 3)
|
||||
#define PK9_CAN_21_RX S32_PINMUX(3, 137, 0, 533, 2)
|
||||
#define PK10_CAN_12_TX S32_PINMUX(4, 138, 2, 0, 0)
|
||||
#define PK10_CAN_6_TX S32_PINMUX(4, 138, 4, 0, 0)
|
||||
#define PK11_CAN_6_RX S32_PINMUX(3, 139, 0, 518, 4)
|
||||
#define PK11_CAN_12_RX S32_PINMUX(3, 139, 0, 524, 4)
|
||||
#define PK12_CAN_7_TX S32_PINMUX(4, 140, 5, 0, 0)
|
||||
#define PK13_CAN_7_RX S32_PINMUX(3, 141, 0, 519, 4)
|
||||
#define PK14_CAN_8_TX S32_PINMUX(4, 142, 5, 0, 0)
|
||||
#define PK15_CAN_8_RX S32_PINMUX(3, 143, 0, 520, 3)
|
||||
#define PM2_CAN_10_TX S32_PINMUX(5, 146, 1, 0, 0)
|
||||
#define PM3_CAN_10_RX S32_PINMUX(3, 147, 0, 522, 2)
|
||||
#define PM4_CAN_11_TX S32_PINMUX(5, 148, 1, 0, 0)
|
||||
#define PM5_CAN_11_RX S32_PINMUX(3, 149, 0, 523, 2)
|
||||
#define PM6_CAN_1_TX S32_PINMUX(5, 150, 5, 0, 0)
|
||||
#define PM7_CAN_1_RX S32_PINMUX(3, 151, 0, 513, 4)
|
||||
#define PM8_CAN_22_TX S32_PINMUX(5, 152, 4, 0, 0)
|
||||
#define PM9_CAN_22_RX S32_PINMUX(3, 153, 0, 534, 2)
|
||||
#define PM10_CAN_13_TX S32_PINMUX(5, 154, 1, 0, 0)
|
||||
#define PM11_CAN_13_RX S32_PINMUX(3, 155, 0, 525, 2)
|
||||
#define PM13_CAN_2_TX S32_PINMUX(5, 157, 4, 0, 0)
|
||||
#define PM14_CAN_2_RX S32_PINMUX(3, 158, 0, 514, 4)
|
||||
#define PM15_CAN_9_TX S32_PINMUX(5, 159, 1, 0, 0)
|
||||
#define PN0_CAN_9_RX S32_PINMUX(3, 160, 0, 521, 2)
|
||||
#define PN1_CAN_5_TX S32_PINMUX(5, 161, 1, 0, 0)
|
||||
#define PN1_CAN_23_TX S32_PINMUX(5, 161, 5, 0, 0)
|
||||
#define PN2_CAN_5_RX S32_PINMUX(3, 162, 0, 517, 3)
|
||||
#define PN2_CAN_23_RX S32_PINMUX(3, 162, 0, 535, 2)
|
||||
#define PN4_CAN_1_TX S32_PINMUX(5, 164, 3, 0, 0)
|
||||
#define PN5_CAN_1_RX S32_PINMUX(3, 165, 0, 513, 5)
|
||||
#define PN6_CAN_2_TX S32_PINMUX(5, 166, 3, 0, 0)
|
||||
#define PN7_CAN_2_RX S32_PINMUX(3, 167, 0, 514, 5)
|
||||
|
||||
/* FR_1 */
|
||||
#define PA6_FR_1_TXE_B_B S32_PINMUX(0, 6, 3, 0, 0)
|
||||
#define PA7_FR_1_TXD_B S32_PINMUX(0, 7, 3, 0, 0)
|
||||
#define PA8_FR_1_RXD_B S32_PINMUX(0, 8, 0, 41, 2)
|
||||
#define PA11_FR_1_DBG0 S32_PINMUX(0, 11, 3, 0, 0)
|
||||
#define PA12_FR_1_DBG1 S32_PINMUX(0, 12, 4, 0, 0)
|
||||
#define PA13_FR_1_DBG2 S32_PINMUX(0, 13, 2, 0, 0)
|
||||
|
||||
/* DEBUG */
|
||||
#define PA8_EVTI_B_0 S32_PINMUX(0, 8, 0, 85, 2)
|
||||
#define PA9_EVTO_B_0 S32_PINMUX(0, 9, 4, 0, 0)
|
||||
|
||||
/* MC_CGM_0 */
|
||||
#define PA9_CLKOUT_0 S32_PINMUX(0, 9, 5, 0, 0)
|
||||
|
||||
/* BOOT */
|
||||
#define PA9_BOOTMOD_0 S32_PINMUX(0, 9, 0, 0, 0)
|
||||
#define PA10_BOOTMOD_1 S32_PINMUX(0, 10, 0, 1, 0)
|
||||
|
||||
/* MISC */
|
||||
#define PA9_TAMPER_IN S32_PINMUX(0, 9, 0, 51, 2)
|
||||
#define PO11_TAMPER_OUT S32_PINMUX(0, 171, 2, 0, 0)
|
||||
|
||||
/* SINC */
|
||||
#define PA10_SINC_MCLK_OUT2 S32_PINMUX(0, 10, 3, 0, 0)
|
||||
#define PA11_SINC_MCLK_OUT0 S32_PINMUX(0, 11, 6, 0, 0)
|
||||
#define PA11_SINC_MCLK_OUT1 S32_PINMUX(0, 11, 7, 0, 0)
|
||||
#define PB7_SINC_MBIT3 S32_PINMUX(0, 23, 0, 63, 2)
|
||||
|
||||
/* MSC_0_DSPI */
|
||||
#define PA11_DSPI_10_PCS0_O S32_PINMUX(0, 11, 1, 0, 0)
|
||||
#define PA11_DSPI_10_PCS0_I S32_PINMUX(0, 11, 0, 9, 2)
|
||||
#define PA12_DSPI_10_PCS1 S32_PINMUX(0, 12, 1, 0, 0)
|
||||
#define PB6_DSPI_10_PCS2 S32_PINMUX(0, 22, 6, 0, 0)
|
||||
|
||||
/* SPI_1 */
|
||||
#define PA11_DSPI_1_PCS4 S32_PINMUX(0, 11, 5, 0, 0)
|
||||
|
||||
/* LINFLEX_2 */
|
||||
#define PA13_LIN_2_TX S32_PINMUX(0, 13, 4, 0, 0)
|
||||
#define PA14_LIN_2_RX S32_PINMUX(0, 14, 0, 50, 2)
|
||||
|
||||
/* LINFLEX_12 */
|
||||
#define PA13_LIN_12_RX S32_PINMUX(0, 13, 0, 49, 2)
|
||||
#define PA14_LIN_12_TX S32_PINMUX(0, 14, 1, 0, 0)
|
||||
|
||||
/* LCU_1 */
|
||||
#define PA14_LCU_1_OUT0 S32_PINMUX(0, 14, 4, 0, 0)
|
||||
#define PB6_LCU_1_OUT8 S32_PINMUX(0, 22, 4, 0, 0)
|
||||
#define PB7_LCU_1_OUT9 S32_PINMUX(0, 23, 3, 0, 0)
|
||||
|
||||
/* NETC */
|
||||
#define PD9_TMR_1588_CLK_O S32_PINMUX(1, 41, 3, 0, 0)
|
||||
#define PD10_ETH_1_MII_TXER S32_PINMUX(1, 42, 1, 0, 0)
|
||||
#define PD10_TMR_1588_CLK_O S32_PINMUX(1, 42, 3, 0, 0)
|
||||
#define PD11_TMR_1588_TRIG1 S32_PINMUX(1, 43, 0, 178, 2)
|
||||
#define PD11_ETH_1_MII_RXER S32_PINMUX(1, 43, 0, 165, 2)
|
||||
#define PD11_ETH_1_RMII_RXER S32_PINMUX(1, 43, 0, 174, 2)
|
||||
#define PD12_TMR_1588_ALARM1 S32_PINMUX(1, 44, 1, 0, 0)
|
||||
#define PD12_TMR_1588_PP1 S32_PINMUX(1, 44, 4, 0, 0)
|
||||
#define PD12_ETH_1_MII_CRS S32_PINMUX(1, 44, 0, 157, 2)
|
||||
#define PD13_TMR_1588_PP2 S32_PINMUX(1, 45, 2, 0, 0)
|
||||
#define PD13_TMR_1588_CLK_O S32_PINMUX(1, 45, 3, 0, 0)
|
||||
#define PD13_ETH_1_MII_COL S32_PINMUX(1, 45, 0, 156, 2)
|
||||
#define PD13_TMR_1588_TRIG2 S32_PINMUX(1, 45, 0, 179, 2)
|
||||
#define PD14_ETH_1_RGMII_TXC S32_PINMUX(1, 46, 1, 0, 0)
|
||||
#define PD15_ETH_1_RGMII_TXCTL S32_PINMUX(1, 47, 1, 0, 0)
|
||||
#define PD15_ETH_1_MII_TXEN S32_PINMUX(1, 47, 2, 0, 0)
|
||||
#define PD15_ETH_1_RMII_TXEN S32_PINMUX(1, 47, 3, 0, 0)
|
||||
#define PD15_ETH_1_RGMII_RXCTL S32_PINMUX(1, 47, 0, 166, 3)
|
||||
#define PE0_ETH_1_RGMII_TXD_0 S32_PINMUX(1, 48, 1, 0, 0)
|
||||
#define PE0_ETH_1_MII_TXD_0 S32_PINMUX(1, 48, 2, 0, 0)
|
||||
#define PE0_ETH_1_RMII_TXD_0 S32_PINMUX(1, 48, 3, 0, 0)
|
||||
#define PE0_ETH_1_RGMII_RXD_0 S32_PINMUX(1, 48, 0, 167, 3)
|
||||
#define PE1_ETH_1_RGMII_TXD_1 S32_PINMUX(1, 49, 1, 0, 0)
|
||||
#define PE1_ETH_1_MII_TXD_1 S32_PINMUX(1, 49, 2, 0, 0)
|
||||
#define PE1_ETH_1_RMII_TXD_1 S32_PINMUX(1, 49, 3, 0, 0)
|
||||
#define PE1_ETH_1_RGMII_RXD_1 S32_PINMUX(1, 49, 0, 168, 3)
|
||||
#define PE2_ETH_1_RGMII_TXD_2 S32_PINMUX(1, 50, 1, 0, 0)
|
||||
#define PE2_ETH_1_MII_TXD_2 S32_PINMUX(1, 50, 2, 0, 0)
|
||||
#define PE2_TMR_1588_PP2 S32_PINMUX(1, 50, 4, 0, 0)
|
||||
#define PE2_ETH_1_RGMII_RXD_2 S32_PINMUX(1, 50, 0, 169, 3)
|
||||
#define PE3_ETH_1_RGMII_TXD_3 S32_PINMUX(1, 51, 1, 0, 0)
|
||||
#define PE3_ETH_1_MII_TXD_3 S32_PINMUX(1, 51, 2, 0, 0)
|
||||
#define PE3_TMR_1588_PP2 S32_PINMUX(1, 51, 5, 0, 0)
|
||||
#define PE3_ETH_1_RGMII_RXD_3 S32_PINMUX(1, 51, 0, 170, 3)
|
||||
#define PE4_ETH_1_RGMII_TST_TXC S32_PINMUX(1, 52, 1, 0, 0)
|
||||
#define PE5_ETH_1_RGMII_TST_TXCTL S32_PINMUX(1, 53, 1, 0, 0)
|
||||
#define PE5_ETH_1_MII_RXDV S32_PINMUX(1, 53, 0, 164, 2)
|
||||
#define PE5_ETH_1_RGMII_RXCTL S32_PINMUX(1, 53, 0, 166, 2)
|
||||
#define PE5_ETH_1_RMII_CRS_DV S32_PINMUX(1, 53, 0, 171, 2)
|
||||
#define PE6_ETH_1_RGMII_TST_TXD_0 S32_PINMUX(1, 54, 1, 0, 0)
|
||||
#define PE6_ETH_1_MII_RXD_0 S32_PINMUX(1, 54, 0, 160, 2)
|
||||
#define PE6_ETH_1_RGMII_RXD_0 S32_PINMUX(1, 54, 0, 167, 2)
|
||||
#define PE6_ETH_1_RMII_RXD_0 S32_PINMUX(1, 54, 0, 172, 2)
|
||||
#define PE7_ETH_1_RGMII_TST_TXD_1 S32_PINMUX(1, 55, 1, 0, 0)
|
||||
#define PE7_ETH_1_MII_RXD_1 S32_PINMUX(1, 55, 0, 161, 2)
|
||||
#define PE7_ETH_1_RGMII_RXD_1 S32_PINMUX(1, 55, 0, 168, 2)
|
||||
#define PE7_ETH_1_RMII_RXD_1 S32_PINMUX(1, 55, 0, 173, 2)
|
||||
#define PE8_ETH_1_RGMII_TST_TXD_2 S32_PINMUX(1, 56, 1, 0, 0)
|
||||
#define PE8_TMR_1588_TRIG1 S32_PINMUX(1, 56, 0, 178, 3)
|
||||
#define PE8_ETH_1_MII_RXD_2 S32_PINMUX(1, 56, 0, 162, 2)
|
||||
#define PE8_ETH_1_RGMII_RXD_2 S32_PINMUX(1, 56, 0, 169, 2)
|
||||
#define PE9_ETH_1_RGMII_TST_TXD_3 S32_PINMUX(1, 57, 1, 0, 0)
|
||||
#define PE9_TMR_1588_TRIG2 S32_PINMUX(1, 57, 0, 179, 3)
|
||||
#define PE9_ETH_1_MII_RXD_3 S32_PINMUX(1, 57, 0, 163, 2)
|
||||
#define PE9_ETH_1_RGMII_RXD_3 S32_PINMUX(1, 57, 0, 170, 2)
|
||||
#define PE10_ETH_MDC_O S32_PINMUX(1, 58, 1, 0, 0)
|
||||
#define PE10_ETH_MDC_I S32_PINMUX(1, 58, 0, 176, 2)
|
||||
#define PE11_ETH_MDIO_O S32_PINMUX(1, 59, 1, 0, 0)
|
||||
#define PE11_ETH_MDIO_I S32_PINMUX(1, 59, 0, 175, 2)
|
||||
#define PE12_ETH_0_RGMII_TXC S32_PINMUX(1, 60, 1, 0, 0)
|
||||
#define PE13_ETH_0_RGMII_TXCTL S32_PINMUX(1, 61, 1, 0, 0)
|
||||
#define PE13_ETH_0_MII_TXEN S32_PINMUX(1, 61, 2, 0, 0)
|
||||
#define PE13_ETH_0_RMII_TXEN S32_PINMUX(1, 61, 3, 0, 0)
|
||||
#define PE13_ETH_0_RGMII_RXCTL S32_PINMUX(1, 61, 0, 147, 3)
|
||||
#define PE14_ETH_0_RGMII_TXD_0 S32_PINMUX(1, 62, 1, 0, 0)
|
||||
#define PE14_ETH_0_MII_TXD_0 S32_PINMUX(1, 62, 2, 0, 0)
|
||||
#define PE14_ETH_0_RMII_TXD_0 S32_PINMUX(1, 62, 3, 0, 0)
|
||||
#define PE14_ETH_0_RGMII_RXD_0 S32_PINMUX(1, 62, 0, 148, 3)
|
||||
#define PE15_ETH_0_RGMII_TXD_1 S32_PINMUX(1, 63, 1, 0, 0)
|
||||
#define PE15_ETH_0_MII_TXD_1 S32_PINMUX(1, 63, 2, 0, 0)
|
||||
#define PE15_ETH_0_RMII_TXD_1 S32_PINMUX(1, 63, 3, 0, 0)
|
||||
#define PE15_ETH_0_RGMII_RXD_1 S32_PINMUX(1, 63, 0, 149, 3)
|
||||
#define PF0_ETH_0_RGMII_TXD_2 S32_PINMUX(1, 64, 1, 0, 0)
|
||||
#define PF0_ETH_0_MII_TXD_2 S32_PINMUX(1, 64, 2, 0, 0)
|
||||
#define PF0_TMR_1588_PP1 S32_PINMUX(1, 64, 4, 0, 0)
|
||||
#define PF0_TMR_1588_ALARM1 S32_PINMUX(1, 64, 5, 0, 0)
|
||||
#define PF0_ETH_0_RGMII_RXD_2 S32_PINMUX(1, 64, 0, 150, 3)
|
||||
#define PF1_ETH_0_RGMII_TXD_3 S32_PINMUX(1, 65, 1, 0, 0)
|
||||
#define PF1_ETH_0_MII_TXD_3 S32_PINMUX(1, 65, 2, 0, 0)
|
||||
#define PF1_TMR_1588_PP2 S32_PINMUX(1, 65, 4, 0, 0)
|
||||
#define PF1_TMR_1588_ALARM2 S32_PINMUX(1, 65, 5, 0, 0)
|
||||
#define PF1_ETH_0_RGMII_RXD_3 S32_PINMUX(1, 65, 0, 151, 3)
|
||||
#define PF2_ETH_0_RGMII_TST_TXC S32_PINMUX(1, 66, 1, 0, 0)
|
||||
#define PF3_ETH_0_RGMII_TST_TXCTL S32_PINMUX(1, 67, 1, 0, 0)
|
||||
#define PF3_ETH_0_MII_RXDV S32_PINMUX(1, 67, 0, 145, 2)
|
||||
#define PF3_ETH_0_RGMII_RXCTL S32_PINMUX(1, 67, 0, 147, 2)
|
||||
#define PF3_ETH_0_RMII_CRS_DV S32_PINMUX(1, 67, 0, 152, 2)
|
||||
#define PF4_ETH_0_RGMII_TST_TXD_0 S32_PINMUX(1, 68, 1, 0, 0)
|
||||
#define PF4_ETH_0_MII_RXD_0 S32_PINMUX(1, 68, 0, 141, 2)
|
||||
#define PF4_ETH_0_RGMII_RXD_0 S32_PINMUX(1, 68, 0, 148, 2)
|
||||
#define PF4_ETH_0_RMII_RXD_0 S32_PINMUX(1, 68, 0, 153, 2)
|
||||
#define PF5_ETH_0_RGMII_TST_TXD_1 S32_PINMUX(1, 69, 1, 0, 0)
|
||||
#define PF5_ETH_0_MII_RXD_1 S32_PINMUX(1, 69, 0, 142, 2)
|
||||
#define PF5_ETH_0_RGMII_RXD_1 S32_PINMUX(1, 69, 0, 149, 2)
|
||||
#define PF5_ETH_0_RMII_RXD_1 S32_PINMUX(1, 69, 0, 154, 2)
|
||||
#define PF6_ETH_0_RGMII_TST_TXD_2 S32_PINMUX(1, 70, 1, 0, 0)
|
||||
#define PF6_TMR_1588_ALARM2 S32_PINMUX(1, 70, 3, 0, 0)
|
||||
#define PF6_TMR_1588_TRIG1 S32_PINMUX(1, 70, 0, 178, 4)
|
||||
#define PF6_ETH_0_MII_RXD_2 S32_PINMUX(1, 70, 0, 143, 2)
|
||||
#define PF6_ETH_0_RGMII_RXD_2 S32_PINMUX(1, 70, 0, 150, 2)
|
||||
#define PF7_ETH_0_RGMII_TST_TXD_3 S32_PINMUX(1, 71, 1, 0, 0)
|
||||
#define PF7_TMR_1588_ALARM1 S32_PINMUX(1, 71, 3, 0, 0)
|
||||
#define PF7_ETH_0_MII_RXD_3 S32_PINMUX(1, 71, 0, 144, 2)
|
||||
#define PF7_ETH_0_RGMII_RXD_3 S32_PINMUX(1, 71, 0, 151, 2)
|
||||
#define PF7_TMR_1588_TRIG2 S32_PINMUX(1, 71, 0, 179, 4)
|
||||
#define PF8_ETH_0_MII_TXER S32_PINMUX(1, 72, 1, 0, 0)
|
||||
#define PF8_TMR_1588_CLK_O S32_PINMUX(1, 72, 3, 0, 0)
|
||||
#define PF9_TMR_1588_TRIG1 S32_PINMUX(1, 73, 0, 178, 5)
|
||||
#define PF9_ETH_0_MII_RXER S32_PINMUX(1, 73, 0, 146, 2)
|
||||
#define PF9_ETH_0_RMII_RXER S32_PINMUX(1, 73, 0, 155, 2)
|
||||
#define PF10_TMR_1588_ALARM1 S32_PINMUX(1, 74, 2, 0, 0)
|
||||
#define PF10_TMR_1588_PP1 S32_PINMUX(1, 74, 3, 0, 0)
|
||||
#define PF10_ETH_0_MII_CRS S32_PINMUX(1, 74, 0, 138, 2)
|
||||
#define PF11_TMR_1588_PP2 S32_PINMUX(1, 75, 2, 0, 0)
|
||||
#define PF11_TMR_1588_CLK_O S32_PINMUX(1, 75, 3, 0, 0)
|
||||
#define PF11_ETH_0_MII_COL S32_PINMUX(1, 75, 0, 137, 2)
|
||||
#define PF11_TMR_1588_TRIG2 S32_PINMUX(1, 75, 0, 179, 5)
|
||||
#define PJ9_TMR_1588_TRIG1 S32_PINMUX(1, 121, 0, 178, 7)
|
||||
|
||||
/* TRGMUX_1 */
|
||||
#define PB6_TRGMUX_1_XIN5 S32_PINMUX(0, 22, 0, 76, 2)
|
||||
|
||||
/* ADC_0 */
|
||||
#define PB6_ADCSAR0_TRG S32_PINMUX(0, 22, 0, 86, 2)
|
||||
#define PB7_ADCSAR0_INJ_TRG S32_PINMUX(0, 23, 0, 87, 2)
|
||||
|
||||
/* ADC_1 */
|
||||
|
||||
/* JTAGC */
|
||||
#define PO10_TDI S32_PINMUX(0, 170, 0, 82, 0)
|
||||
#define PO11_TDO S32_PINMUX(0, 171, 1, 0, 0)
|
||||
#define PO12_TMS_O S32_PINMUX(0, 172, 1, 0, 0)
|
||||
#define PO12_TMS_I S32_PINMUX(0, 172, 0, 83, 0)
|
||||
#define PO13_TCK S32_PINMUX(0, 173, 0, 84, 0)
|
||||
|
||||
/* SIUL2_1 */
|
||||
|
||||
/* SPI_3 */
|
||||
#define PD11_DSPI_3_PCS3 S32_PINMUX(1, 43, 2, 0, 0)
|
||||
#define PD12_DSPI_3_SCK_O S32_PINMUX(1, 44, 3, 0, 0)
|
||||
#define PD12_DSPI_3_SCK_I S32_PINMUX(1, 44, 0, 131, 3)
|
||||
#define PD13_DSPI_3_SIN S32_PINMUX(1, 45, 0, 132, 3)
|
||||
#define PD14_DSPI_3_SOUT S32_PINMUX(1, 46, 3, 0, 0)
|
||||
#define PD15_DSPI_3_PCS0_O S32_PINMUX(1, 47, 5, 0, 0)
|
||||
#define PD15_DSPI_3_PCS0_I S32_PINMUX(1, 47, 0, 130, 3)
|
||||
#define PE0_DSPI_3_PCS1 S32_PINMUX(1, 48, 5, 0, 0)
|
||||
#define PE1_DSPI_3_PCS2 S32_PINMUX(1, 49, 5, 0, 0)
|
||||
|
||||
/* I3C_1 */
|
||||
#define PE7_I3C_1_PUR S32_PINMUX(1, 55, 4, 0, 0)
|
||||
#define PE8_I3C_1_SCL_O S32_PINMUX(1, 56, 3, 0, 0)
|
||||
#define PE8_I3C_1_SCL_I S32_PINMUX(1, 56, 0, 180, 3)
|
||||
#define PE9_I3C_1_SDA0_O S32_PINMUX(1, 57, 3, 0, 0)
|
||||
#define PE9_I3C_1_SDA0_I S32_PINMUX(1, 57, 0, 181, 3)
|
||||
|
||||
/* LINFLEX_4 */
|
||||
#define PD15_LIN_4_TX S32_PINMUX(1, 47, 6, 0, 0)
|
||||
#define PE0_LIN_4_RX S32_PINMUX(1, 48, 0, 186, 3)
|
||||
|
||||
/* LINFLEX_5 */
|
||||
#define PE5_LIN_5_TX S32_PINMUX(1, 53, 4, 0, 0)
|
||||
#define PE6_LIN_5_RX S32_PINMUX(1, 54, 0, 187, 3)
|
||||
|
||||
/* MC_CGM_1 */
|
||||
#define PD7_LFAST_0_EXT_REF_CLK_O S32_PINMUX(1, 39, 2, 0, 0)
|
||||
#define PD7_LFAST_0_EXT_REF_CLK_I S32_PINMUX(1, 39, 0, 207, 2)
|
||||
#define PD9_CLKOUT_1 S32_PINMUX(1, 41, 1, 0, 0)
|
||||
#define PD9_TMR_1588_CLK_I S32_PINMUX(1, 41, 0, 177, 2)
|
||||
#define PD9_ETH_RGMII_REF_CLK S32_PINMUX(1, 41, 0, 136, 2)
|
||||
#define PD10_TMR_1588_CLK_I S32_PINMUX(1, 42, 0, 177, 3)
|
||||
#define PD12_TMR_1588_CLK_I S32_PINMUX(1, 44, 0, 177, 4)
|
||||
#define PD14_ETH_1_TX_CLK S32_PINMUX(1, 46, 0, 158, 2)
|
||||
#define PE4_ETH_1_REF_RMII_CLK S32_PINMUX(1, 52, 4, 0, 0)
|
||||
#define PE4_ETH_1_RX_CLK S32_PINMUX(1, 52, 0, 159, 2)
|
||||
#define PE12_ETH_0_TX_CLK S32_PINMUX(1, 60, 0, 139, 2)
|
||||
#define PF2_ETH_0_REF_RMII_CLK S32_PINMUX(1, 66, 3, 0, 0)
|
||||
#define PF2_ETH_0_RX_CLK S32_PINMUX(1, 66, 0, 140, 2)
|
||||
#define PF8_TMR_1588_CLK_I S32_PINMUX(1, 72, 0, 177, 5)
|
||||
#define PF10_TMR_1588_CLK_I S32_PINMUX(1, 74, 0, 177, 6)
|
||||
|
||||
/* MC_CGM_3 */
|
||||
#define PD8_CLKOUT_4 S32_PINMUX(1, 40, 1, 0, 0)
|
||||
|
||||
/* SPI_4 */
|
||||
#define PE2_DSPI_4_SCK_O S32_PINMUX(1, 50, 5, 0, 0)
|
||||
#define PE2_DSPI_4_SCK_I S32_PINMUX(1, 50, 0, 134, 2)
|
||||
#define PE3_DSPI_4_SIN S32_PINMUX(1, 51, 0, 135, 2)
|
||||
#define PE4_DSPI_4_SOUT S32_PINMUX(1, 52, 3, 0, 0)
|
||||
#define PE5_DSPI_4_PCS0_O S32_PINMUX(1, 53, 3, 0, 0)
|
||||
#define PE5_DSPI_4_PCS0_I S32_PINMUX(1, 53, 0, 133, 2)
|
||||
#define PE6_DSPI_4_PCS1 S32_PINMUX(1, 54, 3, 0, 0)
|
||||
#define PE7_DSPI_4_PCS2 S32_PINMUX(1, 55, 3, 0, 0)
|
||||
|
||||
/* SPI_2 */
|
||||
|
||||
/* SRX_0 */
|
||||
|
||||
/* LINFLEX_3 */
|
||||
|
||||
/* SIUL2_4 */
|
||||
#define PI11_EIRQ_0 S32_PINMUX(4, 107, 0, 357, 2)
|
||||
#define PI13_EIRQ_1 S32_PINMUX(4, 109, 0, 358, 2)
|
||||
#define PJ12_EIRQ_2 S32_PINMUX(4, 124, 0, 359, 2)
|
||||
#define PK4_EIRQ_3 S32_PINMUX(4, 132, 0, 360, 2)
|
||||
#define PK6_EIRQ_4 S32_PINMUX(4, 134, 0, 361, 2)
|
||||
#define PK9_EIRQ_5 S32_PINMUX(4, 137, 0, 362, 2)
|
||||
#define PK11_EIRQ_6 S32_PINMUX(4, 139, 0, 363, 2)
|
||||
#define PK13_EIRQ_7 S32_PINMUX(4, 141, 0, 364, 2)
|
||||
|
||||
/* QUADSPI_0 */
|
||||
#define PH12_QSPI_0_INTA_B S32_PINMUX(4, 92, 0, 292, 2)
|
||||
#define PH13_QSPI_0_CS_A0 S32_PINMUX(4, 93, 1, 0, 0)
|
||||
#define PH14_QSPI_0_DATA_A_O1 S32_PINMUX(4, 94, 1, 0, 0)
|
||||
#define PH15_QSPI_0_DATA_A_O5 S32_PINMUX(4, 95, 1, 0, 0)
|
||||
#define PI0_QSPI_0_DATA_A_O7 S32_PINMUX(4, 96, 1, 0, 0)
|
||||
#define PI1_QSPI_0_DATA_A_O3 S32_PINMUX(4, 97, 1, 0, 0)
|
||||
#define PI2_QSPI_0_CK_A_B S32_PINMUX(4, 98, 1, 0, 0)
|
||||
#define PI3_QSPI_0_CK_A S32_PINMUX(4, 99, 1, 0, 0)
|
||||
#define PI4_QSPI_0_DATA_A_O0 S32_PINMUX(4, 100, 1, 0, 0)
|
||||
#define PI5_QSPI_0_DATA_A_O4 S32_PINMUX(4, 101, 1, 0, 0)
|
||||
#define PI6_QSPI_0_DQS_A_O S32_PINMUX(4, 102, 1, 0, 0)
|
||||
#define PI7_QSPI_0_DATA_A_O6 S32_PINMUX(4, 103, 1, 0, 0)
|
||||
#define PI8_QSPI_0_DATA_A_O2 S32_PINMUX(4, 104, 1, 0, 0)
|
||||
#define PI9_QSPI_0_CS_A1 S32_PINMUX(4, 105, 1, 0, 0)
|
||||
|
||||
/* QUADSPI_1 */
|
||||
#define PI10_QSPI_1_DATA_A_O0 S32_PINMUX(4, 106, 1, 0, 0)
|
||||
#define PI11_QSPI_1_DATA_A_O3 S32_PINMUX(4, 107, 1, 0, 0)
|
||||
#define PI12_QSPI_1_CS_A0 S32_PINMUX(4, 108, 1, 0, 0)
|
||||
#define PI13_QSPI_1_DATA_A_O4 S32_PINMUX(4, 109, 1, 0, 0)
|
||||
#define PI14_QSPI_1_DATA_A_O1 S32_PINMUX(4, 110, 1, 0, 0)
|
||||
#define PI15_QSPI_1_DQS_A_O S32_PINMUX(4, 111, 6, 0, 0)
|
||||
#define PI15_QSPI_1_DQS_A_I S32_PINMUX(4, 111, 0, 295, 2)
|
||||
#define PJ0_QSPI_1_DATA_A_O7 S32_PINMUX(4, 112, 1, 0, 0)
|
||||
#define PJ1_QSPI_1_CK_A S32_PINMUX(4, 113, 1, 0, 0)
|
||||
#define PJ2_QSPI_1_CK_A_B S32_PINMUX(4, 114, 1, 0, 0)
|
||||
#define PJ3_QSPI_1_DATA_A_O5 S32_PINMUX(4, 115, 1, 0, 0)
|
||||
#define PJ4_QSPI_1_DATA_A_O2 S32_PINMUX(4, 116, 1, 0, 0)
|
||||
#define PJ5_QSPI_1_DATA_A_O6 S32_PINMUX(4, 117, 1, 0, 0)
|
||||
#define PJ6_QSPI_1_CS_A1 S32_PINMUX(4, 118, 1, 0, 0)
|
||||
#define PJ7_QSPI_1_INTA_B S32_PINMUX(4, 119, 0, 293, 2)
|
||||
#define PK11_QSPI_1_INTB_B S32_PINMUX(4, 139, 0, 294, 2)
|
||||
#define PK12_QSPI_1_DATA_B_O3 S32_PINMUX(4, 140, 1, 0, 0)
|
||||
#define PK13_QSPI_1_DATA_B_O2 S32_PINMUX(4, 141, 1, 0, 0)
|
||||
#define PK14_QSPI_1_CK_B S32_PINMUX(4, 142, 1, 0, 0)
|
||||
#define PK15_QSPI_1_CS_B0 S32_PINMUX(4, 143, 1, 0, 0)
|
||||
#define PL0_QSPI_1_DATA_B_O1 S32_PINMUX(4, 144, 1, 0, 0)
|
||||
#define PL1_QSPI_1_DATA_B_O0 S32_PINMUX(4, 145, 1, 0, 0)
|
||||
|
||||
/* USDHC */
|
||||
#define PI10_SD_0_CMD_O S32_PINMUX(4, 106, 2, 0, 0)
|
||||
#define PI11_SD_0_D0_O S32_PINMUX(4, 107, 2, 0, 0)
|
||||
#define PI12_SD_0_D1_O S32_PINMUX(4, 108, 2, 0, 0)
|
||||
#define PI13_SD_0_D2_O S32_PINMUX(4, 109, 2, 0, 0)
|
||||
#define PI14_SD_0_D3_O S32_PINMUX(4, 110, 2, 0, 0)
|
||||
#define PI15_SD_0_CLK_O S32_PINMUX(4, 111, 1, 0, 0)
|
||||
#define PI15_SD_0_CLK_I S32_PINMUX(4, 111, 0, 371, 2)
|
||||
#define PJ0_SD_0_D5_O S32_PINMUX(4, 112, 2, 0, 0)
|
||||
#define PJ1_SD_0_D4_O S32_PINMUX(4, 113, 2, 0, 0)
|
||||
#define PJ2_SD_0_D6_O S32_PINMUX(4, 114, 2, 0, 0)
|
||||
#define PJ3_SD_0_D7_O S32_PINMUX(4, 115, 2, 0, 0)
|
||||
#define PJ4_SD_0_RST S32_PINMUX(4, 116, 2, 0, 0)
|
||||
#define PJ5_SD_0_VSELECT S32_PINMUX(4, 117, 2, 0, 0)
|
||||
|
||||
/* SPI_6 */
|
||||
#define PI10_DSPI_6_SCK_O S32_PINMUX(4, 106, 5, 0, 0)
|
||||
#define PI10_DSPI_6_SCK_I S32_PINMUX(4, 106, 0, 305, 2)
|
||||
#define PI11_DSPI_6_SIN S32_PINMUX(4, 107, 0, 306, 2)
|
||||
#define PI12_DSPI_6_SOUT S32_PINMUX(4, 108, 4, 0, 0)
|
||||
#define PI13_DSPI_6_PCS0_O S32_PINMUX(4, 109, 4, 0, 0)
|
||||
#define PI13_DSPI_6_PCS0_I S32_PINMUX(4, 109, 0, 307, 2)
|
||||
#define PI14_DSPI_6_PCS1 S32_PINMUX(4, 110, 5, 0, 0)
|
||||
#define PI15_DSPI_6_PCS2 S32_PINMUX(4, 111, 3, 0, 0)
|
||||
#define PJ6_DSPI_6_PCS3 S32_PINMUX(4, 118, 4, 0, 0)
|
||||
#define PJ7_DSPI_6_PCS4 S32_PINMUX(4, 119, 3, 0, 0)
|
||||
#define PK12_DSPI_6_SCK_O S32_PINMUX(4, 140, 2, 0, 0)
|
||||
#define PK12_DSPI_6_SCK_I S32_PINMUX(4, 140, 0, 305, 3)
|
||||
#define PK13_DSPI_6_SIN S32_PINMUX(4, 141, 0, 306, 3)
|
||||
#define PK14_DSPI_6_SOUT S32_PINMUX(4, 142, 2, 0, 0)
|
||||
#define PK15_DSPI_6_PCS0_O S32_PINMUX(4, 143, 2, 0, 0)
|
||||
#define PK15_DSPI_6_PCS0_I S32_PINMUX(4, 143, 0, 307, 3)
|
||||
#define PL0_DSPI_6_PCS1 S32_PINMUX(4, 144, 2, 0, 0)
|
||||
#define PL1_DSPI_6_PCS2 S32_PINMUX(4, 145, 2, 0, 0)
|
||||
|
||||
/* I3C_2 */
|
||||
#define PI10_I3C_2_SCL_O S32_PINMUX(4, 106, 6, 0, 0)
|
||||
#define PI10_I3C_2_SCL_I S32_PINMUX(4, 106, 0, 311, 2)
|
||||
#define PI11_I3C_2_PUR S32_PINMUX(4, 107, 4, 0, 0)
|
||||
#define PI12_I3C_2_SDA0_O S32_PINMUX(4, 108, 5, 0, 0)
|
||||
#define PI12_I3C_2_SDA0_I S32_PINMUX(4, 108, 0, 312, 2)
|
||||
#define PI13_I3C_2_SDA1_O S32_PINMUX(4, 109, 5, 0, 0)
|
||||
#define PI13_I3C_2_SDA1_I S32_PINMUX(4, 109, 0, 313, 2)
|
||||
#define PI14_I3C_2_SDA2_O S32_PINMUX(4, 110, 6, 0, 0)
|
||||
#define PI14_I3C_2_SDA2_I S32_PINMUX(4, 110, 0, 314, 2)
|
||||
#define PI15_I3C_2_SDA3_O S32_PINMUX(4, 111, 4, 0, 0)
|
||||
#define PI15_I3C_2_SDA3_I S32_PINMUX(4, 111, 0, 315, 2)
|
||||
#define PJ9_I3C_2_PUR S32_PINMUX(4, 121, 5, 0, 0)
|
||||
#define PJ10_I3C_2_SCL_O S32_PINMUX(4, 122, 4, 0, 0)
|
||||
#define PJ10_I3C_2_SCL_I S32_PINMUX(4, 122, 0, 311, 3)
|
||||
#define PJ11_I3C_2_SDA0_O S32_PINMUX(4, 123, 5, 0, 0)
|
||||
#define PJ11_I3C_2_SDA0_I S32_PINMUX(4, 123, 0, 312, 3)
|
||||
|
||||
/* SPI_5 */
|
||||
#define PJ0_DSPI_5_SOUT S32_PINMUX(4, 112, 3, 0, 0)
|
||||
#define PJ1_DSPI_5_SIN S32_PINMUX(4, 113, 0, 303, 2)
|
||||
#define PJ2_DSPI_5_SCK_O S32_PINMUX(4, 114, 3, 0, 0)
|
||||
#define PJ2_DSPI_5_SCK_I S32_PINMUX(4, 114, 0, 302, 2)
|
||||
#define PJ3_DSPI_5_PCS0_O S32_PINMUX(4, 115, 3, 0, 0)
|
||||
#define PJ3_DSPI_5_PCS0_I S32_PINMUX(4, 115, 0, 304, 2)
|
||||
#define PJ4_DSPI_5_PCS1 S32_PINMUX(4, 116, 3, 0, 0)
|
||||
#define PJ5_DSPI_5_PCS2 S32_PINMUX(4, 117, 3, 0, 0)
|
||||
#define PJ6_DSPI_5_PCS3 S32_PINMUX(4, 118, 3, 0, 0)
|
||||
#define PJ7_DSPI_5_PCS4 S32_PINMUX(4, 119, 2, 0, 0)
|
||||
|
||||
/* MC_CGM_4 */
|
||||
#define PJ2_CLKOUT_2 S32_PINMUX(4, 114, 7, 0, 0)
|
||||
|
||||
/* PSI5_1 */
|
||||
#define PJ3_PSI5_1_SDIN0 S32_PINMUX(4, 115, 0, 344, 2)
|
||||
#define PJ4_PSI5_1_SDOUT0 S32_PINMUX(4, 116, 7, 0, 0)
|
||||
#define PJ5_PSI5_1_SDIN1 S32_PINMUX(4, 117, 0, 345, 2)
|
||||
#define PJ6_PSI5_1_SDOUT1 S32_PINMUX(4, 118, 6, 0, 0)
|
||||
#define PJ8_PSI5_1_SDIN0 S32_PINMUX(4, 120, 0, 344, 3)
|
||||
#define PJ9_PSI5_1_SDOUT0 S32_PINMUX(4, 121, 4, 0, 0)
|
||||
#define PJ11_PSI5_1_SDIN1 S32_PINMUX(4, 123, 0, 345, 3)
|
||||
#define PJ12_PSI5_1_SDOUT1 S32_PINMUX(4, 124, 4, 0, 0)
|
||||
#define PJ13_PSI5_1_SDIN2 S32_PINMUX(4, 125, 0, 346, 2)
|
||||
#define PJ14_PSI5_1_SDOUT2 S32_PINMUX(4, 126, 4, 0, 0)
|
||||
#define PJ15_PSI5_1_SDIN3 S32_PINMUX(4, 127, 0, 347, 2)
|
||||
#define PK0_PSI5_1_SDOUT3 S32_PINMUX(4, 128, 3, 0, 0)
|
||||
|
||||
/* LINFLEX_6 */
|
||||
#define PJ8_LIN_6_TX S32_PINMUX(4, 120, 1, 0, 0)
|
||||
#define PJ9_LIN_6_RX S32_PINMUX(4, 121, 0, 256, 2)
|
||||
|
||||
/* LCU_0 */
|
||||
#define PJ8_LCU_0_OUT0 S32_PINMUX(4, 120, 4, 0, 0)
|
||||
#define PJ9_LCU_0_OUT1 S32_PINMUX(4, 121, 2, 0, 0)
|
||||
#define PJ11_LCU_0_OUT2 S32_PINMUX(4, 123, 3, 0, 0)
|
||||
#define PJ12_LCU_0_OUT3 S32_PINMUX(4, 124, 2, 0, 0)
|
||||
#define PJ13_LCU_0_OUT4 S32_PINMUX(4, 125, 4, 0, 0)
|
||||
#define PJ14_LCU_0_OUT5 S32_PINMUX(4, 126, 2, 0, 0)
|
||||
#define PJ15_LCU_0_OUT6 S32_PINMUX(4, 127, 3, 0, 0)
|
||||
#define PK5_LCU_0_OUT7 S32_PINMUX(4, 133, 2, 0, 0)
|
||||
#define PK6_LCU_0_OUT8 S32_PINMUX(4, 134, 2, 0, 0)
|
||||
#define PK7_LCU_0_OUT9 S32_PINMUX(4, 135, 2, 0, 0)
|
||||
#define PK8_LCU_0_OUT10 S32_PINMUX(4, 136, 2, 0, 0)
|
||||
#define PK9_LCU_0_OUT11 S32_PINMUX(4, 137, 2, 0, 0)
|
||||
|
||||
/* PSI5_S_1 */
|
||||
#define PJ10_PSI5_S_1_TXCLK S32_PINMUX(4, 122, 2, 0, 0)
|
||||
#define PK1_PSI5_S_1_TXCLK S32_PINMUX(4, 129, 3, 0, 0)
|
||||
#define PK2_PSI5_S_1_TX S32_PINMUX(4, 130, 3, 0, 0)
|
||||
#define PK3_PSI5_S_1_RX S32_PINMUX(4, 131, 0, 348, 2)
|
||||
|
||||
/* TRGMUX_0 */
|
||||
#define PJ10_TRGMUX_0_XIN5 S32_PINMUX(4, 122, 0, 370, 2)
|
||||
#define PK0_TRGMUX_0_XIN0 S32_PINMUX(4, 128, 0, 365, 2)
|
||||
#define PK1_TRGMUX_0_XIN1 S32_PINMUX(4, 129, 0, 366, 2)
|
||||
#define PK2_TRGMUX_0_XIN2 S32_PINMUX(4, 130, 0, 367, 2)
|
||||
#define PK3_TRGMUX_0_XIN3 S32_PINMUX(4, 131, 0, 368, 2)
|
||||
#define PK4_TRGMUX_0_XIN4 S32_PINMUX(4, 132, 0, 369, 2)
|
||||
#define PK8_TRGMUX_0_XIN5 S32_PINMUX(4, 136, 0, 370, 3)
|
||||
#define PK10_TRGMUX_0_XIN5 S32_PINMUX(4, 138, 0, 370, 4)
|
||||
|
||||
/* LINFLEX_7 */
|
||||
#define PJ11_LIN_7_TX S32_PINMUX(4, 123, 1, 0, 0)
|
||||
#define PJ12_LIN_7_RX S32_PINMUX(4, 124, 0, 257, 2)
|
||||
|
||||
/* SPI_7 */
|
||||
#define PJ12_DSPI_7_PCS1 S32_PINMUX(4, 124, 5, 0, 0)
|
||||
#define PJ13_DSPI_7_SCK_O S32_PINMUX(4, 125, 6, 0, 0)
|
||||
#define PJ13_DSPI_7_SCK_I S32_PINMUX(4, 125, 0, 308, 2)
|
||||
#define PJ14_DSPI_7_SIN S32_PINMUX(4, 126, 0, 309, 2)
|
||||
#define PJ15_DSPI_7_SOUT S32_PINMUX(4, 127, 5, 0, 0)
|
||||
#define PK0_DSPI_7_PCS0_O S32_PINMUX(4, 128, 4, 0, 0)
|
||||
#define PK0_DSPI_7_PCS0_I S32_PINMUX(4, 128, 0, 310, 2)
|
||||
#define PK4_DSPI_7_PCS4 S32_PINMUX(4, 132, 3, 0, 0)
|
||||
#define PK6_DSPI_7_PCS3 S32_PINMUX(4, 134, 5, 0, 0)
|
||||
#define PK8_DSPI_7_PCS2 S32_PINMUX(4, 136, 4, 0, 0)
|
||||
|
||||
/* LINFLEX_8 */
|
||||
#define PJ13_LIN_8_TX S32_PINMUX(4, 125, 1, 0, 0)
|
||||
#define PJ14_LIN_8_RX S32_PINMUX(4, 126, 0, 258, 2)
|
||||
|
||||
/* SRX_1 */
|
||||
#define PK1_SENT_1_CH0_I S32_PINMUX(4, 129, 0, 349, 2)
|
||||
#define PK2_SENT_1_CH1_I S32_PINMUX(4, 130, 0, 350, 2)
|
||||
#define PK3_SENT_1_CH2_I S32_PINMUX(4, 131, 0, 351, 2)
|
||||
#define PK4_SENT_1_CH3_I S32_PINMUX(4, 132, 0, 352, 2)
|
||||
#define PK5_SENT_1_CH4_I S32_PINMUX(4, 133, 0, 353, 2)
|
||||
#define PK6_SENT_1_CH5_I S32_PINMUX(4, 134, 0, 354, 2)
|
||||
#define PK7_SENT_1_CH6_I S32_PINMUX(4, 135, 0, 355, 2)
|
||||
#define PK8_SENT_1_CH7_I S32_PINMUX(4, 136, 0, 356, 2)
|
||||
#define PK10_SENT_1_CH0_I S32_PINMUX(4, 138, 0, 349, 3)
|
||||
#define PK11_SENT_1_CH1_I S32_PINMUX(4, 139, 0, 350, 3)
|
||||
#define PK12_SENT_1_CH2_I S32_PINMUX(4, 140, 0, 351, 3)
|
||||
#define PK13_SENT_1_CH3_I S32_PINMUX(4, 141, 0, 352, 3)
|
||||
#define PK14_SENT_1_CH4_I S32_PINMUX(4, 142, 0, 353, 3)
|
||||
#define PK15_SENT_1_CH5_I S32_PINMUX(4, 143, 0, 354, 3)
|
||||
#define PL0_SENT_1_CH6_I S32_PINMUX(4, 144, 0, 355, 3)
|
||||
#define PL1_SENT_1_CH7_I S32_PINMUX(4, 145, 0, 356, 3)
|
||||
|
||||
/* SIUL2_5 */
|
||||
#define PM3_EIRQ_0 S32_PINMUX(5, 147, 0, 467, 2)
|
||||
#define PM5_EIRQ_1 S32_PINMUX(5, 149, 0, 468, 2)
|
||||
#define PM7_EIRQ_2 S32_PINMUX(5, 151, 0, 469, 2)
|
||||
#define PM9_EIRQ_3 S32_PINMUX(5, 153, 0, 470, 2)
|
||||
#define PN0_EIRQ_4 S32_PINMUX(5, 160, 0, 471, 2)
|
||||
#define PN2_EIRQ_5 S32_PINMUX(5, 162, 0, 472, 2)
|
||||
#define PN5_EIRQ_6 S32_PINMUX(5, 165, 0, 473, 2)
|
||||
#define PN6_EIRQ_7 S32_PINMUX(5, 166, 0, 474, 2)
|
||||
|
||||
/* SPI_9 */
|
||||
#define PM4_DSPI_9_PCS4 S32_PINMUX(5, 148, 3, 0, 0)
|
||||
#define PM5_DSPI_9_PCS3 S32_PINMUX(5, 149, 2, 0, 0)
|
||||
#define PM6_DSPI_9_PCS2 S32_PINMUX(5, 150, 4, 0, 0)
|
||||
#define PM7_DSPI_9_PCS1 S32_PINMUX(5, 151, 3, 0, 0)
|
||||
#define PM13_DSPI_9_SCK_O S32_PINMUX(5, 157, 3, 0, 0)
|
||||
#define PM13_DSPI_9_SCK_I S32_PINMUX(5, 157, 0, 453, 2)
|
||||
#define PM14_DSPI_9_SOUT S32_PINMUX(5, 158, 2, 0, 0)
|
||||
#define PN1_DSPI_9_SIN S32_PINMUX(5, 161, 0, 454, 2)
|
||||
#define PN2_DSPI_9_PCS0_O S32_PINMUX(5, 162, 3, 0, 0)
|
||||
#define PN2_DSPI_9_PCS0_I S32_PINMUX(5, 162, 0, 452, 2)
|
||||
|
||||
/* SPI_8 */
|
||||
#define PM5_DSPI_8_PCS0_O S32_PINMUX(5, 149, 3, 0, 0)
|
||||
#define PM5_DSPI_8_PCS0_I S32_PINMUX(5, 149, 0, 449, 4)
|
||||
#define PM6_DSPI_8_SCK_O S32_PINMUX(5, 150, 3, 0, 0)
|
||||
#define PM6_DSPI_8_SCK_I S32_PINMUX(5, 150, 0, 450, 2)
|
||||
#define PM7_DSPI_8_SOUT S32_PINMUX(5, 151, 2, 0, 0)
|
||||
#define PM8_DSPI_8_SIN S32_PINMUX(5, 152, 0, 451, 2)
|
||||
#define PM9_DSPI_8_PCS0_O S32_PINMUX(5, 153, 2, 0, 0)
|
||||
#define PM9_DSPI_8_PCS0_I S32_PINMUX(5, 153, 0, 449, 2)
|
||||
#define PM15_DSPI_8_PCS1 S32_PINMUX(5, 159, 3, 0, 0)
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#define PN0_DSPI_8_PCS2 S32_PINMUX(5, 160, 2, 0, 0)
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#define PN1_DSPI_8_PCS3 S32_PINMUX(5, 161, 3, 0, 0)
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||||
#define PN2_DSPI_8_PCS4 S32_PINMUX(5, 162, 2, 0, 0)
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||||
#define PN3_DSPI_8_SOUT S32_PINMUX(5, 163, 2, 0, 0)
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||||
#define PN4_DSPI_8_SCK_O S32_PINMUX(5, 164, 2, 0, 0)
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||||
#define PN4_DSPI_8_SCK_I S32_PINMUX(5, 164, 0, 450, 3)
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||||
#define PN5_DSPI_8_SIN S32_PINMUX(5, 165, 0, 451, 3)
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||||
#define PN6_DSPI_8_PCS0_O S32_PINMUX(5, 166, 2, 0, 0)
|
||||
#define PN6_DSPI_8_PCS0_I S32_PINMUX(5, 166, 0, 449, 3)
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||||
#define PN7_DSPI_8_PCS1 S32_PINMUX(5, 167, 2, 0, 0)
|
||||
#define PN8_DSPI_8_PCS2 S32_PINMUX(5, 168, 2, 0, 0)
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#define PN9_DSPI_8_PCS3 S32_PINMUX(5, 169, 2, 0, 0)
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||||
|
||||
/* LINFLEX_9 */
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||||
#define PM6_LIN_9_TX S32_PINMUX(5, 150, 1, 0, 0)
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||||
#define PM7_LIN_9_RX S32_PINMUX(5, 151, 0, 466, 2)
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||||
|
||||
/* LINFLEX_10 */
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||||
#define PM8_LIN_10_TX S32_PINMUX(5, 152, 1, 0, 0)
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||||
#define PM9_LIN_10_RX S32_PINMUX(5, 153, 0, 464, 2)
|
||||
|
||||
/* CANXL_0 */
|
||||
#define PM8_CANXL_0_TX S32_PINMUX(5, 152, 3, 0, 0)
|
||||
#define PM9_CANXL_0_RX S32_PINMUX(5, 153, 0, 462, 2)
|
||||
#define PM12_CANXL_0_RX S32_PINMUX(5, 156, 0, 462, 4)
|
||||
#define PN1_CANXL_0_TX S32_PINMUX(5, 161, 4, 0, 0)
|
||||
#define PN2_CANXL_0_RX S32_PINMUX(5, 162, 0, 462, 3)
|
||||
|
||||
/* CANXL_1 */
|
||||
#define PM10_CANXL_1_TX S32_PINMUX(5, 154, 3, 0, 0)
|
||||
#define PM11_CANXL_1_RX S32_PINMUX(5, 155, 0, 463, 2)
|
||||
|
||||
/* MC_CGM_5 */
|
||||
#define PM12_CLKOUT_3 S32_PINMUX(5, 156, 2, 0, 0)
|
||||
|
||||
/* LINFLEX_11 */
|
||||
#define PM13_LIN_11_TX S32_PINMUX(5, 157, 1, 0, 0)
|
||||
#define PM14_LIN_11_RX S32_PINMUX(5, 158, 0, 465, 2)
|
||||
|
||||
#endif /* HAL_NXP_DTS_NXP_S32_S32Z27_BGA400_PINCTRL_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue