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nrfx: integrate MDK 8.58.0 

Update the MDK in nrfx to version 8.58.0.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
This commit is contained in:
Nikodem Kastelik 2023-10-12 09:41:14 +02:00
parent 275548e2dc
commit ba395a9526
20 changed files with 396 additions and 177 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
nrfx/mdk/nrf.h
View File

@ -37,7 +37,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* MDK version */
#define MDK_MAJOR_VERSION 8
#define MDK_MINOR_VERSION 55
#define MDK_MINOR_VERSION 58
#define MDK_MICRO_VERSION 0

6
nrfx/mdk/nrf51.h
View File

@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n
* @file nrf51.h
* @brief CMSIS HeaderFile
* @version 522
* @date 22. June 2023
* @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:07
* @date 20. September 2023
* @note Generated by SVDConv V3.3.35 on Wednesday, 20.09.2023 12:45:27
* from File 'nrf51.svd',
* last modified on Thursday, 22.06.2023 06:51:53
* last modified on Wednesday, 20.09.2023 10:44:18
*/

6
nrfx/mdk/nrf52.h
View File

@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.
* @file nrf52.h
* @brief CMSIS HeaderFile
* @version 1
* @date 22. June 2023
* @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:14
* @date 20. September 2023
* @note Generated by SVDConv V3.3.35 on Wednesday, 20.09.2023 12:45:31
* from File 'nrf52.svd',
* last modified on Thursday, 22.06.2023 06:51:53
* last modified on Wednesday, 20.09.2023 10:44:18
*/

6
nrfx/mdk/nrf52805.h
View File

@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n
* @file nrf52805.h
* @brief CMSIS HeaderFile
* @version 1
* @date 22. June 2023
* @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:08
* @date 20. September 2023
* @note Generated by SVDConv V3.3.35 on Wednesday, 20.09.2023 12:45:28
* from File 'nrf52805.svd',
* last modified on Thursday, 22.06.2023 06:51:53
* last modified on Wednesday, 20.09.2023 10:44:18
*/

6
nrfx/mdk/nrf52810.h
View File

@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n
* @file nrf52810.h
* @brief CMSIS HeaderFile
* @version 1
* @date 22. June 2023
* @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:10
* @date 20. September 2023
* @note Generated by SVDConv V3.3.35 on Wednesday, 20.09.2023 12:45:28
* from File 'nrf52810.svd',
* last modified on Thursday, 22.06.2023 06:51:53
* last modified on Wednesday, 20.09.2023 10:44:18
*/

6
nrfx/mdk/nrf52811.h
View File

@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n
* @file nrf52811.h
* @brief CMSIS HeaderFile
* @version 1
* @date 04. April 2023
* @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:31
* @date 20. September 2023
* @note Generated by SVDConv V3.3.35 on Wednesday, 20.09.2023 12:45:29
* from File 'nrf52811.svd',
* last modified on Tuesday, 04.04.2023 09:57:14
* last modified on Wednesday, 20.09.2023 10:44:18
*/

6
nrfx/mdk/nrf52820.h
View File

@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n
* @file nrf52820.h
* @brief CMSIS HeaderFile
* @version 1
* @date 22. June 2023
* @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:12
* @date 20. September 2023
* @note Generated by SVDConv V3.3.35 on Wednesday, 20.09.2023 12:45:30
* from File 'nrf52820.svd',
* last modified on Thursday, 22.06.2023 06:51:53
* last modified on Wednesday, 20.09.2023 10:44:18
*/

6
nrfx/mdk/nrf52833.h
View File

@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n
* @file nrf52833.h
* @brief CMSIS HeaderFile
* @version 1
* @date 22. June 2023
* @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:16
* @date 20. September 2023
* @note Generated by SVDConv V3.3.35 on Wednesday, 20.09.2023 12:45:32
* from File 'nrf52833.svd',
* last modified on Thursday, 22.06.2023 06:51:53
* last modified on Wednesday, 20.09.2023 10:44:18
*/

6
nrfx/mdk/nrf52840.h
View File

@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n
* @file nrf52840.h
* @brief CMSIS HeaderFile
* @version 1
* @date 22. June 2023
* @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:18
* @date 20. September 2023
* @note Generated by SVDConv V3.3.35 on Wednesday, 20.09.2023 12:45:33
* from File 'nrf52840.svd',
* last modified on Thursday, 22.06.2023 06:51:54
* last modified on Wednesday, 20.09.2023 10:44:18
*/

30
nrfx/mdk/nrf52_erratas.h
View File

@ -10733,7 +10733,7 @@ static bool nrf52_errata_210(void)
#endif
#ifndef NRF52_ERRATA_211_ENABLE_WORKAROUND
#define NRF52_ERRATA_211_ENABLE_WORKAROUND 0
#define NRF52_ERRATA_211_ENABLE_WORKAROUND NRF52_ERRATA_211_PRESENT
#endif
static bool nrf52_errata_211(void)
@ -12108,7 +12108,6 @@ static bool nrf52_errata_233(void)
/* ========= Errata 236 ========= */
#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \
|| defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \
|| defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \
|| defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \
|| defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
#define NRF52_ERRATA_236_PRESENT 1
@ -12127,7 +12126,6 @@ static bool nrf52_errata_236(void)
#else
#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\
|| defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\
|| defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
|| defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
|| defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
uint32_t var1 = *(uint32_t *)0x10000130ul;
@ -12199,24 +12197,6 @@ static bool nrf52_errata_236(void)
}
}
#endif
#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)
if (var1 == 0x10)
{
switch(var2)
{
case 0x00ul:
return true;
case 0x01ul:
return true;
case 0x02ul:
return false;
case 0x03ul:
return false;
default:
return false;
}
}
#endif
return false;
#endif
}
@ -12437,9 +12417,9 @@ static bool nrf52_errata_241(void)
case 0x01ul:
return true;
case 0x02ul:
return false;
return true;
default:
return false;
return true;
}
}
#endif
@ -12465,9 +12445,9 @@ static bool nrf52_errata_241(void)
case 0x00ul:
return true;
case 0x01ul:
return false;
return true;
default:
return false;
return true;
}
}
#endif

6
nrfx/mdk/nrf5340_application.h
View File

@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.
* @file nrf5340_application.h
* @brief CMSIS HeaderFile
* @version 1
* @date 22. June 2023
* @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:20
* @date 20. September 2023
* @note Generated by SVDConv V3.3.35 on Wednesday, 20.09.2023 12:45:35
* from File 'nrf5340_application.svd',
* last modified on Thursday, 22.06.2023 06:51:54
* last modified on Wednesday, 20.09.2023 10:44:18
*/

6
nrfx/mdk/nrf5340_network.h
View File

@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.
* @file nrf5340_network.h
* @brief CMSIS HeaderFile
* @version 1
* @date 22. June 2023
* @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:31
* @date 20. September 2023
* @note Generated by SVDConv V3.3.35 on Wednesday, 20.09.2023 12:45:43
* from File 'nrf5340_network.svd',
* last modified on Thursday, 22.06.2023 06:51:54
* last modified on Wednesday, 20.09.2023 10:44:18
*/

248
nrfx/mdk/nrf53_erratas.h
View File

@ -142,10 +142,14 @@ static bool nrf53_errata_140(void) __UNUSED;
static bool nrf53_errata_152(void) __UNUSED;
static bool nrf53_errata_153(void) __UNUSED;
static bool nrf53_errata_154(void) __UNUSED;
static bool nrf53_errata_155(void) __UNUSED;
static bool nrf53_errata_157(void) __UNUSED;
static bool nrf53_errata_158(void) __UNUSED;
static bool nrf53_errata_160(void) __UNUSED;
static bool nrf53_errata_161(void) __UNUSED;
static bool nrf53_errata_162(void) __UNUSED;
static bool nrf53_errata_163(void) __UNUSED;
static bool nrf53_errata_165(void) __UNUSED;
/* ========= Errata 1 ========= */
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
@ -5749,10 +5753,59 @@ static bool nrf53_errata_154(void)
#endif
}
/* ========= Errata 155 ========= */
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
#if defined(NRF_NETWORK)
#define NRF53_ERRATA_155_PRESENT 1
#else
#define NRF53_ERRATA_155_PRESENT 0
#endif
#else
#define NRF53_ERRATA_155_PRESENT 0
#endif
#ifndef NRF53_ERRATA_155_ENABLE_WORKAROUND
#define NRF53_ERRATA_155_ENABLE_WORKAROUND NRF53_ERRATA_155_PRESENT
#endif
static bool nrf53_errata_155(void)
{
#ifndef NRF53_SERIES
return false;
#else
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
#if defined(NRF_NETWORK)
uint32_t var1 = *(uint32_t *)0x01FF0130ul;
uint32_t var2 = *(uint32_t *)0x01FF0134ul;
#endif
#endif
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
#if defined (NRF_NETWORK)
if (var1 == 0x07)
{
switch(var2)
{
case 0x02ul:
return false;
case 0x03ul:
return false;
case 0x04ul:
return false;
case 0x05ul:
return true;
default:
return true;
}
}
#endif
#endif
return false;
#endif
}
/* ========= Errata 157 ========= */
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
#if defined(NRF_APPLICATION) || \
defined(NRF_NETWORK)
#if defined(NRF_NETWORK)
#define NRF53_ERRATA_157_PRESENT 1
#else
#define NRF53_ERRATA_157_PRESENT 0
@ -5771,22 +5824,13 @@ static bool nrf53_errata_157(void)
return false;
#else
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
#if defined(NRF_APPLICATION)
#if defined(NRF_TRUSTZONE_NONSECURE)
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
#else
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
#endif
#elif defined(NRF_NETWORK)
#if defined(NRF_NETWORK)
uint32_t var1 = *(uint32_t *)0x01FF0130ul;
uint32_t var2 = *(uint32_t *)0x01FF0134ul;
#endif
#endif
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
#if defined (NRF_APPLICATION)\
|| defined (NRF_NETWORK)
#if defined (NRF_NETWORK)
if (var1 == 0x07)
{
switch(var2)
@ -5921,7 +5965,8 @@ static bool nrf53_errata_160(void)
/* ========= Errata 161 ========= */
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
#if defined(NRF_NETWORK)
#if defined(NRF_APPLICATION) || \
defined(NRF_NETWORK)
#define NRF53_ERRATA_161_PRESENT 1
#else
#define NRF53_ERRATA_161_PRESENT 0
@ -5978,4 +6023,179 @@ static bool nrf53_errata_161(void)
#endif
}
/* ========= Errata 162 ========= */
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
#if defined(NRF_APPLICATION) || \
defined(NRF_NETWORK)
#define NRF53_ERRATA_162_PRESENT 1
#else
#define NRF53_ERRATA_162_PRESENT 0
#endif
#else
#define NRF53_ERRATA_162_PRESENT 0
#endif
#ifndef NRF53_ERRATA_162_ENABLE_WORKAROUND
#define NRF53_ERRATA_162_ENABLE_WORKAROUND NRF53_ERRATA_162_PRESENT
#endif
static bool nrf53_errata_162(void)
{
#ifndef NRF53_SERIES
return false;
#else
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
#if defined(NRF_APPLICATION)
#if defined(NRF_TRUSTZONE_NONSECURE)
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
#else
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
#endif
#elif defined(NRF_NETWORK)
uint32_t var1 = *(uint32_t *)0x01FF0130ul;
uint32_t var2 = *(uint32_t *)0x01FF0134ul;
#endif
#endif
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
#if defined (NRF_APPLICATION)\
|| defined (NRF_NETWORK)
if (var1 == 0x07)
{
switch(var2)
{
case 0x02ul:
return false;
case 0x03ul:
return false;
case 0x04ul:
return false;
case 0x05ul:
return true;
default:
return true;
}
}
#endif
#endif
return false;
#endif
}
/* ========= Errata 163 ========= */
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
#if defined(NRF_APPLICATION)
#define NRF53_ERRATA_163_PRESENT 1
#else
#define NRF53_ERRATA_163_PRESENT 0
#endif
#else
#define NRF53_ERRATA_163_PRESENT 0
#endif
#ifndef NRF53_ERRATA_163_ENABLE_WORKAROUND
#define NRF53_ERRATA_163_ENABLE_WORKAROUND NRF53_ERRATA_163_PRESENT
#endif
static bool nrf53_errata_163(void)
{
#ifndef NRF53_SERIES
return false;
#else
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
#if defined(NRF_APPLICATION)
#if defined(NRF_TRUSTZONE_NONSECURE)
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
#else
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
#endif
#endif
#endif
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
#if defined (NRF_APPLICATION)
if (var1 == 0x07)
{
switch(var2)
{
case 0x02ul:
return false;
case 0x03ul:
return false;
case 0x04ul:
return false;
case 0x05ul:
return true;
default:
return true;
}
}
#endif
#endif
return false;
#endif
}
/* ========= Errata 165 ========= */
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
#if defined(NRF_APPLICATION) || \
defined(NRF_NETWORK)
#define NRF53_ERRATA_165_PRESENT 1
#else
#define NRF53_ERRATA_165_PRESENT 0
#endif
#else
#define NRF53_ERRATA_165_PRESENT 0
#endif
#ifndef NRF53_ERRATA_165_ENABLE_WORKAROUND
#define NRF53_ERRATA_165_ENABLE_WORKAROUND NRF53_ERRATA_165_PRESENT
#endif
static bool nrf53_errata_165(void)
{
#ifndef NRF53_SERIES
return false;
#else
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
#if defined(NRF_APPLICATION)
#if defined(NRF_TRUSTZONE_NONSECURE)
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
#else
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
#endif
#elif defined(NRF_NETWORK)
uint32_t var1 = *(uint32_t *)0x01FF0130ul;
uint32_t var2 = *(uint32_t *)0x01FF0134ul;
#endif
#endif
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
#if defined (NRF_APPLICATION)\
|| defined (NRF_NETWORK)
if (var1 == 0x07)
{
switch(var2)
{
case 0x02ul:
return false;
case 0x03ul:
return false;
case 0x04ul:
return false;
case 0x05ul:
return true;
default:
return true;
}
}
#endif
#endif
return false;
#endif
}
#endif /* NRF53_ERRATAS_H */

6
nrfx/mdk/nrf9120.h
View File

@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.
* @file nrf9120.h
* @brief CMSIS HeaderFile
* @version 1
* @date 22. June 2023
* @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:33
* @date 20. September 2023
* @note Generated by SVDConv V3.3.35 on Wednesday, 20.09.2023 12:45:44
* from File 'nrf9120.svd',
* last modified on Thursday, 22.06.2023 06:51:54
* last modified on Wednesday, 20.09.2023 10:44:18
*/

6
nrfx/mdk/nrf9160.h
View File

@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.
* @file nrf9160.h
* @brief CMSIS HeaderFile
* @version 1
* @date 22. June 2023
* @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:38
* @date 20. September 2023
* @note Generated by SVDConv V3.3.35 on Wednesday, 20.09.2023 12:45:48
* from File 'nrf9160.svd',
* last modified on Thursday, 22.06.2023 06:51:54
* last modified on Wednesday, 20.09.2023 10:44:18
*/

12
nrfx/mdk/system_nrf51.c
View File

@ -59,8 +59,8 @@ void SystemInit(void)
example) will not be available. */
if (nrf51_errata_26())
{
*(uint32_t volatile *)0x40000504 = 0xC007FFDF;
*(uint32_t volatile *)0x40006C18 = 0x00008000;
*(uint32_t volatile *)0x40000504ul = 0xC007FFDFul;
*(uint32_t volatile *)0x40006C18ul = 0x00008000ul;
}
/* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG
@ -75,12 +75,12 @@ void SystemInit(void)
as indicated by PAN 76 "System: Excessive current in sleep mode with retention" found at Product Anomaly document
for your device found at https://infocenter.nordicsemi.com/index.jsp */
if (nrf51_errata_76()){
if (*(uint32_t volatile *)0x4006EC00 != 1){
*(uint32_t volatile *)0x4006EC00 = 0x9375;
while (*(uint32_t volatile *)0x4006EC00 != 1){
if (*(uint32_t volatile *)0x4006EC00ul != 1ul){
*(uint32_t volatile *)0x4006EC00ul = 0x9375ul;
while (*(uint32_t volatile *)0x4006EC00ul != 1ul){
}
}
*(uint32_t volatile *)0x4006EC14 = 0xC0;
*(uint32_t volatile *)0x4006EC14ul = 0xC0ul;
}
}

50
nrfx/mdk/system_nrf52.c
View File

@ -42,33 +42,33 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
/* Simplify later device detection macros. Check DEVELOP_IN first, as they take precedence. */
#if defined (DEVELOP_IN_NRF52805)
#define IS_NRF52805 1
#define IS_NRF52805 1ul
#elif defined (DEVELOP_IN_NRF52810)
#define IS_NRF52810 1
#define IS_NRF52810 1ul
#elif defined (DEVELOP_IN_NRF52811)
#define IS_NRF52811 1
#define IS_NRF52811 1ul
#elif defined (DEVELOP_IN_NRF52820)
#define IS_NRF52820 1
#define IS_NRF52820 1ul
#elif defined (DEVELOP_IN_NRF52832)
#define IS_NRF52832 1
#elif defined (DEVELOP_IN_NRF52833)
#define IS_NRF52833 1
#elif defined (DEVELOP_IN_NRF52840)
#define IS_NRF52840 1
#define IS_NRF52840 1ul
#elif defined (NRF52805_XXAA)
#define IS_NRF52805 1
#define IS_NRF52805 1ul
#elif defined (NRF52810_XXAA)
#define IS_NRF52810 1
#define IS_NRF52810 1ul
#elif defined (NRF52811_XXAA)
#define IS_NRF52811 1
#define IS_NRF52811 1ul
#elif defined (NRF52820_XXAA)
#define IS_NRF52820 1
#define IS_NRF52820 1ul
#elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB)
#define IS_NRF52832 1
#define IS_NRF52832 1ul
#elif defined (NRF52833_XXAA)
#define IS_NRF52833 1
#define IS_NRF52833 1ul
#elif defined (NRF52840_XXAA)
#define IS_NRF52840 1
#define IS_NRF52840 1ul
#else
#error "A supported device macro must be defined."
#endif
@ -97,9 +97,9 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
/* Select correct reset pin */
/* Handle DEVELOP_IN-targets first as they take precedence over the later macros */
#if IS_NRF52805 || IS_NRF52810 || IS_NRF52811 || IS_NRF52832
#define RESET_PIN 21
#define RESET_PIN 21ul
#elif IS_NRF52820 || IS_NRF52833 || IS_NRF52840
#define RESET_PIN 18
#define RESET_PIN 18ul
#else
#error "A supported device macro must be defined."
#endif
@ -182,9 +182,9 @@ void SystemInit(void)
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_36()){
NRF_CLOCK->EVENTS_DONE = 0;
NRF_CLOCK->EVENTS_CTTO = 0;
NRF_CLOCK->CTIV = 0;
NRF_CLOCK->EVENTS_DONE = 0ul;
NRF_CLOCK->EVENTS_CTTO = 0ul;
NRF_CLOCK->CTIV = 0ul;
}
#endif
@ -259,7 +259,7 @@ void SystemInit(void)
/* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_115()){
*(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
*(volatile uint32_t *)0x40000EE4ul = (*(volatile uint32_t *)0x40000EE4ul & 0xFFFFFFF0ul) | (*(uint32_t *)0x10000258ul & 0x0000000Ful);
}
#endif
@ -285,7 +285,7 @@ void SystemInit(void)
/* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_182()){
*(volatile uint32_t *) 0x4000173C |= (0x1 << 10);
*(volatile uint32_t *) 0x4000173Cul |= (0x1ul << 10ul);
}
#endif
@ -301,7 +301,7 @@ void SystemInit(void)
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
#if (__FPU_USED == 1)
SCB->CPACR |= (3UL << 20) | (3UL << 22);
SCB->CPACR |= (3UL << 20ul) | (3UL << 22ul);
__DSB();
__ISB();
#endif
@ -309,12 +309,12 @@ void SystemInit(void)
nrf52_handle_approtect();
#if NRF52_CONFIGURATION_249_ENABLE && (defined(NRF52805_XXAA) || defined(NRF52810_XXAA) || defined(NRF52811_XXAA))
if (nrf52_configuration_249() && (NRF_UICR->NRFMDK[0] == 0xFFFFFFFF || NRF_UICR->NRFMDK[1] == 0xFFFFFFFF))
if (nrf52_configuration_249() && (NRF_UICR->NRFMDK[0] == 0xFFFFFFFFul || NRF_UICR->NRFMDK[1] == 0xFFFFFFFFul))
{
nvmc_config(NVMC_CONFIG_WEN_Wen);
NRF_UICR->NRFMDK[0] = 0;
NRF_UICR->NRFMDK[0] = 0ul;
nvmc_wait();
NRF_UICR->NRFMDK[1] = 0;
NRF_UICR->NRFMDK[1] = 0ul;
nvmc_wait();
nvmc_config(NVMC_CONFIG_WEN_Ren);
}
@ -353,9 +353,9 @@ void SystemInit(void)
make sure NFC pins are mapped as GPIO. */
#if defined (DEVELOP_IN_NRF52832) && defined(NRF52810_XXAA) \
|| defined (DEVELOP_IN_NRF52840) && defined(NRF52811_XXAA)
if ((*((uint32_t *)0x1000120C) & (1 << 0)) != 0){
if ((*((uint32_t *)0x1000120Cul) & (1ul << 0ul)) != 0ul){
nvmc_config(NVMC_CONFIG_WEN_Wen);
*((uint32_t *)0x1000120C) = 0;
*((uint32_t *)0x1000120Cul) = 0ul;
nvmc_wait();
nvmc_config(NVMC_CONFIG_WEN_Ren);
NVIC_SystemReset();

68
nrfx/mdk/system_nrf5340_application.c
View File

@ -75,14 +75,14 @@ void SystemInit(void)
/* Set all ARM SAU regions to NonSecure if TrustZone extensions are enabled.
* Nordic SPU should handle Secure Attribution tasks */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
SAU->CTRL |= (1ul << SAU_CTRL_ALLNS_Pos);
#endif
/* Workaround for Errata 97 "ERASEPROTECT, APPROTECT, or startup problems" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf53_errata_97())
{
if (*((volatile uint32_t *)0x50004A20ul) == 0)
if (*((volatile uint32_t *)0x50004A20ul) == 0ul)
{
*((volatile uint32_t *)0x50004A20ul) = 0xDul;
*((volatile uint32_t *)0x5000491Cul) = 0x1ul;
@ -92,8 +92,8 @@ void SystemInit(void)
/* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim
until one ADDR is not initialized. */
uint32_t index = 0;
for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){
uint32_t index = 0ul;
for (index = 0ul; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){
#if defined ( __ICCARM__ )
/* IAR will complain about the order of volatile pointer accesses. */
#pragma diag_suppress=Pa082
@ -125,7 +125,7 @@ void SystemInit(void)
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf53_errata_46())
{
*((volatile uint32_t *)0x5003254Cul) = 0;
*((volatile uint32_t *)0x5003254Cul) = 0ul;
}
/* Workaround for Errata 49 "SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document
@ -134,8 +134,8 @@ void SystemInit(void)
{
if (NRF_RESET_S->RESETREAS & RESET_RESETREAS_RESETPIN_Msk)
{
NRF_POWER_S->EVENTS_SLEEPENTER = 0;
NRF_POWER_S->EVENTS_SLEEPEXIT = 0;
NRF_POWER_S->EVENTS_SLEEPENTER = 0ul;
NRF_POWER_S->EVENTS_SLEEPEXIT = 0ul;
}
}
@ -157,29 +157,29 @@ void SystemInit(void)
if (nrf53_errata_140())
{
if (*(volatile uint32_t *)0x50032420 & 0x80000000)
if (*(volatile uint32_t *)0x50032420ul & 0x80000000ul)
{
/* Reset occured during calibration */
NRF_CLOCK_S->LFCLKSRC = CLOCK_LFCLKSRC_SRC_LFSYNT;
NRF_CLOCK_S->TASKS_LFCLKSTART = 1;
while (NRF_CLOCK_S->EVENTS_LFCLKSTARTED == 0) {}
NRF_CLOCK_S->EVENTS_LFCLKSTARTED = 0;
NRF_CLOCK_S->TASKS_LFCLKSTOP = 1;
NRF_CLOCK_S->TASKS_LFCLKSTART = 1ul;
while (NRF_CLOCK_S->EVENTS_LFCLKSTARTED == 0ul) {}
NRF_CLOCK_S->EVENTS_LFCLKSTARTED = 0ul;
NRF_CLOCK_S->TASKS_LFCLKSTOP = 1ul;
NRF_CLOCK_S->LFCLKSRC = CLOCK_LFCLKSRC_SRC_LFRC;
}
}
if (nrf53_errata_160())
{
*((volatile uint32_t *)0x5000470C) = 0x7Eul;
*((volatile uint32_t *)0x5000493C) = 0x7Eul;
*((volatile uint32_t *)0x50002118) = 0x7Ful;
*((volatile uint32_t *)0x50039E04) = 0x0ul;
*((volatile uint32_t *)0x50039E08) = 0x0ul;
*((volatile uint32_t *)0x50101110) = 0x0ul;
*((volatile uint32_t *)0x50002124) = 0x0ul;
*((volatile uint32_t *)0x5000212C) = 0x0ul;
*((volatile uint32_t *)0x502012A0) = 0x0ul;
*((volatile uint32_t *)0x5000470Cul) = 0x7Eul;
*((volatile uint32_t *)0x5000493Cul) = 0x7Eul;
*((volatile uint32_t *)0x50002118ul) = 0x7Ful;
*((volatile uint32_t *)0x50039E04ul) = 0x0ul;
*((volatile uint32_t *)0x50039E08ul) = 0x0ul;
*((volatile uint32_t *)0x50101110ul) = 0x0ul;
*((volatile uint32_t *)0x50002124ul) = 0x0ul;
*((volatile uint32_t *)0x5000212Cul) = 0x0ul;
*((volatile uint32_t *)0x502012A0ul) = 0x0ul;
}
#if !defined(NRF_SKIP_FICR_NS_COPY_TO_RAM)
@ -212,7 +212,7 @@ void SystemInit(void)
NRF_TAD_S->CLOCKSTART = TAD_CLOCKSTART_START_Msk;
// Set up Trace pad SPU firewall
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA0_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1ul << TRACE_TRACEDATA0_PIN);
// Configure trace port pad
NRF_P0_S->PIN_CNF[TRACE_TRACEDATA0_PIN] = TRACE_PIN_CNF_VALUE;
@ -232,11 +232,11 @@ void SystemInit(void)
NRF_TAD_S->CLOCKSTART = TAD_CLOCKSTART_START_Msk;
// Set up Trace pads SPU firewall
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACECLK_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA0_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA1_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA2_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA3_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1ul << TRACE_TRACECLK_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1ul << TRACE_TRACEDATA0_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1ul << TRACE_TRACEDATA1_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1ul << TRACE_TRACEDATA2_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1ul << TRACE_TRACEDATA3_PIN);
// Configure trace port pads
NRF_P0_S->PIN_CNF[TRACE_TRACECLK_PIN] = TRACE_PIN_CNF_VALUE;
@ -259,7 +259,7 @@ void SystemInit(void)
/* Allow Non-Secure code to run FPU instructions.
* If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */
SCB->NSACR |= (3UL << 10);
SCB->NSACR |= (3UL << 10ul);
/* Handle fw-branch APPROTECT setup. */
nrf53_handle_approtect();
@ -269,8 +269,8 @@ void SystemInit(void)
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
#if (__FPU_USED == 1)
SCB->CPACR |= (3UL << 20) | (3UL << 22);
#if (__FPU_USED == 1ul)
SCB->CPACR |= (3UL << 20ul) | (3UL << 22ul);
__DSB();
__ISB();
#endif
@ -300,7 +300,7 @@ void SystemStoreFICRNS()
/* Make RAM region NS. */
uint32_t ram_region = ((uint32_t)NRF_FICR_NS - (uint32_t)RAM_BASE) / SPU_RAMREGION_SIZE;
NRF_SPU_S->RAMREGION[ram_region].PERM &= ~(1 << SPU_RAMREGION_PERM_SECATTR_Pos);
NRF_SPU_S->RAMREGION[ram_region].PERM &= ~(1ul << SPU_RAMREGION_PERM_SECATTR_Pos);
}
/* Block write and execute access to FICR RAM region */
@ -315,10 +315,10 @@ void SystemLockFICRNS()
uint32_t ram_region = ((uint32_t)NRF_FICR_NS - (uint32_t)RAM_BASE) / SPU_RAMREGION_SIZE;
NRF_SPU_S->RAMREGION[ram_region].PERM &=
~(
(1 << SPU_RAMREGION_PERM_WRITE_Pos) |
(1 << SPU_RAMREGION_PERM_EXECUTE_Pos)
(1ul << SPU_RAMREGION_PERM_WRITE_Pos) |
(1ul << SPU_RAMREGION_PERM_EXECUTE_Pos)
);
NRF_SPU_S->RAMREGION[ram_region].PERM |= 1 << SPU_RAMREGION_PERM_LOCK_Pos;
NRF_SPU_S->RAMREGION[ram_region].PERM |= 1ul << SPU_RAMREGION_PERM_LOCK_Pos;
}
/*lint --flb "Leave library region" */

16
nrfx/mdk/system_nrf5340_network.c
View File

@ -68,8 +68,8 @@ void SystemInit(void)
{
if (NRF_RESET_NS->RESETREAS & RESET_RESETREAS_RESETPIN_Msk)
{
NRF_POWER_NS->EVENTS_SLEEPENTER = 0;
NRF_POWER_NS->EVENTS_SLEEPEXIT = 0;
NRF_POWER_NS->EVENTS_SLEEPENTER = 0ul;
NRF_POWER_NS->EVENTS_SLEEPEXIT = 0ul;
}
}
@ -84,12 +84,12 @@ void SystemInit(void)
if (nrf53_errata_160())
{
*((volatile uint32_t *)0x41002118) = 0x7Ful;
*((volatile uint32_t *)0x41080E04) = 0x0ul;
*((volatile uint32_t *)0x41080E08) = 0x0ul;
*((volatile uint32_t *)0x41002124) = 0x0ul;
*((volatile uint32_t *)0x4100212C) = 0x0ul;
*((volatile uint32_t *)0x41101110) = 0x0ul;
*((volatile uint32_t *)0x41002118ul) = 0x7Ful;
*((volatile uint32_t *)0x41080E04ul) = 0x0ul;
*((volatile uint32_t *)0x41080E08ul) = 0x0ul;
*((volatile uint32_t *)0x41002124ul) = 0x0ul;
*((volatile uint32_t *)0x4100212Cul) = 0x0ul;
*((volatile uint32_t *)0x41101110ul) = 0x0ul;
}
/* Handle fw-branch APPROTECT setup. */

75
nrfx/mdk/system_nrf91.c
View File

@ -42,11 +42,11 @@ void SystemStoreFICRNS();
(GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) | \
(GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | \
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) )
#define TRACE_TRACECLK_PIN (21)
#define TRACE_TRACEDATA0_PIN (22)
#define TRACE_TRACEDATA1_PIN (23)
#define TRACE_TRACEDATA2_PIN (24)
#define TRACE_TRACEDATA3_PIN (25)
#define TRACE_TRACECLK_PIN (21ul)
#define TRACE_TRACEDATA0_PIN (22ul)
#define TRACE_TRACEDATA1_PIN (23ul)
#define TRACE_TRACEDATA2_PIN (24ul)
#define TRACE_TRACEDATA3_PIN (25ul)
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_DEFAULT;
@ -78,7 +78,7 @@ void SystemInit(void)
/* Set all ARM SAU regions to NonSecure if TrustZone extensions are enabled.
* Nordic SPU should handle Secure Attribution tasks */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
SAU->CTRL |= (1ul << SAU_CTRL_ALLNS_Pos);
#endif
/* Workaround for Errata 6 "POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document
@ -91,7 +91,7 @@ void SystemInit(void)
/* Workaround for Errata 14 "REGULATORS: LDO mode at startup" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf91_errata_14()){
*((volatile uint32_t *)0x50004A38) = 0x01ul;
*((volatile uint32_t *)0x50004A38ul) = 0x01ul;
NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
}
@ -104,14 +104,14 @@ void SystemInit(void)
/* Workaround for Errata 20 "RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf91_errata_20()){
*((volatile uint32_t *)0x5003AEE4) = 0xE;
*((volatile uint32_t *)0x5003AEE4ul) = 0xEul;
}
/* Workaround for Errata 31 "XOSC32k Startup Failure" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf91_errata_31()){
*((volatile uint32_t *)0x5000470Cul) = 0x0;
*((volatile uint32_t *)0x50004710ul) = 0x1;
*((volatile uint32_t *)0x5000470Cul) = 0x0ul;
*((volatile uint32_t *)0x50004710ul) = 0x1ul;
}
#if !defined(NRF_SKIP_FICR_NS_COPY_TO_RAM)
@ -121,7 +121,7 @@ void SystemInit(void)
/* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim
until one ADDR is not initialized. */
for (uint32_t index = 0; index < 256ul && !is_empty_word(&NRF_FICR_S->TRIMCNF[index].ADDR); index++){
for (uint32_t index = 0ul; index < 256ul && !is_empty_word(&NRF_FICR_S->TRIMCNF[index].ADDR); index++){
#if defined ( __ICCARM__ )
#pragma diag_suppress=Pa082
#endif
@ -132,6 +132,7 @@ void SystemInit(void)
}
#if !defined(NRF_SKIP_UICR_HFXO_WORKAROUND)
bool irq_disabled = __get_PRIMASK() == 1;
uint32_t uicr_erased_value;
uint32_t uicr_new_value;
/* Set UICR->HFXOSRC and UICR->HFXOCNT to working defaults if UICR was erased */
@ -144,6 +145,10 @@ void SystemInit(void)
NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen;
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
if (!irq_disabled && nrf91_errata_7()){
__disable_irq();
}
if (uicr_HFXOSRC_erased()){
/* Write default value to UICR->HFXOSRC */
uicr_erased_value = NRF_UICR_S->HFXOSRC;
@ -161,6 +166,10 @@ void SystemInit(void)
__DSB();
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
}
if(!irq_disabled && nrf91_errata_7()){
__enable_irq();
}
/* Enable read mode in NVMC */
NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren;
@ -179,11 +188,11 @@ void SystemInit(void)
NRF_TAD_S->TASKS_CLOCKSTART = TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Msk;
// Set up Trace pads SPU firewall
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACECLK_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA0_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA1_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA2_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA3_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1ul << TRACE_TRACECLK_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1ul << TRACE_TRACEDATA0_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1ul << TRACE_TRACEDATA1_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1ul << TRACE_TRACEDATA2_PIN);
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1ul << TRACE_TRACEDATA3_PIN);
// Configure trace port pads
NRF_P0_S->PIN_CNF[TRACE_TRACECLK_PIN] = TRACE_PIN_CNF_VALUE;
@ -230,7 +239,7 @@ void SystemInit(void)
/* Allow Non-Secure code to run FPU instructions.
* If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */
SCB->NSACR |= (3UL << 10);
SCB->NSACR |= (3UL << 10ul);
nrf91_handle_approtect();
#endif
@ -239,7 +248,7 @@ void SystemInit(void)
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
#if (__FPU_USED == 1)
SCB->CPACR |= (3UL << 20) | (3UL << 22);
SCB->CPACR |= (3UL << 20ul) | (3UL << 22ul);
__DSB();
__ISB();
#endif
@ -251,21 +260,31 @@ void SystemInit(void)
#if !defined(NRF_SKIP_UICR_HFXO_WORKAROUND)
bool uicr_HFXOCNT_erased()
{
if (is_empty_word(&NRF_UICR_S->HFXOCNT)) {
return true;
bool irq_disabled = __get_PRIMASK() == 1;
if (!irq_disabled && nrf91_errata_7()){
__disable_irq();
}
return false;
bool is_empty = is_empty_word(&NRF_UICR_S->HFXOCNT);
if (!irq_disabled && nrf91_errata_7()){
__enable_irq();
}
return is_empty;
}
bool uicr_HFXOSRC_erased()
{
bool irq_disabled = __get_PRIMASK() == 1;
if (!irq_disabled && nrf91_errata_7()){
__disable_irq();
}
uint32_t HFXOSRC_readout = NRF_UICR_S->HFXOSRC;
__DSB();
if ((HFXOSRC_readout & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) {
return true;
bool erased = (HFXOSRC_readout & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO;
if (!irq_disabled && nrf91_errata_7()){
__enable_irq();
}
return false;
return erased;
}
#endif
@ -303,7 +322,7 @@ void SystemStoreFICRNS()
/* Make RAM region NS. */
uint32_t ram_region = ((uint32_t)NRF_FICR_NS - (uint32_t)RAM_BASE) / SPU_RAMREGION_SIZE;
__DSB();
NRF_SPU_S->RAMREGION[ram_region].PERM &= ~(1 << SPU_RAMREGION_PERM_SECATTR_Pos);
NRF_SPU_S->RAMREGION[ram_region].PERM &= ~(1ul << SPU_RAMREGION_PERM_SECATTR_Pos);
}
/* Block write and execute access to FICR RAM region */
@ -319,10 +338,10 @@ void SystemLockFICRNS()
__DSB();
NRF_SPU_S->RAMREGION[ram_region].PERM &=
~(
(1 << SPU_RAMREGION_PERM_WRITE_Pos) |
(1 << SPU_RAMREGION_PERM_EXECUTE_Pos)
(1ul << SPU_RAMREGION_PERM_WRITE_Pos) |
(1ul << SPU_RAMREGION_PERM_EXECUTE_Pos)
);
NRF_SPU_S->RAMREGION[ram_region].PERM |= 1 << SPU_RAMREGION_PERM_LOCK_Pos;
NRF_SPU_S->RAMREGION[ram_region].PERM |= 1ul << SPU_RAMREGION_PERM_LOCK_Pos;
}
/*lint --flb "Leave library region" */