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mdk: nrf54l15: Fix UARTE MAXCNT value 

MDK has a bug and indicates that UARTE DMA transfer length is
limited to 8 bits when it should be 16.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
This commit is contained in:
Krzysztof Chruściński 2024-04-04 08:27:02 +02:00 committed by Nikodem Kastelik
parent 04f0829708
commit 729169433a
4 changed files with 40 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
nrfx/mdk/nrf54l15_application_peripherals.h
View File

@ -507,8 +507,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_COUNT 5
#define UARTE00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE00_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE00_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE00_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE00_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE00_CORE_FREQUENCY 128 /*!< Peripheral clock frequency is 128 MHz. */
@ -517,8 +517,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE20_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE20_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */
@ -527,8 +527,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE21_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE21_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */
@ -537,8 +537,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE22_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE22_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */
@ -547,8 +547,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE30_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE30_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */

20
nrfx/mdk/nrf54l15_enga_application_peripherals.h
View File

@ -507,8 +507,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_COUNT 5
#define UARTE00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE00_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE00_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE00_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE00_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE00_CORE_FREQUENCY 128 /*!< Peripheral clock frequency is 128 MHz. */
@ -517,8 +517,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE20_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE20_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */
@ -527,8 +527,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE21_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE21_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */
@ -537,8 +537,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE22_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE22_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */
@ -547,8 +547,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE30_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE30_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */

20
nrfx/mdk/nrf54l15_enga_flpr_peripherals.h
View File

@ -485,8 +485,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_COUNT 5
#define UARTE00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE00_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE00_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE00_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE00_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE00_CORE_FREQUENCY 128 /*!< Peripheral clock frequency is 128 MHz. */
@ -495,8 +495,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE20_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE20_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */
@ -505,8 +505,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE21_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE21_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */
@ -515,8 +515,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE22_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE22_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */
@ -525,8 +525,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE30_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE30_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */

20
nrfx/mdk/nrf54l15_flpr_peripherals.h
View File

@ -485,8 +485,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_COUNT 5
#define UARTE00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE00_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE00_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE00_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE00_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE00_CORE_FREQUENCY 128 /*!< Peripheral clock frequency is 128 MHz. */
@ -495,8 +495,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE20_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE20_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */
@ -505,8 +505,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE21_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE21_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */
@ -515,8 +515,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE22_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE22_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */
@ -525,8 +525,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */
#define UARTE30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */
#define UARTE30_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */
#define UARTE30_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */
#define UARTE30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */